diff --git a/bsp/essemi/es32f0334/.config b/bsp/essemi/es32f0334/.config index b61c317c6ac73c8f8a408f57748e9c7d6d375df9..aaa2042085e04deadb25af99a536632383c8851d 100644 --- a/bsp/essemi/es32f0334/.config +++ b/bsp/essemi/es32f0334/.config @@ -64,7 +64,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40002 +CONFIG_RT_VER_NUM=0x40003 # CONFIG_RT_USING_CPU_FFS is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set @@ -115,18 +115,29 @@ CONFIG_RT_USING_SERIAL=y # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set +CONFIG_RT_USING_HWTIMER=y # CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_PWM is not set +CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_PWM=y # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_RTC is not set +CONFIG_RT_USING_PM=y +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -192,11 +203,15 @@ CONFIG_RT_USING_PIN=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -223,6 +238,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -235,8 +251,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set @@ -251,6 +269,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set # CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set # # security packages @@ -258,6 +285,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -274,6 +303,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -289,6 +319,12 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set # CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -299,6 +335,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -307,6 +344,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -323,6 +369,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set @@ -336,9 +386,27 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set # CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_LCD_DRIVERS is not set # CONFIG_PKG_USING_MAX17048 is not set # CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -373,8 +441,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set # # Hardware Drivers Config @@ -442,4 +516,18 @@ CONFIG_BSP_USING_UART1=y # # Offboard Peripheral Drivers # + +# +# Peripheral Drivers test example +# +# CONFIG_BSP_USING_EXAMPLE_ADC_VOL is not set +# CONFIG_BSP_USING_EXAMPLE_HWTIMER is not set +# CONFIG_BSP_USING_EXAMPLE_I2C is not set +# CONFIG_BSP_USING_EXAMPLE_LED_BLINK is not set +# CONFIG_BSP_USING_EXAMPLE_PIN_BEEP is not set +# CONFIG_BSP_USING_EXAMPLE_PWM_LED is not set +# CONFIG_BSP_USING_EXAMPLE_RTC is not set +# CONFIG_BSP_USING_EXAMPLE_SPI is not set +# CONFIG_BSP_USING_EXAMPLE_UART is not set +# CONFIG_BSP_USING_EXAMPLE_PM is not set CONFIG_SOC_ES32F0334LT=y diff --git a/bsp/essemi/es32f0334/README.md b/bsp/essemi/es32f0334/README.md index 13dd90018f17ae51b861d363add8d1e4e7c64a99..ac98561868e5007abea4cde1b8908d7001f62cc0 100644 --- a/bsp/essemi/es32f0334/README.md +++ b/bsp/essemi/es32f0334/README.md @@ -86,6 +86,22 @@ msh > 2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + a）如果需要使用内核用例，先配置rt-thread内核，如图： + + ![kernel_config](figures/k_conf.jpg) + + 然后配置内核用例，如图： + + ![kernel_samples](figures/k_ex.jpg) + + b）如果需要使用驱动用例：先使能驱动，如图： + + ![driver_config](figures/drv_conf.jpg) + + 然后配置驱动用例，如图： + + ![driver_sample](figures/drv_ex.jpg) + 3. 输入`pkgs --update`命令更新软件包。 4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 @@ -94,7 +110,7 @@ msh > ## 4. 联系人信息 -- [wangyongquan](https://github.com/wangyq2018) +- [liuhongyan](https://gitee.com/liuhongyan98) ## 5. 参考 diff --git a/bsp/essemi/es32f0334/drivers/Kconfig b/bsp/essemi/es32f0334/drivers/Kconfig index ac57b2da19ae85d9c805125fff84c0e6ec9e4496..05c29ef31336f18d9991c2b6d33563b3528bef05 100644 --- a/bsp/essemi/es32f0334/drivers/Kconfig +++ b/bsp/essemi/es32f0334/drivers/Kconfig @@ -127,4 +127,50 @@ menu "Hardware Drivers Config" endmenu + + menu "Peripheral Drivers test example" + + config BSP_USING_EXAMPLE_ADC_VOL + bool "BSP_USING_EXAMPLE_ADC_VOL" + default n + + config BSP_USING_EXAMPLE_HWTIMER + bool "BSP_USING_EXAMPLE_HWTIMER" + default n + + config BSP_USING_EXAMPLE_I2C + bool "BSP_USING_EXAMPLE_I2C" + default n + + config BSP_USING_EXAMPLE_LED_BLINK + bool "BSP_USING_EXAMPLE_LED_BLINK" + default y + + config BSP_USING_EXAMPLE_PIN_BEEP + bool "BSP_USING_EXAMPLE_PIN_BEEP" + default y + + config BSP_USING_EXAMPLE_PWM_LED + bool "BSP_USING_EXAMPLE_PWM_LED" + default n + + config BSP_USING_EXAMPLE_RTC + bool "BSP_USING_EXAMPLE_RTC" + default n + + config BSP_USING_EXAMPLE_SPI + bool "BSP_USING_EXAMPLE_SPI" + default n + + config BSP_USING_EXAMPLE_UART + bool "BSP_USING_EXAMPLE_UART" + default y + + config BSP_USING_EXAMPLE_PM + bool "BSP_USING_EXAMPLE_PM" + default n + + + endmenu + endmenu diff --git a/bsp/essemi/es32f0334/drivers/SConscript b/bsp/essemi/es32f0334/drivers/SConscript index 42b42394da1bec63d0bb48e5b39e2069f44aeb45..78bd8143122c9ffb2af02d30df738708889794b5 100644 --- a/bsp/essemi/es32f0334/drivers/SConscript +++ b/bsp/essemi/es32f0334/drivers/SConscript @@ -2,6 +2,8 @@ from building import * cwd = GetCurrentDir() +objs = [] + # add the general drivers. src = Split(''' board.c @@ -50,5 +52,43 @@ if GetDepend(['BSP_USING_ADC']): CPPPATH = [cwd] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) +objs = objs + group + +src = [] +cwd = GetCurrentDir() +include_path = [cwd] + +if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'): + src += ['bsp_driver_example/adc_vol_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_HWTIMER'): + src += ['bsp_driver_example/hwtimer_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_I2C'): + src += ['bsp_driver_example/i2c_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'): + src += ['bsp_driver_example/led_blink_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_PIN_BEEP'): + src += ['bsp_driver_example/pin_beep_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_PWM_LED'): + src += ['bsp_driver_example/pwm_led_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_RTC'): + src += ['bsp_driver_example/rtc_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_UART'): + src += ['bsp_driver_example/uart_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_SPI'): + src += ['bsp_driver_example/spi_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_PM'): + src += ['bsp_driver_example/pm_sample.c'] + +group = DefineGroup('bsp-drivers-test-samples', src, depend = [''], CPPPATH = include_path) -Return('group') +objs = objs + group +Return('objs') \ No newline at end of file diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/.gitignore b/bsp/essemi/es32f0334/drivers/bsp_driver_example/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..c6127b38c1aa25968a88db3940604d41529e4cf5 --- /dev/null +++ b/bsp/essemi/es32f0334/drivers/bsp_driver_example/.gitignore @@ -0,0 +1,52 @@ +# Prerequisites +*.d + +# Object files +*.o +*.ko +*.obj +*.elf + +# Linker output +*.ilk +*.map +*.exp + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex + +# Debug files +*.dSYM/ +*.su +*.idb +*.pdb + +# Kernel Module Compile Results +*.mod* +*.cmd +.tmp_versions/ +modules.order +Module.symvers +Mkfile.old +dkms.conf diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/README.md b/bsp/essemi/es32f0334/drivers/bsp_driver_example/README.md new file mode 100644 index 0000000000000000000000000000000000000000..80f12e1949235d15811415581686d64f623599f0 --- /dev/null +++ b/bsp/essemi/es32f0334/drivers/bsp_driver_example/README.md @@ -0,0 +1,47 @@ +# 外设驱动测试用例 + +## 1、介绍 + +这个软件包包含一些外设设备操作的例程。 + +### 1.1 例程说明 + +| 文件 | 说明 | +| ---------------- | ------------------------------- | +| adc_vol_sample.c | 使用 ADC 设备转换电压数据 | +| can_sample.c | 通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。 | +| hwtimer_sample.c | 使用 硬件定时器定时 | +| i2c_sample.c | 使用 i2c 设备进行读写 | +| pm.c | 反复进入不同程度的睡眠。 | +| led_blink_sample.c | 使用 pin 设备控制 LED 闪烁 | +| pin_beep_sample.c | 使用 pin 设备控制蜂鸣器 | +| pwm_led_sample.c | 使用 pwm 设备控制 LED 的亮度 | +| rtc_sample.c | 使用 rtc 设备设置年月日时分秒信息 | +| spi_sample.c | 使用 spi 设备进行读写 | +| uart_sample.c | 使用 serial 设备中断接收及轮询发送模式收发数据 | + +### 1.2 依赖 + +依赖设备管理模块提供的设备驱动。 + +## 2、如何打开 外设驱动测试用例 + +使用 外设驱动测试用例 需要在 RT-Thread 的menuconfig中选择它，具体路径如下： + +``` +Hardware Driver Config ---> + Peripheral Driver test example---> +``` + +## 3、使用 外设驱动测试用例 + +在打开 Peripheral Driver test example 后，当进行 BSP 编译时，选择的软件包相关源代码会被加入到 BSP 工程中进行编译。 + +## 4、注意事项 + +暂无。 + +## 5、联系方式 & 感谢 + +* 维护：[misonyo](https://github.com/misonyo) +* 主页：https://github.com/RT-Thread-packages/peripheral-sample diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/adc_vol_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/adc_vol_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..19eed3f35d66592b76bf99d1d9acb247113847ca --- /dev/null +++ b/bsp/essemi/es32f0334/drivers/bsp_driver_example/adc_vol_sample.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-29 misonyo first implementation. + */ +/* + * 程序清单： ADC 设备使用例程 + * 例程导出了 adc_sample 命令到控制终端 + * 命令调用格式：adc_sample + * 程序功能：通过 ADC 设备采样电压值并转换为数值。 + * 示例代码参考电压为3.3V,转换位数为12位。 +*/ + +#include +#include + +#define ADC_DEV_NAME "adc0" /* ADC 设备名称 */ +#define ADC_DEV_CHANNEL 5 /* PA1 ADC 通道 */ +#define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/ +#define CONVERT_BITS (1 << 12) /* 转换位数为12位 */ + +static int adc_vol_sample(int argc, char *argv[]) +{ + rt_adc_device_t adc_dev; + rt_uint32_t value, vol; + rt_err_t ret = RT_EOK; + + /* 查找设备 */ + adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME); + if (adc_dev == RT_NULL) + { + rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME); + return RT_ERROR; + } + + /* 使能设备 */ + ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL); + + /* 读取采样值 */ + value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL); + rt_kprintf("the value is :%d \n", value); + + /* 转换为对应电压值 */ + vol = value * REFER_VOLTAGE / CONVERT_BITS; + rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); + + /* 关闭通道 */ + ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL); + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/can_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/can_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..e63b11451d75ae6f05f7739c256d4aea8c3f6d42 --- /dev/null +++ b/bsp/essemi/es32f0334/drivers/bsp_driver_example/can_sample.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-06-25 misonyo first implementation. + */ +/* + * 程序清单：这是一个 CAN 设备使用例程 + * 例程导出了 can_sample 命令到控制终端 + * 命令调用格式：can_sample can2 + * 命令解释：命令第二个参数是要使用的 CAN 设备名称，为空则使用默认的 CAN 设备 + * 程序功能：通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。 +*/ + +#include +#include "rtdevice.h" + +#define CAN_DEV_NAME "can2" /* CAN 设备名称 */ + +static struct rt_semaphore rx_sem; /* 用于接收消息的信号量 */ +static rt_device_t can_dev; /* CAN 设备句柄 */ + +/* 接收数据回调函数 */ +static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size) +{ + /* CAN 接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */ + rt_sem_release(&rx_sem); + + return RT_EOK; +} + +static void can_rx_thread(void *parameter) +{ + int i; + struct rt_can_msg rxmsg = {0}; + + /* 设置接收回调函数 */ + rt_device_set_rx_indicate(can_dev, can_rx_call); + +#ifdef RT_CAN_USING_HDR + + rt_err_t res; + + struct rt_can_filter_item items[5] = + { + RT_CAN_FILTER_ITEM_INIT(0x100, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x100~0x1ff，hdr为-1，设置默认过滤表 */ + RT_CAN_FILTER_ITEM_INIT(0x300, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x300~0x3ff，hdr为-1 */ + RT_CAN_FILTER_ITEM_INIT(0x211, 0, 0, 0, 0x7ff, RT_NULL, RT_NULL), /* std,match ID:0x211，hdr为-1 */ + RT_CAN_FILTER_STD_INIT(0x486, RT_NULL, RT_NULL), /* std,match ID:0x486，hdr为-1 */ + {0x555, 0, 0, 0, 0x7ff, 7,} /* std,match ID:0x555，hdr为7，指定设置7号过滤表 */ + }; + struct rt_can_filter_config cfg = {5, 1, items}; /* 一共有5个过滤表 */ + /* 设置硬件过滤表 */ + res = rt_device_control(can_dev, RT_CAN_CMD_SET_FILTER, &cfg); + RT_ASSERT(res == RT_EOK); +#endif + + while (1) + { + /* hdr值为-1，表示直接从uselist链表读取数据 */ + rxmsg.hdr = -1; + /* 阻塞等待接收信号量 */ + rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + /* 从CAN读取一帧数据 */ + rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg)); + /* 打印数据ID及内容 */ + rt_kprintf("ID:%x ", rxmsg.id); + for (i = 0; i < 8; i++) + { + rt_kprintf("%2x ", rxmsg.data[i]); + } + + rt_kprintf("\n"); + } +} + +int can_sample(int argc, char *argv[]) +{ + struct rt_can_msg msg = {0}; + rt_err_t res; + rt_size_t size; + rt_thread_t thread; + char can_name[RT_NAME_MAX]; + + if (argc == 2) + { + rt_strncpy(can_name, argv[1], RT_NAME_MAX); + } + else + { + rt_strncpy(can_name, CAN_DEV_NAME, RT_NAME_MAX); + } + + can_dev = rt_device_find(can_name); + if (!can_dev) + { + rt_kprintf("find %s failed!\n", can_name); + return RT_ERROR; + } + + /* 初始化CAN接收信号量 */ + rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); + + /* 以中断接收及发送方式打开CAN设备 */ + res = rt_device_open(can_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX); + RT_ASSERT(res == RT_EOK); + + thread = rt_thread_create("can_rx", can_rx_thread, RT_NULL, 1024, 25, 10); + if (thread != RT_NULL) + { + rt_thread_startup(thread); + } + else + { + rt_kprintf("create can_rx thread failed!\n"); + } + + msg.id = 0x78; /* ID为0x78 */ + msg.ide = RT_CAN_STDID; /* 标准格式 */ + msg.rtr = RT_CAN_DTR; /* 数据帧 */ + msg.len = 8; /* 数据长度为8 */ + /* 待发送的8字节数据 */ + msg.data[0] = 0x00; + msg.data[1] = 0x11; + msg.data[2] = 0x22; + msg.data[3] = 0x33; + msg.data[4] = 0x44; + msg.data[5] = 0x55; + msg.data[6] = 0x66; + msg.data[7] = 0x77; + /* 发送一帧CAN数据 */ + size = rt_device_write(can_dev, 0, &msg, sizeof(msg)); + if (size == 0) + { + rt_kprintf("can dev write data failed!\n"); + } + + return res; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(can_sample, can device sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/hwtimer_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/hwtimer_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..e2e39664f3a5f7cd1c09f4a1e6dcf6d30e050e57 --- /dev/null +++ b/bsp/essemi/es32f0334/drivers/bsp_driver_example/hwtimer_sample.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-30 misonyo first implementation. + */ +/* + * 程序清单：这是一个 hwtimer 设备使用例程 + * 例程导出了 hwtimer_sample 命令到控制终端 + * 命令调用格式：hwtimer_sample + * 程序功能：硬件定时器超时回调函数周期性的打印当前tick值，2次tick值之差换算为时间等同于定时时间值。 +*/ + +#include +#include + +#define HWTIMER_DEV_NAME "timer0" /* 定时器名称 */ + +/* 定时器超时回调函数 */ +static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) +{ + rt_kprintf("tick is :%d !\n", rt_tick_get()); + + return 0; +} + +static int hwtimer_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + rt_hwtimerval_t timeout_s; /* 定时器超时值 */ + rt_device_t hw_dev = RT_NULL; /* 定时器设备句柄 */ + rt_hwtimer_mode_t mode; /* 定时器模式 */ + + /* 查找定时器设备 */ + hw_dev = rt_device_find(HWTIMER_DEV_NAME); + if (hw_dev == RT_NULL) + { + rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + return RT_ERROR; + } + + /* 以读写方式打开设备 */ + ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); + if (ret != RT_EOK) + { + rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + return ret; + } + + /* 设置超时回调函数 */ + rt_device_set_rx_indicate(hw_dev, timeout_cb); + + /* 设置模式为周期性定时器 */ + mode = HWTIMER_MODE_PERIOD; + ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + if (ret != RT_EOK) + { + rt_kprintf("set mode failed! ret is :%d\n", ret); + return ret; + } + + /* 设置定时器超时值为5s并启动定时器 */ + timeout_s.sec = 5; /* 秒 */ + timeout_s.usec = 0; /* 微秒 */ + + if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s)) + { + rt_kprintf("set timeout value failed\n"); + return RT_ERROR; + } + + /* 延时3500ms */ + rt_thread_mdelay(3500); + + /* 读取定时器当前值 */ + rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); + rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/i2c_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/i2c_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..2d386433c63a7a1a1cb61ab1a7891adf632c7b9e --- /dev/null +++ b/bsp/essemi/es32f0334/drivers/bsp_driver_example/i2c_sample.c @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy first implementation. + */ +/* + * 程序清单：这是一个 I2C 设备使用例程 + * 例程导出了 i2c_io_sample 命令到控制终端 + * 命令调用格式：i2c_io_sample + * 命令解释：使用默认的I2C总线设备 + * 程序功能：通过 I2C 设备接收数据并打印，然后将接收的字符加1输出。 +*/ + +#include +#include + +#define I2C_BUS_NAME "i2c1" /* I2C总线设备名称 */ +#define SLAVE_ADDR 0x2D /* 从机地址 */ +#define STR_LEN 16 /* 接收发送的数据长度 */ + +static void i2c_io_sample(int argc, char *argv[]) +{ + + struct rt_i2c_bus_device *i2c_bus = RT_NULL; /* I2C总线设备句柄 */ + struct rt_i2c_msg temp_msg; /* I2C消息 */ + rt_uint8_t buffer[STR_LEN] = { 0U }; + rt_uint32_t i,num_msg; + rt_size_t s_stat; + + i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(I2C_BUS_NAME); /* 通过名字获取I2C总线设备的句柄 */ + + if( i2c_bus == RT_NULL) + { + rt_kprintf("can't find i2c device :%s !\n",I2C_BUS_NAME); + + return; + } + + /*初始化消息*/ + temp_msg.addr = SLAVE_ADDR; /* 从机地址 */ + temp_msg.len = STR_LEN; /* 传输的数据长度 */ + temp_msg.buf = buffer; /* 读写缓存器 */ + + num_msg = 1; /* 传输一条消息 */ + + temp_msg.flags = RT_I2C_RD; /* I2C读 */ + s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输消息 */ + + rt_thread_mdelay(400); + + if( s_stat == num_msg ) + { + rt_kprintf("receive successful. \n receive messege : %s \n:",buffer); + + for( i = 0 ; i < STR_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + } + else + { + rt_kprintf("device s% recieve fail \n buffer : s%\n",I2C_BUS_NAME,buffer); + return; + } + + for( i = 0 ; i < STR_LEN ; i++) + buffer[i]++; + + temp_msg.flags = RT_I2C_WR; /* I2C写 */ + s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输一条 */ + + rt_thread_mdelay(400); + + if( s_stat == num_msg ) + { + rt_kprintf(" send successful \n messege : %s \n:",buffer); + + for( i = 0 ; i < STR_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + } + else + { + rt_kprintf("device s% send fail \n",I2C_BUS_NAME); + return; + } + + return; + +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(i2c_io_sample, i2c io sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/led_blink_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/led_blink_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..c073b5e5a7e558e2631cb49e07b7156dfebdc35f --- /dev/null +++ b/bsp/essemi/es32f0334/drivers/bsp_driver_example/led_blink_sample.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-09-25 misonyo first edition. + */ +/* + * 程序清单：这是一个通过PIN脚控制LED亮灭的使用例程 + * 例程导出了 led_sample 命令到控制终端 + * 命令调用格式：led_sample + * 命令解释：命令第二个参数是要使用的PIN脚编号，为空则使用例程默认的引脚编号。 + * 程序功能：程序创建一个led线程，线程每隔1000ms改变PIN脚状态，达到控制led灯 + * 亮灭的效果。 +*/ + +#include +#include +#include + +/* PIN脚编号，查看驱动文件drv_gpio.c确定 */ +#define LED_PIN_NUM 45 /*PA12*/ +static int pin_num; + +static void led_entry(void *parameter) +{ + int count = 0; + /* 设置PIN脚模式为输出 */ + rt_pin_mode(pin_num, PIN_MODE_OUTPUT); + + while (1) + { + count++; + rt_kprintf("thread run count : %d\r\n", count); + /* 拉低PIN脚 */ + rt_pin_write(pin_num, PIN_LOW); + rt_kprintf("led on!\r\n"); + /* 延时1000ms */ + rt_thread_mdelay(1000); + + /* 拉高PIN脚 */ + rt_pin_write(pin_num, PIN_HIGH); + rt_kprintf("led off!\r\n"); + rt_thread_mdelay(1000); + } +} + +static int led_sample(int argc, char *argv[]) +{ + rt_thread_t tid; + rt_err_t ret = RT_EOK; + + /* 判断命令行参数是否给定了PIN脚编号 */ + if (argc == 2) + { + pin_num = atoi(argv[1]); + } + else + { + pin_num = LED_PIN_NUM; + } + + tid = rt_thread_create("led", + led_entry, + RT_NULL, + 512, + RT_THREAD_PRIORITY_MAX / 3, + 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + ret = RT_ERROR; + } + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(led_sample, led sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/pin_beep_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/pin_beep_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..911a0c800ec9f88458d3e408fb7cb2201f4f3be4 --- /dev/null +++ b/bsp/essemi/es32f0334/drivers/bsp_driver_example/pin_beep_sample.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-15 misonyo first implementation. + */ +/* + * 程序清单：这是一个 PIN 设备使用例程 + * 例程导出了 pin_beep_sample 命令到控制终端 + * 命令调用格式：pin_beep_sample + * 程序功能：通过按键控制蜂鸣器对应引脚的电平状态控制蜂鸣器 +*/ + +#include +#include + +/* 引脚编号，通过查看驱动文件drv_gpio.c确定 */ +#ifndef BEEP_PIN_NUM + #define BEEP_PIN_NUM 45 /* PA12 */ +#endif +#ifndef KEY0_PIN_NUM + #define KEY0_PIN_NUM 18 /* PF0 */ +#endif +#ifndef KEY1_PIN_NUM + #define KEY1_PIN_NUM 19 /* PF1 */ +#endif + +void beep_on(void *args) +{ + rt_kprintf("turn on beep!\n"); + + rt_pin_write(BEEP_PIN_NUM, PIN_HIGH); +} + +void beep_off(void *args) +{ + rt_kprintf("turn off beep!\n"); + + rt_pin_write(BEEP_PIN_NUM, PIN_LOW); +} + +static void pin_beep_sample(void) +{ + /* 蜂鸣器引脚为输出模式 */ + rt_pin_mode(BEEP_PIN_NUM, PIN_MODE_OUTPUT); + /* 默认低电平 */ + rt_pin_write(BEEP_PIN_NUM, PIN_LOW); + + /* 按键0引脚为输入模式 */ + rt_pin_mode(KEY0_PIN_NUM, PIN_MODE_INPUT_PULLUP); + /* 绑定中断，下降沿模式，回调函数名为beep_on */ + rt_pin_attach_irq(KEY0_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_on, RT_NULL); + /* 使能中断 */ + rt_pin_irq_enable(KEY0_PIN_NUM, PIN_IRQ_ENABLE); + + /* 按键1引脚为输入模式 */ + rt_pin_mode(KEY1_PIN_NUM, PIN_MODE_INPUT_PULLUP); + /* 绑定中断，下降沿模式，回调函数名为beep_off */ + rt_pin_attach_irq(KEY1_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_off, RT_NULL); + /* 使能中断 */ + rt_pin_irq_enable(KEY1_PIN_NUM, PIN_IRQ_ENABLE); +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(pin_beep_sample, pin beep sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/pm_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/pm_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..08258b165007557a7a2c1068fab07af0faa00082 --- /dev/null +++ b/bsp/essemi/es32f0334/drivers/bsp_driver_example/pm_sample.c @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy first implementation. + */ +/* + * 程序清单：这是一个 pm睡眠唤醒的使用例程 + * 例程导出了 pm_sample 命令到控制终端 + * 命令调用格式：pm_sample + * 命令解释：进入不同的睡眠模式，然后用按键唤醒 + * 程序功能：通过串口输出字符串，告知进入睡眠和唤醒睡眠的情况。 +*/ + +#include +#include + +#define PM_NAME "pm" /* 设备名称 */ +#define WAKE_UP_PIN 18 /* 唤醒源 */ +#define SLEEP_TIMES 12 /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */ + +struct pm_callback_t +{ + volatile int in_fun_times; /*进入函数的次数*/ + volatile char flag; /*标志*/ + volatile int mode; /*需要打印的模式*/ +}; + +volatile struct pm_callback_t g_pm_data; + +/*进入睡眠前，睡眠唤醒后，都会进入。*/ +/*函数打印睡眠相关的信息*/ +void sleep_in_out_callback(rt_uint8_t event, rt_uint8_t mode, void *data) +{ + /*没有标志，不处理*/ + if(!(g_pm_data.flag)) + { + return; + } + + /*标志不正常，清空标志*/ + if((g_pm_data.flag) > 2) + { + (g_pm_data.flag) = 0; + return; + } + + /*模式不匹配*/ + if(g_pm_data.mode != mode ) + { + return; + } + + /*进入的事件*/ + switch(event) + { + /*进入睡眠前*/ + case RT_PM_ENTER_SLEEP: g_pm_data.flag = 1; + rt_kprintf("\n\r##%d : ENTER ",g_pm_data.in_fun_times); + g_pm_data.in_fun_times++; /*进入睡眠次数+1*/ + break; + /*睡眠唤醒后*/ + case RT_PM_EXIT_SLEEP: g_pm_data.flag = 0; /*睡眠唤醒后*/ + rt_kprintf("\n\rEXIT\n\r"); + rt_pm_release(mode); /*释放休眠模式*/ + return; + + default: break; + + }; + + /*当前的睡眠模式*/ + switch(mode) + { + case PM_SLEEP_MODE_NONE: rt_kprintf("PM_SLEEP_MODE_NONE\n\r"); + break; + case PM_SLEEP_MODE_IDLE: rt_kprintf("PM_SLEEP_MODE_IDLE\n\r"); + break; + case PM_SLEEP_MODE_LIGHT: rt_kprintf("PM_SLEEP_MODE_LIGHT\n\r"); + break; + case PM_SLEEP_MODE_DEEP: rt_kprintf("PM_SLEEP_MODE_DEEP\n\r"); + break; + case PM_SLEEP_MODE_STANDBY: rt_kprintf("PM_SLEEP_MODE_STANDBY\n\r"); + break; + case PM_SLEEP_MODE_SHUTDOWN: rt_kprintf("PM_SLEEP_MODE_SHUTDOWN\n\r"); + break; + case PM_SLEEP_MODE_MAX: rt_kprintf("PM_SLEEP_MODE_MAX\n\r"); + break; + default: break; + } + +} + +/* pm测试函数 */ +static void pm_test(void *parameter) +{ + int in_mode[7],i = 0; + + g_pm_data.in_fun_times = 0; + g_pm_data.flag = 0; + + in_mode[0] = PM_SLEEP_MODE_NONE; + in_mode[1] = PM_SLEEP_MODE_IDLE; + in_mode[2] = PM_SLEEP_MODE_LIGHT; + in_mode[3] = PM_SLEEP_MODE_DEEP; + in_mode[4] = PM_SLEEP_MODE_STANDBY; + in_mode[5] = PM_SLEEP_MODE_SHUTDOWN; + in_mode[6] = PM_SLEEP_MODE_MAX; + + /*设置回调函数和私有数据*/ + rt_pm_notify_set(sleep_in_out_callback,RT_NULL); + + while(i < SLEEP_TIMES) + { + + g_pm_data.mode = in_mode[i%6]; + + /*无休眠模式，不赋予标志*/ + if(g_pm_data.mode != PM_SLEEP_MODE_NONE) + { + g_pm_data.flag = 2; + + } + + /*请求选择的休眠模式*/ + rt_pm_request(in_mode[i%6]); + + rt_thread_mdelay(500); + + /*无休眠模式，不需要额外的等待*/ + while(( g_pm_data.flag != 0 )&&(g_pm_data.mode != PM_SLEEP_MODE_NONE)) + { + rt_thread_mdelay(500); + } + + /*释放选择的休眠模式*/ + rt_pm_release(in_mode[i%6]); + + i++; + + } + /*清除回调函数和私有数据*/ + rt_pm_notify_set(RT_NULL,RT_NULL); + rt_kprintf("thread pm_test close\n\r"); +} + +/*按键唤醒的回调函数*/ +void wake_by_pin(void *args) +{ + +} + +static int pm_sample(int argc, char *argv[]) +{ + rt_thread_t thread; + + /* 按键引脚为输入模式 */ + rt_pin_mode(WAKE_UP_PIN, PIN_MODE_INPUT_PULLUP); + + /* 绑定中断，下降沿模式，回调函数名为wake_by_pin */ + rt_pin_attach_irq(WAKE_UP_PIN, PIN_IRQ_MODE_RISING, wake_by_pin, RT_NULL); + /* 使能中断 */ + rt_pin_irq_enable(WAKE_UP_PIN, PIN_IRQ_ENABLE); + + thread = rt_thread_create("pm_test", pm_test, RT_NULL, 1024, 25, 10); + + if (thread != RT_NULL) + { + rt_thread_startup(thread); + } + else + { + rt_kprintf("create pm_test thread failed!\n\r"); + } + + return RT_EOK; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(pm_sample, pm sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/pwm_led_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/pwm_led_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..1ac23614458045185a5a11da5dca7a56bf0e2ae8 --- /dev/null +++ b/bsp/essemi/es32f0334/drivers/bsp_driver_example/pwm_led_sample.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-25 misonyo first implementation. + */ +/* + * 程序清单：这是一个 PWM 设备使用例程 + * 例程导出了 pwm_led_sample 命令到控制终端 + * 命令调用格式：pwm_led_sample + * 程序功能：通过 PWM 设备控制 LED 灯的亮度，可以看到LED不停的由暗变到亮，然后又从亮变到暗。 +*/ + +#include +#include + +#define LED_PIN_NUM 45 /* PA12 LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ +#define PWM_DEV_NAME "pwm0" /* PWM设备名称 */ +#define PWM_DEV_CHANNEL 2 /* PA9 PWM通道 */ + +struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */ + +static int pwm_led_sample(int argc, char *argv[]) +{ + rt_uint32_t period, pulse, dir; + + period = 500000; /* 周期为0.5ms，单位为纳秒ns */ + dir = 1; /* PWM脉冲宽度值的增减方向 */ + pulse = 0; /* PWM脉冲宽度值，单位为纳秒ns */ + + /* 查找设备 */ + pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME); + if (pwm_dev == RT_NULL) + { + rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME); + return RT_ERROR; + } + + /* 设置PWM周期和脉冲宽度默认值 */ + rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); + /* 使能设备 */ + rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL); + + while (1) + { + rt_thread_mdelay(50); + if (dir) + { + pulse += 5000; /* 从0值开始每次增加5000ns */ + } + else + { + pulse -= 5000; /* 从最大值开始每次减少5000ns */ + } + if (pulse >= period) + { + dir = 0; + } + if (0 == pulse) + { + dir = 1; + } + + /* 设置PWM周期和脉冲宽度 */ + rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); + } +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(pwm_led_sample, pwm sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/rtc_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/rtc_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..711a3a0ebb497521114bbd24dd99933dbbd786a2 --- /dev/null +++ b/bsp/essemi/es32f0334/drivers/bsp_driver_example/rtc_sample.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-30 misonyo first implementation. + */ +/* + * 程序清单：这是一个 RTC 设备使用例程 + * 例程导出了 rtc_sample 命令到控制终端 + * 命令调用格式：rtc_sample + * 程序功能：设置RTC设备的日期和时间，延时一段时间后获取当前时间并打印显示。 +*/ + +#include +#include + +static int rtc_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + time_t now; + + /* 设置日期 */ + ret = set_date(2018, 12, 3); + if (ret != RT_EOK) + { + rt_kprintf("set RTC date failed\n"); + return ret; + } + + /* 设置时间 */ + ret = set_time(11, 15, 50); + if (ret != RT_EOK) + { + rt_kprintf("set RTC time failed\n"); + return ret; + } + + /* 延时3秒 */ + rt_thread_mdelay(3000); + + /* 获取时间 */ + now = time(RT_NULL); + rt_kprintf("%s\n", ctime(&now)); + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(rtc_sample, rtc sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/spi_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/spi_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..994888cdb0d8a52bebf6bcd89f29df291db6dbe1 --- /dev/null +++ b/bsp/essemi/es32f0334/drivers/bsp_driver_example/spi_sample.c @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy first implementation. + */ +/* + * 程序清单：这是一个 SPI 设备使用例程 + * 例程导出了 spi_io_sample 命令到控制终端 + * 命令调用格式：spi_io_sample + * 程序功能：通过SPI设备先读取数据，然后每个字符加1后输出。 +*/ + +#include +#include + +#define SPI_DEVICE_NAME "spi00" +#define BUF_LEN 16 + +static void spi_io_sample(int argc, char *argv[]) +{ + struct rt_spi_device * spi_dev; /* spi设备的句柄 */ + struct rt_spi_configuration spi_config; + rt_uint8_t i,buffer[BUF_LEN] = { 0U }; + rt_err_t s_stat; + rt_err_t result; + + /* 查找 spi设备 获取spi设备句柄 */ + spi_dev = (struct rt_spi_device *)rt_device_find(SPI_DEVICE_NAME); + + if (spi_dev == RT_NULL) + { + rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_DEVICE_NAME); + return; + } + + + /* 清空配置结构体 */ + rt_memset(&spi_config,0,sizeof(struct rt_spi_configuration)); + + spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ + spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ + spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ + spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ + spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ + spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ + + spi_config.data_width = 8; /* 数据长度：8 */ + + spi_config.max_hz = 2000000; /* 最快时钟频率 */ + + /* 配置SPI设备 */ + s_stat = rt_spi_configure(spi_dev,&spi_config); + + if(s_stat != RT_EOK) + { + rt_kprintf(" spi config fail !\n "); + return; + } + + + /* 获取总线 ，防止总线被多个线程同时使用 */ + result = rt_spi_take_bus(spi_dev); + + if (result != RT_EOK) + { + rt_kprintf(" %s take spi bus failed! \n", SPI_DEVICE_NAME); + return; + } + + /* 选中片选 */ + result = rt_spi_take(spi_dev); + + if (result != RT_EOK) + { + rt_kprintf(" %s take spi cs failed! \n", SPI_DEVICE_NAME); + return; + } + + + /*接收一次数据*/ + result = rt_spi_recv(spi_dev,buffer,BUF_LEN); + + if(result != BUF_LEN) + { + rt_kprintf("receive fail. \n buffer is : %s \n:",buffer); + + for( i = 0 ; i < BUF_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + + return; + } + + rt_kprintf("receive successful. \n buffer is : %s \n:",buffer); + + for( i = 0 ; i < BUF_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + + /* 将接收到的数据加1 */ + for( i = 0 ; i < BUF_LEN ; i++) + buffer[i]++; + + /*发送数据*/ + result = rt_spi_send(spi_dev,buffer,BUF_LEN); + + if(result != BUF_LEN) + { + rt_kprintf("send fail. \n buffer is : %s \n:",buffer); + + for( i = 0 ; i < BUF_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + + return; + } + + rt_kprintf("send successful. \n buffer is : %s \n:",buffer); + + for( i = 0 ; i < BUF_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + + /* 释放片选 */ + result = rt_spi_release(spi_dev); + + if (result != RT_EOK) + { + rt_kprintf(" %s release spi cs failed! \n", SPI_DEVICE_NAME); + return; + } + + /* 释放总线 */ + result = rt_spi_release_bus(spi_dev); + + if (result != RT_EOK) + { + rt_kprintf(" %s release spi bus failed! \n", SPI_DEVICE_NAME); + return; + } + +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(spi_io_sample, spi sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/uart_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/uart_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..cbfd6bcceff5af1e4f5eaaa9a0eb89b3276c8c09 --- /dev/null +++ b/bsp/essemi/es32f0334/drivers/bsp_driver_example/uart_sample.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-15 misonyo first implementation. + */ +/* + * 程序清单：这是一个 串口 设备使用例程 + * 例程导出了 uart_sample 命令到控制终端 + * 命令调用格式：uart_sample uart2 + * 命令解释：命令第二个参数是要使用的串口设备名称，为空则使用默认的串口设备 + * 程序功能：通过串口输出字符串"hello RT-Thread!"，然后错位输出输入的字符 +*/ + +#include + +#define SAMPLE_UART_NAME "uart1" /* 串口设备名称 */ + +/* 用于接收消息的信号量 */ +static struct rt_semaphore rx_sem; +static rt_device_t serial; + +/* 接收数据回调函数 */ +static rt_err_t uart_input(rt_device_t dev, rt_size_t size) +{ + /* 串口接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */ + rt_sem_release(&rx_sem); + + return RT_EOK; +} + +static void serial_thread_entry(void *parameter) +{ + char ch; + + while (1) + { + /* 从串口读取一个字节的数据，没有读取到则等待接收信号量 */ + while (rt_device_read(serial, -1, &ch, 1) != 1) + { + /* 阻塞等待接收信号量，等到信号量后再次读取数据 */ + rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + } + /* 读取到的数据通过串口错位输出 */ + ch = ch + 1; + rt_device_write(serial, 0, &ch, 1); + } +} + +static int uart_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + char uart_name[RT_NAME_MAX]; + char str[] = "hello RT-Thread!\r\n"; + + if (argc == 2) + { + rt_strncpy(uart_name, argv[1], RT_NAME_MAX); + } + else + { + rt_strncpy(uart_name, SAMPLE_UART_NAME, RT_NAME_MAX); + } + + /* 查找串口设备 */ + serial = rt_device_find(uart_name); + if (!serial) + { + rt_kprintf("find %s failed!\n", uart_name); + return RT_ERROR; + } + + /* 初始化信号量 */ + rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); + /* 以中断接收及轮询发送方式打开串口设备 */ + rt_device_open(serial, RT_DEVICE_FLAG_INT_RX); + /* 设置接收回调函数 */ + rt_device_set_rx_indicate(serial, uart_input); + /* 发送字符串 */ + rt_device_write(serial, 0, str, (sizeof(str) - 1)); + + /* 创建 serial 线程 */ + rt_thread_t thread = rt_thread_create("serial", serial_thread_entry, RT_NULL, 1024, 25, 10); + /* 创建成功则启动线程 */ + if (thread != RT_NULL) + { + rt_thread_startup(thread); + } + else + { + ret = RT_ERROR; + } + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(uart_sample, uart device sample); diff --git a/bsp/essemi/es32f0334/drivers/drv_adc.c b/bsp/essemi/es32f0334/drivers/drv_adc.c index 582ebe64bcdb5fb9ed3f6899f40bc010c2160c77..d9f1e5b899da4634cddac2f1785110416ca83e64 100644 --- a/bsp/essemi/es32f0334/drivers/drv_adc.c +++ b/bsp/essemi/es32f0334/drivers/drv_adc.c @@ -146,9 +146,9 @@ static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t c RT_ASSERT(value != RT_NULL); /* config adc channel */ - nm_config.channel = es32f0_adc_get_channel(channel); - nm_config.rank = ADC_NCH_RANK_1; - nm_config.samp_time = ADC_SAMPLETIME_4; + nm_config.ch = es32f0_adc_get_channel(channel); + nm_config.idx = ADC_NCH_IDX_1; + nm_config.samp = ADC_SAMPLETIME_4; ald_adc_normal_channel_config(_hadc, &nm_config); ald_adc_normal_start(_hadc); @@ -172,16 +172,16 @@ int rt_hw_adc_init(void) /* adc function initialization */ _h_adc0.perh = ADC0; - _h_adc0.init.data_align = ADC_DATAALIGN_RIGHT; - _h_adc0.init.scan_mode = DISABLE; - _h_adc0.init.cont_mode = DISABLE; - _h_adc0.init.disc_mode = ADC_ALL_DISABLE; - _h_adc0.init.disc_nbr = ADC_DISC_NBR_1; - _h_adc0.init.conv_res = ADC_CONV_RES_10; - _h_adc0.init.clk_div = ADC_CKDIV_128; + _h_adc0.init.align = ADC_DATAALIGN_RIGHT; + _h_adc0.init.scan = DISABLE; + _h_adc0.init.cont = DISABLE; + _h_adc0.init.disc = ADC_ALL_DISABLE; + _h_adc0.init.disc_nr = ADC_DISC_NR_1; + _h_adc0.init.data_bit = ADC_CONV_BIT_12; + _h_adc0.init.div = ADC_CKDIV_128; _h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL; - _h_adc0.init.neg_ref = ADC_NEG_REF_VSS; - _h_adc0.init.pos_ref = ADC_POS_REF_VDD; + _h_adc0.init.n_ref = ADC_NEG_REF_VSS; + _h_adc0.init.p_ref = ADC_POS_REF_VDD; ald_adc_init(&_h_adc0); rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, &_h_adc0); diff --git a/bsp/essemi/es32f0334/drivers/drv_i2c.c b/bsp/essemi/es32f0334/drivers/drv_i2c.c index 6e8300091480e7ff09fb4839211e65b279be482c..6824d654b524cbba2c0f8059fafd62de7bef79a5 100644 --- a/bsp/essemi/es32f0334/drivers/drv_i2c.c +++ b/bsp/essemi/es32f0334/drivers/drv_i2c.c @@ -7,6 +7,7 @@ * Date Author Notes * 2019-03-19 wangyq the first version * 2019-11-01 wangyq update libraries + * 2020-12-15 liuhy update libraries */ #include @@ -29,7 +30,7 @@ static void _i2c_init(void) /* Initialize I2C Pin */ gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; + gpio_instruct.odos = GPIO_OPEN_DRAIN; gpio_instruct.pupd = GPIO_PUSH_UP; gpio_instruct.odrv = GPIO_OUT_DRIVE_NORMAL; gpio_instruct.flt = GPIO_FILTER_DISABLE; diff --git a/bsp/essemi/es32f0334/drivers/drv_pm.c b/bsp/essemi/es32f0334/drivers/drv_pm.c index dbf6b4be1e87b3feed215edc27fcf94f3c2472a2..d08c13f8d03bf3a47d5a236d318f5fce0dfa1be0 100644 --- a/bsp/essemi/es32f0334/drivers/drv_pm.c +++ b/bsp/essemi/es32f0334/drivers/drv_pm.c @@ -8,7 +8,7 @@ * 2019-04-08 wangyq the first version * 2019-11-01 wangyq adapt to the new power management interface */ - +#include #include #include #include @@ -24,6 +24,21 @@ static void uart_console_reconfig(void) rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config); } +static void delay(void) +{ + long i; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + i = 0; + do{ + i++; + } + while (i < 10000); + + rt_hw_interrupt_enable(level); +} + /** * This function will put ES32F033x into sleep mode. * @@ -50,22 +65,26 @@ static void sleep(struct rt_pm *pm, uint8_t mode) { /* Enter SLEEP Mode, Main regulator is ON */ ald_pmu_stop1_enter(); + delay(); } break; case PM_SLEEP_MODE_DEEP: /* Enter STOP 2 mode */ ald_pmu_stop2_enter(); + delay(); break; case PM_SLEEP_MODE_STANDBY: /* Enter STANDBY mode */ ald_pmu_stop2_enter(); + delay(); break; case PM_SLEEP_MODE_SHUTDOWN: /* Enter SHUTDOWNN mode */ ald_pmu_stop2_enter(); + delay(); break; default: diff --git a/bsp/essemi/es32f0334/drivers/drv_spi.c b/bsp/essemi/es32f0334/drivers/drv_spi.c index e823979a158cf7893e02b4de79b0ea3192afa86d..dd376911259142c4dcfc22be6f6be16fd1ddfce1 100644 --- a/bsp/essemi/es32f0334/drivers/drv_spi.c +++ b/bsp/essemi/es32f0334/drivers/drv_spi.c @@ -5,8 +5,9 @@ * * Change Logs: * Date Author Notes - * 2019-03-19 wangyq the first version + * 2019-01-24 wangyq the first version * 2019-11-01 wangyq update libraries + * 2020-12-15 liuhy update libraries */ #include @@ -146,19 +147,21 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * RT_ASSERT(device != RT_NULL); RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(device->bus->parent.user_data != RT_NULL); - RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL); hspi = (spi_handle_t *)device->bus->parent.user_data; cs = device->parent.user_data; - - /* only send data */ - if (message->recv_buf == RT_NULL) + + if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL) + { + /* send & receive */ + if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL)) { if (message->cs_take) { rt_pin_write(cs->pin, 0); } - res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); + res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, + (rt_int32_t)message->length, SPITIMEOUT); if (message->cs_release) { rt_pin_write(cs->pin, 1); @@ -166,41 +169,56 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * if (res != RT_EOK) return RT_ERROR; } - - /* only receive data */ - if (message->send_buf == RT_NULL) + else { - if (message->cs_take) + /* only send data */ + if (message->recv_buf == RT_NULL) { - rt_pin_write(cs->pin, 0); + if (message->cs_take) + { + rt_pin_write(cs->pin, 0); + } + res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) + { + rt_pin_write(cs->pin, 1); + } + if (res != RT_EOK) + return RT_ERROR; } - res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) + /* only receive data */ + if (message->send_buf == RT_NULL) { - rt_pin_write(cs->pin, 1); + if (message->cs_take) + { + rt_pin_write(cs->pin, 0); + } + res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) + { + rt_pin_write(cs->pin, 1); + } + if (res != RT_EOK) + return RT_ERROR; } - if (res != RT_EOK) - return RT_ERROR; } - /* send & receive */ + } else { - if (message->cs_take) + if (message->cs_take) { rt_pin_write(cs->pin, 0); } - res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, - (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) { rt_pin_write(cs->pin, 1); } - if (res != RT_EOK) - return RT_ERROR; + return RT_EOK; } - return message->length; + } const struct rt_spi_ops es32f0_spi_ops = @@ -209,21 +227,45 @@ const struct rt_spi_ops es32f0_spi_ops = spixfer, }; -static struct rt_spi_bus _spi_bus0, _spi_bus1; -static spi_handle_t _spi0, _spi1; -int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name) + +rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name) +{ + /* define spi Instance */ + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + struct es32f0_hw_spi_cs *cs_pin = (struct es32f0_hw_spi_cs *)rt_malloc(sizeof(struct es32f0_hw_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + cs_pin->pin = pin; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, 1); + return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); +} + +#ifdef BSP_USING_SPI0 + static struct rt_spi_bus _spi_bus0; + static spi_handle_t _spi0; +#endif + +#ifdef BSP_USING_SPI1 + static struct rt_spi_bus _spi_bus1; + static spi_handle_t _spi1; +#endif + +int rt_hw_spi_init(void) { + int result = RT_EOK; + struct rt_spi_bus *spi_bus; spi_handle_t *spi; gpio_init_t gpio_instruct; - if (SPIx == SPI0) - { - _spi0.perh = SPI0; - spi_bus = &_spi_bus0; - spi = &_spi0; +#ifdef BSP_USING_SPI0 + _spi0.perh = SPI0; + spi_bus = &_spi_bus0; + spi = &_spi0; + rt_device_t spi_bus_dev0; - /* SPI0 gpio init */ + /* SPI0 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; gpio_instruct.odos = GPIO_PUSH_PULL; gpio_instruct.func = GPIO_FUNC_4; @@ -236,14 +278,33 @@ int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name) /* PB4->SPI0_MISO */ gpio_instruct.mode = GPIO_MODE_INPUT; ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct); + + spi_bus->parent.user_data = spi; + result = rt_spi_bus_register(spi_bus, "spi0", &es32f0_spi_ops); + if (result != RT_EOK) + { + return result; } - else if (SPIx == SPI1) + + rt_device_register(spi_bus_dev0, "spi00", RT_DEVICE_FLAG_RDWR); + + /* SPI0_NSS = PA15 = PIN 50 */ + result = es32f0_spi_device_attach(50, "spi0", "spi00"); + + if (result != RT_EOK) { - _spi1.perh = SPI1; - spi_bus = &_spi_bus1; - spi = &_spi1; + return result; + } + +#endif - /* SPI1 gpio init */ +#ifdef BSP_USING_SPI1 + _spi1.perh = SPI1; + spi_bus = &_spi_bus1; + spi = &_spi1; + rt_device_t spi_bus_dev0; + + /* SPI1 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; gpio_instruct.odos = GPIO_PUSH_PULL; gpio_instruct.func = GPIO_FUNC_4; @@ -256,39 +317,24 @@ int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name) /* PB14->SPI1_MISO */ gpio_instruct.mode = GPIO_MODE_INPUT; ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct); + + spi_bus->parent.user_data = spi; + result = rt_spi_bus_register(spi_bus, "spi1", &es32f0_spi_ops); + if (result != RT_EOK) + { + return result; } - else + + rt_device_register(spi_bus_dev0, "spi10", RT_DEVICE_FLAG_RDWR); + + /* SPI1_NSS = PC00 = PIN 8 */ + result = es32f0_spi_device_attach(8, "spi1", "spi10"); + + if (result != RT_EOK) { - return -1; + return result; } - spi_bus->parent.user_data = spi; - - return rt_spi_bus_register(spi_bus, name, &es32f0_spi_ops); -} - -rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name) -{ - /* define spi Instance */ - struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); - RT_ASSERT(spi_device != RT_NULL); - struct es32f0_hw_spi_cs *cs_pin = (struct es32f0_hw_spi_cs *)rt_malloc(sizeof(struct es32f0_hw_spi_cs)); - RT_ASSERT(cs_pin != RT_NULL); - cs_pin->pin = pin; - rt_pin_mode(pin, PIN_MODE_OUTPUT); - rt_pin_write(pin, 1); - return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); -} - -int rt_hw_spi_init(void) -{ - int result = 0; - -#ifdef BSP_USING_SPI0 - result = es32f0_spi_register_bus(SPI0, "spi0"); -#endif - -#ifdef BSP_USING_SPI1 - result = es32f0_spi_register_bus(SPI1, "spi1"); + #endif return result; diff --git a/bsp/essemi/es32f0334/figures/drv_conf.jpg b/bsp/essemi/es32f0334/figures/drv_conf.jpg new file mode 100644 index 0000000000000000000000000000000000000000..313e8f1266514b811bfb5c6ab2205ef46df36208 Binary files /dev/null and b/bsp/essemi/es32f0334/figures/drv_conf.jpg differ diff --git a/bsp/essemi/es32f0334/figures/drv_ex.jpg b/bsp/essemi/es32f0334/figures/drv_ex.jpg new file mode 100644 index 0000000000000000000000000000000000000000..be631895b68568dffd891672f77d0d55f523bb54 Binary files /dev/null and b/bsp/essemi/es32f0334/figures/drv_ex.jpg differ diff --git a/bsp/essemi/es32f0334/figures/k_conf.jpg b/bsp/essemi/es32f0334/figures/k_conf.jpg new file mode 100644 index 0000000000000000000000000000000000000000..d900bd825105f3147d9f38919ca1e239cf55149c Binary files /dev/null and b/bsp/essemi/es32f0334/figures/k_conf.jpg differ diff --git a/bsp/essemi/es32f0334/figures/k_ex.jpg b/bsp/essemi/es32f0334/figures/k_ex.jpg new file mode 100644 index 0000000000000000000000000000000000000000..a4b1d3874d47f06a80cc6328322eaba41d62571a Binary files /dev/null and b/bsp/essemi/es32f0334/figures/k_ex.jpg differ diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Include/es32f033x.h b/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Include/es32f033x.h index d815dac5195fa562b2a64f422e3b45b4316acfc8..e322ab99668a7610a744526f58b20bf7dfbb74ba 100644 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Include/es32f033x.h +++ b/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Include/es32f033x.h @@ -40,7 +40,7 @@ typedef enum IRQn { /* es32f0xx specific interrupt index */ WWDG_IWDG_IRQn = 0, LVD_IRQn = 1, - RTC_TSENSE_IRQn = 2, + RTC_TSENSE_IRQn = 2, CRYPT_TRNG_IRQn = 3, CMU_IRQn = 4, EXTI0_3_IRQn = 5, @@ -284,21 +284,11 @@ typedef struct #define BKPC_PCCR_RTCCS_POSE 1U #define BKPC_PCCR_RTCCS_MSK BITS(BKPC_PCCR_RTCCS_POSS,BKPC_PCCR_RTCCS_POSE) -/****************** Bit definition for BKPC_PCR register ************************/ - -#define BKPC_PCR_BORS_POSS 1U -#define BKPC_PCR_BORS_POSE 4U -#define BKPC_PCR_BORS_MSK BITS(BKPC_PCR_BORS_POSS,BKPC_PCR_BORS_POSE) - -#define BKPC_PCR_BOREN_POS 0U -#define BKPC_PCR_BOREN_MSK BIT(BKPC_PCR_BOREN_POS) - typedef struct { __IO uint32_t PROT; __IO uint32_t CR; __IO uint32_t PCCR; - __IO uint32_t PCR; } BKPC_TypeDef; /****************** Bit definition for PMU_CR register ************************/ @@ -1847,18 +1837,18 @@ typedef struct #define RTC_TAMPCON_TAMPTS_POS 16U #define RTC_TAMPCON_TAMPTS_MSK BIT(RTC_TAMPCON_TAMPTS_POS) -#define RTC_TAMPCON_TAMP2LV_POS 9U -#define RTC_TAMPCON_TAMP2LV_MSK BIT(RTC_TAMPCON_TAMP2LV_POS) - -#define RTC_TAMPCON_TAMP2EN_POS 8U -#define RTC_TAMPCON_TAMP2EN_MSK BIT(RTC_TAMPCON_TAMP2EN_POS) - -#define RTC_TAMPCON_TAMP1LV_POS 1U +#define RTC_TAMPCON_TAMP1LV_POS 9U #define RTC_TAMPCON_TAMP1LV_MSK BIT(RTC_TAMPCON_TAMP1LV_POS) -#define RTC_TAMPCON_TAMP1EN_POS 0U +#define RTC_TAMPCON_TAMP1EN_POS 8U #define RTC_TAMPCON_TAMP1EN_MSK BIT(RTC_TAMPCON_TAMP1EN_POS) +#define RTC_TAMPCON_TAMP0LV_POS 1U +#define RTC_TAMPCON_TAMP0LV_MSK BIT(RTC_TAMPCON_TAMP0LV_POS) + +#define RTC_TAMPCON_TAMP0EN_POS 0U +#define RTC_TAMPCON_TAMP0EN_MSK BIT(RTC_TAMPCON_TAMP0EN_POS) + /****************** Bit definition for RTC_TIME register ************************/ #define RTC_TIME_PM_POS 22U @@ -2151,12 +2141,12 @@ typedef struct #define RTC_IER_RSC_POS 16U #define RTC_IER_RSC_MSK BIT(RTC_IER_RSC_POS) -#define RTC_IER_TAMP2_POS 13U -#define RTC_IER_TAMP2_MSK BIT(RTC_IER_TAMP2_POS) - -#define RTC_IER_TAMP1_POS 12U +#define RTC_IER_TAMP1_POS 13U #define RTC_IER_TAMP1_MSK BIT(RTC_IER_TAMP1_POS) +#define RTC_IER_TAMP0_POS 12U +#define RTC_IER_TAMP0_MSK BIT(RTC_IER_TAMP0_POS) + #define RTC_IER_TSOV_POS 11U #define RTC_IER_TSOV_MSK BIT(RTC_IER_TSOV_POS) @@ -2204,12 +2194,12 @@ typedef struct #define RTC_IFR_RSCF_POS 16U #define RTC_IFR_RSCF_MSK BIT(RTC_IFR_RSCF_POS) -#define RTC_IFR_TAMP2F_POS 13U -#define RTC_IFR_TAMP2F_MSK BIT(RTC_IFR_TAMP2F_POS) - -#define RTC_IFR_TAMP1F_POS 12U +#define RTC_IFR_TAMP1F_POS 13U #define RTC_IFR_TAMP1F_MSK BIT(RTC_IFR_TAMP1F_POS) +#define RTC_IFR_TAMP0F_POS 12U +#define RTC_IFR_TAMP0F_MSK BIT(RTC_IFR_TAMP0F_POS) + #define RTC_IFR_TSOVF_POS 11U #define RTC_IFR_TSOVF_MSK BIT(RTC_IFR_TSOVF_POS) @@ -2257,17 +2247,17 @@ typedef struct #define RTC_IFCR_RSCFC_POS 16U #define RTC_IFCR_RSCFC_MSK BIT(RTC_IFCR_RSCFC_POS) -#define RTC_IFCR_TAMP2FC_POS 13U -#define RTC_IFCR_TAMP2FC_MSK BIT(RTC_IFCR_TAMP2FC_POS) - -#define RTC_IFCR_TAMP1FC_POS 12U +#define RTC_IFCR_TAMP1FC_POS 13U #define RTC_IFCR_TAMP1FC_MSK BIT(RTC_IFCR_TAMP1FC_POS) +#define RTC_IFCR_TAMP0FC_POS 12U +#define RTC_IFCR_TAMP0FC_MSK BIT(RTC_IFCR_TAMP0FC_POS) + #define RTC_IFCR_TSOVFC_POS 11U #define RTC_IFCR_TSOVFC_MSK BIT(RTC_IFCR_TSOVFC_POS) -#define RTC_IFCR_TSSTC_POS 10U -#define RTC_IFCR_TSSTC_MSK BIT(RTC_IFCR_TSSTC_POS) +#define RTC_IFCR_TSFC_POS 10U +#define RTC_IFCR_TSFC_MSK BIT(RTC_IFCR_TSFC_POS) #define RTC_IFCR_ALMBFC_POS 9U #define RTC_IFCR_ALMBFC_MSK BIT(RTC_IFCR_ALMBFC_POS) @@ -2310,12 +2300,12 @@ typedef struct #define RTC_ISR_RSCF_POS 16U #define RTC_ISR_RSCF_MSK BIT(RTC_ISR_RSCF_POS) -#define RTC_ISR_TAMP2F_POS 13U -#define RTC_ISR_TAMP2F_MSK BIT(RTC_ISR_TAMP2F_POS) - -#define RTC_ISR_TAMP1F_POS 12U +#define RTC_ISR_TAMP1F_POS 13U #define RTC_ISR_TAMP1F_MSK BIT(RTC_ISR_TAMP1F_POS) +#define RTC_ISR_TAMP0F_POS 12U +#define RTC_ISR_TAMP0F_MSK BIT(RTC_ISR_TAMP0F_POS) + #define RTC_ISR_TSOVF_POS 11U #define RTC_ISR_TSOVF_MSK BIT(RTC_ISR_TSOVF_POS) @@ -4361,736 +4351,6 @@ typedef struct __IO uint32_t RT; } I2C_TypeDef; -/****************** Bit definition for CAN_CON register ************************/ - -#define CAN_CON_DBGSTP_POS 16U -#define CAN_CON_DBGSTP_MSK BIT(CAN_CON_DBGSTP_POS) - -#define CAN_CON_RST_POS 15U -#define CAN_CON_RST_MSK BIT(CAN_CON_RST_POS) - -#define CAN_CON_TTCEN_POS 7U -#define CAN_CON_TTCEN_MSK BIT(CAN_CON_TTCEN_POS) - -#define CAN_CON_ABOFFEN_POS 6U -#define CAN_CON_ABOFFEN_MSK BIT(CAN_CON_ABOFFEN_POS) - -#define CAN_CON_AWKEN_POS 5U -#define CAN_CON_AWKEN_MSK BIT(CAN_CON_AWKEN_POS) - -#define CAN_CON_ARTXDIS_POS 4U -#define CAN_CON_ARTXDIS_MSK BIT(CAN_CON_ARTXDIS_POS) - -#define CAN_CON_RXFOPM_POS 3U -#define CAN_CON_RXFOPM_MSK BIT(CAN_CON_RXFOPM_POS) - -#define CAN_CON_TXMP_POS 2U -#define CAN_CON_TXMP_MSK BIT(CAN_CON_TXMP_POS) - -#define CAN_CON_SLPREQ_POS 1U -#define CAN_CON_SLPREQ_MSK BIT(CAN_CON_SLPREQ_POS) - -#define CAN_CON_INIREQ_POS 0U -#define CAN_CON_INIREQ_MSK BIT(CAN_CON_INIREQ_POS) - -/****************** Bit definition for CAN_STAT register ************************/ - -#define CAN_STAT_RX_POS 11U -#define CAN_STAT_RX_MSK BIT(CAN_STAT_RX_POS) - -#define CAN_STAT_PRESMP_POS 10U -#define CAN_STAT_PRESMP_MSK BIT(CAN_STAT_PRESMP_POS) - -#define CAN_STAT_RXSTAT_POS 9U -#define CAN_STAT_RXSTAT_MSK BIT(CAN_STAT_RXSTAT_POS) - -#define CAN_STAT_TXSTAT_POS 8U -#define CAN_STAT_TXSTAT_MSK BIT(CAN_STAT_TXSTAT_POS) - -#define CAN_STAT_SLPIF_POS 4U -#define CAN_STAT_SLPIF_MSK BIT(CAN_STAT_SLPIF_POS) - -#define CAN_STAT_WKIF_POS 3U -#define CAN_STAT_WKIF_MSK BIT(CAN_STAT_WKIF_POS) - -#define CAN_STAT_ERRIF_POS 2U -#define CAN_STAT_ERRIF_MSK BIT(CAN_STAT_ERRIF_POS) - -#define CAN_STAT_SLPSTAT_POS 1U -#define CAN_STAT_SLPSTAT_MSK BIT(CAN_STAT_SLPSTAT_POS) - -#define CAN_STAT_INISTAT_POS 0U -#define CAN_STAT_INISTAT_MSK BIT(CAN_STAT_INISTAT_POS) - -/****************** Bit definition for CAN_IFC register ************************/ - -#define CAN_IFC_SLPIFC_POS 4U -#define CAN_IFC_SLPIFC_MSK BIT(CAN_IFC_SLPIFC_POS) - -#define CAN_IFC_WKIFC_POS 3U -#define CAN_IFC_WKIFC_MSK BIT(CAN_IFC_WKIFC_POS) - -#define CAN_IFC_ERRIFC_POS 2U -#define CAN_IFC_ERRIFC_MSK BIT(CAN_IFC_ERRIFC_POS) - -/****************** Bit definition for CAN_TXSTAT register ************************/ - -#define CAN_TXSTAT_TXM2LPF_POS 31U -#define CAN_TXSTAT_TXM2LPF_MSK BIT(CAN_TXSTAT_TXM2LPF_POS) - -#define CAN_TXSTAT_TXM1LPF_POS 30U -#define CAN_TXSTAT_TXM1LPF_MSK BIT(CAN_TXSTAT_TXM1LPF_POS) - -#define CAN_TXSTAT_TXM0LPF_POS 29U -#define CAN_TXSTAT_TXM0LPF_MSK BIT(CAN_TXSTAT_TXM0LPF_POS) - -#define CAN_TXSTAT_TXM2EF_POS 28U -#define CAN_TXSTAT_TXM2EF_MSK BIT(CAN_TXSTAT_TXM2EF_POS) - -#define CAN_TXSTAT_TXM1EF_POS 27U -#define CAN_TXSTAT_TXM1EF_MSK BIT(CAN_TXSTAT_TXM1EF_POS) - -#define CAN_TXSTAT_TXM0EF_POS 26U -#define CAN_TXSTAT_TXM0EF_MSK BIT(CAN_TXSTAT_TXM0EF_POS) - -#define CAN_TXSTAT_CODE_POSS 24U -#define CAN_TXSTAT_CODE_POSE 25U -#define CAN_TXSTAT_CODE_MSK BITS(CAN_TXSTAT_CODE_POSS,CAN_TXSTAT_CODE_POSE) - -#define CAN_TXSTAT_M2STPREQ_POS 23U -#define CAN_TXSTAT_M2STPREQ_MSK BIT(CAN_TXSTAT_M2STPREQ_POS) - -#define CAN_TXSTAT_M2TXERR_POS 19U -#define CAN_TXSTAT_M2TXERR_MSK BIT(CAN_TXSTAT_M2TXERR_POS) - -#define CAN_TXSTAT_M2ARBLST_POS 18U -#define CAN_TXSTAT_M2ARBLST_MSK BIT(CAN_TXSTAT_M2ARBLST_POS) - -#define CAN_TXSTAT_M2TXC_POS 17U -#define CAN_TXSTAT_M2TXC_MSK BIT(CAN_TXSTAT_M2TXC_POS) - -#define CAN_TXSTAT_M2REQC_POS 16U -#define CAN_TXSTAT_M2REQC_MSK BIT(CAN_TXSTAT_M2REQC_POS) - -#define CAN_TXSTAT_M1STPREQ_POS 15U -#define CAN_TXSTAT_M1STPREQ_MSK BIT(CAN_TXSTAT_M1STPREQ_POS) - -#define CAN_TXSTAT_M1TXERR_POS 11U -#define CAN_TXSTAT_M1TXERR_MSK BIT(CAN_TXSTAT_M1TXERR_POS) - -#define CAN_TXSTAT_M1ARBLST_POS 10U -#define CAN_TXSTAT_M1ARBLST_MSK BIT(CAN_TXSTAT_M1ARBLST_POS) - -#define CAN_TXSTAT_M1TXC_POS 9U -#define CAN_TXSTAT_M1TXC_MSK BIT(CAN_TXSTAT_M1TXC_POS) - -#define CAN_TXSTAT_M1REQC_POS 8U -#define CAN_TXSTAT_M1REQC_MSK BIT(CAN_TXSTAT_M1REQC_POS) - -#define CAN_TXSTAT_M0STPREQ_POS 7U -#define CAN_TXSTAT_M0STPREQ_MSK BIT(CAN_TXSTAT_M0STPREQ_POS) - -#define CAN_TXSTAT_M0TXERR_POS 3U -#define CAN_TXSTAT_M0TXERR_MSK BIT(CAN_TXSTAT_M0TXERR_POS) - -#define CAN_TXSTAT_M0ARBLST_POS 2U -#define CAN_TXSTAT_M0ARBLST_MSK BIT(CAN_TXSTAT_M0ARBLST_POS) - -#define CAN_TXSTAT_M0TXC_POS 1U -#define CAN_TXSTAT_M0TXC_MSK BIT(CAN_TXSTAT_M0TXC_POS) - -#define CAN_TXSTAT_M0REQC_POS 0U -#define CAN_TXSTAT_M0REQC_MSK BIT(CAN_TXSTAT_M0REQC_POS) - -/****************** Bit definition for CAN_TXSTATC register ************************/ - -#define CAN_TXSTATC_M2TXERR_POS 19U -#define CAN_TXSTATC_M2TXERR_MSK BIT(CAN_TXSTATC_M2TXERR_POS) - -#define CAN_TXSTATC_M2ARBLST_POS 18U -#define CAN_TXSTATC_M2ARBLST_MSK BIT(CAN_TXSTATC_M2ARBLST_POS) - -#define CAN_TXSTATC_M2TXC_POS 17U -#define CAN_TXSTATC_M2TXC_MSK BIT(CAN_TXSTATC_M2TXC_POS) - -#define CAN_TXSTATC_M2REQC_POS 16U -#define CAN_TXSTATC_M2REQC_MSK BIT(CAN_TXSTATC_M2REQC_POS) - -#define CAN_TXSTATC_M1TXERR_POS 11U -#define CAN_TXSTATC_M1TXERR_MSK BIT(CAN_TXSTATC_M1TXERR_POS) - -#define CAN_TXSTATC_M1ARBLST_POS 10U -#define CAN_TXSTATC_M1ARBLST_MSK BIT(CAN_TXSTATC_M1ARBLST_POS) - -#define CAN_TXSTATC_M1TXC_POS 9U -#define CAN_TXSTATC_M1TXC_MSK BIT(CAN_TXSTATC_M1TXC_POS) - -#define CAN_TXSTATC_M1REQC_POS 8U -#define CAN_TXSTATC_M1REQC_MSK BIT(CAN_TXSTATC_M1REQC_POS) - -#define CAN_TXSTATC_M0TXERR_POS 3U -#define CAN_TXSTATC_M0TXERR_MSK BIT(CAN_TXSTATC_M0TXERR_POS) - -#define CAN_TXSTATC_M0ARBLST_POS 2U -#define CAN_TXSTATC_M0ARBLST_MSK BIT(CAN_TXSTATC_M0ARBLST_POS) - -#define CAN_TXSTATC_M0TXC_POS 1U -#define CAN_TXSTATC_M0TXC_MSK BIT(CAN_TXSTATC_M0TXC_POS) - -#define CAN_TXSTATC_M0REQC_POS 0U -#define CAN_TXSTATC_M0REQC_MSK BIT(CAN_TXSTATC_M0REQC_POS) - -/****************** Bit definition for CAN_RXF0 register ************************/ - -#define CAN_RXF0_FREE_POS 5U -#define CAN_RXF0_FREE_MSK BIT(CAN_RXF0_FREE_POS) - -#define CAN_RXF0_OVR_POS 4U -#define CAN_RXF0_OVR_MSK BIT(CAN_RXF0_OVR_POS) - -#define CAN_RXF0_FULL_POS 3U -#define CAN_RXF0_FULL_MSK BIT(CAN_RXF0_FULL_POS) - -#define CAN_RXF0_PEND_POSS 0U -#define CAN_RXF0_PEND_POSE 1U -#define CAN_RXF0_PEND_MSK BITS(CAN_RXF0_PEND_POSS,CAN_RXF0_PEND_POSE) - -/****************** Bit definition for CAN_RXF0C register ************************/ - -#define CAN_RXF0C_OVRC_POS 4U -#define CAN_RXF0C_OVRC_MSK BIT(CAN_RXF0C_OVRC_POS) - -#define CAN_RXF0C_FULLC_POS 3U -#define CAN_RXF0C_FULLC_MSK BIT(CAN_RXF0C_FULLC_POS) - -/****************** Bit definition for CAN_RXF1 register ************************/ - -#define CAN_RXF1_FREE_POS 5U -#define CAN_RXF1_FREE_MSK BIT(CAN_RXF1_FREE_POS) - -#define CAN_RXF1_OVR_POS 4U -#define CAN_RXF1_OVR_MSK BIT(CAN_RXF1_OVR_POS) - -#define CAN_RXF1_FULL_POS 3U -#define CAN_RXF1_FULL_MSK BIT(CAN_RXF1_FULL_POS) - -#define CAN_RXF1_PEND_POSS 0U -#define CAN_RXF1_PEND_POSE 1U -#define CAN_RXF1_PEND_MSK BITS(CAN_RXF1_PEND_POSS,CAN_RXF1_PEND_POSE) - -/****************** Bit definition for CAN_RXF1C register ************************/ - -#define CAN_RXF1C_OVRC_POS 4U -#define CAN_RXF1C_OVRC_MSK BIT(CAN_RXF1C_OVRC_POS) - -#define CAN_RXF1C_FULLC_POS 3U -#define CAN_RXF1C_FULLC_MSK BIT(CAN_RXF1C_FULLC_POS) - -/****************** Bit definition for CAN_IE register ************************/ - -#define CAN_IE_SLPIE_POS 17U -#define CAN_IE_SLPIE_MSK BIT(CAN_IE_SLPIE_POS) - -#define CAN_IE_WKIE_POS 16U -#define CAN_IE_WKIE_MSK BIT(CAN_IE_WKIE_POS) - -#define CAN_IE_ERRIE_POS 15U -#define CAN_IE_ERRIE_MSK BIT(CAN_IE_ERRIE_POS) - -#define CAN_IE_PRERRIE_POS 11U -#define CAN_IE_PRERRIE_MSK BIT(CAN_IE_PRERRIE_POS) - -#define CAN_IE_BOFFIE_POS 10U -#define CAN_IE_BOFFIE_MSK BIT(CAN_IE_BOFFIE_POS) - -#define CAN_IE_PERRIE_POS 9U -#define CAN_IE_PERRIE_MSK BIT(CAN_IE_PERRIE_POS) - -#define CAN_IE_WARNIE_POS 8U -#define CAN_IE_WARNIE_MSK BIT(CAN_IE_WARNIE_POS) - -#define CAN_IE_F1OVRIE_POS 6U -#define CAN_IE_F1OVRIE_MSK BIT(CAN_IE_F1OVRIE_POS) - -#define CAN_IE_F1FULIE_POS 5U -#define CAN_IE_F1FULIE_MSK BIT(CAN_IE_F1FULIE_POS) - -#define CAN_IE_F1PIE_POS 4U -#define CAN_IE_F1PIE_MSK BIT(CAN_IE_F1PIE_POS) - -#define CAN_IE_F0OVRIE_POS 3U -#define CAN_IE_F0OVRIE_MSK BIT(CAN_IE_F0OVRIE_POS) - -#define CAN_IE_F0FULIE_POS 2U -#define CAN_IE_F0FULIE_MSK BIT(CAN_IE_F0FULIE_POS) - -#define CAN_IE_F0PIE_POS 1U -#define CAN_IE_F0PIE_MSK BIT(CAN_IE_F0PIE_POS) - -#define CAN_IE_TXMEIE_POS 0U -#define CAN_IE_TXMEIE_MSK BIT(CAN_IE_TXMEIE_POS) - -/****************** Bit definition for CAN_ERRSTAT register ************************/ - -#define CAN_ERRSTAT_RXERRC_POSS 24U -#define CAN_ERRSTAT_RXERRC_POSE 31U -#define CAN_ERRSTAT_RXERRC_MSK BITS(CAN_ERRSTAT_RXERRC_POSS,CAN_ERRSTAT_RXERRC_POSE) - -#define CAN_ERRSTAT_TXERRC_POSS 16U -#define CAN_ERRSTAT_TXERRC_POSE 23U -#define CAN_ERRSTAT_TXERRC_MSK BITS(CAN_ERRSTAT_TXERRC_POSS,CAN_ERRSTAT_TXERRC_POSE) - -#define CAN_ERRSTAT_PRERRF_POSS 4U -#define CAN_ERRSTAT_PRERRF_POSE 6U -#define CAN_ERRSTAT_PRERRF_MSK BITS(CAN_ERRSTAT_PRERRF_POSS,CAN_ERRSTAT_PRERRF_POSE) - -#define CAN_ERRSTAT_BOFF_POS 2U -#define CAN_ERRSTAT_BOFF_MSK BIT(CAN_ERRSTAT_BOFF_POS) - -#define CAN_ERRSTAT_PERRF_POS 1U -#define CAN_ERRSTAT_PERRF_MSK BIT(CAN_ERRSTAT_PERRF_POS) - -#define CAN_ERRSTAT_WARNF_POS 0U -#define CAN_ERRSTAT_WARNF_MSK BIT(CAN_ERRSTAT_WARNF_POS) - -/****************** Bit definition for CAN_BTIME register ************************/ - -#define CAN_BTIME_SILENT_POS 31U -#define CAN_BTIME_SILENT_MSK BIT(CAN_BTIME_SILENT_POS) - -#define CAN_BTIME_LOOP_POS 30U -#define CAN_BTIME_LOOP_MSK BIT(CAN_BTIME_LOOP_POS) - -#define CAN_BTIME_RESJW_POSS 24U -#define CAN_BTIME_RESJW_POSE 25U -#define CAN_BTIME_RESJW_MSK BITS(CAN_BTIME_RESJW_POSS,CAN_BTIME_RESJW_POSE) - -#define CAN_BTIME_SEG2_POSS 20U -#define CAN_BTIME_SEG2_POSE 22U -#define CAN_BTIME_SEG2_MSK BITS(CAN_BTIME_SEG2_POSS,CAN_BTIME_SEG2_POSE) - -#define CAN_BTIME_SEG1_POSS 16U -#define CAN_BTIME_SEG1_POSE 19U -#define CAN_BTIME_SEG1_MSK BITS(CAN_BTIME_SEG1_POSS,CAN_BTIME_SEG1_POSE) - -#define CAN_BTIME_BPSC_POSS 0U -#define CAN_BTIME_BPSC_POSE 9U -#define CAN_BTIME_BPSC_MSK BITS(CAN_BTIME_BPSC_POSS,CAN_BTIME_BPSC_POSE) - -/****************** Bit definition for CAN_TXID0 register ************************/ - -#define CAN_TXID0_STDID_POSS 21U -#define CAN_TXID0_STDID_POSE 31U -#define CAN_TXID0_STDID_MSK BITS(CAN_TXID0_STDID_POSS,CAN_TXID0_STDID_POSE) - -#define CAN_TXID0_EXID_POSS 3U -#define CAN_TXID0_EXID_POSE 20U -#define CAN_TXID0_EXID_MSK BITS(CAN_TXID0_EXID_POSS,CAN_TXID0_EXID_POSE) - -#define CAN_TXID0_IDE_POS 2U -#define CAN_TXID0_IDE_MSK BIT(CAN_TXID0_IDE_POS) - -#define CAN_TXID0_RTR_POS 1U -#define CAN_TXID0_RTR_MSK BIT(CAN_TXID0_RTR_POS) - -#define CAN_TXID0_TXMREQ_POS 0U -#define CAN_TXID0_TXMREQ_MSK BIT(CAN_TXID0_TXMREQ_POS) - -/****************** Bit definition for CAN_TXFCON0 register ************************/ - -#define CAN_TXFCON0_STAMP_POSS 16U -#define CAN_TXFCON0_STAMP_POSE 31U -#define CAN_TXFCON0_STAMP_MSK BITS(CAN_TXFCON0_STAMP_POSS,CAN_TXFCON0_STAMP_POSE) - -#define CAN_TXFCON0_TXGT_POS 8U -#define CAN_TXFCON0_TXGT_MSK BIT(CAN_TXFCON0_TXGT_POS) - -#define CAN_TXFCON0_DLEN_POSS 0U -#define CAN_TXFCON0_DLEN_POSE 3U -#define CAN_TXFCON0_DLEN_MSK BITS(CAN_TXFCON0_DLEN_POSS,CAN_TXFCON0_DLEN_POSE) - -/****************** Bit definition for CAN_TXDL0 register ************************/ - -#define CAN_TXDL0_BYTE3_POSS 24U -#define CAN_TXDL0_BYTE3_POSE 31U -#define CAN_TXDL0_BYTE3_MSK BITS(CAN_TXDL0_BYTE3_POSS,CAN_TXDL0_BYTE3_POSE) - -#define CAN_TXDL0_BYTE2_POSS 16U -#define CAN_TXDL0_BYTE2_POSE 23U -#define CAN_TXDL0_BYTE2_MSK BITS(CAN_TXDL0_BYTE2_POSS,CAN_TXDL0_BYTE2_POSE) - -#define CAN_TXDL0_BYTE1_POSS 8U -#define CAN_TXDL0_BYTE1_POSE 15U -#define CAN_TXDL0_BYTE1_MSK BITS(CAN_TXDL0_BYTE1_POSS,CAN_TXDL0_BYTE1_POSE) - -#define CAN_TXDL0_BYTE0_POSS 0U -#define CAN_TXDL0_BYTE0_POSE 7U -#define CAN_TXDL0_BYTE0_MSK BITS(CAN_TXDL0_BYTE0_POSS,CAN_TXDL0_BYTE0_POSE) - -/****************** Bit definition for CAN_TXDH0 register ************************/ - -#define CAN_TXDH0_BYTE7_POSS 24U -#define CAN_TXDH0_BYTE7_POSE 31U -#define CAN_TXDH0_BYTE7_MSK BITS(CAN_TXDH0_BYTE7_POSS,CAN_TXDH0_BYTE7_POSE) - -#define CAN_TXDH0_BYTE6_POSS 16U -#define CAN_TXDH0_BYTE6_POSE 23U -#define CAN_TXDH0_BYTE6_MSK BITS(CAN_TXDH0_BYTE6_POSS,CAN_TXDH0_BYTE6_POSE) - -#define CAN_TXDH0_BYTE5_POSS 8U -#define CAN_TXDH0_BYTE5_POSE 15U -#define CAN_TXDH0_BYTE5_MSK BITS(CAN_TXDH0_BYTE5_POSS,CAN_TXDH0_BYTE5_POSE) - -#define CAN_TXDH0_BYTE4_POSS 0U -#define CAN_TXDH0_BYTE4_POSE 7U -#define CAN_TXDH0_BYTE4_MSK BITS(CAN_TXDH0_BYTE4_POSS,CAN_TXDH0_BYTE4_POSE) - -/****************** Bit definition for CAN_TXID1 register ************************/ - -#define CAN_TXID1_STDID_POSS 21U -#define CAN_TXID1_STDID_POSE 31U -#define CAN_TXID1_STDID_MSK BITS(CAN_TXID1_STDID_POSS,CAN_TXID1_STDID_POSE) - -#define CAN_TXID1_EXID_POSS 3U -#define CAN_TXID1_EXID_POSE 20U -#define CAN_TXID1_EXID_MSK BITS(CAN_TXID1_EXID_POSS,CAN_TXID1_EXID_POSE) - -#define CAN_TXID1_IDE_POS 2U -#define CAN_TXID1_IDE_MSK BIT(CAN_TXID1_IDE_POS) - -#define CAN_TXID1_RTR_POS 1U -#define CAN_TXID1_RTR_MSK BIT(CAN_TXID1_RTR_POS) - -#define CAN_TXID1_TXMREQ_POS 0U -#define CAN_TXID1_TXMREQ_MSK BIT(CAN_TXID1_TXMREQ_POS) - -/****************** Bit definition for CAN_TXFCON1 register ************************/ - -#define CAN_TXFCON1_STAMP_POSS 16U -#define CAN_TXFCON1_STAMP_POSE 31U -#define CAN_TXFCON1_STAMP_MSK BITS(CAN_TXFCON1_STAMP_POSS,CAN_TXFCON1_STAMP_POSE) - -#define CAN_TXFCON1_TXGT_POS 8U -#define CAN_TXFCON1_TXGT_MSK BIT(CAN_TXFCON1_TXGT_POS) - -#define CAN_TXFCON1_DLEN_POSS 0U -#define CAN_TXFCON1_DLEN_POSE 3U -#define CAN_TXFCON1_DLEN_MSK BITS(CAN_TXFCON1_DLEN_POSS,CAN_TXFCON1_DLEN_POSE) - -/****************** Bit definition for CAN_TXDL1 register ************************/ - -#define CAN_TXDL1_BYTE3_POSS 24U -#define CAN_TXDL1_BYTE3_POSE 31U -#define CAN_TXDL1_BYTE3_MSK BITS(CAN_TXDL1_BYTE3_POSS,CAN_TXDL1_BYTE3_POSE) - -#define CAN_TXDL1_BYTE2_POSS 16U -#define CAN_TXDL1_BYTE2_POSE 23U -#define CAN_TXDL1_BYTE2_MSK BITS(CAN_TXDL1_BYTE2_POSS,CAN_TXDL1_BYTE2_POSE) - -#define CAN_TXDL1_BYTE1_POSS 8U -#define CAN_TXDL1_BYTE1_POSE 15U -#define CAN_TXDL1_BYTE1_MSK BITS(CAN_TXDL1_BYTE1_POSS,CAN_TXDL1_BYTE1_POSE) - -#define CAN_TXDL1_BYTE0_POSS 0U -#define CAN_TXDL1_BYTE0_POSE 7U -#define CAN_TXDL1_BYTE0_MSK BITS(CAN_TXDL1_BYTE0_POSS,CAN_TXDL1_BYTE0_POSE) - -/****************** Bit definition for CAN_TXDH1 register ************************/ - -#define CAN_TXDH1_BYTE7_POSS 24U -#define CAN_TXDH1_BYTE7_POSE 31U -#define CAN_TXDH1_BYTE7_MSK BITS(CAN_TXDH1_BYTE7_POSS,CAN_TXDH1_BYTE7_POSE) - -#define CAN_TXDH1_BYTE6_POSS 16U -#define CAN_TXDH1_BYTE6_POSE 23U -#define CAN_TXDH1_BYTE6_MSK BITS(CAN_TXDH1_BYTE6_POSS,CAN_TXDH1_BYTE6_POSE) - -#define CAN_TXDH1_BYTE5_POSS 8U -#define CAN_TXDH1_BYTE5_POSE 15U -#define CAN_TXDH1_BYTE5_MSK BITS(CAN_TXDH1_BYTE5_POSS,CAN_TXDH1_BYTE5_POSE) - -#define CAN_TXDH1_BYTE4_POSS 0U -#define CAN_TXDH1_BYTE4_POSE 7U -#define CAN_TXDH1_BYTE4_MSK BITS(CAN_TXDH1_BYTE4_POSS,CAN_TXDH1_BYTE4_POSE) - -/****************** Bit definition for CAN_TXID2 register ************************/ - -#define CAN_TXID2_STDID_POSS 21U -#define CAN_TXID2_STDID_POSE 31U -#define CAN_TXID2_STDID_MSK BITS(CAN_TXID2_STDID_POSS,CAN_TXID2_STDID_POSE) - -#define CAN_TXID2_EXID_POSS 3U -#define CAN_TXID2_EXID_POSE 20U -#define CAN_TXID2_EXID_MSK BITS(CAN_TXID2_EXID_POSS,CAN_TXID2_EXID_POSE) - -#define CAN_TXID2_IDE_POS 2U -#define CAN_TXID2_IDE_MSK BIT(CAN_TXID2_IDE_POS) - -#define CAN_TXID2_RTR_POS 1U -#define CAN_TXID2_RTR_MSK BIT(CAN_TXID2_RTR_POS) - -#define CAN_TXID2_TXMREQ_POS 0U -#define CAN_TXID2_TXMREQ_MSK BIT(CAN_TXID2_TXMREQ_POS) - -/****************** Bit definition for CAN_TXFCON2 register ************************/ - -#define CAN_TXFCON2_STAMP_POSS 16U -#define CAN_TXFCON2_STAMP_POSE 31U -#define CAN_TXFCON2_STAMP_MSK BITS(CAN_TXFCON2_STAMP_POSS,CAN_TXFCON2_STAMP_POSE) - -#define CAN_TXFCON2_TXGT_POS 8U -#define CAN_TXFCON2_TXGT_MSK BIT(CAN_TXFCON2_TXGT_POS) - -#define CAN_TXFCON2_DLEN_POSS 0U -#define CAN_TXFCON2_DLEN_POSE 3U -#define CAN_TXFCON2_DLEN_MSK BITS(CAN_TXFCON2_DLEN_POSS,CAN_TXFCON2_DLEN_POSE) - -/****************** Bit definition for CAN_TXDL2 register ************************/ - -#define CAN_TXDL2_BYTE3_POSS 24U -#define CAN_TXDL2_BYTE3_POSE 31U -#define CAN_TXDL2_BYTE3_MSK BITS(CAN_TXDL2_BYTE3_POSS,CAN_TXDL2_BYTE3_POSE) - -#define CAN_TXDL2_BYTE2_POSS 16U -#define CAN_TXDL2_BYTE2_POSE 23U -#define CAN_TXDL2_BYTE2_MSK BITS(CAN_TXDL2_BYTE2_POSS,CAN_TXDL2_BYTE2_POSE) - -#define CAN_TXDL2_BYTE1_POSS 8U -#define CAN_TXDL2_BYTE1_POSE 15U -#define CAN_TXDL2_BYTE1_MSK BITS(CAN_TXDL2_BYTE1_POSS,CAN_TXDL2_BYTE1_POSE) - -#define CAN_TXDL2_BYTE0_POSS 0U -#define CAN_TXDL2_BYTE0_POSE 7U -#define CAN_TXDL2_BYTE0_MSK BITS(CAN_TXDL2_BYTE0_POSS,CAN_TXDL2_BYTE0_POSE) - -/****************** Bit definition for CAN_TXDH2 register ************************/ - -#define CAN_TXDH2_BYTE7_POSS 24U -#define CAN_TXDH2_BYTE7_POSE 31U -#define CAN_TXDH2_BYTE7_MSK BITS(CAN_TXDH2_BYTE7_POSS,CAN_TXDH2_BYTE7_POSE) - -#define CAN_TXDH2_BYTE6_POSS 16U -#define CAN_TXDH2_BYTE6_POSE 23U -#define CAN_TXDH2_BYTE6_MSK BITS(CAN_TXDH2_BYTE6_POSS,CAN_TXDH2_BYTE6_POSE) - -#define CAN_TXDH2_BYTE5_POSS 8U -#define CAN_TXDH2_BYTE5_POSE 15U -#define CAN_TXDH2_BYTE5_MSK BITS(CAN_TXDH2_BYTE5_POSS,CAN_TXDH2_BYTE5_POSE) - -#define CAN_TXDH2_BYTE4_POSS 0U -#define CAN_TXDH2_BYTE4_POSE 7U -#define CAN_TXDH2_BYTE4_MSK BITS(CAN_TXDH2_BYTE4_POSS,CAN_TXDH2_BYTE4_POSE) - -/****************** Bit definition for CAN_RXF0ID register ************************/ - -#define CAN_RXF0ID_STDID_POSS 21U -#define CAN_RXF0ID_STDID_POSE 31U -#define CAN_RXF0ID_STDID_MSK BITS(CAN_RXF0ID_STDID_POSS,CAN_RXF0ID_STDID_POSE) - -#define CAN_RXF0ID_EXID_POSS 3U -#define CAN_RXF0ID_EXID_POSE 20U -#define CAN_RXF0ID_EXID_MSK BITS(CAN_RXF0ID_EXID_POSS,CAN_RXF0ID_EXID_POSE) - -#define CAN_RXF0ID_IDE_POS 2U -#define CAN_RXF0ID_IDE_MSK BIT(CAN_RXF0ID_IDE_POS) - -#define CAN_RXF0ID_RTR_POS 1U -#define CAN_RXF0ID_RTR_MSK BIT(CAN_RXF0ID_RTR_POS) - -/****************** Bit definition for CAN_RXF0INF register ************************/ - -#define CAN_RXF0INF_STAMP_POSS 16U -#define CAN_RXF0INF_STAMP_POSE 31U -#define CAN_RXF0INF_STAMP_MSK BITS(CAN_RXF0INF_STAMP_POSS,CAN_RXF0INF_STAMP_POSE) - -#define CAN_RXF0INF_FLTIDX_POSS 8U -#define CAN_RXF0INF_FLTIDX_POSE 15U -#define CAN_RXF0INF_FLTIDX_MSK BITS(CAN_RXF0INF_FLTIDX_POSS,CAN_RXF0INF_FLTIDX_POSE) - -#define CAN_RXF0INF_DLEN_POSS 0U -#define CAN_RXF0INF_DLEN_POSE 3U -#define CAN_RXF0INF_DLEN_MSK BITS(CAN_RXF0INF_DLEN_POSS,CAN_RXF0INF_DLEN_POSE) - -/****************** Bit definition for CAN_RXF0DL register ************************/ - -#define CAN_RXF0DL_BYTE3_POSS 24U -#define CAN_RXF0DL_BYTE3_POSE 31U -#define CAN_RXF0DL_BYTE3_MSK BITS(CAN_RXF0DL_BYTE3_POSS,CAN_RXF0DL_BYTE3_POSE) - -#define CAN_RXF0DL_BYTE2_POSS 16U -#define CAN_RXF0DL_BYTE2_POSE 23U -#define CAN_RXF0DL_BYTE2_MSK BITS(CAN_RXF0DL_BYTE2_POSS,CAN_RXF0DL_BYTE2_POSE) - -#define CAN_RXF0DL_BYTE1_POSS 8U -#define CAN_RXF0DL_BYTE1_POSE 15U -#define CAN_RXF0DL_BYTE1_MSK BITS(CAN_RXF0DL_BYTE1_POSS,CAN_RXF0DL_BYTE1_POSE) - -#define CAN_RXF0DL_BYTE0_POSS 0U -#define CAN_RXF0DL_BYTE0_POSE 7U -#define CAN_RXF0DL_BYTE0_MSK BITS(CAN_RXF0DL_BYTE0_POSS,CAN_RXF0DL_BYTE0_POSE) - -/****************** Bit definition for CAN_RXF0DH register ************************/ - -#define CAN_RXF0DH_BYTE7_POSS 24U -#define CAN_RXF0DH_BYTE7_POSE 31U -#define CAN_RXF0DH_BYTE7_MSK BITS(CAN_RXF0DH_BYTE7_POSS,CAN_RXF0DH_BYTE7_POSE) - -#define CAN_RXF0DH_BYTE6_POSS 16U -#define CAN_RXF0DH_BYTE6_POSE 23U -#define CAN_RXF0DH_BYTE6_MSK BITS(CAN_RXF0DH_BYTE6_POSS,CAN_RXF0DH_BYTE6_POSE) - -#define CAN_RXF0DH_BYTE5_POSS 8U -#define CAN_RXF0DH_BYTE5_POSE 15U -#define CAN_RXF0DH_BYTE5_MSK BITS(CAN_RXF0DH_BYTE5_POSS,CAN_RXF0DH_BYTE5_POSE) - -#define CAN_RXF0DH_BYTE4_POSS 0U -#define CAN_RXF0DH_BYTE4_POSE 7U -#define CAN_RXF0DH_BYTE4_MSK BITS(CAN_RXF0DH_BYTE4_POSS,CAN_RXF0DH_BYTE4_POSE) - -/****************** Bit definition for CAN_RXF1ID register ************************/ - -#define CAN_RXF1ID_STDID_POSS 21U -#define CAN_RXF1ID_STDID_POSE 31U -#define CAN_RXF1ID_STDID_MSK BITS(CAN_RXF1ID_STDID_POSS,CAN_RXF1ID_STDID_POSE) - -#define CAN_RXF1ID_EXID_POSS 3U -#define CAN_RXF1ID_EXID_POSE 20U -#define CAN_RXF1ID_EXID_MSK BITS(CAN_RXF1ID_EXID_POSS,CAN_RXF1ID_EXID_POSE) - -#define CAN_RXF1ID_IDE_POS 2U -#define CAN_RXF1ID_IDE_MSK BIT(CAN_RXF1ID_IDE_POS) - -#define CAN_RXF1ID_RTR_POS 1U -#define CAN_RXF1ID_RTR_MSK BIT(CAN_RXF1ID_RTR_POS) - -/****************** Bit definition for CAN_RXF1INF register ************************/ - -#define CAN_RXF1INF_STAMP_POSS 16U -#define CAN_RXF1INF_STAMP_POSE 31U -#define CAN_RXF1INF_STAMP_MSK BITS(CAN_RXF1INF_STAMP_POSS,CAN_RXF1INF_STAMP_POSE) - -#define CAN_RXF1INF_FLTIDX_POSS 8U -#define CAN_RXF1INF_FLTIDX_POSE 15U -#define CAN_RXF1INF_FLTIDX_MSK BITS(CAN_RXF1INF_FLTIDX_POSS,CAN_RXF1INF_FLTIDX_POSE) - -#define CAN_RXF1INF_DLEN_POSS 0U -#define CAN_RXF1INF_DLEN_POSE 3U -#define CAN_RXF1INF_DLEN_MSK BITS(CAN_RXF1INF_DLEN_POSS,CAN_RXF1INF_DLEN_POSE) - -/****************** Bit definition for CAN_RXF1DL register ************************/ - -#define CAN_RXF1DL_BYTE3_POSS 24U -#define CAN_RXF1DL_BYTE3_POSE 31U -#define CAN_RXF1DL_BYTE3_MSK BITS(CAN_RXF1DL_BYTE3_POSS,CAN_RXF1DL_BYTE3_POSE) - -#define CAN_RXF1DL_BYTE2_POSS 16U -#define CAN_RXF1DL_BYTE2_POSE 23U -#define CAN_RXF1DL_BYTE2_MSK BITS(CAN_RXF1DL_BYTE2_POSS,CAN_RXF1DL_BYTE2_POSE) - -#define CAN_RXF1DL_BYTE1_POSS 8U -#define CAN_RXF1DL_BYTE1_POSE 15U -#define CAN_RXF1DL_BYTE1_MSK BITS(CAN_RXF1DL_BYTE1_POSS,CAN_RXF1DL_BYTE1_POSE) - -#define CAN_RXF1DL_BYTE0_POSS 0U -#define CAN_RXF1DL_BYTE0_POSE 7U -#define CAN_RXF1DL_BYTE0_MSK BITS(CAN_RXF1DL_BYTE0_POSS,CAN_RXF1DL_BYTE0_POSE) - -/****************** Bit definition for CAN_RXF1DH register ************************/ - -#define CAN_RXF1DH_BYTE7_POSS 24U -#define CAN_RXF1DH_BYTE7_POSE 31U -#define CAN_RXF1DH_BYTE7_MSK BITS(CAN_RXF1DH_BYTE7_POSS,CAN_RXF1DH_BYTE7_POSE) - -#define CAN_RXF1DH_BYTE6_POSS 16U -#define CAN_RXF1DH_BYTE6_POSE 23U -#define CAN_RXF1DH_BYTE6_MSK BITS(CAN_RXF1DH_BYTE6_POSS,CAN_RXF1DH_BYTE6_POSE) - -#define CAN_RXF1DH_BYTE5_POSS 8U -#define CAN_RXF1DH_BYTE5_POSE 15U -#define CAN_RXF1DH_BYTE5_MSK BITS(CAN_RXF1DH_BYTE5_POSS,CAN_RXF1DH_BYTE5_POSE) - -#define CAN_RXF1DH_BYTE4_POSS 0U -#define CAN_RXF1DH_BYTE4_POSE 7U -#define CAN_RXF1DH_BYTE4_MSK BITS(CAN_RXF1DH_BYTE4_POSS,CAN_RXF1DH_BYTE4_POSE) - -/****************** Bit definition for CAN_FLTCON register ************************/ - -#define CAN_FLTCON_FLTINI_POS 0U -#define CAN_FLTCON_FLTINI_MSK BIT(CAN_FLTCON_FLTINI_POS) - -/****************** Bit definition for CAN_FLTM register ************************/ - -#define CAN_FLTM_MOD_POSS 0U -#define CAN_FLTM_MOD_POSE 13U -#define CAN_FLTM_MOD_MSK BITS(CAN_FLTM_MOD_POSS,CAN_FLTM_MOD_POSE) - -/****************** Bit definition for CAN_FLTWS register ************************/ - -#define CAN_FLTWS_SEL_POSS 0U -#define CAN_FLTWS_SEL_POSE 13U -#define CAN_FLTWS_SEL_MSK BITS(CAN_FLTWS_SEL_POSS,CAN_FLTWS_SEL_POSE) - -/****************** Bit definition for CAN_FLTAS register ************************/ - -#define CAN_FLTAS_ASSIGN_POSS 0U -#define CAN_FLTAS_ASSIGN_POSE 13U -#define CAN_FLTAS_ASSIGN_MSK BITS(CAN_FLTAS_ASSIGN_POSS,CAN_FLTAS_ASSIGN_POSE) - -/****************** Bit definition for CAN_FLTGO register ************************/ - -#define CAN_FLTGO_GO_POSS 0U -#define CAN_FLTGO_GO_POSE 13U -#define CAN_FLTGO_GO_MSK BITS(CAN_FLTGO_GO_POSS,CAN_FLTGO_GO_POSE) - -typedef struct { - __IO uint32_t TXID; - __IO uint32_t TXFCON; - __IO uint32_t TXDL; - __IO uint32_t TXDH; -} CAN_TxMailBox_Typedef; - -typedef struct { - __IO uint32_t RXFID; - __IO uint32_t RXFINF; - __IO uint32_t RXFDL; - __IO uint32_t RXFDH; -} CAN_RxFIFO_Typedef; - -typedef struct { - __IO uint32_t FLT1; - __IO uint32_t FLT2; -} CAN_Filter_Typedef; - -typedef struct -{ - __IO uint32_t CON; - __I uint32_t STAT; - __O uint32_t IFC; - __IO uint32_t TXSTAT; - __O uint32_t TXSTATC; - __IO uint32_t RXF0; - __O uint32_t RXF0C; - __IO uint32_t RXF1; - __O uint32_t RXF1C; - __IO uint32_t IE; - __IO uint32_t ERRSTAT; - __IO uint32_t BTIME; - uint32_t RESERVED0[84] ; - CAN_TxMailBox_Typedef TxMailBox[3]; - CAN_RxFIFO_Typedef RxFIFO[2]; - uint32_t RESERVED1[12] ; - __IO uint32_t FLTCON; - __IO uint32_t FLTM; - uint32_t RESERVED2 ; - __IO uint32_t FLTWS; - uint32_t RESERVED3 ; - __IO uint32_t FLTAS; - uint32_t RESERVED4 ; - __IO uint32_t FLTGO; - uint32_t RESERVED5[8] ; - CAN_Filter_Typedef Filter[14]; -} CAN_TypeDef; - /****************** Bit definition for CRC_CR register ************************/ #define CRC_CR_BYTORD_POS 24U #define CRC_CR_BYTORD_MSK BIT(CRC_CR_BYTORD_POS) @@ -6523,20 +5783,16 @@ typedef struct #define USART1_BASE (APB1_BASE + 0x5400) #define SPI0_BASE (APB1_BASE + 0x6000) #define SPI1_BASE (APB1_BASE + 0x6400) -#define SPI2_BASE (APB1_BASE + 0x6800) #define I2C0_BASE (APB1_BASE + 0x8000) #define I2C1_BASE (APB1_BASE + 0x8400) -#define CAN0_BASE (APB1_BASE + 0xB000) #define DMA0_BASE (APB1_BASE + 0xC000) /* APB2 peripherals Base Address */ #define LPTIM0_BASE (APB2_BASE + 0x0000) #define LPUART0_BASE (APB2_BASE + 0x1000) #define ADC0_BASE (APB2_BASE + 0x2000) -#define ADC1_BASE (APB2_BASE + 0x2400) #define ACMP0_BASE (APB2_BASE + 0x3000) #define ACMP1_BASE (APB2_BASE + 0x3400) -#define OPAMP_BASE (APB2_BASE + 0x4000) #define DAC0_BASE (APB2_BASE + 0x5000) #define WWDT_BASE (APB2_BASE + 0x6000) #define IWDT_BASE (APB2_BASE + 0x6400) @@ -6584,21 +5840,16 @@ typedef struct #define USART1 ((USART_TypeDef *)USART1_BASE) #define SPI0 ((SPI_TypeDef *)SPI0_BASE) #define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define SPI2 ((SPI_TypeDef *)SPI2_BASE) #define I2C0 ((I2C_TypeDef *)I2C0_BASE) #define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define CAN0 ((CAN_TypeDef *)CAN0_BASE) #define DMA0 ((DMA_TypeDef *)DMA0_BASE) /* APB2 peripherals */ #define LPTIM0 ((LPTIM_TypeDef *)LPTIM0_BASE) #define LPUART0 ((LPUART_TypeDef *)LPUART0_BASE) #define ADC0 ((ADC_TypeDef *)ADC0_BASE) -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) #define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) #define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) -#define OPAMP ((OPAMP_TypeDef *)OPAMP_BASE) -#define DAC0 ((DAC_TypeDef *)DAC0_BASE) #define WWDT ((WWDT_TypeDef *)WWDT_BASE) #define IWDT ((IWDT_TypeDef *)IWDT_BASE) #define LCD ((LCD_TypeDef *)LCD_BASE) diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/EASTSOFT_ES32F033x_ALD.chm b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/EASTSOFT_ES32F033x_ALD.chm new file mode 100644 index 0000000000000000000000000000000000000000..9f5df67080cd943183ad6f0c3d781848c6072fb5 Binary files /dev/null and b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/EASTSOFT_ES32F033x_ALD.chm differ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_acmp.h index 452deaf516b8b6506cc0d1493de5f50411737b21..2bbe7437d0e4485ff9e26c63e18018eef8431a6c 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_acmp.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_acmp.h @@ -18,7 +18,7 @@ #define __ALD_ACMP_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -38,187 +38,171 @@ extern "C" { /** * @brief Acmp interrupt */ -typedef enum -{ - ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */ - ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */ +typedef enum { + ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */ + ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */ } acmp_it_t; /** * @brief Acmp interrupt */ -typedef enum -{ - ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */ - ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */ +typedef enum { + ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */ + ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */ } acmp_flag_t; /** * @brief Acmp interrupt flag */ -typedef enum -{ - ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */ - ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */ +typedef enum { + ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */ + ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */ } acmp_status_t; /** * @brief Acmp positive input */ -typedef enum -{ - ACMP_POS_CH0 = 0, /**< Channel 0 as positive input */ - ACMP_POS_CH1 = 1, /**< Channel 1 as positive input */ - ACMP_POS_CH2 = 2, /**< Channel 2 as positive input */ - ACMP_POS_CH3 = 3, /**< Channel 3 as positive input */ - ACMP_POS_CH4 = 4, /**< Channel 4 as positive input */ - ACMP_POS_CH5 = 5, /**< Channel 5 as positive input */ - ACMP_POS_CH6 = 6, /**< Channel 6 as positive input */ - ACMP_POS_CH7 = 7, /**< Channel 7 as positive input */ +typedef enum { + ACMP_POS_CH0 = 0U, /**< Channel 0 as positive input */ + ACMP_POS_CH1 = 1U, /**< Channel 1 as positive input */ + ACMP_POS_CH2 = 2U, /**< Channel 2 as positive input */ + ACMP_POS_CH3 = 3U, /**< Channel 3 as positive input */ + ACMP_POS_CH4 = 4U, /**< Channel 4 as positive input */ + ACMP_POS_CH5 = 5U, /**< Channel 5 as positive input */ + ACMP_POS_CH6 = 6U, /**< Channel 6 as positive input */ + ACMP_POS_CH7 = 7U, /**< Channel 7 as positive input */ } acmp_pos_input_t; /** * @brief Acmp negative input */ -typedef enum -{ - ACMP_NEG_CH0 = 0, /**< Channel 0 as negative input */ - ACMP_NEG_CH1 = 1, /**< Channel 1 as negative input */ - ACMP_NEG_CH2 = 2, /**< Channel 2 as negative input */ - ACMP_NEG_CH3 = 3, /**< Channel 3 as negative input */ - ACMP_NEG_CH4 = 4, /**< Channel 4 as negative input */ - ACMP_NEG_CH5 = 5, /**< Channel 5 as negative input */ - ACMP_NEG_CH6 = 6, /**< Channel 6 as negative input */ - ACMP_NEG_CH7 = 7, /**< Channel 7 as negative input */ - ACMP_NEG_1V25 = 8, /**< 1.25v as negative input */ - ACMP_NEG_2V5 = 9, /**< 2.5v as negative input */ - ACMP_NEG_VDD = 10, /**< VDD as negative input */ +typedef enum { + ACMP_NEG_CH0 = 0U, /**< Channel 0 as negative input */ + ACMP_NEG_CH1 = 1U, /**< Channel 1 as negative input */ + ACMP_NEG_CH2 = 2U, /**< Channel 2 as negative input */ + ACMP_NEG_CH3 = 3U, /**< Channel 3 as negative input */ + ACMP_NEG_CH4 = 4U, /**< Channel 4 as negative input */ + ACMP_NEG_CH5 = 5U, /**< Channel 5 as negative input */ + ACMP_NEG_CH6 = 6U, /**< Channel 6 as negative input */ + ACMP_NEG_CH7 = 7U, /**< Channel 7 as negative input */ + ACMP_NEG_1V25 = 8U, /**< 1.25v as negative input */ + ACMP_NEG_2V5 = 9U, /**< 2.5v as negative input */ + ACMP_NEG_VDD = 10U, /**< VDD as negative input */ } acmp_neg_input_t; /** * @brief Acmp mode */ -typedef enum -{ - ACMP_ULTRA_LOW_POWER = 0, /**< Ultra low power mode */ - ACMP_LOW_POWER = 1, /**< Low power mode */ - ACMP_MIDDLE_POWER = 2, /**< Middle power mode */ - ACMP_HIGH_POWER = 3, /**< High power mode */ +typedef enum { + ACMP_ULTRA_LOW_POWER = 0U, /**< Ultra low power mode */ + ACMP_LOW_POWER = 1U, /**< Low power mode */ + ACMP_MIDDLE_POWER = 2U, /**< Middle power mode */ + ACMP_HIGH_POWER = 3U, /**< High power mode */ } acmp_mode_t; /** * @brief Acmp warm-up time */ -typedef enum -{ - ACMP_4_PCLK = 0, /**< 4 hfperclk cycles */ - ACMP_8_PCLK = 1, /**< 4 hfperclk cycles */ - ACMP_16_PCLK = 2, /**< 4 hfperclk cycles */ - ACMP_32_PCLK = 3, /**< 4 hfperclk cycles */ - ACMP_64_PCLK = 4, /**< 4 hfperclk cycles */ - ACMP_128_PCLK = 5, /**< 4 hfperclk cycles */ - ACMP_256_PCLK = 6, /**< 4 hfperclk cycles */ - ACMP_512_PCLK = 7, /**< 4 hfperclk cycles */ +typedef enum { + ACMP_4_PCLK = 0U, /**< 4 hfperclk cycles */ + ACMP_8_PCLK = 1U, /**< 4 hfperclk cycles */ + ACMP_16_PCLK = 2U, /**< 4 hfperclk cycles */ + ACMP_32_PCLK = 3U, /**< 4 hfperclk cycles */ + ACMP_64_PCLK = 4U, /**< 4 hfperclk cycles */ + ACMP_128_PCLK = 5U, /**< 4 hfperclk cycles */ + ACMP_256_PCLK = 6U, /**< 4 hfperclk cycles */ + ACMP_512_PCLK = 7U, /**< 4 hfperclk cycles */ } acmp_warm_time_t; /** * @brief Acmp hysteresis level */ -typedef enum -{ - ACMP_HYST_0 = 0, /**< No hysteresis */ - ACMP_HYST_15 = 1, /**< 15mV hysteresis */ - ACMP_HYST_22 = 2, /**< 22mV hysteresis */ - ACMP_HYST_29 = 3, /**< 29mV hysteresis */ - ACMP_HYST_36 = 4, /**< 36mV hysteresis */ - ACMP_HYST_43 = 5, /**< 43mV hysteresis */ - ACMP_HYST_50 = 6, /**< 50mV hysteresis */ - ACMP_HYST_57 = 7, /**< 57mV hysteresis */ +typedef enum { + ACMP_HYST_0 = 0U, /**< No hysteresis */ + ACMP_HYST_15 = 1U, /**< 15mV hysteresis */ + ACMP_HYST_22 = 2U, /**< 22mV hysteresis */ + ACMP_HYST_29 = 3U, /**< 29mV hysteresis */ + ACMP_HYST_36 = 4U, /**< 36mV hysteresis */ + ACMP_HYST_43 = 5U, /**< 43mV hysteresis */ + ACMP_HYST_50 = 6U, /**< 50mV hysteresis */ + ACMP_HYST_57 = 7U, /**< 57mV hysteresis */ } acmp_hystsel_t; /** * @brief Acmp inactive state */ -typedef enum -{ - ACMP_INACTVAL_LOW = 0, /**< The inactive value is 0 */ - ACMP_INACTVAL_HIGH = 1, /**< The inactive value is 1 */ +typedef enum { + ACMP_INACTVAL_LOW = 0U, /**< The inactive value is 0 */ + ACMP_INACTVAL_HIGH = 1U, /**< The inactive value is 1 */ } acmp_inactval_t; /** * @brief which edges set up interrupt */ -typedef enum -{ - ACMP_EDGE_NONE = 0, /**< Disable EDGE interrupt */ - ACMP_EDGE_FALL = 1, /**< Falling edges set EDGE interrupt */ - ACMP_EDGE_RISE = 2, /**< rise edges set EDGE interrupt */ - ACMP_EDGE_ALL = 3, /**< Falling edges and rise edges set EDGE interrupt */ +typedef enum { + ACMP_EDGE_NONE = 0U, /**< Disable EDGE interrupt */ + ACMP_EDGE_FALL = 1U, /**< Falling edges set EDGE interrupt */ + ACMP_EDGE_RISE = 2U, /**< rise edges set EDGE interrupt */ + ACMP_EDGE_ALL = 3U, /**< Falling edges and rise edges set EDGE interrupt */ } acmp_edge_t; /** * @brief Acmp output function */ -typedef enum -{ - ACMP_OUT_DISABLE = 0, /**< Disable acmp output */ - ACMP_OUT_ENABLE = 1, /**< Enable acmp output */ +typedef enum { + ACMP_OUT_DISABLE = 0U, /**< Disable acmp output */ + ACMP_OUT_ENABLE = 1U, /**< Enable acmp output */ } acmp_out_func_t; /** * @brief Acmp warm-up interrupt function */ -typedef enum -{ - ACMP_WARM_DISABLE = 0, /**< Disable acmp warm-up interrupt */ - ACMP_WARM_ENABLE = 1, /**< Enable acmp warm-up interrupt */ +typedef enum { + ACMP_WARM_DISABLE = 0U, /**< Disable acmp warm-up interrupt */ + ACMP_WARM_ENABLE = 1U, /**< Enable acmp warm-up interrupt */ } acmp_warm_it_func; /** * @brief Acmp gpio output invert */ -typedef enum -{ - ACMP_GPIO_NO_INV = 0, /**< Acmp output to gpio is not inverted */ - ACMP_GPIO_INV = 1, /**< Acmp output to gpio is inverted */ +typedef enum { + ACMP_GPIO_NO_INV = 0U, /**< Acmp output to gpio is not inverted */ + ACMP_GPIO_INV = 1U, /**< Acmp output to gpio is inverted */ } acmp_invert_t; /** * @brief Acmp output config structure definition */ -typedef struct -{ - acmp_out_func_t out_func; /**< Acmp output function */ - acmp_invert_t gpio_inv; /**< If invert gpio output */ +typedef struct { + acmp_out_func_t out_func; /**< Acmp output function */ + acmp_invert_t gpio_inv; /**< If invert gpio output */ } acmp_output_config_t; /** * @brief Acmp init structure definition */ -typedef struct -{ - acmp_mode_t mode; /**< Acmp operation mode */ - acmp_warm_time_t warm_time; /**< Acmp warm up time */ - acmp_hystsel_t hystsel; /**< Acmp hysteresis level */ - acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */ - acmp_pos_input_t pos_port; /**< Acmp positive port select */ - acmp_neg_input_t neg_port; /**< Acmp negative port select */ - acmp_inactval_t inactval; /**< Acmp inavtive output value */ - acmp_edge_t edge; /** Select edges to set interrupt flag */ - uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */ +typedef struct { + acmp_mode_t mode; /**< Acmp operation mode */ + acmp_warm_time_t warm_time; /**< Acmp warm up time */ + acmp_hystsel_t hystsel; /**< Acmp hysteresis level */ + acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */ + acmp_pos_input_t pos_port; /**< Acmp positive port select */ + acmp_neg_input_t neg_port; /**< Acmp negative port select */ + acmp_inactval_t inactval; /**< Acmp inavtive output value */ + acmp_edge_t edge; /** Select edges to set interrupt flag */ + uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */ } acmp_init_t; /** * @brief ACMP Handle Structure definition */ -typedef struct acmp_handle_s -{ - ACMP_TypeDef *perh; /**< Register base address */ - acmp_init_t init; /**< ACMP required parameters */ - lock_state_t lock; /**< Locking object */ +typedef struct acmp_handle_s { + ACMP_TypeDef *perh; /**< Register base address */ + acmp_init_t init; /**< ACMP required parameters */ + lock_state_t lock; /**< Locking object */ - void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */ - void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */ + void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */ + void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */ } acmp_handle_t; /** * @} @@ -237,64 +221,64 @@ typedef struct acmp_handle_s * @{ */ #define IS_ACMP_TYPE(x) (((x) == ACMP0) || \ - ((x) == ACMP1)) + ((x) == ACMP1)) #define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \ - ((x) == ACMP_LOW_POWER) || \ - ((x) == ACMP_MIDDLE_POWER) || \ - ((x) == ACMP_HIGH_POWER)) + ((x) == ACMP_LOW_POWER) || \ + ((x) == ACMP_MIDDLE_POWER) || \ + ((x) == ACMP_HIGH_POWER)) #define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \ - ((x) == ACMP_IT_WARMUP)) + ((x) == ACMP_IT_WARMUP)) #define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \ - ((x) == ACMP_FLAG_WARMUP)) + ((x) == ACMP_FLAG_WARMUP)) #define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_EDGE) || \ - ((x) == ACMP_STATUS_WARMUP)) + ((x) == ACMP_STATUS_WARMUP)) #define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \ - ((x) == ACMP_POS_CH1) || \ - ((x) == ACMP_POS_CH2) || \ - ((x) == ACMP_POS_CH3) || \ - ((x) == ACMP_POS_CH4) || \ - ((x) == ACMP_POS_CH5) || \ - ((x) == ACMP_POS_CH6) || \ - ((x) == ACMP_POS_CH7)) + ((x) == ACMP_POS_CH1) || \ + ((x) == ACMP_POS_CH2) || \ + ((x) == ACMP_POS_CH3) || \ + ((x) == ACMP_POS_CH4) || \ + ((x) == ACMP_POS_CH5) || \ + ((x) == ACMP_POS_CH6) || \ + ((x) == ACMP_POS_CH7)) #define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \ - ((x) == ACMP_NEG_CH1) || \ - ((x) == ACMP_NEG_CH2) || \ - ((x) == ACMP_NEG_CH3) || \ - ((x) == ACMP_NEG_CH4) || \ - ((x) == ACMP_NEG_CH5) || \ - ((x) == ACMP_NEG_CH6) || \ - ((x) == ACMP_NEG_CH7) || \ - ((x) == ACMP_NEG_1V25) || \ - ((x) == ACMP_NEG_2V5) || \ - ((x) == ACMP_NEG_VDD)) + ((x) == ACMP_NEG_CH1) || \ + ((x) == ACMP_NEG_CH2) || \ + ((x) == ACMP_NEG_CH3) || \ + ((x) == ACMP_NEG_CH4) || \ + ((x) == ACMP_NEG_CH5) || \ + ((x) == ACMP_NEG_CH6) || \ + ((x) == ACMP_NEG_CH7) || \ + ((x) == ACMP_NEG_1V25) || \ + ((x) == ACMP_NEG_2V5) || \ + ((x) == ACMP_NEG_VDD)) #define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \ - ((x) == ACMP_8_PCLK) || \ - ((x) == ACMP_16_PCLK) || \ - ((x) == ACMP_32_PCLK) || \ - ((x) == ACMP_64_PCLK) || \ - ((x) == ACMP_128_PCLK) || \ - ((x) == ACMP_256_PCLK) || \ - ((x) == ACMP_512_PCLK)) + ((x) == ACMP_8_PCLK) || \ + ((x) == ACMP_16_PCLK) || \ + ((x) == ACMP_32_PCLK) || \ + ((x) == ACMP_64_PCLK) || \ + ((x) == ACMP_128_PCLK) || \ + ((x) == ACMP_256_PCLK) || \ + ((x) == ACMP_512_PCLK)) #define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \ - ((x) == ACMP_HYST_15) || \ - ((x) == ACMP_HYST_22) || \ - ((x) == ACMP_HYST_29) || \ - ((x) == ACMP_HYST_36) || \ - ((x) == ACMP_HYST_43) || \ - ((x) == ACMP_HYST_50) || \ - ((x) == ACMP_HYST_57)) + ((x) == ACMP_HYST_15) || \ + ((x) == ACMP_HYST_22) || \ + ((x) == ACMP_HYST_29) || \ + ((x) == ACMP_HYST_36) || \ + ((x) == ACMP_HYST_43) || \ + ((x) == ACMP_HYST_50) || \ + ((x) == ACMP_HYST_57)) #define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \ - ((x) == ACMP_INACTVAL_HIGH)) + ((x) == ACMP_INACTVAL_HIGH)) #define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \ - ((x) == ACMP_EDGE_FALL) || \ - ((x) == ACMP_EDGE_RISE) || \ - ((x) == ACMP_EDGE_ALL)) + ((x) == ACMP_EDGE_FALL) || \ + ((x) == ACMP_EDGE_RISE) || \ + ((x) == ACMP_EDGE_ALL)) #define IS_ACMP_OUT_FUNC_TYPE(x) (((x) == ACMP_OUT_DISABLE) || \ - ((x) == ACMP_OUT_ENABLE)) + ((x) == ACMP_OUT_ENABLE)) #define IS_ACMP_INVERT_TYPE(x) (((x) == ACMP_GPIO_NO_INV) || \ - ((x) == ACMP_GPIO_INV)) + ((x) == ACMP_GPIO_INV)) #define IS_ACMP_WARM_FUNC_TYPE(x) (((x) == ACMP_WARM_DISABLE) || \ - ((x) == ACMP_WARM_ENABLE)) + ((x) == ACMP_WARM_ENABLE)) /** * @} */ @@ -348,8 +332,7 @@ uint8_t ald_acmp_out_result(acmp_handle_t *hperh); * @} */ #ifdef __cplusplus -extern "C" -} + extern "C" } #endif #endif diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_adc.h index d138f16c88d05e061735d8519e36772fec01a008..b5f9532f8db0dccc1b67a87aeac57eb2ee77ba63 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_adc.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_adc.h @@ -17,7 +17,7 @@ #define __ALD_ADC_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -40,368 +40,342 @@ extern "C" { /** * @brief ADC State structures definition */ -typedef enum -{ - ADC_STATE_RESET = 0x0, /**< ADC not yet initialized or disabled */ - ADC_STATE_READY = 0x1, /**< ADC peripheral ready for use */ - ADC_STATE_BUSY_INTERNAL = 0x2, /**< ADC is busy to internal process */ - ADC_STATE_TIMEOUT = 0x4, /**< TimeOut occurrence */ - ADC_STATE_ERROR = 0x10, /**< Internal error occurrence */ - ADC_STATE_NM_BUSY = 0x100, /**< Conversion on group normal is ongoing or can occur */ - ADC_STATE_NM_EOC = 0x200, /**< Conversion data available on group normal */ - ADC_STATE_IST_BUSY = 0x1000, /**< Conversion on group insert is ongoing or can occur */ - ADC_STATE_IST_EOC = 0x2000, /**< Conversion data available on group insert */ - ADC_STATE_AWD = 0x10000, /**< Out-of-window occurrence of analog watchdog */ +typedef enum { + ADC_STATE_RESET = 0x0U, /**< ADC not yet initialized or disabled */ + ADC_STATE_READY = 0x1U, /**< ADC peripheral ready for use */ + ADC_STATE_BUSY = 0x2U, /**< ADC is busy to internal process */ + ADC_STATE_TIMEOUT = 0x4U, /**< TimeOut occurrence */ + ADC_STATE_ERROR = 0x8U, /**< Internal error occurrence */ + ADC_STATE_BUSY_N = 0x10U, /**< Normal channel busy */ + ADC_STATE_BUSY_I = 0x20U, /**< Insert channel busy */ + ADC_STATE_BUSY_WDG = 0x40U, /**< Insert channel busy */ } adc_state_t; /** *@brief ADC Error Code */ -typedef enum -{ - ADC_ERROR_NONE = 0x0, /**< No error */ - ADC_ERROR_INTERNAL = 0x1, /**< ADC IP internal error*/ - ADC_ERROR_OVR = 0x2, /**< Overrun error */ - ADC_ERROR_DMA = 0x4, /**< DMA transfer error */ +typedef enum { + ADC_ERROR_NONE = 0x0U, /**< No error */ + ADC_ERROR_INTERNAL = 0x1U, /**< ADC IP internal error*/ + ADC_ERROR_OVR = 0x2U, /**< Overrun error */ + ADC_ERROR_DMA = 0x4U, /**< DMA transfer error */ } adc_error_t; /** *@brief ADC data alignment */ -typedef enum -{ - ADC_DATAALIGN_RIGHT = 0x0, /**< ADC data alignment right */ - ADC_DATAALIGN_LEFT = 0x1, /**< ADC data alignment left */ +typedef enum { + ADC_DATAALIGN_RIGHT = 0x0U, /**< ADC data alignment right */ + ADC_DATAALIGN_LEFT = 0x1U, /**< ADC data alignment left */ } adc_align_t; /** *@brief ADC config hannal trigger the EOC IT mode */ -typedef enum -{ - ADC_NCHESEL_MODE_ALL = 0x0, /**< ADC set RCHE after convert sequence finish */ - ADC_NCHESEL_MODE_ONE = 0x1, /**< ADC set RCHE after one convert finish */ +typedef enum { + ADC_NCHESEL_MODE_ALL = 0x0U, /**< ADC set RCHE after convert sequence finish */ + ADC_NCHESEL_MODE_ONE = 0x1U, /**< ADC set RCHE after one convert finish */ } adc_nchesel_t; /** *@brief ADC channels */ -typedef enum -{ - ADC_CHANNEL_0 = 0x0, /**< ADC channel 0 */ - ADC_CHANNEL_1 = 0x1, /**< ADC channel 1 */ - ADC_CHANNEL_2 = 0x2, /**< ADC channel 2 */ - ADC_CHANNEL_3 = 0x3, /**< ADC channel 3 */ - ADC_CHANNEL_4 = 0x4, /**< ADC channel 4 */ - ADC_CHANNEL_5 = 0x5, /**< ADC channel 5 */ - ADC_CHANNEL_6 = 0x6, /**< ADC channel 6 */ - ADC_CHANNEL_7 = 0x7, /**< ADC channel 7 */ - ADC_CHANNEL_8 = 0x8, /**< ADC channel 8 */ - ADC_CHANNEL_9 = 0x9, /**< ADC channel 9 */ - ADC_CHANNEL_10 = 0xA, /**< ADC channel 10 */ - ADC_CHANNEL_11 = 0xB, /**< ADC channel 11 */ - ADC_CHANNEL_12 = 0xC, /**< ADC channel 12 */ - ADC_CHANNEL_13 = 0xD, /**< ADC channel 13 */ - ADC_CHANNEL_14 = 0xE, /**< ADC channel 14 */ - ADC_CHANNEL_15 = 0xF, /**< ADC channel 15 */ - ADC_CHANNEL_16 = 0x10, /**< ADC channel 16 */ - ADC_CHANNEL_17 = 0x11, /**< ADC channel 17 */ - ADC_CHANNEL_18 = 0x12, /**< ADC channel 18 */ - ADC_CHANNEL_19 = 0x13, /**< ADC channel 19 */ +typedef enum { + ADC_CHANNEL_0 = 0x0U, /**< ADC channel 0 */ + ADC_CHANNEL_1 = 0x1U, /**< ADC channel 1 */ + ADC_CHANNEL_2 = 0x2U, /**< ADC channel 2 */ + ADC_CHANNEL_3 = 0x3U, /**< ADC channel 3 */ + ADC_CHANNEL_4 = 0x4U, /**< ADC channel 4 */ + ADC_CHANNEL_5 = 0x5U, /**< ADC channel 5 */ + ADC_CHANNEL_6 = 0x6U, /**< ADC channel 6 */ + ADC_CHANNEL_7 = 0x7U, /**< ADC channel 7 */ + ADC_CHANNEL_8 = 0x8U, /**< ADC channel 8 */ + ADC_CHANNEL_9 = 0x9U, /**< ADC channel 9 */ + ADC_CHANNEL_10 = 0xAU, /**< ADC channel 10 */ + ADC_CHANNEL_11 = 0xBU, /**< ADC channel 11 */ + ADC_CHANNEL_12 = 0xCU, /**< ADC channel 12 */ + ADC_CHANNEL_13 = 0xDU, /**< ADC channel 13 */ + ADC_CHANNEL_14 = 0xEU, /**< ADC channel 14 */ + ADC_CHANNEL_15 = 0xFU, /**< ADC channel 15 */ + ADC_CHANNEL_16 = 0x10U, /**< ADC channel 16 */ + ADC_CHANNEL_17 = 0x11U, /**< ADC channel 17 */ + ADC_CHANNEL_18 = 0x12U, /**< ADC channel 18 */ + ADC_CHANNEL_19 = 0x13U, /**< ADC channel 19 */ } adc_channel_t; /** *@brief ADC sampling times */ -typedef enum -{ - ADC_SAMPLETIME_1 = 0x0, /**< ADC sampling times 1 clk */ - ADC_SAMPLETIME_2 = 0x1, /**< ADC sampling times 2 clk */ - ADC_SAMPLETIME_4 = 0x2, /**< ADC sampling times 4 clk */ - ADC_SAMPLETIME_15 = 0x3, /**< ADC sampling times 15 clk */ +typedef enum { + ADC_SAMPLETIME_1 = 0x0U, /**< ADC sampling times 1 clk */ + ADC_SAMPLETIME_2 = 0x1U, /**< ADC sampling times 2 clk */ + ADC_SAMPLETIME_4 = 0x2U, /**< ADC sampling times 4 clk */ + ADC_SAMPLETIME_15 = 0x3U, /**< ADC sampling times 15 clk */ } adc_samp_t; /** - *@brief ADC rank into normal group - */ -typedef enum -{ - ADC_NCH_RANK_1 = 0x1, /**< ADC normal channel rank 1 */ - ADC_NCH_RANK_2 = 0x2, /**< ADC normal channel rank 2 */ - ADC_NCH_RANK_3 = 0x3, /**< ADC normal channel rank 3 */ - ADC_NCH_RANK_4 = 0x4, /**< ADC normal channel rank 4 */ - ADC_NCH_RANK_5 = 0x5, /**< ADC normal channel rank 5 */ - ADC_NCH_RANK_6 = 0x6, /**< ADC normal channel rank 6 */ - ADC_NCH_RANK_7 = 0x7, /**< ADC normal channel rank 7 */ - ADC_NCH_RANK_8 = 0x8, /**< ADC normal channel rank 8 */ - ADC_NCH_RANK_9 = 0x9, /**< ADC normal channel rank 9 */ - ADC_NCH_RANK_10 = 0xA, /**< ADC normal channel rank 10 */ - ADC_NCH_RANK_11 = 0xB, /**< ADC normal channel rank 11 */ - ADC_NCH_RANK_12 = 0xC, /**< ADC normal channel rank 12 */ - ADC_NCH_RANK_13 = 0xD, /**< ADC normal channel rank 13 */ - ADC_NCH_RANK_14 = 0xE, /**< ADC normal channel rank 14 */ - ADC_NCH_RANK_15 = 0xF, /**< ADC normal channel rank 15 */ - ADC_NCH_RANK_16 = 0x10, /**< ADC normal channel rank 16 */ -} adc_nch_rank_t; - -/** - * @brief ADC rank into insert group - */ -typedef enum -{ - ADC_ICH_RANK_1 = 0x1, /**< ADC insert channel rank 1 */ - ADC_ICH_RANK_2 = 0x2, /**< ADC insert channel rank 2 */ - ADC_ICH_RANK_3 = 0x3, /**< ADC insert channel rank 3 */ - ADC_ICH_RANK_4 = 0x4, /**< ADC insert channel rank 4 */ -} adc_ich_rank_t; + *@brief ADC index channel in normal group + */ +typedef enum { + ADC_NCH_IDX_1 = 0x1U, /**< ADC normal channel index 1 */ + ADC_NCH_IDX_2 = 0x2U, /**< ADC normal channel index 2 */ + ADC_NCH_IDX_3 = 0x3U, /**< ADC normal channel index 3 */ + ADC_NCH_IDX_4 = 0x4U, /**< ADC normal channel index 4 */ + ADC_NCH_IDX_5 = 0x5U, /**< ADC normal channel index 5 */ + ADC_NCH_IDX_6 = 0x6U, /**< ADC normal channel index 6 */ + ADC_NCH_IDX_7 = 0x7U, /**< ADC normal channel index 7 */ + ADC_NCH_IDX_8 = 0x8U, /**< ADC normal channel index 8 */ + ADC_NCH_IDX_9 = 0x9U, /**< ADC normal channel index 9 */ + ADC_NCH_IDX_10 = 0xAU, /**< ADC normal channel index 10 */ + ADC_NCH_IDX_11 = 0xBU, /**< ADC normal channel index 11 */ + ADC_NCH_IDX_12 = 0xCU, /**< ADC normal channel index 12 */ + ADC_NCH_IDX_13 = 0xDU, /**< ADC normal channel index 13 */ + ADC_NCH_IDX_14 = 0xEU, /**< ADC normal channel index 14 */ + ADC_NCH_IDX_15 = 0xFU, /**< ADC normal channel index 15 */ + ADC_NCH_IDX_16 = 0x10U, /**< ADC normal channel index 16 */ +} adc_nch_idx_t; + +/** + * @brief ADC index channel in insert group + */ +typedef enum { + ADC_ICH_IDX_1 = 0x1U, /**< ADC insert channel index 1 */ + ADC_ICH_IDX_2 = 0x2U, /**< ADC insert channel index 2 */ + ADC_ICH_IDX_3 = 0x3U, /**< ADC insert channel index 3 */ + ADC_ICH_IDX_4 = 0x4U, /**< ADC insert channel index 4 */ +} adc_ich_idx_t; /** * @brief ADC analog watchdog mode */ -typedef enum -{ - ADC_ANAWTD_NONE = 0x0, /**< No watch dog */ - ADC_ANAWTD_SING_NM = 0x800200, /**< One normal channel watch dog */ - ADC_ANAWTD_SING_IST = 0x400200, /**< One inset channel Injec watch dog */ - ADC_ANAWTD_SING_NMIST = 0xC00200, /**< One normal and inset channel watch dog */ - ADC_ANAWTD_ALL_NM = 0x800000, /**< All normal channel watch dog */ - ADC_ANAWTD_ALL_IST = 0x400000, /**< All inset channel watch dog */ - ADC_ANAWTD_ALL_NMIST = 0xC00000, /**< All normal and inset channel watch dog */ -} adc_ana_wtd_t; +typedef enum { + ADC_ANAWTD_NONE = 0x0U, /**< No watch dog */ + ADC_ANAWTD_SING_NM = 0x800200U, /**< One normal channel watch dog */ + ADC_ANAWTD_SING_IST = 0x400200U, /**< One insert channel watch dog */ + ADC_ANAWTD_SING_NMIST = 0xC00200U, /**< One normal and insert channel watch dog */ + ADC_ANAWTD_ALL_NM = 0x800000U, /**< All normal channel watch dog */ + ADC_ANAWTD_ALL_IST = 0x400000U, /**< All insert channel watch dog */ + ADC_ANAWTD_ALL_NMIST = 0xC00000U, /**< All normal and insert channel watch dog */ +} adc_ana_wdg_t; /** * @brief ADC Event type */ -typedef enum -{ - ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ +typedef enum { + ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ } adc_event_type_t; /** * @brief ADC interrupts definition */ -typedef enum -{ - ADC_IT_NCH = (1U << 5), /**< ADC it normal */ - ADC_IT_AWD = (1U << 6), /**< ADC it awd */ - ADC_IT_ICH = (1U << 7), /**< ADC it insert */ - ADC_IT_OVR = (1U << 26), /**< ADC it overring */ +typedef enum { + ADC_IT_NCH = (1U << 5), /**< ADC it normal */ + ADC_IT_AWD = (1U << 6), /**< ADC it awd */ + ADC_IT_ICH = (1U << 7), /**< ADC it insert */ + ADC_IT_OVR = (1U << 26), /**< ADC it overring */ } adc_it_t; /** * @brief ADC flags definition */ -typedef enum -{ - ADC_FLAG_AWD = (1U << 0), /**perh->CON1, ADC_CON1_ADCEN_MSK)) -#define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) -#define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) -#define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) -#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) -#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) -#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_ENABLE(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) +#define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) +#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) +#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_SPEED_HIGH_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK)) +#define ADC_SPEED_HIGH_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK)) +#define ADC_CALIBRATE_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK)) +#define ADC_CALIBRATE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK)) /** * @} */ @@ -424,68 +402,65 @@ typedef struct /** @defgroup ADC_Private_Macros ADC Private Macros * @{ */ -#define IS_ADC_ICH_RANK_TYPE(x) ((x) <= ADC_ICH_RANK_4) -#define IS_ADC_NCH_RANK_TYPE(x) ((x) <= ADC_NCH_RANK_16) +#define IS_ADC_ICH_IDX_TYPE(x) ((x) <= ADC_ICH_IDX_4) +#define IS_ADC_NCH_IDX_TYPE(x) ((x) <= ADC_NCH_IDX_16) #define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ADC_SAMPLETIME_1) || \ - ((x) == ADC_SAMPLETIME_2) || \ - ((x) == ADC_SAMPLETIME_4) || \ - ((x) == ADC_SAMPLETIME_15)) + ((x) == ADC_SAMPLETIME_2) || \ + ((x) == ADC_SAMPLETIME_4) || \ + ((x) == ADC_SAMPLETIME_15)) #define IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_19) -#define IS_ADC_SCAN_MODE_TYPE(x) (((x) == DISABLE) || \ - ((x) == ENABLE)) #define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ADC_DATAALIGN_RIGHT) || \ - ((x) == ADC_DATAALIGN_LEFT)) + ((x) == ADC_DATAALIGN_LEFT)) #define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ADC_ANAWTD_NONE) || \ - ((x) == ADC_ANAWTD_SING_NM) || \ - ((x) == ADC_ANAWTD_SING_IST) || \ - ((x) == ADC_ANAWTD_SING_NMIST) || \ - ((x) == ADC_ANAWTD_ALL_NM) || \ - ((x) == ADC_ANAWTD_ALL_IST) || \ - ((x) == ADC_ANAWTD_ALL_NMIST)) + ((x) == ADC_ANAWTD_SING_NM) || \ + ((x) == ADC_ANAWTD_SING_IST) || \ + ((x) == ADC_ANAWTD_SING_NMIST) || \ + ((x) == ADC_ANAWTD_ALL_NM) || \ + ((x) == ADC_ANAWTD_ALL_IST) || \ + ((x) == ADC_ANAWTD_ALL_NMIST)) #define IS_ADC_IT_TYPE(x) (((x) == ADC_IT_NCH) || \ - ((x) == ADC_IT_AWD) || \ - ((x) == ADC_IT_ICH) || \ - ((x) == ADC_IT_OVR )) + ((x) == ADC_IT_AWD) || \ + ((x) == ADC_IT_ICH) || \ + ((x) == ADC_IT_OVR )) #define IS_ADC_FLAGS_TYPE(x) (((x) == ADC_FLAG_AWD) || \ - ((x) == ADC_FLAG_NCH) || \ - ((x) == ADC_FLAG_ICH) || \ - ((x) == ADC_FLAG_OVR) || \ - ((x) == ADC_FLAG_NCHS) || \ - ((x) == ADC_FLAG_ICHS)) + ((x) == ADC_FLAG_NCH) || \ + ((x) == ADC_FLAG_ICH) || \ + ((x) == ADC_FLAG_OVR) || \ + ((x) == ADC_FLAG_NCHS) || \ + ((x) == ADC_FLAG_ICHS)) #define IS_ADC_CLK_DIV_TYPE(x) (((x) == ADC_CKDIV_1) || \ - ((x) == ADC_CKDIV_2) || \ - ((x) == ADC_CKDIV_4) || \ - ((x) == ADC_CKDIV_8) || \ - ((x) == ADC_CKDIV_16) || \ - ((x) == ADC_CKDIV_32) || \ - ((x) == ADC_CKDIV_64) || \ - ((x) == ADC_CKDIV_128)) + ((x) == ADC_CKDIV_2) || \ + ((x) == ADC_CKDIV_4) || \ + ((x) == ADC_CKDIV_8) || \ + ((x) == ADC_CKDIV_16) || \ + ((x) == ADC_CKDIV_32) || \ + ((x) == ADC_CKDIV_64) || \ + ((x) == ADC_CKDIV_128)) #define IS_ADC_NEG_REF_VOLTAGE_TYPE(x) (((x) == ADC_NEG_REF_VSS ) || \ - ((x) == ADC_NEG_REF_VREFN )) + ((x) == ADC_NEG_REF_VREFN )) #define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ADC_POS_REF_VDD) || \ - ((x) == ADC_POS_REF_VREEFP) || \ - ((x) == ADC_POS_REF_VREEFP_BUF)) -#define IS_ADC_NCH_LEN_TYPE(x) ((x) <= ADC_NCH_LEN_16) -#define IS_ADC_NBR_OF_IST_TYPE(x) ((x) <= ADC_ICH_LEN_4) + ((x) == ADC_POS_REF_VREEFP) || \ + ((x) == ADC_POS_REF_VREEFP_BUF)) +#define IS_ADC_NCH_NR_TYPE(x) ((x) <= ADC_NCH_NR_16) +#define IS_ADC_ICH_NR_TYPE(x) ((x) <= ADC_ICH_NR_4) #define IS_ADC_DISC_MODE_TYPE(x) (((x) == ADC_ALL_DISABLE) || \ - ((x) == ADC_NCH_DISC_EN) || \ - ((x) == ADC_ICH_DISC_EN)) -#define IS_ADC_DISC_NBR_TYPE(x) ((x) <= ADC_DISC_NBR_8) -#define IS_ADC_CONV_RES_TYPE(x) (((x) == ADC_CONV_RES_12) || \ - ((x) == ADC_CONV_RES_6) || \ - ((x) == ADC_CONV_RES_8) || \ - ((x) == ADC_CONV_RES_10)) + ((x) == ADC_NCH_DISC_EN) || \ + ((x) == ADC_ICH_DISC_EN)) +#define IS_ADC_DISC_NR_TYPE(x) ((x) <= ADC_DISC_NR_8) +#define IS_ADC_CONV_BIT_TYPE(x) (((x) == ADC_CONV_BIT_12) || \ + ((x) == ADC_CONV_BIT_6) || \ + ((x) == ADC_CONV_BIT_8) || \ + ((x) == ADC_CONV_BIT_10)) #define IS_ADC_TRIG_MODE_TYPE(x) (((x) == ADC_TRIG_SOFT) || \ - ((x) == ADC_TRIG_PIS) || \ - ((x) == ADC_TRIG_PIS_SOFT)) -#define IS_ADC_TYPE(x) (((x) == ADC0) || \ - ((x) == ADC1)) + ((x) == ADC_TRIG_PIS) || \ + ((x) == ADC_TRIG_PIS_SOFT)) +#define IS_ADC_TYPE(x) (((x) == ADC0)) #define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ADC_NCHESEL_MODE_ALL) || \ - ((x) == ADC_NCHESEL_MODE_ONE)) + ((x) == ADC_NCHESEL_MODE_ONE)) #define IS_ADC_EVENT_TYPE(x) ((x) == ADC_AWD_EVENT) -#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff) -#define IS_HTR_TYPE(x) ((x) <= 0xfff) -#define IS_LTR_TYPE(x) ((x) <= 0xfff) +#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xFFF) +#define IS_HTR_TYPE(x) ((x) <= 0xFFF) +#define IS_LTR_TYPE(x) ((x) <= 0xFFF) /** * @} */ @@ -514,7 +489,7 @@ ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh); ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh); #ifdef ALD_DMA ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh); +ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel); ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config); #endif uint32_t ald_adc_normal_get_value(adc_handle_t *hperh); @@ -524,7 +499,7 @@ ald_status_t ald_adc_insert_stop(adc_handle_t *hperh); ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh); ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh); -uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank); +uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t ih_rank); void ald_adc_irq_handler(adc_handle_t *hperh); /** * @} @@ -565,8 +540,7 @@ uint32_t ald_adc_get_error(adc_handle_t *hperh); * @} */ #ifdef __cplusplus -extern "C" -} + extern "C" } #endif -#endif /* __ALD_ADC_H */ +#endif /* __ALD_ADC_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_bkpc.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_bkpc.h index 7bac14c70ecbba4ed9a32cebfb28916215252f96..cbaa1c88f8dca5b61c368369d0f88c80dc99e7c4 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_bkpc.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_bkpc.h @@ -35,44 +35,44 @@ extern "C" { /** @defgroup BKPC_Public_Macros BKPC Public Macros * @{ */ -#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0)) -#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55)) +#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0U)) +#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55U)) #define BKPC_LRC_ENABLE() \ - do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ - BKPC_LOCK(); \ - } while (0) +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) #define BKPC_LRC_DISABLE() \ - do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ - BKPC_LOCK(); \ - } while (0) +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) #define BKPC_LOSM_ENABLE() \ - do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \ - BKPC_LOCK(); \ - } while (0) +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \ + BKPC_LOCK(); \ +} while (0) #define BKPC_LOSM_DISABLE() \ - do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\ - BKPC_LOCK(); \ - } while (0) +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\ + BKPC_LOCK(); \ +} while (0) #define BKPC_LOSC_ENABLE() \ - do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \ - BKPC_LOCK(); \ - } while (0) +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) #define BKPC_LOSC_DISABLE() \ - do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\ - BKPC_LOCK(); \ - } while (0) +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\ + BKPC_LOCK(); \ +} while (0) /** * @} */ @@ -83,37 +83,31 @@ extern "C" { /** * @brief BKPC ldo output select */ -typedef enum -{ - BKPC_LDO_OUTPUT_1_6 = 0x0, /**< 1.6V */ - BKPC_LDO_OUTPUT_1_3 = 0x1, /**< 1.3V */ - BKPC_LDO_OUTPUT_1_4 = 0x2, /**< 1.4V */ - BKPC_LDO_OUTPUT_1_5 = 0x4, /**< 1.5V */ +typedef enum { + BKPC_LDO_OUTPUT_1_6 = 0x0U, /**< 1.6V */ + BKPC_LDO_OUTPUT_1_3 = 0x1U, /**< 1.3V */ + BKPC_LDO_OUTPUT_1_4 = 0x2U, /**< 1.4V */ + BKPC_LDO_OUTPUT_1_5 = 0x4U, /**< 1.5V */ } bkpc_ldo_output_t; /** - * @brief BKPC BOR voltage select - */ -typedef enum -{ - BKPC_BOR_VOL_1_7 = 0x0, /**< 1.7V */ - BKPC_BOR_VOL_2_0 = 0x1, /**< 2.0V */ - BKPC_BOR_VOL_2_1 = 0x2, /**< 2.1V */ - BKPC_BOR_VOL_2_2 = 0x3, /**< 2.2V */ - BKPC_BOR_VOL_2_3 = 0x4, /**< 2.3V */ - BKPC_BOR_VOL_2_4 = 0x5, /**< 2.4V */ - BKPC_BOR_VOL_2_5 = 0x6, /**< 2.5V */ - BKPC_BOR_VOL_2_6 = 0x7, /**< 2.6V */ - BKPC_BOR_VOL_2_8 = 0x8, /**< 2.8V */ - BKPC_BOR_VOL_3_0 = 0x9, /**< 3.0V */ - BKPC_BOR_VOL_3_1 = 0xA, /**< 3.1V */ - BKPC_BOR_VOL_3_3 = 0xB, /**< 3.3V */ - BKPC_BOR_VOL_3_6 = 0xC, /**< 3.6V */ - BKPC_BOR_VOL_3_7 = 0xD, /**< 3.7V */ - BKPC_BOR_VOL_4_0 = 0xE, /**< 4.0V */ - BKPC_BOR_VOL_4_3 = 0xF, /**< 4.3V */ -} bkpc_bor_vol_t; + * @brief Standby wakeup port select + */ +typedef enum { + PMU_STANDBY_PORT_SEL_PA0 = 0x0U, /**< Wakeup by PA0 */ + PMU_STANDBY_PORT_SEL_PA1 = 0x1U, /**< Wakeup by PA1 */ + PMU_STANDBY_PORT_SEL_PA2 = 0x2U, /**< Wakeup by PA2 */ + PMU_STANDBY_PORT_SEL_PA3 = 0x3U, /**< Wakeup by PA3 */ + PMU_STANDBY_PORT_SEL_NONE = 0xFU, /**< Wakeup by other source */ +} bkpc_wakeup_port_t; +/** + * @brief Standby wakeup level + */ +typedef enum { + PMU_STANDBY_LEVEL_HIGH = 0x0U, /**< High level */ + PMU_STANDBY_LEVEL_LOW = 0x1U, /**< Low level */ +} bkpc_wakeup_level_t; /** * @} */ @@ -126,22 +120,13 @@ typedef enum ((x) == BKPC_LDO_OUTPUT_1_3) || \ ((x) == BKPC_LDO_OUTPUT_1_4) || \ ((x) == BKPC_LDO_OUTPUT_1_5)) -#define IS_BKPC_BOR_VOL(x) (((x) == BKPC_BOR_VOL_1_7) || \ - ((x) == BKPC_BOR_VOL_2_0) || \ - ((x) == BKPC_BOR_VOL_2_1) || \ - ((x) == BKPC_BOR_VOL_2_2) || \ - ((x) == BKPC_BOR_VOL_2_3) || \ - ((x) == BKPC_BOR_VOL_2_4) || \ - ((x) == BKPC_BOR_VOL_2_5) || \ - ((x) == BKPC_BOR_VOL_2_6) || \ - ((x) == BKPC_BOR_VOL_2_8) || \ - ((x) == BKPC_BOR_VOL_3_0) || \ - ((x) == BKPC_BOR_VOL_3_1) || \ - ((x) == BKPC_BOR_VOL_3_3) || \ - ((x) == BKPC_BOR_VOL_3_6) || \ - ((x) == BKPC_BOR_VOL_3_7) || \ - ((x) == BKPC_BOR_VOL_4_0) || \ - ((x) == BKPC_BOR_VOL_4_3)) +#define IS_BKPC_WAKEUP_PORT(x) (((x) == PMU_STANDBY_PORT_SEL_PA0) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA1) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA2) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA3) || \ + ((x) == PMU_STANDBY_PORT_SEL_NONE)) +#define IS_BKPC_WAKEUP_LEVEL(x) (((x) == PMU_STANDBY_LEVEL_HIGH) || \ + ((x) == PMU_STANDBY_LEVEL_LOW)) #define IS_BKPC_RAM_IDX(x) ((x) < 32) /** * @} @@ -154,8 +139,8 @@ typedef enum * @{ */ /* control functions */ +extern void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level); extern void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state); -extern void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state); /** * @} */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_cmu.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_cmu.h index 5bcae0bd075aa20383264f2e98295db69d5770b0..648b3c2b50cad804099fcd0216266904e822853f 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_cmu.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_cmu.h @@ -37,91 +37,91 @@ extern "C" { * @{ */ #define CMU_LOSC_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LOSC_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LRC_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LRC_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_ULRC_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_ULRC_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) /* Low power mode control */ #define CMU_LP_LRC_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LP_LRC_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LP_LOSC_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LP_LOSC_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LP_HRC_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LP_HRC_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LP_HOSC_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LP_HOSC_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) /** * @} */ @@ -133,287 +133,282 @@ extern "C" { /** * @brief CMU state structure definition */ -typedef enum -{ - CMU_CLOCK_HRC = 0x1, /**< HRC */ - CMU_CLOCK_LRC = 0x2, /**< LRC */ - CMU_CLOCK_LOSC = 0x3, /**< LOSC */ - CMU_CLOCK_PLL1 = 0x4, /**< PLL1 */ - CMU_CLOCK_HOSC = 0x5, /**< HOSC */ +typedef enum { + CMU_CLOCK_HRC = 0x1U, /**< HRC */ + CMU_CLOCK_LRC = 0x2U, /**< LRC */ + CMU_CLOCK_LOSC = 0x3U, /**< LOSC */ + CMU_CLOCK_PLL1 = 0x4U, /**< PLL1 */ + CMU_CLOCK_HOSC = 0x5U, /**< HOSC */ } cmu_clock_t; /** * @brief PLL1 output clock */ -typedef enum -{ - CMU_PLL1_OUTPUT_32M = 0x0, /**< x8 (32MHz) */ - CMU_PLL1_OUTPUT_48M = 0x1, /**< x12 (48MHz) */ +typedef enum { + CMU_PLL1_OUTPUT_32M = 0x0U, /**< x8 (32MHz) */ + CMU_PLL1_OUTPUT_48M = 0x1U, /**< x12 (48MHz) */ } cmu_pll1_output_t; /** * @brief PLL1 referance clock */ -typedef enum -{ - CMU_PLL1_INPUT_HRC_6 = 0x0, /**< HRC / 6 */ - CMU_PLL1_INPUT_PLL2 = 0x1, /**< PLL2 */ - CMU_PLL1_INPUT_HOSC = 0x2, /**< HOSC / 1 */ - CMU_PLL1_INPUT_HOSC_2 = 0x3, /**< HOSC / 2 */ - CMU_PLL1_INPUT_HOSC_3 = 0x4, /**< HOSC / 3 */ - CMU_PLL1_INPUT_HOSC_4 = 0x5, /**< HOSC / 4 */ - CMU_PLL1_INPUT_HOSC_5 = 0x6, /**< HOSC / 5 */ - CMU_PLL1_INPUT_HOSC_6 = 0x7, /**< HOSC / 6 */ +typedef enum { + CMU_PLL1_INPUT_HRC_6 = 0x0U, /**< HRC / 6 */ + CMU_PLL1_INPUT_PLL2 = 0x1U, /**< PLL2 */ + CMU_PLL1_INPUT_HOSC = 0x2U, /**< HOSC / 1 */ + CMU_PLL1_INPUT_HOSC_2 = 0x3U, /**< HOSC / 2 */ + CMU_PLL1_INPUT_HOSC_3 = 0x4U, /**< HOSC / 3 */ + CMU_PLL1_INPUT_HOSC_4 = 0x5U, /**< HOSC / 4 */ + CMU_PLL1_INPUT_HOSC_5 = 0x6U, /**< HOSC / 5 */ + CMU_PLL1_INPUT_HOSC_6 = 0x7U, /**< HOSC / 6 */ } cmu_pll1_input_t; /** * @brief HOSC range */ -typedef enum -{ - CMU_HOSC_2M = 0x0, - CMU_HOSC_4M = 0x1, - CMU_HOSC_8M = 0x2, - CMU_HOSC_16M = 0x3, - CMU_HOSC_24M = 0x4, +typedef enum { + CMU_HOSC_2M = 0x0U, /**< 0~2MHz */ + CMU_HOSC_4M = 0x1U, /**< 2~4MHz */ + CMU_HOSC_8M = 0x2U, /**< 4~8MHz */ + CMU_HOSC_16M = 0x3U, /**< 8~16MHz */ + CMU_HOSC_24M = 0x4U, /**< 16~24MHz */ } cmu_hosc_range_t; /** * @brief Auto-calibrate input */ -typedef enum -{ - CMU_AUTO_CALIB_INPUT_LOSE = 0x0, - CMU_AUTO_CALIB_INPUT_HOSE = 0x1, +typedef enum { + CMU_AUTO_CALIB_INPUT_LOSE = 0x0U, /**< LOSC */ + CMU_AUTO_CALIB_INPUT_HOSE = 0x1U, /**< HOSC */ } cmu_auto_calib_input_t; /** * @brief Auto-calibrate output */ -typedef enum -{ - CMU_AUTO_CALIB_OUTPUT_24M = 0x0, - CMU_AUTO_CALIB_OUTPUT_2M = 0x1, +typedef enum { + CMU_AUTO_CALIB_OUTPUT_24M = 0x0U, /**< HOSC 24MHz */ + CMU_AUTO_CALIB_OUTPUT_2M = 0x1U, /**< HOSC 2MHz */ } cmu_auto_calib_output_t; +/** + * @brief Safe clock source type + */ +typedef enum { + CMU_SAFE_CLK_HOSC = 0x0U, /**< HOSC */ + CMU_SAFE_CLK_LOSC = 0x1U, /**< LOSC */ + CMU_SAFE_CLK_PLL = 0x2U, /**< PLL */ +} cmu_clock_safe_type_t; + /** * @brief Frequency division select bit */ -typedef enum -{ - CMU_DIV_1 = 0x0, /**< Division by 1 */ - CMU_DIV_2 = 0x1, /**< Division by 2 */ - CMU_DIV_4 = 0x2, /**< Division by 4 */ - CMU_DIV_8 = 0x3, /**< Division by 8 */ - CMU_DIV_16 = 0x4, /**< Division by 16 */ - CMU_DIV_32 = 0x5, /**< Division by 32 */ - CMU_DIV_64 = 0x6, /**< Division by 64 */ - CMU_DIV_128 = 0x7, /**< Division by 128 */ - CMU_DIV_256 = 0x8, /**< Division by 256 */ - CMU_DIV_512 = 0x9, /**< Division by 512 */ - CMU_DIV_1024 = 0xA, /**< Division by 1024 */ - CMU_DIV_2048 = 0xB, /**< Division by 2048 */ - CMU_DIV_4096 = 0xC, /**< Division by 4096 */ +typedef enum { + CMU_DIV_1 = 0x0U, /**< Division by 1 */ + CMU_DIV_2 = 0x1U, /**< Division by 2 */ + CMU_DIV_4 = 0x2U, /**< Division by 4 */ + CMU_DIV_8 = 0x3U, /**< Division by 8 */ + CMU_DIV_16 = 0x4U, /**< Division by 16 */ + CMU_DIV_32 = 0x5U, /**< Division by 32 */ + CMU_DIV_64 = 0x6U, /**< Division by 64 */ + CMU_DIV_128 = 0x7U, /**< Division by 128 */ + CMU_DIV_256 = 0x8U, /**< Division by 256 */ + CMU_DIV_512 = 0x9U, /**< Division by 512 */ + CMU_DIV_1024 = 0xAU, /**< Division by 1024 */ + CMU_DIV_2048 = 0xBU, /**< Division by 2048 */ + CMU_DIV_4096 = 0xCU, /**< Division by 4096 */ } cmu_div_t; /** * @brief Bus type */ -typedef enum -{ - CMU_HCLK_1 = 0x0, /**< AHB1 bus */ - CMU_SYS = 0x1, /**< SYS bus */ - CMU_PCLK_1 = 0x2, /**< APB1 bus */ - CMU_PCLK_2 = 0x3, /**< APB2 bus */ +typedef enum { + CMU_HCLK_1 = 0x0U, /**< AHB1 bus */ + CMU_SYS = 0x1U, /**< SYS bus */ + CMU_PCLK_1 = 0x2U, /**< APB1 bus */ + CMU_PCLK_2 = 0x3U, /**< APB2 bus */ } cmu_bus_t; /** * @brief Output high clock select */ -typedef enum -{ - CMU_OUTPUT_HIGH_SEL_HOSC = 0x0, /**< Select HOSC */ - CMU_OUTPUT_HIGH_SEL_LOSC = 0x1, /**< Select LOSC */ - CMU_OUTPUT_HIGH_SEL_HRC = 0x2, /**< Select HRC */ - CMU_OUTPUT_HIGH_SEL_LRC = 0x3, /**< Select LRC */ - CMU_OUTPUT_HIGH_SEL_HOSM = 0x4, /**< Select HOSM */ - CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5, /**< Select PLL1 */ - CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6, /**< Select PLL2 */ - CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7, /**< Select SYSCLK */ +typedef enum { + CMU_OUTPUT_HIGH_SEL_HOSC = 0x0U, /**< Select HOSC */ + CMU_OUTPUT_HIGH_SEL_LOSC = 0x1U, /**< Select LOSC */ + CMU_OUTPUT_HIGH_SEL_HRC = 0x2U, /**< Select HRC */ + CMU_OUTPUT_HIGH_SEL_LRC = 0x3U, /**< Select LRC */ + CMU_OUTPUT_HIGH_SEL_HOSM = 0x4U, /**< Select HOSM */ + CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5U, /**< Select PLL1 */ + CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6U, /**< Select PLL2 */ + CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7U, /**< Select SYSCLK */ } cmu_output_high_sel_t; /** * @brief Output frequency division */ -typedef enum -{ - CMU_OUTPUT_DIV_1 = 0x0, /**< Division by 1 */ - CMU_OUTPUT_DIV_2 = 0x1, /**< Division by 2 */ - CMU_OUTPUT_DIV_4 = 0x2, /**< Division by 4 */ - CMU_OUTPUT_DIV_8 = 0x3, /**< Division by 8 */ - CMU_OUTPUT_DIV_16 = 0x4, /**< Division by 16 */ - CMU_OUTPUT_DIV_32 = 0x5, /**< Division by 32 */ - CMU_OUTPUT_DIV_64 = 0x6, /**< Division by 64 */ - CMU_OUTPUT_DIV_128 = 0x7, /**< Division by 128 */ +typedef enum { + CMU_OUTPUT_DIV_1 = 0x0U, /**< Division by 1 */ + CMU_OUTPUT_DIV_2 = 0x1U, /**< Division by 2 */ + CMU_OUTPUT_DIV_4 = 0x2U, /**< Division by 4 */ + CMU_OUTPUT_DIV_8 = 0x3U, /**< Division by 8 */ + CMU_OUTPUT_DIV_16 = 0x4U, /**< Division by 16 */ + CMU_OUTPUT_DIV_32 = 0x5U, /**< Division by 32 */ + CMU_OUTPUT_DIV_64 = 0x6U, /**< Division by 64 */ + CMU_OUTPUT_DIV_128 = 0x7U, /**< Division by 128 */ } cmu_output_high_div_t; /** * @brief Output low clock select */ -typedef enum -{ - CMU_OUTPUT_LOW_SEL_LOSC = 0x0, /**< Select LOSC */ - CMU_OUTPUT_LOW_SEL_LRC = 0x1, /**< Select LRC */ - CMU_OUTPUT_LOW_SEL_LOSM = 0x2, /**< Select LOSM */ - CMU_OUTPUT_LOW_SEL_BUZZ = 0x3, /**< Select BUZZ */ - CMU_OUTPUT_LOW_SEL_ULRC = 0x4, /**< Select ULRC */ +typedef enum { + CMU_OUTPUT_LOW_SEL_LOSC = 0x0U, /**< Select LOSC */ + CMU_OUTPUT_LOW_SEL_LRC = 0x1U, /**< Select LRC */ + CMU_OUTPUT_LOW_SEL_LOSM = 0x2U, /**< Select LOSM */ + CMU_OUTPUT_LOW_SEL_BUZZ = 0x3U, /**< Select BUZZ */ + CMU_OUTPUT_LOW_SEL_ULRC = 0x4U, /**< Select ULRC */ } cmu_output_low_sel_t; /** * @brief BUZZ frequency division */ -typedef enum -{ - CMU_BUZZ_DIV_2 = 0x0, /**< Division by 2 */ - CMU_BUZZ_DIV_4 = 0x1, /**< Division by 4 */ - CMU_BUZZ_DIV_8 = 0x2, /**< Division by 8 */ - CMU_BUZZ_DIV_16 = 0x3, /**< Division by 16 */ - CMU_BUZZ_DIV_32 = 0x4, /**< Division by 32 */ - CMU_BUZZ_DIV_64 = 0x5, /**< Division by 64 */ - CMU_BUZZ_DIV_128 = 0x6, /**< Division by 128 */ - CMU_BUZZ_DIV_256 = 0x7, /**< Division by 256 */ +typedef enum { + CMU_BUZZ_DIV_2 = 0x0U, /**< Division by 2 */ + CMU_BUZZ_DIV_4 = 0x1U, /**< Division by 4 */ + CMU_BUZZ_DIV_8 = 0x2U, /**< Division by 8 */ + CMU_BUZZ_DIV_16 = 0x3U, /**< Division by 16 */ + CMU_BUZZ_DIV_32 = 0x4U, /**< Division by 32 */ + CMU_BUZZ_DIV_64 = 0x5U, /**< Division by 64 */ + CMU_BUZZ_DIV_128 = 0x6U, /**< Division by 128 */ + CMU_BUZZ_DIV_256 = 0x7U, /**< Division by 256 */ } cmu_buzz_div_t; /** * @brief Low power peripheral clock select */ -typedef enum -{ - CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0, /**< Select PCLK2 */ - CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1, /**< Select PLL1 */ - CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2, /**< Select PLL2 */ - CMU_LP_PERH_CLOCK_SEL_HRC = 0x3, /**< Select HRC */ - CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4, /**< Select HOSC */ - CMU_LP_PERH_CLOCK_SEL_LRC = 0x5, /**< Select LRC */ - CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6, /**< Select LOSC */ - CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7, /**< Select ULRC */ - CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8, /**< Select HRC down to 1MHz */ - CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9, /**< Select HOSC down to 1MHz */ - CMU_LP_PERH_CLOCK_SEL_LOSM = 0xA, /**< Select LOSM */ - CMU_LP_PERH_CLOCK_SEL_HOSM = 0xB, /**< Select HOSM */ +typedef enum { + CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0U, /**< Select PCLK2 */ + CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1U, /**< Select PLL1 */ + CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2U, /**< Select PLL2 */ + CMU_LP_PERH_CLOCK_SEL_HRC = 0x3U, /**< Select HRC */ + CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4U, /**< Select HOSC */ + CMU_LP_PERH_CLOCK_SEL_LRC = 0x5U, /**< Select LRC */ + CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6U, /**< Select LOSC */ + CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7U, /**< Select ULRC */ + CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8U, /**< Select HRC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9U, /**< Select HOSC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_LOSM = 0xAU, /**< Select LOSM */ + CMU_LP_PERH_CLOCK_SEL_HOSM = 0xBU, /**< Select HOSM */ } cmu_lp_perh_clock_sel_t; /** * @brief LCD clock select */ -typedef enum -{ - CMU_LCD_SEL_LOSM = 0x0, /**< Select LOSM */ - CMU_LCD_SEL_LOSC = 0x1, /**< Select LOSC */ - CMU_LCD_SEL_LRC = 0x2, /**< Select LRC */ - CMU_LCD_SEL_ULRC = 0x3, /**< Select ULRC */ - CMU_LCD_SEL_HRC_1M = 0x4, /**< Select HRC down to 1MHz */ - CMU_LCD_SEL_HOSC_1M = 0x5, /**< Select HOSC down to 1MHz */ +typedef enum { + CMU_LCD_SEL_LOSM = 0x0U, /**< Select LOSM */ + CMU_LCD_SEL_LOSC = 0x1U, /**< Select LOSC */ + CMU_LCD_SEL_LRC = 0x2U, /**< Select LRC */ + CMU_LCD_SEL_ULRC = 0x3U, /**< Select ULRC */ + CMU_LCD_SEL_HRC_1M = 0x4U, /**< Select HRC down to 1MHz */ + CMU_LCD_SEL_HOSC_1M = 0x5U, /**< Select HOSC down to 1MHz */ } cmu_lcd_clock_sel_t; /** * @brief Peripheral clock enable/disable - * @note ES32F065x: - * AD16C4T0--TIMER0 - * GP16C4T0--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - * - * ES32F033x: - * ES32F093x: - * GP16C4T0--TIMER0 - * GP16C4T1--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - */ -typedef enum -{ - CMU_PERH_GPIO = (1U << 0), /**< GPIO */ - CMU_PERH_CRC = (1U << 1), /**< CRC */ - CMU_PERH_CALC = (1U << 2), /**< CALC */ - CMU_PERH_CRYPT = (1U << 3), /**< CRYPT */ - CMU_PERH_TRNG = (1U << 4), /**< TRNG */ - CMU_PERH_PIS = (1U << 5), /**< PIS */ - CMU_PERH_TIMER0 = (1U << 0) | (1U << 27), /**< TIMER0 */ - CMU_PERH_TIMER1 = (1U << 1) | (1U << 27), /**< TIMER1 */ - CMU_PERH_TIMER2 = (1U << 2) | (1U << 27), /**< TIMER2 */ - CMU_PERH_TIMER3 = (1U << 3) | (1U << 27), /**< TIMER3 */ - CMU_PERH_TIMER4 = (1U << 4) | (1U << 27), /**< TIMER4 */ - CMU_PERH_TIMER5 = (1U << 5) | (1U << 27), /**< TIMER5 */ - CMU_PERH_TIMER6 = (1U << 6) | (1U << 27), /**< TIMER6 */ - CMU_PERH_TIMER7 = (1U << 7) | (1U << 27), /**< TIMER7 */ - CMU_PERH_UART0 = (1U << 8) | (1U << 27), /**< UART0 */ - CMU_PERH_UART1 = (1U << 9) | (1U << 27), /**< UART1 */ - CMU_PERH_UART2 = (1U << 10) | (1U << 27), /**< UART2 */ - CMU_PERH_UART3 = (1U << 11) | (1U << 27), /**< UART3 */ - CMU_PERH_USART0 = (1U << 12) | (1U << 27), /**< USART0 */ - CMU_PERH_USART1 = (1U << 13) | (1U << 27), /**< USART1 */ - CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ - CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ - CMU_PERH_SPI2 = (1U << 18) | (1U << 27), /**< SPI2 */ - CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ - CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ - CMU_PERH_CAN = (1U << 24) | (1U << 27), /**< CAN */ - CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), /**< LPTIM0 */ - CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), /**< LPUART0 */ - CMU_PERH_ADC0 = (1U << 4) | (1U << 28), /**< ADC0 */ - CMU_PERH_ADC1 = (1U << 5) | (1U << 28), /**< ADC1 */ - CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), /**< ACMP0 */ - CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), /**< ACMP1 */ - CMU_PERH_OPAMP = (1U << 8) | (1U << 28), /**< OPAMP */ - CMU_PERH_DAC0 = (1U << 9) | (1U << 28), /**< DAC0 */ - CMU_PERH_WWDT = (1U << 12) | (1U << 28), /**< WWDT */ - CMU_PERH_LCD = (1U << 13) | (1U << 28), /**< LCD */ - CMU_PERH_IWDT = (1U << 14) | (1U << 28), /**< IWDT */ - CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */ - CMU_PERH_TSENSE = (1U << 16) | (1U << 28), /**< TSENSE */ - CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */ - CMU_PERH_BKRPAM = (1U << 18) | (1U << 28), /**< BKPRAM */ - CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */ - CMU_PERH_ALL = (0x7FFFFFFF), /**< ALL */ + * @verbatim + In this module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F065x series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + TIMER4 ----> BS16T1 + TIMER5 ----> BS16T2 + TIMER6 ----> GP16C4T0 + TIMER7 ----> BS16T3 + + 2. For ES32F033x/ES32F093x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + TIMER4 ----> BS16T1 + TIMER5 ----> BS16T2 + TIMER6 ----> GP16C4T1 + TIMER7 ----> BS16T3 + @endverbatim + */ +typedef enum { + CMU_PERH_GPIO = (1U << 0), /**< GPIO */ + CMU_PERH_CRC = (1U << 1), /**< CRC */ + CMU_PERH_CALC = (1U << 2), /**< CALC */ + CMU_PERH_CRYPT = (1U << 3), /**< CRYPT */ + CMU_PERH_TRNG = (1U << 4), /**< TRNG */ + CMU_PERH_PIS = (1U << 5), /**< PIS */ + CMU_PERH_TIMER0 = (1U << 0) | (1U << 27), /**< TIMER0 */ + CMU_PERH_TIMER1 = (1U << 1) | (1U << 27), /**< TIMER1 */ + CMU_PERH_TIMER2 = (1U << 2) | (1U << 27), /**< TIMER2 */ + CMU_PERH_TIMER3 = (1U << 3) | (1U << 27), /**< TIMER3 */ + CMU_PERH_TIMER4 = (1U << 4) | (1U << 27), /**< TIMER4 */ + CMU_PERH_TIMER5 = (1U << 5) | (1U << 27), /**< TIMER5 */ + CMU_PERH_TIMER6 = (1U << 6) | (1U << 27), /**< TIMER6 */ + CMU_PERH_TIMER7 = (1U << 7) | (1U << 27), /**< TIMER7 */ + CMU_PERH_UART0 = (1U << 8) | (1U << 27), /**< UART0 */ + CMU_PERH_UART1 = (1U << 9) | (1U << 27), /**< UART1 */ + CMU_PERH_UART2 = (1U << 10) | (1U << 27), /**< UART2 */ + CMU_PERH_UART3 = (1U << 11) | (1U << 27), /**< UART3 */ + CMU_PERH_USART0 = (1U << 12) | (1U << 27), /**< USART0 */ + CMU_PERH_USART1 = (1U << 13) | (1U << 27), /**< USART1 */ + CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ + CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ + CMU_PERH_SPI2 = (1U << 18) | (1U << 27), /**< SPI2 */ + CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ + CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ + CMU_PERH_CAN = (1U << 24) | (1U << 27), /**< CAN */ + CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), /**< LPTIM0 */ + CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), /**< LPUART0 */ + CMU_PERH_ADC0 = (1U << 4) | (1U << 28), /**< ADC0 */ + CMU_PERH_ADC1 = (1U << 5) | (1U << 28), /**< ADC1 */ + CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), /**< ACMP0 */ + CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), /**< ACMP1 */ + CMU_PERH_OPAMP = (1U << 8) | (1U << 28), /**< OPAMP */ + CMU_PERH_DAC0 = (1U << 9) | (1U << 28), /**< DAC0 */ + CMU_PERH_WWDT = (1U << 12) | (1U << 28), /**< WWDT */ + CMU_PERH_LCD = (1U << 13) | (1U << 28), /**< LCD */ + CMU_PERH_IWDT = (1U << 14) | (1U << 28), /**< IWDT */ + CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */ + CMU_PERH_TSENSE = (1U << 16) | (1U << 28), /**< TSENSE */ + CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */ + CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */ + CMU_PERH_ALL = (0x7FFFFFFF), /**< ALL */ } cmu_perh_t; /** * @brief CMU interrupt type */ -typedef enum -{ - CMU_LOSC_STOP = 0x0, /**< LOSC STOP INTERRUPT */ - CMU_HOSC_STOP = 0x1, /**< HOSC STOP INTERRUPT */ - CMU_PLL1_UNLOCK = 0x2, /**< PLL1 UNLOCK INTERRUPT */ - CMU_LOSC_START = 0x3, /**< LOSC START INTERRUPT */ - CMU_HOSC_START = 0x4, /**< HOSC START INTERRUPT */ +typedef enum { + CMU_LOSC_STOP = 0x0U, /**< LOSC STOP INTERRUPT */ + CMU_HOSC_STOP = 0x1U, /**< HOSC STOP INTERRUPT */ + CMU_PLL1_UNLOCK = 0x2U, /**< PLL1 UNLOCK INTERRUPT */ + CMU_LOSC_START = 0x3U, /**< LOSC START INTERRUPT */ + CMU_HOSC_START = 0x4U, /**< HOSC START INTERRUPT */ } cmu_security_t; /** * @brief CMU clock state type */ -typedef enum -{ - CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ - CMU_CLOCK_STATE_LOSCACT = (1U << 1), /**< LOSC active */ - CMU_CLOCK_STATE_HRCACT = (1U << 2), /**< HRC active */ - CMU_CLOCK_STATE_LRCACT = (1U << 3), /**< LRC active */ - CMU_CLOCK_STATE_ULRCACT = (1U << 4), /**< ULRC active */ - CMU_CLOCK_STATE_PLLACT = (1U << 8), /**< PLL active */ - CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ - CMU_CLOCK_STATE_LOSCRDY = (1U << 17), /**< LOSC ready */ - CMU_CLOCK_STATE_HRCRDY = (1U << 18), /**< HRC ready */ - CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ - CMU_CLOCK_STATE_PLLRDY = (1U << 24), /**< PLL ready */ +typedef enum { + CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ + CMU_CLOCK_STATE_LOSCACT = (1U << 1), /**< LOSC active */ + CMU_CLOCK_STATE_HRCACT = (1U << 2), /**< HRC active */ + CMU_CLOCK_STATE_LRCACT = (1U << 3), /**< LRC active */ + CMU_CLOCK_STATE_ULRCACT = (1U << 4), /**< ULRC active */ + CMU_CLOCK_STATE_PLLACT = (1U << 8), /**< PLL active */ + CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ + CMU_CLOCK_STATE_LOSCRDY = (1U << 17), /**< LOSC ready */ + CMU_CLOCK_STATE_HRCRDY = (1U << 18), /**< HRC ready */ + CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ + CMU_CLOCK_STATE_PLLRDY = (1U << 24), /**< PLL ready */ } cmu_clock_state_t; /** * @} @@ -424,10 +419,10 @@ typedef enum * @{ */ #define IS_CMU_CLOCK(x) (((x) == CMU_CLOCK_HRC) || \ - ((x) == CMU_CLOCK_LRC) || \ - ((x) == CMU_CLOCK_LOSC) || \ - ((x) == CMU_CLOCK_PLL1) || \ - ((x) == CMU_CLOCK_HOSC)) + ((x) == CMU_CLOCK_LRC) || \ + ((x) == CMU_CLOCK_LOSC) || \ + ((x) == CMU_CLOCK_PLL1) || \ + ((x) == CMU_CLOCK_HOSC)) #define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_32M) || \ ((x) == CMU_PLL1_OUTPUT_48M)) #define IS_CMU_PLL1_INPUT(x) (((x) == CMU_PLL1_INPUT_HRC_6) || \ @@ -444,67 +439,70 @@ typedef enum ((x) == CMU_HOSC_16M) || \ ((x) == CMU_HOSC_24M)) #define IS_CMU_DIV(x) (((x) == CMU_DIV_1) || \ - ((x) == CMU_DIV_2) || \ - ((x) == CMU_DIV_4) || \ - ((x) == CMU_DIV_8) || \ - ((x) == CMU_DIV_16) || \ - ((x) == CMU_DIV_32) || \ - ((x) == CMU_DIV_64) || \ - ((x) == CMU_DIV_128) || \ - ((x) == CMU_DIV_256) || \ - ((x) == CMU_DIV_512) || \ - ((x) == CMU_DIV_1024) || \ - ((x) == CMU_DIV_2048) || \ - ((x) == CMU_DIV_4096)) + ((x) == CMU_DIV_2) || \ + ((x) == CMU_DIV_4) || \ + ((x) == CMU_DIV_8) || \ + ((x) == CMU_DIV_16) || \ + ((x) == CMU_DIV_32) || \ + ((x) == CMU_DIV_64) || \ + ((x) == CMU_DIV_128) || \ + ((x) == CMU_DIV_256) || \ + ((x) == CMU_DIV_512) || \ + ((x) == CMU_DIV_1024) || \ + ((x) == CMU_DIV_2048) || \ + ((x) == CMU_DIV_4096)) #define IS_CMU_BUS(x) (((x) == CMU_HCLK_1) || \ - ((x) == CMU_SYS) || \ - ((x) == CMU_PCLK_1) || \ - ((x) == CMU_PCLK_2)) + ((x) == CMU_SYS) || \ + ((x) == CMU_PCLK_1) || \ + ((x) == CMU_PCLK_2)) #define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_HRC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_LRC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK)) + ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_HRC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_LRC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK)) #define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == CMU_OUTPUT_DIV_1) || \ - ((x) == CMU_OUTPUT_DIV_2) || \ - ((x) == CMU_OUTPUT_DIV_4) || \ - ((x) == CMU_OUTPUT_DIV_8) || \ - ((x) == CMU_OUTPUT_DIV_16) || \ - ((x) == CMU_OUTPUT_DIV_32) || \ - ((x) == CMU_OUTPUT_DIV_64) || \ - ((x) == CMU_OUTPUT_DIV_128)) + ((x) == CMU_OUTPUT_DIV_2) || \ + ((x) == CMU_OUTPUT_DIV_4) || \ + ((x) == CMU_OUTPUT_DIV_8) || \ + ((x) == CMU_OUTPUT_DIV_16) || \ + ((x) == CMU_OUTPUT_DIV_32) || \ + ((x) == CMU_OUTPUT_DIV_64) || \ + ((x) == CMU_OUTPUT_DIV_128)) #define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \ - ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \ - ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \ - ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \ - ((x) == CMU_OUTPUT_LOW_SEL_ULRC)) + ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \ + ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \ + ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \ + ((x) == CMU_OUTPUT_LOW_SEL_ULRC)) #define IS_CMU_AUTO_CALIB_INPUT(x) (((x) == CMU_AUTO_CALIB_INPUT_LOSE) || \ - ((x) == CMU_AUTO_CALIB_INPUT_HOSE)) + ((x) == CMU_AUTO_CALIB_INPUT_HOSE)) #define IS_CMU_AUTO_CALIB_OUTPUT(x) (((x) == CMU_AUTO_CALIB_OUTPUT_24M) || \ - ((x) == CMU_AUTO_CALIB_OUTPUT_2M)) + ((x) == CMU_AUTO_CALIB_OUTPUT_2M)) +#define IS_CMU_SAFE_CLOCK_TYPE(x) (((x) == CMU_SAFE_CLK_HOSC) || \ + ((x) == CMU_SAFE_CLK_LOSC) || \ + ((x) == CMU_SAFE_CLK_PLL)) #define IS_CMU_BUZZ_DIV(x) (((x) == CMU_BUZZ_DIV_2) || \ - ((x) == CMU_BUZZ_DIV_4) || \ - ((x) == CMU_BUZZ_DIV_8) || \ - ((x) == CMU_BUZZ_DIV_16) || \ - ((x) == CMU_BUZZ_DIV_32) || \ - ((x) == CMU_BUZZ_DIV_64) || \ - ((x) == CMU_BUZZ_DIV_128) || \ - ((x) == CMU_BUZZ_DIV_256)) + ((x) == CMU_BUZZ_DIV_4) || \ + ((x) == CMU_BUZZ_DIV_8) || \ + ((x) == CMU_BUZZ_DIV_16) || \ + ((x) == CMU_BUZZ_DIV_32) || \ + ((x) == CMU_BUZZ_DIV_64) || \ + ((x) == CMU_BUZZ_DIV_128) || \ + ((x) == CMU_BUZZ_DIV_256)) #define IS_CMU_LP_PERH_CLOCK_SEL(x) (((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HRC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_LRC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM)) + ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM)) #define IS_CMU_LCD_CLOCK_SEL(x) (((x) == CMU_LCD_SEL_LOSM) || \ ((x) == CMU_LCD_SEL_LOSC) || \ ((x) == CMU_LCD_SEL_LRC) || \ @@ -512,59 +510,58 @@ typedef enum ((x) == CMU_LCD_SEL_HRC_1M) || \ ((x) == CMU_LCD_SEL_HOSC_1M)) #define IS_CMU_PERH(x) (((x) == CMU_PERH_GPIO) || \ - ((x) == CMU_PERH_CRC) || \ - ((x) == CMU_PERH_CALC) || \ - ((x) == CMU_PERH_CRYPT) || \ - ((x) == CMU_PERH_TRNG) || \ - ((x) == CMU_PERH_PIS) || \ - ((x) == CMU_PERH_TIMER0) || \ - ((x) == CMU_PERH_TIMER1) || \ - ((x) == CMU_PERH_TIMER2) || \ - ((x) == CMU_PERH_TIMER3) || \ - ((x) == CMU_PERH_TIMER4) || \ - ((x) == CMU_PERH_TIMER5) || \ - ((x) == CMU_PERH_TIMER6) || \ - ((x) == CMU_PERH_TIMER7) || \ - ((x) == CMU_PERH_UART0) || \ - ((x) == CMU_PERH_UART1) || \ - ((x) == CMU_PERH_UART2) || \ - ((x) == CMU_PERH_UART3) || \ - ((x) == CMU_PERH_USART0) || \ - ((x) == CMU_PERH_USART1) || \ - ((x) == CMU_PERH_SPI0) || \ - ((x) == CMU_PERH_SPI1) || \ - ((x) == CMU_PERH_SPI2) || \ - ((x) == CMU_PERH_I2C0) || \ - ((x) == CMU_PERH_I2C1) || \ - ((x) == CMU_PERH_CAN) || \ - ((x) == CMU_PERH_LPTIM0) || \ - ((x) == CMU_PERH_LPUART0) || \ - ((x) == CMU_PERH_ADC0) || \ - ((x) == CMU_PERH_ADC1) || \ - ((x) == CMU_PERH_ACMP0) || \ - ((x) == CMU_PERH_ACMP1) || \ - ((x) == CMU_PERH_OPAMP) || \ - ((x) == CMU_PERH_DAC0) || \ - ((x) == CMU_PERH_WWDT) || \ - ((x) == CMU_PERH_LCD) || \ - ((x) == CMU_PERH_IWDT) || \ - ((x) == CMU_PERH_RTC) || \ - ((x) == CMU_PERH_TSENSE) || \ - ((x) == CMU_PERH_BKPC) || \ - ((x) == CMU_PERH_BKRPAM ) || \ - ((x) == CMU_PERH_DBGC) || \ - ((x) == CMU_PERH_ALL)) + ((x) == CMU_PERH_CRC) || \ + ((x) == CMU_PERH_CALC) || \ + ((x) == CMU_PERH_CRYPT) || \ + ((x) == CMU_PERH_TRNG) || \ + ((x) == CMU_PERH_PIS) || \ + ((x) == CMU_PERH_TIMER0) || \ + ((x) == CMU_PERH_TIMER1) || \ + ((x) == CMU_PERH_TIMER2) || \ + ((x) == CMU_PERH_TIMER3) || \ + ((x) == CMU_PERH_TIMER4) || \ + ((x) == CMU_PERH_TIMER5) || \ + ((x) == CMU_PERH_TIMER6) || \ + ((x) == CMU_PERH_TIMER7) || \ + ((x) == CMU_PERH_UART0) || \ + ((x) == CMU_PERH_UART1) || \ + ((x) == CMU_PERH_UART2) || \ + ((x) == CMU_PERH_UART3) || \ + ((x) == CMU_PERH_USART0) || \ + ((x) == CMU_PERH_USART1) || \ + ((x) == CMU_PERH_SPI0) || \ + ((x) == CMU_PERH_SPI1) || \ + ((x) == CMU_PERH_SPI2) || \ + ((x) == CMU_PERH_I2C0) || \ + ((x) == CMU_PERH_I2C1) || \ + ((x) == CMU_PERH_CAN) || \ + ((x) == CMU_PERH_LPTIM0) || \ + ((x) == CMU_PERH_LPUART0) || \ + ((x) == CMU_PERH_ADC0) || \ + ((x) == CMU_PERH_ADC1) || \ + ((x) == CMU_PERH_ACMP0) || \ + ((x) == CMU_PERH_ACMP1) || \ + ((x) == CMU_PERH_OPAMP) || \ + ((x) == CMU_PERH_DAC0) || \ + ((x) == CMU_PERH_WWDT) || \ + ((x) == CMU_PERH_LCD) || \ + ((x) == CMU_PERH_IWDT) || \ + ((x) == CMU_PERH_RTC) || \ + ((x) == CMU_PERH_TSENSE) || \ + ((x) == CMU_PERH_BKPC) || \ + ((x) == CMU_PERH_DBGC) || \ + ((x) == CMU_PERH_ALL)) #define IS_CMU_CLOCK_STATE(x) (((x) == CMU_CLOCK_STATE_HOSCACT) || \ ((x) == CMU_CLOCK_STATE_LOSCACT) || \ - ((x) == CMU_CLOCK_STATE_HRCACT) || \ - ((x) == CMU_CLOCK_STATE_LRCACT) || \ - ((x) == CMU_CLOCK_STATE_ULRCACT) || \ - ((x) == CMU_CLOCK_STATE_PLLACT) || \ - ((x) == CMU_CLOCK_STATE_HOSCRDY) || \ - ((x) == CMU_CLOCK_STATE_LOSCRDY) || \ - ((x) == CMU_CLOCK_STATE_HRCRDY) || \ - ((x) == CMU_CLOCK_STATE_LRCRDY) || \ - ((x) == CMU_CLOCK_STATE_PLLRDY)) + ((x) == CMU_CLOCK_STATE_HRCACT) || \ + ((x) == CMU_CLOCK_STATE_LRCACT) || \ + ((x) == CMU_CLOCK_STATE_ULRCACT) || \ + ((x) == CMU_CLOCK_STATE_PLLACT) || \ + ((x) == CMU_CLOCK_STATE_HOSCRDY) || \ + ((x) == CMU_CLOCK_STATE_LOSCRDY) || \ + ((x) == CMU_CLOCK_STATE_HRCRDY) || \ + ((x) == CMU_CLOCK_STATE_LRCRDY) || \ + ((x) == CMU_CLOCK_STATE_PLLRDY)) /** * @} */ @@ -605,6 +602,7 @@ uint32_t ald_cmu_get_pclk2_clock(void); void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status); void ald_cmu_losc_safe_config(type_func_t status); void ald_cmu_pll_safe_config(type_func_t status); +uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type); flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr); void ald_cmu_irq_handler(void); void ald_cmu_irq_cbk(cmu_security_t se); @@ -617,7 +615,7 @@ void ald_cmu_irq_cbk(cmu_security_t se); */ /* Clock output configure */ void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, - cmu_output_high_div_t div, type_func_t status); + cmu_output_high_div_t div, type_func_t status); void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status); /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crc.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crc.h index e3281dc166891a72aae047822aacfed3f1568c26..3ea24ea92734ec25a368dc259bd4b387234f8c8b 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crc.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crc.h @@ -18,7 +18,7 @@ #define __ALD_CRC_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -39,75 +39,69 @@ extern "C" { /** * @brief CRC mode */ -typedef enum -{ - CRC_MODE_CCITT = 0, /**< Ccitt */ - CRC_MODE_8 = 1, /**< Crc8 */ - CRC_MODE_16 = 2, /**< Crc16 */ - CRC_MODE_32 = 3, /**< Crc32 */ +typedef enum { + CRC_MODE_CCITT = 0U, /**< Ccitt */ + CRC_MODE_8 = 1U, /**< Crc8 */ + CRC_MODE_16 = 2U, /**< Crc16 */ + CRC_MODE_32 = 3U, /**< Crc32 */ } crc_mode_t; /** * @brief CRC input length */ -typedef enum -{ - CRC_LEN_AUTO = 0, /**< Auto */ - CRC_DATASIZE_8 = 1, /**< Byte */ - CRC_DATASIZE_16 = 2, /**< Half word */ - CRC_DATASIZE_32 = 3, /**< Word */ +typedef enum { + CRC_LEN_AUTO = 0U, /**< Auto */ + CRC_DATASIZE_8 = 1U, /**< Byte */ + CRC_DATASIZE_16 = 2U, /**< Half word */ + CRC_DATASIZE_32 = 3U, /**< Word */ } crc_datasize_t; /** * @brief CRC whether write error or no */ -typedef enum -{ - CRC_WERR_NO = 0, /**< No error */ - CRC_WERR_ERR = 1, /**< Error */ +typedef enum { + CRC_WERR_NO = 0U, /**< No error */ + CRC_WERR_ERR = 1U, /**< Error */ } crc_werr_t; /** * @brief CRC state structures definition */ -typedef enum -{ - CRC_STATE_RESET = 0x0, /**< Peripheral is not initialized */ - CRC_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - CRC_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - CRC_STATE_ERROR = 0x4, /**< Error */ +typedef enum { + CRC_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ + CRC_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + CRC_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + CRC_STATE_ERROR = 0x4U, /**< Error */ } crc_state_t; /** * @brief CRC init structure definition */ -typedef struct -{ - crc_mode_t mode; /**< CRC mode */ - type_func_t data_rev; /**< CRC data reverse or no */ - type_func_t data_inv; /**< CRC data inverse or no */ - type_func_t chs_rev; /**< CRC check sum reverse or no */ - type_func_t chs_inv; /**< CRC check sum inverse or no */ - uint32_t seed; /**< CRC seed */ +typedef struct { + crc_mode_t mode; /**< CRC mode */ + type_func_t data_rev; /**< CRC data reverse or no */ + type_func_t data_inv; /**< CRC data inverse or no */ + type_func_t chs_rev; /**< CRC check sum reverse or no */ + type_func_t chs_inv; /**< CRC check sum inverse or no */ + uint32_t seed; /**< CRC seed */ } crc_init_t; /** * @brief CRC Handle Structure definition */ -typedef struct crc_handle_s -{ - CRC_TypeDef *perh; /**< Register base address */ - crc_init_t init; /**< CRC required parameters */ - uint8_t *cal_buf; /**< The pointer of preparing buffer */ - uint32_t *cal_res; /**< The pointer of result */ +typedef struct crc_handle_s { + CRC_TypeDef *perh; /**< Register base address */ + crc_init_t init; /**< CRC required parameters */ + uint8_t *cal_buf; /**< The pointer of preparing buffer */ + uint32_t *cal_res; /**< The pointer of result */ #ifdef ALD_DMA - dma_handle_t hdma; /**< CRC DMA handle parameters */ + dma_handle_t hdma; /**< CRC DMA handle parameters */ #endif - lock_state_t lock; /**< Locking object */ - crc_state_t state; /**< CRC operation state */ + lock_state_t lock; /**< Locking object */ + crc_state_t state; /**< CRC operation state */ - void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */ - void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */ + void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */ + void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */ } crc_handle_t; /** * @} @@ -131,9 +125,9 @@ typedef struct crc_handle_s */ #define IS_CRC(x) ((x) == CRC) #define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \ - ((x) == CRC_MODE_8) || \ - ((x) == CRC_MODE_16) || \ - ((x) == CRC_MODE_32)) + ((x) == CRC_MODE_8) || \ + ((x) == CRC_MODE_16) || \ + ((x) == CRC_MODE_32)) /** * @} */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crypt.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crypt.h index 18340558a2d5e6b2c805d2b2035025bcec1b3e6a..483c15a31e674030fe34830bdb712c43238392db 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crypt.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crypt.h @@ -18,7 +18,7 @@ #define __ALD_CRYPT_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -39,105 +39,96 @@ extern "C" { /** * @brief CRYPT encrypt or decrypt select */ -typedef enum -{ - CRYPT_DECRYPT = 0, /**< Decrypt */ - CRYPT_ENCRYPT = 1, /**< Encrypt */ +typedef enum { + CRYPT_DECRYPT = 0U, /**< Decrypt */ + CRYPT_ENCRYPT = 1U, /**< Encrypt */ } crypt_encs_t; /** * @brief CRYPT mode select */ -typedef enum -{ - CRYPT_MODE_ECB = 0, /**< ECB */ - CRYPT_MODE_CBC = 1, /**< CBC */ - CRYPT_MODE_CTR = 2, /**< CTR */ +typedef enum { + CRYPT_MODE_ECB = 0U, /**< ECB */ + CRYPT_MODE_CBC = 1U, /**< CBC */ + CRYPT_MODE_CTR = 2U, /**< CTR */ } crypt_mode_t; /** * @brief CRYPT data type */ -typedef enum -{ - CRYPT_DATA_CHANGE_NO = 0, /**< No exchange */ - CRYPT_DATA_CHANGE_16 = 1, /**< 16bit exchange */ - CRYPT_DATA_CHANGE_8 = 2, /**< 8bit exchange */ - CRYPT_DATA_CHANGE_1 = 3, /**< 1bit exchange */ +typedef enum { + CRYPT_DATA_CHANGE_NO = 0U, /**< No exchange */ + CRYPT_DATA_CHANGE_16 = 1U, /**< 16bit exchange */ + CRYPT_DATA_CHANGE_8 = 2U, /**< 8bit exchange */ + CRYPT_DATA_CHANGE_1 = 3U, /**< 1bit exchange */ } crypt_datatype_t; /** * @brief CRYPT interrupt */ -typedef enum -{ - CRYPT_IT_IT = 0x80, /**< Interrupt */ +typedef enum { + CRYPT_IT_IT = 0x80U, /**< Interrupt */ } crypt_it_t; /** * @brief CRYPT interrupt flag */ -typedef enum -{ - CRYPT_FLAG_AESIF = 0x1, /**< Aes flag */ - CRYPT_FLAG_DONE = 0x100, /**< Complete flag */ +typedef enum { + CRYPT_FLAG_AESIF = 0x1U, /**< Aes flag */ + CRYPT_FLAG_DONE = 0x100U, /**< Complete flag */ } crypt_flag_t; /** * @brief CRYPT state structures definition */ -typedef enum -{ - CRYPT_STATE_RESET = 0x0, /**< Peripheral is not initialized */ - CRYPT_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - CRYPT_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - CRYPT_STATE_ERROR = 0x4, /**< Error */ +typedef enum { + CRYPT_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ + CRYPT_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + CRYPT_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + CRYPT_STATE_ERROR = 0x4U, /**< Error */ } crypt_state_t; /** * @brief CRYPT data type */ -typedef enum -{ - DATA_32_BIT = 0, /**< 32 bit data,don't swap */ - DATA_16_BIT = 1, /**< 16 bit data,swap */ - DATA_8_BIT = 2, /**< 8 bit data,swap */ - DATA_1_BIT = 3, /**< 1 bit data, swap */ +typedef enum { + DATA_32_BIT = 0U, /**< 32 bit data,don't swap */ + DATA_16_BIT = 1U, /**< 16 bit data,swap */ + DATA_8_BIT = 2U, /**< 8 bit data,swap */ + DATA_1_BIT = 3U, /**< 1 bit data, swap */ } crypt_data_t; /** * @brief CRYPT init structure definition */ -typedef struct -{ - crypt_mode_t mode; /**< Crypt mode */ - crypt_data_t type; /**< Data type select */ +typedef struct { + crypt_mode_t mode; /**< Crypt mode */ + crypt_data_t type; /**< Data type select */ } crypt_init_t; /** * @brief CRYPT Handle Structure definition */ -typedef struct crypt_handle_s -{ - CRYPT_TypeDef *perh; /**< Register base address */ - crypt_init_t init; /**< CRYPT required parameters */ +typedef struct crypt_handle_s { + CRYPT_TypeDef *perh; /**< Register base address */ + crypt_init_t init; /**< CRYPT required parameters */ #ifdef ALD_DMA - dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */ - dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */ + dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */ + dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */ #endif - uint8_t *plain_text; /**< Pointer to plain text */ - uint8_t *cipher_text; /**< Pointer to cipher text */ - uint32_t size; /**< The size of crypt data buf */ - uint32_t count; /**< The count of crypt data buf */ - uint32_t step; /**< The step of once crypt 4(aes) */ - uint32_t dir; /**< ENCRYPT or DECRYPT */ - uint32_t iv[4]; /**< The iv of crypt */ - uint32_t key[4]; /**< The key of crypt */ - lock_state_t lock; /**< Locking object */ - crypt_state_t state; /**< CRYPT operation state */ - - void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */ - void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */ + uint8_t *plain_text; /**< Pointer to plain text */ + uint8_t *cipher_text; /**< Pointer to cipher text */ + uint32_t size; /**< The size of crypt data buf */ + uint32_t count; /**< The count of crypt data buf */ + uint32_t step; /**< The step of once crypt 4(aes) */ + uint32_t dir; /**< ENCRYPT or DECRYPT */ + uint32_t iv[4]; /**< The iv of crypt */ + uint32_t key[4]; /**< The key of crypt */ + lock_state_t lock; /**< Locking object */ + crypt_state_t state; /**< CRYPT operation state */ + + void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */ + void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */ } crypt_handle_t; /** * @} @@ -148,7 +139,7 @@ typedef struct crypt_handle_s */ #define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK)) #define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) -#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) +#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) #define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) #define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) #define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) @@ -156,7 +147,7 @@ typedef struct crypt_handle_s #define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) #define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) #define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \ - (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0) + (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0) #define CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data)) #define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO) /** @@ -168,13 +159,13 @@ typedef struct crypt_handle_s */ #define IS_CRYPT(x) ((x) == CRYPT) #define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \ - ((x) == CRYPT_MODE_CBC) || \ - ((x) == CRYPT_MODE_CTR)) + ((x) == CRYPT_MODE_CBC) || \ + ((x) == CRYPT_MODE_CTR)) #define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT) #define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \ - ((x) == CRYPT_FLAG_DONE)) + ((x) == CRYPT_FLAG_DONE)) #define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \ - ((x) == IV_4_LEN)) + ((x) == IV_4_LEN)) /** * @} */ @@ -205,9 +196,9 @@ ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); #ifdef ALD_DMA ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, - uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); + uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, - uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); + uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); #endif /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dbgc.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dbgc.h index 31b8dc6ca40a811eca70ef4dd86608feec96534b..3f695b7e8f477a5949dcb331ecf9293e27a35c4f 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dbgc.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dbgc.h @@ -18,7 +18,7 @@ #define __ALD_DBGC_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -41,34 +41,32 @@ extern "C" { /** * @brief Debug mode select */ -typedef enum -{ - DEBC_MODE_SLEEP = (1u << 0), /**< Sleep mode */ - DEBC_MODE_STOP1 = (1u << 1), /**< STOP1 mode */ - DEBC_MODE_STOP2 = (1u << 2), /**< STOP2 mode */ - DEBC_MODE_STANDBY = (1u << 3), /**< Standby mode */ +typedef enum { + DEBC_MODE_SLEEP = (1U << 0), /**< Sleep mode */ + DEBC_MODE_STOP1 = (1U << 1), /**< STOP1 mode */ + DEBC_MODE_STOP2 = (1U << 2), /**< STOP2 mode */ + DEBC_MODE_STANDBY = (1U << 3), /**< Standby mode */ } dbgc_mode_t; /** * @brief Debug peripheral select */ -typedef enum -{ - DEBC_PERH_TIMER0 = (1u << 0), /**< AD16C4T0 */ - DEBC_PERH_TIMER1 = (1u << 1), /**< BS16T0 */ - DEBC_PERH_TIMER2 = (1u << 2), /**< GP16C2T0 */ - DEBC_PERH_TIMER3 = (1u << 3), /**< GP16C2T1 */ - DEBC_PERH_TIMER4 = (1u << 4), /**< BS16T1 */ - DEBC_PERH_TIMER5 = (1u << 5), /**< BS16T2 */ - DEBC_PERH_TIMER6 = (1u << 6), /**< GP16C4T0 */ - DEBC_PERH_TIMER7 = (1u << 7), /**< BS16T3 */ - DEBC_PERH_I2C0 = (1u << 8), /**< I2C0 SMBUS */ - DEBC_PERH_I2C1 = (1u << 9), /**< I2C1 SMBUS */ - DEBC_PERH_CAN = (1u << 12), /**< CAN */ - DEBC_PERH_LPTIM0 = (1u << 0) | (1u << 16), /**< LPTIM0 */ - DEBC_PERH_IWDT = (1u << 8) | (1u << 16), /**< IWDT */ - DEBC_PERH_WWDT = (1u << 9) | (1u << 16), /**< WWDT */ - DEBC_PERH_RTC = (1u << 10) | (1u << 16), /**< RTC */ +typedef enum { + DEBC_PERH_TIMER0 = (1U << 0), /**< AD16C4T0 */ + DEBC_PERH_TIMER1 = (1U << 1), /**< BS16T0 */ + DEBC_PERH_TIMER2 = (1U << 2), /**< GP16C2T0 */ + DEBC_PERH_TIMER3 = (1U << 3), /**< GP16C2T1 */ + DEBC_PERH_TIMER4 = (1U << 4), /**< BS16T1 */ + DEBC_PERH_TIMER5 = (1U << 5), /**< BS16T2 */ + DEBC_PERH_TIMER6 = (1U << 6), /**< GP16C4T0 */ + DEBC_PERH_TIMER7 = (1U << 7), /**< BS16T3 */ + DEBC_PERH_I2C0 = (1U << 8), /**< I2C0 SMBUS */ + DEBC_PERH_I2C1 = (1U << 9), /**< I2C1 SMBUS */ + DEBC_PERH_CAN = (1U << 12), /**< CAN */ + DEBC_PERH_LPTIM0 = (1U << 0) | (1U << 16), /**< LPTIM0 */ + DEBC_PERH_IWDT = (1U << 8) | (1U << 16), /**< IWDT */ + DEBC_PERH_WWDT = (1U << 9) | (1U << 16), /**< WWDT */ + DEBC_PERH_RTC = (1U << 10) | (1U << 16), /**< RTC */ } dbgc_perh_t; /** * @} @@ -83,7 +81,7 @@ typedef enum */ __INLINE uint32_t ald_dbgc_get_rev_id(void) { - return (DBGC->IDCODE >> 16); + return (DBGC->IDCODE >> 16); } /** @@ -92,7 +90,7 @@ __INLINE uint32_t ald_dbgc_get_rev_id(void) */ __INLINE uint32_t ald_dbgc_get_core_id(void) { - return (DBGC->IDCODE >> 12) & 0xF; + return (DBGC->IDCODE >> 12) & 0xF; } /** @@ -101,7 +99,7 @@ __INLINE uint32_t ald_dbgc_get_core_id(void) */ __INLINE uint32_t ald_dbgc_get_device_id(void) { - return DBGC->IDCODE & 0xFFF; + return DBGC->IDCODE & 0xFFF; } /** @@ -112,10 +110,10 @@ __INLINE uint32_t ald_dbgc_get_device_id(void) */ __INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state) { - if (state) - SET_BIT(DBGC->CR, mode); - else - CLEAR_BIT(DBGC->CR, mode); + if (state) + SET_BIT(DBGC->CR, mode); + else + CLEAR_BIT(DBGC->CR, mode); } /** @@ -126,20 +124,18 @@ __INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state) */ __INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state) { - if ((perh >> 16) & 0x1) - { - if (state) - SET_BIT(DBGC->APB2FZ, perh); - else - CLEAR_BIT(DBGC->APB2FZ, perh); - } - else - { - if (state) - SET_BIT(DBGC->APB1FZ, perh); - else - CLEAR_BIT(DBGC->APB1FZ, perh); - } + if ((perh >> 16) & 0x1) { + if (state) + SET_BIT(DBGC->APB2FZ, perh); + else + CLEAR_BIT(DBGC->APB2FZ, perh); + } + else { + if (state) + SET_BIT(DBGC->APB1FZ, perh); + else + CLEAR_BIT(DBGC->APB1FZ, perh); + } } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dma.h index 364f9e16cb40498c8e85e6deeb80c3b4a1afd769..1fbebd56bf2bf2da37dc11be653d1287beb041da 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dma.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dma.h @@ -18,7 +18,7 @@ #define __ALD_DMA_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -36,8 +36,8 @@ extern "C" { * @defgroup DMA_Public_Macros DMA Public Macros * @{ */ -#define DMA_CH_COUNT 6 -#define DMA_ERR 31 +#define DMA_CH_COUNT 6U +#define DMA_ERR 31U /** * @} */ @@ -49,257 +49,260 @@ extern "C" { /** * @brief Input source to DMA channel - * @note ES32F065x: - * AD16C4T0--TIMER0 - * GP16C4T0--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - * - * ES32F033x: - * ES32F093x: - * GP16C4T0--TIMER0 - * GP16C4T1--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 + * @verbatim + In this module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F065x series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + TIMER4 ----> BS16T1 + TIMER5 ----> BS16T2 + TIMER6 ----> GP16C4T0 + TIMER7 ----> BS16T3 + + 2. For ES32F033x/ES32F093x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + TIMER4 ----> BS16T1 + TIMER5 ----> BS16T2 + TIMER6 ----> GP16C4T1 + TIMER7 ----> BS16T3 + @endverbatim */ -typedef enum -{ - DMA_MSEL_NONE = 0x0, /**< NONE */ - DMA_MSEL_GPIO = 0x1, /**< GPIO */ - DMA_MSEL_CRYPT = 0x2, /**< CRYPT */ - DMA_MSEL_ACMP = 0x3, /**< ACMP */ - DMA_MSEL_DAC0 = 0x4, /**< DAC0 */ - DMA_MSEL_ADC0 = 0x6, /**< ADC0 */ - DMA_MSEL_CRC = 0x7, /**< CRC */ - DMA_MSEL_UART0 = 0x8, /**< UART0 */ - DMA_MSEL_UART1 = 0x9, /**< UART1 */ - DMA_MSEL_UART2 = 0xA, /**< UART2 */ - DMA_MSEL_UART3 = 0xB, /**< UART3 */ - DMA_MSEL_USART0 = 0xC, /**< USART0 */ - DMA_MSEL_USART1 = 0xD, /**< USART1 */ - DMA_MSEL_SPI0 = 0xE, /**< SPI0 */ - DMA_MSEL_SPI1 = 0xF, /**< SPI1 */ - DMA_MSEL_I2C0 = 0x10, /**< I2C0 */ - DMA_MSEL_I2C1 = 0x11, /**< I2C1 */ - DMA_MSEL_TIMER0 = 0x12, /**< TIMER0 */ - DMA_MSEL_TIMER1 = 0x13, /**< TIMER1 */ - DMA_MSEL_TIMER2 = 0x14, /**< TIMER2 */ - DMA_MSEL_TIMER3 = 0x15, /**< TIMER3 */ - DMA_MSEL_RTC = 0x16, /**< RTC */ - DMA_MSEL_LPTIM0 = 0x17, /**< LPTIM0 */ - DMA_MSEL_LPUART0 = 0x18, /**< LPUART0 */ - DMA_MSEL_DMA = 0x19, /**< DMA */ - DMA_MSEL_SPI2 = 0x1A, /**< SPI2 */ - DMA_MSEL_TIMER4 = 0x1B, /**< TIMER4 */ - DMA_MSEL_TIMER5 = 0x1C, /**< TIMER5 */ - DMA_MSEL_TIMER6 = 0x1D, /**< TIMER6 */ - DMA_MSEL_TIMER7 = 0x1E, /**< TIMER7 */ - DMA_MSEL_ADC1 = 0x1F, /**< ADC1 */ - DMA_MSEL_PIS = 0x20, /**< PIS */ - DMA_MSEL_TRNG = 0x21, /**< TRNG */ +typedef enum { + DMA_MSEL_NONE = 0x0U, /**< NONE */ + DMA_MSEL_GPIO = 0x1U, /**< GPIO */ + DMA_MSEL_CRYPT = 0x2U, /**< CRYPT */ + DMA_MSEL_ACMP = 0x3U, /**< ACMP */ + DMA_MSEL_DAC0 = 0x4U, /**< DAC0 */ + DMA_MSEL_ADC0 = 0x6U, /**< ADC0 */ + DMA_MSEL_CRC = 0x7U, /**< CRC */ + DMA_MSEL_UART0 = 0x8U, /**< UART0 */ + DMA_MSEL_UART1 = 0x9U, /**< UART1 */ + DMA_MSEL_UART2 = 0xAU, /**< UART2 */ + DMA_MSEL_UART3 = 0xBU, /**< UART3 */ + DMA_MSEL_USART0 = 0xCU, /**< USART0 */ + DMA_MSEL_USART1 = 0xDU, /**< USART1 */ + DMA_MSEL_SPI0 = 0xEU, /**< SPI0 */ + DMA_MSEL_SPI1 = 0xFU, /**< SPI1 */ + DMA_MSEL_I2C0 = 0x10U, /**< I2C0 */ + DMA_MSEL_I2C1 = 0x11U, /**< I2C1 */ + DMA_MSEL_TIMER0 = 0x12U, /**< TIMER0 */ + DMA_MSEL_TIMER1 = 0x13U, /**< TIMER1 */ + DMA_MSEL_TIMER2 = 0x14U, /**< TIMER2 */ + DMA_MSEL_TIMER3 = 0x15U, /**< TIMER3 */ + DMA_MSEL_RTC = 0x16U, /**< RTC */ + DMA_MSEL_LPTIM0 = 0x17U, /**< LPTIM0 */ + DMA_MSEL_LPUART0 = 0x18U, /**< LPUART0 */ + DMA_MSEL_DMA = 0x19U, /**< DMA */ + DMA_MSEL_SPI2 = 0x1AU, /**< SPI2 */ + DMA_MSEL_TIMER4 = 0x1BU, /**< TIMER4 */ + DMA_MSEL_TIMER5 = 0x1CU, /**< TIMER5 */ + DMA_MSEL_TIMER6 = 0x1DU, /**< TIMER6 */ + DMA_MSEL_TIMER7 = 0x1EU, /**< TIMER7 */ + DMA_MSEL_ADC1 = 0x1FU, /**< ADC1 */ + DMA_MSEL_PIS = 0x20U, /**< PIS */ + DMA_MSEL_TRNG = 0x21U, /**< TRNG */ } dma_msel_t; /** * @brief Input signal to DMA channel */ -typedef enum -{ - DMA_MSIGSEL_NONE = 0x0, /**< NONE */ - DMA_MSIGSEL_EXTI_0 = 0x0, /**< External interrupt 0 */ - DMA_MSIGSEL_EXTI_1 = 0x1, /**< External interrupt 1 */ - DMA_MSIGSEL_EXTI_2 = 0x2, /**< External interrupt 2 */ - DMA_MSIGSEL_EXTI_3 = 0x3, /**< External interrupt 3 */ - DMA_MSIGSEL_EXTI_4 = 0x4, /**< External interrupt 4 */ - DMA_MSIGSEL_EXTI_5 = 0x5, /**< External interrupt 5 */ - DMA_MSIGSEL_EXTI_6 = 0x6, /**< External interrupt 6 */ - DMA_MSIGSEL_EXTI_7 = 0x7, /**< External interrupt 7 */ - DMA_MSIGSEL_EXTI_8 = 0x8, /**< External interrupt 8 */ - DMA_MSIGSEL_EXTI_9 = 0x9, /**< External interrupt 9 */ - DMA_MSIGSEL_EXTI_10 = 0xA, /**< External interrupt 10 */ - DMA_MSIGSEL_EXTI_11 = 0xB, /**< External interrupt 11 */ - DMA_MSIGSEL_EXTI_12 = 0xC, /**< External interrupt 12 */ - DMA_MSIGSEL_EXTI_13 = 0xD, /**< External interrupt 13 */ - DMA_MSIGSEL_EXTI_14 = 0xE, /**< External interrupt 14 */ - DMA_MSIGSEL_EXTI_15 = 0xF, /**< External interrupt 15 */ - DMA_MSIGSEL_CRYPT_WRITE = 0x0, /**< CRYPT write mode */ - DMA_MSIGSEL_CRYPT_READ = 0x1, /**< CRYPT read mode */ - DMA_MSIGSEL_CALC_WRITE = 0x0, /**< CALC write mode */ - DMA_MSIGSEL_CALC_READ = 0x1, /**< CALC read mode */ - DMA_MSIGSEL_DAC0_CH0 = 0x0, /**< DAC0 channel 0 complete */ - DMA_MSIGSEL_DAC0_CH1 = 0x1, /**< DAC0 channel 1 complete */ - DMA_MSIGSEL_ADC = 0x0, /**< ADC mode */ - DMA_MSIGSEL_UART_TXEMPTY = 0x0, /**< UART transmit */ - DMA_MSIGSEL_UART_RNR = 0x1, /**< UART receive */ - DMA_MSIGSEL_USART_RNR = 0x0, /**< USART reveive */ - DMA_MSIGSEL_USART_TXEMPTY = 0x1, /**< USART transmit */ - DMA_MSIGSEL_SPI_RNR = 0x0, /**< SPI receive */ - DMA_MSIGSEL_SPI_TXEMPTY = 0x1, /**< SPI transmit */ - DMA_MSIGSEL_I2C_RNR = 0x0, /**< I2C receive */ - DMA_MSIGSEL_I2C_TXEMPTY = 0x1, /**< I2C transmit */ - DMA_MSIGSEL_TIMER_CH1 = 0x0, /**< TIM channal 1 */ - DMA_MSIGSEL_TIMER_CH2 = 0x1, /**< TIM channal 2 */ - DMA_MSIGSEL_TIMER_CH3 = 0x2, /**< TIM channal 3 */ - DMA_MSIGSEL_TIMER_CH4 = 0x3, /**< TIM channal 4 */ - DMA_MSIGSEL_TIMER_TRI = 0x4, /**< TIM trigger */ - DMA_MSIGSEL_TIMER_COMP = 0x5, /**< TIM compare */ - DMA_MSIGSEL_TIMER_UPDATE = 0x6, /**< TIM update */ - DMA_MSIGSEL_LPUART_RNR = 0x0, /**< LPUART receive */ - DMA_MSIGSEL_LPUART_TXEMPTY = 0x1, /**< LPUART transmit */ - DMA_MSIGSEL_PIS_CH0 = 0x0, /**< PIS channal 0 */ - DMA_MSIGSEL_PIS_CH1 = 0x1, /**< PIS channal 1 */ - DMA_MSIGSEL_PIS_CH2 = 0x2, /**< PIS channal 2 */ - DMA_MSIGSEL_PIS_CH3 = 0x3, /**< PIS channal 3 */ - DMA_MSIGSEL_PIS_CH4 = 0x4, /**< PIS channal 4 */ - DMA_MSIGSEL_PIS_CH5 = 0x5, /**< PIS channal 5 */ - DMA_MSIGSEL_PIS_CH6 = 0x6, /**< PIS channal 6 */ - DMA_MSIGSEL_PIS_CH7 = 0x7, /**< PIS channal 7 */ - DMA_MSIGSEL_PIS_CH8 = 0x8, /**< PIS channal 8 */ - DMA_MSIGSEL_PIS_CH9 = 0x9, /**< PIS channal 9 */ - DMA_MSIGSEL_PIS_CH10 = 0xA, /**< PIS channal 10 */ - DMA_MSIGSEL_PIS_CH11 = 0xB, /**< PIS channal 11 */ - DMA_MSIGSEL_PIS_CH12 = 0xC, /**< PIS channal 12 */ - DMA_MSIGSEL_PIS_CH13 = 0xD, /**< PIS channal 13 */ - DMA_MSIGSEL_PIS_CH14 = 0xE, /**< PIS channal 14 */ - DMA_MSIGSEL_PIS_CH15 = 0xF, /**< PIS channal 15 */ +typedef enum { + DMA_MSIGSEL_NONE = 0x0U, /**< NONE */ + DMA_MSIGSEL_EXTI_0 = 0x0U, /**< External interrupt 0 */ + DMA_MSIGSEL_EXTI_1 = 0x1U, /**< External interrupt 1 */ + DMA_MSIGSEL_EXTI_2 = 0x2U, /**< External interrupt 2 */ + DMA_MSIGSEL_EXTI_3 = 0x3U, /**< External interrupt 3 */ + DMA_MSIGSEL_EXTI_4 = 0x4U, /**< External interrupt 4 */ + DMA_MSIGSEL_EXTI_5 = 0x5U, /**< External interrupt 5 */ + DMA_MSIGSEL_EXTI_6 = 0x6U, /**< External interrupt 6 */ + DMA_MSIGSEL_EXTI_7 = 0x7U, /**< External interrupt 7 */ + DMA_MSIGSEL_EXTI_8 = 0x8U, /**< External interrupt 8 */ + DMA_MSIGSEL_EXTI_9 = 0x9U, /**< External interrupt 9 */ + DMA_MSIGSEL_EXTI_10 = 0xAU, /**< External interrupt 10 */ + DMA_MSIGSEL_EXTI_11 = 0xBU, /**< External interrupt 11 */ + DMA_MSIGSEL_EXTI_12 = 0xCU, /**< External interrupt 12 */ + DMA_MSIGSEL_EXTI_13 = 0xDU, /**< External interrupt 13 */ + DMA_MSIGSEL_EXTI_14 = 0xEU, /**< External interrupt 14 */ + DMA_MSIGSEL_EXTI_15 = 0xFU, /**< External interrupt 15 */ + DMA_MSIGSEL_CRYPT_WRITE = 0x0U, /**< CRYPT write mode */ + DMA_MSIGSEL_CRYPT_READ = 0x1U, /**< CRYPT read mode */ + DMA_MSIGSEL_CALC_WRITE = 0x0U, /**< CALC write mode */ + DMA_MSIGSEL_CALC_READ = 0x1U, /**< CALC read mode */ + DMA_MSIGSEL_DAC0_CH0 = 0x0U, /**< DAC0 channel 0 complete */ + DMA_MSIGSEL_DAC0_CH1 = 0x1U, /**< DAC0 channel 1 complete */ + DMA_MSIGSEL_ADC = 0x0U, /**< ADC mode */ + DMA_MSIGSEL_UART_TXEMPTY = 0x0U, /**< UART transmit */ + DMA_MSIGSEL_UART_RNR = 0x1U, /**< UART receive */ + DMA_MSIGSEL_USART_RNR = 0x0U, /**< USART reveive */ + DMA_MSIGSEL_USART_TXEMPTY = 0x1U, /**< USART transmit */ + DMA_MSIGSEL_SPI_RNR = 0x0U, /**< SPI receive */ + DMA_MSIGSEL_SPI_TXEMPTY = 0x1U, /**< SPI transmit */ + DMA_MSIGSEL_I2C_RNR = 0x0U, /**< I2C receive */ + DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, /**< I2C transmit */ + DMA_MSIGSEL_TIMER_CH1 = 0x0U, /**< TIM channal 1 */ + DMA_MSIGSEL_TIMER_CH2 = 0x1U, /**< TIM channal 2 */ + DMA_MSIGSEL_TIMER_CH3 = 0x2U, /**< TIM channal 3 */ + DMA_MSIGSEL_TIMER_CH4 = 0x3U, /**< TIM channal 4 */ + DMA_MSIGSEL_TIMER_TRI = 0x4U, /**< TIM trigger */ + DMA_MSIGSEL_TIMER_COMP = 0x5U, /**< TIM compare */ + DMA_MSIGSEL_TIMER_UPDATE = 0x6U, /**< TIM update */ + DMA_MSIGSEL_LPUART_RNR = 0x0U, /**< LPUART receive */ + DMA_MSIGSEL_LPUART_TXEMPTY = 0x1U, /**< LPUART transmit */ + DMA_MSIGSEL_PIS_CH0 = 0x0U, /**< PIS channal 0 */ + DMA_MSIGSEL_PIS_CH1 = 0x1U, /**< PIS channal 1 */ + DMA_MSIGSEL_PIS_CH2 = 0x2U, /**< PIS channal 2 */ + DMA_MSIGSEL_PIS_CH3 = 0x3U, /**< PIS channal 3 */ + DMA_MSIGSEL_PIS_CH4 = 0x4U, /**< PIS channal 4 */ + DMA_MSIGSEL_PIS_CH5 = 0x5U, /**< PIS channal 5 */ + DMA_MSIGSEL_PIS_CH6 = 0x6U, /**< PIS channal 6 */ + DMA_MSIGSEL_PIS_CH7 = 0x7U, /**< PIS channal 7 */ + DMA_MSIGSEL_PIS_CH8 = 0x8U, /**< PIS channal 8 */ + DMA_MSIGSEL_PIS_CH9 = 0x9U, /**< PIS channal 9 */ + DMA_MSIGSEL_PIS_CH10 = 0xAU, /**< PIS channal 10 */ + DMA_MSIGSEL_PIS_CH11 = 0xBU, /**< PIS channal 11 */ + DMA_MSIGSEL_PIS_CH12 = 0xCU, /**< PIS channal 12 */ + DMA_MSIGSEL_PIS_CH13 = 0xDU, /**< PIS channal 13 */ + DMA_MSIGSEL_PIS_CH14 = 0xEU, /**< PIS channal 14 */ + DMA_MSIGSEL_PIS_CH15 = 0xFU, /**< PIS channal 15 */ } dma_msigsel_t; /** * @brief DMA Descriptor control type */ -typedef union -{ - struct - { - uint32_t cycle_ctrl : 3; /**< DMA operating mode @ref dma_cycle_ctrl_t */ - uint32_t next_useburst : 1; /**< Uses the alternate data structure when complete a DMA cycle */ - uint32_t n_minus_1 : 10; /**< Represent the total number of DMA transfers that DMA cycle contains. */ - uint32_t R_power : 4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ - uint32_t src_prot_ctrl : 3; /**< Control the state of HPROT when reads the source data. */ - uint32_t dst_prot_ctrl : 3; /**< Control the state of HPROT when writes the destination data */ - uint32_t src_size : 2; /**< Source data size @ref dma_data_size_t */ - uint32_t src_inc : 2; /**< Control the source address increment. @ref dma_data_inc_t */ - uint32_t dst_size : 2; /**< Destination data size. @ref dma_data_size_t */ - uint32_t dst_inc : 2; /**< Destination address increment. @ref dma_data_inc_t */ - }; - uint32_t word; +typedef union { + struct { + uint32_t cycle_ctrl :3; /**< DMA operating mode @ref dma_cycle_ctrl_t */ + uint32_t next_useburst :1; /**< Uses the alternate data structure when complete a DMA cycle */ + uint32_t n_minus_1 :10; /**< Represent the total number of DMA transfers that DMA cycle contains. */ + uint32_t R_power :4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ + uint32_t src_prot_ctrl :3; /**< Control the state of HPROT when reads the source data. */ + uint32_t dst_prot_ctrl :3; /**< Control the state of HPROT when writes the destination data */ + uint32_t src_size :2; /**< Source data size @ref dma_data_size_t */ + uint32_t src_inc :2; /**< Control the source address increment. @ref dma_data_inc_t */ + uint32_t dst_size :2; /**< Destination data size. @ref dma_data_size_t */ + uint32_t dst_inc :2; /**< Destination address increment. @ref dma_data_inc_t */ + }; + uint32_t word; } dma_ctrl_t; /** * @brief Channel control data structure */ -typedef struct -{ - void *src; /**< Source data end pointer */ - void *dst; /**< Destination data end pointer */ - dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */ - uint32_t use; /**< Reserve for user */ +typedef struct { + void *src; /**< Source data end pointer */ + void *dst; /**< Destination data end pointer */ + dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */ + uint32_t use; /**< Reserve for user */ } dma_descriptor_t; /** * @brief data increment */ -typedef enum -{ - DMA_DATA_INC_BYTE = 0x0, /**< Address increment by byte */ - DMA_DATA_INC_HALFWORD = 0x1, /**< Address increment by halfword */ - DMA_DATA_INC_WORD = 0x2, /**< Address increment by word */ - DMA_DATA_INC_NONE = 0x3, /**< No increment */ +typedef enum { + DMA_DATA_INC_BYTE = 0x0U, /**< Address increment by byte */ + DMA_DATA_INC_HALFWORD = 0x1U, /**< Address increment by halfword */ + DMA_DATA_INC_WORD = 0x2U, /**< Address increment by word */ + DMA_DATA_INC_NONE = 0x3U, /**< No increment */ } dma_data_inc_t; /** * @brief Data size */ -typedef enum -{ - DMA_DATA_SIZE_BYTE = 0x0, /**< Byte */ - DMA_DATA_SIZE_HALFWORD = 0x1, /**< Halfword */ - DMA_DATA_SIZE_WORD = 0x2, /**< Word */ +typedef enum { + DMA_DATA_SIZE_BYTE = 0x0U, /**< Byte */ + DMA_DATA_SIZE_HALFWORD = 0x1U, /**< Halfword */ + DMA_DATA_SIZE_WORD = 0x2U, /**< Word */ } dma_data_size_t; /** * @brief The operating mode of the DMA cycle */ -typedef enum -{ - DMA_CYCLE_CTRL_NONE = 0x0, /**< Stop */ - DMA_CYCLE_CTRL_BASIC = 0x1, /**< Basic */ - DMA_CYCLE_CTRL_AUTO = 0x2, /**< Auto-request */ - DMA_CYCLE_CTRL_PINGPONG = 0x3, /**< Ping-pong */ - DMA_CYCLE_CTRL_MEM_SCATTER_GATHER = 0x4, /**< Memory scatter/gather */ - DMA_CYCLE_CTRL_PER_SCATTER_GATHER = 0x6, /**< Peripheral scatter/gather */ +typedef enum { + DMA_CYCLE_CTRL_NONE = 0x0U, /**< Stop */ + DMA_CYCLE_CTRL_BASIC = 0x1U, /**< Basic */ + DMA_CYCLE_CTRL_AUTO = 0x2U, /**< Auto-request */ + DMA_CYCLE_CTRL_PINGPONG = 0x3U, /**< Ping-pong */ + DMA_CYCLE_CTRL_MEM_SG_PRIMARY = 0x4U, /**< Memory scatter-gather using the primary structure */ + DMA_CYCLE_CTRL_MEM_SG_ALTERNATE = 0x5U, /**< Memory scatter-gather using the alternate structure */ + DMA_CYCLE_CTRL_PER_SG_PRIMARY = 0x6U, /**< Peripheral scatter-gather using the primary structure */ + DMA_CYCLE_CTRL_PER_SG_ALTERNATE = 0x7U, /**< Peripheral scatter-gather using the alternate structure */ } dma_cycle_ctrl_t; /** * @brief Control how many DMA transfers can occur * before the controller re-arbitrates */ -typedef enum -{ - DMA_R_POWER_1 = 0x0, /**< Arbitrates after each DMA transfer */ - DMA_R_POWER_2 = 0x1, /**< Arbitrates after 2 DMA transfer */ - DMA_R_POWER_4 = 0x2, /**< Arbitrates after 4 DMA transfer */ - DMA_R_POWER_8 = 0x3, /**< Arbitrates after 8 DMA transfer */ - DMA_R_POWER_16 = 0x4, /**< Arbitrates after 16 DMA transfer */ - DMA_R_POWER_32 = 0x5, /**< Arbitrates after 32 DMA transfer */ - DMA_R_POWER_64 = 0x6, /**< Arbitrates after 64 DMA transfer */ - DMA_R_POWER_128 = 0x7, /**< Arbitrates after 128 DMA transfer */ - DMA_R_POWER_256 = 0x8, /**< Arbitrates after 256 DMA transfer */ - DMA_R_POWER_512 = 0x9, /**< Arbitrates after 512 DMA transfer */ - DMA_R_POWER_1024 = 0xA, /**< Arbitrates after 1024 DMA transfer */ +typedef enum { + DMA_R_POWER_1 = 0x0U, /**< Arbitrates after each DMA transfer */ + DMA_R_POWER_2 = 0x1U, /**< Arbitrates after 2 DMA transfer */ + DMA_R_POWER_4 = 0x2U, /**< Arbitrates after 4 DMA transfer */ + DMA_R_POWER_8 = 0x3U, /**< Arbitrates after 8 DMA transfer */ + DMA_R_POWER_16 = 0x4U, /**< Arbitrates after 16 DMA transfer */ + DMA_R_POWER_32 = 0x5U, /**< Arbitrates after 32 DMA transfer */ + DMA_R_POWER_64 = 0x6U, /**< Arbitrates after 64 DMA transfer */ + DMA_R_POWER_128 = 0x7U, /**< Arbitrates after 128 DMA transfer */ + DMA_R_POWER_256 = 0x8U, /**< Arbitrates after 256 DMA transfer */ + DMA_R_POWER_512 = 0x9U, /**< Arbitrates after 512 DMA transfer */ + DMA_R_POWER_1024 = 0xAU, /**< Arbitrates after 1024 DMA transfer */ } dma_arbiter_config_t; /** * @brief Callback function pointer and param */ -typedef struct -{ - void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ - void (*err_cbk)(void *arg); /**< DMA occurs error callback */ - void *cplt_arg; /**< The parameter of cplt_cbk() */ - void *err_arg; /**< The parameter of err_cbk() */ +typedef struct { + void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*err_cbk)(void* arg); /**< DMA occurs error callback */ + void *cplt_arg; /**< The parameter of cplt_cbk() */ + void *err_arg; /**< The parameter of err_cbk() */ } dma_call_back_t; /** * @brief DMA channal configure structure */ -typedef struct -{ - void *src; /**< Source data begin pointer */ - void *dst; /**< Destination data begin pointer */ - uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ - dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */ - dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */ - dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */ - dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ - type_func_t primary; /**< Use primary descriptor or alternate descriptor */ - type_func_t burst; /**< Uses the alternate data structure when complete a DMA cycle */ - type_func_t high_prio; /**< High priority or default priority */ - type_func_t iterrupt; /**< Enable/disable interrupt */ - dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */ - dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */ - uint8_t channel; /**< Channel index */ +typedef struct { + void *src; /**< Source data begin pointer */ + void *dst; /**< Destination data begin pointer */ + uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ + dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */ + dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */ + dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */ + dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ + type_func_t primary; /**< Use primary descriptor or alternate descriptor */ + type_func_t burst; /**< Enable/Disable the useburst setting for this channel */ + type_func_t high_prio; /**< High priority or default priority */ + type_func_t interrupt; /**< Enable/disable interrupt */ + dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */ + dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */ + uint8_t channel; /**< Channel index */ } dma_config_t; /** * @brief DMA handle structure definition */ -typedef struct -{ - DMA_TypeDef *perh; /**< DMA registers base address */ - dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ - void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ - void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */ - void *cplt_arg; /**< The parameter of cplt_cbk() */ - void *err_arg; /**< The parameter of err_cbk() */ +typedef struct { + DMA_TypeDef *perh; /**< DMA registers base address */ + dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ + void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */ + void *cplt_arg; /**< The parameter of cplt_cbk() */ + void *err_arg; /**< The parameter of err_cbk() */ } dma_handle_t; + +/** + * @brief Descriptor complete state + */ +typedef enum { + DMA_DESCP_CPLT_PRI = 0x0U, /**< Primary descriptor has been completed */ + DMA_DESCP_CPLT_ALT = 0x1U, /**< Alternate descriptor has been completed */ + DMA_DESCP_CPLT_ALL = 0x2U, /**< Both primary and alternate descriptors have been completed */ +} dma_descrp_cplt_t; /** * @} */ @@ -317,12 +320,14 @@ typedef struct #define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \ ((x) == DMA_DATA_SIZE_HALFWORD) || \ ((x) == DMA_DATA_SIZE_WORD)) -#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ - ((x) == DMA_CYCLE_CTRL_BASIC) || \ - ((x) == DMA_CYCLE_CTRL_AUTO) || \ - ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ - ((x) == DMA_CYCLE_CTRL_MEM_SCATTER_GATHER) || \ - ((x) == DMA_CYCLE_CTRL_PER_SCATTER_GATHER)) +#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ + ((x) == DMA_CYCLE_CTRL_BASIC) || \ + ((x) == DMA_CYCLE_CTRL_AUTO) || \ + ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ + ((x) == DMA_CYCLE_CTRL_MEM_SG_PRIMARY) || \ + ((x) == DMA_CYCLE_CTRL_MEM_SG_ALTERNATE) || \ + ((x) == DMA_CYCLE_CTRL_PER_SG_PRIMARY) || \ + ((x) == DMA_CYCLE_CTRL_PER_SG_ALTERNATE)) #define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \ ((x) == DMA_R_POWER_2) || \ ((x) == DMA_R_POWER_4) || \ @@ -354,6 +359,7 @@ typedef struct extern void ald_dma_reset(DMA_TypeDef *DMAx); extern void ald_dma_init(DMA_TypeDef *DMAx); extern void ald_dma_config_struct(dma_config_t *p); +extern void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory); /** * @} */ @@ -366,11 +372,17 @@ extern void ald_dma_config_struct(dma_config_t *p); extern void ald_dma_config_auto(dma_handle_t *hperh); extern void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size); extern void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, - uint16_t size, uint8_t channel, void (*cbk)(void *arg)); + uint16_t size, uint8_t channel, void (*cbk)(void *arg)); extern void ald_dma_config_basic(dma_handle_t *hperh); extern void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size); extern void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, - dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); + dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); +extern void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config, + uint8_t first, void (*cbk)(void *arg)); +extern void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, + uint32_t nr, uint8_t channel, void (*cbk)(void *arg)); +extern void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, + dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); /** * @} */ @@ -384,7 +396,8 @@ extern void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_fu extern it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel); extern flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel); extern void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel); -void ald_dma_irq_handler(void); +extern dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel); +extern void ald_dma_irq_handler(void); /** * @} */ @@ -393,7 +406,6 @@ void ald_dma_irq_handler(void); * @} */ - /** * @} */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_flash.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_flash.h index 9a4a66b0686fcf6dd519a503252441dc25053be6..8858b8b707fd605d702d32ea63491f19cb0a34a5 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_flash.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_flash.h @@ -36,21 +36,21 @@ extern "C" { * @{ */ #define FLASH_REG_UNLOCK() \ - do { \ - if (op_cmd == OP_FLASH) { \ - WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \ - WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \ - } \ - else { \ - WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \ - WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \ - } \ - } while (0) +do { \ + if (op_cmd == OP_FLASH) { \ + WRITE_REG(MSC->FLASHKEY, 0x8ACE0246U); \ + WRITE_REG(MSC->FLASHKEY, 0x9BDF1357U); \ + } \ + else { \ + WRITE_REG(MSC->INFOKEY, 0x7153BFD9U); \ + WRITE_REG(MSC->INFOKEY, 0x0642CEA8U); \ + } \ +} while (0) #define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) #define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) #define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) #define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) -#define FLASH_BASE_ADDR 0x00000000 +#define FLASH_BASE_ADDR 0x00000000U #define FLASH_PAGE_SIZE 1024UL #define FLASH_WORD_SIZE 8UL #define FLASH_TOTAL_SIZE 256UL @@ -67,9 +67,9 @@ extern "C" { #define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK)) #ifdef USE_FLASH_FIFO -#define FLASH_FIFO 1 + #define FLASH_FIFO 1 #else -#define FLASH_FIFO 0 + #define FLASH_FIFO 0 #endif /** * @} @@ -78,24 +78,22 @@ extern "C" { /** @defgroup FLASH_Private_Types FLASH Private Types * @{ */ -typedef enum -{ - FLASH_CMD_AE = 0x000051AE, /**< Program area erase all */ - FLASH_CMD_PE = 0x00005EA1, /**< Page erase */ - FLASH_CMD_WP = 0x00005DA2, /**< Word program */ - FLASH_CMD_DATAPE = 0x00005BA4, /**< Data flash page page erase */ - FLASH_CMD_DATAWP = 0x00005AA5, /**< Data flash word program */ +typedef enum { + FLASH_CMD_AE = 0x000051AEU, /**< Program area erase all */ + FLASH_CMD_PE = 0x00005EA1U, /**< Page erase */ + FLASH_CMD_WP = 0x00005DA2U, /**< Word program */ + FLASH_CMD_DATAPE = 0x00005BA4U, /**< Data flash page page erase */ + FLASH_CMD_DATAWP = 0x00005AA5U, /**< Data flash word program */ } flash_cmd_type; -typedef enum -{ - OP_FLASH = 0, /**< Operate Pragram area */ - OP_INFO = 1, /**< Operate info area */ +typedef enum { + OP_FLASH = 0U, /**< Operate Pragram area */ + OP_INFO = 1U, /**< Operate info area */ } op_cmd_type; /** * @} - */ + */ /** @addtogroup Flash_Private_Functions * @{ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_gpio.h index a8a2e9ebe0571b01ebf85abc75c43957e3f85381..336c90f97701ef6fad4ec8d3fdd4a969673d7027 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_gpio.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_gpio.h @@ -18,7 +18,7 @@ #define __ALD_GPIO_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -52,7 +52,7 @@ extern "C" { #define GPIO_PIN_13 (1U << 13) #define GPIO_PIN_14 (1U << 14) #define GPIO_PIN_15 (1U << 15) -#define GPIO_PIN_ALL (0xFFFF) +#define GPIO_PIN_ALL (0xFFFFU) /** * @} */ @@ -65,125 +65,114 @@ extern "C" { /** * @brief GPIO mode */ -typedef enum -{ - GPIO_MODE_CLOSE = 0x0, /**< Digital close Analog open */ - GPIO_MODE_INPUT = 0x1, /**< Input */ - GPIO_MODE_OUTPUT = 0x2, /**< Output */ +typedef enum { + GPIO_MODE_CLOSE = 0x0U, /**< Digital close Analog open */ + GPIO_MODE_INPUT = 0x1U, /**< Input */ + GPIO_MODE_OUTPUT = 0x2U, /**< Output */ } gpio_mode_t; /** * @brief GPIO open-drain or push-pull */ -typedef enum -{ - GPIO_PUSH_PULL = 0x0, /**< Push-Pull */ - GPIO_OPEN_DRAIN = 0x2, /**< Open-Drain */ - GPIO_OPEN_SOURCE = 0x3, /**< Open-Source */ +typedef enum { + GPIO_PUSH_PULL = 0x0U, /**< Push-Pull */ + GPIO_OPEN_DRAIN = 0x2U, /**< Open-Drain. Can't output high level */ + GPIO_OPEN_SOURCE = 0x3U, /**< Open-Source. Can't output low level */ } gpio_odos_t; /** * @brief GPIO push-up or push-down */ -typedef enum -{ - GPIO_FLOATING = 0x0,/**< Floating */ - GPIO_PUSH_UP = 0x1,/**< Push-Up */ - GPIO_PUSH_DOWN = 0x2,/**< Push-Down */ - GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */ +typedef enum { + GPIO_FLOATING = 0x0U, /**< Floating */ + GPIO_PUSH_UP = 0x1U, /**< Push-Up */ + GPIO_PUSH_DOWN = 0x2U, /**< Push-Down */ + GPIO_PUSH_UP_DOWN = 0x3U, /**< Push-Up and Push-Down */ } gpio_push_t; /** * @brief GPIO output drive */ -typedef enum -{ - GPIO_OUT_DRIVE_NORMAL = 0x0, /**< Normal current flow */ - GPIO_OUT_DRIVE_STRONG = 0x1, /**< Strong current flow */ +typedef enum { + GPIO_OUT_DRIVE_NORMAL = 0x0U, /**< Normal current flow */ + GPIO_OUT_DRIVE_STRONG = 0x1U, /**< Strong current flow */ } gpio_out_drive_t; /** * @brief GPIO filter */ -typedef enum -{ - GPIO_FILTER_DISABLE = 0x0, /**< Disable filter */ - GPIO_FILTER_ENABLE = 0x1, /**< Enable filter */ +typedef enum { + GPIO_FILTER_DISABLE = 0x0U, /**< Disable filter */ + GPIO_FILTER_ENABLE = 0x1U, /**< Enable filter */ } gpio_filter_t; /** * @brief GPIO type */ -typedef enum -{ - GPIO_TYPE_CMOS = 0x0, /**< CMOS Type */ - GPIO_TYPE_TTL = 0x1, /**< TTL Type */ +typedef enum { + GPIO_TYPE_CMOS = 0x0U, /**< CMOS Type */ + GPIO_TYPE_TTL = 0x1U, /**< TTL Type */ } gpio_type_t; /** * @brief GPIO functions */ -typedef enum -{ - GPIO_FUNC_0 = 0, /**< function #0 */ - GPIO_FUNC_1 = 1, /**< function #1 */ - GPIO_FUNC_2 = 2, /**< function #2 */ - GPIO_FUNC_3 = 3, /**< function #3 */ - GPIO_FUNC_4 = 4, /**< function #4 */ - GPIO_FUNC_5 = 5, /**< function #5 */ - GPIO_FUNC_6 = 6, /**< function #6 */ - GPIO_FUNC_7 = 7, /**< function #7 */ +typedef enum { + GPIO_FUNC_0 = 0U, /**< function #0 */ + GPIO_FUNC_1 = 1U, /**< function #1 */ + GPIO_FUNC_2 = 2U, /**< function #2 */ + GPIO_FUNC_3 = 3U, /**< function #3 */ + GPIO_FUNC_4 = 4U, /**< function #4 */ + GPIO_FUNC_5 = 5U, /**< function #5 */ + GPIO_FUNC_6 = 6U, /**< function #6 */ + GPIO_FUNC_7 = 7U, /**< function #7 */ } gpio_func_t; /** * @brief GPIO Init Structure definition */ -typedef struct -{ - gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. +typedef struct { + gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. This parameter can be any value of @ref gpio_mode_t */ - gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins. + gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins. This parameter can be a value of @ref gpio_odos_t */ - gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. + gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. This parameter can be a value of @ref gpio_push_t */ - gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins. + gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins. This parameter can be a value of @ref gpio_out_drive_t */ - gpio_filter_t flt; /**< Specifies the input filter for the selected pins. + gpio_filter_t flt; /**< Specifies the input filter for the selected pins. This parameter can be a value of @ref gpio_filter_t */ - gpio_type_t type; /**< Specifies the type for the selected pins. + gpio_type_t type; /**< Specifies the type for the selected pins. This parameter can be a value of @ref gpio_type_t */ - gpio_func_t func; /**< Specifies the function for the selected pins. + gpio_func_t func; /**< Specifies the function for the selected pins. This parameter can be a value of @ref gpio_func_t */ } gpio_init_t; /** * @brief EXTI trigger style */ -typedef enum -{ - EXTI_TRIGGER_RISING_EDGE = 0, /**< Rising edge trigger */ - EXTI_TRIGGER_TRAILING_EDGE = 1, /**< Trailing edge trigger */ - EXTI_TRIGGER_BOTH_EDGE = 2, /**< Rising and trailing edge trigger */ +typedef enum { + EXTI_TRIGGER_RISING_EDGE = 0U, /**< Rising edge trigger */ + EXTI_TRIGGER_TRAILING_EDGE = 1U, /**< Trailing edge trigger */ + EXTI_TRIGGER_BOTH_EDGE = 2U, /**< Rising and trailing edge trigger */ } exti_trigger_style_t; /** * @brief EXTI filter clock select */ -typedef enum -{ - EXTI_FILTER_CLOCK_10K = 0, /**< cks = 10KHz */ - EXTI_FILTER_CLOCK_32K = 1, /**< cks = 32KHz */ +typedef enum { + EXTI_FILTER_CLOCK_10K = 0U, /**< cks = 10KHz */ + EXTI_FILTER_CLOCK_32K = 1U, /**< cks = 32KHz */ } exti_filter_clock_t; /** * @brief EXTI Init Structure definition */ -typedef struct -{ - type_func_t filter; /**< Enable filter. */ - exti_filter_clock_t cks; /**< Filter clock select. */ - uint8_t filter_time; /**< Filter duration */ +typedef struct { + type_func_t filter; /**< Enable filter. */ + exti_filter_clock_t cks; /**< Filter clock select. */ + uint8_t filter_time; /**< Filter duration */ } exti_init_t; /** * @} @@ -193,37 +182,37 @@ typedef struct * @defgroup GPIO_Private_Macros GPIO Private Macros * @{ */ -#define PIN_MASK 0xFFFF -#define UNLOCK_KEY 0x55AA +#define PIN_MASK 0xFFFFU +#define UNLOCK_KEY 0x55AAU #define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0)) #define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \ - (GPIOx == GPIOB) || \ - (GPIOx == GPIOC) || \ - (GPIOx == GPIOD) || \ - (GPIOx == GPIOE) || \ - (GPIOx == GPIOF) || \ - (GPIOx == GPIOG) || \ - (GPIOx == GPIOH)) + (GPIOx == GPIOB) || \ + (GPIOx == GPIOC) || \ + (GPIOx == GPIOD) || \ + (GPIOx == GPIOE) || \ + (GPIOx == GPIOF) || \ + (GPIOx == GPIOG) || \ + (GPIOx == GPIOH)) #define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \ - ((x) == GPIO_MODE_INPUT) || \ - ((x) == GPIO_MODE_OUTPUT)) + ((x) == GPIO_MODE_INPUT) || \ + ((x) == GPIO_MODE_OUTPUT)) #define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \ - ((x) == GPIO_OPEN_DRAIN) || \ - ((x) == GPIO_OPEN_SOURCE)) + ((x) == GPIO_OPEN_DRAIN) || \ + ((x) == GPIO_OPEN_SOURCE)) #define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \ - ((x) == GPIO_PUSH_UP) || \ - ((x) == GPIO_PUSH_DOWN) || \ - ((x) == GPIO_PUSH_UP_DOWN)) + ((x) == GPIO_PUSH_UP) || \ + ((x) == GPIO_PUSH_DOWN) || \ + ((x) == GPIO_PUSH_UP_DOWN)) #define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_NORMAL) || \ - ((x) == GPIO_OUT_DRIVE_STRONG)) + ((x) == GPIO_OUT_DRIVE_STRONG)) #define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \ - ((x) == GPIO_FILTER_ENABLE)) + ((x) == GPIO_FILTER_ENABLE)) #define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \ - ((x) == GPIO_TYPE_CMOS)) + ((x) == GPIO_TYPE_CMOS)) #define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \ - ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \ - ((x) == EXTI_TRIGGER_BOTH_EDGE)) + ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \ + ((x) == EXTI_TRIGGER_BOTH_EDGE)) #define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \ ((x) == EXTI_FILTER_CLOCK_32K)) #define IS_GPIO_FUNC(x) ((x) <= 7) diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_i2c.h index a05aaf0ebb357a68831fa28efc094a41bef9601c..f421ff168e0deec6606d21b62f773adf1ccbb6e4 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_i2c.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_i2c.h @@ -39,111 +39,102 @@ extern "C" { /** * @brief I2C Error Code */ -typedef enum -{ - I2C_ERROR_NONE = 0x0, /**< No error */ - I2C_ERROR_BERR = 0x1, /**< Berr error */ - I2C_ERROR_ARLO = 0x2, /**< Arlo error */ - I2C_ERROR_AF = 0x4, /**< Af error */ - I2C_ERROR_OVR = 0x8, /**< Ovr error */ - I2C_ERROR_DMA = 0x10, /**< Dma error */ - I2C_ERROR_TIMEOUT = 0x20, /**< Timeout error */ +typedef enum { + I2C_ERROR_NONE = 0x0U, /**< No error */ + I2C_ERROR_BERR = 0x1U, /**< Berr error */ + I2C_ERROR_ARLO = 0x2U, /**< Arlo error */ + I2C_ERROR_AF = 0x4U, /**< Af error */ + I2C_ERROR_OVR = 0x8U, /**< Ovr error */ + I2C_ERROR_DMA = 0x10U, /**< Dma error */ + I2C_ERROR_TIMEOUT = 0x20U, /**< Timeout error */ } i2c_error_t; /** * @brief I2C state structure definition */ -typedef enum -{ - I2C_STATE_RESET = 0x0, /**< Peripheral is not yet Initialized */ - I2C_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - I2C_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - I2C_STATE_BUSY_TX = 0x3, /**< Data Transmission process is ongoing */ - I2C_STATE_BUSY_RX = 0x4, /**< Data Reception process is ongoing */ - I2C_STATE_TIMEOUT = 0x5, /**< timeout state */ - I2C_STATE_ERROR = 0x6, /**< Error */ +typedef enum { + I2C_STATE_RESET = 0x0U, /**< Peripheral is not yet Initialized */ + I2C_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + I2C_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + I2C_STATE_BUSY_TX = 0x3U, /**< Data Transmission process is ongoing */ + I2C_STATE_BUSY_RX = 0x4U, /**< Data Reception process is ongoing */ + I2C_STATE_TIMEOUT = 0x5U, /**< timeout state */ + I2C_STATE_ERROR = 0x6U, /**< Error */ } i2c_state_t; /** * @brief I2C Duty Cycle */ -typedef enum -{ - I2C_DUTYCYCLE_2 = 0x0, /**< duty cycle is 2 */ - I2C_DUTYCYCLE_16_9 = 0x4000, /**< duty cycle is 16/9 */ +typedef enum { + I2C_DUTYCYCLE_2 = 0x0U, /**< duty cycle is 2 */ + I2C_DUTYCYCLE_16_9 = 0x4000U, /**< duty cycle is 16/9 */ } i2c_duty_t; /** * @brief I2C Addressing Mode */ -typedef enum -{ - I2C_ADDR_7BIT = 0x1, /**< 7 bit address */ - I2C_ADDR_10BIT = 0x2, /**< 10 bit address */ +typedef enum { + I2C_ADDR_7BIT = 0x1U, /**< 7 bit address */ + I2C_ADDR_10BIT = 0x2U, /**< 10 bit address */ } i2c_addr_t; /** * @brief I2C Dual Addressing Mode */ -typedef enum -{ - I2C_DUALADDR_DISABLE = 0x0, /**< dual address is disable */ - I2C_DUALADDR_ENABLE = 0x1, /**< dual address is enable */ +typedef enum { + I2C_DUALADDR_DISABLE = 0x0U, /**< dual address is disable */ + I2C_DUALADDR_ENABLE = 0x1U, /**< dual address is enable */ } i2c_dual_addr_t; /** * @brief I2C General Call Addressing mode */ -typedef enum -{ - I2C_GENERALCALL_DISABLE = 0x0, /**< feneral call address is disable */ - I2C_GENERALCALL_ENABLE = 0x40, /**< feneral call address is enable */ +typedef enum { + I2C_GENERALCALL_DISABLE = 0x0U, /**< feneral call address is disable */ + I2C_GENERALCALL_ENABLE = 0x40U, /**< feneral call address is enable */ } i2c_general_addr_t; /** * @brief I2C Nostretch Mode */ -typedef enum -{ - I2C_NOSTRETCH_DISABLE = 0x0, /**< Nostretch disable */ - I2C_NOSTRETCH_ENABLE = 0x80, /**< Nostretch enable */ +typedef enum { + I2C_NOSTRETCH_DISABLE = 0x0U, /**< Nostretch disable */ + I2C_NOSTRETCH_ENABLE = 0x80U, /**< Nostretch enable */ } i2c_nostretch_t; /** * @brief I2C Memory Address Size */ -typedef enum -{ - I2C_MEMADD_SIZE_8BIT = 0x1, /**< 8 bit memory address size */ - I2C_MEMADD_SIZE_16BIT = 0x10 /**< 10 bit memory address size */ +typedef enum { + I2C_MEMADD_SIZE_8BIT = 0x1U, /**< 8 bit memory address size */ + I2C_MEMADD_SIZE_16BIT = 0x10U, /**< 10 bit memory address size */ } i2c_addr_size_t; /** * @brief I2C Flag Definition */ -typedef enum -{ - I2C_FLAG_SB = (1U << 0), - I2C_FLAG_ADDR = (1U << 1), - I2C_FLAG_BTF = (1U << 2), - I2C_FLAG_ADD10 = (1U << 3), - I2C_FLAG_STOPF = (1U << 4), - I2C_FLAG_RXNE = (1U << 6), - I2C_FLAG_TXE = (1U << 7), - I2C_FLAG_BERR = (1U << 8), - I2C_FLAG_ARLO = (1U << 9), - I2C_FLAG_AF = (1U << 10), - I2C_FLAG_OVR = (1U << 11), - I2C_FLAG_PECERR = (1U << 12), - I2C_FLAG_TIMEOUT = (1U << 14), - I2C_FLAG_SMBALERT = (1U << 15), - I2C_FLAG_MSL = (1U << 16), - I2C_FLAG_BUSY = (1U << 17), - I2C_FLAG_TRA = (1U << 18), - I2C_FLAG_GENCALL = (1U << 20), - I2C_FLAG_SMBDEFAULT = (1U << 21), - I2C_FLAG_SMBHOST = (1U << 22), - I2C_FLAG_DUALF = (1U << 23), +typedef enum { + I2C_FLAG_SB = (1U << 0), + I2C_FLAG_ADDR = (1U << 1), + I2C_FLAG_BTF = (1U << 2), + I2C_FLAG_ADD10 = (1U << 3), + I2C_FLAG_STOPF = (1U << 4), + I2C_FLAG_RXNE = (1U << 6), + I2C_FLAG_TXE = (1U << 7), + I2C_FLAG_BERR = (1U << 8), + I2C_FLAG_ARLO = (1U << 9), + I2C_FLAG_AF = (1U << 10), + I2C_FLAG_OVR = (1U << 11), + I2C_FLAG_PECERR = (1U << 12), + I2C_FLAG_TIMEOUT = (1U << 14), + I2C_FLAG_SMBALERT = (1U << 15), + I2C_FLAG_MSL = (1U << 16), + I2C_FLAG_BUSY = (1U << 17), + I2C_FLAG_TRA = (1U << 18), + I2C_FLAG_GENCALL = (1U << 20), + I2C_FLAG_SMBDEFAULT = (1U << 21), + I2C_FLAG_SMBHOST = (1U << 22), + I2C_FLAG_DUALF = (1U << 23), } i2c_flag_t; /** @@ -151,193 +142,181 @@ typedef enum */ typedef enum { - I2C_MODE_NONE = 0x0, /**< No I2C communication on going */ - I2C_MODE_MASTER = 0x10, /**< I2C communication is in Master mode */ - I2C_MODE_SLAVE = 0x20, /**< I2C communication is in Slave mode */ - I2C_MODE_MEM = 0x40, /**< I2C communication is in Memory mode */ + I2C_MODE_NONE = 0x0U, /**< No I2C communication on going */ + I2C_MODE_MASTER = 0x10U, /**< I2C communication is in Master mode */ + I2C_MODE_SLAVE = 0x20U, /**< I2C communication is in Slave mode */ + I2C_MODE_MEM = 0x40U, /**< I2C communication is in Memory mode */ } i2c_mode_t; /** * @brief I2C Clock */ -typedef enum -{ - I2C_STANDARD_MODE_MAX_CLK = 100000, /**< Standard mode clock */ - I2C_FAST_MODE_MAX_CLK = 400000, /**< Fast mode clock */ +typedef enum { + I2C_STANDARD_MODE_MAX_CLK = 100000U, /**< Standard mode clock */ + I2C_FAST_MODE_MAX_CLK = 400000U, /**< Fast mode clock */ } i2c_clock_t; /** * @brief Interrupt Configuration Definition */ -typedef enum -{ - I2C_IT_BUF = (1U << 10), /**< Buffer interrupt */ - I2C_IT_EVT = (1U << 9), /**< Event interrupt */ - I2C_IT_ERR = (1U << 8), /**< Error interrupt */ +typedef enum { + I2C_IT_BUF = (1U << 10), /**< Buffer interrupt */ + I2C_IT_EVT = (1U << 9), /**< Event interrupt */ + I2C_IT_ERR = (1U << 8), /**< Error interrupt */ } i2c_interrupt_t; /** * @brief I2C CON1 Register */ -typedef enum -{ - I2C_CON1_PEN = (1U << 0), /**< PEN BIT */ - I2C_CON1_PMOD = (1U << 1), /**< PMOD BIT */ - I2C_CON1_SMBMOD = (1U << 3), /**< SMBMOD BIT */ - I2C_CON1_ARPEN = (1U << 4), /**< ARPEN BIT */ - I2C_CON1_PECEN = (1U << 5), /**< PECEN BIT */ - I2C_CON1_GCEN = (1U << 6), /**< GCEN BIT */ - I2C_CON1_DISCS = (1U << 7), /**< DISCS BIT */ - I2C_CON1_START = (1U << 8), /**< START BIT */ - I2C_CON1_STOP = (1U << 9), /**< STOP BIT */ - I2C_CON1_ACKEN = (1U << 10), /**< ACKEN BIT */ - I2C_CON1_POSAP = (1U << 11), /**< POSAP BIT */ - I2C_CON1_TRPEC = (1U << 12), /**< TRPEC BIT */ - I2C_CON1_ALARM = (1U << 13), /**< ALARM BIT */ - I2C_CON1_SRST = (1U << 15), /**< SRST BIT */ +typedef enum { + I2C_CON1_PEN = (1U << 0), /**< PEN BIT */ + I2C_CON1_PMOD = (1U << 1), /**< PMOD BIT */ + I2C_CON1_SMBMOD = (1U << 3), /**< SMBMOD BIT */ + I2C_CON1_ARPEN = (1U << 4), /**< ARPEN BIT */ + I2C_CON1_PECEN = (1U << 5), /**< PECEN BIT */ + I2C_CON1_GCEN = (1U << 6), /**< GCEN BIT */ + I2C_CON1_DISCS = (1U << 7), /**< DISCS BIT */ + I2C_CON1_START = (1U << 8), /**< START BIT */ + I2C_CON1_STOP = (1U << 9), /**< STOP BIT */ + I2C_CON1_ACKEN = (1U << 10), /**< ACKEN BIT */ + I2C_CON1_POSAP = (1U << 11), /**< POSAP BIT */ + I2C_CON1_TRPEC = (1U << 12), /**< TRPEC BIT */ + I2C_CON1_ALARM = (1U << 13), /**< ALARM BIT */ + I2C_CON1_SRST = (1U << 15), /**< SRST BIT */ } i2c_con1_t; /** * @brief I2C CON2 Register */ -typedef enum -{ - I2C_CON2_CLKF = 0x3F, /**< CLKF BITS */ - I2C_CON2_CLKF_0 = (1U << 0), /**< CLKF_0 BIT */ - I2C_CON2_CLKF_1 = (1U << 1), /**< CLKF_1 BIT */ - I2C_CON2_CLKF_2 = (1U << 2), /**< CLKF_2 BIT */ - I2C_CON2_CLKF_3 = (1U << 3), /**< CLKF_3 BIT */ - I2C_CON2_CLKF_4 = (1U << 4), /**< CLKF_4 BIT */ - I2C_CON2_CLKF_5 = (1U << 5), /**< CLKF_5 BIT */ - I2C_CON2_ERRIE = (1U << 8), /**< ERRIE BIT */ - I2C_CON2_EVTIE = (1U << 9), /**< EVTIE BIT */ - I2C_CON2_BUFIE = (1U << 10), /**< BUFIE BIT */ - I2C_CON2_DMAEN = (1U << 11), /**< DMAEN BIT */ - I2C_CON2_LDMA = (1U << 12), /**< LDMA BIT */ +typedef enum { + I2C_CON2_CLKF = 0x3FU, /**< CLKF BITS */ + I2C_CON2_CLKF_0 = (1U << 0), /**< CLKF_0 BIT */ + I2C_CON2_CLKF_1 = (1U << 1), /**< CLKF_1 BIT */ + I2C_CON2_CLKF_2 = (1U << 2), /**< CLKF_2 BIT */ + I2C_CON2_CLKF_3 = (1U << 3), /**< CLKF_3 BIT */ + I2C_CON2_CLKF_4 = (1U << 4), /**< CLKF_4 BIT */ + I2C_CON2_CLKF_5 = (1U << 5), /**< CLKF_5 BIT */ + I2C_CON2_ERRIE = (1U << 8), /**< ERRIE BIT */ + I2C_CON2_EVTIE = (1U << 9), /**< EVTIE BIT */ + I2C_CON2_BUFIE = (1U << 10), /**< BUFIE BIT */ + I2C_CON2_DMAEN = (1U << 11), /**< DMAEN BIT */ + I2C_CON2_LDMA = (1U << 12), /**< LDMA BIT */ } i2c_con2_t; /** * @brief I2C ADDR1 Register */ -typedef enum -{ - I2C_ADDR1_ADDH0 = (1U << 0), /**< ADDH0 BIT */ - I2C_ADDR1_ADDH1 = (1U << 1), /**< ADDH1 BIT */ - I2C_ADDR1_ADDH2 = (1U << 2), /**< ADDH2 BIT */ - I2C_ADDR1_ADDH3 = (1U << 3), /**< ADDH3 BIT */ - I2C_ADDR1_ADDH4 = (1U << 4), /**< ADDH4 BIT */ - I2C_ADDR1_ADDH5 = (1U << 5), /**< ADDH5 BIT */ - I2C_ADDR1_ADDH6 = (1U << 6), /**< ADDH6 BIT */ - I2C_ADDR1_ADDH7 = (1U << 7), /**< ADDH7 BIT */ - I2C_ADDR1_ADDH8 = (1U << 8), /**< ADDH8 BIT */ - I2C_ADDR1_ADDH9 = (1U << 9), /**< ADDH9 BIT */ - I2C_ADDR1_ADDTYPE = (1U << 15), /**< ADDTYPE BIT */ +typedef enum { + I2C_ADDR1_ADDH0 = (1U << 0), /**< ADDH0 BIT */ + I2C_ADDR1_ADDH1 = (1U << 1), /**< ADDH1 BIT */ + I2C_ADDR1_ADDH2 = (1U << 2), /**< ADDH2 BIT */ + I2C_ADDR1_ADDH3 = (1U << 3), /**< ADDH3 BIT */ + I2C_ADDR1_ADDH4 = (1U << 4), /**< ADDH4 BIT */ + I2C_ADDR1_ADDH5 = (1U << 5), /**< ADDH5 BIT */ + I2C_ADDR1_ADDH6 = (1U << 6), /**< ADDH6 BIT */ + I2C_ADDR1_ADDH7 = (1U << 7), /**< ADDH7 BIT */ + I2C_ADDR1_ADDH8 = (1U << 8), /**< ADDH8 BIT */ + I2C_ADDR1_ADDH9 = (1U << 9), /**< ADDH9 BIT */ + I2C_ADDR1_ADDTYPE = (1U << 15), /**< ADDTYPE BIT */ } i2c_addr1_t; /** * @brief I2C ADDR2 Register */ -typedef enum -{ - I2C_ADDR2_DUALEN = (1U << 0), /**< DUALEN BIT */ - I2C_ADDR2_ADD = (1U << 1), /**< ADD BIT */ +typedef enum { + I2C_ADDR2_DUALEN = (1U << 0), /**< DUALEN BIT */ + I2C_ADDR2_ADD = (1U << 1), /**< ADD BIT */ } i2c_addr2_t; /** * @brief I2C STAT1 Register */ -typedef enum -{ - I2C_STAT1_SB = (1U << 0), /**< SB BIT */ - I2C_STAT1_ADDR = (1U << 1), /**< ADDR BIT */ - I2C_STAT1_BTC = (1U << 2), /**< BTC BIT */ - I2C_STAT1_SENDADD10 = (1U << 3), /**< SENDADD10 BIT */ - I2C_STAT1_DETSTP = (1U << 4), /**< DETSTP BIT */ - I2C_STAT1_RXBNE = (1U << 6), /**< RXBNE BIT */ - I2C_STAT1_TXBE = (1U << 7), /**< TXBE BIT */ - I2C_STAT1_BUSERR = (1U << 8), /**< BUSERR BIT */ - I2C_STAT1_LARB = (1U << 9), /**< LARB BIT */ - I2C_STAT1_ACKERR = (1U << 10), /**< ACKERR BIT */ - I2C_STAT1_ROUERR = (1U << 11), /**< ROUERR BIT */ - I2C_STAT1_PECERR = (1U << 12), /**< PECERR BIT */ - I2C_STAT1_SMBTO = (1U << 14), /**< SMBTO BIT */ - I2C_STAT1_SMBALARM = (1U << 15), /**< SMBALARM BIT */ +typedef enum { + I2C_STAT1_SB = (1U << 0), /**< SB BIT */ + I2C_STAT1_ADDR = (1U << 1), /**< ADDR BIT */ + I2C_STAT1_BTC = (1U << 2), /**< BTC BIT */ + I2C_STAT1_SENDADD10 = (1U << 3), /**< SENDADD10 BIT */ + I2C_STAT1_DETSTP = (1U << 4), /**< DETSTP BIT */ + I2C_STAT1_RXBNE = (1U << 6), /**< RXBNE BIT */ + I2C_STAT1_TXBE = (1U << 7), /**< TXBE BIT */ + I2C_STAT1_BUSERR = (1U << 8), /**< BUSERR BIT */ + I2C_STAT1_LARB = (1U << 9), /**< LARB BIT */ + I2C_STAT1_ACKERR = (1U << 10), /**< ACKERR BIT */ + I2C_STAT1_ROUERR = (1U << 11), /**< ROUERR BIT */ + I2C_STAT1_PECERR = (1U << 12), /**< PECERR BIT */ + I2C_STAT1_SMBTO = (1U << 14), /**< SMBTO BIT */ + I2C_STAT1_SMBALARM = (1U << 15), /**< SMBALARM BIT */ } i2c_stat1_t; /** * @brief I2C STAT2 Register */ -typedef enum -{ - I2C_STAT2_MASTER = (1U << 0), /**< MASTER BIT */ - I2C_STAT2_BSYF = (1U << 1), /**< BSYF BIT */ - I2C_STAT2_TRF = (1U << 2), /**< TRF BIT */ - I2C_STAT2_RXGCF = (1U << 4), /**< RXGCF BIT */ - I2C_STAT2_SMBDEF = (1U << 5), /**< SMBDEF BIT */ - I2C_STAT2_SMBHH = (1U << 6), /**< SMBHH BIT */ - I2C_STAT2_DUALF = (1U << 7), /**< DMF BIT */ - I2C_STAT2_PECV = (1U << 8), /**< PECV BIT */ +typedef enum { + I2C_STAT2_MASTER = (1U << 0), /**< MASTER BIT */ + I2C_STAT2_BSYF = (1U << 1), /**< BSYF BIT */ + I2C_STAT2_TRF = (1U << 2), /**< TRF BIT */ + I2C_STAT2_RXGCF = (1U << 4), /**< RXGCF BIT */ + I2C_STAT2_SMBDEF = (1U << 5), /**< SMBDEF BIT */ + I2C_STAT2_SMBHH = (1U << 6), /**< SMBHH BIT */ + I2C_STAT2_DUALF = (1U << 7), /**< DMF BIT */ + I2C_STAT2_PECV = (1U << 8), /**< PECV BIT */ } i2c_stat2_t; /** * @brief I2C CKCFG Register */ -typedef enum -{ - I2C_CKCFG_CLKSET = 0xFFF, /**< CLKSET BITS */ - I2C_CKCFG_DUTY = (1U << 14), /**< DUTY BIT */ - I2C_CKCFG_CLKMOD = (1U << 15), /**< CLKMOD BIT */ +typedef enum { + I2C_CKCFG_CLKSET = 0xFFFU, /**< CLKSET BITS */ + I2C_CKCFG_DUTY = (1U << 14), /**< DUTY BIT */ + I2C_CKCFG_CLKMOD = (1U << 15), /**< CLKMOD BIT */ } i2c_ckcfg_t; /** * @brief I2C RT Register */ -typedef enum -{ - I2C_RT_RISET = 0x3F, /**< RISET BITS */ +typedef enum { + I2C_RT_RISET = 0x3FU, /**< RISET BITS */ } i2c_trise_t; /** * @brief I2C Configuration Structure definition */ -typedef struct -{ - uint32_t clk_speed; /**< Specifies the clock frequency */ - i2c_duty_t duty; /**< Specifies the I2C fast mode duty cycle */ - uint32_t own_addr1; /**< Specifies the first device own address */ - i2c_addr_t addr_mode; /**< Specifies addressing mode */ - i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ - uint32_t own_addr2; /**< Specifies the second device own address */ - i2c_general_addr_t general_call; /**< Specifies if general call mode is selected */ - i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ +typedef struct { + uint32_t clk_speed; /**< Specifies the clock frequency */ + i2c_duty_t duty; /**< Specifies the I2C fast mode duty cycle */ + uint32_t own_addr1; /**< Specifies the first device own address */ + i2c_addr_t addr_mode; /**< Specifies addressing mode */ + i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ + uint32_t own_addr2; /**< Specifies the second device own address */ + i2c_general_addr_t general_call; /**< Specifies if general call mode is selected */ + i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ } i2c_init_t; /** * @brief I2C handle Structure definition */ -typedef struct i2c_handle_s -{ - I2C_TypeDef *perh; /**< I2C registers base address */ - i2c_init_t init; /**< I2C communication parameters */ - uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ - uint16_t xfer_size; /**< I2C transfer size */ - __IO uint16_t xfer_count; /**< I2C transfer counter */ +typedef struct i2c_handle_s { + I2C_TypeDef *perh; /**< I2C registers base address */ + i2c_init_t init; /**< I2C communication parameters */ + uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ + uint16_t xfer_size; /**< I2C transfer size */ + __IO uint16_t xfer_count; /**< I2C transfer counter */ #ifdef ALD_DMA - dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ + dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ #endif - lock_state_t lock; /**< I2C locking object */ - __IO i2c_state_t state; /**< I2C communication state */ - __IO i2c_mode_t mode; /**< I2C communication mode */ - __IO uint32_t error_code; /**< I2C Error code */ - - void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */ - void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */ - void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Tx completed callback */ - void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Rx completed callback */ - void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Tx to Memory completed callback */ - void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Rx from Memory completed callback */ - void (*error_callback)(struct i2c_handle_s *arg); /**< Error callback */ + lock_state_t lock; /**< I2C locking object */ + __IO i2c_state_t state; /**< I2C communication state */ + __IO i2c_mode_t mode; /**< I2C communication mode */ + __IO uint32_t error_code; /**< I2C Error code */ + + void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */ + void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */ + void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Tx completed callback */ + void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Rx completed callback */ + void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Tx to Memory completed callback */ + void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Rx from Memory completed callback */ + void (*error_callback)(struct i2c_handle_s *arg); /**< Error callback */ } i2c_handle_t; /** @@ -349,19 +328,19 @@ typedef struct i2c_handle_s */ #define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET) #define I2C_CLEAR_ADDRFLAG(x) \ - do { \ - __IO uint32_t tmpreg; \ - tmpreg = (x)->perh->STAT1; \ - tmpreg = (x)->perh->STAT2; \ - UNUSED(tmpreg); \ - } while (0) +do { \ + __IO uint32_t tmpreg; \ + tmpreg = (x)->perh->STAT1; \ + tmpreg = (x)->perh->STAT2; \ + UNUSED(tmpreg); \ +} while (0) #define __I2C_CLEAR_STOPFLAG(x) \ - do { \ - __IO uint32_t tmpreg; \ - tmpreg = (x)->perh->STAT1; \ - tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN); \ - UNUSED(tmpreg); \ - } while (0) +do { \ + __IO uint32_t tmpreg; \ + tmpreg = (x)->perh->STAT1; \ + tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN); \ + UNUSED(tmpreg); \ +} while (0) #define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) #define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) /** @@ -372,56 +351,56 @@ typedef struct i2c_handle_s * @{ */ #define IS_I2C_TYPE(x) (((x) == I2C0) || \ - ((x) == I2C1)) + ((x) == I2C1)) #define IS_I2C_ADDRESSING_MODE(x) (((x) == I2C_ADDR_7BIT) || \ - ((x) == I2C_ADDR_10BIT)) + ((x) == I2C_ADDR_10BIT)) #define IS_I2C_DUAL_ADDRESS(x) (((x) == I2C_DUALADDR_DISABLE) || \ - ((x) == I2C_DUALADDR_ENABLE)) + ((x) == I2C_DUALADDR_ENABLE)) #define IS_I2C_GENERAL_CALL(x) (((x) == I2C_GENERALCALL_DISABLE) || \ - ((x) == I2C_GENERALCALL_ENABLE)) + ((x) == I2C_GENERALCALL_ENABLE)) #define IS_I2C_MEMADD_size(x) (((x) == I2C_MEMADD_SIZE_8BIT) || \ - ((x) == I2C_MEMADD_SIZE_16BIT)) + ((x) == I2C_MEMADD_SIZE_16BIT)) #define IS_I2C_NO_STRETCH(x) (((x) == I2C_NOSTRETCH_DISABLE) || \ - ((x) == I2C_NOSTRETCH_ENABLE)) + ((x) == I2C_NOSTRETCH_ENABLE)) #define IS_I2C_OWN_ADDRESS1(x) (((x) & (uint32_t)(0xFFFFFC00)) == 0) #define IS_I2C_OWN_ADDRESS2(x) (((x) & (uint32_t)(0xFFFFFF01)) == 0) #define IS_I2C_CLOCK_SPEED(x) (((x) > 0) && ((x) <= I2C_FAST_MODE_MAX_CLK)) #define IS_I2C_DUTY_CYCLE(x) (((x) == I2C_DUTYCYCLE_2) || \ - ((x) == I2C_DUTYCYCLE_16_9)) + ((x) == I2C_DUTYCYCLE_16_9)) #define IS_I2C_IT_TYPE(x) (((x) == I2C_IT_BUF) || \ - ((x) == I2C_IT_EVT) || \ - ((x) == I2C_IT_ERR)) + ((x) == I2C_IT_EVT) || \ + ((x) == I2C_IT_ERR)) #define IS_I2C_FLAG(x) (((x) == I2C_FLAG_SB) || \ - ((x) == I2C_FLAG_ADDR) || \ - ((x) == I2C_FLAG_BTF) || \ - ((x) == I2C_FLAG_ADD10) || \ - ((x) == I2C_FLAG_STOPF) || \ - ((x) == I2C_FLAG_RXNE) || \ - ((x) == I2C_FLAG_TXE) || \ - ((x) == I2C_FLAG_BERR) || \ - ((x) == I2C_FLAG_ARLO) || \ - ((x) == I2C_FLAG_AF) || \ - ((x) == I2C_FLAG_OVR) || \ - ((x) == I2C_FLAG_PECERR) || \ - ((x) == I2C_FLAG_TIMEOUT) || \ - ((x) == I2C_FLAG_SMBALERT) || \ - ((x) == I2C_FLAG_MSL) || \ - ((x) == I2C_FLAG_BUSY) || \ - ((x) == I2C_FLAG_TRA) || \ - ((x) == I2C_FLAG_GENCALL) || \ - ((x) == I2C_FLAG_SMBDEFAULT) || \ - ((x) == I2C_FLAG_SMBHOST) || \ - ((x) == I2C_FLAG_DUALF)) + ((x) == I2C_FLAG_ADDR) || \ + ((x) == I2C_FLAG_BTF) || \ + ((x) == I2C_FLAG_ADD10) || \ + ((x) == I2C_FLAG_STOPF) || \ + ((x) == I2C_FLAG_RXNE) || \ + ((x) == I2C_FLAG_TXE) || \ + ((x) == I2C_FLAG_BERR) || \ + ((x) == I2C_FLAG_ARLO) || \ + ((x) == I2C_FLAG_AF) || \ + ((x) == I2C_FLAG_OVR) || \ + ((x) == I2C_FLAG_PECERR) || \ + ((x) == I2C_FLAG_TIMEOUT) || \ + ((x) == I2C_FLAG_SMBALERT) || \ + ((x) == I2C_FLAG_MSL) || \ + ((x) == I2C_FLAG_BUSY) || \ + ((x) == I2C_FLAG_TRA) || \ + ((x) == I2C_FLAG_GENCALL) || \ + ((x) == I2C_FLAG_SMBDEFAULT) || \ + ((x) == I2C_FLAG_SMBHOST) || \ + ((x) == I2C_FLAG_DUALF)) #define I2C_FREQ_RANGE(x) ((x) / 1000000) #define I2C_RISE_TIME(x, u) (((u) <= I2C_STANDARD_MODE_MAX_CLK) ? ((x) + 1) :\ ((((x) * 300) / 1000) + 1)) #define I2C_SPEED_STANDARD(x, y) (((((x) / ((y) << 1)) & I2C_CKCFG_CLKSET) < 4) ? 4:\ - ((x) / ((y) << 1))) + ((x) / ((y) << 1))) #define I2C_SPEED_FAST(x, y, z) (((z) == I2C_DUTYCYCLE_2) ? ((x) / ((y) * 3)) :\ (((x) / ((y) * 25)) | I2C_DUTYCYCLE_16_9)) #define I2C_SPEED(x, y, z) (((y) <= 100000) ? (I2C_SPEED_STANDARD((x), (y))) :\ - ((I2C_SPEED_FAST((x), (y), (z)) & I2C_CKCFG_CLKSET) == 0) ? 1 : \ + ((I2C_SPEED_FAST((x), (y), (z)) & I2C_CKCFG_CLKSET) == 0) ? 1 : \ ((I2C_SPEED_FAST((x), (y), (z))) | I2C_CKCFG_CLKMOD)) #define I2C_MEM_ADD_MSB(x) ((uint8_t)((uint16_t)(((uint16_t)((x) &\ (uint16_t)(0xFF00))) >> 8))) @@ -432,7 +411,7 @@ typedef struct i2c_handle_s #define I2C_10BIT_HEADER_WRITE(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) #define I2C_10BIT_HEADER_READ(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ - (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) + (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) /** * @} */ @@ -454,41 +433,41 @@ ald_status_t ald_i2c_reset(i2c_handle_t *hperh); /** @addtogroup I2C_Public_Functions_Group2 * @{ */ -/** Blocking mode: Polling */ + /** Blocking mode: Polling */ ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint32_t timeout); + uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout); -/** Non-Blocking mode: Interrupt */ + /** Non-Blocking mode: Interrupt */ ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); #ifdef ALD_DMA -/** Non-Blocking mode: DMA */ + /** Non-Blocking mode: DMA */ ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint8_t channel); + uint8_t *buf, uint16_t size, uint8_t channel); ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint8_t channel); + uint8_t *buf, uint16_t size, uint8_t channel); ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel); + uint8_t *buf, uint16_t size, uint8_t channel); ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel); + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel); #endif /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_iap.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_iap.h index 7a841e7c2a32601e2bc3445920576765863ed8dd..a777fca4a9ddc55f06be917d4544a9c71ef16d38 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_iap.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_iap.h @@ -36,10 +36,10 @@ extern "C" { * @defgroup IAP_Private_Macros IAP Private Macros * @{ */ -#define IAP_WSP_ADDR 0x10000000 -#define IAP_PE_ADDR 0x10000004 -#define IAP_WP_ADDR 0x10000008 -#define IAP_DWP_ADDR 0x1000000c +#define IAP_WSP_ADDR 0x10000000U +#define IAP_PE_ADDR 0x10000004U +#define IAP_WP_ADDR 0x10000008U +#define IAP_DWP_ADDR 0x1000000cU /** * @} */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lcd.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lcd.h index 393a280b857c28595e4b79376bbf01ff77aa9dec..9b14bdb67fb3bd82cea9b4d7f01117104cc1472e 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lcd.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lcd.h @@ -38,237 +38,219 @@ extern "C" { /** * @brief Lcd vlcd voltage type */ -typedef enum -{ - LCD_VCHPS_3V2 = 0, /**< 3.2V */ - LCD_VCHPS_3V8 = 1, /**< 3.8V */ - LCD_VCHPS_4V8 = 2, /**< 4.8V */ - LCD_VCHPS_5V4 = 3, /**< 5.4V */ +typedef enum { + LCD_VCHPS_3V2 = 0U, /**< 3.2V */ + LCD_VCHPS_3V8 = 1U, /**< 3.8V */ + LCD_VCHPS_4V8 = 2U, /**< 4.8V */ + LCD_VCHPS_5V4 = 3U, /**< 5.4V */ } lcd_vchps_t; /** * @brief Lcd function type */ -typedef enum -{ - LCD_FUNC_DISABLE = 0, /**< Lcd's function disable */ - LCD_FUNC_ENABLE = 1, /**< Lcd's function enable */ +typedef enum { + LCD_FUNC_DISABLE = 0U, /**< Lcd's function disable */ + LCD_FUNC_ENABLE = 1U, /**< Lcd's function enable */ } lcd_func_t; /** * @brief Lcd voltage type */ -typedef enum -{ - LCD_VSEL_VDD = 0, /**< VDD */ - LCD_VSEL_CP = 1, /**< Charge pump output */ - LCD_VSEL_VLCD = 2, /**< VLCD input */ +typedef enum { + LCD_VSEL_VDD = 0U, /**< VDD */ + LCD_VSEL_CP = 1U, /**< Charge pump output */ + LCD_VSEL_VLCD = 2U, /**< VLCD input */ } lcd_vsel_t; /** * @brief Lcd resistance select bit */ -typedef enum -{ - LCD_RES_1MOHM = 0, /**< 1M ohm */ - LCD_RES_2MOHM = 1, /**< 2M ohm */ - LCD_RES_3MOHM = 2, /**< 3M ohm */ +typedef enum { + LCD_RES_1MOHM = 0U, /**< 1M ohm */ + LCD_RES_2MOHM = 1U, /**< 2M ohm */ + LCD_RES_3MOHM = 2U, /**< 3M ohm */ } lcd_res_t; /** * @brief Lcd bias selector */ -typedef enum -{ - LCD_BIAS_1_4 = 0, /**< 1/4 bias */ - LCD_BIAS_1_2 = 2, /**< 1/2 bias */ - LCD_BIAS_1_3 = 3, /**< 1/3 bias */ +typedef enum { + LCD_BIAS_1_4 = 0U, /**< 1/4 bias */ + LCD_BIAS_1_2 = 2U, /**< 1/2 bias */ + LCD_BIAS_1_3 = 3U, /**< 1/3 bias */ } lcd_bias_t; /** * @brief Lcd duty */ -typedef enum -{ - LCD_DUTY_STATIC = 0, /**< Static duty (COM0) */ - LCD_DUTY_1_2 = 1, /**< 1/2 duty (COM0~COM1) */ - LCD_DUTY_1_3 = 2, /**< 1/3 duty (COM0~COM2) */ - LCD_DUTY_1_4 = 3, /**< 1/4 duty (COM0~COM3) */ - LCD_DUTY_1_6 = 4, /**< 1/6 duty (COM0~COM5) */ - LCD_DUTY_1_8 = 5, /**< 1/8 duty (COM0~COM7) */ +typedef enum { + LCD_DUTY_STATIC = 0U, /**< Static duty (COM0) */ + LCD_DUTY_1_2 = 1U, /**< 1/2 duty (COM0~COM1) */ + LCD_DUTY_1_3 = 2U, /**< 1/3 duty (COM0~COM2) */ + LCD_DUTY_1_4 = 3U, /**< 1/4 duty (COM0~COM3) */ + LCD_DUTY_1_6 = 4U, /**< 1/6 duty (COM0~COM5) */ + LCD_DUTY_1_8 = 5U, /**< 1/8 duty (COM0~COM7) */ } lcd_duty_t; /** * @brief Lcd prescaler */ -typedef enum -{ - LCD_PRS_1 = 0, /**< CLKPRS = LCDCLK / 1 */ - LCD_PRS_2 = 1, /**< CLKPRS = LCDCLK / 2 */ - LCD_PRS_4 = 2, /**< CLKPRS = LCDCLK / 4 */ - LCD_PRS_8 = 3, /**< CLKPRS = LCDCLK / 8 */ - LCD_PRS_16 = 4, /**< CLKPRS = LCDCLK / 16 */ - LCD_PRS_32 = 5, /**< CLKPRS = LCDCLK / 32 */ - LCD_PRS_64 = 6, /**< CLKPRS = LCDCLK / 64 */ - LCD_PRS_128 = 7, /**< CLKPRS = LCDCLK / 128 */ - LCD_PRS_256 = 8, /**< CLKPRS = LCDCLK / 256 */ - LCD_PRS_512 = 9, /**< CLKPRS = LCDCLK / 512 */ - LCD_PRS_1024 = 10, /**< CLKPRS = LCDCLK / 1024 */ - LCD_PRS_2048 = 11, /**< CLKPRS = LCDCLK / 2048 */ - LCD_PRS_4096 = 12, /**< CLKPRS = LCDCLK / 4096 */ - LCD_PRS_8192 = 13, /**< CLKPRS = LCDCLK / 8192 */ - LCD_PRS_16384 = 14, /**< CLKPRS = LCDCLK / 16384 */ - LCD_PRS_32768 = 15, /**< CLKPRS = LCDCLK / 32768 */ +typedef enum { + LCD_PRS_1 = 0U, /**< CLKPRS = LCDCLK / 1 */ + LCD_PRS_2 = 1U, /**< CLKPRS = LCDCLK / 2 */ + LCD_PRS_4 = 2U, /**< CLKPRS = LCDCLK / 4 */ + LCD_PRS_8 = 3U, /**< CLKPRS = LCDCLK / 8 */ + LCD_PRS_16 = 4U, /**< CLKPRS = LCDCLK / 16 */ + LCD_PRS_32 = 5U, /**< CLKPRS = LCDCLK / 32 */ + LCD_PRS_64 = 6U, /**< CLKPRS = LCDCLK / 64 */ + LCD_PRS_128 = 7U, /**< CLKPRS = LCDCLK / 128 */ + LCD_PRS_256 = 8U, /**< CLKPRS = LCDCLK / 256 */ + LCD_PRS_512 = 9U, /**< CLKPRS = LCDCLK / 512 */ + LCD_PRS_1024 = 10U, /**< CLKPRS = LCDCLK / 1024 */ + LCD_PRS_2048 = 11U, /**< CLKPRS = LCDCLK / 2048 */ + LCD_PRS_4096 = 12U, /**< CLKPRS = LCDCLK / 4096 */ + LCD_PRS_8192 = 13U, /**< CLKPRS = LCDCLK / 8192 */ + LCD_PRS_16384 = 14U, /**< CLKPRS = LCDCLK / 16384 */ + LCD_PRS_32768 = 15U, /**< CLKPRS = LCDCLK / 32768 */ } lcd_prs_t; /** * @brief Lcd divider */ -typedef enum -{ - LCD_DIV_16 = 0, /**< DIVCLK = CLKPRS / 16 */ - LCD_DIV_17 = 1, /**< DIVCLK = CLKPRS / 17 */ - LCD_DIV_18 = 2, /**< DIVCLK = CLKPRS / 18 */ - LCD_DIV_19 = 3, /**< DIVCLK = CLKPRS / 19 */ - LCD_DIV_20 = 4, /**< DIVCLK = CLKPRS / 20 */ - LCD_DIV_21 = 5, /**< DIVCLK = CLKPRS / 21 */ - LCD_DIV_22 = 6, /**< DIVCLK = CLKPRS / 22 */ - LCD_DIV_23 = 7, /**< DIVCLK = CLKPRS / 23 */ - LCD_DIV_24 = 8, /**< DIVCLK = CLKPRS / 24 */ - LCD_DIV_25 = 9, /**< DIVCLK = CLKPRS / 25 */ - LCD_DIV_26 = 10, /**< DIVCLK = CLKPRS / 26 */ - LCD_DIV_27 = 11, /**< DIVCLK = CLKPRS / 27 */ - LCD_DIV_28 = 12, /**< DIVCLK = CLKPRS / 28 */ - LCD_DIV_29 = 13, /**< DIVCLK = CLKPRS / 29 */ - LCD_DIV_30 = 14, /**< DIVCLK = CLKPRS / 30 */ - LCD_DIV_31 = 15, /**< DIVCLK = CLKPRS / 31 */ +typedef enum { + LCD_DIV_16 = 0U, /**< DIVCLK = CLKPRS / 16 */ + LCD_DIV_17 = 1U, /**< DIVCLK = CLKPRS / 17 */ + LCD_DIV_18 = 2U, /**< DIVCLK = CLKPRS / 18 */ + LCD_DIV_19 = 3U, /**< DIVCLK = CLKPRS / 19 */ + LCD_DIV_20 = 4U, /**< DIVCLK = CLKPRS / 20 */ + LCD_DIV_21 = 5U, /**< DIVCLK = CLKPRS / 21 */ + LCD_DIV_22 = 6U, /**< DIVCLK = CLKPRS / 22 */ + LCD_DIV_23 = 7U, /**< DIVCLK = CLKPRS / 23 */ + LCD_DIV_24 = 8U, /**< DIVCLK = CLKPRS / 24 */ + LCD_DIV_25 = 9U, /**< DIVCLK = CLKPRS / 25 */ + LCD_DIV_26 = 10U, /**< DIVCLK = CLKPRS / 26 */ + LCD_DIV_27 = 11U, /**< DIVCLK = CLKPRS / 27 */ + LCD_DIV_28 = 12U, /**< DIVCLK = CLKPRS / 28 */ + LCD_DIV_29 = 13U, /**< DIVCLK = CLKPRS / 29 */ + LCD_DIV_30 = 14U, /**< DIVCLK = CLKPRS / 30 */ + LCD_DIV_31 = 15U, /**< DIVCLK = CLKPRS / 31 */ } lcd_div_t; /** * @brief Lcd blink mode */ -typedef enum -{ - LCD_BLINK_OFF = 0, /**< Blink disabled */ - LCD_BLINK_SEG0_COM0 = 1, /**< Blink enabled on SEG0, COM0 */ - LCD_BLINK_SEG0_COMX2 = 2, /**< Blink enabled on SEG0, COMx2 */ - LCD_BLINK_ALLSEG_ALLCOM = 3, /**< Blink enabled on all SEG and all COM */ +typedef enum { + LCD_BLINK_OFF = 0U, /**< Blink disabled */ + LCD_BLINK_SEG0_COM0 = 1U, /**< Blink enabled on SEG0, COM0 */ + LCD_BLINK_SEG0_COMX2 = 2U, /**< Blink enabled on SEG0, COMx2 */ + LCD_BLINK_ALLSEG_ALLCOM = 3U, /**< Blink enabled on all SEG and all COM */ } lcd_blink_t; /** * @brief Lcd blink frequency */ -typedef enum -{ - LCD_BLFRQ_8 = 0, /**< DIVCLK / 8 */ - LCD_BLFRQ_16 = 1, /**< DIVCLK / 16 */ - LCD_BLFRQ_32 = 2, /**< DIVCLK / 32 */ - LCD_BLFRQ_64 = 3, /**< DIVCLK / 64 */ - LCD_BLFRQ_128 = 4, /**< DIVCLK / 128 */ - LCD_BLFRQ_256 = 5, /**< DIVCLK / 256 */ - LCD_BLFRQ_512 = 6, /**< DIVCLK / 512 */ - LCD_BLFRQ_1024 = 7, /**< DIVCLK / 1024 */ +typedef enum { + LCD_BLFRQ_8 = 0U, /**< DIVCLK / 8 */ + LCD_BLFRQ_16 = 1U, /**< DIVCLK / 16 */ + LCD_BLFRQ_32 = 2U, /**< DIVCLK / 32 */ + LCD_BLFRQ_64 = 3U, /**< DIVCLK / 64 */ + LCD_BLFRQ_128 = 4U, /**< DIVCLK / 128 */ + LCD_BLFRQ_256 = 5U, /**< DIVCLK / 256 */ + LCD_BLFRQ_512 = 6U, /**< DIVCLK / 512 */ + LCD_BLFRQ_1024 = 7U, /**< DIVCLK / 1024 */ } lcd_blfrq_t; /** * @brief Lcd dead time */ -typedef enum -{ - LCD_DEAD_TIME_NONE = 0, /**< No dead time */ - LCD_DEAD_TIME_1_DIVCLK = 1, /**< Dead time is 1 divclk */ - LCD_DEAD_TIME_2_DIVCLK = 2, /**< Dead time is 2 divclk */ - LCD_DEAD_TIME_3_DIVCLK = 3, /**< Dead time is 3 divclk */ - LCD_DEAD_TIME_4_DIVCLK = 4, /**< Dead time is 4 divclk */ - LCD_DEAD_TIME_5_DIVCLK = 5, /**< Dead time is 5 divclk */ - LCD_DEAD_TIME_6_DIVCLK = 6, /**< Dead time is 6 divclk */ - LCD_DEAD_TIME_7_DIVCLK = 7, /**< Dead time is 7 divclk */ +typedef enum { + LCD_DEAD_TIME_NONE = 0U, /**< No dead time */ + LCD_DEAD_TIME_1_DIVCLK = 1U, /**< Dead time is 1 divclk */ + LCD_DEAD_TIME_2_DIVCLK = 2U, /**< Dead time is 2 divclk */ + LCD_DEAD_TIME_3_DIVCLK = 3U, /**< Dead time is 3 divclk */ + LCD_DEAD_TIME_4_DIVCLK = 4U, /**< Dead time is 4 divclk */ + LCD_DEAD_TIME_5_DIVCLK = 5U, /**< Dead time is 5 divclk */ + LCD_DEAD_TIME_6_DIVCLK = 6U, /**< Dead time is 6 divclk */ + LCD_DEAD_TIME_7_DIVCLK = 7U, /**< Dead time is 7 divclk */ } lcd_dead_t; /** * @brief Lcd pulse keep time */ -typedef enum -{ - LCD_PON_NONE = 0, /**< No pulse keep time */ - LCD_PON_1_PRSCLK = 1, /**< Pulse keep 1 prsclk */ - LCD_PON_2_PRSCLK = 2, /**< Pulse keep 2 prsclk */ - LCD_PON_3_PRSCLK = 3, /**< Pulse keep 3 prsclk */ - LCD_PON_4_PRSCLK = 4, /**< Pulse keep 4 prsclk */ - LCD_PON_5_PRSCLK = 5, /**< Pulse keep 5 prsclk */ - LCD_PON_6_PRSCLK = 6, /**< Pulse keep 6 prsclk */ - LCD_PON_7_PRSCLK = 7, /**< Pulse keep 7 prsclk */ +typedef enum { + LCD_PON_NONE = 0U, /**< No pulse keep time */ + LCD_PON_1_PRSCLK = 1U, /**< Pulse keep 1 prsclk */ + LCD_PON_2_PRSCLK = 2U, /**< Pulse keep 2 prsclk */ + LCD_PON_3_PRSCLK = 3U, /**< Pulse keep 3 prsclk */ + LCD_PON_4_PRSCLK = 4U, /**< Pulse keep 4 prsclk */ + LCD_PON_5_PRSCLK = 5U, /**< Pulse keep 5 prsclk */ + LCD_PON_6_PRSCLK = 6U, /**< Pulse keep 6 prsclk */ + LCD_PON_7_PRSCLK = 7U, /**< Pulse keep 7 prsclk */ } lcd_pluse_on_t; /** * @brief Lcd vgs select */ -typedef enum -{ - LCD_VGS_0 = 0, /**< Grey level display voltage is 30/45 vlcd */ - LCD_VGS_1 = 1, /**< Grey level display voltage is 31/45 vlcd */ - LCD_VGS_2 = 2, /**< Grey level display voltage is 32/45 vlcd */ - LCD_VGS_3 = 3, /**< Grey level display voltage is 33/45 vlcd */ - LCD_VGS_4 = 4, /**< Grey level display voltage is 34/45 vlcd */ - LCD_VGS_5 = 5, /**< Grey level display voltage is 35/45 vlcd */ - LCD_VGS_6 = 6, /**< Grey level display voltage is 36/45 vlcd */ - LCD_VGS_7 = 7, /**< Grey level display voltage is 37/45 vlcd */ - LCD_VGS_8 = 8, /**< Grey level display voltage is 38/45 vlcd */ - LCD_VGS_9 = 9, /**< Grey level display voltage is 39/45 vlcd */ - LCD_VGS_10 = 10, /**< Grey level display voltage is 40/45 vlcd */ - LCD_VGS_11 = 11, /**< Grey level display voltage is 41/45 vlcd */ - LCD_VGS_12 = 12, /**< Grey level display voltage is 42/45 vlcd */ - LCD_VGS_13 = 13, /**< Grey level display voltage is 43/45 vlcd */ - LCD_VGS_14 = 14, /**< Grey level display voltage is 44/45 vlcd */ - LCD_VGS_15 = 15, /**< Grey level display voltage is equal to vlcd */ +typedef enum { + LCD_VGS_0 = 0U, /**< Grey level display voltage is 30/45 vlcd */ + LCD_VGS_1 = 1U, /**< Grey level display voltage is 31/45 vlcd */ + LCD_VGS_2 = 2U, /**< Grey level display voltage is 32/45 vlcd */ + LCD_VGS_3 = 3U, /**< Grey level display voltage is 33/45 vlcd */ + LCD_VGS_4 = 4U, /**< Grey level display voltage is 34/45 vlcd */ + LCD_VGS_5 = 5U, /**< Grey level display voltage is 35/45 vlcd */ + LCD_VGS_6 = 6U, /**< Grey level display voltage is 36/45 vlcd */ + LCD_VGS_7 = 7U, /**< Grey level display voltage is 37/45 vlcd */ + LCD_VGS_8 = 8U, /**< Grey level display voltage is 38/45 vlcd */ + LCD_VGS_9 = 9U, /**< Grey level display voltage is 39/45 vlcd */ + LCD_VGS_10 = 10U, /**< Grey level display voltage is 40/45 vlcd */ + LCD_VGS_11 = 11U, /**< Grey level display voltage is 41/45 vlcd */ + LCD_VGS_12 = 12U, /**< Grey level display voltage is 42/45 vlcd */ + LCD_VGS_13 = 13U, /**< Grey level display voltage is 43/45 vlcd */ + LCD_VGS_14 = 14U, /**< Grey level display voltage is 44/45 vlcd */ + LCD_VGS_15 = 15U, /**< Grey level display voltage is equal to vlcd */ } lcd_vgs_t; /** * @brief Lcd wave choose */ -typedef enum -{ - LCD_WAVE_A = 0, /**< Wave type is A */ - LCD_WAVE_B = 1, /**< Wave type is B */ +typedef enum { + LCD_WAVE_A = 0U, /**< Wave type is A */ + LCD_WAVE_B = 1U, /**< Wave type is B */ } lcd_wfs_t; /** * @brief Lcd status select bit */ -typedef enum -{ - LCD_STATUS_RDY = (1U << 0), /**< VLCD voltage state flag */ - LCD_STATUS_ENS = (1U << 1), /**< LCD Enable state flag*/ - LCD_STATUS_UDR = (1U << 2), /**< Update display request state flag */ - LCD_STATUS_FCRSF = (1U << 3), /**< LCD frame control sync flag */ - LCD_STATUS_ALL = 0xFFFFFFF, /**< All flag */ +typedef enum { + LCD_STATUS_RDY = (1U << 0), /**< VLCD voltage state flag */ + LCD_STATUS_ENS = (1U << 1), /**< LCD Enable state flag*/ + LCD_STATUS_UDR = (1U << 2), /**< Update display request state flag */ + LCD_STATUS_FCRSF = (1U << 3), /**< LCD frame control sync flag */ + LCD_STATUS_ALL = 0xFFFFFFFU, /**< All flag */ } lcd_status_t; /** * @brief Lcd interrupt type */ -typedef enum -{ - LCD_IT_SOF = (1U << 0), /**< Start of frame interrupt enable */ - LCD_IT_UDD = (1U << 1), /**< Update display done interrupt enable*/ +typedef enum { + LCD_IT_SOF = (1U << 0), /**< Start of frame interrupt enable */ + LCD_IT_UDD = (1U << 1), /**< Update display done interrupt enable*/ } lcd_it_t; /** * @brief Lcd interrupt flag */ -typedef enum -{ - LCD_FLAG_SOF = (1U << 0), /**< Start of frame interrupt enable flag*/ - LCD_FLAG_UDD = (1U << 1), /**< Update display done interrupt enable flag*/ +typedef enum { + LCD_FLAG_SOF = (1U << 0), /**< Start of frame interrupt enable flag*/ + LCD_FLAG_UDD = (1U << 1), /**< Update display done interrupt enable flag*/ } lcd_flag_t; /** * @brief Lcd interrupt type */ -typedef enum -{ - SEG_0_TO_31 = 0, /**< Segment 0 to 31 to be set */ - SEG_32_TO_59 = 1, /**< Segment 32 to 59 to be set */ +typedef enum { + SEG_0_TO_31 = 0U, /**< Segment 0 to 31 to be set */ + SEG_32_TO_59 = 1U, /**< Segment 32 to 59 to be set */ } lcd_seg_t; /** @@ -276,36 +258,35 @@ typedef enum */ typedef struct { - lcd_vsel_t lcd_vsel; /**< Lcd power choose */ - lcd_vchps_t lcd_vchps; /**< Charge pump voltage choose */ - lcd_func_t lcd_vbufld; /**< Low drive mode function */ - lcd_func_t lcd_vbufhd; /**< High drive mode function */ - uint32_t lcd_dsld; /**< Low drive mode level */ - uint32_t lcd_dshd; /**< High drive mode level */ - lcd_res_t lcd_resld; /**< Low dirve mode resistance choose */ - lcd_res_t lcd_reshd; /**< High dirve mode resistance choose */ - lcd_bias_t lcd_bias; /**< LCD bias */ - lcd_duty_t lcd_duty; /**< LCD duty */ - lcd_wfs_t lcd_wfs; /**< Wave choose */ - lcd_prs_t lcd_prs; /**< Lcd clock prs */ - lcd_div_t lcd_div; /**< Lcd div */ - lcd_dead_t lcd_dead; /**< Lcd dead time */ - lcd_pluse_on_t lcd_pon; /**< Lcd pluse on time */ - lcd_vgs_t lcd_vgs; /**< Lcd gray level display voltage */ - cmu_lcd_clock_sel_t clock; /**< Lcd clock choose */ + lcd_vsel_t lcd_vsel; /**< Lcd power choose */ + lcd_vchps_t lcd_vchps; /**< Charge pump voltage choose */ + lcd_func_t lcd_vbufld; /**< Low drive mode function */ + lcd_func_t lcd_vbufhd; /**< High drive mode function */ + uint32_t lcd_dsld; /**< Low drive mode level */ + uint32_t lcd_dshd; /**< High drive mode level */ + lcd_res_t lcd_resld; /**< Low dirve mode resistance choose */ + lcd_res_t lcd_reshd; /**< High dirve mode resistance choose */ + lcd_bias_t lcd_bias; /**< LCD bias */ + lcd_duty_t lcd_duty; /**< LCD duty */ + lcd_wfs_t lcd_wfs; /**< Wave choose */ + lcd_prs_t lcd_prs; /**< Lcd clock prs */ + lcd_div_t lcd_div; /**< Lcd div */ + lcd_dead_t lcd_dead; /**< Lcd dead time */ + lcd_pluse_on_t lcd_pon; /**< Lcd pluse on time */ + lcd_vgs_t lcd_vgs; /**< Lcd gray level display voltage */ + cmu_lcd_clock_sel_t clock; /**< Lcd clock choose */ } lcd_init_t; /** * @brief Lcd handle Structure definition */ -typedef struct lcd_handle_s -{ - LCD_TypeDef *perh; /**< LCD registers base address */ - lcd_init_t init; /**< LCD initialize parameters */ - lock_state_t lock; /**< Locking object */ +typedef struct lcd_handle_s { + LCD_TypeDef *perh; /**< LCD registers base address */ + lcd_init_t init; /**< LCD initialize parameters */ + lock_state_t lock; /**< Locking object */ - void (*display_cplt_cbk)(struct lcd_handle_s *arg); /**< Display completed callback */ - void (*frame_start_cbk)(struct lcd_handle_s *arg); /**< Frame start callback */ + void (*display_cplt_cbk)(struct lcd_handle_s *arg); /**< Display completed callback */ + void (*frame_start_cbk)(struct lcd_handle_s *arg); /**< Frame start callback */ } lcd_handle_t; /** @@ -327,77 +308,77 @@ typedef struct lcd_handle_s */ #define IS_LCD_PERH_TYPE(x) ((x) == LCD) #define IS_LCD_VCHPS_TYPE(x) (((x) == LCD_VCHPS_3V2) || \ - ((x) == LCD_VCHPS_3V8) || \ - ((x) == LCD_VCHPS_4V8) || \ - ((x) == LCD_VCHPS_5V4)) + ((x) == LCD_VCHPS_3V8) || \ + ((x) == LCD_VCHPS_4V8) || \ + ((x) == LCD_VCHPS_5V4)) #define IS_LCD_VSEL_TYPE(x) (((x) == LCD_VSEL_VDD) || \ - ((x) == LCD_VSEL_CP) || \ - ((x) == LCD_VSEL_VLCD)) + ((x) == LCD_VSEL_CP) || \ + ((x) == LCD_VSEL_VLCD)) #define IS_LCD_FUNC_TYPE(x) (((x) == LCD_FUNC_DISABLE) || \ - ((x) == LCD_FUNC_ENABLE)) + ((x) == LCD_FUNC_ENABLE)) #define IS_LCD_LEVEL_TYPE(x) (((x) > 0) | ((x) <= 0xF)) #define IS_LCD_RES_TYPE(x) (((x) == LCD_RES_1MOHM) || \ - ((x) == LCD_RES_2MOHM) || \ - ((x) == LCD_RES_3MOHM)) + ((x) == LCD_RES_2MOHM) || \ + ((x) == LCD_RES_3MOHM)) #define IS_LCD_BIAS_TYPE(x) (((x) == LCD_BIAS_1_4) || \ - ((x) == LCD_BIAS_1_2) || \ - ((x) == LCD_BIAS_1_3)) + ((x) == LCD_BIAS_1_2) || \ + ((x) == LCD_BIAS_1_3)) #define IS_LCD_DUTY_TYPE(x) (((x) == LCD_DUTY_STATIC) || \ - ((x) == LCD_DUTY_1_2) || \ - ((x) == LCD_DUTY_1_3) || \ - ((x) == LCD_DUTY_1_4) || \ - ((x) == LCD_DUTY_1_6) || \ - ((x) == LCD_DUTY_1_8)) + ((x) == LCD_DUTY_1_2) || \ + ((x) == LCD_DUTY_1_3) || \ + ((x) == LCD_DUTY_1_4) || \ + ((x) == LCD_DUTY_1_6) || \ + ((x) == LCD_DUTY_1_8)) #define IS_LCD_WFS_TYPE(x) (((x) == LCD_WAVE_A) || \ - ((x) == LCD_WAVE_B)) + ((x) == LCD_WAVE_B)) #define IS_LCD_PRS_TYPE(x) (((x) == LCD_PRS_1) || \ - ((x) == LCD_PRS_2) || \ - ((x) == LCD_PRS_4) || \ - ((x) == LCD_PRS_8) || \ - ((x) == LCD_PRS_16) || \ - ((x) == LCD_PRS_32) || \ - ((x) == LCD_PRS_64) || \ - ((x) == LCD_PRS_128) || \ - ((x) == LCD_PRS_256) || \ - ((x) == LCD_PRS_512) || \ - ((x) == LCD_PRS_1024) || \ - ((x) == LCD_PRS_2048) || \ - ((x) == LCD_PRS_4096) || \ - ((x) == LCD_PRS_8192) || \ - ((x) == LCD_PRS_16384) || \ - ((x) == LCD_PRS_32768)) + ((x) == LCD_PRS_2) || \ + ((x) == LCD_PRS_4) || \ + ((x) == LCD_PRS_8) || \ + ((x) == LCD_PRS_16) || \ + ((x) == LCD_PRS_32) || \ + ((x) == LCD_PRS_64) || \ + ((x) == LCD_PRS_128) || \ + ((x) == LCD_PRS_256) || \ + ((x) == LCD_PRS_512) || \ + ((x) == LCD_PRS_1024) || \ + ((x) == LCD_PRS_2048) || \ + ((x) == LCD_PRS_4096) || \ + ((x) == LCD_PRS_8192) || \ + ((x) == LCD_PRS_16384) || \ + ((x) == LCD_PRS_32768)) #define IS_LCD_DIV_TYPE(x) (((x) == LCD_DIV_16) || \ - ((x) == LCD_DIV_17) || \ - ((x) == LCD_DIV_18) || \ - ((x) == LCD_DIV_19) || \ - ((x) == LCD_DIV_20) || \ - ((x) == LCD_DIV_21) || \ - ((x) == LCD_DIV_22) || \ - ((x) == LCD_DIV_23) || \ - ((x) == LCD_DIV_24) || \ - ((x) == LCD_DIV_25) || \ - ((x) == LCD_DIV_26) || \ - ((x) == LCD_DIV_27) || \ - ((x) == LCD_DIV_28) || \ - ((x) == LCD_DIV_29) || \ - ((x) == LCD_DIV_30) || \ - ((x) == LCD_DIV_31)) + ((x) == LCD_DIV_17) || \ + ((x) == LCD_DIV_18) || \ + ((x) == LCD_DIV_19) || \ + ((x) == LCD_DIV_20) || \ + ((x) == LCD_DIV_21) || \ + ((x) == LCD_DIV_22) || \ + ((x) == LCD_DIV_23) || \ + ((x) == LCD_DIV_24) || \ + ((x) == LCD_DIV_25) || \ + ((x) == LCD_DIV_26) || \ + ((x) == LCD_DIV_27) || \ + ((x) == LCD_DIV_28) || \ + ((x) == LCD_DIV_29) || \ + ((x) == LCD_DIV_30) || \ + ((x) == LCD_DIV_31)) #define IS_LCD_BLINK_MODE(x) (((x) == LCD_BLINK_OFF) || \ - ((x) == LCD_BLINK_SEG0_COM0) || \ - ((x) == LCD_BLINK_SEG0_COMX2) || \ - ((x) == LCD_BLINK_ALLSEG_ALLCOM)) + ((x) == LCD_BLINK_SEG0_COM0) || \ + ((x) == LCD_BLINK_SEG0_COMX2) || \ + ((x) == LCD_BLINK_ALLSEG_ALLCOM)) #define IS_LCD_BLFRQ_TYPE(x) (((x) == LCD_BLFRQ_8) || \ - ((x) == LCD_BLFRQ_16) || \ - ((x) == LCD_BLFRQ_32) || \ - ((x) == LCD_BLFRQ_64) || \ - ((x) == LCD_BLFRQ_128) || \ - ((x) == LCD_BLFRQ_256) || \ - ((x) == LCD_BLFRQ_512) || \ - ((x) == LCD_BLFRQ_1024)) + ((x) == LCD_BLFRQ_16) || \ + ((x) == LCD_BLFRQ_32) || \ + ((x) == LCD_BLFRQ_64) || \ + ((x) == LCD_BLFRQ_128) || \ + ((x) == LCD_BLFRQ_256) || \ + ((x) == LCD_BLFRQ_512) || \ + ((x) == LCD_BLFRQ_1024)) #define IS_LCD_STATUS_TYPE(x) (((x) == LCD_STATUS_RDY) || \ ((x) == LCD_STATUS_ENS) || \ ((x) == LCD_STATUS_UDR) || \ - ((x) == LCD_STATUS_FCRSF) || \ + ((x) == LCD_STATUS_FCRSF) || \ ((x) == LCD_STATUS_ALL)) #define IS_LCD_CLEARFLAG_TYPE(x)(((x) == LCD_FLAG_SOF) || \ ((x) == LCD_FLAG_UDD) || \ @@ -405,41 +386,41 @@ typedef struct lcd_handle_s #define IS_LCD_IT_TYPE(x) (((x) == LCD_IT_SOF) || \ ((x) == LCD_IT_UDD)) #define IS_LCD_FLAG_TYPE(x) (((x) == LCD_FLAG_SOF) || \ - ((x) == LCD_FLAG_UDD)) + ((x) == LCD_FLAG_UDD)) #define IS_LCD_SEG_TYPE(x) (((x) == SEG_0_TO_31) || \ - ((x) == SEG_32_TO_59)) + ((x) == SEG_32_TO_59)) #define IS_LCD_DEAD_TYPE(x) (((x) == LCD_DEAD_TIME_NONE) || \ - ((x) == LCD_DEAD_TIME_1_DIVCLK) || \ - ((x) == LCD_DEAD_TIME_2_DIVCLK) || \ - ((x) == LCD_DEAD_TIME_3_DIVCLK) || \ - ((x) == LCD_DEAD_TIME_4_DIVCLK) || \ - ((x) == LCD_DEAD_TIME_5_DIVCLK) || \ - ((x) == LCD_DEAD_TIME_6_DIVCLK) || \ - ((x) == LCD_DEAD_TIME_7_DIVCLK)) + ((x) == LCD_DEAD_TIME_1_DIVCLK) || \ + ((x) == LCD_DEAD_TIME_2_DIVCLK) || \ + ((x) == LCD_DEAD_TIME_3_DIVCLK) || \ + ((x) == LCD_DEAD_TIME_4_DIVCLK) || \ + ((x) == LCD_DEAD_TIME_5_DIVCLK) || \ + ((x) == LCD_DEAD_TIME_6_DIVCLK) || \ + ((x) == LCD_DEAD_TIME_7_DIVCLK)) #define IS_LCD_PON_TYPE(x) (((x) == LCD_PON_NONE) || \ - ((x) == LCD_PON_1_PRSCLK) || \ - ((x) == LCD_PON_2_PRSCLK) || \ - ((x) == LCD_PON_3_PRSCLK) || \ - ((x) == LCD_PON_4_PRSCLK) || \ - ((x) == LCD_PON_5_PRSCLK) || \ - ((x) == LCD_PON_6_PRSCLK) || \ - ((x) == LCD_PON_7_PRSCLK)) + ((x) == LCD_PON_1_PRSCLK) || \ + ((x) == LCD_PON_2_PRSCLK) || \ + ((x) == LCD_PON_3_PRSCLK) || \ + ((x) == LCD_PON_4_PRSCLK) || \ + ((x) == LCD_PON_5_PRSCLK) || \ + ((x) == LCD_PON_6_PRSCLK) || \ + ((x) == LCD_PON_7_PRSCLK)) #define IS_LCD_VGS_TYPE(x) (((x) == LCD_VGS_0) || \ - ((x) == LCD_VGS_1) || \ - ((x) == LCD_VGS_2) || \ - ((x) == LCD_VGS_3) || \ - ((x) == LCD_VGS_4) || \ - ((x) == LCD_VGS_5) || \ - ((x) == LCD_VGS_6) || \ - ((x) == LCD_VGS_7) || \ - ((x) == LCD_VGS_8) || \ - ((x) == LCD_VGS_9) || \ - ((x) == LCD_VGS_10) || \ - ((x) == LCD_VGS_11) || \ - ((x) == LCD_VGS_12) || \ - ((x) == LCD_VGS_13) || \ - ((x) == LCD_VGS_14) || \ - ((x) == LCD_VGS_15)) + ((x) == LCD_VGS_1) || \ + ((x) == LCD_VGS_2) || \ + ((x) == LCD_VGS_3) || \ + ((x) == LCD_VGS_4) || \ + ((x) == LCD_VGS_5) || \ + ((x) == LCD_VGS_6) || \ + ((x) == LCD_VGS_7) || \ + ((x) == LCD_VGS_8) || \ + ((x) == LCD_VGS_9) || \ + ((x) == LCD_VGS_10) || \ + ((x) == LCD_VGS_11) || \ + ((x) == LCD_VGS_12) || \ + ((x) == LCD_VGS_13) || \ + ((x) == LCD_VGS_14) || \ + ((x) == LCD_VGS_15)) #define IS_LCD_BUFFER_TYPE(x) ((x) <= 15) /** diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lptim.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lptim.h index 7f8df81f8541ef1206275480cc453cc7e6e3a0cb..dc570df1c56670693b3cb2eaa7d88c7e753d35d0 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lptim.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lptim.h @@ -19,7 +19,7 @@ #define __ALD_LPTIM_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -41,179 +41,163 @@ extern "C" { /** * @brief LPTIM clock select */ -typedef enum -{ - LPTIM_CKSEL_INTERNAL = 0, /**< Select internal clock */ - LPTIM_CKSEL_EXTERNAL = 1, /**< Select external clock */ +typedef enum { + LPTIM_CKSEL_INTERNAL = 0U, /**< Select internal clock */ + LPTIM_CKSEL_EXTERNAL = 1U, /**< Select external clock */ } lptim_cksel_t; /** * @brief LPTIM clock pol */ -typedef enum -{ - LPTIM_CKPOL_RISING = 0, /**< using rising edge */ - LPTIM_CKPOL_FALLING = 1, /**< using falling edge */ +typedef enum { + LPTIM_CKPOL_RISING = 0U, /**< using rising edge */ + LPTIM_CKPOL_FALLING = 1U, /**< using falling edge */ } lptim_ckpol_t; /** * @brief LPTIM clock fliter */ -typedef enum -{ - LPTIM_CKFLT_0 = 0, /**< not clock filter */ - LPTIM_CKFLT_2 = 1, /**< 2 cycle filter */ - LPTIM_CKFLT_4 = 2, /**< 4 cycle filter */ - LPTIM_CKFLT_8 = 3, /**< 8 cycle filter */ +typedef enum { + LPTIM_CKFLT_0 = 0U, /**< not clock filter */ + LPTIM_CKFLT_2 = 1U, /**< 2 cycle filter */ + LPTIM_CKFLT_4 = 2U, /**< 4 cycle filter */ + LPTIM_CKFLT_8 = 3U, /**< 8 cycle filter */ } lptim_ckflt_t; /** * @brief LPTIM trigger fliter */ -typedef enum -{ - LPTIM_TRGFLT_0 = 0, /**< not clock filter */ - LPTIM_TRGFLT_2 = 1, /**< 2 cycle filter */ - LPTIM_TRGFLT_4 = 2, /**< 4 cycle filter */ - LPTIM_TRGFLT_8 = 3, /**< 8 cycle filter */ +typedef enum { + LPTIM_TRGFLT_0 = 0U, /**< not clock filter */ + LPTIM_TRGFLT_2 = 1U, /**< 2 cycle filter */ + LPTIM_TRGFLT_4 = 2U, /**< 4 cycle filter */ + LPTIM_TRGFLT_8 = 3U, /**< 8 cycle filter */ } lptim_trgflt_t; /** * @brief LPTIM prescaler */ -typedef enum -{ - LPTIM_PRESC_1 = 0, /**< No prescaler is used */ - LPTIM_PRESC_2 = 1, /**< Clock is divided by 2 */ - LPTIM_PRESC_4 = 2, /**< Clock is divided by 4 */ - LPTIM_PRESC_8 = 3, /**< Clock is divided by 8 */ - LPTIM_PRESC_16 = 4, /**< Clock is divided by 16 */ - LPTIM_PRESC_32 = 5, /**< Clock is divided by 32 */ - LPTIM_PRESC_64 = 6, /**< Clock is divided by 64 */ - LPTIM_PRESC_128 = 7, /**< Clock is divided by 128 */ +typedef enum { + LPTIM_PRESC_1 = 0U, /**< No prescaler is used */ + LPTIM_PRESC_2 = 1U, /**< Clock is divided by 2 */ + LPTIM_PRESC_4 = 2U, /**< Clock is divided by 4 */ + LPTIM_PRESC_8 = 3U, /**< Clock is divided by 8 */ + LPTIM_PRESC_16 = 4U, /**< Clock is divided by 16 */ + LPTIM_PRESC_32 = 5U, /**< Clock is divided by 32 */ + LPTIM_PRESC_64 = 6U, /**< Clock is divided by 64 */ + LPTIM_PRESC_128 = 7U, /**< Clock is divided by 128 */ } lptim_presc_t; /** * @brief LPTIM trig select */ -typedef enum -{ - LPTIM_TRIGSEL_EXT0 = 0, /**< Trigger select external channel 0 */ - LPTIM_TRIGSEL_EXT1 = 1, /**< Trigger select external channel 1 */ - LPTIM_TRIGSEL_EXT2 = 2, /**< Trigger select external channel 2 */ - LPTIM_TRIGSEL_EXT3 = 3, /**< Trigger select external channel 3 */ - LPTIM_TRIGSEL_EXT4 = 4, /**< Trigger select external channel 4 */ - LPTIM_TRIGSEL_EXT5 = 5, /**< Trigger select external channel 5 */ - LPTIM_TRIGSEL_EXT6 = 6, /**< Trigger select external channel 6 */ - LPTIM_TRIGSEL_EXT7 = 7, /**< Trigger select external channel 7 */ +typedef enum { + LPTIM_TRIGSEL_EXT0 = 0U, /**< Trigger select external channel 0 */ + LPTIM_TRIGSEL_EXT1 = 1U, /**< Trigger select external channel 1 */ + LPTIM_TRIGSEL_EXT2 = 2U, /**< Trigger select external channel 2 */ + LPTIM_TRIGSEL_EXT3 = 3U, /**< Trigger select external channel 3 */ + LPTIM_TRIGSEL_EXT4 = 4U, /**< Trigger select external channel 4 */ + LPTIM_TRIGSEL_EXT5 = 5U, /**< Trigger select external channel 5 */ + LPTIM_TRIGSEL_EXT6 = 6U, /**< Trigger select external channel 6 */ + LPTIM_TRIGSEL_EXT7 = 7U, /**< Trigger select external channel 7 */ } lptim_trigsel_t; /** * @brief LPTIM start mode select */ -typedef enum -{ - LPTIM_MODE_SINGLE = 0, /**< Start single mode */ - LPTIM_MODE_CONTINUOUS = 1, /**< Start continuous mode */ +typedef enum { + LPTIM_MODE_SINGLE = 0U, /**< Start single mode */ + LPTIM_MODE_CONTINUOUS = 1U, /**< Start continuous mode */ } lptim_mode_t; /** * @brief LPTIM trig en */ -typedef enum -{ - LPTIM_TRIGEN_SW = 0, /**< software trigger */ - LPTIM_TRIGEN_RISING = 1, /**< rising edge trigger */ - LPTIM_TRIGEN_FALLING = 2, /**< falling edge trigger */ - LPTIM_TRIGEN_BOTH = 3, /**< rising and falling edge trigger */ +typedef enum { + LPTIM_TRIGEN_SW = 0U, /**< software trigger */ + LPTIM_TRIGEN_RISING = 1U, /**< rising edge trigger */ + LPTIM_TRIGEN_FALLING = 2U, /**< falling edge trigger */ + LPTIM_TRIGEN_BOTH = 3U, /**< rising and falling edge trigger */ } lptim_trigen_t; /** * @brief LPTIM wave */ -typedef enum -{ - LPTIM_WAVE_NONE = 0, /**< Output close */ - LPTIM_WAVE_TOGGLE = 1, /**< Output toggle */ - LPTIM_WAVE_PULSE = 2, /**< Output pulse */ - LPTIM_WAVE_PWM = 3, /**< Output PWM */ +typedef enum { + LPTIM_WAVE_NONE = 0U, /**< Output close */ + LPTIM_WAVE_TOGGLE = 1U, /**< Output toggle */ + LPTIM_WAVE_PULSE = 2U, /**< Output pulse */ + LPTIM_WAVE_PWM = 3U, /**< Output PWM */ } lptim_wave_t; /** * @brief LPTIM interrupt */ -typedef enum -{ - LPTIM_IT_CMPMAT = 1, /**< Compare interrupt bit */ - LPTIM_IT_ARRMAT = 2, /**< Update interrupt bit */ - LPTIM_IT_EXTTRIG = 4, /**< external trigger interrupt bit */ +typedef enum { + LPTIM_IT_CMPMAT = 1U, /**< Compare interrupt bit */ + LPTIM_IT_ARRMAT = 2U, /**< Update interrupt bit */ + LPTIM_IT_EXTTRIG = 4U, /**< external trigger interrupt bit */ } lptim_it_t; /** * @brief LPTIM Interrupt flag */ -typedef enum -{ - LPTIM_FLAG_CMPMAT = 1, /**< Compare interrupt flag */ - LPTIM_FLAG_ARRMAT = 2, /**< Update interrupt flag */ - LPTIM_FLAG_EXTTRIG = 4, /**< Update interrupt flag */ +typedef enum { + LPTIM_FLAG_CMPMAT = 1U, /**< Compare interrupt flag */ + LPTIM_FLAG_ARRMAT = 2U, /**< Update interrupt flag */ + LPTIM_FLAG_EXTTRIG = 4U, /**< Update interrupt flag */ } lptim_flag_t; /** * @brief LPTIM state structures definition */ -typedef enum -{ - LPTIM_STATE_RESET = 0x00, /**< Peripheral not yet initialized or disabled */ - LPTIM_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - LPTIM_STATE_BUSY = 0x02, /**< An internal process is ongoing */ - LPTIM_STATE_TIMEOUT = 0x03, /**< Timeout state */ - LPTIM_STATE_ERROR = 0x04, /**< Reception process is ongoing */ +typedef enum { + LPTIM_STATE_RESET = 0x00U, /**< Peripheral not yet initialized or disabled */ + LPTIM_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + LPTIM_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ + LPTIM_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + LPTIM_STATE_ERROR = 0x04U, /**< Reception process is ongoing */ } lptim_state_t; /** * @brief LPTIM Init Structure definition */ -typedef struct -{ - lptim_presc_t psc; /**< Specifies the prescaler value */ - uint16_t arr; /**< Specifies the update value */ - uint16_t cmp; /**< Specifies the compare value */ - cmu_lp_perh_clock_sel_t clock; /**< Specifies the clock choose */ - lptim_mode_t mode; /**< Specifies the start mode */ +typedef struct { + lptim_presc_t psc; /**< Specifies the prescaler value */ + uint16_t arr; /**< Specifies the update value */ + uint16_t cmp; /**< Specifies the compare value */ + cmu_lp_perh_clock_sel_t clock; /**< Specifies the clock choose */ + lptim_mode_t mode; /**< Specifies the start mode */ } lptim_init_t; /** * @brief LPTIM trigger Structure definition */ -typedef struct -{ - lptim_trigen_t mode; /**< Specifies the trigger mode */ - lptim_trigsel_t sel; /**< Specifies the trigger source select */ +typedef struct { + lptim_trigen_t mode; /**< Specifies the trigger mode */ + lptim_trigsel_t sel; /**< Specifies the trigger source select */ } lptim_trigger_init_t; /** * @brief LPTIM trigger Structure definition */ -typedef struct -{ - lptim_cksel_t sel; /**< Specifies the clock select */ - lptim_ckpol_t polarity; /**< Specifies the clock polarity */ +typedef struct { + lptim_cksel_t sel; /**< Specifies the clock select */ + lptim_ckpol_t polarity; /**< Specifies the clock polarity */ } lptim_clock_source_init_t; /** * @brief LPTIM Handle Structure definition */ -typedef struct lptim_handle_s -{ - LPTIM_TypeDef *perh; /**< Register base address */ - lptim_init_t init; /**< LPTIM Time required parameters */ - lock_state_t lock; /**< Locking object */ - lptim_state_t state; /**< LPTIM operation state */ +typedef struct lptim_handle_s { + LPTIM_TypeDef *perh; /**< Register base address */ + lptim_init_t init; /**< LPTIM Time required parameters */ + lock_state_t lock; /**< Locking object */ + lptim_state_t state; /**< LPTIM operation state */ - void (*trig_cbk)(struct lptim_handle_s *arg); /**< Trigger callback */ - void (*update_cbk)(struct lptim_handle_s *arg); /**< Update callback */ - void (*cmp_cbk)(struct lptim_handle_s *arg); /**< Compare callback */ + void (*trig_cbk)(struct lptim_handle_s *arg); /**< Trigger callback */ + void (*update_cbk)(struct lptim_handle_s *arg); /**< Update callback */ + void (*cmp_cbk)(struct lptim_handle_s *arg); /**< Compare callback */ } lptim_handle_t; /** * @} @@ -241,45 +225,45 @@ typedef struct lptim_handle_s */ #define IS_LPTIM(x) ((x) == LPTIM0) #define IS_LPTIM_CKSEL(x) (((x) == LPTIM_CKSEL_INTERNAL) || \ - ((x) == LPTIM_CKSEL_EXTERNAL)) + ((x) == LPTIM_CKSEL_EXTERNAL)) #define IS_LPTIM_CKPOL(x) (((x) == LPTIM_CKPOL_RISING) || \ - ((x) == LPTIM_CKPOL_FALLING)) + ((x) == LPTIM_CKPOL_FALLING)) #define IS_LPTIM_MODE(x) (((x) == LPTIM_MODE_SINGLE) || \ - ((x) == LPTIM_MODE_CONTINUOUS)) + ((x) == LPTIM_MODE_CONTINUOUS)) #define IS_LPTIM_CKFLT(x) (((x) == LPTIM_CKFLT_0) || \ - ((x) == LPTIM_CKFLT_2) || \ - ((x) == LPTIM_CKFLT_4) || \ - ((x) == LPTIM_CKFLT_8)) + ((x) == LPTIM_CKFLT_2) || \ + ((x) == LPTIM_CKFLT_4) || \ + ((x) == LPTIM_CKFLT_8)) #define IS_LPTIM_TRGFLT(x) (((x) == LPTIM_TRGFLT_0) || \ - ((x) == LPTIM_TRGFLT_2) || \ - ((x) == LPTIM_TRGFLT_4) || \ - ((x) == LPTIM_TRGFLT_8)) + ((x) == LPTIM_TRGFLT_2) || \ + ((x) == LPTIM_TRGFLT_4) || \ + ((x) == LPTIM_TRGFLT_8)) #define IS_LPTIM_PRESC(x) (((x) == LPTIM_PRESC_1) || \ - ((x) == LPTIM_PRESC_2) || \ - ((x) == LPTIM_PRESC_4) || \ - ((x) == LPTIM_PRESC_8) || \ - ((x) == LPTIM_PRESC_16) || \ - ((x) == LPTIM_PRESC_32) || \ - ((x) == LPTIM_PRESC_64) || \ - ((x) == LPTIM_PRESC_128)) + ((x) == LPTIM_PRESC_2) || \ + ((x) == LPTIM_PRESC_4) || \ + ((x) == LPTIM_PRESC_8) || \ + ((x) == LPTIM_PRESC_16) || \ + ((x) == LPTIM_PRESC_32) || \ + ((x) == LPTIM_PRESC_64) || \ + ((x) == LPTIM_PRESC_128)) #define IS_LPTIM_TRIGSEL(x) (((x) == LPTIM_TRIGSEL_EXT0) || \ - ((x) == LPTIM_TRIGSEL_EXT1) || \ - ((x) == LPTIM_TRIGSEL_EXT2) || \ - ((x) == LPTIM_TRIGSEL_EXT3) || \ - ((x) == LPTIM_TRIGSEL_EXT4) || \ - ((x) == LPTIM_TRIGSEL_EXT5) || \ - ((x) == LPTIM_TRIGSEL_EXT6) || \ - ((x) == LPTIM_TRIGSEL_EXT7)) + ((x) == LPTIM_TRIGSEL_EXT1) || \ + ((x) == LPTIM_TRIGSEL_EXT2) || \ + ((x) == LPTIM_TRIGSEL_EXT3) || \ + ((x) == LPTIM_TRIGSEL_EXT4) || \ + ((x) == LPTIM_TRIGSEL_EXT5) || \ + ((x) == LPTIM_TRIGSEL_EXT6) || \ + ((x) == LPTIM_TRIGSEL_EXT7)) #define IS_LPTIM_TRIGEN(x) (((x) == LPTIM_TRIGEN_SW) || \ - ((x) == LPTIM_TRIGEN_RISING) || \ - ((x) == LPTIM_TRIGEN_FALLING) || \ - ((x) == LPTIM_TRIGEN_BOTH)) + ((x) == LPTIM_TRIGEN_RISING) || \ + ((x) == LPTIM_TRIGEN_FALLING) || \ + ((x) == LPTIM_TRIGEN_BOTH)) #define IS_LPTIM_IT(x) (((x) == LPTIM_IT_CMPMAT) || \ - ((x) == LPTIM_IT_ARRMAT) || \ - ((x) == LPTIM_IT_EXTTRIG)) + ((x) == LPTIM_IT_ARRMAT) || \ + ((x) == LPTIM_IT_EXTTRIG)) #define IS_LPTIM_FLAG(x) (((x) == LPTIM_FLAG_CMPMAT) || \ - ((x) == LPTIM_FLAG_ARRMAT) || \ - ((x) == LPTIM_FLAG_EXTTRIG)) + ((x) == LPTIM_FLAG_ARRMAT) || \ + ((x) == LPTIM_FLAG_EXTTRIG)) /** * @} */ @@ -303,6 +287,18 @@ void ald_lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt); /** @addtogroup LPTIM_Public_Functions_Group2 * @{ */ +ald_status_t ald_lptim_base_init(lptim_handle_t *hperh); +void ald_lptim_base_start(lptim_handle_t *hperh); +void ald_lptim_base_stop(lptim_handle_t *hperh); +void ald_lptim_base_start_by_it(lptim_handle_t *hperh); +void ald_lptim_base_stop_by_it(lptim_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup LPTIM_Public_Functions_Group3 + * @{ + */ ald_status_t ald_lptim_toggle_init(lptim_handle_t *hperh); void ald_lptim_toggle_start(lptim_handle_t *hperh); void ald_lptim_toggle_stop(lptim_handle_t *hperh); @@ -312,7 +308,7 @@ void ald_lptim_toggle_stop_by_it(lptim_handle_t *hperh); * @} */ -/** @addtogroup LPTIM_Public_Functions_Group3 +/** @addtogroup LPTIM_Public_Functions_Group4 * @{ */ ald_status_t ald_lptim_pulse_init(lptim_handle_t *hperh); @@ -324,7 +320,7 @@ void ald_lptim_pulse_stop_by_it(lptim_handle_t *hperh); * @} */ -/** @addtogroup LPTIM_Public_Functions_Group4 +/** @addtogroup LPTIM_Public_Functions_Group5 * @{ */ ald_status_t ald_lptim_pwm_init(lptim_handle_t *hperh); @@ -336,7 +332,7 @@ void ald_lptim_pwm_stop_by_it(lptim_handle_t *hperh); * @} */ -/** @addtogroup LPTIM_Public_Functions_Group5 +/** @addtogroup LPTIM_Public_Functions_Group6 * @{ */ void ald_lptim_irq_handler(lptim_handle_t *hperh); @@ -348,7 +344,7 @@ void ald_lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag); * @} */ -/** @addtogroup LPTIM_Public_Functions_Group6 +/** @addtogroup LPTIM_Public_Functions_Group7 * @{ */ lptim_state_t ald_lptim_get_state(lptim_handle_t *hperh); diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lpuart.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lpuart.h index fd8520b2cabaf001a0a391a86d2de07721bac2a4..fe9d619159837addfd2040aaf83c2b08fe5c86cd 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lpuart.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lpuart.h @@ -126,207 +126,192 @@ extern "C" { /** * @brief LPUART Word Length */ -typedef enum -{ - LPUART_WORD_LENGTH_5B = 0x0, /**< 5-bits */ - LPUART_WORD_LENGTH_6B = 0x1, /**< 6-bits */ - LPUART_WORD_LENGTH_7B = 0x2, /**< 7-bits */ - LPUART_WORD_LENGTH_8B = 0x3, /**< 8-bits */ - LPUART_WORD_LENGTH_9B = 0x4, /**< 9-bits */ +typedef enum { + LPUART_WORD_LENGTH_5B = 0x0U, /**< 5-bits */ + LPUART_WORD_LENGTH_6B = 0x1U, /**< 6-bits */ + LPUART_WORD_LENGTH_7B = 0x2U, /**< 7-bits */ + LPUART_WORD_LENGTH_8B = 0x3U, /**< 8-bits */ + LPUART_WORD_LENGTH_9B = 0x4U, /**< 9-bits */ } lpuart_word_length_t; /** * @brief LPUART Stop Bits */ -typedef enum -{ - LPUART_STOP_BITS_1 = 0x0, /**< 1-bits */ - LPUART_STOP_BITS_2 = 0x1, /**< 2-bits */ +typedef enum { + LPUART_STOP_BITS_1 = 0x0U, /**< 1-bits */ + LPUART_STOP_BITS_2 = 0x1U, /**< 2-bits */ } lpuart_stop_bits_t; /** * @brief LPUART Parity */ -typedef enum -{ - LPUART_PARITY_NONE = 0x0, /**< Not parity */ - LPUART_PARITY_ODD = 0x1, /**< Odd parity */ - LPUART_PARITY_EVEN = 0x3, /**< Even parity */ +typedef enum { + LPUART_PARITY_NONE = 0x0U, /**< Not parity */ + LPUART_PARITY_ODD = 0x1U, /**< Odd parity */ + LPUART_PARITY_EVEN = 0x3U, /**< Even parity */ } lpuart_parity_t; /** * @brief LPUART Mode */ -typedef enum -{ - LPUART_MODE_UART = 0x0, /**< UART */ - LPUART_MODE_IrDA = 0x2, /**< IrDA */ - LPUART_MODE_RS485 = 0x3, /**< RS485 */ +typedef enum { + LPUART_MODE_UART = 0x0U, /**< UART */ + LPUART_MODE_IrDA = 0x2U, /**< IrDA */ + LPUART_MODE_RS485 = 0x3U, /**< RS485 */ } lpuart_mode_t; /** * @brief LPUART Hardware Flow Control */ -typedef enum -{ - LPUART_HW_FLOW_CTL_NONE = 0x0, /**< None */ - LPUART_HW_FLOW_CTL_RTS = 0x1, /**< RTS */ - LPUART_HW_FLOW_CTL_CTS = 0x2, /**< CTS */ - LPUART_HW_FLOW_CTL_RTS_CTS = 0x3, /**< RTS & CTS */ +typedef enum { + LPUART_HW_FLOW_CTL_NONE = 0x0U, /**< None */ + LPUART_HW_FLOW_CTL_RTS = 0x1U, /**< RTS */ + LPUART_HW_FLOW_CTL_CTS = 0x2U, /**< CTS */ + LPUART_HW_FLOW_CTL_RTS_CTS = 0x3U, /**< RTS & CTS */ } lpuart_hw_flow_ctl_t; /** * @brief ALD LPUART State */ -typedef enum -{ - LPUART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - LPUART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - LPUART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - LPUART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - LPUART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ - LPUART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ - LPUART_STATE_TIMEOUT = 0x03, /**< Timeout state */ - LPUART_STATE_ERROR = 0x04, /**< Error */ +typedef enum { + LPUART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + LPUART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + LPUART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + LPUART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ + LPUART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ + LPUART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */ + LPUART_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + LPUART_STATE_ERROR = 0x04U, /**< Error */ } lpuart_state_t; /** * @brief LPUART Error Codes */ -typedef enum -{ - LPUART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ - LPUART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ - LPUART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ - LPUART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ - LPUART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ - LPUART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +typedef enum { + LPUART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ + LPUART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ + LPUART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ + LPUART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ + LPUART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ + LPUART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ } lpuart_error_t; /** * @brief LPUART Init structure definition */ -typedef struct -{ - uint32_t baud; /**< Specifies the lpuart communication baud rate */ - lpuart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ - lpuart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ - lpuart_parity_t parity; /**< Specifies the parity mode */ - lpuart_mode_t mode; /**< Specifies uart mode */ - lpuart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ - cmu_lp_perh_clock_sel_t clock; /**< Specifies clock, only support LOSC and LRC */ +typedef struct { + uint32_t baud; /**< Specifies the lpuart communication baud rate */ + lpuart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ + lpuart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ + lpuart_parity_t parity; /**< Specifies the parity mode */ + lpuart_mode_t mode; /**< Specifies uart mode */ + lpuart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ + cmu_lp_perh_clock_sel_t clock; /**< Specifies clock, only support LOSC and LRC */ } lpuart_init_t; /** * @brief LPUART handle structure definition */ -typedef struct lpuart_handle_s -{ - LPUART_TypeDef *perh; /**< LPUART registers base address */ - lpuart_init_t init; /**< LPUART communication parameters */ - uint8_t *tx_buf; /**< Pointer to LPUART Tx transfer Buffer */ - uint16_t tx_size; /**< LPUART Tx Transfer size */ - uint16_t tx_count; /**< LPUART Tx Transfer Counter */ - uint8_t *rx_buf; /**< Pointer to LPUART Rx transfer Buffer */ - uint16_t rx_size; /**< LPUART Rx Transfer size */ - uint16_t rx_count; /**< LPUART Rx Transfer Counter */ +typedef struct lpuart_handle_s { + LPUART_TypeDef *perh; /**< LPUART registers base address */ + lpuart_init_t init; /**< LPUART communication parameters */ + uint8_t *tx_buf; /**< Pointer to LPUART Tx transfer Buffer */ + uint16_t tx_size; /**< LPUART Tx Transfer size */ + uint16_t tx_count; /**< LPUART Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to LPUART Rx transfer Buffer */ + uint16_t rx_size; /**< LPUART Rx Transfer size */ + uint16_t rx_count; /**< LPUART Rx Transfer Counter */ #ifdef ALD_DMA - dma_handle_t hdmatx; /**< LPUART Tx DMA Handle parameters */ - dma_handle_t hdmarx; /**< LPUART Rx DMA Handle parameters */ + dma_handle_t hdmatx; /**< LPUART Tx DMA Handle parameters */ + dma_handle_t hdmarx; /**< LPUART Rx DMA Handle parameters */ #endif - lock_state_t lock; /**< Locking object */ - lpuart_state_t state; /**< LPUART communication state */ - lpuart_error_t err_code; /**< LPUART Error code */ + lock_state_t lock; /**< Locking object */ + lpuart_state_t state; /**< LPUART communication state */ + lpuart_error_t err_code; /**< LPUART Error code */ - void (*tx_cplt_cbk)(struct lpuart_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct lpuart_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct lpuart_handle_s *arg); /**< error callback */ + void (*tx_cplt_cbk)(struct lpuart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct lpuart_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct lpuart_handle_s *arg); /**< error callback */ } lpuart_handle_t; /** * @brief LPUART RS485 Configure Structure definition */ -typedef struct -{ - type_func_t RS485_NMM; /**< Normal Point Mode */ - type_func_t RS485_AAD; /**< Auto-Address Detect */ - type_func_t RS485_AUD; /**< Auto-Direction Mode */ - type_func_t RS485_ADD_DET; /**< Eable/Disable Address Detect */ - uint8_t RS485_ADDCMP; /**< Address for compare */ +typedef struct { + type_func_t RS485_NMM; /**< Normal Point Mode */ + type_func_t RS485_AAD; /**< Auto-Address Detect */ + type_func_t RS485_AUD; /**< Auto-Direction Mode */ + type_func_t RS485_ADD_DET; /**< Eable/Disable Address Detect */ + uint8_t RS485_ADDCMP; /**< Address for compare */ } lpuart_rs485_config_t; /** * @brief LPUART DMA Requests */ -typedef enum -{ - LPUART_DMA_REQ_TX = 0x0, /**< TX dma */ - LPUART_DMA_REQ_RX = 0x1, /**< RX dma */ +typedef enum { + LPUART_DMA_REQ_TX = 0x0U, /**< TX dma */ + LPUART_DMA_REQ_RX = 0x1U, /**< RX dma */ } lpuart_dma_req_t; /** * @brief LPUART RXFIFO size */ -typedef enum -{ - LPUART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */ - LPUART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */ - LPUART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */ - LPUART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */ +typedef enum { + LPUART_RXFIFO_1BYTE = 0x0U, /**< 1-Byte */ + LPUART_RXFIFO_4BYTE = 0x1U, /**< 4-Bytes */ + LPUART_RXFIFO_8BYTE = 0x2U, /**< 8-Bytes */ + LPUART_RXFIFO_14BYTE = 0x3U, /**< 14-Bytes */ } lpuart_rxfifo_t; /** * @brief LPUART Interrupts Types */ -typedef enum -{ - LPUART_IT_RBR = (1U << 0), /**< RBR */ - LPUART_IT_TBEMP = (1U << 1), /**< TBEMP */ - LPUART_IT_CTSDET = (1U << 2), /**< CTSDET */ - LPUART_IT_RXTO = (1U << 3), /**< RXTO */ - LPUART_IT_RXOV = (1U << 4), /**< RXOV */ - LPUART_IT_TXOV = (1U << 5), /**< TXOV */ - LPUART_IT_CTSWK = (1U << 7), /**< CTSWK */ - LPUART_IT_DATWK = (1U << 8), /**< DATWK */ - LPUART_IT_PERR = (1U << 9), /**< PERR */ - LPUART_IT_FERR = (1U << 10), /**< FERR */ - LPUART_IT_BRKERR = (1U << 11), /**< BRKERR */ - LPUART_IT_ADET = (1U << 12), /**< ADET */ - LPUART_IT_TC = (1U << 15), /**< TC */ +typedef enum { + LPUART_IT_RBR = (1U << 0), /**< RBR */ + LPUART_IT_TBEMP = (1U << 1), /**< TBEMP */ + LPUART_IT_CTSDET = (1U << 2), /**< CTSDET */ + LPUART_IT_RXTO = (1U << 3), /**< RXTO */ + LPUART_IT_RXOV = (1U << 4), /**< RXOV */ + LPUART_IT_TXOV = (1U << 5), /**< TXOV */ + LPUART_IT_CTSWK = (1U << 7), /**< CTSWK */ + LPUART_IT_DATWK = (1U << 8), /**< DATWK */ + LPUART_IT_PERR = (1U << 9), /**< PERR */ + LPUART_IT_FERR = (1U << 10), /**< FERR */ + LPUART_IT_BRKERR = (1U << 11), /**< BRKERR */ + LPUART_IT_ADET = (1U << 12), /**< ADET */ + LPUART_IT_TC = (1U << 15), /**< TC */ } lpuart_it_t; /** * @brief LPUART Flags Types */ -typedef enum -{ - LPUART_IF_RBR = (1U << 0), /**< RBR */ - LPUART_IF_TBEMP = (1U << 1), /**< TBEMP */ - LPUART_IF_CTSDET = (1U << 2), /**< CTSDET */ - LPUART_IF_RXTO = (1U << 3), /**< RXTO */ - LPUART_IF_RXOV = (1U << 4), /**< RXOV */ - LPUART_IF_TXOV = (1U << 5), /**< TXOV */ - LPUART_IF_CTSWK = (1U << 7), /**< CTSWK */ - LPUART_IF_DATWK = (1U << 8), /**< DATWK */ - LPUART_IF_PERR = (1U << 9), /**< PERR */ - LPUART_IF_FERR = (1U << 10), /**< FERR */ - LPUART_IF_BRKERR = (1U << 11), /**< BRKERR */ - LPUART_IF_ADET = (1U << 12), /**< ADET */ - LPUART_IF_TC = (1U << 15), /**< TC */ +typedef enum { + LPUART_IF_RBR = (1U << 0), /**< RBR */ + LPUART_IF_TBEMP = (1U << 1), /**< TBEMP */ + LPUART_IF_CTSDET = (1U << 2), /**< CTSDET */ + LPUART_IF_RXTO = (1U << 3), /**< RXTO */ + LPUART_IF_RXOV = (1U << 4), /**< RXOV */ + LPUART_IF_TXOV = (1U << 5), /**< TXOV */ + LPUART_IF_CTSWK = (1U << 7), /**< CTSWK */ + LPUART_IF_DATWK = (1U << 8), /**< DATWK */ + LPUART_IF_PERR = (1U << 9), /**< PERR */ + LPUART_IF_FERR = (1U << 10), /**< FERR */ + LPUART_IF_BRKERR = (1U << 11), /**< BRKERR */ + LPUART_IF_ADET = (1U << 12), /**< ADET */ + LPUART_IF_TC = (1U << 15), /**< TC */ } lpuart_flag_t; /** * @brief LPUART Status Types */ -typedef enum -{ - LPUART_STAT_RXEMP = (1U << 6), /**< RX FIFO empty */ - LPUART_STAT_RXFULL = (1U << 7), /**< RX FIFO full */ - LPUART_STAT_TXEMP = (1U << 14), /**< TX FIFO empty */ - LPUART_STAT_TXFULL = (1U << 15), /**< TX FIFO full */ - LPUART_STAT_TXIDLE = (1U << 16), /**< TX idle */ - LPUART_STAT_CTSSTAT = (1U << 17), /**< CTS status */ - LPUART_STAT_RTSSTAT = (1U << 18), /**< RTS status */ +typedef enum { + LPUART_STAT_RXEMP = (1U << 6), /**< RX FIFO empty */ + LPUART_STAT_RXFULL = (1U << 7), /**< RX FIFO full */ + LPUART_STAT_TXEMP = (1U << 14), /**< TX FIFO empty */ + LPUART_STAT_TXFULL = (1U << 15), /**< TX FIFO full */ + LPUART_STAT_TXIDLE = (1U << 16), /**< TX idle */ + LPUART_STAT_CTSSTAT = (1U << 17), /**< CTS status */ + LPUART_STAT_RTSSTAT = (1U << 18), /**< RTS status */ } lpuart_status_t; /** * @} @@ -352,10 +337,10 @@ typedef enum ((x) == LPUART_MODE_IrDA) || \ ((x) == LPUART_MODE_RS485)) #define IS_LPUART_HARDWARE_FLOW_CONTROL(x)\ - (((x) == LPUART_HW_FLOW_CTL_NONE) || \ - ((x) == LPUART_HW_FLOW_CTL_RTS) || \ - ((x) == LPUART_HW_FLOW_CTL_CTS) || \ - ((x) == LPUART_HW_FLOW_CTL_RTS_CTS)) + (((x) == LPUART_HW_FLOW_CTL_NONE) || \ + ((x) == LPUART_HW_FLOW_CTL_RTS) || \ + ((x) == LPUART_HW_FLOW_CTL_CTS) || \ + ((x) == LPUART_HW_FLOW_CTL_RTS_CTS)) #define IS_LPUART_DMAREQ(x) (((x) == LPUART_DMA_REQ_TX) || ((x) == LPUART_DMA_REQ_RX)) #define IS_LPUART_RXFIFO(x) (((x) == LPUART_RXFIFO_1BYTE) || \ ((x) == LPUART_RXFIFO_4BYTE) || \ @@ -388,15 +373,15 @@ typedef enum ((x) == LPUART_IF_ADET) || \ ((x) == LPUART_IF_TC)) #define IS_LPUART_STAT(x) (((x) == LPUART_STAT_RXEMP) || \ - ((x) == LPUART_STAT_RXFULL) || \ - ((x) == LPUART_STAT_TXEMP) || \ - ((x) == LPUART_STAT_TXFULL) || \ - ((x) == LPUART_STAT_TXIDLE) || \ - ((x) == LPUART_STAT_CTSSTAT) || \ - ((x) == LPUART_STAT_RTSSTAT)) - -#define LPUART_STATE_TX_MASK (1 << 4) -#define LPUART_STATE_RX_MASK (1 << 5) + ((x) == LPUART_STAT_RXFULL) || \ + ((x) == LPUART_STAT_TXEMP) || \ + ((x) == LPUART_STAT_TXFULL) || \ + ((x) == LPUART_STAT_TXIDLE) || \ + ((x) == LPUART_STAT_CTSSTAT) || \ + ((x) == LPUART_STAT_RTSSTAT)) + +#define LPUART_STATE_TX_MASK (1U << 4) +#define LPUART_STATE_RX_MASK (1U << 5) /** * @} */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pis.h index a40bc998d119597634ffde2fca08300e5164b7f6..c17b03cfd96c762dd6a6ab1d514d8e9aea7ae707 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pis.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pis.h @@ -18,7 +18,7 @@ #define __ALD_PIS_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -37,327 +37,277 @@ extern "C" { */ /** * @brief Producer entry - * @note ES32F065x: - * AD16C4T0--TIMER0 - * GP16C4T0--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - * - * ES32F033x: - * ES32F093x: - * GP16C4T0--TIMER0 - * GP16C4T1--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - */ -typedef enum -{ - PIS_NON = 0x0, /**< No async */ - PIS_GPIO_PIN0 = 0x10, /**< Pin0, level,support async */ - PIS_GPIO_PIN1 = 0x11, /**< Pin1, level,support async */ - PIS_GPIO_PIN2 = 0x12, /**< Pin2, level,support async */ - PIS_GPIO_PIN3 = 0x13, /**< Pin3, level,support async */ - PIS_GPIO_PIN4 = 0x14, /**< Pin4, level,support async */ - PIS_GPIO_PIN5 = 0x15, /**< Pin5, level,support async */ - PIS_GPIO_PIN6 = 0x16, /**< Pin6, level,support async */ - PIS_GPIO_PIN7 = 0x17, /**< Pin7, level,support async */ - PIS_GPIO_PIN8 = 0x18, /**< Pin8, level,support async */ - PIS_GPIO_PIN9 = 0x19, /**< Pin9, level,support async */ - PIS_GPIO_PIN10 = 0x1a, /**< Pin10, level,support async */ - PIS_GPIO_PIN11 = 0x1b, /**< Pin11, level,support async */ - PIS_GPIO_PIN12 = 0x1c, /**< Pin12, level,support async */ - PIS_GPIO_PIN13 = 0x1d, /**< Pin13, level,support async */ - PIS_GPIO_PIN14 = 0x1e, /**< Pin14, level,support async */ - PIS_GPIO_PIN15 = 0x1f, /**< Pin15, level,support async */ - PIS_ACMP_OUT0 = 0x30, /**< Acmp0 output, level,support async */ - PIS_ACMP_OUT1 = 0x31, /**< Acmp1 output, level,support async */ - PIS_DAC0_CH0 = 0x40, /**< Dac0 channel 0, pclk2 pulse,support async */ - PIS_DAC0_CH1 = 0x41, /**< Dac0 channel 1, pclk2 pulse,support async */ - PIS_ADC0_INJECT = 0x60, /**< Adc0 inject, pclk2 pulse,support async */ - PIS_ADC0_REGULAT = 0x61, /**< Adc0 regulat, pclk2 pulse,support async */ - PIS_ADC0_WINDOW = 0x62, /**< Adc0 window, no have */ - PIS_LVD = 0x70, /**< Lvd, level,support async */ - PIS_UART0_ASY_SEND = 0x80, /**< Uart0 asy send, pulse,support async */ - PIS_UART0_ASY_RECV = 0x81, /**< Uart0 asy recv, pulse,support async */ - PIS_UART0_IRDAOUT = 0x82, /**< Uart0 irdaout, level,support async */ - PIS_UART0_RTSOUT = 0x83, /**< Uart0 rtsout, level,support async */ - PIS_UART0_TXOUT = 0x84, /**< Uart0 txout, level,support async */ - PIS_UART0_SYN_SEND = 0x85, /**< Uart0 syn send, pulse,support async */ - PIS_UART0_SYN_RECV = 0x86, /**< Uart0 syn recv, pulse,support async */ - PIS_UART1_ASY_SEND = 0x90, /**< Uart1 asy send, pulse,support async */ - PIS_UART1_ASY_RECV = 0x91, /**< Uart1 asy recv, pulse,support async */ - PIS_UART1_IRDA = 0x92, /**< Uart1 irdaout, level,support async */ - PIS_UART1_RTS = 0x93, /**< Uart1 rtsout, level,support async */ - PIS_UART1_TXOUT = 0x94, /**< Uart1 txout, level,support async */ - PIS_UART1_SYN_SEND = 0x95, /**< Uart1 syn send, pulse,support async */ - PIS_UART1_SYN_RECV = 0x96, /**< Uart1 syn recv, pulse,support async */ - PIS_UART2_ASY_SEND = 0xa0, /**< Uart2 asy send, pulse,support async */ - PIS_UART2_ASY_RECV = 0xa1, /**< Uart2 asy recv, pulse,support async */ - PIS_UART2_IRDA = 0xa2, /**< Uart2 irdaout, level,support async */ - PIS_UART2_RTS = 0xa3, /**< Uart2 rtsout, level,support async */ - PIS_UART2_TXOUT = 0xa4, /**< Uart2 txout, level,support async */ - PIS_UART2_SYN_SEND = 0xa5, /**< Uart2 syn send, pulse,support async */ - PIS_UART2_SYN_RECV = 0xa6, /**< Uart2 syn recv, pulse,support async */ - PIS_UART3_ASY_SEND = 0xb1, /**< Uart3 asy send, pulse,support async */ - PIS_UART3_ASY_RECV = 0xb2, /**< Uart3 asy recv, pulse,support async */ - PIS_UART3_IRDA = 0xb3, /**< Uart3 irdaout, level,support async */ - PIS_UART3_RTS = 0xb4, /**< Uart3 rtsout, level,support async */ - PIS_UART3_TXOUT = 0xb5, /**< Uart3 txout, level,support async */ - PIS_UART3_SYN_SEND = 0xb6, /**< Uart3 syn send, pulse,support async */ - PIS_UART3_SYN_RECV = 0xb7, /**< Uart3 syn recv, pulse,support async */ - PIS_EUART0_RECV = 0xc0, /**< Euart0 recv, plck1 pulse */ - PIS_EUART0_SEND = 0xc1, /**< Euart0 send, plck1 pulse */ - PIS_EUART0_TXOUT = 0xc2, /**< Euart0 txout, plck1 level */ - PIS_EUART1_RECV = 0xd0, /**< Euart1 recv, plck1 pulse */ - PIS_EUART1_SEND = 0xd1, /**< Euart1 send, plck1 pulse */ - PIS_EUART1_TXOUT = 0xd2, /**< Euart1 txout, plck1 level */ - PIS_SPI0_RECV = 0xe0, /**< Spi0 recv, plck1 pulse */ - PIS_SPI0_SEND = 0xe1, /**< Spi0 send, plck1 pulse */ - PIS_SPI0_NE = 0xe2, /**< Spi0 ne, plck1 level */ - PIS_SPI1_RECV = 0xf0, /**< Spi1 recv, plck1 pulse */ - PIS_SPI1_SEND = 0xf1, /**< Spi1 send, plck1 pulse */ - PIS_SPI1_NE = 0xf2, /**< Spi1 ne, plck1 level */ - PIS_I2C0_RECV = 0x100, /**< I2c0 recv, plck1 level */ - PIS_I2C0_SEND = 0x101, /**< I2c0 send, plck1 level */ - PIS_I2C1_RECV = 0x110, /**< I2c1 recv, plck1 level */ - PIS_I2C1_SEND = 0x111, /**< I2c1 send, plck1 level */ - PIS_TIMER0_UPDATA = 0x120, /**< Timer0 updata, plck1 pulse */ - PIS_TIMER0_TRIG = 0x121, /**< Timer0 trig, plck1 pulse */ - PIS_TIMER0_INPUT = 0x122, /**< Timer0 input, plck1 pulse */ - PIS_TIMER0_OUTPUT = 0x123, /**< Timer0 output, plck1 pulse */ - PIS_TIMER1_UPDATA = 0x130, /**< Timer1 updata, plck1 pulse */ - PIS_TIMER1_TRIG = 0x131, /**< Timer1 trig, plck1 pulse */ - PIS_TIMER1_INPUT = 0x132, /**< Timer1 input, plck1 pulse */ - PIS_TIMER1_OUTPUT = 0x133, /**< Timer1 output, plck1 pulse */ - PIS_TIMER2_UPDATA = 0x140, /**< Timer2 updata, plck1 pulse */ - PIS_TIMER2_TRIG = 0x141, /**< Timer2 trig, plck1 pulse */ - PIS_TIMER2_INPUT = 0x142, /**< Timer2 input, plck1 pulse */ - PIS_TIMER2_OUTPUT = 0x143, /**< Timer2 output, plck1 pulse */ - PIS_TIMER3_UPDATA = 0x150, /**< Timer0 updata, plck1 pulse */ - PIS_TIMER3_TRIG = 0x151, /**< Timer0 trig, plck1 pulse */ - PIS_TIMER3_INPUT = 0x152, /**< Timer0 input, plck1 pulse */ - PIS_TIMER3_OUTPUT = 0x153, /**< Timer0 output, plck1 pulse */ - PIS_RTC_CLOCK = 0x160, /**< Rtc clock, pulse,support async */ - PIS_RTC_ALARM = 0x161, /**< Rtc alarm, pulse,support async */ - PIS_LPTIM0_SYN_UPDATA = 0x170, /**< Lptimer0 syn updata, pulse,support async */ - PIS_LPTIM0_ASY_UPDATA = 0x171, /**< Lptimer0 asy updata, pulse,support async */ - PIS_LPUART0_ASY_RECV = 0x180, /**< Lpuart0 asy recv, pulse,support async */ - PIS_LPUART0_ASY_SEND = 0x181, /**< Lpuart0 asy send, pulse,support async */ - PIS_LPUART0_SYN_RECV = 0x182, /**< Lpuart0 syn recv, pulse,support async */ - PIS_LPUART0_SYN_SEND = 0x183, /**< Lpuart0 syn recv, pulse,support async */ - PIS_DMA = 0x190, /**< Dma, pulse,support async */ - PIS_ADC1_INJECT = 0x1a0, /**< Adc1 inject, pclk2 pulse,support async */ - PIS_ADC1_REGULAT = 0x1a1, /**< Adc1 regulat, pclk2 pulse,support async */ - PIS_ADC1_WINDOW = 0x1a2, /**< Adc1 window, no have */ + * @verbatim + In this module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F065x series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + + 2. For ES32F033x/ES32F093x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + @endverbatim + */ +typedef enum { + PIS_NON = 0x0U, /**< No async */ + PIS_GPIO_PIN0 = 0x10U, /**< Pin0, level,support async */ + PIS_GPIO_PIN1 = 0x11U, /**< Pin1, level,support async */ + PIS_GPIO_PIN2 = 0x12U, /**< Pin2, level,support async */ + PIS_GPIO_PIN3 = 0x13U, /**< Pin3, level,support async */ + PIS_GPIO_PIN4 = 0x14U, /**< Pin4, level,support async */ + PIS_GPIO_PIN5 = 0x15U, /**< Pin5, level,support async */ + PIS_GPIO_PIN6 = 0x16U, /**< Pin6, level,support async */ + PIS_GPIO_PIN7 = 0x17U, /**< Pin7, level,support async */ + PIS_GPIO_PIN8 = 0x18U, /**< Pin8, level,support async */ + PIS_GPIO_PIN9 = 0x19U, /**< Pin9, level,support async */ + PIS_GPIO_PIN10 = 0x1aU, /**< Pin10, level,support async */ + PIS_GPIO_PIN11 = 0x1bU, /**< Pin11, level,support async */ + PIS_GPIO_PIN12 = 0x1cU, /**< Pin12, level,support async */ + PIS_GPIO_PIN13 = 0x1dU, /**< Pin13, level,support async */ + PIS_GPIO_PIN14 = 0x1eU, /**< Pin14, level,support async */ + PIS_GPIO_PIN15 = 0x1fU, /**< Pin15, level,support async */ + PIS_ACMP_OUT0 = 0x30U, /**< Acmp0 output, level,support async */ + PIS_ACMP_OUT1 = 0x31U, /**< Acmp1 output, level,support async */ + PIS_DAC0_CH0 = 0x40U, /**< Dac0 channel 0, pclk2 pulse,support async */ + PIS_DAC0_CH1 = 0x41U, /**< Dac0 channel 1, pclk2 pulse,support async */ + PIS_ADC0_INJECT = 0x60U, /**< Adc0 inject, pclk2 pulse,support async */ + PIS_ADC0_REGULAT = 0x61U, /**< Adc0 regulat, pclk2 pulse,support async */ + PIS_ADC0_WINDOW = 0x62U, /**< Adc0 window, no have */ + PIS_LVD = 0x70U, /**< Lvd, level,support async */ + PIS_UART0_ASY_SEND = 0x80U, /**< Uart0 asy send, pulse,support async */ + PIS_UART0_ASY_RECV = 0x81U, /**< Uart0 asy recv, pulse,support async */ + PIS_UART0_IRDAOUT = 0x82U, /**< Uart0 irdaout, level,support async */ + PIS_UART0_RTSOUT = 0x83U, /**< Uart0 rtsout, level,support async */ + PIS_UART0_TXOUT = 0x84U, /**< Uart0 txout, level,support async */ + PIS_UART0_SYN_SEND = 0x85U, /**< Uart0 syn send, pulse,support async */ + PIS_UART0_SYN_RECV = 0x86U, /**< Uart0 syn recv, pulse,support async */ + PIS_UART1_ASY_SEND = 0x90U, /**< Uart1 asy send, pulse,support async */ + PIS_UART1_ASY_RECV = 0x91U, /**< Uart1 asy recv, pulse,support async */ + PIS_UART1_IRDA = 0x92U, /**< Uart1 irdaout, level,support async */ + PIS_UART1_RTS = 0x93U, /**< Uart1 rtsout, level,support async */ + PIS_UART1_TXOUT = 0x94U, /**< Uart1 txout, level,support async */ + PIS_UART1_SYN_SEND = 0x95U, /**< Uart1 syn send, pulse,support async */ + PIS_UART1_SYN_RECV = 0x96U, /**< Uart1 syn recv, pulse,support async */ + PIS_UART2_ASY_SEND = 0xa0U, /**< Uart2 asy send, pulse,support async */ + PIS_UART2_ASY_RECV = 0xa1U, /**< Uart2 asy recv, pulse,support async */ + PIS_UART2_IRDA = 0xa2U, /**< Uart2 irdaout, level,support async */ + PIS_UART2_RTS = 0xa3U, /**< Uart2 rtsout, level,support async */ + PIS_UART2_TXOUT = 0xa4U, /**< Uart2 txout, level,support async */ + PIS_UART2_SYN_SEND = 0xa5U, /**< Uart2 syn send, pulse,support async */ + PIS_UART2_SYN_RECV = 0xa6U, /**< Uart2 syn recv, pulse,support async */ + PIS_UART3_ASY_SEND = 0xb1U, /**< Uart3 asy send, pulse,support async */ + PIS_UART3_ASY_RECV = 0xb2U, /**< Uart3 asy recv, pulse,support async */ + PIS_UART3_IRDA = 0xb3U, /**< Uart3 irdaout, level,support async */ + PIS_UART3_RTS = 0xb4U, /**< Uart3 rtsout, level,support async */ + PIS_UART3_TXOUT = 0xb5U, /**< Uart3 txout, level,support async */ + PIS_UART3_SYN_SEND = 0xb6U, /**< Uart3 syn send, pulse,support async */ + PIS_UART3_SYN_RECV = 0xb7U, /**< Uart3 syn recv, pulse,support async */ + PIS_EUART0_RECV = 0xc0U, /**< Euart0 recv, plck1 pulse */ + PIS_EUART0_SEND = 0xc1U, /**< Euart0 send, plck1 pulse */ + PIS_EUART0_TXOUT = 0xc2U, /**< Euart0 txout, plck1 level */ + PIS_EUART1_RECV = 0xd0U, /**< Euart1 recv, plck1 pulse */ + PIS_EUART1_SEND = 0xd1U, /**< Euart1 send, plck1 pulse */ + PIS_EUART1_TXOUT = 0xd2U, /**< Euart1 txout, plck1 level */ + PIS_SPI0_RECV = 0xe0U, /**< Spi0 recv, plck1 pulse */ + PIS_SPI0_SEND = 0xe1U, /**< Spi0 send, plck1 pulse */ + PIS_SPI0_NE = 0xe2U, /**< Spi0 ne, plck1 level */ + PIS_SPI1_RECV = 0xf0U, /**< Spi1 recv, plck1 pulse */ + PIS_SPI1_SEND = 0xf1U, /**< Spi1 send, plck1 pulse */ + PIS_SPI1_NE = 0xf2U, /**< Spi1 ne, plck1 level */ + PIS_I2C0_RECV = 0x100U, /**< I2c0 recv, plck1 level */ + PIS_I2C0_SEND = 0x101U, /**< I2c0 send, plck1 level */ + PIS_I2C1_RECV = 0x110U, /**< I2c1 recv, plck1 level */ + PIS_I2C1_SEND = 0x111U, /**< I2c1 send, plck1 level */ + PIS_TIMER0_UPDATA = 0x120U, /**< Timer0 updata, plck1 pulse */ + PIS_TIMER0_TRIG = 0x121U, /**< Timer0 trig, plck1 pulse */ + PIS_TIMER0_INPUT = 0x122U, /**< Timer0 input, plck1 pulse */ + PIS_TIMER0_OUTPUT = 0x123U, /**< Timer0 output, plck1 pulse */ + PIS_TIMER1_UPDATA = 0x130U, /**< Timer1 updata, plck1 pulse */ + PIS_TIMER1_TRIG = 0x131U, /**< Timer1 trig, plck1 pulse */ + PIS_TIMER1_INPUT = 0x132U, /**< Timer1 input, plck1 pulse */ + PIS_TIMER1_OUTPUT = 0x133U, /**< Timer1 output, plck1 pulse */ + PIS_TIMER2_UPDATA = 0x140U, /**< Timer2 updata, plck1 pulse */ + PIS_TIMER2_TRIG = 0x141U, /**< Timer2 trig, plck1 pulse */ + PIS_TIMER2_INPUT = 0x142U, /**< Timer2 input, plck1 pulse */ + PIS_TIMER2_OUTPUT = 0x143U, /**< Timer2 output, plck1 pulse */ + PIS_TIMER3_UPDATA = 0x150U, /**< Timer0 updata, plck1 pulse */ + PIS_TIMER3_TRIG = 0x151U, /**< Timer0 trig, plck1 pulse */ + PIS_TIMER3_INPUT = 0x152U, /**< Timer0 input, plck1 pulse */ + PIS_TIMER3_OUTPUT = 0x153U, /**< Timer0 output, plck1 pulse */ + PIS_RTC_CLOCK = 0x160U, /**< Rtc clock, pulse,support async */ + PIS_RTC_ALARM = 0x161U, /**< Rtc alarm, pulse,support async */ + PIS_LPTIM0_SYN_UPDATA = 0x170U, /**< Lptimer0 syn updata, pulse,support async */ + PIS_LPTIM0_ASY_UPDATA = 0x171U, /**< Lptimer0 asy updata, pulse,support async */ + PIS_LPUART0_ASY_RECV = 0x180U, /**< Lpuart0 asy recv, pulse,support async */ + PIS_LPUART0_ASY_SEND = 0x181U, /**< Lpuart0 asy send, pulse,support async */ + PIS_LPUART0_SYN_RECV = 0x182U, /**< Lpuart0 syn recv, pulse,support async */ + PIS_LPUART0_SYN_SEND = 0x183U, /**< Lpuart0 syn recv, pulse,support async */ + PIS_DMA = 0x190U, /**< Dma, pulse,support async */ + PIS_ADC1_INJECT = 0x1a0U, /**< Adc1 inject, pclk2 pulse,support async */ + PIS_ADC1_REGULAT = 0x1a1U, /**< Adc1 regulat, pclk2 pulse,support async */ + PIS_ADC1_WINDOW = 0x1a2U, /**< Adc1 window, no have */ } pis_src_t; /** * @brief Consumer entry - * @note ES32F065x: - * AD16C4T0--TIMER0 - * GP16C4T0--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - * - * ES32F033x: - * ES32F093x: - * GP16C4T0--TIMER0 - * GP16C4T1--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 */ -typedef enum -{ - PIS_CH0_TIMER0_BRKIN = 0x0400, /**< Timer0 brkin */ - PIS_CH0_SPI1_CLK = 0x0F10, /**< Spi1 clk */ - PIS_CH0_LPTIM0_EXT0 = 0x0030, /**< Lptimer0 ext0 */ - PIS_CH0_ADC1_NORMAL = 0x0030, /**< Adc1 normal */ - PIS_CH1_TIMER0_CH1IN = 0x0001, /**< Timer0 ch1in */ - PIS_CH1_TIMER2_CH1IN = 0x1001, /**< Timer2 ch1in */ - PIS_CH1_TIMER3_CH1IN = 0x1801, /**< Timer3 ch1in */ - PIS_CH1_LPTIM0_EXT1 = 0x0031, /**< Lptime0 ext1 */ - PIS_CH1_UART0_RX_IRDA = 0x0011, /**< Uart0 rx irda */ - PIS_CH1_ADC1_INSERT = 0x0031, /**< Adc1 insert */ - PIS_CH2_TIMER0_CH2IN = 0x0102, /**< Timer0 ch2in */ - PIS_CH2_TIMER2_CH2IN = 0x1102, /**< Timer2 ch2in */ - PIS_CH2_TIMER3_CH2IN = 0x1902, /**< Timer3 ch2in */ - PIS_CH2_LPTIM0_EXT2 = 0x0032, /**< Lptime0 ext2 */ - PIS_CH2_UART1_RX_IRDA = 0x0112, /**< Uart1 rx irda */ - PIS_CH3_TIMER0_CH3IN = 0x0203, /**< Timer0 ch3in */ - PIS_CH3_LPTIM0_EXT3 = 0x0033, /**< Lptime0 ext3 */ - PIS_CH3_UART2_RX_IRDA = 0x0213, /**< Uart2 rx irda */ - PIS_CH4_TIMER0_CH4IN = 0x0004, /**< Timer0 ch4in */ - PIS_CH4_TIMER0_ITR0 = 0x0034, /**< Timer0 itr0 */ - PIS_CH4_TIMER2_ITR0 = 0x0034, /**< Timer2 itr0 */ - PIS_CH4_TIMER3_ITR0 = 0x0034, /**< Timer3 itr0 */ - PIS_CH4_LPTIM0_EXT4 = 0x0434, /**< Lptime0 ext4 */ - PIS_CH4_UART3_RX_IRDA = 0x0314, /**< Uart3 rx irda */ - PIS_CH5_SPI0_RX = 0x0C15, /**< Spi0 rx */ - PIS_CH5_LPTIM0_EXT5 = 0x0035, /**< Lptime0 ext5 */ - PIS_CH5_EUART0_RX = 0x0615, /**< Euart0 rx */ - PIS_CH5_TIMER0_ITR1 = 0x0035, /**< Timer0 itr1 */ - PIS_CH5_TIMER2_ITR1 = 0x0035, /**< Timer2 itr1 */ - PIS_CH5_TIMER3_ITR1 = 0x0035, /**< Timer3 itr1 */ - PIS_CH6_SPI0_CLK = 0x0D16, /**< Spi0 clk */ - PIS_CH6_ADC0_NORMAL = 0x0036, /**< Adc0 normal */ - PIS_CH6_LPTIM0_EXT6 = 0x0036, /**< Lptime0 ext6 */ - PIS_CH6_EUART1_RX = 0x0716, /**< Euart1 rx */ - PIS_CH6_TIMER0_ITR2 = 0x0036, /**< Timer0 itr2 */ - PIS_CH6_TIMER2_ITR2 = 0x0036, /**< Timer2 itr2 */ - PIS_CH6_TIMER3_ITR2 = 0x0036, /**< Timer3 itr2 */ - PIS_CH6_DAC_CH1 = 0x0036, /**< Dac channel 1 */ - PIS_CH7_SPI1_RX = 0x0E17, /**< Spi1 rx */ - PIS_CH7_ADC0_INSERT = 0x0037, /**< Adc0 insert */ - PIS_CH7_LPTIM0_EXT7 = 0x0037, /**< Lptime0 ext7 */ - PIS_CH7_DMA = 0x0037, /**< Dma */ - PIS_CH7_TIMER0_ITR3 = 0x0037, /**< Timer0 itr3 */ - PIS_CH7_TIMER2_ITR3 = 0x0037, /**< Timer2 itr3 */ - PIS_CH7_TIMER3_ITR3 = 0x0037, /**< Timer3 itr3 */ - PIS_CH7_LPUART_RX = 0x0817, /**< Lpuart rx */ - PIS_CH7_DAC_CH0 = 0x0037, /**< Dac channel 0 */ +typedef enum { + PIS_CH0_TIMER0_BRKIN = 0x0400U, /**< Timer0 brkin */ + PIS_CH0_SPI1_CLK = 0x0F10U, /**< Spi1 clk */ + PIS_CH0_LPTIM0_EXT0 = 0x0030U, /**< Lptimer0 ext0 */ + PIS_CH0_ADC1_NORMAL = 0x0030U, /**< Adc1 normal */ + PIS_CH1_TIMER0_CH1IN = 0x0001U, /**< Timer0 ch1in */ + PIS_CH1_TIMER2_CH1IN = 0x1001U, /**< Timer2 ch1in */ + PIS_CH1_TIMER3_CH1IN = 0x1801U, /**< Timer3 ch1in */ + PIS_CH1_LPTIM0_EXT1 = 0x0031U, /**< Lptime0 ext1 */ + PIS_CH1_UART0_RX_IRDA = 0x0011U, /**< Uart0 rx irda */ + PIS_CH1_ADC1_INSERT = 0x0031U, /**< Adc1 insert */ + PIS_CH2_TIMER0_CH2IN = 0x0102U, /**< Timer0 ch2in */ + PIS_CH2_TIMER2_CH2IN = 0x1102U, /**< Timer2 ch2in */ + PIS_CH2_TIMER3_CH2IN = 0x1902U, /**< Timer3 ch2in */ + PIS_CH2_LPTIM0_EXT2 = 0x0032U, /**< Lptime0 ext2 */ + PIS_CH2_UART1_RX_IRDA = 0x0112U, /**< Uart1 rx irda */ + PIS_CH3_TIMER0_CH3IN = 0x0203U, /**< Timer0 ch3in */ + PIS_CH3_LPTIM0_EXT3 = 0x0033U, /**< Lptime0 ext3 */ + PIS_CH3_UART2_RX_IRDA = 0x0213U, /**< Uart2 rx irda */ + PIS_CH4_TIMER0_CH4IN = 0x0004U, /**< Timer0 ch4in */ + PIS_CH4_TIMER0_ITR0 = 0x0034U, /**< Timer0 itr0 */ + PIS_CH4_TIMER2_ITR0 = 0x0034U, /**< Timer2 itr0 */ + PIS_CH4_TIMER3_ITR0 = 0x0034U, /**< Timer3 itr0 */ + PIS_CH4_LPTIM0_EXT4 = 0x0434U, /**< Lptime0 ext4 */ + PIS_CH4_UART3_RX_IRDA = 0x0314U, /**< Uart3 rx irda */ + PIS_CH5_SPI0_RX = 0x0C15U, /**< Spi0 rx */ + PIS_CH5_LPTIM0_EXT5 = 0x0035U, /**< Lptime0 ext5 */ + PIS_CH5_EUART0_RX = 0x0615U, /**< Euart0 rx */ + PIS_CH5_TIMER0_ITR1 = 0x0035U, /**< Timer0 itr1 */ + PIS_CH5_TIMER2_ITR1 = 0x0035U, /**< Timer2 itr1 */ + PIS_CH5_TIMER3_ITR1 = 0x0035U, /**< Timer3 itr1 */ + PIS_CH6_SPI0_CLK = 0x0D16U, /**< Spi0 clk */ + PIS_CH6_ADC0_NORMAL = 0x0036U, /**< Adc0 normal */ + PIS_CH6_LPTIM0_EXT6 = 0x0036U, /**< Lptime0 ext6 */ + PIS_CH6_EUART1_RX = 0x0716U, /**< Euart1 rx */ + PIS_CH6_TIMER0_ITR2 = 0x0036U, /**< Timer0 itr2 */ + PIS_CH6_TIMER2_ITR2 = 0x0036U, /**< Timer2 itr2 */ + PIS_CH6_TIMER3_ITR2 = 0x0036U, /**< Timer3 itr2 */ + PIS_CH6_DAC_CH1 = 0x0036U, /**< Dac channel 1 */ + PIS_CH7_SPI1_RX = 0x0E17U, /**< Spi1 rx */ + PIS_CH7_ADC0_INSERT = 0x0037U, /**< Adc0 insert */ + PIS_CH7_LPTIM0_EXT7 = 0x0037U, /**< Lptime0 ext7 */ + PIS_CH7_DMA = 0x0037U, /**< Dma */ + PIS_CH7_TIMER0_ITR3 = 0x0037U, /**< Timer0 itr3 */ + PIS_CH7_TIMER2_ITR3 = 0x0037U, /**< Timer2 itr3 */ + PIS_CH7_TIMER3_ITR3 = 0x0037U, /**< Timer3 itr3 */ + PIS_CH7_LPUART_RX = 0x0817U, /**< Lpuart rx */ + PIS_CH7_DAC_CH0 = 0x0037U, /**< Dac channel 0 */ } pis_trig_t; /** * @brief Clock select */ -typedef enum -{ - PIS_CLK_PCLK1 = 0, /**< Pclock1 */ - PIS_CLK_PCLK2 = 1, /**< Pclock2 */ - PIS_CLK_SYS = 2, /**< Sys clock */ - PIS_CLK_LP = 3, /**< Low power clock */ +typedef enum { + PIS_CLK_PCLK1 = 0U, /**< Pclock1 */ + PIS_CLK_PCLK2 = 1U, /**< Pclock2 */ + PIS_CLK_SYS = 2U, /**< Sys clock */ + PIS_CLK_LP = 3U, /**< Low power clock */ } pis_clock_t; /** * @brief Level select */ -typedef enum -{ - PIS_EDGE_NONE = 0, /**< None edge */ - PIS_EDGE_UP = 1, /**< Up edge */ - PIS_EDGE_DOWN = 2, /**< Down edge */ - PIS_EDGE_UP_DOWN = 3, /**< Up and down edge */ +typedef enum { + PIS_EDGE_NONE = 0U, /**< None edge */ + PIS_EDGE_UP = 1U, /**< Up edge */ + PIS_EDGE_DOWN = 2U, /**< Down edge */ + PIS_EDGE_UP_DOWN = 3U, /**< Up and down edge */ } pis_edge_t; /** * @brief Output style */ -typedef enum -{ - PIS_OUT_LEVEL = 0, /**< Level */ - PIS_OUT_PULSE = 1, /**< Pulse */ +typedef enum { + PIS_OUT_LEVEL = 0U, /**< Level */ + PIS_OUT_PULSE = 1U, /**< Pulse */ } pis_output_t; /** * @brief Sync select */ -typedef enum -{ - PIS_SYN_DIRECT = 0, /**< Direct */ - PIS_SYN_ASY_PCLK1 = 1, /**< Asy pclk1 */ - PIS_SYN_ASY_PCLK2 = 2, /**< Asy pclk2 */ - PIS_SYN_ASY_PCLK = 3, /**< Asy pclk */ - PIS_SYN_PCLK2_PCLK1 = 4, /**< Pclk2 to pclk1 */ - PIS_SYN_PCLK1_PCLK2 = 5, /**< Pclk1 to pclk2 */ - PIS_SYN_PCLK12_SYS = 6, /**< Pclk1 or pclk2 to sysclk */ +typedef enum { + PIS_SYN_DIRECT = 0U, /**< Direct */ + PIS_SYN_ASY_PCLK1 = 1U, /**< Asy pclk1 */ + PIS_SYN_ASY_PCLK2 = 2U, /**< Asy pclk2 */ + PIS_SYN_ASY_PCLK = 3U, /**< Asy pclk */ + PIS_SYN_PCLK2_PCLK1 = 4U, /**< Pclk2 to pclk1 */ + PIS_SYN_PCLK1_PCLK2 = 5U, /**< Pclk1 to pclk2 */ + PIS_SYN_PCLK12_SYS = 6U, /**< Pclk1 or pclk2 to sysclk */ } pis_syncsel_t; /** * @brief Pis channel */ -typedef enum -{ - PIS_CH_0 = 0, /**< Channel 0 */ - PIS_CH_1 = 1, /**< Channel 1 */ - PIS_CH_2 = 2, /**< Channel 2 */ - PIS_CH_3 = 3, /**< Channel 3 */ - PIS_CH_4 = 4, /**< Channel 4 */ - PIS_CH_5 = 5, /**< Channel 5 */ - PIS_CH_6 = 6, /**< Channel 6 */ - PIS_CH_7 = 7, /**< Channel 7 */ +typedef enum { + PIS_CH_0 = 0U, /**< Channel 0 */ + PIS_CH_1 = 1U, /**< Channel 1 */ + PIS_CH_2 = 2U, /**< Channel 2 */ + PIS_CH_3 = 3U, /**< Channel 3 */ + PIS_CH_4 = 4U, /**< Channel 4 */ + PIS_CH_5 = 5U, /**< Channel 5 */ + PIS_CH_6 = 6U, /**< Channel 6 */ + PIS_CH_7 = 7U, /**< Channel 7 */ } pis_ch_t; /** * @brief Pis output channel */ -typedef enum -{ - PIS_OUT_CH_0 = 0, /**< Channel 0 */ - PIS_OUT_CH_1 = 1, /**< Channel 1 */ - PIS_OUT_CH_2 = 2, /**< Channel 2 */ - PIS_OUT_CH_3 = 3, /**< Channel 3 */ +typedef enum { + PIS_OUT_CH_0 = 0U, /**< Channel 0 */ + PIS_OUT_CH_1 = 1U, /**< Channel 1 */ + PIS_OUT_CH_2 = 2U, /**< Channel 2 */ + PIS_OUT_CH_3 = 3U, /**< Channel 3 */ } pis_out_ch_t; /** * @brief Indirect value,no care of it. */ -typedef enum -{ - PIS_CON_0 = 0, /**< Con 0 */ - PIS_CON_1 = 1, /**< Con 1 */ - PIS_CON_NONE = 2, /**< None */ +typedef enum { + PIS_CON_0 = 0U, /**< Con 0 */ + PIS_CON_1 = 1U, /**< Con 1 */ + PIS_CON_NONE = 2U, /**< None */ } pis_con_t; -/** - * @brief Indirect value,no care of it. - */ -typedef union -{ - struct - { - uint8_t ch : 4; /**< Channel */ - uint8_t con : 4; /**< Contorl */ - uint8_t shift : 8; /**< Shift */ - }; - uint16_t HalfWord; -} pis_divide_t; - /** * @brief PIS state structures definition */ -typedef enum -{ - PIS_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - PIS_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - PIS_STATE_BUSY = 0x02, /**< An internal process is ongoing */ - PIS_STATE_TIMEOUT = 0x03, /**< Timeout state */ - PIS_STATE_ERROR = 0x04, /**< Error */ +typedef enum { + PIS_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + PIS_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + PIS_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ + PIS_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + PIS_STATE_ERROR = 0x04U, /**< Error */ } pis_state_t; /** * @brief PIS modulate target */ -typedef enum -{ - PIS_UART0_TX = 0, /**< Modulate uart0 tx */ - PIS_UART1_TX = 1, /**< Modulate uart1 tx */ - PIS_UART2_TX = 2, /**< Modulate uart2 tx */ - PIS_UART3_TX = 3, /**< Modulate uart3 tx */ - PIS_LPUART0_TX = 4, /**< Modulate lpuart0 tx */ +typedef enum { + PIS_UART0_TX = 0U, /**< Modulate uart0 tx */ + PIS_UART1_TX = 1U, /**< Modulate uart1 tx */ + PIS_UART2_TX = 2U, /**< Modulate uart2 tx */ + PIS_UART3_TX = 3U, /**< Modulate uart3 tx */ + PIS_LPUART0_TX = 4U, /**< Modulate lpuart0 tx */ } pis_modu_targ_t; /** * @brief PIS modulate level */ -typedef enum -{ - PIS_LOW_LEVEL = 0, /**< Modulate low level */ - PIS_HIGH_LEVEL = 1, /**< Modulate high level */ +typedef enum { + PIS_LOW_LEVEL = 0U, /**< Modulate low level */ + PIS_HIGH_LEVEL = 1U, /**< Modulate high level */ } pis_modu_level_t; /** @@ -383,66 +333,61 @@ typedef enum * BS16T2----TIMER5 * BS16T3----TIMER7 */ -typedef enum -{ - PIS_SRC_NONE = 0, /**< Stop modulate */ - PIS_SRC_TIMER0 = 1, /**< Modulate source is TIMER0 */ - PIS_SRC_TIMER1 = 2, /**< Modulate source is TIMER1 */ - PIS_SRC_TIMER2 = 3, /**< Modulate source is TIMER2 */ - PIS_SRC_TIMER3 = 4, /**< Modulate source is TIMER3 */ - PIS_SRC_TIMER6 = 5, /**< Modulate source is TIMER6 */ - PIS_SRC_TIMER7 = 6, /**< Modulate source is TIMER7 */ - PIS_SRC_LPTIM0 = 7, /**< Modulate source is LPTIM0 */ - PIS_SRC_BUZ = 8, /**< Modulate source is buz */ +typedef enum { + PIS_SRC_NONE = 0U, /**< Stop modulate */ + PIS_SRC_TIMER0 = 1U, /**< Modulate source is TIMER0 */ + PIS_SRC_TIMER1 = 2U, /**< Modulate source is TIMER1 */ + PIS_SRC_TIMER2 = 3U, /**< Modulate source is TIMER2 */ + PIS_SRC_TIMER3 = 4U, /**< Modulate source is TIMER3 */ + PIS_SRC_TIMER6 = 5U, /**< Modulate source is TIMER6 */ + PIS_SRC_TIMER7 = 6U, /**< Modulate source is TIMER7 */ + PIS_SRC_LPTIM0 = 7U, /**< Modulate source is LPTIM0 */ + PIS_SRC_BUZ = 8U, /**< Modulate source is buz */ } pis_modu_src_t; /** * @brief PIS modulate channel */ -typedef enum -{ - PIS_TIMER_CH1 = 0, /**< Src is TIMERx and choose channel 1 */ - PIS_TIMER_CH2 = 1, /**< Src is TIMERx and choose channel 2 */ - PIS_TIMER_CH3 = 2, /**< Src is TIMERx and choose channel 3 */ - PIS_TIMER_CH4 = 3, /**< Src is TIMERx and choose channel 4 */ +typedef enum { + PIS_TIMER_CH1 = 0U, /**< Src is TIMERx and choose channel 1 */ + PIS_TIMER_CH2 = 1U, /**< Src is TIMERx and choose channel 2 */ + PIS_TIMER_CH3 = 2U, /**< Src is TIMERx and choose channel 3 */ + PIS_TIMER_CH4 = 3U, /**< Src is TIMERx and choose channel 4 */ } pis_modu_channel_t; /** * @brief PIS init structure definition */ -typedef struct -{ - pis_src_t producer_src; /**< Producer entry */ - pis_clock_t producer_clk; /**< Producer module clock */ - pis_edge_t producer_edge; /**< Producer module pin output edge */ - pis_trig_t consumer_trig; /**< Consumer entry */ - pis_clock_t consumer_clk; /**< Consumer clock */ +typedef struct { + pis_src_t producer_src; /**< Producer entry */ + pis_clock_t producer_clk; /**< Producer module clock */ + pis_edge_t producer_edge; /**< Producer module pin output edge */ + pis_trig_t consumer_trig; /**< Consumer entry */ + pis_clock_t consumer_clk; /**< Consumer clock */ } pis_init_t; /** * @brief PIS modulate config structure definition */ -typedef struct -{ - pis_modu_targ_t target; /**< Modulate target */ - pis_modu_level_t level; /**< Modulate level */ - pis_modu_src_t src; /**< Modulate src */ - pis_modu_channel_t channel; /**< Modulate channel */ +typedef struct { + pis_modu_targ_t target; /**< Modulate target */ + pis_modu_level_t level; /**< Modulate level */ + pis_modu_src_t src; /**< Modulate src */ + pis_modu_channel_t channel; /**< Modulate channel */ } pis_modulate_config_t; /** * @brief PIS Handle Structure definition */ -typedef struct pis_handle_s -{ - PIS_TypeDef *perh; /**< Register base address */ - pis_init_t init; /**< PIS required parameters */ - pis_ch_t consumer_ch; /**< Indirect value, no care of it */ - pis_con_t consumer_con; /**< Indirect value, no care of it */ - uint8_t consumer_pos; /**< Indirect value, no care of it */ - uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ - lock_state_t lock; /**< Locking object */ - pis_state_t state; /**< PIS operation state */ +typedef struct pis_handle_s { + PIS_TypeDef *perh; /**< Register base address */ + pis_init_t init; /**< PIS required parameters */ + pis_ch_t consumer_ch; /**< Indirect value, no care of it */ + pis_con_t consumer_con; /**< Indirect value, no care of it */ + uint8_t consumer_pos; /**< Indirect value, no care of it */ + uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ + lock_state_t lock; /**< Locking object */ + pis_state_t state; /**< PIS operation state */ } pis_handle_t; /** * @} @@ -454,183 +399,183 @@ typedef struct pis_handle_s */ #define IS_PIS(x) (((x) == PIS)) #define IS_PIS_SRC(x) (((x) == PIS_NON) || \ - ((x) == PIS_GPIO_PIN0) || \ - ((x) == PIS_GPIO_PIN1) || \ - ((x) == PIS_GPIO_PIN2) || \ - ((x) == PIS_GPIO_PIN3) || \ - ((x) == PIS_GPIO_PIN4) || \ - ((x) == PIS_GPIO_PIN5) || \ - ((x) == PIS_GPIO_PIN6) || \ - ((x) == PIS_GPIO_PIN7) || \ - ((x) == PIS_GPIO_PIN8) || \ - ((x) == PIS_GPIO_PIN9) || \ - ((x) == PIS_GPIO_PIN10) || \ - ((x) == PIS_GPIO_PIN11) || \ - ((x) == PIS_GPIO_PIN12) || \ - ((x) == PIS_GPIO_PIN13) || \ - ((x) == PIS_GPIO_PIN14) || \ - ((x) == PIS_GPIO_PIN15) || \ - ((x) == PIS_ACMP_OUT0) || \ - ((x) == PIS_ACMP_OUT1) || \ - ((x) == PIS_DAC0_CH1) || \ - ((x) == PIS_ACMP_OUT1) || \ - ((x) == PIS_ADC0_INJECT) || \ - ((x) == PIS_ADC0_REGULAT) || \ - ((x) == PIS_ADC0_WINDOW) || \ - ((x) == PIS_LVD) || \ - ((x) == PIS_UART0_ASY_SEND) || \ - ((x) == PIS_UART0_ASY_RECV) || \ - ((x) == PIS_UART0_IRDAOUT) || \ - ((x) == PIS_UART0_RTSOUT) || \ - ((x) == PIS_UART0_TXOUT) || \ - ((x) == PIS_UART0_SYN_SEND) || \ - ((x) == PIS_UART0_SYN_RECV) || \ - ((x) == PIS_UART1_ASY_SEND) || \ - ((x) == PIS_UART1_ASY_RECV) || \ - ((x) == PIS_UART1_IRDA) || \ - ((x) == PIS_UART1_RTS) || \ - ((x) == PIS_UART1_TXOUT) || \ - ((x) == PIS_UART1_SYN_SEND) || \ - ((x) == PIS_UART1_SYN_RECV) || \ - ((x) == PIS_UART2_ASY_SEND) || \ - ((x) == PIS_UART2_ASY_RECV) || \ - ((x) == PIS_UART2_IRDA) || \ - ((x) == PIS_UART2_RTS) || \ - ((x) == PIS_UART2_TXOUT) || \ - ((x) == PIS_UART2_SYN_SEND) || \ - ((x) == PIS_UART2_SYN_RECV) || \ - ((x) == PIS_UART3_ASY_SEND) || \ - ((x) == PIS_UART3_ASY_RECV) || \ - ((x) == PIS_UART3_IRDA) || \ - ((x) == PIS_UART3_RTS) || \ - ((x) == PIS_UART3_TXOUT) || \ - ((x) == PIS_UART3_SYN_SEND) || \ - ((x) == PIS_UART3_SYN_RECV) || \ - ((x) == PIS_EUART0_RECV) || \ - ((x) == PIS_EUART0_SEND) || \ - ((x) == PIS_EUART0_TXOUT) || \ - ((x) == PIS_EUART1_RECV) || \ - ((x) == PIS_EUART1_SEND) || \ - ((x) == PIS_EUART1_TXOUT) || \ - ((x) == PIS_SPI0_RECV) || \ - ((x) == PIS_SPI0_SEND) || \ - ((x) == PIS_SPI0_NE) || \ - ((x) == PIS_SPI1_RECV) || \ - ((x) == PIS_SPI1_SEND) || \ - ((x) == PIS_SPI1_NE) || \ - ((x) == PIS_I2C0_RECV) || \ - ((x) == PIS_I2C0_SEND) || \ - ((x) == PIS_I2C1_RECV) || \ - ((x) == PIS_I2C1_SEND) || \ - ((x) == PIS_TIMER0_UPDATA) || \ - ((x) == PIS_TIMER0_TRIG) || \ - ((x) == PIS_TIMER0_INPUT) || \ - ((x) == PIS_TIMER0_OUTPUT) || \ - ((x) == PIS_TIMER1_UPDATA) || \ - ((x) == PIS_TIMER1_TRIG) || \ - ((x) == PIS_TIMER1_INPUT) || \ - ((x) == PIS_TIMER1_OUTPUT) || \ - ((x) == PIS_TIMER2_UPDATA) || \ - ((x) == PIS_TIMER2_TRIG) || \ - ((x) == PIS_TIMER2_INPUT) || \ - ((x) == PIS_TIMER2_OUTPUT) || \ - ((x) == PIS_TIMER3_UPDATA) || \ - ((x) == PIS_TIMER3_TRIG) || \ - ((x) == PIS_TIMER3_INPUT) || \ - ((x) == PIS_TIMER3_OUTPUT) || \ - ((x) == PIS_RTC_CLOCK) || \ - ((x) == PIS_RTC_ALARM) || \ - ((x) == PIS_LPTIM0_SYN_UPDATA) || \ - ((x) == PIS_LPTIM0_ASY_UPDATA) || \ - ((x) == PIS_LPUART0_ASY_RECV) || \ - ((x) == PIS_LPUART0_ASY_SEND) || \ - ((x) == PIS_LPUART0_SYN_RECV) || \ - ((x) == PIS_LPUART0_SYN_SEND) || \ - ((x) == PIS_DMA) || \ - ((x) == PIS_ADC1_INJECT) || \ - ((x) == PIS_ADC1_REGULAT) || \ - ((x) == PIS_ADC1_WINDOW)) + ((x) == PIS_GPIO_PIN0) || \ + ((x) == PIS_GPIO_PIN1) || \ + ((x) == PIS_GPIO_PIN2) || \ + ((x) == PIS_GPIO_PIN3) || \ + ((x) == PIS_GPIO_PIN4) || \ + ((x) == PIS_GPIO_PIN5) || \ + ((x) == PIS_GPIO_PIN6) || \ + ((x) == PIS_GPIO_PIN7) || \ + ((x) == PIS_GPIO_PIN8) || \ + ((x) == PIS_GPIO_PIN9) || \ + ((x) == PIS_GPIO_PIN10) || \ + ((x) == PIS_GPIO_PIN11) || \ + ((x) == PIS_GPIO_PIN12) || \ + ((x) == PIS_GPIO_PIN13) || \ + ((x) == PIS_GPIO_PIN14) || \ + ((x) == PIS_GPIO_PIN15) || \ + ((x) == PIS_ACMP_OUT0) || \ + ((x) == PIS_ACMP_OUT1) || \ + ((x) == PIS_DAC0_CH1) || \ + ((x) == PIS_ACMP_OUT1) || \ + ((x) == PIS_ADC0_INJECT) || \ + ((x) == PIS_ADC0_REGULAT) || \ + ((x) == PIS_ADC0_WINDOW) || \ + ((x) == PIS_LVD) || \ + ((x) == PIS_UART0_ASY_SEND) || \ + ((x) == PIS_UART0_ASY_RECV) || \ + ((x) == PIS_UART0_IRDAOUT) || \ + ((x) == PIS_UART0_RTSOUT) || \ + ((x) == PIS_UART0_TXOUT) || \ + ((x) == PIS_UART0_SYN_SEND) || \ + ((x) == PIS_UART0_SYN_RECV) || \ + ((x) == PIS_UART1_ASY_SEND) || \ + ((x) == PIS_UART1_ASY_RECV) || \ + ((x) == PIS_UART1_IRDA) || \ + ((x) == PIS_UART1_RTS) || \ + ((x) == PIS_UART1_TXOUT) || \ + ((x) == PIS_UART1_SYN_SEND) || \ + ((x) == PIS_UART1_SYN_RECV) || \ + ((x) == PIS_UART2_ASY_SEND) || \ + ((x) == PIS_UART2_ASY_RECV) || \ + ((x) == PIS_UART2_IRDA) || \ + ((x) == PIS_UART2_RTS) || \ + ((x) == PIS_UART2_TXOUT) || \ + ((x) == PIS_UART2_SYN_SEND) || \ + ((x) == PIS_UART2_SYN_RECV) || \ + ((x) == PIS_UART3_ASY_SEND) || \ + ((x) == PIS_UART3_ASY_RECV) || \ + ((x) == PIS_UART3_IRDA) || \ + ((x) == PIS_UART3_RTS) || \ + ((x) == PIS_UART3_TXOUT) || \ + ((x) == PIS_UART3_SYN_SEND) || \ + ((x) == PIS_UART3_SYN_RECV) || \ + ((x) == PIS_EUART0_RECV) || \ + ((x) == PIS_EUART0_SEND) || \ + ((x) == PIS_EUART0_TXOUT) || \ + ((x) == PIS_EUART1_RECV) || \ + ((x) == PIS_EUART1_SEND) || \ + ((x) == PIS_EUART1_TXOUT) || \ + ((x) == PIS_SPI0_RECV) || \ + ((x) == PIS_SPI0_SEND) || \ + ((x) == PIS_SPI0_NE) || \ + ((x) == PIS_SPI1_RECV) || \ + ((x) == PIS_SPI1_SEND) || \ + ((x) == PIS_SPI1_NE) || \ + ((x) == PIS_I2C0_RECV) || \ + ((x) == PIS_I2C0_SEND) || \ + ((x) == PIS_I2C1_RECV) || \ + ((x) == PIS_I2C1_SEND) || \ + ((x) == PIS_TIMER0_UPDATA) || \ + ((x) == PIS_TIMER0_TRIG) || \ + ((x) == PIS_TIMER0_INPUT) || \ + ((x) == PIS_TIMER0_OUTPUT) || \ + ((x) == PIS_TIMER1_UPDATA) || \ + ((x) == PIS_TIMER1_TRIG) || \ + ((x) == PIS_TIMER1_INPUT) || \ + ((x) == PIS_TIMER1_OUTPUT) || \ + ((x) == PIS_TIMER2_UPDATA) || \ + ((x) == PIS_TIMER2_TRIG) || \ + ((x) == PIS_TIMER2_INPUT) || \ + ((x) == PIS_TIMER2_OUTPUT) || \ + ((x) == PIS_TIMER3_UPDATA) || \ + ((x) == PIS_TIMER3_TRIG) || \ + ((x) == PIS_TIMER3_INPUT) || \ + ((x) == PIS_TIMER3_OUTPUT) || \ + ((x) == PIS_RTC_CLOCK) || \ + ((x) == PIS_RTC_ALARM) || \ + ((x) == PIS_LPTIM0_SYN_UPDATA) || \ + ((x) == PIS_LPTIM0_ASY_UPDATA) || \ + ((x) == PIS_LPUART0_ASY_RECV) || \ + ((x) == PIS_LPUART0_ASY_SEND) || \ + ((x) == PIS_LPUART0_SYN_RECV) || \ + ((x) == PIS_LPUART0_SYN_SEND) || \ + ((x) == PIS_DMA) || \ + ((x) == PIS_ADC1_INJECT) || \ + ((x) == PIS_ADC1_REGULAT) || \ + ((x) == PIS_ADC1_WINDOW)) #define IS_PIS_TRIG(x) (((x) == PIS_CH0_TIMER0_BRKIN) || \ - ((x) == PIS_CH0_SPI1_CLK) || \ - ((x) == PIS_CH0_LPTIM0_EXT0) || \ - ((x) == PIS_CH0_ADC1_NORMAL) || \ - ((x) == PIS_CH1_TIMER0_CH1IN) || \ - ((x) == PIS_CH1_TIMER2_CH1IN) || \ - ((x) == PIS_CH1_TIMER3_CH1IN) || \ - ((x) == PIS_CH1_UART0_RX_IRDA) || \ - ((x) == PIS_CH1_LPTIM0_EXT1) || \ - ((x) == PIS_CH1_ADC1_INSERT) || \ - ((x) == PIS_CH2_TIMER0_CH2IN) || \ - ((x) == PIS_CH2_TIMER2_CH2IN) || \ - ((x) == PIS_CH2_TIMER3_CH2IN) || \ - ((x) == PIS_CH2_LPTIM0_EXT2) || \ - ((x) == PIS_CH2_UART1_RX_IRDA) || \ - ((x) == PIS_CH3_TIMER0_CH3IN) || \ - ((x) == PIS_CH3_LPTIM0_EXT3) || \ - ((x) == PIS_CH3_UART2_RX_IRDA) || \ - ((x) == PIS_CH4_TIMER0_CH4IN) || \ - ((x) == PIS_CH4_TIMER0_ITR0) || \ - ((x) == PIS_CH4_TIMER2_ITR0) || \ - ((x) == PIS_CH4_TIMER3_ITR0) || \ - ((x) == PIS_CH4_LPTIM0_EXT4) || \ - ((x) == PIS_CH4_UART3_RX_IRDA) || \ - ((x) == PIS_CH5_SPI0_RX) || \ - ((x) == PIS_CH5_LPTIM0_EXT5) || \ - ((x) == PIS_CH5_EUART0_RX) || \ - ((x) == PIS_CH5_TIMER0_ITR1) || \ - ((x) == PIS_CH5_TIMER2_ITR1) || \ - ((x) == PIS_CH5_TIMER3_ITR1) || \ - ((x) == PIS_CH6_SPI0_CLK) || \ - ((x) == PIS_CH6_ADC0_NORMAL) || \ - ((x) == PIS_CH6_LPTIM0_EXT6) || \ - ((x) == PIS_CH6_EUART1_RX) || \ - ((x) == PIS_CH6_TIMER0_ITR2) || \ - ((x) == PIS_CH6_TIMER2_ITR2) || \ - ((x) == PIS_CH6_TIMER3_ITR2) || \ - ((x) == PIS_CH6_DAC_CH1) || \ - ((x) == PIS_CH7_SPI1_RX) || \ - ((x) == PIS_CH7_ADC0_INSERT) || \ - ((x) == PIS_CH7_LPTIM0_EXT7) || \ - ((x) == PIS_CH7_DMA) || \ - ((x) == PIS_CH7_TIMER0_ITR3) || \ - ((x) == PIS_CH7_TIMER2_ITR3) || \ - ((x) == PIS_CH7_TIMER3_ITR3) || \ - ((x) == PIS_CH7_DAC_CH0) || \ - ((x) == PIS_CH7_LPUART_RX)) + ((x) == PIS_CH0_SPI1_CLK) || \ + ((x) == PIS_CH0_LPTIM0_EXT0) || \ + ((x) == PIS_CH0_ADC1_NORMAL) || \ + ((x) == PIS_CH1_TIMER0_CH1IN) || \ + ((x) == PIS_CH1_TIMER2_CH1IN) || \ + ((x) == PIS_CH1_TIMER3_CH1IN) || \ + ((x) == PIS_CH1_UART0_RX_IRDA) || \ + ((x) == PIS_CH1_LPTIM0_EXT1) || \ + ((x) == PIS_CH1_ADC1_INSERT) || \ + ((x) == PIS_CH2_TIMER0_CH2IN) || \ + ((x) == PIS_CH2_TIMER2_CH2IN) || \ + ((x) == PIS_CH2_TIMER3_CH2IN) || \ + ((x) == PIS_CH2_LPTIM0_EXT2) || \ + ((x) == PIS_CH2_UART1_RX_IRDA) || \ + ((x) == PIS_CH3_TIMER0_CH3IN) || \ + ((x) == PIS_CH3_LPTIM0_EXT3) || \ + ((x) == PIS_CH3_UART2_RX_IRDA) || \ + ((x) == PIS_CH4_TIMER0_CH4IN) || \ + ((x) == PIS_CH4_TIMER0_ITR0) || \ + ((x) == PIS_CH4_TIMER2_ITR0) || \ + ((x) == PIS_CH4_TIMER3_ITR0) || \ + ((x) == PIS_CH4_LPTIM0_EXT4) || \ + ((x) == PIS_CH4_UART3_RX_IRDA) || \ + ((x) == PIS_CH5_SPI0_RX) || \ + ((x) == PIS_CH5_LPTIM0_EXT5) || \ + ((x) == PIS_CH5_EUART0_RX) || \ + ((x) == PIS_CH5_TIMER0_ITR1) || \ + ((x) == PIS_CH5_TIMER2_ITR1) || \ + ((x) == PIS_CH5_TIMER3_ITR1) || \ + ((x) == PIS_CH6_SPI0_CLK) || \ + ((x) == PIS_CH6_ADC0_NORMAL) || \ + ((x) == PIS_CH6_LPTIM0_EXT6) || \ + ((x) == PIS_CH6_EUART1_RX) || \ + ((x) == PIS_CH6_TIMER0_ITR2) || \ + ((x) == PIS_CH6_TIMER2_ITR2) || \ + ((x) == PIS_CH6_TIMER3_ITR2) || \ + ((x) == PIS_CH6_DAC_CH1) || \ + ((x) == PIS_CH7_SPI1_RX) || \ + ((x) == PIS_CH7_ADC0_INSERT) || \ + ((x) == PIS_CH7_LPTIM0_EXT7) || \ + ((x) == PIS_CH7_DMA) || \ + ((x) == PIS_CH7_TIMER0_ITR3) || \ + ((x) == PIS_CH7_TIMER2_ITR3) || \ + ((x) == PIS_CH7_TIMER3_ITR3) || \ + ((x) == PIS_CH7_DAC_CH0) || \ + ((x) == PIS_CH7_LPUART_RX)) #define IS_PIS_CLOCK(x) (((x) == PIS_CLK_PCLK1) || \ - ((x) == PIS_CLK_PCLK2) || \ - ((x) == PIS_CLK_SYS) || \ - ((x) == PIS_CLK_LP)) + ((x) == PIS_CLK_PCLK2) || \ + ((x) == PIS_CLK_SYS) || \ + ((x) == PIS_CLK_LP)) #define IS_PIS_EDGE(x) (((x) == PIS_EDGE_NONE) || \ - ((x) == PIS_EDGE_UP) || \ - ((x) == PIS_EDGE_DOWN) || \ - ((x) == PIS_EDGE_UP_DOWN)) + ((x) == PIS_EDGE_UP) || \ + ((x) == PIS_EDGE_DOWN) || \ + ((x) == PIS_EDGE_UP_DOWN)) #define IS_PIS_OUTPUT(x) (((x) == PIS_OUT_LEVEL) || \ - ((x) == PIS_OUT_PULSE)) + ((x) == PIS_OUT_PULSE)) #define IS_PIS_OUPUT_CH(x) (((x) == PIS_OUT_CH_0) || \ - ((x) == PIS_OUT_CH_1) || \ - ((x) == PIS_OUT_CH_2) || \ - ((x) == PIS_OUT_CH_3)) + ((x) == PIS_OUT_CH_1) || \ + ((x) == PIS_OUT_CH_2) || \ + ((x) == PIS_OUT_CH_3)) #define IS_PIS_MODU_TARGET(x) (((x) == PIS_UART0_TX) || \ - ((x) == PIS_UART1_TX) || \ - ((x) == PIS_UART2_TX) || \ - ((x) == PIS_UART3_TX) || \ - ((x) == PIS_LPUART0_TX)) + ((x) == PIS_UART1_TX) || \ + ((x) == PIS_UART2_TX) || \ + ((x) == PIS_UART3_TX) || \ + ((x) == PIS_LPUART0_TX)) #define IS_PIS_MODU_LEVEL(x) (((x) == PIS_LOW_LEVEL) || \ - ((x) == PIS_HIGH_LEVEL)) + ((x) == PIS_HIGH_LEVEL)) #define IS_PIS_MODU_SRC(x) (((x) == PIS_SRC_NONE) || \ - ((x) == PIS_SRC_TIMER0) || \ - ((x) == PIS_SRC_TIMER1) || \ - ((x) == PIS_SRC_TIMER2) || \ - ((x) == PIS_SRC_TIMER3) || \ - ((x) == PIS_SRC_TIMER6) || \ - ((x) == PIS_SRC_TIMER7) || \ - ((x) == PIS_SRC_LPTIM0) || \ - ((x) == PIS_SRC_BUZ)) + ((x) == PIS_SRC_TIMER0) || \ + ((x) == PIS_SRC_TIMER1) || \ + ((x) == PIS_SRC_TIMER2) || \ + ((x) == PIS_SRC_TIMER3) || \ + ((x) == PIS_SRC_TIMER6) || \ + ((x) == PIS_SRC_TIMER7) || \ + ((x) == PIS_SRC_LPTIM0) || \ + ((x) == PIS_SRC_BUZ)) #define IS_PIS_MODU_CHANNEL(x) (((x) == PIS_TIMER_CH1) || \ - ((x) == PIS_TIMER_CH2) || \ - ((x) == PIS_TIMER_CH3) || \ - ((x) == PIS_TIMER_CH4)) + ((x) == PIS_TIMER_CH2) || \ + ((x) == PIS_TIMER_CH3) || \ + ((x) == PIS_TIMER_CH4)) /** * @} */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pmu.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pmu.h index c0f3a9392838531d98615f3a64468fcad5eb4edc..13f59774596f1e6284afa96a064d665820d70008 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pmu.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pmu.h @@ -23,6 +23,7 @@ extern "C" { #include "utils.h" #include "ald_syscfg.h" +#include "ald_bkpc.h" /** @addtogroup ES32FXXX_ALD @@ -37,66 +38,66 @@ extern "C" { * @{ */ #define PMU_SRAM0_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \ + SYSCFG_LOCK(); \ +} while (0) #define PMU_SRAM0_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\ + SYSCFG_LOCK(); \ +} while (0) #define PMU_SRAM1_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \ + SYSCFG_LOCK(); \ +} while (0) #define PMU_SRAM1_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\ + SYSCFG_LOCK(); \ +} while (0) #define PMU_BXCAN_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define PMU_BXCAN_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define PMU_LPSTOP_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define PMU_LPSTOP_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define PMU_MTSTOP_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define PMU_MTSTOP_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS)) /** @@ -110,57 +111,54 @@ extern "C" { /** * @brief Low power mode */ -typedef enum -{ - PMU_LP_STOP1 = 0x0, /**< Stop1 */ - PMU_LP_STOP2 = 0x1, /**< Stop2 */ +typedef enum { + PMU_LP_STOP1 = 0x0U, /**< Stop1 */ + PMU_LP_STOP2 = 0x1U, /**< Stop2 */ + PMU_LP_STANDBY = 0x2U, /**< Standby */ } pmu_lp_mode_t; -typedef enum -{ - PMU_SR_WUF = (1U << 0), +typedef enum { + PMU_SR_WUF = (1U << 0), + PMU_SR_STANDBY = (1U << 1), } pmu_status_t; /** * @brief LVD voltage select */ -typedef enum -{ - PMU_LVD_VOL_SEL_2_0 = 0x0, /**< 2.0V ~ 2.05V */ - PMU_LVD_VOL_SEL_2_1 = 0x1, /**< 2.1V ~ 2.15V */ - PMU_LVD_VOL_SEL_2_2 = 0x2, /**< 2.2V ~ 2.25V */ - PMU_LVD_VOL_SEL_2_4 = 0x3, /**< 2.4V ~ 2.45V */ - PMU_LVD_VOL_SEL_2_6 = 0x4, /**< 2.6V ~ 2.65V */ - PMU_LVD_VOL_SEL_2_8 = 0x5, /**< 2.8V ~ 2.85V */ - PMU_LVD_VOL_SEL_3_0 = 0x6, /**< 3.0V ~ 3.05V */ - PMU_LVD_VOL_SEL_3_6 = 0x7, /**< 3.6V ~ 3.65V */ - PMU_LVD_VOL_SEL_4_0 = 0x8, /**< 4.0V ~ 4.05V */ - PMU_LVD_VOL_SEL_4_6 = 0x9, /**< 4.6V ~ 4.65V */ - PMU_LVD_VOL_SEL_2_3 = 0xA, /**< 2.3V ~ 2.35V */ - PMU_LVD_VOL_SEL_EXT = 0xF, /**< Select external input. It must be 1.2V */ +typedef enum { + PMU_LVD_VOL_SEL_2_0 = 0x0U, /**< 2.0V ~ 2.05V */ + PMU_LVD_VOL_SEL_2_1 = 0x1U, /**< 2.1V ~ 2.15V */ + PMU_LVD_VOL_SEL_2_2 = 0x2U, /**< 2.2V ~ 2.25V */ + PMU_LVD_VOL_SEL_2_4 = 0x3U, /**< 2.4V ~ 2.45V */ + PMU_LVD_VOL_SEL_2_6 = 0x4U, /**< 2.6V ~ 2.65V */ + PMU_LVD_VOL_SEL_2_8 = 0x5U, /**< 2.8V ~ 2.85V */ + PMU_LVD_VOL_SEL_3_0 = 0x6U, /**< 3.0V ~ 3.05V */ + PMU_LVD_VOL_SEL_3_6 = 0x7U, /**< 3.6V ~ 3.65V */ + PMU_LVD_VOL_SEL_4_0 = 0x8U, /**< 4.0V ~ 4.05V */ + PMU_LVD_VOL_SEL_4_6 = 0x9U, /**< 4.6V ~ 4.65V */ + PMU_LVD_VOL_SEL_2_3 = 0xAU, /**< 2.3V ~ 2.35V */ + PMU_LVD_VOL_SEL_EXT = 0xFU, /**< Select external input. It must be 1.2V */ } pmu_lvd_voltage_sel_t; /** * @brief LVD trigger mode */ -typedef enum -{ - PMU_LVD_TRIGGER_RISING_EDGE = 0x0, /**< Rising edge */ - PMU_LVD_TRIGGER_FALLING_EDGE = 0x1, /**< Falling edge */ - PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2, /**< High level */ - PMU_LVD_TRIGGER_LOW_LEVEL = 0x3, /**< Low level */ - PMU_LVD_TRIGGER_RISING_FALLING = 0x4, /**< Rising and falling edge */ +typedef enum { + PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, /**< Rising edge */ + PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, /**< Falling edge */ + PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, /**< High level */ + PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U, /**< Low level */ + PMU_LVD_TRIGGER_RISING_FALLING = 0x4U, /**< Rising and falling edge */ } pmu_lvd_trigger_mode_t; /** * @brief LDO output voltage selest in low power mode */ -typedef enum -{ - PMU_LDO_LPMODE_OUTPUT_1_5 = 0x0, /**< 1.5V */ - PMU_LDO_LPMODE_OUTPUT_1_4 = 0x1, /**< 1.4V */ - PMU_LDO_LPMODE_OUTPUT_1_3 = 0x2, /**< 1.3V */ - PMU_LDO_LPMODE_OUTPUT_1_2 = 0x4, /**< 1.2V */ +typedef enum { + PMU_LDO_LPMODE_OUTPUT_1_5 = 0x0U, /**< 1.5V */ + PMU_LDO_LPMODE_OUTPUT_1_4 = 0x1U, /**< 1.4V */ + PMU_LDO_LPMODE_OUTPUT_1_3 = 0x2U, /**< 1.3V */ + PMU_LDO_LPMODE_OUTPUT_1_2 = 0x4U, /**< 1.2V */ } pmu_ldo_lpmode_output_t; /** * @} @@ -171,29 +169,30 @@ typedef enum * @{ */ #define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \ - ((x) == PMU_LP_STOP2)) -#define IS_PMU_STATUS(x) ((x) == PMU_SR_WUF) + ((x) == PMU_LP_STOP2) || \ + ((x) == PMU_LP_STANDBY)) +#define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || ((x) == PMU_SR_STANDBY)) #define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_0) || \ - ((x) == PMU_LVD_VOL_SEL_2_1) || \ - ((x) == PMU_LVD_VOL_SEL_2_2) || \ - ((x) == PMU_LVD_VOL_SEL_2_4) || \ - ((x) == PMU_LVD_VOL_SEL_2_6) || \ - ((x) == PMU_LVD_VOL_SEL_2_8) || \ - ((x) == PMU_LVD_VOL_SEL_3_0) || \ - ((x) == PMU_LVD_VOL_SEL_3_6) || \ - ((x) == PMU_LVD_VOL_SEL_4_0) || \ - ((x) == PMU_LVD_VOL_SEL_4_6) || \ - ((x) == PMU_LVD_VOL_SEL_2_3) || \ - ((x) == PMU_LVD_VOL_SEL_EXT)) + ((x) == PMU_LVD_VOL_SEL_2_1) || \ + ((x) == PMU_LVD_VOL_SEL_2_2) || \ + ((x) == PMU_LVD_VOL_SEL_2_4) || \ + ((x) == PMU_LVD_VOL_SEL_2_6) || \ + ((x) == PMU_LVD_VOL_SEL_2_8) || \ + ((x) == PMU_LVD_VOL_SEL_3_0) || \ + ((x) == PMU_LVD_VOL_SEL_3_6) || \ + ((x) == PMU_LVD_VOL_SEL_4_0) || \ + ((x) == PMU_LVD_VOL_SEL_4_6) || \ + ((x) == PMU_LVD_VOL_SEL_2_3) || \ + ((x) == PMU_LVD_VOL_SEL_EXT)) #define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \ - ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \ - ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \ - ((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \ - ((x) == PMU_LVD_TRIGGER_RISING_FALLING)) + ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \ + ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \ + ((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \ + ((x) == PMU_LVD_TRIGGER_RISING_FALLING)) #define IS_PMU_LDO_LPMODE_OUTPUT(x) (((x) == PMU_LDO_LPMODE_OUTPUT_1_5) || \ - ((x) == PMU_LDO_LPMODE_OUTPUT_1_4) || \ - ((x) == PMU_LDO_LPMODE_OUTPUT_1_3) || \ - ((x) == PMU_LDO_LPMODE_OUTPUT_1_2)) + ((x) == PMU_LDO_LPMODE_OUTPUT_1_4) || \ + ((x) == PMU_LDO_LPMODE_OUTPUT_1_3) || \ + ((x) == PMU_LDO_LPMODE_OUTPUT_1_2)) /** * @} */ @@ -207,17 +206,18 @@ typedef enum /* Low power mode select */ __STATIC_INLINE__ void ald_pmu_sleep() { - __WFI(); + __WFI(); } __STATIC_INLINE__ void ald_pmu_sleep_deep() { - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); } void ald_pmu_stop1_enter(void); void ald_pmu_stop2_enter(void); +void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level); void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state); flag_status_t ald_pmu_get_status(pmu_status_t sr); void ald_pmu_clear_status(pmu_status_t sr); diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rmu.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rmu.h index b6a7060e4e0ee60c584355ce62d266ab40cce573..164ebb5e3fe5513ec4dc3c421b13ec85a6cce93b 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rmu.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rmu.h @@ -37,127 +37,128 @@ extern "C" { /** * @brief RMU BOR fliter */ -typedef enum -{ - RMU_BORFLT_1 = 0x1, /**< 1 cycle */ - RMU_BORFLT_2 = 0x2, /**< 2 cycles */ - RMU_BORFLT_3 = 0x3, /**< 3 cycles */ - RMU_BORFLT_4 = 0x4, /**< 4 cycles */ - RMU_BORFLT_5 = 0x5, /**< 5 cycles */ - RMU_BORFLT_6 = 0x6, /**< 6 cycles */ - RMU_BORFLT_7 = 0x7, /**< 7 cycles */ +typedef enum { + RMU_BORFLT_1 = 0x1U, /**< 1 cycle */ + RMU_BORFLT_2 = 0x2U, /**< 2 cycles */ + RMU_BORFLT_3 = 0x3U, /**< 3 cycles */ + RMU_BORFLT_4 = 0x4U, /**< 4 cycles */ + RMU_BORFLT_5 = 0x5U, /**< 5 cycles */ + RMU_BORFLT_6 = 0x6U, /**< 6 cycles */ + RMU_BORFLT_7 = 0x7U, /**< 7 cycles */ } rmu_bor_filter_t; /** * @brief RMU BOR voltage */ -typedef enum -{ - RMU_VOL_1_7 = 0x0, /**< 1.7V */ - RMU_VOL_2_0 = 0x1, /**< 2.0V */ - RMU_VOL_2_1 = 0x2, /**< 2.1V */ - RMU_VOL_2_2 = 0x3, /**< 2.2V */ - RMU_VOL_2_3 = 0x4, /**< 2.3V */ - RMU_VOL_2_4 = 0x5, /**< 2.4V */ - RMU_VOL_2_5 = 0x6, /**< 2.5V */ - RMU_VOL_2_6 = 0x7, /**< 2.6V */ - RMU_VOL_2_8 = 0x8, /**< 2.8V */ - RMU_VOL_3_0 = 0x9, /**< 3.0V */ - RMU_VOL_3_1 = 0xA, /**< 3.1V */ - RMU_VOL_3_3 = 0xB, /**< 3.3V */ - RMU_VOL_3_6 = 0xC, /**< 3.6V */ - RMU_VOL_3_7 = 0xD, /**< 3.7V */ - RMU_VOL_4_0 = 0xE, /**< 4.0V */ - RMU_VOL_4_3 = 0xF, /**< 4.3V */ +typedef enum { + RMU_VOL_1_8 = 0x0U, /**< 1.8V */ + RMU_VOL_2_0 = 0x1U, /**< 2.0V */ + RMU_VOL_2_2 = 0x2U, /**< 2.2V */ + RMU_VOL_2_4 = 0x3U, /**< 2.4V */ + RMU_VOL_2_6 = 0x4U, /**< 2.6V */ + RMU_VOL_2_8 = 0x5U, /**< 2.8V */ + RMU_VOL_3_0 = 0x6U, /**< 3.0V */ + RMU_VOL_3_2 = 0x7U, /**< 3.2V */ + RMU_VOL_3_4 = 0x8U, /**< 3.4V */ + RMU_VOL_3_6 = 0x9U, /**< 3.6V */ + RMU_VOL_3_8 = 0xAU, /**< 3.8V */ + RMU_VOL_4_0 = 0xBU, /**< 4.0V */ + RMU_VOL_4_2 = 0xCU, /**< 4.2V */ + RMU_VOL_4_4 = 0xDU, /**< 4.4V */ + RMU_VOL_4_6 = 0xEU, /**< 4.6V */ + RMU_VOL_4_8 = 0xFU, /**< 4.8V */ } rmu_bor_vol_t; /** * @brief RMU reset status */ -typedef enum -{ - RMU_RST_POR = (1U << 0), /**< POR */ - RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ - RMU_RST_BOR = (1U << 2), /**< BOR */ - RMU_RST_NMRST = (1U << 3), /**< NMRST */ - RMU_RST_IWDT = (1U << 4), /**< IWDT */ - RMU_RST_WWDT = (1U << 5), /**< WWDT */ - RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ - RMU_RST_CHIP = (1U << 7), /**< CHIP */ - RMU_RST_MCU = (1U << 8), /**< MCU */ - RMU_RST_CPU = (1U << 9), /**< CPU */ - RMU_RST_CFG = (1U << 10), /**< CFG */ - RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ +typedef enum { + RMU_RST_POR = (1U << 0), /**< POR */ + RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ + RMU_RST_BOR = (1U << 2), /**< BOR */ + RMU_RST_NMRST = (1U << 3), /**< NMRST */ + RMU_RST_IWDT = (1U << 4), /**< IWDT */ + RMU_RST_WWDT = (1U << 5), /**< WWDT */ + RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ + RMU_RST_CHIP = (1U << 7), /**< CHIP */ + RMU_RST_MCU = (1U << 8), /**< MCU */ + RMU_RST_CPU = (1U << 9), /**< CPU */ + RMU_RST_CFG = (1U << 10), /**< CFG */ + RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ + RMU_RST_ALL = (0xFFFFFU), /**< ALL */ } rmu_state_t; /** * @brief RMU periperal select bit - * @note ES32F065x: - * AD16C4T0--TIMER0 - * GP16C4T0--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - * - * ES32F033x: - * ES32F093x: - * GP16C4T0--TIMER0 - * GP16C4T1--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 + * @verbatim + In this module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F065x series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + TIMER4 ----> BS16T1 + TIMER5 ----> BS16T2 + TIMER6 ----> GP16C4T0 + TIMER7 ----> BS16T3 + + 2. For ES32F033x/ES32F093x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + TIMER4 ----> BS16T1 + TIMER5 ----> BS16T2 + TIMER6 ----> GP16C4T1 + TIMER7 ----> BS16T3 + @endverbatim */ -typedef enum -{ - RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ - RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ - RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */ - RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */ - RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */ - RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ - RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ - RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ - RMU_PERH_TIMER0 = (1U << 0) | (1U << 28), /**< APB1: TIMER0 */ - RMU_PERH_TIMER1 = (1U << 1) | (1U << 28), /**< APB1: TIMER1 */ - RMU_PERH_TIMER2 = (1U << 2) | (1U << 28), /**< APB1: TIMER2 */ - RMU_PERH_TIMER3 = (1U << 3) | (1U << 28), /**< APB1: TIMER3 */ - RMU_PERH_TIMER4 = (1U << 4) | (1U << 28), /**< APB1: TIMER4 */ - RMU_PERH_TIMER5 = (1U << 5) | (1U << 28), /**< APB1: TIMER5 */ - RMU_PERH_TIMER6 = (1U << 6) | (1U << 28), /**< APB1: TIMER6 */ - RMU_PERH_TIMER7 = (1U << 7) | (1U << 28), /**< APB1: TIMER7 */ - RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */ - RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */ - RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */ - RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */ - RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */ - RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */ - RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */ - RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */ - RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */ - RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */ - RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */ - RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */ - RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */ - RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */ - RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */ - RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */ - RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */ - RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */ - RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */ - RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */ - RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */ - RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */ - RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */ - RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */ - RMU_PERH_TSENSE = (1U << 16) | (1U << 29), /**< APB2: TSENSE */ - RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */ - RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */ +typedef enum { + RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ + RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ + RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */ + RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */ + RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */ + RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ + RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ + RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ + RMU_PERH_TIMER0 = (1U << 0) | (1U << 28), /**< APB1: TIMER0 */ + RMU_PERH_TIMER1 = (1U << 1) | (1U << 28), /**< APB1: TIMER1 */ + RMU_PERH_TIMER2 = (1U << 2) | (1U << 28), /**< APB1: TIMER2 */ + RMU_PERH_TIMER3 = (1U << 3) | (1U << 28), /**< APB1: TIMER3 */ + RMU_PERH_TIMER4 = (1U << 4) | (1U << 28), /**< APB1: TIMER4 */ + RMU_PERH_TIMER5 = (1U << 5) | (1U << 28), /**< APB1: TIMER5 */ + RMU_PERH_TIMER6 = (1U << 6) | (1U << 28), /**< APB1: TIMER6 */ + RMU_PERH_TIMER7 = (1U << 7) | (1U << 28), /**< APB1: TIMER7 */ + RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */ + RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */ + RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */ + RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */ + RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */ + RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */ + RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */ + RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */ + RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */ + RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */ + RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */ + RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */ + RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */ + RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */ + RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */ + RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */ + RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */ + RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */ + RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */ + RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */ + RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */ + RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */ + RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */ + RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */ + RMU_PERH_TSENSE = (1U << 16) | (1U << 29), /**< APB2: TSENSE */ + RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */ + RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */ } rmu_peripheral_t; /** * @} @@ -168,40 +169,41 @@ typedef enum * @{ */ #define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \ - ((x) == RMU_BORFLT_2) || \ - ((x) == RMU_BORFLT_3) || \ - ((x) == RMU_BORFLT_4) || \ - ((x) == RMU_BORFLT_5) || \ - ((x) == RMU_BORFLT_6) || \ - ((x) == RMU_BORFLT_7)) -#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_7) || \ - ((x) == RMU_VOL_2_0) || \ - ((x) == RMU_VOL_2_1) || \ - ((x) == RMU_VOL_2_2) || \ - ((x) == RMU_VOL_2_3) || \ - ((x) == RMU_VOL_2_4) || \ - ((x) == RMU_VOL_2_5) || \ - ((x) == RMU_VOL_2_6) || \ - ((x) == RMU_VOL_2_8) || \ - ((x) == RMU_VOL_3_0) || \ - ((x) == RMU_VOL_3_1) || \ - ((x) == RMU_VOL_3_3) || \ - ((x) == RMU_VOL_3_6) || \ - ((x) == RMU_VOL_3_7) || \ - ((x) == RMU_VOL_4_0) || \ - ((x) == RMU_VOL_4_3)) + ((x) == RMU_BORFLT_2) || \ + ((x) == RMU_BORFLT_3) || \ + ((x) == RMU_BORFLT_4) || \ + ((x) == RMU_BORFLT_5) || \ + ((x) == RMU_BORFLT_6) || \ + ((x) == RMU_BORFLT_7)) +#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_8) || \ + ((x) == RMU_VOL_2_0) || \ + ((x) == RMU_VOL_2_2) || \ + ((x) == RMU_VOL_2_4) || \ + ((x) == RMU_VOL_2_6) || \ + ((x) == RMU_VOL_2_8) || \ + ((x) == RMU_VOL_3_0) || \ + ((x) == RMU_VOL_3_2) || \ + ((x) == RMU_VOL_3_4) || \ + ((x) == RMU_VOL_3_6) || \ + ((x) == RMU_VOL_3_8) || \ + ((x) == RMU_VOL_4_0) || \ + ((x) == RMU_VOL_4_2) || \ + ((x) == RMU_VOL_4_4) || \ + ((x) == RMU_VOL_4_6) || \ + ((x) == RMU_VOL_4_8)) #define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \ - ((x) == RMU_RST_WAKEUP) || \ - ((x) == RMU_RST_BOR) || \ - ((x) == RMU_RST_NMRST) || \ - ((x) == RMU_RST_IWDT) || \ - ((x) == RMU_RST_WWDT) || \ - ((x) == RMU_RST_LOCKUP) || \ - ((x) == RMU_RST_CHIP) || \ - ((x) == RMU_RST_MCU) || \ - ((x) == RMU_RST_CPU) || \ - ((x) == RMU_RST_CFG) || \ - ((x) == RMU_RST_CFGERR)) + ((x) == RMU_RST_WAKEUP) || \ + ((x) == RMU_RST_BOR) || \ + ((x) == RMU_RST_NMRST) || \ + ((x) == RMU_RST_IWDT) || \ + ((x) == RMU_RST_WWDT) || \ + ((x) == RMU_RST_LOCKUP) || \ + ((x) == RMU_RST_CHIP) || \ + ((x) == RMU_RST_MCU) || \ + ((x) == RMU_RST_CPU) || \ + ((x) == RMU_RST_CFG) || \ + ((x) == RMU_RST_CFGERR) || \ + ((x) == RMU_RST_ALL)) #define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \ ((x) == RMU_RST_WAKEUP) || \ ((x) == RMU_RST_BOR) || \ @@ -212,50 +214,51 @@ typedef enum ((x) == RMU_RST_CHIP) || \ ((x) == RMU_RST_MCU) || \ ((x) == RMU_RST_CPU) || \ - ((x) == RMU_RST_CFG)) + ((x) == RMU_RST_CFG) || \ + ((x) == RMU_RST_ALL)) #define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \ - ((x) == RMU_PERH_CRC) || \ - ((x) == RMU_PERH_CALC) || \ - ((x) == RMU_PERH_CRYPT) || \ - ((x) == RMU_PERH_TRNG) || \ - ((x) == RMU_PERH_PIS) || \ - ((x) == RMU_PERH_CHIP) || \ - ((x) == RMU_PERH_CPU) || \ - ((x) == RMU_PERH_TIMER0) || \ - ((x) == RMU_PERH_TIMER1) || \ - ((x) == RMU_PERH_TIMER2) || \ - ((x) == RMU_PERH_TIMER3) || \ - ((x) == RMU_PERH_TIMER4) || \ - ((x) == RMU_PERH_TIMER5) || \ - ((x) == RMU_PERH_TIMER6) || \ - ((x) == RMU_PERH_TIMER7) || \ - ((x) == RMU_PERH_UART0) || \ - ((x) == RMU_PERH_UART1) || \ - ((x) == RMU_PERH_UART2) || \ - ((x) == RMU_PERH_UART3) || \ - ((x) == RMU_PERH_USART0) || \ - ((x) == RMU_PERH_USART1) || \ - ((x) == RMU_PERH_SPI0) || \ - ((x) == RMU_PERH_SPI1) || \ - ((x) == RMU_PERH_SPI2) || \ - ((x) == RMU_PERH_I2C0) || \ - ((x) == RMU_PERH_I2C1) || \ - ((x) == RMU_PERH_CAN0) || \ - ((x) == RMU_PERH_LPTIM0) || \ - ((x) == RMU_PERH_LPUART0) || \ - ((x) == RMU_PERH_ADC0) || \ - ((x) == RMU_PERH_ADC1) || \ - ((x) == RMU_PERH_ACMP0) || \ - ((x) == RMU_PERH_ACMP1) || \ - ((x) == RMU_PERH_OPAMP) || \ - ((x) == RMU_PERH_DAC0) || \ - ((x) == RMU_PERH_WWDT) || \ - ((x) == RMU_PERH_LCD) || \ - ((x) == RMU_PERH_IWDT) || \ - ((x) == RMU_PERH_RTC) || \ - ((x) == RMU_PERH_TSENSE) || \ - ((x) == RMU_PERH_BKPC) || \ - ((x) == RMU_PERH_BKPRAM)) + ((x) == RMU_PERH_CRC) || \ + ((x) == RMU_PERH_CALC) || \ + ((x) == RMU_PERH_CRYPT) || \ + ((x) == RMU_PERH_TRNG) || \ + ((x) == RMU_PERH_PIS) || \ + ((x) == RMU_PERH_CHIP) || \ + ((x) == RMU_PERH_CPU) || \ + ((x) == RMU_PERH_TIMER0) || \ + ((x) == RMU_PERH_TIMER1) || \ + ((x) == RMU_PERH_TIMER2) || \ + ((x) == RMU_PERH_TIMER3) || \ + ((x) == RMU_PERH_TIMER4) || \ + ((x) == RMU_PERH_TIMER5) || \ + ((x) == RMU_PERH_TIMER6) || \ + ((x) == RMU_PERH_TIMER7) || \ + ((x) == RMU_PERH_UART0) || \ + ((x) == RMU_PERH_UART1) || \ + ((x) == RMU_PERH_UART2) || \ + ((x) == RMU_PERH_UART3) || \ + ((x) == RMU_PERH_USART0) || \ + ((x) == RMU_PERH_USART1) || \ + ((x) == RMU_PERH_SPI0) || \ + ((x) == RMU_PERH_SPI1) || \ + ((x) == RMU_PERH_SPI2) || \ + ((x) == RMU_PERH_I2C0) || \ + ((x) == RMU_PERH_I2C1) || \ + ((x) == RMU_PERH_CAN0) || \ + ((x) == RMU_PERH_LPTIM0) || \ + ((x) == RMU_PERH_LPUART0) || \ + ((x) == RMU_PERH_ADC0) || \ + ((x) == RMU_PERH_ADC1) || \ + ((x) == RMU_PERH_ACMP0) || \ + ((x) == RMU_PERH_ACMP1) || \ + ((x) == RMU_PERH_OPAMP) || \ + ((x) == RMU_PERH_DAC0) || \ + ((x) == RMU_PERH_WWDT) || \ + ((x) == RMU_PERH_LCD) || \ + ((x) == RMU_PERH_IWDT) || \ + ((x) == RMU_PERH_RTC) || \ + ((x) == RMU_PERH_TSENSE) || \ + ((x) == RMU_PERH_BKPC) || \ + ((x) == RMU_PERH_BKPRAM)) /** * @} */ @@ -264,7 +267,7 @@ typedef enum * @{ */ void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state); -flag_status_t ald_rmu_get_reset_status(rmu_state_t state); +uint32_t ald_rmu_get_reset_status(rmu_state_t state); void ald_rmu_clear_reset_status(rmu_state_t state); void ald_rmu_reset_periperal(rmu_peripheral_t perh); /** diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rtc.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rtc.h index e14f542363707152db84d1ace5f3a59c874c31b5..dd5d8ad7ee2ed9de3d8e9cdc517e8ea3da7e8700 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rtc.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rtc.h @@ -38,365 +38,335 @@ extern "C" { /** * @brief Hours format */ -typedef enum -{ - RTC_HOUR_FORMAT_24 = 0x0, /**< 24-hours format */ - RTC_HOUR_FORMAT_12 = 0x1, /**< 12-hours format */ +typedef enum { + RTC_HOUR_FORMAT_24 = 0x0U, /**< 24-hours format */ + RTC_HOUR_FORMAT_12 = 0x1U, /**< 12-hours format */ } rtc_hour_format_t; /** * @brief Output mode */ -typedef enum -{ - RTC_OUTPUT_DISABLE = 0x0, /**< Disable output */ - RTC_OUTPUT_ALARM_A = 0x1, /**< Output alarm_a signal */ - RTC_OUTPUT_ALARM_B = 0x2, /**< Output alarm_b signal */ - RTC_OUTPUT_WAKEUP = 0x3, /**< Output wakeup signal */ +typedef enum { + RTC_OUTPUT_DISABLE = 0x0U, /**< Disable output */ + RTC_OUTPUT_ALARM_A = 0x1U, /**< Output alarm_a signal */ + RTC_OUTPUT_ALARM_B = 0x2U, /**< Output alarm_b signal */ + RTC_OUTPUT_WAKEUP = 0x3U, /**< Output wakeup signal */ } rtc_output_select_t; /** * @brief Output polarity */ -typedef enum -{ - RTC_OUTPUT_POLARITY_HIGH = 0x0, /**< Polarity is high */ - RTC_OUTPUT_POLARITY_LOW = 0x0, /**< Polarity is low */ +typedef enum { + RTC_OUTPUT_POLARITY_HIGH = 0x0U, /**< Polarity is high */ + RTC_OUTPUT_POLARITY_LOW = 0x1U, /**< Polarity is low */ } rtc_output_polarity_t; /** * @brief Initialization structure */ -typedef struct -{ - rtc_hour_format_t hour_format; /**< Hours format */ - uint32_t asynch_pre_div; /**< Asynchronous predivider value */ - uint32_t synch_pre_div; /**< Synchronous predivider value */ - rtc_output_select_t output; /**< Output signal type */ - rtc_output_polarity_t output_polarity; /**< Output polarity */ +typedef struct { + rtc_hour_format_t hour_format; /**< Hours format */ + uint32_t asynch_pre_div; /**< Asynchronous predivider value */ + uint32_t synch_pre_div; /**< Synchronous predivider value */ + rtc_output_select_t output; /**< Output signal type */ + rtc_output_polarity_t output_polarity; /**< Output polarity */ } rtc_init_t; /** * @brief Source select */ -typedef enum -{ - RTC_SOURCE_LOSC = 0x0, /**< LOSC */ - RTC_SOURCE_LRC = 0x1, /**< LRC */ - RTC_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ - RTC_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ +typedef enum { + RTC_SOURCE_LOSC = 0x0U, /**< LOSC */ + RTC_SOURCE_LRC = 0x1U, /**< LRC */ + RTC_SOURCE_HRC_DIV_1M = 0x2U, /**< HRC divide to 1MHz */ + RTC_SOURCE_HOSC_DIV_1M = 0x3U, /**< HOSC divide to 1MHz */ } rtc_source_sel_t; /** * @brief Time structure */ -typedef struct -{ - uint8_t hour; /**< Hours */ - uint8_t minute; /**< Minutes */ - uint8_t second; /**< Seconds */ - uint16_t sub_sec; /**< Sub-seconds */ +typedef struct { + uint8_t hour; /**< Hours */ + uint8_t minute; /**< Minutes */ + uint8_t second; /**< Seconds */ + uint16_t sub_sec; /**< Sub-seconds */ } rtc_time_t; /** * @brief Date structure */ -typedef struct -{ - uint8_t week; /**< Weeks */ - uint8_t day; /**< days */ - uint8_t month; /**< months */ - uint8_t year; /**< years */ +typedef struct { + uint8_t week; /**< Weeks */ + uint8_t day; /**< days */ + uint8_t month; /**< months */ + uint8_t year; /**< years */ } rtc_date_t; /** * @brief Data format */ -typedef enum -{ - RTC_FORMAT_DEC = 0, - RTC_FORMAT_BCD = 1, +typedef enum { + RTC_FORMAT_DEC = 0U, /**< DEC format */ + RTC_FORMAT_BCD = 1U, /**< BCD format */ } rtc_format_t; /** * @brief Index of alarm */ -typedef enum -{ - RTC_ALARM_A = 0x0, /**< Alarm-A */ - RTC_ALARM_B = 0x1, /**< Alarm-B */ +typedef enum { + RTC_ALARM_A = 0x0U, /**< Alarm-A */ + RTC_ALARM_B = 0x1U, /**< Alarm-B */ } rtc_alarm_idx_t; /** * @brief Alarm mask */ -typedef enum -{ - RTC_ALARM_MASK_NONE = 0x0, /**< Mask is disable */ - RTC_ALARM_MASK_WEEK_DAY = (1U << 30), /**< Mask week or day */ - RTC_ALARM_MASK_HOUR = (1U << 23), /**< Mask hour */ - RTC_ALARM_MASK_MINUTE = (1U << 15), /**< Mask minute */ - RTC_ALARM_MASK_SECOND = (1U << 7), /**< Mask second */ - RTC_ALARM_MASK_ALL = 0x40808080, /**< Mask all */ +typedef enum { + RTC_ALARM_MASK_NONE = 0x0U, /**< Mask is disable */ + RTC_ALARM_MASK_WEEK_DAY = (1U << 30), /**< Mask week or day */ + RTC_ALARM_MASK_HOUR = (1U << 23), /**< Mask hour */ + RTC_ALARM_MASK_MINUTE = (1U << 15), /**< Mask minute */ + RTC_ALARM_MASK_SECOND = (1U << 7), /**< Mask second */ + RTC_ALARM_MASK_ALL = 0x40808080U, /**< Mask all */ } rtc_alarm_mask_t; /** * @brief Alarm sub-second mask */ -typedef enum -{ - RTC_ALARM_SS_MASK_NONE = 0xF, /**< Mask is disable */ - RTC_ALARM_SS_MASK_14_1 = 0x1, /**< Mask bit(1-14) */ - RTC_ALARM_SS_MASK_14_2 = 0x2, /**< Mask bit(2-14) */ - RTC_ALARM_SS_MASK_14_3 = 0x3, /**< Mask bit(3-14) */ - RTC_ALARM_SS_MASK_14_4 = 0x4, /**< Mask bit(4-14) */ - RTC_ALARM_SS_MASK_14_5 = 0x5, /**< Mask bit(5-14) */ - RTC_ALARM_SS_MASK_14_6 = 0x6, /**< Mask bit(6-14) */ - RTC_ALARM_SS_MASK_14_7 = 0x7, /**< Mask bit(7-14) */ - RTC_ALARM_SS_MASK_14_8 = 0x8, /**< Mask bit(8-14) */ - RTC_ALARM_SS_MASK_14_9 = 0x9, /**< Mask bit(9-14) */ - RTC_ALARM_SS_MASK_14_10 = 0xA, /**< Mask bit(10-14) */ - RTC_ALARM_SS_MASK_14_11 = 0xB, /**< Mask bit(11-14) */ - RTC_ALARM_SS_MASK_14_12 = 0xC, /**< Mask bit(12-14) */ - RTC_ALARM_SS_MASK_14_13 = 0xD, /**< Mask bit(13-14) */ - RTC_ALARM_SS_MASK_14 = 0xE, /**< Mask bit14 */ - RTC_ALARM_SS_MASK_ALL = 0x0, /**< Mask bit(0-14) */ +typedef enum { + RTC_ALARM_SS_MASK_NONE = 0xFU, /**< Mask is disable */ + RTC_ALARM_SS_MASK_14_1 = 0x1U, /**< Mask bit(1-14) */ + RTC_ALARM_SS_MASK_14_2 = 0x2U, /**< Mask bit(2-14) */ + RTC_ALARM_SS_MASK_14_3 = 0x3U, /**< Mask bit(3-14) */ + RTC_ALARM_SS_MASK_14_4 = 0x4U, /**< Mask bit(4-14) */ + RTC_ALARM_SS_MASK_14_5 = 0x5U, /**< Mask bit(5-14) */ + RTC_ALARM_SS_MASK_14_6 = 0x6U, /**< Mask bit(6-14) */ + RTC_ALARM_SS_MASK_14_7 = 0x7U, /**< Mask bit(7-14) */ + RTC_ALARM_SS_MASK_14_8 = 0x8U, /**< Mask bit(8-14) */ + RTC_ALARM_SS_MASK_14_9 = 0x9U, /**< Mask bit(9-14) */ + RTC_ALARM_SS_MASK_14_10 = 0xAU, /**< Mask bit(10-14) */ + RTC_ALARM_SS_MASK_14_11 = 0xBU, /**< Mask bit(11-14) */ + RTC_ALARM_SS_MASK_14_12 = 0xCU, /**< Mask bit(12-14) */ + RTC_ALARM_SS_MASK_14_13 = 0xDU, /**< Mask bit(13-14) */ + RTC_ALARM_SS_MASK_14 = 0xEU, /**< Mask bit14 */ + RTC_ALARM_SS_MASK_ALL = 0x0U, /**< Mask bit(0-14) */ } rtc_sub_second_mask_t; /** * @brief Alarm select week or day */ -typedef enum -{ - RTC_SELECT_DAY = 0x0, /**< Alarm select day */ - RTC_SELECT_WEEK = 0x1, /**< Alarm select week */ +typedef enum { + RTC_SELECT_DAY = 0x0U, /**< Alarm select day */ + RTC_SELECT_WEEK = 0x1U, /**< Alarm select week */ } rtc_week_day_sel_t; /** * @brief Alarm structure */ -typedef struct -{ - rtc_alarm_idx_t idx; /**< Index of alarm */ - rtc_time_t time; /**< Time structure */ - uint32_t mask; /**< Alarm mask */ - rtc_sub_second_mask_t ss_mask; /**< Alarm sub-second mask */ - rtc_week_day_sel_t sel; /**< Select week or day */ - - union - { - uint8_t week; /**< Alarm select week */ - uint8_t day; /**< Alarm select day */ - }; +typedef struct { + rtc_alarm_idx_t idx; /**< Index of alarm */ + rtc_time_t time; /**< Time structure */ + uint32_t mask; /**< Alarm mask */ + rtc_sub_second_mask_t ss_mask; /**< Alarm sub-second mask */ + rtc_week_day_sel_t sel; /**< Select week or day */ + + union { + uint8_t week; /**< Alarm select week */ + uint8_t day; /**< Alarm select day */ + }; } rtc_alarm_t; /** * @brief Time stamp signel select */ -typedef enum -{ - RTC_TS_SIGNAL_SEL_TAMPER0 = 0, /**< Select tamper0 */ - RTC_TS_SIGNAL_SEL_TAMPER1 = 1, /**< Select tamper1 */ +typedef enum { + RTC_TS_SIGNAL_SEL_TAMPER0 = 0U, /**< Select tamper0 */ + RTC_TS_SIGNAL_SEL_TAMPER1 = 1U, /**< Select tamper1 */ } rtc_ts_signal_sel_t; /** * @brief Time stamp trigger style */ -typedef enum -{ - RTC_TS_RISING_EDGE = 0, /**< Rising edge */ - RTC_TS_FALLING_EDGE = 1, /**< Falling edge */ +typedef enum { + RTC_TS_RISING_EDGE = 0U, /**< Rising edge */ + RTC_TS_FALLING_EDGE = 1U, /**< Falling edge */ } rtc_ts_trigger_style_t; /** * @brief Index of tamper */ -typedef enum -{ - RTC_TAMPER_0 = 0, /**< Tamper0 */ - RTC_TAMPER_1 = 1, /**< Tamper1 */ +typedef enum { + RTC_TAMPER_0 = 0U, /**< Tamper0 */ + RTC_TAMPER_1 = 1U, /**< Tamper1 */ } rtc_tamper_idx_t; /** * @brief Tamper trigger type */ -typedef enum -{ - RTC_TAMPER_TRIGGER_LOW = 0, /**< High trigger */ - RTC_TAMPER_TRIGGER_HIGH = 1, /**< Low trigger */ +typedef enum { + RTC_TAMPER_TRIGGER_LOW = 0U, /**< High trigger */ + RTC_TAMPER_TRIGGER_HIGH = 1U, /**< Low trigger */ } rtc_tamper_trigger_t; /** * @brief Tamper sampling frequency */ -typedef enum -{ - RTC_TAMPER_SAMPLING_FREQ_32768 = 0, /**< RTCCLK / 32768 */ - RTC_TAMPER_SAMPLING_FREQ_16384 = 1, /**< RTCCLK / 16384 */ - RTC_TAMPER_SAMPLING_FREQ_8192 = 2, /**< RTCCLK / 8192 */ - RTC_TAMPER_SAMPLING_FREQ_4096 = 3, /**< RTCCLK / 4096 */ - RTC_TAMPER_SAMPLING_FREQ_2048 = 4, /**< RTCCLK / 2048 */ - RTC_TAMPER_SAMPLING_FREQ_1024 = 5, /**< RTCCLK / 1024 */ - RTC_TAMPER_SAMPLING_FREQ_512 = 6, /**< RTCCLK / 512 */ - RTC_TAMPER_SAMPLING_FREQ_256 = 7, /**< RTCCLK / 256 */ +typedef enum { + RTC_TAMPER_SAMPLING_FREQ_32768 = 0U, /**< RTCCLK / 32768 */ + RTC_TAMPER_SAMPLING_FREQ_16384 = 1U, /**< RTCCLK / 16384 */ + RTC_TAMPER_SAMPLING_FREQ_8192 = 2U, /**< RTCCLK / 8192 */ + RTC_TAMPER_SAMPLING_FREQ_4096 = 3U, /**< RTCCLK / 4096 */ + RTC_TAMPER_SAMPLING_FREQ_2048 = 4U, /**< RTCCLK / 2048 */ + RTC_TAMPER_SAMPLING_FREQ_1024 = 5U, /**< RTCCLK / 1024 */ + RTC_TAMPER_SAMPLING_FREQ_512 = 6U, /**< RTCCLK / 512 */ + RTC_TAMPER_SAMPLING_FREQ_256 = 7U, /**< RTCCLK / 256 */ } rtc_tamper_sampling_freq_t; /** * @brief Tamper filter time */ -typedef enum -{ - RTC_TAMPER_DURATION_1 = 0, /**< Duration 1 sampling */ - RTC_TAMPER_DURATION_2 = 1, /**< Duration 2 sampling */ - RTC_TAMPER_DURATION_4 = 2, /**< Duration 4 sampling */ - RTC_TAMPER_DURATION_8 = 3, /**< Duration 8 sampling */ +typedef enum { + RTC_TAMPER_DURATION_1 = 0U, /**< Duration 1 sampling */ + RTC_TAMPER_DURATION_2 = 1U, /**< Duration 2 sampling */ + RTC_TAMPER_DURATION_4 = 2U, /**< Duration 4 sampling */ + RTC_TAMPER_DURATION_8 = 3U, /**< Duration 8 sampling */ } rtc_tamper_duration_t; /** * @brief Tamper structure */ -typedef struct -{ - rtc_tamper_idx_t idx; /**< Index of tamper */ - rtc_tamper_trigger_t trig; /**< Trigger type */ - rtc_tamper_sampling_freq_t freq; /**< Sampling frequency */ - rtc_tamper_duration_t dur; /**< Filter time */ - type_func_t ts; /**< Enable/Disable trigger time stamp event */ +typedef struct { + rtc_tamper_idx_t idx; /**< Index of tamper */ + rtc_tamper_trigger_t trig; /**< Trigger type */ + rtc_tamper_sampling_freq_t freq; /**< Sampling frequency */ + rtc_tamper_duration_t dur; /**< Filter time */ + type_func_t ts; /**< Enable/Disable trigger time stamp event */ } rtc_tamper_t; /** * @brief Wake-up clock */ -typedef enum -{ - RTC_WAKEUP_CLOCK_DIV_16 = 0, /**< RTCCLK / 16 */ - RTC_WAKEUP_CLOCK_DIV_8 = 1, /**< RTCCLK / 8 */ - RTC_WAKEUP_CLOCK_DIV_4 = 2, /**< RTCCLK / 4 */ - RTC_WAKEUP_CLOCK_DIV_2 = 3, /**< RTCCLK / 2 */ - RTC_WAKEUP_CLOCK_1HZ = 4, /**< 1Hz */ - RTC_WAKEUP_CLOCK_1HZ_PULS = 6, /**< 1Hz and WUT + 65536 */ +typedef enum { + RTC_WAKEUP_CLOCK_DIV_16 = 0U, /**< RTCCLK / 16 */ + RTC_WAKEUP_CLOCK_DIV_8 = 1U, /**< RTCCLK / 8 */ + RTC_WAKEUP_CLOCK_DIV_4 = 2U, /**< RTCCLK / 4 */ + RTC_WAKEUP_CLOCK_DIV_2 = 3U, /**< RTCCLK / 2 */ + RTC_WAKEUP_CLOCK_1HZ = 4U, /**< 1Hz */ + RTC_WAKEUP_CLOCK_1HZ_PULS = 6U, /**< 1Hz and WUT + 65536 */ } rtc_wakeup_clock_t; /** * @brief RTC clock output type */ -typedef enum -{ - RTC_CLOCK_OUTPUT_32768 = 0, /**< 32768Hz */ - RTC_CLOCK_OUTPUT_1024 = 1, /**< 1024Hz */ - RTC_CLOCK_OUTPUT_32 = 2, /**< 32Hz */ - RTC_CLOCK_OUTPUT_1 = 3, /**< 1Hz */ - RTC_CLOCK_OUTPUT_CAL_1 = 4, /**< 1Hz after calibration */ - RTC_CLOCK_OUTPUT_EXA_1 = 5, /**< Exact 1Hz */ +typedef enum { + RTC_CLOCK_OUTPUT_32768 = 0U, /**< 32768Hz */ + RTC_CLOCK_OUTPUT_1024 = 1U, /**< 1024Hz */ + RTC_CLOCK_OUTPUT_32 = 2U, /**< 32Hz */ + RTC_CLOCK_OUTPUT_1 = 3U, /**< 1Hz */ + RTC_CLOCK_OUTPUT_CAL_1 = 4U, /**< 1Hz after calibration */ + RTC_CLOCK_OUTPUT_EXA_1 = 5U, /**< Exact 1Hz */ } rtc_clock_output_t; /** * @ Calibration frequency */ -typedef enum -{ - RTC_CALI_FREQ_10_SEC = 0, /**< Calibrate every 10 seconds */ - RTC_CALI_FREQ_20_SEC = 1, /**< Calibrate every 20 seconds */ - RTC_CALI_FREQ_1_MIN = 2, /**< Calibrate every 1 minute */ - RTC_CALI_FREQ_2_MIN = 3, /**< Calibrate every 2 minutes */ - RTC_CALI_FREQ_5_MIN = 4, /**< Calibrate every 5 minutes */ - RTC_CALI_FREQ_10_MIN = 5, /**< Calibrate every 10 minutes */ - RTC_CALI_FREQ_20_MIN = 6, /**< Calibrate every 20 minutes */ - RTC_CALI_FREQ_1_SEC = 7, /**< Calibrate every 1 second */ +typedef enum { + RTC_CALI_FREQ_10_SEC = 0U, /**< Calibrate every 10 seconds */ + RTC_CALI_FREQ_20_SEC = 1U, /**< Calibrate every 20 seconds */ + RTC_CALI_FREQ_1_MIN = 2U, /**< Calibrate every 1 minute */ + RTC_CALI_FREQ_2_MIN = 3U, /**< Calibrate every 2 minutes */ + RTC_CALI_FREQ_5_MIN = 4U, /**< Calibrate every 5 minutes */ + RTC_CALI_FREQ_10_MIN = 5U, /**< Calibrate every 10 minutes */ + RTC_CALI_FREQ_20_MIN = 6U, /**< Calibrate every 20 minutes */ + RTC_CALI_FREQ_1_SEC = 7U, /**< Calibrate every 1 second */ } rtc_cali_freq_t; /** * @brief Temperature compensate type */ -typedef enum -{ - RTC_CALI_TC_NONE = 0, /**< Temperature compensate disable */ - RTC_CALI_TC_AUTO_BY_HW = 1, /**< Temperature compensate by hardware */ - RTC_CALI_TC_AUTO_BY_SF = 2, /**< Temperature compensate by software */ - RTC_CALI_TC_AUTO_BY_HW_SF = 3, /**< Temperature compensate by hardware, trigger by software */ +typedef enum { + RTC_CALI_TC_NONE = 0U, /**< Temperature compensate disable */ + RTC_CALI_TC_AUTO_BY_HW = 1U, /**< Temperature compensate by hardware */ + RTC_CALI_TC_AUTO_BY_SF = 2U, /**< Temperature compensate by software */ + RTC_CALI_TC_AUTO_BY_HW_SF = 3U, /**< Temperature compensate by hardware, trigger by software */ } rtc_cali_tc_t; /** * @ Calculate frequency */ -typedef enum -{ - RTC_CALI_CALC_FREQ_10_SEC = 0, /**< Calculate every 10 seconds */ - RTC_CALI_CALC_FREQ_20_SEC = 1, /**< Calculate every 20 seconds */ - RTC_CALI_CALC_FREQ_1_MIN = 2, /**< Calculate every 1 minute */ - RTC_CALI_CALC_FREQ_2_MIN = 3, /**< Calculate every 2 minutes */ - RTC_CALI_CALC_FREQ_5_MIN = 4, /**< Calculate every 5 minutes */ - RTC_CALI_CALC_FREQ_10_MIN = 5, /**< Calculate every 10 minutes */ - RTC_CALI_CALC_FREQ_20_MIN = 6, /**< Calculate every 20 minutes */ - RTC_CALI_CALC_FREQ_1_HOUR = 7, /**< Calculate every 1 hour */ +typedef enum { + RTC_CALI_CALC_FREQ_10_SEC = 0U, /**< Calculate every 10 seconds */ + RTC_CALI_CALC_FREQ_20_SEC = 1U, /**< Calculate every 20 seconds */ + RTC_CALI_CALC_FREQ_1_MIN = 2U, /**< Calculate every 1 minute */ + RTC_CALI_CALC_FREQ_2_MIN = 3U, /**< Calculate every 2 minutes */ + RTC_CALI_CALC_FREQ_5_MIN = 4U, /**< Calculate every 5 minutes */ + RTC_CALI_CALC_FREQ_10_MIN = 5U, /**< Calculate every 10 minutes */ + RTC_CALI_CALC_FREQ_20_MIN = 6U, /**< Calculate every 20 minutes */ + RTC_CALI_CALC_FREQ_1_HOUR = 7U, /**< Calculate every 1 hour */ } rtc_cali_calc_freq_t; /** * @brief Calibration algorithm */ -typedef enum -{ - RTC_CALI_CALC_4 = 0, /**< 4-polynomial */ - RTC_CALI_CALC_2 = 1, /**< 2-parabola */ +typedef enum { + RTC_CALI_CALC_4 = 0U, /**< 4-polynomial */ + RTC_CALI_CALC_2 = 1U, /**< 2-parabola */ } rtc_cali_calc_t; /** * @brief Calibration structure */ -typedef struct -{ - rtc_cali_freq_t cali_freq; /**< calibrate frequency */ - rtc_cali_tc_t tc; /**< Temperature compensate type */ - rtc_cali_calc_freq_t calc_freq; /**< Calculate frequency */ - rtc_cali_calc_t calc; /**< algorithm */ - type_func_t acc; /**< Enable/Disable decimal accumulate */ +typedef struct { + rtc_cali_freq_t cali_freq; /**< calibrate frequency */ + rtc_cali_tc_t tc; /**< Temperature compensate type */ + rtc_cali_calc_freq_t calc_freq; /**< Calculate frequency */ + rtc_cali_calc_t calc; /**< algorithm */ + type_func_t acc; /**< Enable/Disable decimal accumulate */ } rtc_cali_t; /** * @brief Interrupt type */ -typedef enum -{ - RTC_IT_SEC = (1U << 0), /**< Second */ - RTC_IT_MIN = (1U << 1), /**< Minute */ - RTC_IT_HR = (1U << 2), /**< Hour */ - RTC_IT_DAY = (1U << 3), /**< Day */ - RTC_IT_MON = (1U << 4), /**< Month */ - RTC_IT_YR = (1U << 5), /**< Year */ - RTC_IT_ALMA = (1U << 8), /**< Alarm-A */ - RTC_IT_ALMB = (1U << 9), /**< Alarm-B */ - RTC_IT_TS = (1U << 10), /**< Time stamp */ - RTC_IT_TSOV = (1U << 11), /**< Time stamp overflow */ - RTC_IT_TP0 = (1U << 12), /**< Tamper-0 */ - RTC_IT_TP1 = (1U << 13), /**< Tamper-1 */ - RTC_IT_RSC = (1U << 16), /**< Synchronous complete */ - RTC_IT_SFC = (1U << 17), /**< Shift complete */ - RTC_IT_WU = (1U << 18), /**< Wake-up */ - RTC_IT_TCC = (1U << 24), /**< Temperature compensate complete */ - RTC_IT_TCE = (1U << 25), /**< Temperature compensate error */ +typedef enum { + RTC_IT_SEC = (1U << 0), /**< Second */ + RTC_IT_MIN = (1U << 1), /**< Minute */ + RTC_IT_HR = (1U << 2), /**< Hour */ + RTC_IT_DAY = (1U << 3), /**< Day */ + RTC_IT_MON = (1U << 4), /**< Month */ + RTC_IT_YR = (1U << 5), /**< Year */ + RTC_IT_ALMA = (1U << 8), /**< Alarm-A */ + RTC_IT_ALMB = (1U << 9), /**< Alarm-B */ + RTC_IT_TS = (1U << 10), /**< Time stamp */ + RTC_IT_TSOV = (1U << 11), /**< Time stamp overflow */ + RTC_IT_TP0 = (1U << 12), /**< Tamper-0 */ + RTC_IT_TP1 = (1U << 13), /**< Tamper-1 */ + RTC_IT_RSC = (1U << 16), /**< Synchronous complete */ + RTC_IT_SFC = (1U << 17), /**< Shift complete */ + RTC_IT_WU = (1U << 18), /**< Wake-up */ + RTC_IT_TCC = (1U << 24), /**< Temperature compensate complete */ + RTC_IT_TCE = (1U << 25), /**< Temperature compensate error */ } rtc_it_t; /** * @brief Interrupt flag */ -typedef enum -{ - RTC_IF_SEC = (1U << 0), /**< Second */ - RTC_IF_MIN = (1U << 1), /**< Minute */ - RTC_IF_HR = (1U << 2), /**< Hour */ - RTC_IF_DAY = (1U << 3), /**< Day */ - RTC_IF_MON = (1U << 4), /**< Month */ - RTC_IF_YR = (1U << 5), /**< Year */ - RTC_IF_ALMA = (1U << 8), /**< Alarm-A */ - RTC_IF_ALMB = (1U << 9), /**< Alarm-B */ - RTC_IF_TS = (1U << 10), /**< Time stamp */ - RTC_IF_TSOV = (1U << 11), /**< Time stamp overflow */ - RTC_IF_TP0 = (1U << 12), /**< Tamper-0 */ - RTC_IF_TP1 = (1U << 13), /**< Tamper-1 */ - RTC_IF_RSC = (1U << 16), /**< Synchronous complete */ - RTC_IF_SFC = (1U << 17), /**< Shift complete */ - RTC_IF_WU = (1U << 18), /**< Wake-up */ - RTC_IF_TCC = (1U << 24), /**< Temperature compensate complete */ - RTC_IF_TCE = (1U << 25), /**< Temperature compensate error */ +typedef enum { + RTC_IF_SEC = (1U << 0), /**< Second */ + RTC_IF_MIN = (1U << 1), /**< Minute */ + RTC_IF_HR = (1U << 2), /**< Hour */ + RTC_IF_DAY = (1U << 3), /**< Day */ + RTC_IF_MON = (1U << 4), /**< Month */ + RTC_IF_YR = (1U << 5), /**< Year */ + RTC_IF_ALMA = (1U << 8), /**< Alarm-A */ + RTC_IF_ALMB = (1U << 9), /**< Alarm-B */ + RTC_IF_TS = (1U << 10), /**< Time stamp */ + RTC_IF_TSOV = (1U << 11), /**< Time stamp overflow */ + RTC_IF_TP0 = (1U << 12), /**< Tamper-0 */ + RTC_IF_TP1 = (1U << 13), /**< Tamper-1 */ + RTC_IF_RSC = (1U << 16), /**< Synchronous complete */ + RTC_IF_SFC = (1U << 17), /**< Shift complete */ + RTC_IF_WU = (1U << 18), /**< Wake-up */ + RTC_IF_TCC = (1U << 24), /**< Temperature compensate complete */ + RTC_IF_TCE = (1U << 25), /**< Temperature compensate error */ } rtc_flag_t; /** * @} @@ -405,44 +375,44 @@ typedef enum /** @defgroup RTC_Public_Macro RTC Public Macros * @{ */ -#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55)) -#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0)) +#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55U)) +#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0U)) #define RTC_BY_PASS_ENABLE() \ - do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ - RTC_LOCK(); \ - } while (0) +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ + RTC_LOCK(); \ +} while (0) #define RTC_BY_PASS_DISABLE() \ - do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ - RTC_LOCK(); \ - } while (0) +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ + RTC_LOCK(); \ +} while (0) #define RTC_SUMMER_TIME_ENABLE() \ - do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ - RTC_LOCK(); \ - } while (0) +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ + RTC_LOCK(); \ +} while (0) #define RTC_SUMMER_TIME_DISABLE() \ - do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ - RTC_LOCK(); \ - } while (0) +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ + RTC_LOCK(); \ +} while (0) #define RTC_WINTER_TIME_ENABLE() \ - do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ - RTC_LOCK(); \ - } while (0) +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ + RTC_LOCK(); \ +} while (0) #define RTC_WINTER_TIME_DISABLE() \ - do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ - RTC_LOCK(); \ - } while (0) +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ + RTC_LOCK(); \ +} while (0) /** * @} */ @@ -450,10 +420,10 @@ typedef enum /** @defgroup CAN_Private_Macros CAN Private Macros * @{ */ -#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AA)) -#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0)) -#define ALARM_MASK_ALL 0x40808080 -#define RTC_TIMEOUT_VALUE 100 +#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AAU)) +#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0U)) +#define ALARM_MASK_ALL 0x40808080U +#define RTC_TIMEOUT_VALUE 100U #define IS_SHIFT_SUB_SS(x) ((x) < (1U << 15)) #define IS_RTC_HOUR_FORMAT(x) (((x) == RTC_HOUR_FORMAT_24) || \ @@ -463,15 +433,15 @@ typedef enum ((x) == RTC_OUTPUT_ALARM_B) || \ ((x) == RTC_OUTPUT_WAKEUP)) #define IS_RTC_OUTPUT_POLARITY(x) (((x) == RTC_OUTPUT_POLARITY_HIGH) || \ - ((x) == RTC_OUTPUT_POLARITY_LOW)) + ((x) == RTC_OUTPUT_POLARITY_LOW)) #define IS_RTC_SOURCE_SEL(x) (((x) == RTC_SOURCE_LOSC) || \ ((x) == RTC_SOURCE_LRC) || \ ((x) == RTC_SOURCE_HRC_DIV_1M ) || \ ((x) == RTC_SOURCE_HOSC_DIV_1M)) #define IS_RTC_ALARM(x) (((x) == RTC_ALARM_A) || \ - ((x) == RTC_ALARM_B)) + ((x) == RTC_ALARM_B)) #define IS_RTC_ALARM_SEL(x) (((x) == RTC_SELECT_DAY) || \ - ((x) == RTC_SELECT_WEEK)) + ((x) == RTC_SELECT_WEEK)) #define IS_RTC_ALARM_MASK(x) (((x) == RTC_ALARM_MASK_NONE) || \ ((x) == RTC_ALARM_MASK_WEEK_DAY) || \ ((x) == RTC_ALARM_MASK_HOUR) || \ @@ -495,27 +465,27 @@ typedef enum ((x) == RTC_ALARM_SS_MASK_14) || \ ((x) == RTC_ALARM_SS_MASK_ALL)) #define IS_RTC_TS_SIGNAL(x) (((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \ - ((x) == RTC_TS_SIGNAL_SEL_TAMPER1)) + ((x) == RTC_TS_SIGNAL_SEL_TAMPER1)) #define IS_RTC_TS_STYLE(x) (((x) == RTC_TS_RISING_EDGE) || \ - ((x) == RTC_TS_FALLING_EDGE)) + ((x) == RTC_TS_FALLING_EDGE)) #define IS_RTC_FORMAT(x) (((x) == RTC_FORMAT_DEC) || \ - ((x) == RTC_FORMAT_BCD)) + ((x) == RTC_FORMAT_BCD)) #define IS_RTC_TAMPER(x) (((x) == RTC_TAMPER_0) || \ - ((x) == RTC_TAMPER_1)) + ((x) == RTC_TAMPER_1)) #define IS_RTC_TAMPER_TRIGGER(x) (((x) == RTC_TAMPER_TRIGGER_LOW) || \ - ((x) == RTC_TAMPER_TRIGGER_HIGH)) + ((x) == RTC_TAMPER_TRIGGER_HIGH)) #define IS_RTC_TAMPER_SAMPLING_FREQ(x) (((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_8192) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_4096) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_2048) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_1024) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_512) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_256)) + ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_8192) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_4096) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_2048) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_1024) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_512) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_256)) #define IS_RTC_TAMPER_DURATION(x) (((x) == RTC_TAMPER_DURATION_1) || \ - ((x) == RTC_TAMPER_DURATION_2) || \ - ((x) == RTC_TAMPER_DURATION_4) || \ - ((x) == RTC_TAMPER_DURATION_8)) + ((x) == RTC_TAMPER_DURATION_2) || \ + ((x) == RTC_TAMPER_DURATION_4) || \ + ((x) == RTC_TAMPER_DURATION_8)) #define IS_RTC_WAKEUP_CLOCK(x) (((x) == RTC_WAKEUP_CLOCK_DIV_16) || \ ((x) == RTC_WAKEUP_CLOCK_DIV_8) || \ ((x) == RTC_WAKEUP_CLOCK_DIV_4) || \ @@ -529,61 +499,61 @@ typedef enum ((x) == RTC_CLOCK_OUTPUT_CAL_1) || \ ((x) == RTC_CLOCK_OUTPUT_EXA_1)) #define IS_RTC_CALI_FREQ(x) (((x) == RTC_CALI_FREQ_10_SEC) || \ - ((x) == RTC_CALI_FREQ_20_SEC) || \ - ((x) == RTC_CALI_FREQ_1_MIN) || \ - ((x) == RTC_CALI_FREQ_2_MIN) || \ - ((x) == RTC_CALI_FREQ_5_MIN) || \ - ((x) == RTC_CALI_FREQ_10_MIN) || \ - ((x) == RTC_CALI_FREQ_20_MIN) || \ - ((x) == RTC_CALI_FREQ_1_SEC)) + ((x) == RTC_CALI_FREQ_20_SEC) || \ + ((x) == RTC_CALI_FREQ_1_MIN) || \ + ((x) == RTC_CALI_FREQ_2_MIN) || \ + ((x) == RTC_CALI_FREQ_5_MIN) || \ + ((x) == RTC_CALI_FREQ_10_MIN) || \ + ((x) == RTC_CALI_FREQ_20_MIN) || \ + ((x) == RTC_CALI_FREQ_1_SEC)) #define IS_RTC_CALI_TC(x) (((x) == RTC_CALI_TC_NONE) || \ - ((x) == RTC_CALI_TC_AUTO_BY_HW) || \ - ((x) == RTC_CALI_TC_AUTO_BY_SF) || \ - ((x) == RTC_CALI_TC_AUTO_BY_HW_SF)) + ((x) == RTC_CALI_TC_AUTO_BY_HW) || \ + ((x) == RTC_CALI_TC_AUTO_BY_SF) || \ + ((x) == RTC_CALI_TC_AUTO_BY_HW_SF)) #define IS_RTC_CALC_FREQ(x) (((x) == RTC_CALI_CALC_FREQ_10_SEC) || \ - ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \ - ((x) == RTC_CALI_CALC_FREQ_1_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_2_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_5_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_1_HOUR)) + ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \ + ((x) == RTC_CALI_CALC_FREQ_1_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_2_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_5_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_1_HOUR)) #define IS_RTC_CALI_CALC(x) (((x) == RTC_CALI_CALC_4) || \ - ((x) == RTC_CALI_CALC_2)) + ((x) == RTC_CALI_CALC_2)) #define IS_RTC_IT(x) (((x) == RTC_IT_SEC) || \ - ((x) == RTC_IT_MIN) || \ - ((x) == RTC_IT_HR) || \ - ((x) == RTC_IT_DAY) || \ - ((x) == RTC_IT_MON) || \ - ((x) == RTC_IT_YR) || \ - ((x) == RTC_IT_ALMA) || \ - ((x) == RTC_IT_ALMB) || \ - ((x) == RTC_IT_TS) || \ - ((x) == RTC_IT_TSOV) || \ - ((x) == RTC_IT_TP0) || \ - ((x) == RTC_IT_TP1) || \ - ((x) == RTC_IT_RSC) || \ - ((x) == RTC_IT_SFC) || \ - ((x) == RTC_IT_WU) || \ - ((x) == RTC_IT_TCC) || \ - ((x) == RTC_IT_TCE)) + ((x) == RTC_IT_MIN) || \ + ((x) == RTC_IT_HR) || \ + ((x) == RTC_IT_DAY) || \ + ((x) == RTC_IT_MON) || \ + ((x) == RTC_IT_YR) || \ + ((x) == RTC_IT_ALMA) || \ + ((x) == RTC_IT_ALMB) || \ + ((x) == RTC_IT_TS) || \ + ((x) == RTC_IT_TSOV) || \ + ((x) == RTC_IT_TP0) || \ + ((x) == RTC_IT_TP1) || \ + ((x) == RTC_IT_RSC) || \ + ((x) == RTC_IT_SFC) || \ + ((x) == RTC_IT_WU) || \ + ((x) == RTC_IT_TCC) || \ + ((x) == RTC_IT_TCE)) #define IS_RTC_IF(x) (((x) == RTC_IF_SEC) || \ - ((x) == RTC_IF_MIN) || \ - ((x) == RTC_IF_HR) || \ - ((x) == RTC_IF_DAY) || \ - ((x) == RTC_IF_MON) || \ - ((x) == RTC_IF_YR) || \ - ((x) == RTC_IF_ALMA) || \ - ((x) == RTC_IF_ALMB) || \ - ((x) == RTC_IF_TS) || \ - ((x) == RTC_IF_TSOV) || \ - ((x) == RTC_IF_TP0) || \ - ((x) == RTC_IF_TP1) || \ - ((x) == RTC_IF_RSC) || \ - ((x) == RTC_IF_SFC) || \ - ((x) == RTC_IF_WU) || \ - ((x) == RTC_IF_TCC) || \ - ((x) == RTC_IF_TCE)) + ((x) == RTC_IF_MIN) || \ + ((x) == RTC_IF_HR) || \ + ((x) == RTC_IF_DAY) || \ + ((x) == RTC_IF_MON) || \ + ((x) == RTC_IF_YR) || \ + ((x) == RTC_IF_ALMA) || \ + ((x) == RTC_IF_ALMB) || \ + ((x) == RTC_IF_TS) || \ + ((x) == RTC_IF_TSOV) || \ + ((x) == RTC_IF_TP0) || \ + ((x) == RTC_IF_TP1) || \ + ((x) == RTC_IF_RSC) || \ + ((x) == RTC_IF_SFC) || \ + ((x) == RTC_IF_WU) || \ + ((x) == RTC_IF_TCC) || \ + ((x) == RTC_IF_TCE)) #define IS_RTC_SECOND(x) ((x) < 60) #define IS_RTC_MINUTE(x) ((x) < 60) #define IS_RTC_HOUR(x) ((x) < 24) diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_smartcard.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_smartcard.h index b04380ee6d0973f1fc31238a247a07616adce0c3..74401fecc136614fdec18985ba4e61d0efe1deee 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_smartcard.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_smartcard.h @@ -18,7 +18,7 @@ #define __ALD_SMARTCARD_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -41,52 +41,50 @@ extern "C" { /** * @brief SMARTCARD error codes */ -typedef enum -{ - SMARTCARD_ERROR_NONE = ((uint32_t)0x00), /**< No error */ - SMARTCARD_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ - SMARTCARD_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ - SMARTCARD_ERROR_FE = ((uint32_t)0x04), /**< frame error */ - SMARTCARD_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ - SMARTCARD_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +typedef enum { + SMARTCARD_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ + SMARTCARD_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ + SMARTCARD_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ + SMARTCARD_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ + SMARTCARD_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ + SMARTCARD_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ } smartcard_error_t; /** * @brief SMARTCARD Prescaler */ -typedef enum -{ - SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1), /**< SYSCLK divided by 2 */ - SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2), /**< SYSCLK divided by 4 */ - SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3), /**< SYSCLK divided by 6 */ - SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4), /**< SYSCLK divided by 8 */ - SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5), /**< SYSCLK divided by 10 */ - SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6), /**< SYSCLK divided by 12 */ - SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7), /**< SYSCLK divided by 14 */ - SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8), /**< SYSCLK divided by 16 */ - SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9), /**< SYSCLK divided by 18 */ - SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xA), /**< SYSCLK divided by 20 */ - SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xB), /**< SYSCLK divided by 22 */ - SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xC), /**< SYSCLK divided by 24 */ - SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xD), /**< SYSCLK divided by 26 */ - SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xE), /**< SYSCLK divided by 28 */ - SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xF), /**< SYSCLK divided by 30 */ - SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10), /**< SYSCLK divided by 32 */ - SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11), /**< SYSCLK divided by 34 */ - SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12), /**< SYSCLK divided by 36 */ - SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13), /**< SYSCLK divided by 38 */ - SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14), /**< SYSCLK divided by 40 */ - SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15), /**< SYSCLK divided by 42 */ - SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16), /**< SYSCLK divided by 44 */ - SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17), /**< SYSCLK divided by 46 */ - SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18), /**< SYSCLK divided by 48 */ - SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19), /**< SYSCLK divided by 50 */ - SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1A), /**< SYSCLK divided by 52 */ - SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1B), /**< SYSCLK divided by 54 */ - SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1C), /**< SYSCLK divided by 56 */ - SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1D), /**< SYSCLK divided by 58 */ - SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1E), /**< SYSCLK divided by 60 */ - SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1F), /**< SYSCLK divided by 62 */ +typedef enum { + SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1U), /**< SYSCLK divided by 2 */ + SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2U), /**< SYSCLK divided by 4 */ + SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3U), /**< SYSCLK divided by 6 */ + SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4U), /**< SYSCLK divided by 8 */ + SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5U), /**< SYSCLK divided by 10 */ + SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6U), /**< SYSCLK divided by 12 */ + SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7U), /**< SYSCLK divided by 14 */ + SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8U), /**< SYSCLK divided by 16 */ + SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9U), /**< SYSCLK divided by 18 */ + SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xAU), /**< SYSCLK divided by 20 */ + SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xBU), /**< SYSCLK divided by 22 */ + SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xCU), /**< SYSCLK divided by 24 */ + SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xDU), /**< SYSCLK divided by 26 */ + SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xEU), /**< SYSCLK divided by 28 */ + SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xFU), /**< SYSCLK divided by 30 */ + SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10U), /**< SYSCLK divided by 32 */ + SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11U), /**< SYSCLK divided by 34 */ + SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12U), /**< SYSCLK divided by 36 */ + SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13U), /**< SYSCLK divided by 38 */ + SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14U), /**< SYSCLK divided by 40 */ + SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15U), /**< SYSCLK divided by 42 */ + SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16U), /**< SYSCLK divided by 44 */ + SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17U), /**< SYSCLK divided by 46 */ + SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18U), /**< SYSCLK divided by 48 */ + SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19U), /**< SYSCLK divided by 50 */ + SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1AU), /**< SYSCLK divided by 52 */ + SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1BU), /**< SYSCLK divided by 54 */ + SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1CU), /**< SYSCLK divided by 56 */ + SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1DU), /**< SYSCLK divided by 58 */ + SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1EU), /**< SYSCLK divided by 60 */ + SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1FU), /**< SYSCLK divided by 62 */ } smartcard_prescaler_t; /** @@ -100,69 +98,66 @@ typedef enum /** * @brief SMARTCARD Init Structure definition */ -typedef struct -{ - uint32_t baud; /**< This member configures the SmartCard communication baud rate. */ - usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ - usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ - usart_parity_t parity; /**< Specifies the parity mode. +typedef struct { + uint32_t baud; /**< This member configures the SmartCard communication baud rate. */ + usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ + usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ + usart_parity_t parity; /**< Specifies the parity mode. @note When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).*/ - usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */ - usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ - usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/ - usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted + usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */ + usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ + usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/ + usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref usart_last_bit_t */ - smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock + smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock to provide the smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency. */ - uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */ - type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */ + uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */ + type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */ } smartcard_init_t; /** * @brief ALD state structures definition */ -typedef enum -{ - SMARTCARD_STATE_RESET = 0x00, /**< Peripheral is not yet Initialized */ - SMARTCARD_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - SMARTCARD_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - SMARTCARD_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - SMARTCARD_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ - SMARTCARD_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission and Reception process is ongoing */ - SMARTCARD_STATE_TIMEOUT = 0x03, /**< Timeout state */ - SMARTCARD_STATE_ERROR = 0x04 /**< Error */ +typedef enum { + SMARTCARD_STATE_RESET = 0x00U, /**< Peripheral is not yet Initialized */ + SMARTCARD_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + SMARTCARD_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + SMARTCARD_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ + SMARTCARD_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ + SMARTCARD_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission and Reception process is ongoing */ + SMARTCARD_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + SMARTCARD_STATE_ERROR = 0x04U, /**< Error */ } smartcard_state_t; /** * @brief SMARTCARD handle structure definition */ -typedef struct smartcard_handle_s -{ - USART_TypeDef *perh; /**< USART registers base address */ - smartcard_init_t init; /**< SmartCard communication parameters */ - uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */ - uint16_t tx_size; /**< SmartCard Tx Transfer size */ - uint16_t tx_count; /**< SmartCard Tx Transfer Counter */ - uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */ - uint16_t rx_size; /**< SmartCard Rx Transfer size */ - uint16_t rx_count; /**< SmartCard Rx Transfer Counter */ +typedef struct smartcard_handle_s { + USART_TypeDef *perh; /**< USART registers base address */ + smartcard_init_t init; /**< SmartCard communication parameters */ + uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */ + uint16_t tx_size; /**< SmartCard Tx Transfer size */ + uint16_t tx_count; /**< SmartCard Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */ + uint16_t rx_size; /**< SmartCard Rx Transfer size */ + uint16_t rx_count; /**< SmartCard Rx Transfer Counter */ #ifdef ALD_DMA - dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */ - dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */ + dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */ + dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */ #endif - lock_state_t lock; /**< Locking object */ - smartcard_state_t state; /**< SmartCard communication state */ - uint32_t err_code; /**< SmartCard Error code */ + lock_state_t lock; /**< Locking object */ + smartcard_state_t state; /**< SmartCard communication state */ + uint32_t err_code; /**< SmartCard Error code */ - void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */ + void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */ } smartcard_handle_t; /** @@ -214,7 +209,7 @@ typedef struct smartcard_handle_s */ #define IS_SMARTCARD_PRESCALER(x) (((x) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \ - ((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62)) + ((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62)) /** * @} */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_spi.h index d92aefb219bd36f88c6b54c2f17eb07cdb7d180a..1a7c7c7e5ead6a5c1d4a196d87897625a86aca89 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_spi.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_spi.h @@ -18,7 +18,7 @@ #define __ALD_SPI_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -39,97 +39,88 @@ extern "C" { /** * @brief clock phase */ -typedef enum -{ - SPI_CPHA_FIRST = 0, /**< Transiting data in the first edge */ - SPI_CPHA_SECOND = 1, /**< Transiting data in the seconde edge */ +typedef enum { + SPI_CPHA_FIRST = 0U, /**< Transiting data in the first edge */ + SPI_CPHA_SECOND = 1U, /**< Transiting data in the seconde edge */ } spi_cpha_t; /** * @brief clock polarity */ -typedef enum -{ - SPI_CPOL_LOW = 0, /**< Polarity hold low when spi-bus is idle */ - SPI_CPOL_HIGH = 1, /**< Polarity hold high when spi-bus is idle */ +typedef enum { + SPI_CPOL_LOW = 0U, /**< Polarity hold low when spi-bus is idle */ + SPI_CPOL_HIGH = 1U, /**< Polarity hold high when spi-bus is idle */ } spi_cpol_t; /** * @brief master selection */ -typedef enum -{ - SPI_MODE_SLAVER = 0, /**< Slave mode */ - SPI_MODE_MASTER = 1, /**< Master mode */ +typedef enum { + SPI_MODE_SLAVER = 0U, /**< Slave mode */ + SPI_MODE_MASTER = 1U, /**< Master mode */ } spi_mode_t; /** * @brief baud rate control */ -typedef enum -{ - SPI_BAUD_2 = 0, /**< fpclk/2 */ - SPI_BAUD_4 = 1, /**< fpclk/4 */ - SPI_BAUD_8 = 2, /**< fpclk/8 */ - SPI_BAUD_16 = 3, /**< fpclk/16 */ - SPI_BAUD_32 = 4, /**< fpclk/32 */ - SPI_BAUD_64 = 5, /**< fpclk/64 */ - SPI_BAUD_128 = 6, /**< fpclk/128 */ - SPI_BAUD_256 = 7, /**< fpclk/256 */ +typedef enum { + SPI_BAUD_2 = 0U, /**< fpclk/2 */ + SPI_BAUD_4 = 1U, /**< fpclk/4 */ + SPI_BAUD_8 = 2U, /**< fpclk/8 */ + SPI_BAUD_16 = 3U, /**< fpclk/16 */ + SPI_BAUD_32 = 4U, /**< fpclk/32 */ + SPI_BAUD_64 = 5U, /**< fpclk/64 */ + SPI_BAUD_128 = 6U, /**< fpclk/128 */ + SPI_BAUD_256 = 7U, /**< fpclk/256 */ } spi_baud_t; /** * @brief frame format */ -typedef enum -{ - SPI_FIRSTBIT_MSB = 0, /**< MSB transmitted first */ - SPI_FIRSTBIT_LSB = 1, /**< LSB transmitted first */ +typedef enum { + SPI_FIRSTBIT_MSB = 0U, /**< MSB transmitted first */ + SPI_FIRSTBIT_LSB = 1U, /**< LSB transmitted first */ } spi_firstbit_t; /** * @brief data frame format */ -typedef enum -{ - SPI_DATA_SIZE_8 = 0, /**< 8-bit data frame format is selected for transmission/reception */ - SPI_DATA_SIZE_16 = 1, /**< 16-bit data frame format is selected for transmission/reception */ +typedef enum { + SPI_DATA_SIZE_8 = 0U, /**< 8-bit data frame format is selected for transmission/reception */ + SPI_DATA_SIZE_16 = 1U, /**< 16-bit data frame format is selected for transmission/reception */ } spi_datasize_t; /** * @brief interrupt control */ -typedef enum -{ - SPI_IT_ERR = (1U << 5), /**< error interrupt */ - SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */ - SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */ +typedef enum { + SPI_IT_ERR = (1U << 5), /**< error interrupt */ + SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */ + SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */ } spi_it_t; /** * @brief interrupt flag */ -typedef enum -{ - SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */ - SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */ - SPI_IF_CRCERR = (1U << 4), /**< crc error flag */ - SPI_IF_MODF = (1U << 5), /**< mode fault */ - SPI_IF_OVE = (1U << 6), /**< overrun flag */ - SPI_IF_BUSY = (1U << 7), /**< busy flag */ +typedef enum { + SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */ + SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */ + SPI_IF_CRCERR = (1U << 4), /**< crc error flag */ + SPI_IF_MODF = (1U << 5), /**< mode fault */ + SPI_IF_OVE = (1U << 6), /**< overrun flag */ + SPI_IF_BUSY = (1U << 7), /**< busy flag */ } spi_flag_t; /** * @brief SPI error status */ -typedef enum -{ - SPI_ERROR_NONE = 0, /**< none */ - SPI_ERROR_MODF = 1, /**< mode fault */ - SPI_ERROR_CRC = 2, /**< crc error */ - SPI_ERROR_OVE = 4, /**< overrun error */ - SPI_ERROR_DMA = 8, /**< dma error */ - SPI_ERROR_FLAG = 0x10, /**< interrupt flag error */ +typedef enum { + SPI_ERROR_NONE = 0U, /**< none */ + SPI_ERROR_MODF = 1U, /**< mode fault */ + SPI_ERROR_CRC = 2U, /**< crc error */ + SPI_ERROR_OVE = 4U, /**< overrun error */ + SPI_ERROR_DMA = 8U, /**< dma error */ + SPI_ERROR_FLAG = 0x10U, /**< interrupt flag error */ } spi_error_t; @@ -137,104 +128,97 @@ typedef enum /** * @brief SPI state structures definition */ -typedef enum -{ - SPI_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - SPI_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - SPI_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - SPI_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */ - SPI_STATE_BUSY_RX = 0x21, /**< receive is ongoing */ - SPI_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */ - SPI_STATE_TIMEOUT = 0x03, /**< Timeout state */ - SPI_STATE_ERROR = 0x04, /**< Error */ +typedef enum { + SPI_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + SPI_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + SPI_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + SPI_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */ + SPI_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */ + SPI_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */ + SPI_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + SPI_STATE_ERROR = 0x04U, /**< Error */ } spi_state_t; /** * @brief SPI status definition */ -typedef enum -{ - SPI_STATUS_RXBNE = (1U << 0), /**< Receive not empty status */ - SPI_STATUS_TXBE = (1U << 1), /**< Transmit empty status */ - SPI_STATUS_CRCERR = (1U << 4), /**< CRC error status */ - SPI_STATUS_MODEERR = (1U << 5), /**< Mode error status */ - SPI_STATUS_OVERR = (1U << 6), /**< Overflow status */ - SPI_STATUS_BUSY = (1U << 7), /**< Busy status */ +typedef enum { + SPI_STATUS_RXBNE = (1U << 0), /**< Receive not empty status */ + SPI_STATUS_TXBE = (1U << 1), /**< Transmit empty status */ + SPI_STATUS_CRCERR = (1U << 4), /**< CRC error status */ + SPI_STATUS_MODEERR = (1U << 5), /**< Mode error status */ + SPI_STATUS_OVERR = (1U << 6), /**< Overflow status */ + SPI_STATUS_BUSY = (1U << 7), /**< Busy status */ } spi_status_t; /** * @brief SPI direction definition */ -typedef enum -{ - SPI_DIRECTION_2LINES = 0, /**< 2 lines */ - SPI_DIRECTION_2LINES_RXONLY = 1, /**< 2 lines only rx */ - SPI_DIRECTION_1LINE = 2, /**< 1 line */ - SPI_DIRECTION_1LINE_RX = 3, /**< 1 line only rx */ +typedef enum { + SPI_DIRECTION_2LINES = 0U, /**< 2 lines */ + SPI_DIRECTION_2LINES_RXONLY = 1U, /**< 2 lines only rx */ + SPI_DIRECTION_1LINE = 2U, /**< 1 line */ + SPI_DIRECTION_1LINE_RX = 3U, /**< 1 line only rx */ } spi_direction_t; /** * @brief SPI dma request definition */ -typedef enum -{ - SPI_DMA_REQ_TX = 0, /**< TX dma request */ - SPI_DMA_REQ_RX = 1, /**< RX dma request */ +typedef enum { + SPI_DMA_REQ_TX = 0U, /**< TX dma request */ + SPI_DMA_REQ_RX = 1U, /**< RX dma request */ } spi_dma_req_t; /** * @brief SPI TXE/RXNE status definition */ -typedef enum -{ - SPI_SR_TXBE = 0, /**< SR.TXE set */ - SPI_SR_RXBNE = 1, /**< SR.RXNE set */ - SPI_SR_TXBE_RXBNE = 2, /**< SR.TXE and SR.RXNE set */ +typedef enum { + SPI_SR_TXBE = 0U, /**< SR.TXE set */ + SPI_SR_RXBNE = 1U, /**< SR.RXNE set */ + SPI_SR_TXBE_RXBNE = 2U, /**< SR.TXE and SR.RXNE set */ } spi_sr_status_t; /** * @brief SPI init structure definition */ -typedef struct -{ - spi_mode_t mode; /**< SPI mode */ - spi_direction_t dir; /**< SPI direction */ - spi_datasize_t data_size; /**< SPI data size */ - spi_baud_t baud; /**< SPI baudrate prescaler */ - spi_cpha_t phase; /**< SPI clock phase */ - spi_cpol_t polarity; /**< SPI clock polarity */ - spi_firstbit_t first_bit; /**< SPI first bit */ - type_func_t ss_en; /**< SPI ssm enable or disable */ - type_func_t crc_calc; /**< SPI crc calculation */ - uint16_t crc_poly; /**< SPI crc polynomial */ +typedef struct { + spi_mode_t mode; /**< SPI mode */ + spi_direction_t dir; /**< SPI direction */ + spi_datasize_t data_size; /**< SPI data size */ + spi_baud_t baud; /**< SPI baudrate prescaler */ + spi_cpha_t phase; /**< SPI clock phase */ + spi_cpol_t polarity; /**< SPI clock polarity */ + spi_firstbit_t first_bit; /**< SPI first bit */ + type_func_t ss_en; /**< SPI ssm enable or disable */ + type_func_t crc_calc; /**< SPI crc calculation */ + uint16_t crc_poly; /**< SPI crc polynomial */ } spi_init_t; /** * @brief SPI handle structure definition */ -typedef struct spi_handle_s -{ - SPI_TypeDef *perh; /**< SPI registers base address */ - spi_init_t init; /**< SPI communication parameters */ - uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */ - uint16_t tx_size; /**< SPI Tx transfer size */ - uint16_t tx_count; /**< SPI Tx transfer counter */ - uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */ - uint16_t rx_size; /**< SPI Rx Transfer size */ - uint16_t rx_count; /**< SPI Rx Transfer Counter */ +typedef struct spi_handle_s { + SPI_TypeDef *perh; /**< SPI registers base address */ + spi_init_t init; /**< SPI communication parameters */ + uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */ + uint16_t tx_size; /**< SPI Tx transfer size */ + uint16_t tx_count; /**< SPI Tx transfer counter */ + uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */ + uint16_t rx_size; /**< SPI Rx Transfer size */ + uint16_t rx_count; /**< SPI Rx Transfer Counter */ #ifdef ALD_DMA - dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */ + dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */ #endif - lock_state_t lock; /**< Locking object */ - spi_state_t state; /**< SPI communication state */ - uint32_t err_code; /**< SPI error code */ - - void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */ - void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */ - void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */ + lock_state_t lock; /**< Locking object */ + spi_state_t state; /**< SPI communication state */ + uint32_t err_code; /**< SPI error code */ + + void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */ + void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */ + void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */ } spi_handle_t; /** * @} @@ -247,10 +231,10 @@ typedef struct spi_handle_s #define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS)) #define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS)) #define SPI_CRC_RESET(x) \ - do { \ - CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ - SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ - } while (0) +do { \ + CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ + SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ +} while (0) #define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) #define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) #define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) @@ -268,9 +252,12 @@ typedef struct spi_handle_s /** @defgroup SPI_Private_Macros SPI Private Macros * @{ */ -#define IS_SPI(x) (((x) == SPI0) || \ - ((x) == SPI1) || \ - ((x) == SPI2)) +#if defined(ES32F065x) || defined(ES32F033x) +#define IS_SPI(x) (((x) == SPI0) || ((x) == SPI1)) +#endif +#if defined(ES32F093x) +#define IS_SPI(x) (((x) == SPI0) || ((x) == SPI1) || ((x) == SPI2)) +#endif #define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \ ((x) == SPI_CPHA_SECOND)) #define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \ @@ -286,20 +273,22 @@ typedef struct spi_handle_s ((x) == SPI_BAUD_128) || \ ((x) == SPI_BAUD_256)) #define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \ - ((x) == SPI_DATA_SIZE_16)) + ((x) == SPI_DATA_SIZE_16)) +#define IS_SPI_FIRSTBIT(x) (((x) == SPI_FIRSTBIT_MSB) || \ + ((x) == SPI_FIRSTBIT_LSB)) #define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \ - ((x) == SPI_BID_TX)) + ((x) == SPI_BID_TX)) #define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \ - ((x) == SPI_BIDMODE_SOLE)) + ((x) == SPI_BIDMODE_SOLE)) #define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \ - ((x) == SPI_DIRECTION_2LINES_RXONLY) || \ - ((x) == SPI_DIRECTION_1LINE) || \ - ((x) == SPI_DIRECTION_1LINE_RX)) + ((x) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((x) == SPI_DIRECTION_1LINE) || \ + ((x) == SPI_DIRECTION_1LINE_RX)) #define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \ - ((x) == SPI_DMA_REQ_RX)) + ((x) == SPI_DMA_REQ_RX)) #define IS_SPI_SR_STATUS(x) (((x) == SPI_SR_TXBE) || \ - ((x) == SPI_SR_RXBNE) || \ - ((x) == SPI_SR_TXBE_RXBNE)) + ((x) == SPI_SR_RXBNE) || \ + ((x) == SPI_SR_TXBE_RXBNE)) #define IS_SPI_IT(x) (((x) == SPI_IT_ERR) || \ ((x) == SPI_IT_RXBNE) || \ ((x) == SPI_IT_TXBE)) @@ -310,11 +299,11 @@ typedef struct spi_handle_s ((x) == SPI_IF_OVE) || \ ((x) == SPI_IF_BUSY)) #define IS_SPI_STATUS(x) (((x) == SPI_STATUS_RXBNE) || \ - ((x) == SPI_STATUS_TXBE) || \ - ((x) == SPI_STATUS_CRCERR) || \ - ((x) == SPI_STATUS_MODEERR) || \ - ((x) == SPI_STATUS_OVERR) || \ - ((x) == SPI_STATUS_BUSY)) + ((x) == SPI_STATUS_TXBE) || \ + ((x) == SPI_STATUS_CRCERR) || \ + ((x) == SPI_STATUS_MODEERR) || \ + ((x) == SPI_STATUS_OVERR) || \ + ((x) == SPI_STATUS_BUSY)) /** * @} */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_syscfg.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_syscfg.h index d173be011f324fc1bfbb603fbef600f7f14bdebe..35844c887edf1c20bb2292ccaecdedc06fa0745a 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_syscfg.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_syscfg.h @@ -18,7 +18,7 @@ #define __ALD_SYSCFG_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -36,33 +36,33 @@ extern "C" { /** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros * @{ */ -#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0) -#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996) +#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0U) +#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996U) #define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK) #define BOOT_FROM_BOOT_ROM() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define BOOT_FROM_BOOT_FLASH() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define BOOT_FROM_FLASH() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) /** * @} */ @@ -73,20 +73,18 @@ extern "C" { */ __STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status) { - SYSCFG_UNLOCK(); - - if (status) - { - MODIFY_REG(SYSCFG->VTOR, SYSCFG_VTOR_VTO_MSK, (offset & ~0x3F)); - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK); - } - else - { - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK); - } - - SYSCFG_LOCK(); - return; + SYSCFG_UNLOCK(); + + if (status) { + MODIFY_REG(SYSCFG->VTOR, SYSCFG_VTOR_VTO_MSK, (offset & ~0x3FU)); + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK); + } + else { + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK); + } + + SYSCFG_LOCK(); + return; } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_timer.h index 9fe5ee6d6445ab35e2f8e49becf616b63f24c3c9..538fc0ca0b064ae745aaf0275fe9e0fef2046bf3 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_timer.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_timer.h @@ -19,7 +19,7 @@ #define __ALD_TIMER_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -40,527 +40,488 @@ extern "C" { /** * @brief TIMER counter mode */ -typedef enum -{ - TIMER_CNT_MODE_UP = 0, /**< Counter mode up */ - TIMER_CNT_MODE_DOWN = 1, /**< Counter mode down */ - TIMER_CNT_MODE_CENTER1 = 2, /**< Counter mode center1 */ - TIMER_CNT_MODE_CENTER2 = 3, /**< Counter mode center2 */ - TIMER_CNT_MODE_CENTER3 = 4, /**< Counter mode center3 */ +typedef enum { + TIMER_CNT_MODE_UP = 0U, /**< Counter mode up */ + TIMER_CNT_MODE_DOWN = 1U, /**< Counter mode down */ + TIMER_CNT_MODE_CENTER1 = 2U, /**< Counter mode center1 */ + TIMER_CNT_MODE_CENTER2 = 3U, /**< Counter mode center2 */ + TIMER_CNT_MODE_CENTER3 = 4U, /**< Counter mode center3 */ } timer_cnt_mode_t; /** * @brief TIMER clock division */ -typedef enum -{ - TIMER_CLOCK_DIV1 = 0, /**< No prescaler is used */ - TIMER_CLOCK_DIV2 = 1, /** Clock is divided by 2 */ - TIMER_CLOCK_DIV4 = 2, /** Clock is divided by 4 */ +typedef enum { + TIMER_CLOCK_DIV1 = 0U, /**< No prescaler is used */ + TIMER_CLOCK_DIV2 = 1U, /** Clock is divided by 2 */ + TIMER_CLOCK_DIV4 = 2U, /** Clock is divided by 4 */ } timer_clock_division_t; /** * @brief TIMER output compare and PWM modes */ -typedef enum -{ - TIMER_OC_MODE_TIMERING = 0, /**< Output compare mode is timering */ - TIMER_OC_MODE_ACTIVE = 1, /**< Output compare mode is active */ - TIMER_OC_MODE_INACTIVE = 2, /**< Output compare mode is inactive */ - TIMER_OC_MODE_TOGGLE = 3, /**< Output compare mode is toggle */ - TIMER_OC_MODE_FORCE_INACTIVE = 4, /**< Output compare mode is force inactive */ - TIMER_OC_MODE_FORCE_ACTIVE = 5, /**< Output compare mode is force active */ - TIMER_OC_MODE_PWM1 = 6, /**< Output compare mode is pwm1 */ - TIMER_OC_MODE_PWM2 = 7, /**< Output compare mode is pwm2 */ +typedef enum { + TIMER_OC_MODE_TIMERING = 0U, /**< Output compare mode is timering */ + TIMER_OC_MODE_ACTIVE = 1U, /**< Output compare mode is active */ + TIMER_OC_MODE_INACTIVE = 2U, /**< Output compare mode is inactive */ + TIMER_OC_MODE_TOGGLE = 3U, /**< Output compare mode is toggle */ + TIMER_OC_MODE_FORCE_INACTIVE = 4U, /**< Output compare mode is force inactive */ + TIMER_OC_MODE_FORCE_ACTIVE = 5U, /**< Output compare mode is force active */ + TIMER_OC_MODE_PWM1 = 6U, /**< Output compare mode is pwm1 */ + TIMER_OC_MODE_PWM2 = 7U, /**< Output compare mode is pwm2 */ } timer_oc_mode_t; /** * @brief TIMER output compare polarity */ -typedef enum -{ - TIMER_OC_POLARITY_HIGH = 0, /**< Output compare polarity is high */ - TIMER_OC_POLARITY_LOW = 1, /**< Output compare polarity is low */ +typedef enum { + TIMER_OC_POLARITY_HIGH = 0U, /**< Output compare polarity is high */ + TIMER_OC_POLARITY_LOW = 1U, /**< Output compare polarity is low */ } timer_oc_polarity_t; /** * @brief TIMER complementary output compare polarity */ -typedef enum -{ - TIMER_OCN_POLARITY_HIGH = 0, /**< Complementary output compare polarity is high */ - TIMER_OCN_POLARITY_LOW = 1, /**< Complementary output compare polarity is low */ +typedef enum { + TIMER_OCN_POLARITY_HIGH = 0U, /**< Complementary output compare polarity is high */ + TIMER_OCN_POLARITY_LOW = 1U, /**< Complementary output compare polarity is low */ } timer_ocn_polarity_t; /** * @brief TIMER output compare idle state */ -typedef enum -{ - TIMER_OC_IDLE_RESET = 0, /**< Output compare idle state is reset */ - TIMER_OC_IDLE_SET = 1, /**< Output compare idle state is set */ +typedef enum { + TIMER_OC_IDLE_RESET = 0U, /**< Output compare idle state is reset */ + TIMER_OC_IDLE_SET = 1U, /**< Output compare idle state is set */ } timer_oc_idle_t; /** * @brief TIMER complementary output compare idle state */ -typedef enum -{ - TIMER_OCN_IDLE_RESET = 0, /**< Complementary output compare idle state is reset */ - TIMER_OCN_IDLE_SET = 1, /**< Complementary output compare idle state is set */ +typedef enum { + TIMER_OCN_IDLE_RESET = 0U, /**< Complementary output compare idle state is reset */ + TIMER_OCN_IDLE_SET = 1U, /**< Complementary output compare idle state is set */ } timer_ocn_idle_t; /** * @brief TIMER channel */ -typedef enum -{ - TIMER_CHANNEL_1 = 0, /**< Channel 1 */ - TIMER_CHANNEL_2 = 1, /**< Channel 2 */ - TIMER_CHANNEL_3 = 2, /**< Channel 3 */ - TIMER_CHANNEL_4 = 4, /**< Channel 4 */ - TIMER_CHANNEL_ALL = 0xF, /**< All channel */ +typedef enum { + TIMER_CHANNEL_1 = 0U, /**< Channel 1 */ + TIMER_CHANNEL_2 = 1U, /**< Channel 2 */ + TIMER_CHANNEL_3 = 2U, /**< Channel 3 */ + TIMER_CHANNEL_4 = 4U, /**< Channel 4 */ + TIMER_CHANNEL_ALL = 0xFU, /**< All channel */ } timer_channel_t; /** * @brief TIMER one pulse mode */ -typedef enum -{ - TIMER_OP_MODE_REPEAT = 0, /**< Repetitive */ - TIMER_OP_MODE_SINGLE = 1, /**< single */ +typedef enum { + TIMER_OP_MODE_REPEAT = 0U, /**< Repetitive */ + TIMER_OP_MODE_SINGLE = 1U, /**< single */ } timer_op_mode_t; /** * @brief TIMER one pulse output channel */ -typedef enum -{ - TIMER_OP_OUTPUT_CHANNEL_1 = 0, /**< One pulse output channal 1 */ - TIMER_OP_OUTPUT_CHANNEL_2 = 1, /**< One pulse output channal 2 */ +typedef enum { + TIMER_OP_OUTPUT_CHANNEL_1 = 0U, /**< One pulse output channal 1 */ + TIMER_OP_OUTPUT_CHANNEL_2 = 1U, /**< One pulse output channal 2 */ } timer_op_output_channel_t; /** * @brief TIMER time base configuration structure definition */ -typedef struct -{ - uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ - timer_cnt_mode_t mode; /**< Specifies the counter mode. */ - uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ - timer_clock_division_t clk_div; /**< Specifies the clock division.*/ - uint32_t re_cnt; /**< Specifies the repetition counter value. */ +typedef struct { + uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ + timer_cnt_mode_t mode; /**< Specifies the counter mode. */ + uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ + timer_clock_division_t clk_div; /**< Specifies the clock division.*/ + uint32_t re_cnt; /**< Specifies the repetition counter value. */ } timer_base_init_t; /** * @brief TIMER output compare configuration structure definition */ -typedef struct -{ - timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ - uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ - timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ - timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ - type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ - timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ - timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ +typedef struct { + timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ + uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ + timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ + timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ + type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ + timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ + timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ } timer_oc_init_t; /** * @brief State structures definition */ -typedef enum -{ - TIMER_STATE_RESET = 0x00, /**< Peripheral not yet initialized or disabled */ - TIMER_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - TIMER_STATE_BUSY = 0x02, /**< An internal process is ongoing */ - TIMER_STATE_TIMEREOUT = 0x03, /**< Timeout state */ - TIMER_STATE_ERROR = 0x04, /**< Reception process is ongoing */ +typedef enum { + TIMER_STATE_RESET = 0x00U, /**< Peripheral not yet initialized or disabled */ + TIMER_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + TIMER_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ + TIMER_STATE_TIMEREOUT = 0x03U, /**< Timeout state */ + TIMER_STATE_ERROR = 0x04U, /**< Reception process is ongoing */ } timer_state_t; /** * @brief Active channel structures definition */ -typedef enum -{ - TIMER_ACTIVE_CHANNEL_1 = 0x01, /**< The active channel is 1 */ - TIMER_ACTIVE_CHANNEL_2 = 0x02, /**< The active channel is 2 */ - TIMER_ACTIVE_CHANNEL_3 = 0x04, /**< The active channel is 3 */ - TIMER_ACTIVE_CHANNEL_4 = 0x08, /**< The active channel is 4 */ - TIMER_ACTIVE_CHANNEL_CLEARED = 0x00, /**< All active channels cleared */ +typedef enum { + TIMER_ACTIVE_CHANNEL_1 = 0x01U, /**< The active channel is 1 */ + TIMER_ACTIVE_CHANNEL_2 = 0x02U, /**< The active channel is 2 */ + TIMER_ACTIVE_CHANNEL_3 = 0x04U, /**< The active channel is 3 */ + TIMER_ACTIVE_CHANNEL_4 = 0x08U, /**< The active channel is 4 */ + TIMER_ACTIVE_CHANNEL_CLEARED = 0x00U, /**< All active channels cleared */ } timer_active_channel_t; /** * @brief TIMER time base handle structure definition */ -typedef struct timer_handle_s -{ - TIMER_TypeDef *perh; /**< Register base address */ - timer_base_init_t init; /**< TIMER Time Base required parameters */ - timer_active_channel_t ch; /**< Active channel */ - lock_state_t lock; /**< Locking object */ - timer_state_t state; /**< TIMER operation state */ - - void (*period_elapse_cbk)(struct timer_handle_s *arg); /**< Period elapse callback */ - void (*delay_elapse_cbk)(struct timer_handle_s *arg); /**< Delay_elapse callback */ - void (*capture_cbk)(struct timer_handle_s *arg); /**< Capture callback */ - void (*pwm_pulse_finish_cbk)(struct timer_handle_s *arg); /**< PWM_pulse_finish callback */ - void (*trigger_cbk)(struct timer_handle_s *arg); /**< Trigger callback */ - void (*break_cbk)(struct timer_handle_s *arg); /**< Break callback */ - void (*com_cbk)(struct timer_handle_s *arg); /**< commutation callback */ - void (*error_cbk)(struct timer_handle_s *arg); /**< Error callback */ +typedef struct timer_handle_s { + TIMER_TypeDef *perh; /**< Register base address */ + timer_base_init_t init; /**< TIMER Time Base required parameters */ + timer_active_channel_t ch; /**< Active channel */ + lock_state_t lock; /**< Locking object */ + timer_state_t state; /**< TIMER operation state */ + +#ifdef ALD_DMA + dma_handle_t hdma1; /**< Timer DMA handle parameters */ + dma_handle_t hdma2; +#endif + + void (*period_elapse_cbk)(struct timer_handle_s *arg); /**< Period elapse callback */ + void (*delay_elapse_cbk)(struct timer_handle_s *arg); /**< Delay_elapse callback */ + void (*capture_cbk)(struct timer_handle_s *arg); /**< Capture callback */ + void (*pwm_pulse_finish_cbk)(struct timer_handle_s *arg); /**< PWM_pulse_finish callback */ + void (*trigger_cbk)(struct timer_handle_s *arg); /**< Trigger callback */ + void (*break_cbk)(struct timer_handle_s *arg); /**< Break callback */ + void (*com_cbk)(struct timer_handle_s *arg); /**< commutation callback */ + void (*error_cbk)(struct timer_handle_s *arg); /**< Error callback */ } timer_handle_t; /** * @brief TIMER encoder mode */ -typedef enum -{ - TIMER_ENC_MODE_TI1 = 1, /**< encoder mode 1 */ - TIMER_ENC_MODE_TI2 = 2, /**< encoder mode 2 */ - TIMER_ENC_MODE_TI12 = 3, /**< encoder mode 3 */ +typedef enum { + TIMER_ENC_MODE_TI1 = 1U, /**< encoder mode 1 */ + TIMER_ENC_MODE_TI2 = 2U, /**< encoder mode 2 */ + TIMER_ENC_MODE_TI12 = 3U, /**< encoder mode 3 */ } timer_encoder_mode_t; /** * @brief TIMER input capture polarity */ -typedef enum -{ - TIMER_IC_POLARITY_RISE = 0, /**< Input capture polarity rising */ - TIMER_IC_POLARITY_FALL = 1, /**< Input capture polarity falling */ +typedef enum { + TIMER_IC_POLARITY_RISE = 0U, /**< Input capture polarity rising */ + TIMER_IC_POLARITY_FALL = 1U, /**< Input capture polarity falling */ } timer_ic_polarity_t; /** *@brief TIMER input capture selection */ -typedef enum -{ - TIMER_IC_SEL_DIRECT = 1, /**< IC1 -- TI1 */ - TIMER_IC_SEL_INDIRECT = 2, /**< IC1 -- TI2 */ - TIMER_IC_SEL_TRC = 3, /**< IC1 -- TRC */ +typedef enum { + TIMER_IC_SEL_DIRECT = 1U, /**< IC1 -- TI1 */ + TIMER_IC_SEL_INDIRECT = 2U, /**< IC1 -- TI2 */ + TIMER_IC_SEL_TRC = 3U, /**< IC1 -- TRC */ } timer_ic_select_t; /** * @brief TIMER input capture prescaler */ -typedef enum -{ - TIMER_IC_PSC_DIV1 = 0, /**< Capture performed once every 1 events */ - TIMER_IC_PSC_DIV2 = 1, /**< Capture performed once every 2 events */ - TIMER_IC_PSC_DIV4 = 2, /**< Capture performed once every 4 events */ - TIMER_IC_PSC_DIV8 = 3, /**< Capture performed once every 4 events */ +typedef enum { + TIMER_IC_PSC_DIV1 = 0U, /**< Capture performed once every 1 events */ + TIMER_IC_PSC_DIV2 = 1U, /**< Capture performed once every 2 events */ + TIMER_IC_PSC_DIV4 = 2U, /**< Capture performed once every 4 events */ + TIMER_IC_PSC_DIV8 = 3U, /**< Capture performed once every 4 events */ } timer_ic_prescaler_t; /** * @brief TIMER encoder configuration structure definition */ -typedef struct -{ - timer_encoder_mode_t mode; /**< Specifies the encoder mode */ - timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t ic1_sel; /**< Specifies the input */ - timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ - uint32_t ic1_filter; /**< Specifies the input capture filter */ - timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t ic2_sel; /**< Specifies the input */ - timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ - uint32_t ic2_filter; /**< Specifies the input capture filter */ +typedef struct { + timer_encoder_mode_t mode; /**< Specifies the encoder mode */ + timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t ic1_sel; /**< Specifies the input */ + timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic1_filter; /**< Specifies the input capture filter */ + timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t ic2_sel; /**< Specifies the input */ + timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic2_filter; /**< Specifies the input capture filter */ } timer_encoder_init_t; /** * @brief TIMER input capture configuration structure definition */ -typedef struct -{ - timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t sel; /**< Specifies the input */ - timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ - uint32_t filter; /**< Specifies the input capture filter */ +typedef struct { + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t sel; /**< Specifies the input */ + timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter */ } timer_ic_init_t; /** * @brief TIMER one pulse mode configuration structure definition */ -typedef struct -{ - timer_oc_mode_t mode; /**< Specifies the TIMER mode */ - uint16_t pulse; /**< Specifies the pulse value */ - timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ - timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ - timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ - timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ - timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t sel; /**< Specifies the input */ - uint32_t filter; /**< Specifies the input capture filter */ +typedef struct { + timer_oc_mode_t mode; /**< Specifies the TIMER mode */ + uint16_t pulse; /**< Specifies the pulse value */ + timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ + timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ + timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t sel; /**< Specifies the input */ + uint32_t filter; /**< Specifies the input capture filter */ } timer_one_pulse_init_t; /** @brief TIMER clear input source */ -typedef enum -{ - TIMER_INPUT_NONE = 0, /**< Clear input none */ - TIMER_INPUT_ETR = 1, /**< Clear input etr */ +typedef enum { + TIMER_INPUT_NONE = 0U, /**< Clear input none */ + TIMER_INPUT_ETR = 1U, /**< Clear input etr */ } timer_clear_input_source_t; /** @brief TIMER clear input polarity */ -typedef enum -{ - TIMER_POLARITY_NO_INV = 0, /**< Polarity for ETRx pin */ - TIMER_POLARITY_INV = 1, /**< Polarity for ETRx pin */ +typedef enum { + TIMER_POLARITY_NO_INV = 0U, /**< Polarity for ETRx pin */ + TIMER_POLARITY_INV = 1U, /**< Polarity for ETRx pin */ } timer_clear_input_polarity_t; /** @brief TIMER clear input polarity */ -typedef enum -{ - TIMER_ETR_PSC_DIV1 = 0, /**< No prescaler is used */ - TIMER_ETR_PSC_DIV2 = 1, /**< ETR input source is divided by 2 */ - TIMER_ETR_PSC_DIV4 = 2, /**< ETR input source is divided by 4 */ - TIMER_ETR_PSC_DIV8 = 3, /**< ETR input source is divided by 8 */ +typedef enum { + TIMER_ETR_PSC_DIV1 = 0U, /**< No prescaler is used */ + TIMER_ETR_PSC_DIV2 = 1U, /**< ETR input source is divided by 2 */ + TIMER_ETR_PSC_DIV4 = 2U, /**< ETR input source is divided by 4 */ + TIMER_ETR_PSC_DIV8 = 3U, /**< ETR input source is divided by 8 */ } timer_etr_psc_t; /** * @brief TIMER clear input configuration handle structure definition */ -typedef struct -{ - type_func_t state; /**< TIMER clear Input state */ - timer_clear_input_source_t source; /**< TIMER clear Input sources */ - timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ - timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ - uint32_t filter; /**< TIMER Clear Input filter */ +typedef struct { + type_func_t state; /**< TIMER clear Input state */ + timer_clear_input_source_t source; /**< TIMER clear Input sources */ + timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ + timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ + uint32_t filter; /**< TIMER Clear Input filter */ } timer_clear_input_config_t; /** @brief TIMER clock source */ -typedef enum -{ - TIMER_SRC_ETRMODE2 = 0, /**< Clock source is etr mode2 */ - TIMER_SRC_INTER = 1, /**< Clock source is etr internal */ - TIMER_SRC_ITR0 = 2, /**< Clock source is etr itr0 */ - TIMER_SRC_ITR1 = 3, /**< Clock source is etr itr1 */ - TIMER_SRC_ITR2 = 4, /**< Clock source is etr itr2 */ - TIMER_SRC_ITR3 = 5, /**< Clock source is etr itr3 */ - TIMER_SRC_TI1ED = 6, /**< Clock source is etr ti1ed */ - TIMER_SRC_TI1 = 7, /**< Clock source is etr ti1 */ - TIMER_SRC_TI2 = 8, /**< Clock source is etr ti2 */ - TIMER_SRC_ETRMODE1 = 9, /**< Clock source is etr mode1 */ +typedef enum { + TIMER_SRC_ETRMODE2 = 0U, /**< Clock source is etr mode2 */ + TIMER_SRC_INTER = 1U, /**< Clock source is etr internal */ + TIMER_SRC_ITR0 = 2U, /**< Clock source is etr itr0 */ + TIMER_SRC_ITR1 = 3U, /**< Clock source is etr itr1 */ + TIMER_SRC_ITR2 = 4U, /**< Clock source is etr itr2 */ + TIMER_SRC_ITR3 = 5U, /**< Clock source is etr itr3 */ + TIMER_SRC_TI1ED = 6U, /**< Clock source is etr ti1ed */ + TIMER_SRC_TI1 = 7U, /**< Clock source is etr ti1 */ + TIMER_SRC_TI2 = 8U, /**< Clock source is etr ti2 */ + TIMER_SRC_ETRMODE1 = 9U, /**< Clock source is etr mode1 */ } timer_clock_source_t; /** @brief TIMER clock polarity */ -typedef enum -{ - TIMER_CLK_POLARITY_INV = 1, /**< Polarity for ETRx clock sources */ - TIMER_CLK_POLARITY_NO_INV = 0, /**< Polarity for ETRx clock sources */ - TIMER_CLK_POLARITY_RISE = 0, /**< Polarity for TIx clock sources */ - TIMER_CLK_POLARITY_FALL = 1, /**< Polarity for TIx clock sources */ - TIMER_CLK_POLARITY_BOTH = 3, /**< Polarity for TIx clock sources */ +typedef enum { + TIMER_CLK_POLARITY_INV = 1U, /**< Polarity for ETRx clock sources */ + TIMER_CLK_POLARITY_NO_INV = 0U, /**< Polarity for ETRx clock sources */ + TIMER_CLK_POLARITY_RISE = 0U, /**< Polarity for TIx clock sources */ + TIMER_CLK_POLARITY_FALL = 1U, /**< Polarity for TIx clock sources */ + TIMER_CLK_POLARITY_BOTH = 3U, /**< Polarity for TIx clock sources */ } timer_clock_polarity_t; /** * @brief TIMER clock config structure definition */ -typedef struct -{ - timer_clock_source_t source; /**< TIMER clock sources */ - timer_clock_polarity_t polarity; /**< TIMER clock polarity */ - timer_etr_psc_t psc; /**< TIMER clock prescaler */ - uint32_t filter; /**< TIMER clock filter */ +typedef struct { + timer_clock_source_t source; /**< TIMER clock sources */ + timer_clock_polarity_t polarity; /**< TIMER clock polarity */ + timer_etr_psc_t psc; /**< TIMER clock prescaler */ + uint32_t filter; /**< TIMER clock filter */ } timer_clock_config_t; /** * @brief TIMER slave mode */ -typedef enum -{ - TIMER_MODE_DISABLE = 0, /**< Slave mode is disable */ - TIMER_MODE_ENC1 = 1, /**< Slave mode is encoder1 */ - TIMER_MODE_ENC2 = 2, /**< Slave mode is encoder2 */ - TIMER_MODE_ENC3 = 3, /**< Slave mode is encoder3 */ - TIMER_MODE_RESET = 4, /**< Slave mode is reset */ - TIMER_MODE_GATED = 5, /**< Slave mode is gated */ - TIMER_MODE_TRIG = 6, /**< Slave mode is trigger */ - TIMER_MODE_EXTERNAL1 = 7, /**< Slave mode is external1 */ +typedef enum { + TIMER_MODE_DISABLE = 0U, /**< Slave mode is disable */ + TIMER_MODE_ENC1 = 1U, /**< Slave mode is encoder1 */ + TIMER_MODE_ENC2 = 2U, /**< Slave mode is encoder2 */ + TIMER_MODE_ENC3 = 3U, /**< Slave mode is encoder3 */ + TIMER_MODE_RESET = 4U, /**< Slave mode is reset */ + TIMER_MODE_GATED = 5U, /**< Slave mode is gated */ + TIMER_MODE_TRIG = 6U, /**< Slave mode is trigger */ + TIMER_MODE_EXTERNAL1 = 7U, /**< Slave mode is external1 */ } timer_slave_mode_t; /** * @brief TIMER ts definition */ -typedef enum -{ - TIMER_TS_ITR0 = 0, /**< ITR0 */ - TIMER_TS_ITR1 = 1, /**< ITR1 */ - TIMER_TS_ITR2 = 2, /**< ITR2 */ - TIMER_TS_ITR3 = 3, /**< ITR3 */ - TIMER_TS_TI1F_ED = 4, /**< TI1F_ED */ - TIMER_TS_TI1FP1 = 5, /**< TI1FP1 */ - TIMER_TS_TI2FP2 = 6, /**< TI2FP2 */ - TIMER_TS_ETRF = 7, /**< ETRF */ +typedef enum { + TIMER_TS_ITR0 = 0U, /**< ITR0 */ + TIMER_TS_ITR1 = 1U, /**< ITR1 */ + TIMER_TS_ITR2 = 2U, /**< ITR2 */ + TIMER_TS_ITR3 = 3U, /**< ITR3 */ + TIMER_TS_TI1F_ED = 4U, /**< TI1F_ED */ + TIMER_TS_TI1FP1 = 5U, /**< TI1FP1 */ + TIMER_TS_TI2FP2 = 6U, /**< TI2FP2 */ + TIMER_TS_ETRF = 7U, /**< ETRF */ } timer_ts_t; /** * @brief TIMER slave configuration structure definition */ -typedef struct -{ - timer_slave_mode_t mode; /**< Slave mode selection */ - timer_ts_t input; /**< Input Trigger source */ - timer_clock_polarity_t polarity; /**< Input Trigger polarity */ - timer_etr_psc_t psc; /**< Input trigger prescaler */ - uint32_t filter; /**< Input trigger filter */ +typedef struct { + timer_slave_mode_t mode; /**< Slave mode selection */ + timer_ts_t input; /**< Input Trigger source */ + timer_clock_polarity_t polarity; /**< Input Trigger polarity */ + timer_etr_psc_t psc; /**< Input trigger prescaler */ + uint32_t filter; /**< Input trigger filter */ } timer_slave_config_t; /** * @brief TIMER hall sensor configuretion structure definition */ -typedef struct -{ - timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ - timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ - uint32_t filter; /**< Specifies the input capture filter [0x0, 0xF] */ - uint32_t delay; /**< Specifies the pulse value to be loaded into the register [0x0, 0xFFFF] */ +typedef struct { + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter [0x0, 0xF] */ + uint32_t delay; /**< Specifies the pulse value to be loaded into the register [0x0, 0xFFFF] */ } timer_hall_sensor_init_t; /** * @brief TIMER lock level */ -typedef enum -{ - TIMER_LOCK_LEVEL_OFF = 0, /**< Lock off */ - TIMER_LOCK_LEVEL_1 = 1, /**< Lock level 1 */ - TIMER_LOCK_LEVEL_2 = 2, /**< Lock level 2 */ - TIMER_LOCK_LEVEL_3 = 3, /**< Lock level 3 */ +typedef enum { + TIMER_LOCK_LEVEL_OFF = 0U, /**< Lock off */ + TIMER_LOCK_LEVEL_1 = 1U, /**< Lock level 1 */ + TIMER_LOCK_LEVEL_2 = 2U, /**< Lock level 2 */ + TIMER_LOCK_LEVEL_3 = 3U, /**< Lock level 3 */ } timer_lock_level_t; /** * @brief TIMER break polarity */ -typedef enum -{ - TIMER_BREAK_POLARITY_LOW = 0, /**< LOW */ - TIMER_BREAK_POLARITY_HIGH = 1, /**< HIGH */ +typedef enum { + TIMER_BREAK_POLARITY_LOW = 0U, /**< LOW */ + TIMER_BREAK_POLARITY_HIGH = 1U, /**< HIGH */ } timer_break_polarity_t; /** * @brief TIMER break and dead time configuretion structure definition */ -typedef struct -{ - type_func_t off_run; /**< Enalbe/Disable off state in run mode */ - type_func_t off_idle; /**< Enalbe/Disable off state in idle mode */ - timer_lock_level_t lock_level; /**< Lock level */ - uint32_t dead_time; /**< Dead time, [0x0, 0xFF] */ - type_func_t break_state; /**< Break state */ - timer_break_polarity_t polarity; /**< Break input polarity */ - type_func_t auto_out; /**< Enalbe/Disable automatic output */ +typedef struct { + type_func_t off_run; /**< Enalbe/Disable off state in run mode */ + type_func_t off_idle; /**< Enalbe/Disable off state in idle mode */ + timer_lock_level_t lock_level; /**< Lock level */ + uint32_t dead_time; /**< Dead time, [0x0, 0xFF] */ + type_func_t break_state; /**< Break state */ + timer_break_polarity_t polarity; /**< Break input polarity */ + type_func_t auto_out; /**< Enalbe/Disable automatic output */ } timer_break_dead_time_t; /** * @brief TIMER commutation event channel configuretion structure definition */ -typedef struct -{ - type_func_t en; /**< Enalbe/Disable the channel */ - type_func_t n_en; /**< Enalbe/Disable the complementary channel */ - timer_oc_mode_t mode; /**< Mode of the channel */ +typedef struct { + type_func_t en; /**< Enalbe/Disable the channel */ + type_func_t n_en; /**< Enalbe/Disable the complementary channel */ + timer_oc_mode_t mode; /**< Mode of the channel */ } timer_channel_config_t; /** * @brief TIMER commutation event configuretion structure definition */ -typedef struct -{ - timer_channel_config_t ch[3]; /**< Configure of channel */ +typedef struct { + timer_channel_config_t ch[3]; /**< Configure of channel */ } timer_com_channel_config_t; /** * @brief TIMER master mode selection */ -typedef enum -{ - TIMER_TRGO_RESET = 0, /**< RESET */ - TIMER_TRGO_ENABLE = 1, /**< ENABLE */ - TIMER_TRGO_UPDATE = 2, /**< UPDATE */ - TIMER_TRGO_OC1 = 3, /**< OC1 */ - TIMER_TRGO_OC1REF = 4, /**< OC1REF */ - TIMER_TRGO_OC2REF = 5, /**< OC2REF */ - TIMER_TRGO_OC3REF = 6, /**< OC3REF */ - TIMER_TRGO_OC4REF = 7, /**< OC4REF */ +typedef enum { + TIMER_TRGO_RESET = 0U, /**< RESET */ + TIMER_TRGO_ENABLE = 1U, /**< ENABLE */ + TIMER_TRGO_UPDATE = 2U, /**< UPDATE */ + TIMER_TRGO_OC1 = 3U, /**< OC1 */ + TIMER_TRGO_OC1REF = 4U, /**< OC1REF */ + TIMER_TRGO_OC2REF = 5U, /**< OC2REF */ + TIMER_TRGO_OC3REF = 6U, /**< OC3REF */ + TIMER_TRGO_OC4REF = 7U, /**< OC4REF */ } timer_master_mode_sel_t; /** * @brief TIMER master configuretion structure definition */ -typedef struct -{ - timer_master_mode_sel_t sel; /**< Specifies the active edge of the input signal */ - type_func_t master_en; /**< Master/Slave mode selection */ +typedef struct { + timer_master_mode_sel_t sel; /**< Specifies the active edge of the input signal */ + type_func_t master_en; /**< Master/Slave mode selection */ } timer_master_config_t; /** * @brief Specifies the event source */ -typedef enum -{ - TIMER_SRC_UPDATE = (1U << 0), /**< Event source is update */ - TIMER_SRC_CC1 = (1U << 1), /**< Event source is channel1 */ - TIMER_SRC_CC2 = (1U << 2), /**< Event source is channel2 */ - TIMER_SRC_CC3 = (1U << 3), /**< Event source is channel3 */ - TIMER_SRC_CC4 = (1U << 4), /**< Event source is channel4 */ - TIMER_SRC_COM = (1U << 5), /**< Event source is compare */ - TIMER_SRC_TRIG = (1U << 6), /**< Event source is trigger */ - TIMER_SRC_BREAK = (1U << 7), /**< Event source is break */ +typedef enum { + TIMER_SRC_UPDATE = (1U << 0), /**< Event source is update */ + TIMER_SRC_CC1 = (1U << 1), /**< Event source is channel1 */ + TIMER_SRC_CC2 = (1U << 2), /**< Event source is channel2 */ + TIMER_SRC_CC3 = (1U << 3), /**< Event source is channel3 */ + TIMER_SRC_CC4 = (1U << 4), /**< Event source is channel4 */ + TIMER_SRC_COM = (1U << 5), /**< Event source is compare */ + TIMER_SRC_TRIG = (1U << 6), /**< Event source is trigger */ + TIMER_SRC_BREAK = (1U << 7), /**< Event source is break */ } timer_event_source_t; /** * @brief TIMER interrupt definition */ -typedef enum -{ - TIMER_IT_UPDATE = (1U << 0), /**< Update interrupt bit */ - TIMER_IT_CC1 = (1U << 1), /**< Channel1 interrupt bit */ - TIMER_IT_CC2 = (1U << 2), /**< Channel2 interrupt bit */ - TIMER_IT_CC3 = (1U << 3), /**< Channel3 interrupt bit */ - TIMER_IT_CC4 = (1U << 4), /**< Channel4 interrupt bit */ - TIMER_IT_COM = (1U << 5), /**< compare interrupt bit */ - TIMER_IT_TRIGGER = (1U << 6), /**< Trigger interrupt bit */ - TIMER_IT_BREAK = (1U << 7), /**< Break interrupt bit */ +typedef enum { + TIMER_IT_UPDATE = (1U << 0), /**< Update interrupt bit */ + TIMER_IT_CC1 = (1U << 1), /**< Channel1 interrupt bit */ + TIMER_IT_CC2 = (1U << 2), /**< Channel2 interrupt bit */ + TIMER_IT_CC3 = (1U << 3), /**< Channel3 interrupt bit */ + TIMER_IT_CC4 = (1U << 4), /**< Channel4 interrupt bit */ + TIMER_IT_COM = (1U << 5), /**< compare interrupt bit */ + TIMER_IT_TRIGGER = (1U << 6), /**< Trigger interrupt bit */ + TIMER_IT_BREAK = (1U << 7), /**< Break interrupt bit */ } timer_it_t; /** * @brief TIMER DMA request */ -typedef enum -{ - TIMER_DMA_UPDATE = (1U << 8), /**< DMA request from update */ - TIMER_DMA_CC1 = (1U << 9), /**< DMA request from channel1 */ - TIMER_DMA_CC2 = (1U << 10), /**< DMA request from channel2 */ - TIMER_DMA_CC3 = (1U << 11), /**< DMA request from channel3 */ - TIMER_DMA_CC4 = (1U << 12), /**< DMA request from channel4 */ - TIMER_DMA_COM = (1U << 13), /**< DMA request from compare */ - TIMER_DMA_TRIGGER = (1U << 14), /**< DMA request from trigger */ +typedef enum { + TIMER_DMA_UPDATE = (1U << 8), /**< DMA request from update */ + TIMER_DMA_CC1 = (1U << 9), /**< DMA request from channel1 */ + TIMER_DMA_CC2 = (1U << 10), /**< DMA request from channel2 */ + TIMER_DMA_CC3 = (1U << 11), /**< DMA request from channel3 */ + TIMER_DMA_CC4 = (1U << 12), /**< DMA request from channel4 */ + TIMER_DMA_COM = (1U << 13), /**< DMA request from compare */ + TIMER_DMA_TRIGGER = (1U << 14), /**< DMA request from trigger */ } timer_dma_req_t; /** * @brief TIMER flag definition */ -typedef enum -{ - TIMER_FLAG_UPDATE = (1U << 0), /**< Update interrupt flag */ - TIMER_FLAG_CC1 = (1U << 1), /**< Channel1 interrupt flag */ - TIMER_FLAG_CC2 = (1U << 2), /**< Channel2 interrupt flag */ - TIMER_FLAG_CC3 = (1U << 3), /**< Channel3 interrupt flag */ - TIMER_FLAG_CC4 = (1U << 4), /**< Channel4 interrupt flag */ - TIMER_FLAG_COM = (1U << 5), /**< Compare interrupt flag */ - TIMER_FLAG_TRIGGER = (1U << 6), /**< Trigger interrupt flag */ - TIMER_FLAG_BREAK = (1U << 7), /**< Break interrupt flag */ - TIMER_FLAG_CC1OF = (1U << 9), /**< Channel1 override state flag */ - TIMER_FLAG_CC2OF = (1U << 10), /**< Channel2 override state flag */ - TIMER_FLAG_CC3OF = (1U << 11), /**< Channel3 override state flag */ - TIMER_FLAG_CC4OF = (1U << 12), /**< Channel4 override state flag */ +typedef enum { + TIMER_FLAG_UPDATE = (1U << 0), /**< Update interrupt flag */ + TIMER_FLAG_CC1 = (1U << 1), /**< Channel1 interrupt flag */ + TIMER_FLAG_CC2 = (1U << 2), /**< Channel2 interrupt flag */ + TIMER_FLAG_CC3 = (1U << 3), /**< Channel3 interrupt flag */ + TIMER_FLAG_CC4 = (1U << 4), /**< Channel4 interrupt flag */ + TIMER_FLAG_COM = (1U << 5), /**< Compare interrupt flag */ + TIMER_FLAG_TRIGGER = (1U << 6), /**< Trigger interrupt flag */ + TIMER_FLAG_BREAK = (1U << 7), /**< Break interrupt flag */ + TIMER_FLAG_CC1OF = (1U << 9), /**< Channel1 override state flag */ + TIMER_FLAG_CC2OF = (1U << 10), /**< Channel2 override state flag */ + TIMER_FLAG_CC3OF = (1U << 11), /**< Channel3 override state flag */ + TIMER_FLAG_CC4OF = (1U << 12), /**< Channel4 override state flag */ } timer_flag_t; /** * @} @@ -591,11 +552,11 @@ typedef enum * @brief Disable the TIMER peripheral. */ #define TIMER_DISABLE(hperh) \ - do { \ - if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ - && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ - CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ - } while (0) +do { \ + if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ +} while (0) /** * @brief Disable the TIMER main output. @@ -603,21 +564,21 @@ typedef enum * all the CCx and CCxN channels have been disabled */ #define TIMER_MOE_DISABLE(hperh) \ - do { \ - if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ - && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ - CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ - } while (0) +do { \ + if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ +} while (0) /** * @brief Sets the TIMER autoreload register value on runtime without calling * another time any Init function. */ #define TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \ - do { \ - (handle)->perh->AR = (AUTORELOAD); \ - (handle)->init.period = (AUTORELOAD); \ - } while (0) +do { \ + (handle)->perh->AR = (AUTORELOAD); \ + (handle)->init.period = (AUTORELOAD); \ +} while (0) /** * @brief Gets the TIMER autoreload register value on runtime @@ -654,7 +615,7 @@ typedef enum * TIMER_CHANNEL_4 */ #define TIMER_CCx_ENABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ - (SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2)))))) +(SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2)))))) /** * @brief Disable channel @@ -666,7 +627,7 @@ typedef enum * TIMER_CHANNEL_4 */ #define TIMER_CCx_DISABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ - (CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2)))) +(CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2)))) /** * @brief Enable complementary channel @@ -706,55 +667,55 @@ typedef enum #define IS_ADTIMER_INSTANCE(x) ((x) == AD16C4T0) #define IS_TIMER_XOR_INSTANCE(x) (((x) == AD16C4T0) || ((x) == GP16C4T0)) #define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) #define IS_TIMER_CC2_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) + ((x) == GP16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) #define IS_TIMER_CC4_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C4T0)) + ((x) == GP16C4T0)) #define IS_TIMER_BREAK_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) #define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == AD16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == AD16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2)))) + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == AD16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2)))) #define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == AD16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) || \ - (((x) == GP16C2T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4)))) + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4)))) #define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == AD16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) #define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) #define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) #elif defined (ES32F033x) || defined (ES32F093x) @@ -770,128 +731,128 @@ typedef enum #define IS_ADTIMER_INSTANCE(x) ((x) == AD16C4T0) #define IS_TIMER_XOR_INSTANCE(x) (((x) == GP16C4T0) || ((x) == GP16C4T1)) #define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) #define IS_TIMER_CC2_INSTANCE(x) (((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1) || \ - ((x) == GP16C4T1)) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1) || \ + ((x) == GP16C4T1)) #define IS_TIMER_CC4_INSTANCE(x) (((x) == GP16C4T0) || \ - ((x) == GP16C4T1)) + ((x) == GP16C4T1)) #define IS_TIMER_BREAK_INSTANCE(x) (((x) == GP16C4T0)) #define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == GP16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C4T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2)))) + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2)))) #define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == GP16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) || \ - (((x) == GP16C2T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C4T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4)))) + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4)))) #define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) #define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) #define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) #endif #define IS_TIMER_COUNTER_MODE(x) (((x) == TIMER_CNT_MODE_UP) || \ - ((x) == TIMER_CNT_MODE_DOWN) || \ - ((x) == TIMER_CNT_MODE_CENTER1) || \ - ((x) == TIMER_CNT_MODE_CENTER2) || \ - ((x) == TIMER_CNT_MODE_CENTER3)) + ((x) == TIMER_CNT_MODE_DOWN) || \ + ((x) == TIMER_CNT_MODE_CENTER1) || \ + ((x) == TIMER_CNT_MODE_CENTER2) || \ + ((x) == TIMER_CNT_MODE_CENTER3)) #define IS_TIMER_CLOCK_DIVISION(x) (((x) == TIMER_CLOCK_DIV1) || \ - ((x) == TIMER_CLOCK_DIV2) || \ - ((x) == TIMER_CLOCK_DIV4)) + ((x) == TIMER_CLOCK_DIV2) || \ + ((x) == TIMER_CLOCK_DIV4)) #define IS_TIMER_PWM_MODE(x) (((x) == TIMER_OC_MODE_PWM1) || \ - ((x) == TIMER_OC_MODE_PWM2)) + ((x) == TIMER_OC_MODE_PWM2)) #define IS_TIMER_OC_MODE(x) (((x) == TIMER_OC_MODE_TIMERING) || \ - ((x) == TIMER_OC_MODE_ACTIVE) || \ - ((x) == TIMER_OC_MODE_INACTIVE) || \ - ((x) == TIMER_OC_MODE_TOGGLE) || \ - ((x) == TIMER_OC_MODE_FORCE_ACTIVE) || \ - ((x) == TIMER_OC_MODE_FORCE_INACTIVE) || \ - ((x) == TIMER_OC_MODE_PWM1) || \ - ((x) == TIMER_OC_MODE_PWM2)) + ((x) == TIMER_OC_MODE_ACTIVE) || \ + ((x) == TIMER_OC_MODE_INACTIVE) || \ + ((x) == TIMER_OC_MODE_TOGGLE) || \ + ((x) == TIMER_OC_MODE_FORCE_ACTIVE) || \ + ((x) == TIMER_OC_MODE_FORCE_INACTIVE) || \ + ((x) == TIMER_OC_MODE_PWM1) || \ + ((x) == TIMER_OC_MODE_PWM2)) #define IS_TIMER_OC_POLARITY(x) (((x) == TIMER_OC_POLARITY_HIGH) || \ - ((x) == TIMER_OC_POLARITY_LOW)) + ((x) == TIMER_OC_POLARITY_LOW)) #define IS_TIMER_OCN_POLARITY(x) (((x) == TIMER_OCN_POLARITY_HIGH) || \ - ((x) == TIMER_OCN_POLARITY_LOW)) + ((x) == TIMER_OCN_POLARITY_LOW)) #define IS_TIMER_OCIDLE_STATE(x) (((x) == TIMER_OC_IDLE_RESET) || \ - ((x) == TIMER_OC_IDLE_SET)) + ((x) == TIMER_OC_IDLE_SET)) #define IS_TIMER_OCNIDLE_STATE(x) (((x) == TIMER_OCN_IDLE_RESET) || \ - ((x) == TIMER_OCN_IDLE_SET)) + ((x) == TIMER_OCN_IDLE_SET)) #define IS_TIMER_CHANNELS(x) (((x) == TIMER_CHANNEL_1) || \ - ((x) == TIMER_CHANNEL_2) || \ - ((x) == TIMER_CHANNEL_3) || \ - ((x) == TIMER_CHANNEL_4) || \ - ((x) == TIMER_CHANNEL_ALL)) + ((x) == TIMER_CHANNEL_2) || \ + ((x) == TIMER_CHANNEL_3) || \ + ((x) == TIMER_CHANNEL_4) || \ + ((x) == TIMER_CHANNEL_ALL)) #define IS_TIMER_OP_MODE(x) (((x) == TIMER_OP_MODE_REPEAT) || \ - ((x) == TIMER_OP_MODE_SINGLE)) + ((x) == TIMER_OP_MODE_SINGLE)) #define IS_TIMER_OP_OUTPUT_CH(x) (((x) == TIMER_OP_OUTPUT_CHANNEL_1) || \ - ((x) == TIMER_OP_OUTPUT_CHANNEL_2)) + ((x) == TIMER_OP_OUTPUT_CHANNEL_2)) #define IS_TIMER_ENCODER_MODE(x) (((x) == TIMER_ENC_MODE_TI1) || \ - ((x) == TIMER_ENC_MODE_TI2) || \ - ((x) == TIMER_ENC_MODE_TI12)) + ((x) == TIMER_ENC_MODE_TI2) || \ + ((x) == TIMER_ENC_MODE_TI12)) #define IS_TIMER_IC_POLARITY(x) (((x) == TIMER_IC_POLARITY_RISE) || \ - ((x) == TIMER_IC_POLARITY_FALL)) + ((x) == TIMER_IC_POLARITY_FALL)) #define IS_TIMER_IC_SELECT(x) (((x) == TIMER_IC_SEL_DIRECT) || \ - ((x) == TIMER_IC_SEL_INDIRECT) || \ - ((x) == TIMER_IC_SEL_TRC)) + ((x) == TIMER_IC_SEL_INDIRECT) || \ + ((x) == TIMER_IC_SEL_TRC)) #define IS_TIMER_IC_PSC(x) (((x) == TIMER_IC_PSC_DIV1) || \ - ((x) == TIMER_IC_PSC_DIV2) || \ - ((x) == TIMER_IC_PSC_DIV4) || \ - ((x) == TIMER_IC_PSC_DIV8)) + ((x) == TIMER_IC_PSC_DIV2) || \ + ((x) == TIMER_IC_PSC_DIV4) || \ + ((x) == TIMER_IC_PSC_DIV8)) #define IS_TIMER_IC_FILTER(x) ((x) <= 0xF) #define IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF) #define IS_TIMER_CLEAR_INPUT_SOURCE(x) (((x) == TIMER_INPUT_NONE) || \ - ((x) == TIMER_INPUT_ETR)) + ((x) == TIMER_INPUT_ETR)) #define IS_TIMER_CLEAR_INPUT_POLARITY(x) (((x) == TIMER_POLARITY_NO_INV) || \ - ((x) == TIMER_POLARITY_INV)) + ((x) == TIMER_POLARITY_INV)) #define IS_TIMER_ETR_PSC(x) (((x) == TIMER_ETR_PSC_DIV1) || \ - ((x) == TIMER_ETR_PSC_DIV2) || \ - ((x) == TIMER_ETR_PSC_DIV4) || \ - ((x) == TIMER_ETR_PSC_DIV8)) + ((x) == TIMER_ETR_PSC_DIV2) || \ + ((x) == TIMER_ETR_PSC_DIV4) || \ + ((x) == TIMER_ETR_PSC_DIV8)) #define IS_TIMER_CLOCK_SOURCE(x) (((x) == TIMER_SRC_ETRMODE2) || \ - ((x) == TIMER_SRC_INTER) || \ - ((x) == TIMER_SRC_ITR0) || \ - ((x) == TIMER_SRC_ITR1) || \ - ((x) == TIMER_SRC_ITR2) || \ - ((x) == TIMER_SRC_ITR3) || \ - ((x) == TIMER_SRC_TI1ED) || \ - ((x) == TIMER_SRC_TI1) || \ - ((x) == TIMER_SRC_TI2) || \ - ((x) == TIMER_SRC_ETRMODE1)) + ((x) == TIMER_SRC_INTER) || \ + ((x) == TIMER_SRC_ITR0) || \ + ((x) == TIMER_SRC_ITR1) || \ + ((x) == TIMER_SRC_ITR2) || \ + ((x) == TIMER_SRC_ITR3) || \ + ((x) == TIMER_SRC_TI1ED) || \ + ((x) == TIMER_SRC_TI1) || \ + ((x) == TIMER_SRC_TI2) || \ + ((x) == TIMER_SRC_ETRMODE1)) #define IS_TIMER_CLOCK_POLARITY(x) (((x) == TIMER_CLK_POLARITY_INV) || \ - ((x) == TIMER_CLK_POLARITY_NO_INV) || \ - ((x) == TIMER_CLK_POLARITY_RISE) || \ - ((x) == TIMER_CLK_POLARITY_FALL) || \ - ((x) == TIMER_CLK_POLARITY_BOTH)) + ((x) == TIMER_CLK_POLARITY_NO_INV) || \ + ((x) == TIMER_CLK_POLARITY_RISE) || \ + ((x) == TIMER_CLK_POLARITY_FALL) || \ + ((x) == TIMER_CLK_POLARITY_BOTH)) #define IS_TIMER_SLAVE_MODE(x) (((x) == TIMER_MODE_DISABLE) || \ ((x) == TIMER_MODE_ENC1) || \ ((x) == TIMER_MODE_ENC2) || \ @@ -901,35 +862,35 @@ typedef enum ((x) == TIMER_MODE_TRIG) || \ ((x) == TIMER_MODE_EXTERNAL1)) #define IS_TIMER_EVENT_SOURCE(x) (((x) == TIMER_SRC_UPDATE) || \ - ((x) == TIMER_SRC_CC1) || \ - ((x) == TIMER_SRC_CC2) || \ - ((x) == TIMER_SRC_CC3) || \ - ((x) == TIMER_SRC_CC4) || \ - ((x) == TIMER_SRC_COM) || \ - ((x) == TIMER_SRC_TRIG) || \ - ((x) == TIMER_SRC_BREAK)) + ((x) == TIMER_SRC_CC1) || \ + ((x) == TIMER_SRC_CC2) || \ + ((x) == TIMER_SRC_CC3) || \ + ((x) == TIMER_SRC_CC4) || \ + ((x) == TIMER_SRC_COM) || \ + ((x) == TIMER_SRC_TRIG) || \ + ((x) == TIMER_SRC_BREAK)) #define IS_TIMER_TS(x) (((x) == TIMER_TS_ITR0) || \ - ((x) == TIMER_TS_ITR1) || \ - ((x) == TIMER_TS_ITR2) || \ - ((x) == TIMER_TS_ITR3) || \ - ((x) == TIMER_TS_TI1F_ED) || \ - ((x) == TIMER_TS_TI1FP1) || \ - ((x) == TIMER_TS_TI2FP2) || \ - ((x) == TIMER_TS_ETRF)) + ((x) == TIMER_TS_ITR1) || \ + ((x) == TIMER_TS_ITR2) || \ + ((x) == TIMER_TS_ITR3) || \ + ((x) == TIMER_TS_TI1F_ED) || \ + ((x) == TIMER_TS_TI1FP1) || \ + ((x) == TIMER_TS_TI2FP2) || \ + ((x) == TIMER_TS_ETRF)) #define IS_TIMER_CLOCK_LEVEL(x) (((x) == TIMER_LOCK_LEVEL_OFF) || \ ((x) == TIMER_LOCK_LEVEL_1) || \ ((x) == TIMER_LOCK_LEVEL_2) || \ ((x) == TIMER_LOCK_LEVEL_3)) #define IS_TIMER_BREAK_POLARITY(x) (((x) == TIMER_BREAK_POLARITY_LOW) || \ - ((x) == TIMER_BREAK_POLARITY_HIGH)) + ((x) == TIMER_BREAK_POLARITY_HIGH)) #define IS_TIMER_MASTER_MODE_SEL(x) (((x) == TIMER_TRGO_RESET) || \ - ((x) == TIMER_TRGO_ENABLE) || \ - ((x) == TIMER_TRGO_UPDATE) || \ - ((x) == TIMER_TRGO_OC1) || \ - ((x) == TIMER_TRGO_OC1REF) || \ - ((x) == TIMER_TRGO_OC2REF) || \ - ((x) == TIMER_TRGO_OC3REF) || \ - ((x) == TIMER_TRGO_OC4REF)) + ((x) == TIMER_TRGO_ENABLE) || \ + ((x) == TIMER_TRGO_UPDATE) || \ + ((x) == TIMER_TRGO_OC1) || \ + ((x) == TIMER_TRGO_OC1REF) || \ + ((x) == TIMER_TRGO_OC2REF) || \ + ((x) == TIMER_TRGO_OC3REF) || \ + ((x) == TIMER_TRGO_OC4REF)) #define IS_TIMER_IT(x) (((x) == TIMER_IT_UPDATE) || \ ((x) == TIMER_IT_CC1) || \ ((x) == TIMER_IT_CC2) || \ @@ -939,24 +900,24 @@ typedef enum ((x) == TIMER_IT_TRIGGER) || \ ((x) == TIMER_IT_BREAK)) #define IS_TIMER_DMA_REQ(x) (((x) == TIMER_DMA_UPDATE) || \ - ((x) == TIMER_DMA_CC1) || \ - ((x) == TIMER_DMA_CC2) || \ - ((x) == TIMER_DMA_CC3) || \ - ((x) == TIMER_DMA_CC4) || \ - ((x) == TIMER_DMA_COM) || \ - ((x) == TIMER_DMA_TRIGGER)) + ((x) == TIMER_DMA_CC1) || \ + ((x) == TIMER_DMA_CC2) || \ + ((x) == TIMER_DMA_CC3) || \ + ((x) == TIMER_DMA_CC4) || \ + ((x) == TIMER_DMA_COM) || \ + ((x) == TIMER_DMA_TRIGGER)) #define IS_TIMER_FLAG(x) (((x) == TIMER_FLAG_UPDATE) || \ - ((x) == TIMER_FLAG_CC1) || \ - ((x) == TIMER_FLAG_CC2) || \ - ((x) == TIMER_FLAG_CC3) || \ - ((x) == TIMER_FLAG_CC4) || \ - ((x) == TIMER_FLAG_COM) || \ - ((x) == TIMER_FLAG_TRIGGER) || \ - ((x) == TIMER_FLAG_BREAK) || \ - ((x) == TIMER_FLAG_CC1OF) || \ - ((x) == TIMER_FLAG_CC2OF) || \ - ((x) == TIMER_FLAG_CC3OF) || \ - ((x) == TIMER_FLAG_CC4OF)) + ((x) == TIMER_FLAG_CC1) || \ + ((x) == TIMER_FLAG_CC2) || \ + ((x) == TIMER_FLAG_CC3) || \ + ((x) == TIMER_FLAG_CC4) || \ + ((x) == TIMER_FLAG_COM) || \ + ((x) == TIMER_FLAG_TRIGGER) || \ + ((x) == TIMER_FLAG_BREAK) || \ + ((x) == TIMER_FLAG_CC1OF) || \ + ((x) == TIMER_FLAG_CC2OF) || \ + ((x) == TIMER_FLAG_CC3OF) || \ + ((x) == TIMER_FLAG_CC4OF)) /** * @} */ @@ -975,8 +936,8 @@ void ald_timer_base_stop(timer_handle_t *hperh); void ald_timer_base_start_by_it(timer_handle_t *hperh); void ald_timer_base_stop_by_it(timer_handle_t *hperh); #ifdef ALD_DMA -ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - uint16_t *buf, uint32_t len, uint8_t dma_ch); +ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_base_stop_by_dma(timer_handle_t *hperh); #endif /** @@ -994,7 +955,7 @@ void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); + uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1015,7 +976,7 @@ void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); + uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1033,7 +994,7 @@ void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); + uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1064,8 +1025,8 @@ void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, - uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2); + uint16_t *buf1, uint16_t *buf2, uint32_t len, + uint8_t dma_ch1, uint8_t dma_ch2); void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1082,8 +1043,8 @@ void ald_timer_hall_sensor_stop(timer_handle_t *hperh); void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh); void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh); #ifdef ALD_DMA -ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - uint16_t *buf, uint32_t len, uint8_t dma_ch); +ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh); #endif /** @@ -1099,8 +1060,8 @@ void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA -ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1116,8 +1077,8 @@ void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA -ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1140,10 +1101,10 @@ void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @{ */ /* Control functions */ -ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch); -ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch); +ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch); +ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch); ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, - timer_channel_t ch_out, timer_channel_t ch_in); + timer_channel_t ch_out, timer_channel_t ch_in); ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch); ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config); ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select); diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_trng.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_trng.h index a1142838eb5fe1e247e0e5fea1e0fc93381d77ae..635cb1a90abfb3f21ad0f6ecc9b4e60ebda49a97 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_trng.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_trng.h @@ -38,93 +38,85 @@ extern "C" { /** * @brief Data width */ -typedef enum -{ - TRNG_DSEL_1B = 0x0, /**< 1-bit */ - TRNG_DSEL_8B = 0x1, /**< 8-bit */ - TRNG_DSEL_16B = 0x2, /**< 16-bit */ - TRNG_DSEL_32B = 0x3, /**< 32-bit */ +typedef enum { + TRNG_DSEL_1B = 0x0U, /**< 1-bit */ + TRNG_DSEL_8B = 0x1U, /**< 8-bit */ + TRNG_DSEL_16B = 0x2U, /**< 16-bit */ + TRNG_DSEL_32B = 0x3U, /**< 32-bit */ } trng_data_width_t; /** * @brief seed type */ -typedef enum -{ - TRNG_SEED_TYPE_0 = 0x0, /**< Using 0 as seed */ - TRNG_SEED_TYPE_1 = 0x1, /**< Using 1 as seed */ - TRNG_SEED_TYPE_LAST = 0x2, /**< Using last seed */ - TRNG_SEED_TYPE_SEED = 0x3, /**< Using value of register */ +typedef enum { + TRNG_SEED_TYPE_0 = 0x0U, /**< Using 0 as seed */ + TRNG_SEED_TYPE_1 = 0x1U, /**< Using 1 as seed */ + TRNG_SEED_TYPE_LAST = 0x2U, /**< Using last seed */ + TRNG_SEED_TYPE_SEED = 0x3U, /**< Using value of register */ } trng_seed_type_t; /** * @brief TRNG init structure definition */ -typedef struct -{ - trng_data_width_t data_width; /**< The width of data */ - trng_seed_type_t seed_type; /**< The seed type */ - uint32_t seed; /**< The value of seed */ - uint16_t t_start; /**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */ - uint8_t adjc; /**< Adjust parameter */ - type_func_t posten; /**< Data back handle function */ +typedef struct { + trng_data_width_t data_width; /**< The width of data */ + trng_seed_type_t seed_type; /**< The seed type */ + uint32_t seed; /**< The value of seed */ + uint16_t t_start; /**< T(start) = T(trng) * 2 ^ (t_start + 1), T(start) > 1ms */ + uint8_t adjc; /**< Adjust parameter */ + type_func_t posten; /**< Data back handle function */ } trng_init_t; /** * @brief TRNG state structures definition */ -typedef enum -{ - TRNG_STATE_RESET = 0x0, /**< Peripheral is not initialized */ - TRNG_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - TRNG_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - TRNG_STATE_ERROR = 0x4, /**< Error */ +typedef enum { + TRNG_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ + TRNG_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + TRNG_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + TRNG_STATE_ERROR = 0x4U, /**< Error */ } trng_state_t; /** * @brief State type */ -typedef enum -{ - TRNG_STATUS_START = (1U << 0), /**< Start state */ - TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */ - TRNG_STATUS_SERR = (1U << 2), /**< Error state */ +typedef enum { + TRNG_STATUS_START = (1U << 0), /**< Start state */ + TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */ + TRNG_STATUS_SERR = (1U << 2), /**< Error state */ } trng_status_t; /** * @brief Interrupt type */ -typedef enum -{ - TRNG_IT_START = (1U << 0), /**< Start */ - TRNG_IT_DAVLD = (1U << 1), /**< Data valid */ - TRNG_IT_SERR = (1U << 2), /**< Error */ +typedef enum { + TRNG_IT_START = (1U << 0), /**< Start */ + TRNG_IT_DAVLD = (1U << 1), /**< Data valid */ + TRNG_IT_SERR = (1U << 2), /**< Error */ } trng_it_t; /** * @brief Interrupt flag type */ -typedef enum -{ - TRNG_IF_START = (1U << 0), /**< Start */ - TRNG_IF_DAVLD = (1U << 1), /**< Data valid */ - TRNG_IF_SERR = (1U << 2), /**< Error */ +typedef enum { + TRNG_IF_START = (1U << 0), /**< Start */ + TRNG_IF_DAVLD = (1U << 1), /**< Data valid */ + TRNG_IF_SERR = (1U << 2), /**< Error */ } trng_flag_t; /** * @brief TRNG Handle Structure definition */ -typedef struct trng_handle_s -{ - TRNG_TypeDef *perh; /**< Register base address */ - trng_init_t init; /**< TRNG required parameters */ - uint32_t data; /**< result data */ - lock_state_t lock; /**< Locking object */ - trng_state_t state; /**< TRNG operation state */ - - void (*trng_cplt_cbk)(struct trng_handle_s *arg); /**< Trng completed callback */ - void (*err_cplt_cbk)(struct trng_handle_s *arg); /**< Trng error callback */ - void (*init_cplt_cbk)(struct trng_handle_s *arg); /**< Trng init completed callback */ +typedef struct trng_handle_s { + TRNG_TypeDef *perh; /**< Register base address */ + trng_init_t init; /**< TRNG required parameters */ + uint32_t data; /**< result data */ + lock_state_t lock; /**< Locking object */ + trng_state_t state; /**< TRNG operation state */ + + void (*trng_cplt_cbk)(struct trng_handle_s *arg); /**< Trng completed callback */ + void (*err_cplt_cbk)(struct trng_handle_s *arg); /**< Trng error callback */ + void (*init_cplt_cbk)(struct trng_handle_s *arg); /**< Trng init completed callback */ } trng_handle_t; /** * @} @@ -154,15 +146,16 @@ typedef struct trng_handle_s ((x) == TRNG_SEED_TYPE_LAST) || \ ((x) == TRNG_SEED_TYPE_SEED)) #define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \ - ((x) == TRNG_STATUS_DAVLD) || \ - ((x) == TRNG_STATUS_SERR)) -#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \ - ((x) == TRNG_IT_DAVLD) || \ - ((x) == TRNG_IT_SERR)) -#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \ - ((x) == TRNG_IF_DAVLD) || \ - ((x) == TRNG_IF_SERR)) -#define IS_TRNG_ADJC(x) ((x) < 4) + ((x) == TRNG_STATUS_DAVLD) || \ + ((x) == TRNG_STATUS_SERR)) +#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \ + ((x) == TRNG_IT_DAVLD) || \ + ((x) == TRNG_IT_SERR)) +#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \ + ((x) == TRNG_IF_DAVLD) || \ + ((x) == TRNG_IF_SERR)) +#define IS_TRNG_ADJC(x) ((x) < 4) +#define IS_TRNG_T_START(x) ((x) < 8) /** * @} */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_tsense.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_tsense.h index 0f55db2a2981f546e323e3ff1d7417558b01ed50..410dcb7ff6b51d2a1a0cc0b8fa7bf5c6fb347245 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_tsense.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_tsense.h @@ -35,74 +35,74 @@ extern "C" { /** @defgroup TSENSE_Public_Macros TSENSE Public Macros * @{ */ -#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0)) -#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669)) +#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U)) +#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U)) #define TSENSE_ENABLE() \ - do { \ - TSENSE_UNLOCK(); \ - SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ - TSENSE_LOCK(); \ - } while (0) +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_DISABLE() \ - do { \ - TSENSE_UNLOCK(); \ - CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ - TSENSE_LOCK(); \ - } while (0) +do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_REQ_ENABLE() \ - do { \ - TSENSE_UNLOCK(); \ - SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ - TSENSE_LOCK(); \ - } while (0) +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_REQ_DISABLE() \ - do { \ - TSENSE_UNLOCK(); \ - CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ - TSENSE_LOCK(); \ - } while (0) +do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_CTN_ENABLE() \ - do { \ - TSENSE_UNLOCK(); \ - SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ - TSENSE_LOCK(); \ - } while (0) +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_CTN_DISABLE() \ - do { \ - TSENSE_UNLOCK(); \ - CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ - TSENSE_LOCK(); \ - } while (0) +do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_RESET() \ - do { \ - TSENSE_UNLOCK(); \ - SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK); \ - TSENSE_LOCK(); \ - } while (0) +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_LTGR_WR(data) \ - do { \ - TSENSE_UNLOCK(); \ - WRITE_REG(TSENSE->LTGR, (data)); \ - TSENSE_LOCK(); \ - } while(0) +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->LTGR, (data)); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_HTGR_WR(data) \ - do { \ - TSENSE_UNLOCK(); \ - WRITE_REG(TSENSE->HTGR, (data)); \ - TSENSE_LOCK(); \ - } while(0) +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->HTGR, (data)); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_TBDR_WR(data) \ - do { \ - TSENSE_UNLOCK(); \ - WRITE_REG(TSENSE->TBDR, (data)); \ - TSENSE_LOCK(); \ - } while(0) +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->TBDR, (data)); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_TCALBDR_WR(data) \ - do { \ - TSENSE_UNLOCK(); \ - WRITE_REG(TSENSE->TCALBDR, (data)); \ - TSENSE_LOCK(); \ - } while(0) +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->TCALBDR, (data)); \ + TSENSE_LOCK(); \ +} while (0) /** * @} */ @@ -113,50 +113,34 @@ extern "C" { /** * @brief Temperature update time */ -typedef enum -{ - TSENSE_UPDATE_CYCLE_3 = 0x3, /**< 3 Cycles */ - TSENSE_UPDATE_CYCLE_4 = 0x4, /**< 4 Cycles */ - TSENSE_UPDATE_CYCLE_5 = 0x5, /**< 5 Cycles */ - TSENSE_UPDATE_CYCLE_6 = 0x6, /**< 6 Cycles */ - TSENSE_UPDATE_CYCLE_7 = 0x7, /**< 7 Cycles */ +typedef enum { + TSENSE_UPDATE_CYCLE_3 = 0x3U, /**< 3 Cycles */ + TSENSE_UPDATE_CYCLE_4 = 0x4U, /**< 4 Cycles */ + TSENSE_UPDATE_CYCLE_5 = 0x5U, /**< 5 Cycles */ + TSENSE_UPDATE_CYCLE_6 = 0x6U, /**< 6 Cycles */ + TSENSE_UPDATE_CYCLE_7 = 0x7U, /**< 7 Cycles */ } tsense_update_cycle_t; /** * @brief Temperature output mode */ -typedef enum -{ - TSENSE_OUTPUT_MODE_200 = 0x0, /**< 200 cycles update one temperature */ - TSENSE_OUTPUT_MODE_400 = 0x1, /**< 400 cycles update one temperature */ - TSENSE_OUTPUT_MODE_800 = 0x2, /**< 800 cycles update one temperature */ - TSENSE_OUTPUT_MODE_1600 = 0x3, /**< 1600 cycles update one temperature */ - TSENSE_OUTPUT_MODE_3200 = 0x4, /**< 3200 cycles update one temperature */ +typedef enum { + TSENSE_OUTPUT_MODE_200 = 0x0U, /**< 200 cycles update one temperature */ + TSENSE_OUTPUT_MODE_400 = 0x1U, /**< 400 cycles update one temperature */ + TSENSE_OUTPUT_MODE_800 = 0x2U, /**< 800 cycles update one temperature */ + TSENSE_OUTPUT_MODE_1600 = 0x3U, /**< 1600 cycles update one temperature */ + TSENSE_OUTPUT_MODE_3200 = 0x4U, /**< 3200 cycles update one temperature */ } tsense_output_mode_t; /** * @brief Source select */ -typedef enum -{ - TSENSE_SOURCE_LOSC = 0x0, /**< LOSC */ - TSENSE_SOURCE_LRC = 0x1, /**< LRC */ - TSENSE_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ - TSENSE_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ +typedef enum { + TSENSE_SOURCE_LOSC = 0x0U, /**< LOSC */ + TSENSE_SOURCE_LRC = 0x1U, /**< LRC */ } tsense_source_sel_t; -/** - * @brief TSENSE init structure definition - */ -typedef struct -{ - tsense_update_cycle_t cycle; /**< Temperature update time */ - tsense_output_mode_t mode; /**< Temperature output mode */ - type_func_t ctn; /**< Continue mode */ - uint8_t psc; /**< Perscaler */ -} tsense_init_t; - /** * @brief Define callback function type */ @@ -169,20 +153,8 @@ typedef void (*tsense_cbk)(uint16_t value, ald_status_t status); * @defgroup TSENSE_Private_Macros TSENSE Private Macros * @{ */ -#define IS_TSENSE_UPDATE_CYCLE(x) (((x) == TSENSE_UPDATE_CYCLE_3) || \ - ((x) == TSENSE_UPDATE_CYCLE_4) || \ - ((x) == TSENSE_UPDATE_CYCLE_5) || \ - ((x) == TSENSE_UPDATE_CYCLE_6) || \ - ((x) == TSENSE_UPDATE_CYCLE_7)) -#define IS_TSENSE_OUTPUT_MODE(x) (((x) == TSENSE_OUTPUT_MODE_200) || \ - ((x) == TSENSE_OUTPUT_MODE_400) || \ - ((x) == TSENSE_OUTPUT_MODE_800) || \ - ((x) == TSENSE_OUTPUT_MODE_1600) || \ - ((x) == TSENSE_OUTPUT_MODE_3200)) -#define IS_TSENSE_SOURCE_SEL(x) (((x) == TSENSE_SOURCE_LOSC) || \ - ((x) == TSENSE_SOURCE_LRC) || \ - ((x) == TSENSE_SOURCE_HRC_DIV_1M ) || \ - ((x) == TSENSE_SOURCE_HOSC_DIV_1M)) +#define IS_TSENSE_SOURCE_SEL(x) (((x) == TSENSE_SOURCE_LOSC) || \ + ((x) == TSENSE_SOURCE_LRC)) /** * @} */ @@ -194,7 +166,7 @@ typedef void (*tsense_cbk)(uint16_t value, ald_status_t status); * @{ */ /* Initialization functions */ -extern void ald_tsense_init(tsense_init_t *init); +extern void ald_tsense_init(void); extern void ald_tsense_source_select(tsense_source_sel_t sel); /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_uart.h index 49cc24d9efb9d72fa7ce911da99613ccd353f702..10a351ca19371befb32b6e80701b564b5f343c10 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_uart.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_uart.h @@ -74,233 +74,216 @@ extern "C" { /** * @brief UART word length */ -typedef enum -{ - UART_WORD_LENGTH_5B = 0x0, /**< 5-bits */ - UART_WORD_LENGTH_6B = 0x1, /**< 6-bits */ - UART_WORD_LENGTH_7B = 0x2, /**< 7-bits */ - UART_WORD_LENGTH_8B = 0x3, /**< 8-bits */ +typedef enum { + UART_WORD_LENGTH_5B = 0x0U, /**< 5-bits */ + UART_WORD_LENGTH_6B = 0x1U, /**< 6-bits */ + UART_WORD_LENGTH_7B = 0x2U, /**< 7-bits */ + UART_WORD_LENGTH_8B = 0x3U, /**< 8-bits */ } uart_word_length_t; /** * @brief UART stop bits */ -typedef enum -{ - UART_STOP_BITS_1 = 0x0, /**< 1-bits */ - UART_STOP_BITS_2 = 0x1, /**< 2-bits */ - UART_STOP_BITS_0_5 = 0x0, /**< 0.5-bits, using smartcard mode */ - UART_STOP_BITS_1_5 = 0x1, /**< 1.5-bits, using smartcard mode */ +typedef enum { + UART_STOP_BITS_1 = 0x0U, /**< 1-bits */ + UART_STOP_BITS_2 = 0x1U, /**< 2-bits */ + UART_STOP_BITS_0_5 = 0x0U, /**< 0.5-bits, using smartcard mode */ + UART_STOP_BITS_1_5 = 0x1U, /**< 1.5-bits, using smartcard mode */ } uart_stop_bits_t; /** * @brief UART parity */ -typedef enum -{ - UART_PARITY_NONE = 0x0, /**< Not parity */ - UART_PARITY_ODD = 0x1, /**< Odd parity */ - UART_PARITY_EVEN = 0x3, /**< Even parity */ +typedef enum { + UART_PARITY_NONE = 0x0U, /**< Not parity */ + UART_PARITY_ODD = 0x1U, /**< Odd parity */ + UART_PARITY_EVEN = 0x3U, /**< Even parity */ } uart_parity_t; /** * @brief UART mode */ -typedef enum -{ - UART_MODE_UART = 0x0, /**< UART */ - UART_MODE_LIN = 0x1, /**< LIN */ - UART_MODE_IrDA = 0x2, /**< IrDA */ - UART_MODE_RS485 = 0x3, /**< RS485 */ - UART_MODE_HDSEL = 0x4, /**< Single-wire half-duplex */ +typedef enum { + UART_MODE_UART = 0x0U, /**< UART */ + UART_MODE_LIN = 0x1U, /**< LIN */ + UART_MODE_IrDA = 0x2U, /**< IrDA */ + UART_MODE_RS485 = 0x3U, /**< RS485 */ + UART_MODE_HDSEL = 0x4U, /**< Single-wire half-duplex */ } uart_mode_t; /** * @brief UART hardware flow control */ -typedef enum -{ - UART_HW_FLOW_CTL_DISABLE = 0x0, /**< Auto-flow-control disable */ - UART_HW_FLOW_CTL_ENABLE = 0x1, /**< Auto-flow-control enable */ +typedef enum { + UART_HW_FLOW_CTL_DISABLE = 0x0U, /**< Auto-flow-control disable */ + UART_HW_FLOW_CTL_ENABLE = 0x1U, /**< Auto-flow-control enable */ } uart_hw_flow_ctl_t; /** * @brief ALD UART state */ -typedef enum -{ - UART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - UART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - UART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - UART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - UART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ - UART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ - UART_STATE_TIMEOUT = 0x03, /**< Timeout state */ - UART_STATE_ERROR = 0x04, /**< Error */ +typedef enum { + UART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + UART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + UART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + UART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ + UART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ + UART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */ + UART_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + UART_STATE_ERROR = 0x04U, /**< Error */ } uart_state_t; /** * @brief UART error codes */ -typedef enum -{ - UART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ - UART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ - UART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ - UART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ - UART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ - UART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +typedef enum { + UART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ + UART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ + UART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ + UART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ + UART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ + UART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ } uart_error_t; /** * @brief UART init structure definition */ -typedef struct -{ - uint32_t baud; /**< Specifies the uart communication baud rate */ - uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ - uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ - uart_parity_t parity; /**< Specifies the parity mode */ - uart_mode_t mode; /**< Specifies uart mode */ - uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ +typedef struct { + uint32_t baud; /**< Specifies the uart communication baud rate */ + uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ + uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ + uart_parity_t parity; /**< Specifies the parity mode */ + uart_mode_t mode; /**< Specifies uart mode */ + uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ } uart_init_t; /** * @brief UART handle structure definition */ -typedef struct uart_handle_s -{ - UART_TypeDef *perh; /**< UART registers base address */ - uart_init_t init; /**< UART communication parameters */ - uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */ - uint16_t tx_size; /**< UART Tx Transfer size */ - uint16_t tx_count; /**< UART Tx Transfer Counter */ - uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */ - uint16_t rx_size; /**< UART Rx Transfer size */ - uint16_t rx_count; /**< UART Rx Transfer Counter */ +typedef struct uart_handle_s { + UART_TypeDef *perh; /**< UART registers base address */ + uart_init_t init; /**< UART communication parameters */ + uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */ + uint16_t tx_size; /**< UART Tx Transfer size */ + uint16_t tx_count; /**< UART Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */ + uint16_t rx_size; /**< UART Rx Transfer size */ + uint16_t rx_count; /**< UART Rx Transfer Counter */ #ifdef ALD_DMA - dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */ - dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */ + dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */ + dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */ #endif - lock_state_t lock; /**< Locking object */ - uart_state_t state; /**< UART communication state */ - uart_error_t err_code; /**< UART Error code */ + lock_state_t lock; /**< Locking object */ + uart_state_t state; /**< UART communication state */ + uart_error_t err_code; /**< UART Error code */ - void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */ + void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */ } uart_handle_t; /** * @brief UART RS485 configure structure definition */ -typedef struct -{ - type_func_t normal; /**< Normal mode */ - type_func_t dir; /**< Auto-direction mode */ - type_func_t invert; /**< Address detection invert */ - uint8_t addr; /**< Address for compare */ +typedef struct { + type_func_t normal; /**< Normal mode */ + type_func_t dir; /**< Auto-direction mode */ + type_func_t invert; /**< Address detection invert */ + uint8_t addr; /**< Address for compare */ } uart_rs485_config_t; /** * @brief LIN detection break length */ -typedef enum -{ - LIN_BREAK_LEN_10B = 0x0, /**< 10-bit break */ - LIN_BREAK_LEN_11B = 0x1, /**< 11-bit break */ +typedef enum { + LIN_BREAK_LEN_10B = 0x0U, /**< 10-bit break */ + LIN_BREAK_LEN_11B = 0x1U, /**< 11-bit break */ } uart_lin_break_len_t; /** * @brief UART TXFIFO size */ -typedef enum -{ - UART_TXFIFO_EMPTY = 0x0, /**< Empty */ - UART_TXFIFO_2BYTE = 0x1, /**< 2-Bytes */ - UART_TXFIFO_4BYTE = 0x2, /**< 4-Bytes */ - UART_TXFIFO_8BYTE = 0x3, /**< 8-Bytes */ +typedef enum { + UART_TXFIFO_EMPTY = 0x0U, /**< Empty */ + UART_TXFIFO_2BYTE = 0x1U, /**< 2-Bytes */ + UART_TXFIFO_4BYTE = 0x2U, /**< 4-Bytes */ + UART_TXFIFO_8BYTE = 0x3U, /**< 8-Bytes */ } uart_txfifo_t; /** * @brief UART RXFIFO size */ -typedef enum -{ - UART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */ - UART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */ - UART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */ - UART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */ +typedef enum { + UART_RXFIFO_1BYTE = 0x0U, /**< 1-Byte */ + UART_RXFIFO_4BYTE = 0x1U, /**< 4-Bytes */ + UART_RXFIFO_8BYTE = 0x2U, /**< 8-Bytes */ + UART_RXFIFO_14BYTE = 0x3U, /**< 14-Bytes */ } uart_rxfifo_t; /** * @brief UART auto-baud mode */ -typedef enum -{ - UART_ABRMOD_1_TO_0 = 0x0, /**< Detect bit0:1, bit1:0 */ - UART_ABRMOD_1 = 0x1, /**< Detect bit0:1 */ - UART_ABRMOD_0_TO_1 = 0x2, /**< Detect bit0:0, bit1:1 */ +typedef enum { + UART_ABRMOD_1_TO_0 = 0x0U, /**< Detect bit0:1, bit1:0 */ + UART_ABRMOD_1 = 0x1U, /**< Detect bit0:1 */ + UART_ABRMOD_0_TO_1 = 0x2U, /**< Detect bit0:0, bit1:1 */ } uart_auto_baud_mode_t; /** * @brief UART status types */ -typedef enum -{ - UART_STATUS_DR = (1U << 0), /**< Data ready */ - UART_STATUS_OE = (1U << 1), /**< Overrun error */ - UART_STATUS_PE = (1U << 2), /**< Parity error */ - UART_STATUS_FE = (1U << 3), /**< Framing error */ - UART_STATUS_BI = (1U << 4), /**< Break interrupt */ - UART_STATUS_TBEM = (1U << 5), /**< Transmit buffer empty */ - UART_STATUS_TEM = (1U << 6), /**< Transmitter empty */ - UART_STATUS_RFE = (1U << 7), /**< Reveiver FIFO data error */ - UART_STATUS_BUSY = (1U << 8), /**< UART busy */ - UART_STATUS_TFNF = (1U << 9), /**< Transmit FIFO not full */ - UART_STATUS_TFEM = (1U << 10), /**< Transmit FIFO not empty */ - UART_STATUS_RFNE = (1U << 11), /**< Receive FIFO not empty */ - UART_STATUS_RFF = (1U << 12), /**< Receive FIFO full */ - UART_STATUS_DCTS = (1U << 14), /**< Delta clear to send */ - UART_STATUS_CTS = (1U << 15), /**< Clear to send */ +typedef enum { + UART_STATUS_DR = (1U << 0), /**< Data ready */ + UART_STATUS_OE = (1U << 1), /**< Overrun error */ + UART_STATUS_PE = (1U << 2), /**< Parity error */ + UART_STATUS_FE = (1U << 3), /**< Framing error */ + UART_STATUS_BI = (1U << 4), /**< Break interrupt */ + UART_STATUS_TBEM = (1U << 5), /**< Transmit buffer empty */ + UART_STATUS_TEM = (1U << 6), /**< Transmitter empty */ + UART_STATUS_RFE = (1U << 7), /**< Reveiver FIFO data error */ + UART_STATUS_BUSY = (1U << 8), /**< UART busy */ + UART_STATUS_TFNF = (1U << 9), /**< Transmit FIFO not full */ + UART_STATUS_TFEM = (1U << 10), /**< Transmit FIFO not empty */ + UART_STATUS_RFNE = (1U << 11), /**< Receive FIFO not empty */ + UART_STATUS_RFF = (1U << 12), /**< Receive FIFO full */ + UART_STATUS_DCTS = (1U << 14), /**< Delta clear to send */ + UART_STATUS_CTS = (1U << 15), /**< Clear to send */ } uart_status_t; /** * @brief UART interrupt types */ -typedef enum -{ - UART_IT_RXRD = (1U << 0), /**< Receive data available */ - UART_IT_TXS = (1U << 1), /**< Tx empty status */ - UART_IT_RXS = (1U << 2), /**< Rx line status */ - UART_IT_MDS = (1U << 3), /**< Modem status */ - UART_IT_RTO = (1U << 4), /**< Receiver timeout */ - UART_IT_BZ = (1U << 5), /**< Busy status */ - UART_IT_ABE = (1U << 6), /**< Auto-baud rate detection end */ - UART_IT_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ - UART_IT_LINBK = (1U << 8), /**< Lin break detection */ - UART_IT_TC = (1U << 9), /**< Transmission complete */ - UART_IT_EOB = (1U << 10), /**< End of block */ - UART_IT_CM = (1U << 11), /**< Character match */ +typedef enum { + UART_IT_RXRD = (1U << 0), /**< Receive data available */ + UART_IT_TXS = (1U << 1), /**< Tx empty status */ + UART_IT_RXS = (1U << 2), /**< Rx line status */ + UART_IT_MDS = (1U << 3), /**< Modem status */ + UART_IT_RTO = (1U << 4), /**< Receiver timeout */ + UART_IT_BZ = (1U << 5), /**< Busy status */ + UART_IT_ABE = (1U << 6), /**< Auto-baud rate detection end */ + UART_IT_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ + UART_IT_LINBK = (1U << 8), /**< Lin break detection */ + UART_IT_TC = (1U << 9), /**< Transmission complete */ + UART_IT_EOB = (1U << 10), /**< End of block */ + UART_IT_CM = (1U << 11), /**< Character match */ } uart_it_t; /** * @brief UART flags types */ -typedef enum -{ - UART_IF_RXRD = (1U << 0), /**< Receive data available */ - UART_IF_TXS = (1U << 1), /**< Tx empty status */ - UART_IF_RXS = (1U << 2), /**< Rx line status */ - UART_IF_MDS = (1U << 3), /**< Modem status */ - UART_IF_RTO = (1U << 4), /**< Receiver timeout */ - UART_IF_BZ = (1U << 5), /**< Busy status */ - UART_IF_ABE = (1U << 6), /**< Auto-baud rate detection end */ - UART_IF_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ - UART_IF_LINBK = (1U << 8), /**< Lin break detection */ - UART_IF_TC = (1U << 9), /**< Transmission complete */ - UART_IF_EOB = (1U << 10), /**< End of block */ - UART_IF_CM = (1U << 11), /**< Character match */ +typedef enum { + UART_IF_RXRD = (1U << 0), /**< Receive data available */ + UART_IF_TXS = (1U << 1), /**< Tx empty status */ + UART_IF_RXS = (1U << 2), /**< Rx line status */ + UART_IF_MDS = (1U << 3), /**< Modem status */ + UART_IF_RTO = (1U << 4), /**< Receiver timeout */ + UART_IF_BZ = (1U << 5), /**< Busy status */ + UART_IF_ABE = (1U << 6), /**< Auto-baud rate detection end */ + UART_IF_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ + UART_IF_LINBK = (1U << 8), /**< Lin break detection */ + UART_IF_TC = (1U << 9), /**< Transmission complete */ + UART_IF_EOB = (1U << 10), /**< End of block */ + UART_IF_CM = (1U << 11), /**< Character match */ } uart_flag_t; /** * @} @@ -318,22 +301,22 @@ typedef enum ((x) == UART_WORD_LENGTH_7B) || \ ((x) == UART_WORD_LENGTH_8B)) #define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \ - ((x) == UART_STOP_BITS_2) || \ - ((x) == UART_STOP_BITS_0_5) || \ - ((x) == UART_STOP_BITS_1_5)) + ((x) == UART_STOP_BITS_2) || \ + ((x) == UART_STOP_BITS_0_5) || \ + ((x) == UART_STOP_BITS_1_5)) #define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \ - ((x) == UART_PARITY_ODD) || \ - ((x) == UART_PARITY_EVEN)) + ((x) == UART_PARITY_ODD) || \ + ((x) == UART_PARITY_EVEN)) #define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \ - ((x) == UART_MODE_LIN) || \ - ((x) == UART_MODE_IrDA) || \ - ((x) == UART_MODE_RS485) || \ - ((x) == UART_MODE_HDSEL)) + ((x) == UART_MODE_LIN) || \ + ((x) == UART_MODE_IrDA) || \ + ((x) == UART_MODE_RS485) || \ + ((x) == UART_MODE_HDSEL)) #define IS_UART_HARDWARE_FLOW_CONTROL(x) \ - (((x) == UART_HW_FLOW_CTL_DISABLE) || \ - ((x) == UART_HW_FLOW_CTL_ENABLE)) + (((x) == UART_HW_FLOW_CTL_DISABLE) || \ + ((x) == UART_HW_FLOW_CTL_ENABLE)) #define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \ - ((x) == LIN_BREAK_LEN_11B)) + ((x) == LIN_BREAK_LEN_11B)) #define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \ ((x) == UART_TXFIFO_2BYTE) || \ ((x) == UART_TXFIFO_4BYTE) || \ @@ -343,47 +326,47 @@ typedef enum ((x) == UART_RXFIFO_8BYTE) || \ ((x) == UART_RXFIFO_14BYTE)) #define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \ - ((x) == UART_ABRMOD_1) || \ - ((x) == UART_ABRMOD_0_TO_1)) + ((x) == UART_ABRMOD_1) || \ + ((x) == UART_ABRMOD_0_TO_1)) #define IS_UART_STATUS(x) (((x) == UART_STATUS_DR) || \ - ((x) == UART_STATUS_OE) || \ - ((x) == UART_STATUS_PE) || \ - ((x) == UART_STATUS_FE) || \ - ((x) == UART_STATUS_BI) || \ - ((x) == UART_STATUS_TBEM) || \ - ((x) == UART_STATUS_TEM) || \ - ((x) == UART_STATUS_RFE) || \ - ((x) == UART_STATUS_BUSY) || \ - ((x) == UART_STATUS_TFNF) || \ - ((x) == UART_STATUS_TFEM) || \ - ((x) == UART_STATUS_RFNE) || \ - ((x) == UART_STATUS_RFF) || \ - ((x) == UART_STATUS_DCTS) || \ - ((x) == UART_STATUS_CTS)) + ((x) == UART_STATUS_OE) || \ + ((x) == UART_STATUS_PE) || \ + ((x) == UART_STATUS_FE) || \ + ((x) == UART_STATUS_BI) || \ + ((x) == UART_STATUS_TBEM) || \ + ((x) == UART_STATUS_TEM) || \ + ((x) == UART_STATUS_RFE) || \ + ((x) == UART_STATUS_BUSY) || \ + ((x) == UART_STATUS_TFNF) || \ + ((x) == UART_STATUS_TFEM) || \ + ((x) == UART_STATUS_RFNE) || \ + ((x) == UART_STATUS_RFF) || \ + ((x) == UART_STATUS_DCTS) || \ + ((x) == UART_STATUS_CTS)) #define IS_UART_IT(x) (((x) == UART_IT_RXRD) || \ - ((x) == UART_IT_TXS) || \ - ((x) == UART_IT_RXS) || \ - ((x) == UART_IT_MDS) || \ - ((x) == UART_IT_RTO) || \ - ((x) == UART_IT_BZ) || \ - ((x) == UART_IT_ABE) || \ - ((x) == UART_IT_ABTO) || \ - ((x) == UART_IT_LINBK) || \ - ((x) == UART_IT_TC) || \ - ((x) == UART_IT_EOB) || \ - ((x) == UART_IT_CM)) + ((x) == UART_IT_TXS) || \ + ((x) == UART_IT_RXS) || \ + ((x) == UART_IT_MDS) || \ + ((x) == UART_IT_RTO) || \ + ((x) == UART_IT_BZ) || \ + ((x) == UART_IT_ABE) || \ + ((x) == UART_IT_ABTO) || \ + ((x) == UART_IT_LINBK) || \ + ((x) == UART_IT_TC) || \ + ((x) == UART_IT_EOB) || \ + ((x) == UART_IT_CM)) #define IS_UART_IF(x) (((x) == UART_IF_RXRD) || \ - ((x) == UART_IF_TXS) || \ - ((x) == UART_IF_RXS) || \ - ((x) == UART_IF_MDS) || \ - ((x) == UART_IF_RTO) || \ - ((x) == UART_IF_BZ) || \ - ((x) == UART_IF_ABE) || \ - ((x) == UART_IF_ABTO) || \ - ((x) == UART_IF_LINBK) || \ - ((x) == UART_IF_TC) || \ - ((x) == UART_IF_EOB) || \ - ((x) == UART_IF_CM)) + ((x) == UART_IF_TXS) || \ + ((x) == UART_IF_RXS) || \ + ((x) == UART_IF_MDS) || \ + ((x) == UART_IF_RTO) || \ + ((x) == UART_IF_BZ) || \ + ((x) == UART_IF_ABE) || \ + ((x) == UART_IF_ABTO) || \ + ((x) == UART_IF_LINBK) || \ + ((x) == UART_IF_TC) || \ + ((x) == UART_IF_EOB) || \ + ((x) == UART_IF_CM)) #define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21)) #define IS_UART_DATA(x) ((x) <= 0x1FF) @@ -434,8 +417,8 @@ void ald_uart_irq_handler(uart_handle_t *hperh); /* Peripheral Control functions */ void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state); void ald_uart_dma_req_config(uart_handle_t *hperh, type_func_t state); -void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); -void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); +void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config); +void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config); void ald_uart_lin_send_break(uart_handle_t *hperh); void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len); void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode); diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_usart.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_usart.h index 62214b2a089d43a973487d3bb104619895f7ce4d..4f30e2c2a4e49d847a1f3378a051e57ed93dc51c 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_usart.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_usart.h @@ -18,7 +18,7 @@ #define __ALD_USART_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -40,174 +40,159 @@ extern "C" { /** * @brief usart_word_length */ -typedef enum -{ - USART_WORD_LENGTH_8B = 0x0, /**< Word length is 8-bits */ - USART_WORD_LENGTH_9B = 0x1, /**< Word length is 9-bits */ +typedef enum { + USART_WORD_LENGTH_8B = 0x0U, /**< Word length is 8-bits */ + USART_WORD_LENGTH_9B = 0x1U, /**< Word length is 9-bits */ } usart_word_length_t; /** * @brief usart_stop_bits */ -typedef enum -{ - USART_STOP_BITS_1 = 0x0, /**< Stop bits is 1-bits */ - USART_STOP_BITS_0_5 = 0x1, /**< Stop bits is 0.5-bits */ - USART_STOP_BITS_2 = 0x2, /**< Stop bits is 2-bits */ - USART_STOP_BITS_1_5 = 0x3, /**< Stop bits is 1.5-bits */ +typedef enum { + USART_STOP_BITS_1 = 0x0U, /**< Stop bits is 1-bits */ + USART_STOP_BITS_0_5 = 0x1U, /**< Stop bits is 0.5-bits */ + USART_STOP_BITS_2 = 0x2U, /**< Stop bits is 2-bits */ + USART_STOP_BITS_1_5 = 0x3U, /**< Stop bits is 1.5-bits */ } usart_stop_bits_t; /** * @brief usart_parity */ -typedef enum -{ - USART_PARITY_NONE = 0x0, /**< Not parity */ - USART_PARITY_EVEN = 0x2, /**< Even parity */ - USART_PARITY_ODD = 0x3, /**< Odd parity */ +typedef enum { + USART_PARITY_NONE = 0x0U, /**< Not parity */ + USART_PARITY_EVEN = 0x2U, /**< Even parity */ + USART_PARITY_ODD = 0x3U, /**< Odd parity */ } usart_parity_t; /** * @brief usart_mode */ -typedef enum -{ - USART_MODE_RX = 0x1, /**< TX mode */ - USART_MODE_TX = 0x2, /**< RX mode */ - USART_MODE_TX_RX = 0x3, /**< TX & RX mode */ +typedef enum { + USART_MODE_RX = 0x1U, /**< TX mode */ + USART_MODE_TX = 0x2U, /**< RX mode */ + USART_MODE_TX_RX = 0x3U, /**< TX & RX mode */ } usart_mode_t; /** * @brief usart_hardware_flow_control */ -typedef enum -{ - USART_HW_FLOW_CTL_NONE = 0x0, /**< Not flow control */ - USART_HW_FLOW_CTL_RTS = 0x1, /**< RTS flow control */ - USART_HW_FLOW_CTL_CTS = 0x2, /**< CTS flow control */ - USART_HW_FLOW_CTL_RTS_CTS = 0x3, /**< RTS & CTS flow control */ +typedef enum { + USART_HW_FLOW_CTL_NONE = 0x0U, /**< Not flow control */ + USART_HW_FLOW_CTL_RTS = 0x1U, /**< RTS flow control */ + USART_HW_FLOW_CTL_CTS = 0x2U, /**< CTS flow control */ + USART_HW_FLOW_CTL_RTS_CTS = 0x3U, /**< RTS & CTS flow control */ } usart_hw_flow_ctl_t; /** * @brief usart_clock */ -typedef enum -{ - USART_CLOCK_DISABLE = 0x0, /**< Disable clock output */ - USART_CLOCK_ENABLE = 0x1, /**< Enable clock output */ +typedef enum { + USART_CLOCK_DISABLE = 0x0U, /**< Disable clock output */ + USART_CLOCK_ENABLE = 0x1U, /**< Enable clock output */ } usart_clock_t; /** * @brief usart_clock_polarity */ -typedef enum -{ - USART_CPOL_LOW = 0x0, /**< Clock polarity low */ - USART_CPOL_HIGH = 0x1, /**< Clock polarity high */ +typedef enum { + USART_CPOL_LOW = 0x0U, /**< Clock polarity low */ + USART_CPOL_HIGH = 0x1U, /**< Clock polarity high */ } usart_cpol_t; /** * @brief usart_clock_phase */ -typedef enum -{ - USART_CPHA_1EDGE = 0x0, /**< Clock phase first edge */ - USART_CPHA_2EDGE = 0x1, /**< Clock phase second edge */ +typedef enum { + USART_CPHA_1EDGE = 0x0U, /**< Clock phase first edge */ + USART_CPHA_2EDGE = 0x1U, /**< Clock phase second edge */ } usart_cpha_t; /** * @brief usart_last_bit */ -typedef enum -{ - USART_LAST_BIT_DISABLE = 0x0, /**< Disable last bit clock output */ - USART_LAST_BIT_ENABLE = 0x1, /**< Enable last bit clock output */ +typedef enum { + USART_LAST_BIT_DISABLE = 0x0U, /**< Disable last bit clock output */ + USART_LAST_BIT_ENABLE = 0x1U, /**< Enable last bit clock output */ } usart_last_bit_t; /** * @brief usart state structures definition */ -typedef enum -{ - USART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - USART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - USART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - USART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - USART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ - USART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ - USART_STATE_TIMEOUT = 0x03, /**< Timeout state */ - USART_STATE_ERROR = 0x04, /**< Error */ +typedef enum { + USART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + USART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + USART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + USART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ + USART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ + USART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */ + USART_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + USART_STATE_ERROR = 0x04U, /**< Error */ } usart_state_t; /** * @brief usart error codes */ -typedef enum -{ - USART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ - USART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ - USART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ - USART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ - USART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ - USART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +typedef enum { + USART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ + USART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ + USART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ + USART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ + USART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ + USART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ } usart_error_t; /** * @brief usart init structure definition */ -typedef struct -{ - uint32_t baud; /**< This member configures the Usart communication baud rate. */ - usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ - usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ - usart_parity_t parity; /**< Specifies the parity mode. +typedef struct { + uint32_t baud; /**< This member configures the Usart communication baud rate. */ + usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ + usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ + usart_parity_t parity; /**< Specifies the parity mode. @note When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits). */ - usart_mode_t mode; /**< Specifies wether the Receive or Transmit mode is enabled or disabled. */ - usart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled. */ - type_func_t over_sampling; /**< Specifies whether the Over sampling 8 is enabled or disabled. */ + usart_mode_t mode; /**< Specifies wether the Receive or Transmit mode is enabled or disabled. */ + usart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled. */ } usart_init_t; /** * @brief USART handle structure definition */ -typedef struct usart_handle_s -{ - USART_TypeDef *perh; /**< USART registers base address */ - usart_init_t init; /**< USART communication parameters */ - uint8_t *tx_buf; /**< Pointer to USART Tx transfer buffer */ - uint16_t tx_size; /**< USART Tx transfer size */ - uint16_t tx_count; /**< USART Tx transfer counter */ - uint8_t *rx_buf; /**< Pointer to USART Rx transfer buffer */ - uint16_t rx_size; /**< USART Rx Transfer size */ - uint16_t rx_count; /**< USART Rx Transfer Counter */ +typedef struct usart_handle_s { + USART_TypeDef *perh; /**< USART registers base address */ + usart_init_t init; /**< USART communication parameters */ + uint8_t *tx_buf; /**< Pointer to USART Tx transfer buffer */ + uint16_t tx_size; /**< USART Tx transfer size */ + uint16_t tx_count; /**< USART Tx transfer counter */ + uint8_t *rx_buf; /**< Pointer to USART Rx transfer buffer */ + uint16_t rx_size; /**< USART Rx Transfer size */ + uint16_t rx_count; /**< USART Rx Transfer Counter */ #ifdef ALD_DMA - dma_handle_t hdmatx; /**< USART Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< USART Rx DMA handle parameters */ + dma_handle_t hdmatx; /**< USART Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< USART Rx DMA handle parameters */ #endif - lock_state_t lock; /**< Locking object */ - usart_state_t state; /**< USART communication state */ - uint32_t err_code; /**< USART error code */ - - void (*tx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct usart_handle_s *arg); /**< Rx completed callback */ - void (*tx_rx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx & Rx completed callback */ - void (*error_cbk)(struct usart_handle_s *arg); /**< error callback */ + lock_state_t lock; /**< Locking object */ + usart_state_t state; /**< USART communication state */ + uint32_t err_code; /**< USART error code */ + + void (*tx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct usart_handle_s *arg); /**< Rx completed callback */ + void (*tx_rx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx & Rx completed callback */ + void (*error_cbk)(struct usart_handle_s *arg); /**< error callback */ } usart_handle_t; /** * @brief USART clock init structure definition */ -typedef struct -{ - usart_clock_t clk; /**< Pecifies whether the USART clock is enable or disable. */ - usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ - usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made. */ - usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted +typedef struct { + usart_clock_t clk; /**< Pecifies whether the USART clock is enable or disable. */ + usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ + usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made. */ + usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. */ } usart_clock_init_t; @@ -215,61 +200,56 @@ typedef struct /** * @brief usart_dma_request */ -typedef enum -{ - USART_DMA_REQ_TX = (1U << 7), /**< TX dma bit */ - USART_DMA_REQ_RX = (1U << 6), /**< RX dma bit */ +typedef enum { + USART_DMA_REQ_TX = (1U << 7), /**< TX dma bit */ + USART_DMA_REQ_RX = (1U << 6), /**< RX dma bit */ } usart_dma_req_t; /** * @brief usart_wakeup_methods */ -typedef enum -{ - USART_WAKEUP_IDLE = 0x0, /**< Wake up the machine when bus-line is idle */ - USART_WAKEUP_ADDR = 0x1, /**< Wake up the machine when match the address */ +typedef enum { + USART_WAKEUP_IDLE = 0x0U, /**< Wake up the machine when bus-line is idle */ + USART_WAKEUP_ADDR = 0x1U, /**< Wake up the machine when match the address */ } usart_wakeup_t; /** * @brief usart_IrDA_low_power */ -typedef enum -{ - USART_IrDA_MODE_NORMAL = 0x0, /**< Normal IrDA mode */ - USART_IrDA_MODE_LOW_POWER = 0x1, /**< Low-power IrDA mode */ +typedef enum { + USART_IrDA_MODE_NORMAL = 0x0U, /**< Normal IrDA mode */ + USART_IrDA_MODE_LOW_POWER = 0x1U, /**< Low-power IrDA mode */ } usart_IrDA_mode_t; /** * @brief USART interrupts definition */ -typedef enum -{ - USART_IT_PE = ((1U << 8) | (1U << 16)), /**< Parity error */ - USART_IT_TXE = ((1U << 7) | (1U << 16)), /**< Tx empty */ - USART_IT_TC = ((1U << 6) | (1U << 16)), /**< Tx complete */ - USART_IT_RXNE = ((1U << 5) | (1U << 16)), /**< Rx not empty */ - USART_IT_IDLE = ((1U << 4) | (1U << 16)), /**< Idle */ - USART_IT_CTS = ((1U << 10) | (1U << 18)), /**< CTS */ - USART_IT_ERR = ((1U << 0) | (1U << 18)), /**< Error */ - USART_IT_ORE = (1U << 3), /**< Overrun error */ - USART_IT_NE = (1U << 2), /**< Noise error */ - USART_IT_FE = (1U << 0), /**< Frame error */ +typedef enum { + USART_IT_PE = ((1U << 8) | (1U << 16)), /**< Parity error */ + USART_IT_TXE = ((1U << 7) | (1U << 16)), /**< Tx empty */ + USART_IT_TC = ((1U << 6) | (1U << 16)), /**< Tx complete */ + USART_IT_RXNE = ((1U << 5) | (1U << 16)), /**< Rx not empty */ + USART_IT_IDLE = ((1U << 4) | (1U << 16)), /**< Idle */ + USART_IT_CTS = ((1U << 10)| (1U << 18)), /**< CTS */ + USART_IT_ERR = ((1U << 0) | (1U << 18)), /**< Error */ + USART_IT_ORE = (1U << 3), /**< Overrun error */ + USART_IT_NE = (1U << 2), /**< Noise error */ + USART_IT_FE = (1U << 0), /**< Frame error */ } usart_it_t; /** * @brief USART flags */ -typedef enum -{ - USART_FLAG_CTS = (1U << 9), /**< CTS */ - USART_FLAG_TXE = (1U << 7), /**< Tx empty */ - USART_FLAG_TC = (1U << 6), /**< Tx complete */ - USART_FLAG_RXNE = (1U << 5), /**< Rx not empty */ - USART_FLAG_IDLE = (1U << 4), /**< Idle */ - USART_FLAG_ORE = (1U << 3), /**< Overrun error */ - USART_FLAG_NE = (1U << 2), /**< Noise error */ - USART_FLAG_FE = (1U << 1), /**< Frame error */ - USART_FLAG_PE = (1U << 0), /**< Parity error */ +typedef enum { + USART_FLAG_CTS = (1U << 9), /**< CTS */ + USART_FLAG_TXE = (1U << 7), /**< Tx empty */ + USART_FLAG_TC = (1U << 6), /**< Tx complete */ + USART_FLAG_RXNE = (1U << 5), /**< Rx not empty */ + USART_FLAG_IDLE = (1U << 4), /**< Idle */ + USART_FLAG_ORE = (1U << 3), /**< Overrun error */ + USART_FLAG_NE = (1U << 2), /**< Noise error */ + USART_FLAG_FE = (1U << 1), /**< Frame error */ + USART_FLAG_PE = (1U << 0), /**< Parity error */ } usart_flag_t; /** @@ -293,12 +273,12 @@ typedef enum * @{ */ #define USART_CLEAR_PEFLAG(handle) \ - do { \ - __IO uint32_t tmpreg; \ - tmpreg = (handle)->perh->STAT; \ - tmpreg = (handle)->perh->DATA; \ - UNUSED(tmpreg); \ - } while (0) +do { \ + __IO uint32_t tmpreg; \ + tmpreg = (handle)->perh->STAT; \ + tmpreg = (handle)->perh->DATA; \ + UNUSED(tmpreg); \ +} while (0) /** * @} */ @@ -339,7 +319,7 @@ typedef enum * @{ */ #define USART_HWCONTROL_CTS_ENABLE(handle) \ - (SET_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) + (SET_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) /** * @} */ @@ -348,7 +328,7 @@ typedef enum * @{ */ #define USART_HWCONTROL_CTS_DISABLE(handle) \ - (CLEAR_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) + (CLEAR_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) /** * @} */ @@ -357,7 +337,7 @@ typedef enum * @{ */ #define USART_HWCONTROL_RTS_ENABLE(handle) \ - (SET_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) + (SET_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) /** * @} */ @@ -366,7 +346,7 @@ typedef enum * @{ */ #define USART_HWCONTROL_RTS_DISABLE(handle) \ - (CLEAR_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) + (CLEAR_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) /** * @} */ @@ -383,9 +363,9 @@ typedef enum * @{ */ #define USART_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) -/** - * @} - */ + /** + * @} + */ /** * @} @@ -406,13 +386,13 @@ typedef enum ((x) == USART_PARITY_EVEN) || \ ((x) == USART_PARITY_ODD)) #define IS_USART_MODE(x) (((x) == USART_MODE_RX) || \ - ((x) == USART_MODE_TX) || \ - ((x) == USART_MODE_TX_RX)) + ((x) == USART_MODE_TX) || \ + ((x) == USART_MODE_TX_RX)) #define IS_USART_HARDWARE_FLOW_CONTROL(x)\ - (((x) == USART_HW_FLOW_CTL_NONE) || \ - ((x) == USART_HW_FLOW_CTL_RTS) || \ - ((x) == USART_HW_FLOW_CTL_CTS) || \ - ((x) == USART_HW_FLOW_CTL_RTS_CTS)) + (((x) == USART_HW_FLOW_CTL_NONE) || \ + ((x) == USART_HW_FLOW_CTL_RTS) || \ + ((x) == USART_HW_FLOW_CTL_CTS) || \ + ((x) == USART_HW_FLOW_CTL_RTS_CTS)) #define IS_USART_CLOCK(x) (((x) == USART_CLOCK_DISABLE) || \ ((x) == USART_CLOCK_ENABLE)) #define IS_USART_CPOL(x) (((x) == USART_CPOL_LOW) || ((x) == USART_CPOL_HIGH)) @@ -436,7 +416,7 @@ typedef enum ((x) == USART_IT_NE) || ((x) == USART_IT_FE) || \ ((x) == USART_IT_ERR)) #define IS_USART_CLEAR_IT(x) (((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ - ((x) == USART_IT_CTS)) + ((x) == USART_IT_CTS)) #define IS_USART_FLAG(x) (((x) == USART_FLAG_PE) || ((x) == USART_FLAG_TXE) || \ ((x) == USART_FLAG_TC) || ((x) == USART_FLAG_RXNE) || \ @@ -450,8 +430,8 @@ typedef enum #define IS_USART_ADDRESS(x) ((x) <= 0xF) #define IS_USART_DATA(x) ((x) <= 0x1FF) #define DUMMY_DATA 0xFFFF -#define USART_STATE_TX_MASK (1 << 4) -#define USART_STATE_RX_MASK (1 << 5) +#define USART_STATE_TX_MASK (1U << 4) +#define USART_STATE_RX_MASK (1U << 5) /** * @} @@ -509,7 +489,7 @@ ald_status_t ald_usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_b ald_status_t ald_usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, - uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); + uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); #endif /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_wdt.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_wdt.h index b2b0e2203ab5cbb3b988f6e8926a3ce60798090f..619f777324f9b9134f60cde25c2d7d6868cd724a 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_wdt.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_wdt.h @@ -38,12 +38,11 @@ extern "C" { /** * @brief Wwdt no dog window */ -typedef enum -{ - WWDT_WIN_25 = 0x0, /**< No dog window size: 25% */ - WWDT_WIN_50 = 0x1, /**< No dog window size: 50% */ - WWDT_WIN_75 = 0x2, /**< No dog window size: 75% */ - WWDT_WIN_00 = 0x3, /**< No dog window size: 0% */ +typedef enum { + WWDT_WIN_25 = 0x0U, /**< No dog window size: 25% */ + WWDT_WIN_50 = 0x1U, /**< No dog window size: 50% */ + WWDT_WIN_75 = 0x2U, /**< No dog window size: 75% */ + WWDT_WIN_00 = 0x3U, /**< No dog window size: 0% */ } wwdt_win_t; /** @@ -54,10 +53,10 @@ typedef enum * @defgroup WDT_Private_Macros WDT Private Macros * @{ */ -#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551);} -#define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFF);} -#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551);} -#define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFF);} +#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);} +#define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);} +#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);} +#define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);} /** * @} @@ -72,7 +71,7 @@ typedef enum (x == WWDT_WIN_75) || \ (x == WWDT_WIN_00)) #define IS_FUNC_STATE(x) (((x) == DISABLE) || \ - ((x) == ENABLE)) + ((x) == ENABLE)) /** * @} */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/type.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/type.h index 7bf1c1e543558d14b5db019e1cbc96bfef772173..54082f3f2192d488c395ba7a0329c17b7dd66375 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/type.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/type.h @@ -34,41 +34,36 @@ extern "C" { #define __isr__ -typedef enum -{ - RESET = 0x0, - SET = 0x1, +typedef enum { + RESET = 0x0U, + SET = 0x1U, } flag_status_t, it_status_t; -typedef enum -{ - BIT_RESET = 0x0, - BIT_SET = 0x1, +typedef enum { + BIT_RESET = 0x0U, + BIT_SET = 0x1U, } bit_status_t; -typedef enum -{ - DISABLE = 0x0, - ENABLE = 0x1, +typedef enum { + DISABLE = 0x0U, + ENABLE = 0x1U, } type_func_t; #define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) -typedef enum -{ - FALSE = 0x0, - TRUE = 0x1, +typedef enum { + FALSE = 0x0U, + TRUE = 0x1U, } type_bool_t; -typedef enum -{ - UNLOCK = 0x0, - LOCK = 0x1, +typedef enum { + UNLOCK = 0x0U, + LOCK = 0x1U, } lock_state_t; #define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) #define BIT(x) ((1U << (x))) -#define BITS(s, e) ((0xffffffff << (s)) & (0xffffffff >> (31 - (e)))) +#define BITS(s, e) ((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e)))) #define SET_BIT(reg, bit) ((reg) |= (bit)) #define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) #define READ_BIT(reg, bit) ((reg) & (bit)) @@ -77,18 +72,18 @@ typedef enum #define WRITE_REG(reg, val) ((reg) = (val)) #define READ_REG(reg) ((reg)) #define MODIFY_REG(reg, clearmask, setmask) \ - WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask))) + WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask))) #define UNUSED(x) ((void)(x)) #ifdef USE_ASSERT #define assert_param(x) \ - do { \ - if (!(x)) { \ - __disable_irq(); \ - while (1) \ - ; \ - } \ - } while (0) +do { \ + if (!(x)) { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ +} while (0) #else #define assert_param(x) #endif @@ -101,23 +96,23 @@ typedef enum __STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val) { - uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2); - *((volatile uint32_t *)tmp) = (uint32_t)val; + uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; } __STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val) { - uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2); - *((volatile uint32_t *)tmp) = (uint32_t)val; + uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; } #if defined ( __GNUC__ ) -#ifndef __weak -#define __weak __attribute__((weak)) -#endif /* __weak */ -#ifndef __packed -#define __packed __attribute__((__packed__)) -#endif /* __packed */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ #endif /* __GNUC__ */ #ifdef __cplusplus diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/utils.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/utils.h index d503e70a86c9a3b4190c6ff3b084e5d1a7b7faf2..619914c23afbc250d1c7fd6cb551820f70d473db 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/utils.h +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/utils.h @@ -18,7 +18,7 @@ #define __UTILS_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include @@ -46,23 +46,21 @@ extern uint32_t __systick_interval; /** * @brief ALD Status structures definition */ -typedef enum -{ - OK = 0x0, - ERROR = 0x1, - BUSY = 0x2, - TIMEOUT = 0x3 +typedef enum { + OK = 0x0U, /**< Status: OK */ + ERROR = 0x1U, /**< Status: ERROR */ + BUSY = 0x2U, /**< Status: BUSY */ + TIMEOUT = 0x3U, /**< Status: TIMEOUT */ } ald_status_t; /** * @brief SysTick interval definition */ -typedef enum -{ - SYSTICK_INTERVAL_1MS = 1000, /**< Interval is 1ms */ - SYSTICK_INTERVAL_10MS = 100, /**< Interval is 10ms */ - SYSTICK_INTERVAL_100MS = 10, /**< Interval is 100ms */ - SYSTICK_INTERVAL_1000MS = 1, /**< Interval is 1s */ +typedef enum { + SYSTICK_INTERVAL_1MS = 1000U, /**< Interval is 1ms */ + SYSTICK_INTERVAL_10MS = 100U, /**< Interval is 10ms */ + SYSTICK_INTERVAL_100MS = 10U, /**< Interval is 100ms */ + SYSTICK_INTERVAL_1000MS = 1U, /**< Interval is 1s */ } systick_interval_t; /** * @} @@ -71,25 +69,24 @@ typedef enum /** @defgroup ALD_Public_Macros Public Macros * @{ */ -#define ALD_MAX_DELAY 0xFFFFFFFF - +#define ALD_MAX_DELAY 0xFFFFFFFFU #define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET) #define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET) #define RESET_HANDLE_STATE(x) ((x)->state = 0) #define __LOCK(x) \ - do { \ - if ((x)->lock == LOCK) { \ - return BUSY; \ - } \ - else { \ - (x)->lock = LOCK; \ - } \ - } while (0) + do { \ + if ((x)->lock == LOCK) { \ + return BUSY; \ + } \ + else { \ + (x)->lock = LOCK; \ + } \ + } while (0) #define __UNLOCK(x) \ - do { \ - (x)->lock = UNLOCK; \ - } while (0) + do { \ + (x)->lock = UNLOCK; \ + } while (0) /** * @} @@ -98,6 +95,10 @@ typedef enum /** @defgroup ALD_Private_Macros Private Macros * @{ */ +#define MCU_UID0_ADDR 0x000403E0U +#define MCU_UID1_ADDR 0x000403E8U +#define MCU_UID2_ADDR 0x000403F0U +#define MCU_CHIPID_ADDR 0x000403F8U #define IS_PRIO(x) ((x) < 4) #define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \ ((x) == SYSTICK_INTERVAL_10MS) || \ @@ -140,7 +141,8 @@ ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, ui void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status); uint32_t ald_mcu_get_tick(void); uint32_t ald_mcu_get_cpu_id(void); - +void ald_mcu_get_uid(uint8_t *buf); +uint32_t ald_mcu_get_chipid(void); /** * @} */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_acmp.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_acmp.c index 3057d7d2463cd952b6bc0ea6331f4a7d3341b2ef..e480de1697bdb336f7987c49e96ca296abfcb784 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_acmp.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_acmp.c @@ -44,86 +44,82 @@ */ ald_status_t ald_acmp_init(acmp_handle_t *hperh) { - uint32_t tmp = 0; + uint32_t tmp = 0; - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - if (hperh->init.vdd_level > 63) - return ERROR; + if (hperh->init.vdd_level > 63) + return ERROR; - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode)); - assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time)); - assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel)); - assert_param(IS_ACMP_WARM_FUNC_TYPE(hperh->init.warm_func)); - assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.pos_port)); - assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.neg_port)); - assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval)); - assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode)); + assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time)); + assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel)); + assert_param(IS_ACMP_WARM_FUNC_TYPE(hperh->init.warm_func)); + assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.pos_port)); + assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.neg_port)); + assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval)); + assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge)); - __LOCK(hperh); + __LOCK(hperh); - tmp = hperh->perh->CON; + tmp = hperh->perh->CON; - tmp |= ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) | - (hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS)); + tmp |= ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) | + (hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS)); - hperh->perh->CON = tmp; + hperh->perh->CON = tmp; - tmp = hperh->perh->INPUTSEL; + tmp = hperh->perh->INPUTSEL; - tmp |= ((hperh->init.pos_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.neg_port << ACMP_INPUTSEL_NSEL_POSS) | - (hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS)); + tmp |= ((hperh->init.pos_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.neg_port << ACMP_INPUTSEL_NSEL_POSS) | + (hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS)); - hperh->perh->INPUTSEL = tmp; + hperh->perh->INPUTSEL = tmp; - if (hperh->init.warm_func == ACMP_WARM_DISABLE) - CLEAR_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK); - else - SET_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK); + if (hperh->init.warm_func == ACMP_WARM_DISABLE) + CLEAR_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK); + else + SET_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK); - switch (hperh->init.edge) - { - case ACMP_EDGE_NONE: - CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; + switch (hperh->init.edge) { + case ACMP_EDGE_NONE: + CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; - case ACMP_EDGE_FALL: - SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; + case ACMP_EDGE_FALL: + SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; - case ACMP_EDGE_RISE: - CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; + case ACMP_EDGE_RISE: + CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; - case ACMP_EDGE_ALL: - SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; + case ACMP_EDGE_ALL: + SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; - default: - break; - } + default: + break; + } - SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK); - tmp = 0; + tmp = 0; + while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) { + if (tmp++ >= 600000) { + __UNLOCK(hperh); + return ERROR; + } + } - while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) - { - if (tmp++ >= 600000) - { - __UNLOCK(hperh); - return ERROR; - } - } - - __UNLOCK(hperh); - return OK; + __UNLOCK(hperh); + return OK; } /** * @} @@ -147,20 +143,20 @@ ald_status_t ald_acmp_init(acmp_handle_t *hperh) */ ald_status_t ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state) { - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_IT_TYPE(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); - __LOCK(hperh); + __LOCK(hperh); - if (state) - hperh->perh->IES |= it; - else - hperh->perh->IEC |= it; + if (state) + hperh->perh->IES |= it; + else + hperh->perh->IEC |= it; - __UNLOCK(hperh); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -175,13 +171,13 @@ ald_status_t ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_ */ it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it) { - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_IT_TYPE(it)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_IT_TYPE(it)); - if (hperh->perh->IEV & it) - return SET; - else - return RESET; + if (hperh->perh->IEV & it) + return SET; + else + return RESET; } /** @@ -196,16 +192,15 @@ it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it) */ it_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) { - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_FLAG_TYPE(flag)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_FLAG_TYPE(flag)); - if (hperh->perh->RIF & flag) - { - __UNLOCK(hperh); - return SET; - } + if (hperh->perh->RIF & flag) { + __UNLOCK(hperh); + return SET; + } - return RESET; + return RESET; } /** @brief Clear the specified ACMP it flags. @@ -217,14 +212,14 @@ it_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) */ ald_status_t ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) { - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_FLAG_TYPE(flag)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_FLAG_TYPE(flag)); - __LOCK(hperh); - hperh->perh->IFC |= flag; - __UNLOCK(hperh); + __LOCK(hperh); + hperh->perh->IFC |= flag; + __UNLOCK(hperh); - return OK; + return OK; } /** @brief Set the specified acmp it flags. @@ -236,14 +231,14 @@ ald_status_t ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) */ ald_status_t acmp_set_it_mask(acmp_handle_t *hperh, acmp_it_t it) { - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_IT_TYPE(it)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_IT_TYPE(it)); - __LOCK(hperh); - hperh->perh->IFM |= it; - __UNLOCK(hperh); + __LOCK(hperh); + hperh->perh->IFM |= it; + __UNLOCK(hperh); - return OK; + return OK; } /** @brief Check whether the specified ACMP flag is set or not. @@ -257,16 +252,15 @@ ald_status_t acmp_set_it_mask(acmp_handle_t *hperh, acmp_it_t it) */ flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status) { - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_STATUS_TYPE(status)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_STATUS_TYPE(status)); - if (hperh->perh->STAT & status) - { - __UNLOCK(hperh); - return SET; - } + if (hperh->perh->STAT & status) { + __UNLOCK(hperh); + return SET; + } - return RESET; + return RESET; } /** * @} @@ -285,23 +279,19 @@ flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status) */ void ald_acmp_irq_handler(acmp_handle_t *hperh) { - if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_WARMUP) == SET)) - { - if (hperh->acmp_warmup_cplt_cbk) - hperh->acmp_warmup_cplt_cbk(hperh); - - ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP); - } - - if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_EDGE) == SET)) - { - if (hperh->acmp_edge_cplt_cbk) - hperh->acmp_edge_cplt_cbk(hperh); - - ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE); - } - - return; + if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_WARMUP) == SET)) { + if (hperh->acmp_warmup_cplt_cbk) + hperh->acmp_warmup_cplt_cbk(hperh); + ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP); + } + + if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_EDGE) == SET)) { + if (hperh->acmp_edge_cplt_cbk) + hperh->acmp_edge_cplt_cbk(hperh); + ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE); + } + + return; } /** @@ -314,22 +304,22 @@ void ald_acmp_irq_handler(acmp_handle_t *hperh) */ ald_status_t ald_acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config) { - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - if (config == NULL) - return ERROR; + if (config == NULL) + return ERROR; - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_INVERT_TYPE(config->gpio_inv)); - assert_param(IS_ACMP_OUT_FUNC_TYPE(config->out_func)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_INVERT_TYPE(config->gpio_inv)); + assert_param(IS_ACMP_OUT_FUNC_TYPE(config->out_func)); - __LOCK(hperh); - hperh->perh->CON |= (config->gpio_inv << ACMP_CON_OUTINV_POS); - hperh->perh->PORT = config->out_func; - __UNLOCK(hperh); + __LOCK(hperh); + hperh->perh->CON |= (config->gpio_inv << ACMP_CON_OUTINV_POS); + hperh->perh->PORT = config->out_func; + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -340,9 +330,9 @@ ald_status_t ald_acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *con */ uint8_t ald_acmp_out_result(acmp_handle_t *hperh) { - assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_TYPE(hperh->perh)); - return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS); + return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS); } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_adc.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_adc.c index 2019e5a948a337a2a9e99769f0f66514bff45faa..7f1f522c7af9d8b201c399258e283d8a6606bd91 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_adc.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_adc.c @@ -47,8 +47,8 @@ * @{ */ #ifdef ALD_DMA - static void adc_dma_normal_conv_cplt(void *arg); - static void adc_dma_error(void *arg); +static void adc_dma_normal_conv_cplt(void *arg); +static void adc_dma_error(void *arg); #endif /** * @} @@ -73,114 +73,96 @@ */ ald_status_t ald_adc_init(adc_handle_t *hperh) { - ald_status_t tmp_status = OK; - - if (hperh == NULL) - return ERROR; - - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.data_align)); - assert_param(IS_ADC_SCAN_MODE_TYPE(hperh->init.scan_mode)); - assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.clk_div)); - assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.neg_ref)); - assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.pos_ref)); - assert_param(IS_ADC_CONV_RES_TYPE(hperh->init.conv_res)); - assert_param(IS_ADC_NCH_LEN_TYPE(hperh->init.nch_len)); - assert_param(IS_ADC_DISC_MODE_TYPE(hperh->init.disc_mode)); - assert_param(IS_ADC_DISC_NBR_TYPE(hperh->init.disc_nbr)); - assert_param(IS_FUNC_STATE(hperh->init.cont_mode)); - assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_sel)); - - if (hperh->state == ADC_STATE_RESET) - { - hperh->error_code = ADC_ERROR_NONE; - hperh->lock = UNLOCK; - } - - if ((hperh->init.pos_ref == ADC_POS_REF_VDD) && (hperh->init.neg_ref == ADC_NEG_REF_VSS)) - { - ADC_ENABLE(hperh); - - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.neg_ref << ADC_CCR_VRNSEL_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.pos_ref << ADC_CCR_VRPSEL_POSS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, 1 << ADC_CCR_VCMBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, 1 << ADC_CCR_IREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, 1 << ADC_CCR_VREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, 6 << ADC_CCR_CKDIV_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, ADC_DATAALIGN_RIGHT << ADC_CON1_ALIGN_POS); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, ADC_CONV_RES_12 << ADC_CON0_RSEL_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, DISABLE << ADC_CON1_CM_POS); - MODIFY_REG(hperh->perh->NCHS1, ADC_NCHS1_NS1_MSK, ADC_CHANNEL_18 << ADC_NCHS1_NS1_POSS); - - hperh->perh->SMPT2 = 0x30; - - /* Start adc normal convert */ - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - - /* Wait convert finish */ - while (!READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK)); - - hperh->vdd_value = (hperh->perh->NCHDR & 0xfff); - - /* Get calibration VDD value */ - hperh->vdd_value = 2000 * 4096 / hperh->vdd_value; - } - - ADC_DISABLE(hperh); - ald_adc_reset(hperh); - hperh->state = ADC_STATE_BUSY_INTERNAL; - MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.data_align << ADC_CON1_ALIGN_POS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont_mode << ADC_CON1_CM_POS); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan_mode << ADC_CON0_SCANEN_POS); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.conv_res << ADC_CON0_RSEL_POSS); - - /* Enable discontinuous mode only if continuous mode is enabled */ - if (hperh->init.disc_mode == ADC_NCH_DISC_EN) - { - hperh->init.scan_mode = ENABLE; - SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nbr << ADC_CON0_ETRGN_POSS); - } - else if (hperh->init.disc_mode == ADC_ICH_DISC_EN) - { - hperh->init.scan_mode = ENABLE; - SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nbr << ADC_CON0_ETRGN_POSS); - } - else - { - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); - } - - if ((hperh->init.scan_mode == ENABLE) || (hperh->init.disc_mode == ADC_NCH_DISC_EN)) - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_len << ADC_CHSL_NSL_POSS); - - MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan_mode << ADC_CON0_SCANEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS); - /* if the ADC CLK less than 1MHZ,PWRMOD should be Enable*/ - MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.clk_div << ADC_CCR_CKDIV_POSS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.neg_ref << ADC_CCR_VRNSEL_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.pos_ref << ADC_CCR_VRPSEL_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS); - - if (tmp_status == OK) - { - hperh->error_code = ADC_ERROR_NONE; - hperh->state |= ADC_STATE_READY; - hperh->state &= ~(ADC_STATE_ERROR | ADC_STATE_NM_BUSY - | ADC_STATE_IST_BUSY | ADC_STATE_BUSY_INTERNAL); - } - - ald_adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE); - return tmp_status; + if (hperh == NULL) + return ERROR; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.align)); + assert_param(IS_FUNC_STATE(hperh->init.scan)); + assert_param(IS_ADC_NCH_NR_TYPE(hperh->init.nch_nr)); + assert_param(IS_ADC_DISC_MODE_TYPE(hperh->init.disc)); + assert_param(IS_ADC_DISC_NR_TYPE(hperh->init.disc_nr)); + assert_param(IS_ADC_CONV_BIT_TYPE(hperh->init.data_bit)); + assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.div)); + assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_sel)); + assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.n_ref)); + assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.p_ref)); + + if (hperh->state == ADC_STATE_RESET ) { + hperh->error_code = ADC_ERROR_NONE; + hperh->lock = UNLOCK; + } + + if ((hperh->init.p_ref == ADC_POS_REF_VDD) && (hperh->init.n_ref == ADC_NEG_REF_VSS)) { + ADC_ENABLE(hperh); + + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, 1 << ADC_CCR_VCMBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, 1 << ADC_CCR_IREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, 1 << ADC_CCR_VREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, 6 << ADC_CCR_CKDIV_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, ADC_DATAALIGN_RIGHT << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, ADC_CONV_BIT_12 << ADC_CON0_RSEL_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, DISABLE << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->NCHS1, ADC_NCHS1_NS1_MSK, ADC_CHANNEL_18 << ADC_NCHS1_NS1_POSS); + hperh->perh->SMPT2 = 0x30; + + /* Start adc normal convert */ + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + /* Wait convert finish */ + while (!READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK)); + hperh->vdd_value = (hperh->perh->NCHDR & 0xfff); + /* Get calibration VDD value */ + hperh->vdd_value = 2000 * 4096 / hperh->vdd_value; + } + + ADC_DISABLE(hperh); + ald_adc_reset(hperh); + hperh->state = ADC_STATE_BUSY; + MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.align << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.data_bit << ADC_CON0_RSEL_POSS); + + /* Enable discontinuous mode only if continuous mode is disable */ + if (hperh->init.disc == ADC_NCH_DISC_EN) { + hperh->init.scan = ENABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS); + } + else if (hperh->init.disc == ADC_ICH_DISC_EN) { + hperh->init.scan = ENABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS); + } + else { + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + } + + if ((hperh->init.scan == ENABLE) || (hperh->init.disc == ADC_NCH_DISC_EN)) + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_nr << ADC_CHSL_NSL_POSS); + + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.scan << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS); + /* if the ADC clock less than 1MHz,PWRMOD should be disable*/ + MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.div << ADC_CCR_CKDIV_POSS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS); + ald_adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE); + ADC_ENABLE(hperh); + + hperh->init.cont = DISABLE; + hperh->error_code = ADC_ERROR_NONE; + hperh->state = ADC_STATE_READY; + return OK; } /** @@ -192,41 +174,31 @@ ald_status_t ald_adc_init(adc_handle_t *hperh) */ ald_status_t ald_adc_reset(adc_handle_t *hperh) { - if (hperh == NULL) - return ERROR; - - assert_param(IS_ADC_TYPE(hperh->perh)); - - ADC_DISABLE(hperh); - - ald_adc_clear_flag_status(hperh, ADC_FLAG_AWD); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); - ald_adc_clear_flag_status(hperh, ADC_FLAG_OVR); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); - - WRITE_REG(hperh->perh->CON0, 0x0); - WRITE_REG(hperh->perh->CON1, 0x0); - WRITE_REG(hperh->perh->CCR, 0x0); - WRITE_REG(hperh->perh->WDTH, 0xFFF); - WRITE_REG(hperh->perh->WDTL, 0x0); - WRITE_REG(hperh->perh->ICHOFF[0], 0x0); - WRITE_REG(hperh->perh->ICHOFF[1], 0x0); - WRITE_REG(hperh->perh->ICHOFF[2], 0x0); - WRITE_REG(hperh->perh->ICHOFF[3], 0x0); - WRITE_REG(hperh->perh->ICHS, 0x0); - WRITE_REG(hperh->perh->NCHS1, 0x0); - WRITE_REG(hperh->perh->NCHS2, 0x0); - WRITE_REG(hperh->perh->NCHS3, 0x0); - WRITE_REG(hperh->perh->NCHS4, 0x0); - WRITE_REG(hperh->perh->SMPT1, 0x0); - WRITE_REG(hperh->perh->SMPT2, 0x0); - WRITE_REG(hperh->perh->CHSL, 0x0); - - hperh->state = ADC_STATE_RESET; - hperh->error_code = ADC_ERROR_NONE; - return OK; + assert_param(IS_ADC_TYPE(hperh->perh)); + + ADC_DISABLE(hperh); + WRITE_REG(hperh->perh->CLR, 0x30F); + WRITE_REG(hperh->perh->CON0, 0x0); + WRITE_REG(hperh->perh->CON1, 0x0); + WRITE_REG(hperh->perh->CCR, 0x0); + WRITE_REG(hperh->perh->WDTH, 0xFFF); + WRITE_REG(hperh->perh->WDTL, 0x0); + WRITE_REG(hperh->perh->ICHOFF[0], 0x0); + WRITE_REG(hperh->perh->ICHOFF[1], 0x0); + WRITE_REG(hperh->perh->ICHOFF[2], 0x0); + WRITE_REG(hperh->perh->ICHOFF[3], 0x0); + WRITE_REG(hperh->perh->ICHS, 0x0); + WRITE_REG(hperh->perh->NCHS1, 0x0); + WRITE_REG(hperh->perh->NCHS2, 0x0); + WRITE_REG(hperh->perh->NCHS3, 0x0); + WRITE_REG(hperh->perh->NCHS4, 0x0); + WRITE_REG(hperh->perh->SMPT1, 0x0); + WRITE_REG(hperh->perh->SMPT2, 0x0); + WRITE_REG(hperh->perh->CHSL, 0x0); + + hperh->state = ADC_STATE_RESET; + hperh->error_code = ADC_ERROR_NONE; + return OK; } /** * @} @@ -245,21 +217,13 @@ ald_status_t ald_adc_reset(adc_handle_t *hperh) */ ald_status_t ald_adc_normal_start(adc_handle_t *hperh) { - if (hperh == NULL) - return ERROR; + assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_TYPE(hperh->perh)); + ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - __LOCK(hperh); - ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); - hperh->state |= ADC_STATE_NM_BUSY; - __UNLOCK(hperh); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - - return OK; + return OK; } /** @@ -274,16 +238,11 @@ ald_status_t ald_adc_normal_start(adc_handle_t *hperh) */ ald_status_t ald_adc_normal_stop(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); - - __LOCK(hperh); - - ADC_DISABLE(hperh); - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_NM_EOC); - hperh->state |= ADC_STATE_READY; + assert_param(IS_ADC_TYPE(hperh->perh)); - __UNLOCK(hperh); - return OK; + ADC_DISABLE(hperh); + hperh->state = ADC_STATE_READY; + return OK; } /** @@ -300,39 +259,22 @@ ald_status_t ald_adc_normal_stop(adc_handle_t *hperh) */ ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = 0; - - assert_param(IS_ADC_TYPE(hperh->perh)); - - tickstart = ald_get_tick(); - - while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) - { - if (timeout != ALD_MAX_DELAY) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->state |= ADC_STATE_TIMEOUT; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - - hperh->state |= ADC_STATE_NM_EOC; - - if ((hperh->init.cont_mode == DISABLE) && (hperh->init.scan_mode == DISABLE)) - { - hperh->state &= ~ADC_STATE_NM_BUSY; - - if ((hperh->state & ADC_STATE_IST_BUSY) == 0) - hperh->state |= ADC_STATE_READY; - } - - return OK; + uint32_t _tick; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + _tick = ald_get_tick(); + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) { + if (timeout != ALD_MAX_DELAY ) { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { + hperh->state = ADC_STATE_TIMEOUT; + return TIMEOUT; + } + } + } + + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCHS | ADC_FLAG_NCH); + return OK; } /** @@ -347,28 +289,24 @@ ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t ti */ ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout) { - uint32_t tickstart = 0; - - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_EVENT_TYPE(event_type)); - - tickstart = ald_get_tick(); - - while (ald_adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) - { - if (timeout != ALD_MAX_DELAY) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->state |= ADC_STATE_TIMEOUT; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - - hperh->state |= ADC_STATE_AWD; - return OK; + uint32_t _tick; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_EVENT_TYPE(event_type)); + + _tick = ald_get_tick(); + while (ald_adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) { + if (timeout != ALD_MAX_DELAY ) { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { + hperh->state = ADC_STATE_TIMEOUT; + return TIMEOUT; + } + } + } + + + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_WDG); + return OK; } /** @@ -382,27 +320,15 @@ ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_ */ ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); - - __LOCK(hperh); - ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); - hperh->state |= ADC_STATE_NM_BUSY; - hperh->error_code = ADC_ERROR_NONE; - - if (READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)) - { - hperh->state &= ~(ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_IST_BUSY; - } - - __UNLOCK(hperh); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - ald_adc_interrupt_config(hperh, ADC_IT_NCH, ENABLE); + assert_param(IS_ADC_TYPE(hperh->perh)); - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + SET_BIT(hperh->state, ADC_STATE_BUSY_N); + ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH); + ald_adc_interrupt_config(hperh, ADC_IT_NCH, ENABLE); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - return OK; + return OK; } /** @@ -415,16 +341,13 @@ ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh) */ ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_TYPE(hperh->perh)); - __LOCK(hperh); - ADC_DISABLE(hperh); - ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); - hperh->state |= ADC_STATE_READY; - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); + ADC_DISABLE(hperh); + ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); - __UNLOCK(hperh); - return OK; + return OK; } #ifdef ALD_DMA @@ -440,58 +363,36 @@ ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh) */ ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) { - if ((hperh == NULL) || (buf == NULL) || (size == 0) || (channel > 5)) - return ERROR; - - assert_param(IS_ADC_TYPE(hperh->perh)); - - __LOCK(hperh); - ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); - hperh->state |= ADC_STATE_NM_BUSY; - - if (READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)) - { - hperh->state &= ~(ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_IST_BUSY; - } - - if ((hperh->state & ADC_STATE_IST_BUSY) != 0) - { - hperh->state &= ~(ADC_STATE_ERROR); - hperh->error_code &= ~(ADC_ERROR_OVR | ADC_ERROR_DMA); - } - else - { - hperh->state &= ~(ADC_STATE_ERROR); - hperh->error_code = ADC_ERROR_NONE; - } - - __UNLOCK(hperh); - - if (hperh->hdma.perh == NULL) - hperh->hdma.perh = DMA0; - - hperh->hdma.cplt_cbk = adc_dma_normal_conv_cplt; - hperh->hdma.cplt_arg = hperh; - hperh->hdma.err_cbk = adc_dma_error; - hperh->hdma.err_arg = hperh; - - ald_dma_config_struct(&hperh->hdma.config); - hperh->hdma.config.src = (void *)&hperh->perh->NCHDR; - hperh->hdma.config.dst = (void *)buf; - hperh->hdma.config.size = size; - hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma.config.msel = DMA_MSEL_ADC0; - hperh->hdma.config.msigsel = DMA_MSIGSEL_ADC; - hperh->hdma.config.channel = channel; - ald_dma_config_basic(&hperh->hdma); - - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - - return OK; + if ((buf == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + SET_BIT(hperh->state, ADC_STATE_BUSY_N); + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_cbk = adc_dma_normal_conv_cplt; + hperh->hdma.cplt_arg = hperh; + hperh->hdma.err_cbk = adc_dma_error; + hperh->hdma.err_arg = hperh; + + ald_dma_config_struct(&hperh->hdma.config); + hperh->hdma.config.src = (void *)&hperh->perh->NCHDR; + hperh->hdma.config.dst = (void *)buf; + hperh->hdma.config.size = size; + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.msel = DMA_MSEL_ADC0; + hperh->hdma.config.msigsel = DMA_MSIGSEL_ADC; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&hperh->hdma); + + ADC_ENABLE(hperh); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + return OK; } /** @@ -500,20 +401,17 @@ ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t s * ADC peripheral. * @param hperh: Pointer to a adc_handle_t structure that contains * the configuration information for the specified ADC module. + * @param channel: The DMA channel. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_stop_dma(adc_handle_t *hperh) +ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel) { - assert_param(IS_ADC_TYPE(hperh->perh)); - __LOCK(hperh); + assert_param(IS_ADC_TYPE(hperh->perh)); - ADC_DISABLE(hperh); - ald_pis_destroy(&hperh->hpis); - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); - hperh->state |= ADC_STATE_READY; - - __UNLOCK(hperh); - return OK; + ADC_DISABLE(hperh); + ald_dma_channel_config(hperh->hdma.perh, channel, DISABLE); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); + return OK; } /** @@ -523,19 +421,19 @@ ald_status_t adc_stop_dma(adc_handle_t *hperh) */ static void adc_dma_timer_trigger_cplt(void *arg) { - adc_timer_config_t *hperh = (adc_timer_config_t *)arg; - - ADC_DISABLE(&hperh->lh_adc); - ald_timer_base_stop(&hperh->lh_timer); + adc_timer_config_t *hperh = (adc_timer_config_t *)arg; - __UNLOCK(hperh); + ald_timer_base_stop(&hperh->h_timer); + ADC_DISABLE(&hperh->h_adc); + ald_dma_channel_config(hperh->h_dma.perh, hperh->dma_ch, DISABLE); + CLEAR_BIT(hperh->h_adc.state, ADC_STATE_BUSY_N); - if (hperh->lh_adc.adc_reg_cplt_cbk != NULL) - hperh->lh_adc.adc_reg_cplt_cbk(&hperh->lh_adc); + if (hperh->h_adc.normal_cplt_cbk) + hperh->h_adc.normal_cplt_cbk(&hperh->h_adc); + return; } - /** * @brief Config Timer trigger adc function * @param config: Pointer to a adc_timer_config_t structure that @@ -544,98 +442,90 @@ static void adc_dma_timer_trigger_cplt(void *arg) */ ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) { - __LOCK(config); - - config->lh_pis.perh = PIS; - config->lh_pis.init.producer_clk = PIS_CLK_PCLK1; - config->lh_pis.init.producer_edge = PIS_EDGE_NONE; - config->lh_pis.init.consumer_clk = PIS_CLK_PCLK2; - -#if defined (ES32F065x) - - if (config->p_timer == AD16C4T0) - config->lh_pis.init.producer_src = PIS_TIMER0_UPDATA; - -#elif defined(ES32F033x) || defined (ES32F093x) - - if (config->p_timer == GP16C4T0) - config->lh_pis.init.producer_src = PIS_TIMER0_UPDATA; - -#endif - - else if (config->p_timer == BS16T0) - config->lh_pis.init.producer_src = PIS_TIMER1_UPDATA; - else if (config->p_timer == GP16C2T0) - config->lh_pis.init.producer_src = PIS_TIMER2_UPDATA; - else if (config->p_timer == GP16C2T1) - config->lh_pis.init.producer_src = PIS_TIMER3_UPDATA; - else - return ERROR; - - if (config->p_adc == ADC0) - config->lh_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL; - else if (config->p_adc == ADC1) - config->lh_pis.init.consumer_trig = PIS_CH0_ADC1_NORMAL; - else - return ERROR; - - ald_pis_create(&config->lh_pis); - - /* Initialize TIMER0 */ - config->lh_timer.perh = config->p_timer; - config->lh_timer.init.prescaler = 0; - config->lh_timer.init.mode = TIMER_CNT_MODE_UP; - config->lh_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time); - config->lh_timer.init.clk_div = TIMER_CLOCK_DIV1; - config->lh_timer.init.re_cnt = 0; - ald_timer_base_init(&config->lh_timer); - - config->lh_adc.perh = config->p_adc; - config->lh_adc.init.data_align = ADC_DATAALIGN_RIGHT; - config->lh_adc.init.scan_mode = DISABLE; - config->lh_adc.init.cont_mode = DISABLE; - config->lh_adc.init.nch_len = ADC_NCH_LEN_1; - config->lh_adc.init.disc_mode = ADC_ALL_DISABLE; - config->lh_adc.init.disc_nbr = ADC_DISC_NBR_1; - config->lh_adc.init.conv_res = ADC_CONV_RES_12; - config->lh_adc.init.clk_div = ADC_CKDIV_16; - config->lh_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE; - config->lh_adc.init.neg_ref = config->n_ref; - config->lh_adc.init.pos_ref = config->p_ref; - config->lh_adc.adc_reg_cplt_cbk = config->adc_cplt_cbk; - config->lh_adc.adc_inj_cplt_cbk = NULL; - config->lh_adc.adc_out_of_win_cbk = NULL; - config->lh_adc.adc_error_cbk = NULL; - config->lh_adc.adc_ovr_cbk = NULL; - ald_adc_init(&config->lh_adc); - - config->lnm_config.channel = config->adc_ch; - config->lnm_config.rank = ADC_NCH_RANK_1; - config->lnm_config.samp_time = ADC_SAMPLETIME_1; - ald_adc_normal_channel_config(&config->lh_adc, &config->lnm_config); - - config->lh_dma.cplt_cbk = adc_dma_timer_trigger_cplt; - config->lh_dma.cplt_arg = config; - config->lh_dma.err_cbk = adc_dma_error; - config->lh_dma.err_arg = &config->lh_adc; - - ald_dma_config_struct(&config->lh_dma.config); - config->lh_dma.perh = DMA0; - config->lh_dma.config.src = (void *)&config->lh_adc.perh->NCHDR; - config->lh_dma.config.dst = (void *)config->buf; - config->lh_dma.config.size = config->size; - config->lh_dma.config.data_width = DMA_DATA_SIZE_HALFWORD; - config->lh_dma.config.src_inc = DMA_DATA_INC_NONE; - config->lh_dma.config.dst_inc = DMA_DATA_INC_HALFWORD; - config->lh_dma.config.msel = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1; - config->lh_dma.config.msigsel = DMA_MSIGSEL_ADC; - config->lh_dma.config.channel = config->dma_ch; - ald_dma_config_basic(&config->lh_dma); - - ADC_ENABLE(&config->lh_adc); - ald_timer_base_start(&config->lh_timer); - - return OK; + SET_BIT(config->h_adc.state, ADC_STATE_BUSY_N); + + config->h_pis.perh = PIS; + config->h_pis.init.producer_clk = PIS_CLK_PCLK1; + config->h_pis.init.producer_edge = PIS_EDGE_NONE; + config->h_pis.init.consumer_clk = PIS_CLK_PCLK2; + + #if defined (ES32F065x) + if (config->p_timer == AD16C4T0) + config->h_pis.init.producer_src = PIS_TIMER0_UPDATA; + #elif defined(ES32F033x) || defined (ES32F093x) + if (config->p_timer == GP16C4T0) + config->h_pis.init.producer_src = PIS_TIMER0_UPDATA; + #endif + else if (config->p_timer == BS16T0) + config->h_pis.init.producer_src = PIS_TIMER1_UPDATA; + else if (config->p_timer == GP16C2T0) + config->h_pis.init.producer_src = PIS_TIMER2_UPDATA; + else if (config->p_timer == GP16C2T1) + config->h_pis.init.producer_src = PIS_TIMER3_UPDATA; + else + return ERROR; + + if (config->p_adc == ADC0) + config->h_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL; + else + return ERROR; + + ald_pis_create(&config->h_pis); + + /* Initialize TIMER0 */ + config->h_timer.perh = config->p_timer; + config->h_timer.init.prescaler = 0; + config->h_timer.init.mode = TIMER_CNT_MODE_UP; + config->h_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time); + config->h_timer.init.clk_div = TIMER_CLOCK_DIV1; + config->h_timer.init.re_cnt = 0; + ald_timer_base_init(&config->h_timer); + + config->h_adc.perh = config->p_adc; + config->h_adc.init.align = ADC_DATAALIGN_RIGHT; + config->h_adc.init.scan = DISABLE; + config->h_adc.init.cont = DISABLE; + config->h_adc.init.nch_nr = ADC_NCH_NR_1; + config->h_adc.init.disc = ADC_ALL_DISABLE; + config->h_adc.init.disc_nr = ADC_DISC_NR_1; + config->h_adc.init.data_bit = ADC_CONV_BIT_12; + config->h_adc.init.div = ADC_CKDIV_128; + config->h_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE; + config->h_adc.init.n_ref = config->n_ref; + config->h_adc.init.p_ref = config->p_ref; + config->h_adc.normal_cplt_cbk = config->cplt_cbk; + config->h_adc.insert_cplt_cbk = NULL; + config->h_adc.wdg_cbk = NULL; + config->h_adc.error_cbk = NULL; + config->h_adc.ovr_cbk = NULL; + ald_adc_init(&config->h_adc); + ADC_ENABLE(&config->h_adc); + + config->config.ch = config->adc_ch; + config->config.idx = ADC_NCH_IDX_1; + config->config.samp = ADC_SAMPLETIME_4; + ald_adc_normal_channel_config(&config->h_adc, &config->config); + + config->h_dma.cplt_cbk = adc_dma_timer_trigger_cplt; + config->h_dma.cplt_arg = config; + config->h_dma.err_cbk = adc_dma_error; + config->h_dma.err_arg = &config->h_adc; + + ald_dma_config_struct(&config->h_dma.config); + config->h_dma.perh = DMA0; + config->h_dma.config.src = (void *)&config->h_adc.perh->NCHDR; + config->h_dma.config.dst = (void *)config->buf; + config->h_dma.config.size = config->size; + config->h_dma.config.data_width = DMA_DATA_SIZE_HALFWORD; + config->h_dma.config.src_inc = DMA_DATA_INC_NONE; + config->h_dma.config.dst_inc = DMA_DATA_INC_HALFWORD; + config->h_dma.config.msel = DMA_MSEL_ADC0; + config->h_dma.config.msigsel = DMA_MSIGSEL_ADC; + config->h_dma.config.channel = config->dma_ch; + ald_dma_config_basic(&config->h_dma); + ald_timer_base_start(&config->h_timer); + + return OK; } #endif @@ -647,10 +537,9 @@ ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) */ uint32_t ald_adc_normal_get_value(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_TYPE(hperh->perh)); - hperh->state &= ~ADC_STATE_NM_EOC; - return hperh->perh->NCHDR; + return hperh->perh->NCHDR; } /** @@ -662,43 +551,45 @@ uint32_t ald_adc_normal_get_value(adc_handle_t *hperh) */ uint32_t ald_adc_get_vdd_value(adc_handle_t *hperh) { - uint32_t value = 0; - - if ((hperh->init.pos_ref != ADC_POS_REF_VDD) || (hperh->init.neg_ref != ADC_NEG_REF_VSS)) - return 0; - - __LOCK(hperh); - ADC_ENABLE(hperh); - - /* Set adc and measure 2V */ - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, DISABLE << ADC_CCR_VRBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFOEN_MSK, DISABLE << ADC_CCR_VREFOEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, ENABLE << ADC_CCR_PWRMODSEL_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, 6 << ADC_CCR_CKDIV_POSS); - MODIFY_REG(hperh->perh->CON0, ADC_CON1_ALIGN_MSK, ADC_DATAALIGN_RIGHT << ADC_CON1_ALIGN_POS); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, ADC_CONV_RES_12 << ADC_CON0_RSEL_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, DISABLE << ADC_CON1_CM_POS); - MODIFY_REG(hperh->perh->NCHS1, ADC_NCHS1_NS1_MSK, ADC_CHANNEL_18 << ADC_NCHS1_NS1_POSS); - - hperh->perh->SMPT2 = 0x30; - /* Start adc normal convert */ - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - - /* Wait convert finish */ - while (!READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK)); - - value = (hperh->perh->NCHDR & 0xfff); - /* Get calibration VDD value */ - value = 2000 * 4096 / value; - hperh->vdd_value = value; - - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); - __UNLOCK(hperh); - - return value; + uint32_t value, _tmp[5]; + + if ((hperh->init.p_ref != ADC_POS_REF_VDD) || (hperh->init.n_ref != ADC_NEG_REF_VSS)) + return 0; + + _tmp[0] = hperh->perh->CCR; + _tmp[1] = hperh->perh->CON0; + _tmp[2] = hperh->perh->CON1; + _tmp[3] = hperh->perh->NCHS1; + _tmp[4] = hperh->perh->SMPT2; + + hperh->perh->CON0 = 0x0; + hperh->perh->CON1 = 0x0; + hperh->perh->NCHS1 = 0x0; + + ADC_ENABLE(hperh); + hperh->perh->CCR = 0x8B06; + MODIFY_REG(hperh->perh->CON0, ADC_CON1_ALIGN_MSK, ADC_DATAALIGN_RIGHT << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, ADC_CONV_BIT_12 << ADC_CON0_RSEL_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, DISABLE << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->NCHS1, ADC_NCHS1_NS1_MSK, ADC_CHANNEL_18 << ADC_NCHS1_NS1_POSS); + hperh->perh->SMPT2 = 0x30; + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + while (!READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK)); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS); + value = (hperh->perh->NCHDR & 0xfff); + value = value == 0 ? 1 : value; + value = (2000 << 12) / value; + hperh->vdd_value = value; + + hperh->perh->CCR = _tmp[0]; + hperh->perh->CON0 = _tmp[1]; + hperh->perh->CON1 = _tmp[2]; + hperh->perh->NCHS1 = _tmp[3]; + hperh->perh->SMPT2 = _tmp[4]; + ADC_DISABLE(hperh); + + return value; } /** @@ -710,25 +601,15 @@ uint32_t ald_adc_get_vdd_value(adc_handle_t *hperh) */ ald_status_t ald_adc_insert_start(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); - - __LOCK(hperh); - ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_IST_BUSY; + assert_param(IS_ADC_TYPE(hperh->perh)); - if ((hperh->state & ADC_STATE_NM_BUSY) == 0) - hperh->error_code = ADC_ERROR_NONE; + ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICH); - __UNLOCK(hperh); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); - if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) - { - SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); - } - - return OK; + return OK; } /** @@ -745,26 +626,11 @@ ald_status_t ald_adc_insert_start(adc_handle_t *hperh) */ ald_status_t ald_adc_insert_stop(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); - - __LOCK(hperh); - - if (((hperh->state & ADC_STATE_NM_BUSY) == 0) - && (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))) - { - ADC_DISABLE(hperh); - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY | ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_READY; - } - else - { - hperh->state |= ADC_STATE_ERROR; - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); - return OK; + assert_param(IS_ADC_TYPE(hperh->perh)); + + ADC_DISABLE(hperh); + hperh->state = ADC_STATE_READY; + return OK; } /** @@ -776,39 +642,23 @@ ald_status_t ald_adc_insert_stop(adc_handle_t *hperh) */ ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart; - - assert_param(IS_ADC_TYPE(hperh->perh)); + uint32_t _tick; - tickstart = ald_get_tick(); + assert_param(IS_ADC_TYPE(hperh->perh)); - while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) - { - if (timeout != ALD_MAX_DELAY) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->state |= ADC_STATE_TIMEOUT; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } + _tick = ald_get_tick(); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) { + if (timeout != ALD_MAX_DELAY) { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { + hperh->state = ADC_STATE_TIMEOUT; + return TIMEOUT; + } + } + } - hperh->state |= ADC_STATE_IST_EOC; - - hperh->state &= ~(ADC_STATE_IST_BUSY); - - if ((hperh->state & ADC_STATE_NM_BUSY) == 0) - hperh->state |= ADC_STATE_READY; - - hperh->state &= ~(ADC_STATE_TIMEOUT); - __UNLOCK(hperh); - return OK; + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICHS | ADC_FLAG_ICH); + return OK; } /** @@ -821,24 +671,17 @@ ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t ti */ ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); - - __LOCK(hperh); - ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_IST_BUSY; + assert_param(IS_ADC_TYPE(hperh->perh)); - if ((hperh->state & ADC_STATE_NM_BUSY) == 0) - hperh->error_code = ADC_ERROR_NONE; + SET_BIT(hperh->state, ADC_STATE_BUSY_I); + ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICHS | ADC_FLAG_ICH); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, ENABLE); - __UNLOCK(hperh); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); - ald_adc_interrupt_config(hperh, ADC_IT_ICH, ENABLE); + if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); - if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) - SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); - - return OK; + return OK; } /** @@ -856,72 +699,27 @@ ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh) */ ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); - - __LOCK(hperh); - - if (((hperh->state & ADC_STATE_NM_BUSY) == 0) - && (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))) - { - ADC_DISABLE(hperh); - ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); - hperh->state |= ADC_STATE_READY; - } - else - { - ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); - hperh->state |= ADC_STATE_ERROR; - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); - return OK; + assert_param(IS_ADC_TYPE(hperh->perh)); + + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_I); + ADC_DISABLE(hperh); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); + return OK; } /** * @brief Get ADC insert group conversion result. * @param hperh: Pointer to a adc_handle_t structure that contains * the configuration information for the specified ADC module. - * @param ih_rank: the converted ADC insert rank. - * This parameter can be one of the following values: - * @arg ADC_INJ_RANK_1: insert Channel1 selected - * @arg ADC_INJ_RANK_2: insert Channel2 selected - * @arg ADC_INJ_RANK_3: insert Channel3 selected - * @arg ADC_INJ_RANK_4: insert Channel4 selected + * @param idx: Index of the insert channel. * @retval ADC group insert conversion data */ -uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank) +uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t idx) { - uint32_t tmp; - - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_ICH_RANK_TYPE(ih_rank)); + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_ICH_IDX_TYPE(idx)); - switch (ih_rank) - { - case ADC_ICH_RANK_1: - tmp = hperh->perh->ICHDR[0]; - break; - - case ADC_ICH_RANK_2: - tmp = hperh->perh->ICHDR[1]; - break; - - case ADC_ICH_RANK_3: - tmp = hperh->perh->ICHDR[2]; - break; - - case ADC_ICH_RANK_4: - tmp = hperh->perh->ICHDR[3]; - break; - - default: - break; - } - - return tmp; + return hperh->perh->ICHDR[idx - 1]; } /** @@ -932,70 +730,40 @@ uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank) */ void ald_adc_irq_handler(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); - - if (ald_adc_get_it_status(hperh, ADC_IT_NCH) && ald_adc_get_flag_status(hperh, ADC_FLAG_NCH)) - { - if ((hperh->state & ADC_STATE_ERROR) == 0) - hperh->state |= ADC_STATE_NM_EOC; - - if (hperh->init.cont_mode == DISABLE) - { - ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); - hperh->state &= ~(ADC_STATE_NM_BUSY); - - if ((hperh->state & ADC_STATE_IST_BUSY) == 0) - hperh->state |= ADC_STATE_READY; - } - - if (hperh->adc_reg_cplt_cbk != NULL) - hperh->adc_reg_cplt_cbk(hperh); - - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - } - - if (ald_adc_get_it_status(hperh, ADC_IT_ICH) && ald_adc_get_flag_status(hperh, ADC_FLAG_ICH)) - { - if ((hperh->state & ADC_STATE_ERROR) == 0) - hperh->state |= ADC_STATE_IST_EOC; - - if ((!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) - && (hperh->init.cont_mode == DISABLE)) - { - ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); - hperh->state &= ~(ADC_STATE_IST_BUSY); - - if ((hperh->state & ADC_STATE_NM_BUSY) == 0) - hperh->state |= ADC_STATE_READY; - } - - if (hperh->adc_inj_cplt_cbk != NULL) - hperh->adc_inj_cplt_cbk(hperh); - - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); - } - - if (ald_adc_get_it_status(hperh, ADC_IT_AWD) && ald_adc_get_flag_status(hperh, ADC_FLAG_AWD)) - { - hperh->state |= ADC_STATE_AWD; - - if (hperh->adc_out_of_win_cbk != NULL) - hperh->adc_out_of_win_cbk(hperh); - - ald_adc_clear_flag_status(hperh, ADC_FLAG_AWD); - } - - if (ald_adc_get_it_status(hperh, ADC_IT_OVR) && ald_adc_get_flag_status(hperh, ADC_FLAG_OVR)) - { - ald_adc_clear_flag_status(hperh, ADC_FLAG_OVR); - hperh->error_code |= ADC_ERROR_OVR; - hperh->state |= ADC_STATE_ERROR; - - if (hperh->adc_ovr_cbk != NULL) - hperh->adc_ovr_cbk(hperh); - } + assert_param(IS_ADC_TYPE(hperh->perh)); + + if (ald_adc_get_it_status(hperh, ADC_IT_NCH) && ald_adc_get_flag_status(hperh, ADC_FLAG_NCH)) { + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); + + if (hperh->normal_cplt_cbk) + hperh->normal_cplt_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ADC_IT_ICH) && ald_adc_get_flag_status(hperh, ADC_FLAG_ICH)) { + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICH | ADC_FLAG_ICHS); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_I); + + if (hperh->insert_cplt_cbk) + hperh->insert_cplt_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ADC_IT_AWD) && ald_adc_get_flag_status(hperh, ADC_FLAG_AWD)) { + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_WDG); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_AWD); + + if (hperh->wdg_cbk) + hperh->wdg_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ADC_IT_OVR) && ald_adc_get_flag_status(hperh, ADC_FLAG_OVR)) { + WRITE_REG(hperh->perh->CLR, ADC_FLAG_OVR); + hperh->error_code |= ADC_ERROR_OVR; + hperh->state |= ADC_STATE_ERROR; + + if (hperh->ovr_cbk) + hperh->ovr_cbk(hperh); + } } /** @@ -1017,47 +785,39 @@ void ald_adc_irq_handler(adc_handle_t *hperh) */ ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config) { - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); - assert_param(IS_ADC_NCH_RANK_TYPE(config->rank)); - assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp_time)); - - __LOCK(hperh); - - if (config->rank <= ADC_NCH_RANK_4) - { - hperh->perh->NCHS1 &= ~(0x1f << ((config->rank - 1) << 3)); - hperh->perh->NCHS1 |= (config->channel << ((config->rank - 1) << 3)); - } - else if (config->rank <= ADC_NCH_RANK_8) - { - hperh->perh->NCHS2 &= ~(0x1f << ((config->rank - 5) << 3)); - hperh->perh->NCHS2 |= (config->channel << ((config->rank - 5) << 3)); - } - else if (config->rank <= ADC_NCH_RANK_12) - { - hperh->perh->NCHS3 &= ~(0x1f << ((config->rank - 9) << 3)); - hperh->perh->NCHS3 |= (config->channel << ((config->rank - 9) << 3)); - } - else - { - hperh->perh->NCHS4 &= ~(0x1f << ((config->rank - 13) << 3)); - hperh->perh->NCHS4 |= (config->channel << ((config->rank - 13) << 3)); - } - - if (config->channel <= 15) - { - hperh->perh->SMPT1 &= ~(0x03 << (config->channel << 1)); - hperh->perh->SMPT1 |= config->samp_time << (config->channel << 1); - } - else - { - hperh->perh->SMPT2 &= ~(0x03 << ((config->channel - 16) << 1)); - hperh->perh->SMPT2 |= config->samp_time << ((config->channel - 16) << 1); - } - - __UNLOCK(hperh); - return OK; + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + assert_param(IS_ADC_NCH_IDX_TYPE(config->idx)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp)); + + if (config->idx <= ADC_NCH_IDX_4 ) { + hperh->perh->NCHS1 &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); + hperh->perh->NCHS1 |= (config->ch << (uint32_t)((config->idx - 1) << 3)); + } + else if (config->idx <= ADC_NCH_IDX_8) { + hperh->perh->NCHS2 &= ~(0x1f << (uint32_t)((config->idx - 5) << 3)); + hperh->perh->NCHS2 |= (config->ch << (uint32_t)((config->idx - 5) << 3)); + } + else if (config->idx <= ADC_NCH_IDX_12) { + hperh->perh->NCHS3 &= ~(0x1f << (uint32_t)((config->idx - 9) << 3)); + hperh->perh->NCHS3 |= (config->ch << (uint32_t)((config->idx - 9) << 3)); + } + else { + hperh->perh->NCHS4 &= ~(0x1f << (uint32_t)((config->idx - 13) << 3)); + hperh->perh->NCHS4 |= (config->ch << (uint32_t)((config->idx - 13) << 3)); + } + + if (config->ch <= 15) { + hperh->perh->SMPT1 &= ~(0x03 << (uint32_t)(config->ch << 1)); + hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 1); + } + else { + hperh->perh->SMPT2 &= ~(0x03 << (uint32_t)((config->ch - 16) << 1)); + hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - 16) << 1); + } + + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_SCANEN_MSK); + return OK; } /** @@ -1070,121 +830,52 @@ ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t * */ ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config) { - uint8_t tmp1, tmp2; - ald_status_t tmp_status = OK; - - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); - assert_param(IS_ADC_ICH_RANK_TYPE(config->rank)); - assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp_time)); - assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset)); - assert_param(IS_ADC_NBR_OF_IST_TYPE(config->ich_len)); - assert_param(IS_FUNC_STATE(config->auto_inj)); - - __LOCK(hperh); - - if (hperh->init.scan_mode == DISABLE) - { - switch (config->rank) - { - case ADC_ICH_RANK_1: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS1_MSK, config->channel << ADC_ICHS_IS1_POSS); - break; - - case ADC_ICH_RANK_2: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS2_MSK, config->channel << ADC_ICHS_IS2_POSS); - break; - - case ADC_ICH_RANK_3: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS3_MSK, config->channel << ADC_ICHS_IS3_POSS); - break; - - case ADC_ICH_RANK_4: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS4_MSK, config->channel << ADC_ICHS_IS4_POSS); - break; - - default: - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_INTERNAL; - tmp_status = ERROR; - break; - } - } - else - { - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->ich_len << ADC_CHSL_ISL_POSS); - tmp1 = config->rank ; - tmp2 = config->ich_len; - - if (tmp1 <= tmp2) - { - hperh->perh->ICHS &= ~(0x1f << ((tmp1 - 1) << 3)); - hperh->perh->ICHS |= config->channel - << ((tmp1 - 1) << 3); - } - else - { - hperh->perh->ICHS &= ~(0x1f << ((tmp1 - 1) << 3)); - hperh->perh->ICHS |= config->channel - << ((tmp1 - 1) << 3); - } - } - - if (config->auto_inj == ENABLE) - { - SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); - } - - if (hperh->init.disc_mode == ADC_ICH_DISC_EN) - { - if (config->auto_inj == DISABLE) - { - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->ich_len << ADC_CHSL_ISL_POSS); - SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); - } - else - { - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_INTERNAL; - tmp_status = ERROR; - } - } - - if (config->channel <= 15) - { - hperh->perh->SMPT1 &= ~(0x03 << (config->channel << 1)); - hperh->perh->SMPT1 |= config->samp_time << (config->channel << 1); - } - else - { - hperh->perh->SMPT2 &= ~(0x03 << ((config->channel - 16) << 1)); - hperh->perh->SMPT2 |= config->samp_time << ((config->channel - 16) << 1); - } - - switch (config->rank) - { - case ADC_ICH_RANK_1: - hperh->perh->ICHOFF[0] = config->offset; - break; - - case ADC_ICH_RANK_2: - hperh->perh->ICHOFF[1] = config->offset; - break; - - case ADC_ICH_RANK_3: - hperh->perh->ICHOFF[2] = config->offset; - break; - - case ADC_ICH_RANK_4: - hperh->perh->ICHOFF[3] = config->offset; - break; - - default: - break; - } - - __UNLOCK(hperh); - return tmp_status; + ald_status_t status = OK; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + assert_param(IS_ADC_ICH_IDX_TYPE(config->idx)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp)); + assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset)); + assert_param(IS_ADC_ICH_NR_TYPE(config->nr)); + assert_param(IS_FUNC_STATE(config->auto_m)); + + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nr << ADC_CHSL_ISL_POSS); + hperh->perh->ICHS &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); + hperh->perh->ICHS |= config->ch << (uint32_t)((config->idx - 1) << 3); + + if (config->nr > 0) + SET_BIT(hperh->perh->CON0, ADC_CON0_SCANEN_MSK); + else + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_SCANEN_MSK); + + if (config->auto_m == ENABLE) + SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); + else + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); + + if (hperh->init.disc == ADC_ICH_DISC_EN) { + if (config->auto_m == DISABLE) { + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + } + else { + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_INTERNAL; + status = ERROR; + } + } + + if (config->ch <= 15) { + hperh->perh->SMPT1 &= ~(0x03U << ((uint32_t)config->ch << 1)); + hperh->perh->SMPT1 |= config->samp << ((uint32_t)config->ch << 1); + } + else { + hperh->perh->SMPT2 &= ~(0x03U << (((uint32_t)config->ch - 16) << 1)); + hperh->perh->SMPT2 |= config->samp << (((uint32_t)config->ch - 16) << 1); + } + + hperh->perh->ICHOFF[config->idx] = config->offset; + return status; } /** @@ -1196,38 +887,35 @@ ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t * */ ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config) { - - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->watchdog_mode)); - assert_param(IS_FUNC_STATE(config->it_mode)); - assert_param(IS_HTR_TYPE(config->high_threshold)); - assert_param(IS_LTR_TYPE(config->low_threshold)); - - __LOCK(hperh); - - if ((config->watchdog_mode == ADC_ANAWTD_SING_NM) - || (config->watchdog_mode == ADC_ANAWTD_SING_IST) - || (config->watchdog_mode == ADC_ANAWTD_SING_NMIST)) - assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); - - if (config->it_mode == DISABLE) - ald_adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE); - else - ald_adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE); - - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK); - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK); - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK); - hperh->perh->CON0 |= config->watchdog_mode; - - if (READ_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK)) - MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->channel << ADC_CON0_AWDCH_POSS); - - WRITE_REG(hperh->perh->WDTL, config->low_threshold); - WRITE_REG(hperh->perh->WDTH, config->high_threshold); - - __UNLOCK(hperh); - return OK; + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->mode)); + assert_param(IS_FUNC_STATE(config->interrupt)); + assert_param(IS_HTR_TYPE(config->high_thrd)); + assert_param(IS_LTR_TYPE(config->low_thrd)); + + if ((config->mode == ADC_ANAWTD_SING_NM) + || (config->mode == ADC_ANAWTD_SING_IST) + || (config->mode == ADC_ANAWTD_SING_NMIST)) + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + + if (config->interrupt == DISABLE) + ald_adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE); + else + ald_adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE); + + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK); + hperh->perh->CON0 |= config->mode; + + if (READ_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK)) + MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->ch << ADC_CON0_AWDCH_POSS); + + WRITE_REG(hperh->perh->WDTL, config->low_thrd); + WRITE_REG(hperh->perh->WDTH, config->high_thrd); + SET_BIT(hperh->state, ADC_STATE_BUSY_WDG); + + return OK; } /** @@ -1242,16 +930,16 @@ ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_ */ void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state) { - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_IT_TYPE(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - SET_BIT(hperh->perh->CON0, it); - else - CLEAR_BIT(hperh->perh->CON0, it); + if (state == ENABLE) + SET_BIT(hperh->perh->CON0, it); + else + CLEAR_BIT(hperh->perh->CON0, it); - return; + return; } /** @@ -1265,13 +953,13 @@ void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t stat */ it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it) { - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_IT_TYPE(it)); + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IT_TYPE(it)); - if (READ_BIT(hperh->perh->CON0, it)) - return SET; + if (READ_BIT(hperh->perh->CON0, it)) + return SET; - return RESET; + return RESET; } /** @brief Check whether the specified ADC flag is set or not. @@ -1284,13 +972,13 @@ it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it) */ flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag) { - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_FLAGS_TYPE(flag)); + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_FLAGS_TYPE(flag)); - if (READ_BIT(hperh->perh->STAT, flag)) - return SET; + if (READ_BIT(hperh->perh->STAT, flag)) + return SET; - return RESET; + return RESET; } /** @brief Clear the specified ADC pending flags. @@ -1301,11 +989,11 @@ flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag) */ void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag) { - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_FLAGS_TYPE(flag)); + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_FLAGS_TYPE(flag)); - WRITE_REG(hperh->perh->CLR, flag); - return; + WRITE_REG(hperh->perh->CLR, flag); + return; } /** * @} @@ -1324,7 +1012,7 @@ void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag) */ uint32_t ald_adc_get_state(adc_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** @@ -1335,7 +1023,7 @@ uint32_t ald_adc_get_state(adc_handle_t *hperh) */ uint32_t ald_adc_get_error(adc_handle_t *hperh) { - return hperh->error_code; + return hperh->error_code; } /** @@ -1358,10 +1046,10 @@ uint32_t ald_adc_get_error(adc_handle_t *hperh) */ static void adc_dma_normal_conv_cplt(void *arg) { - adc_handle_t *hperh = (adc_handle_t *)arg; + adc_handle_t *hperh = (adc_handle_t *)arg; - if (hperh->adc_reg_cplt_cbk != NULL) - hperh->adc_reg_cplt_cbk(hperh); + if (hperh->normal_cplt_cbk) + hperh->normal_cplt_cbk(hperh); } @@ -1372,12 +1060,12 @@ static void adc_dma_normal_conv_cplt(void *arg) */ static void adc_dma_error(void *arg) { - adc_handle_t *hperh = (adc_handle_t *)arg; - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_DMA; + adc_handle_t *hperh = (adc_handle_t *)arg; + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_DMA; - if (hperh->adc_error_cbk != NULL) - hperh->adc_error_cbk(hperh); + if (hperh->error_cbk) + hperh->error_cbk(hperh); } #endif /** diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_bkpc.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_bkpc.c index 7035bc506719ee6d2087ea7f769ff69bc515c95b..a3852bdb2277845f25dc2d15c188bd8363702156 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_bkpc.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_bkpc.c @@ -41,7 +41,7 @@ ============================================================================== [..] This section provides functions allowing to: (+) ald_bkpc_ldo_config() API can configure LDO in backup field. - (+) ald_bkpc_bor_config() API can configure BOR in backup field. + (+) ald_bkpc_standby_wakeup_config() API can configure STANDBY wakeup. @endverbatim * @{ @@ -55,40 +55,44 @@ */ void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state) { - assert_param(IS_BKPC_LDO_OUTPUT(output)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_BKPC_LDO_OUTPUT(output)); + assert_param(IS_FUNC_STATE(state)); - BKPC_UNLOCK(); - MODIFY_REG(BKPC->CR, BKPC_CR_MT_STDB_MSK, state << BKPC_CR_MT_STDB_POS); + BKPC_UNLOCK(); + MODIFY_REG(BKPC->CR, BKPC_CR_MT_STDB_MSK, state << BKPC_CR_MT_STDB_POS); - if (state) - MODIFY_REG(BKPC->CR, BKPC_CR_LDO_VSEL_MSK, output << BKPC_CR_LDO_VSEL_POSS); + if (state) + MODIFY_REG(BKPC->CR, BKPC_CR_LDO_VSEL_MSK, output << BKPC_CR_LDO_VSEL_POSS); - BKPC_LOCK(); - return; + BKPC_LOCK(); + return; } /** - * @brief Configure bor voltage in backup field - * @param vol: Voltage select. - * @param state: DISABLE/ENABLE. + * @brief Configure standby wakeup in backup field + * @param port: Wakeup port + * @param level: HIGH/LOW. * @retval None */ -void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state) +void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level) { - assert_param(IS_BKPC_BOR_VOL(vol)); - assert_param(IS_FUNC_STATE(state)); - - BKPC_UNLOCK(); - MODIFY_REG(BKPC->PCR, BKPC_PCR_BOREN_MSK, state << BKPC_PCR_BOREN_POS); - - if (state) - MODIFY_REG(BKPC->PCR, BKPC_PCR_BORS_MSK, vol << BKPC_PCR_BORS_POSS); - - BKPC_LOCK(); - return; - - + assert_param(IS_BKPC_WAKEUP_PORT(port)); + assert_param(IS_BKPC_WAKEUP_LEVEL(level)); + + if (port == PMU_STANDBY_PORT_SEL_NONE) { + BKPC_UNLOCK(); + CLEAR_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK); + BKPC_LOCK(); + return; + } + + BKPC_UNLOCK(); + SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK); + MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS); + MODIFY_REG(BKPC->CR, BKPC_CR_WKPOL_MSK, level << BKPC_CR_WKPOL_POS); + BKPC_LOCK(); + + return; } /** * @} @@ -117,13 +121,13 @@ void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state) */ void ald_bkpc_write_ram(uint8_t idx, uint32_t value) { - assert_param(IS_BKPC_RAM_IDX(idx)); + assert_param(IS_BKPC_RAM_IDX(idx)); - RTC_UNLOCK(); - WRITE_REG(RTC->BKPR[idx], value); - RTC_LOCK(); + RTC_UNLOCK(); + WRITE_REG(RTC->BKPR[idx], value); + RTC_LOCK(); - return; + return; } /** @@ -133,9 +137,9 @@ void ald_bkpc_write_ram(uint8_t idx, uint32_t value) */ uint32_t ald_bkpc_read_ram(uint8_t idx) { - assert_param(IS_BKPC_RAM_IDX(idx)); + assert_param(IS_BKPC_RAM_IDX(idx)); - return READ_REG(RTC->BKPR[idx]); + return READ_REG(RTC->BKPR[idx]); } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_calc.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_calc.c index 26a67f249377d3d27d137bacd4a0af09dd0f10f2..ec2400453d960401cc3acbc2b0b8ffbb5734b7e6 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_calc.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_calc.c @@ -45,16 +45,15 @@ /** * @brief Square root operation. - * @param data: The data; + * @param data: The radicand * @retval The value of square root. */ uint32_t ald_calc_sqrt(uint32_t data) { - WRITE_REG(CALC->RDCND, data); + WRITE_REG(CALC->RDCND, data); + while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK)); - while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK)); - - return READ_REG(CALC->SQRTRES); + return READ_REG(CALC->SQRTRES); } /** @@ -66,15 +65,15 @@ uint32_t ald_calc_sqrt(uint32_t data) */ uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder) { - CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); - SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); - WRITE_REG(CALC->DIVDR, dividend); - WRITE_REG(CALC->DIVSR, divisor); + CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); + SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); + WRITE_REG(CALC->DIVDR, dividend); + WRITE_REG(CALC->DIVSR, divisor); - while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); + while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); - *remainder = READ_REG(CALC->DIVRR); - return READ_REG(CALC->DIVQR); + *remainder = READ_REG(CALC->DIVRR); + return READ_REG(CALC->DIVQR); } /** @@ -86,15 +85,15 @@ uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder) */ int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder) { - SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); - SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); - WRITE_REG(CALC->DIVDR, dividend); - WRITE_REG(CALC->DIVSR, divisor); + SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); + SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); + WRITE_REG(CALC->DIVDR, dividend); + WRITE_REG(CALC->DIVSR, divisor); - while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); + while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); - *remainder = READ_REG(CALC->DIVRR); - return READ_REG(CALC->DIVQR); + *remainder = READ_REG(CALC->DIVRR); + return READ_REG(CALC->DIVQR); } /** @@ -103,10 +102,10 @@ int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder) */ flag_status_t ald_calc_get_dz_status(void) { - if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK)) - return SET; + if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK)) + return SET; - return RESET; + return RESET; } /** diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_cmu.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_cmu.c index f5a6016d23ce682b856404f17ac3b7f605913c55..e43b12c7d1a143c66e7cd4e0fcf79f1abe54c063 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_cmu.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_cmu.c @@ -125,7 +125,7 @@ * @defgroup CMU_Private_Variables CMU Private Variables * @{ */ -uint32_t __system_clock = 24000000; +uint32_t __system_clock = 24000000U; /** * @} */ @@ -143,12 +143,12 @@ uint32_t __system_clock = 24000000; static void cmu_clock_update(uint32_t clock) { - __system_clock = clock; + __system_clock = clock; - if (clock > 1000000) - ald_tick_init(TICK_INT_PRIORITY); + if (clock > 1000000) + ald_tick_init(TICK_INT_PRIORITY); - return; + return; } /** @@ -157,69 +157,61 @@ static void cmu_clock_update(uint32_t clock) */ void ald_cmu_irq_handler(void) { - /* HOSC stop */ - if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) - { - SYSCFG_UNLOCK(); - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); - SYSCFG_LOCK(); - - if ((READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) - && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) - || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) - cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); - - ald_cmu_irq_cbk(CMU_HOSC_STOP); - } - - /* HOSC start */ - if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) - { - SYSCFG_UNLOCK(); - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK); - SYSCFG_LOCK(); - - if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) - && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))) - cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000); - - ald_cmu_irq_cbk(CMU_HOSC_START); - } - - /* LOSC stop */ - if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK)) - { - SYSCFG_UNLOCK(); - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); - SYSCFG_LOCK(); - ald_cmu_irq_cbk(CMU_LOSC_STOP); - } - - /* LOSC start */ - if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIE_MSK)) - { - SYSCFG_UNLOCK(); - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK); - SYSCFG_LOCK(); - ald_cmu_irq_cbk(CMU_LOSC_START); - } - - /* PLL1 lose */ - if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) - { - SYSCFG_UNLOCK(); - SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); - SYSCFG_LOCK(); - - if (READ_BIT(CMU->PULMCR, CMU_PULMCR_CLKS_MSK) - && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) - || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) - cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); - - ald_cmu_irq_cbk(CMU_PLL1_UNLOCK); - } - - return; + /* HOSC stop */ + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); + SYSCFG_LOCK(); + + if ((READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) + || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) + cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); + ald_cmu_irq_cbk(CMU_HOSC_STOP); + } + + /* HOSC start */ + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK); + SYSCFG_LOCK(); + + if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))) + cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000); + ald_cmu_irq_cbk(CMU_HOSC_START); + } + + /* LOSC stop */ + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); + SYSCFG_LOCK(); + ald_cmu_irq_cbk(CMU_LOSC_STOP); + } + + /* LOSC start */ + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK); + SYSCFG_LOCK(); + ald_cmu_irq_cbk(CMU_LOSC_START); + } + + /* PLL1 lose */ + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); + SYSCFG_LOCK(); + + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_CLKS_MSK) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) + || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) + cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); + ald_cmu_irq_cbk(CMU_PLL1_UNLOCK); + } + + return; } /** * @} @@ -254,30 +246,28 @@ void ald_cmu_irq_handler(void) */ ald_status_t ald_cmu_clock_config_default(void) { - uint32_t cnt = 4000, tmp; + uint32_t cnt = 4000, tmp; - SYSCFG_UNLOCK(); + SYSCFG_UNLOCK(); - /* Select HRC */ - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); + /* Select HRC */ + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) { + SYSCFG_LOCK(); + return ERROR; + } - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) - { - SYSCFG_LOCK(); - return ERROR; - } + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); /* Select 24Mhz */ - CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); /* Select 24Mhz */ + tmp = READ_REG(CMU->CLKENR); + /* Enable HRC/LRC/LOSC */ + SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK | CMU_CLKENR_LOSCEN_MSK); + WRITE_REG(CMU->CLKENR, tmp); - tmp = READ_REG(CMU->CLKENR); - /* Enable HRC/LRC/LOSC */ - SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK | CMU_CLKENR_LOSCEN_MSK); - WRITE_REG(CMU->CLKENR, tmp); - - SYSCFG_LOCK(); - return OK; + SYSCFG_LOCK(); + return OK; } /** @@ -294,161 +284,132 @@ ald_status_t ald_cmu_clock_config_default(void) */ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock) { - uint32_t cnt = 4000; - - assert_param(IS_CMU_CLOCK(clk)); - SYSCFG_UNLOCK(); - - switch (clk) - { - case CMU_CLOCK_HRC: - assert_param(clock == 24000000 || clock == 2000000); - - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); - - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) - { - SYSCFG_LOCK(); - return ERROR; - } - - if (clock == 24000000) - CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); - else - SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); - - SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); - - for (cnt = 4000; cnt; --cnt); - - cnt = 4000; - - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt)); - - cnt = 4000; - - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt)); - - cmu_clock_update(clock); - break; + uint32_t cnt = 4000; - case CMU_CLOCK_LRC: - /* Close SysTick interrupt in lower clock */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + assert_param(IS_CMU_CLOCK(clk)); + SYSCFG_UNLOCK(); - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); + switch (clk) { + case CMU_CLOCK_HRC: + assert_param(clock == 24000000 || clock == 2000000); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) - { - SYSCFG_LOCK(); - return ERROR; - } + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) { + SYSCFG_LOCK(); + return ERROR; + } - SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); + if (clock == 24000000) + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); + else + SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); - cnt = 4000; + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt)); + for (cnt = 4000; cnt; --cnt); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt)); - cnt = 4000; + cmu_clock_update(clock); + break; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); + case CMU_CLOCK_LRC: + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - cmu_clock_update(32768); - break; + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - case CMU_CLOCK_LOSC: - /* Close SysTick interrupt in lower clock */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) { + SYSCFG_LOCK(); + return ERROR; + } - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS); + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) - { - SYSCFG_LOCK(); - return ERROR; - } + cmu_clock_update(32768); + break; - SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); + case CMU_CLOCK_LOSC: + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - cnt = 4000; + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt)); + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) { + SYSCFG_LOCK(); + return ERROR; + } - cnt = 4000; + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt)); - cmu_clock_update(32768); - break; + cmu_clock_update(32768); + break; - case CMU_CLOCK_PLL1: - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS); + case CMU_CLOCK_PLL1: + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) { + SYSCFG_LOCK(); + return ERROR; + } - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) - { - SYSCFG_LOCK(); - return ERROR; - } + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); - SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); + for (cnt = 4000; cnt; --cnt); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); - for (cnt = 4000; cnt; --cnt); + cmu_clock_update(clock); + break; - cnt = 4000; + case CMU_CLOCK_HOSC: + assert_param(clock <= 24000000); - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt)); + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - cnt = 4000; + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) { + SYSCFG_LOCK(); + return ERROR; + } - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1); - cmu_clock_update(clock); - break; + for (cnt = 4000; cnt; --cnt); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); - case CMU_CLOCK_HOSC: - assert_param(clock <= 24000000); + cmu_clock_update(clock); + break; - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); + default: + break; + } - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) - { - SYSCFG_LOCK(); - return ERROR; - } - - SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); - MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1); - - for (cnt = 4000; cnt; --cnt); - - cnt = 4000; - - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); - - cnt = 4000; - - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); - - cmu_clock_update(clock); - break; - - default: - break; - } - - SYSCFG_LOCK(); - return OK; + SYSCFG_LOCK(); + return OK; } @@ -463,40 +424,35 @@ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock) */ void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) { - uint32_t cnt = 4000; - - assert_param(IS_CMU_PLL1_INPUT(input)); - assert_param(IS_CMU_PLL1_OUTPUT(output)); - - SYSCFG_UNLOCK(); - - if (input == CMU_PLL1_INPUT_HRC_6) - { - SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); - } - else if (input == CMU_PLL1_INPUT_PLL2) - { - SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); - CLEAR_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2RFS_MSK); - SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); - } - else - { - SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); - } - - MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1RFS_MSK, input << CMU_PLLCFG_PLL1RFS_POSS); - MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1OS_MSK, output << CMU_PLLCFG_PLL1OS_POS); - SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); - - while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL1LCKN_MSK)) && (--cnt)); - - cnt = 4000; - - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); - - SYSCFG_LOCK(); - return; + uint32_t cnt = 4000; + + assert_param(IS_CMU_PLL1_INPUT(input)); + assert_param(IS_CMU_PLL1_OUTPUT(output)); + + SYSCFG_UNLOCK(); + + if (input == CMU_PLL1_INPUT_HRC_6) { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); + } + else if (input == CMU_PLL1_INPUT_PLL2) { + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); + CLEAR_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2RFS_MSK); + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + } + else { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + } + + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1RFS_MSK, input << CMU_PLLCFG_PLL1RFS_POSS); + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1OS_MSK, output << CMU_PLLCFG_PLL1OS_POS); + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); + + while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL1LCKN_MSK)) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); + + SYSCFG_LOCK(); + return; } /** @@ -505,7 +461,7 @@ void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) */ uint32_t ald_cmu_get_clock(void) { - return __system_clock; + return __system_clock; } /** @@ -518,39 +474,36 @@ uint32_t ald_cmu_get_clock(void) */ int32_t ald_cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq) { - uint32_t cnt = 5000, tmp; + uint32_t cnt = 5000, tmp; - assert_param(IS_CMU_AUTO_CALIB_INPUT(input)); - assert_param(IS_CMU_AUTO_CALIB_OUTPUT(freq)); + assert_param(IS_CMU_AUTO_CALIB_INPUT(input)); + assert_param(IS_CMU_AUTO_CALIB_OUTPUT(freq)); - SYSCFG_UNLOCK(); + SYSCFG_UNLOCK(); - tmp = READ_REG(CMU->HRCACR); + tmp = READ_REG(CMU->HRCACR); - MODIFY_REG(tmp, CMU_HRCACR_AC_MSK, 1 << CMU_HRCACR_AC_POSS); - MODIFY_REG(tmp, CMU_HRCACR_RFSEL_MSK, input << CMU_HRCACR_RFSEL_POS); - MODIFY_REG(tmp, CMU_HRCACR_FREQ_MSK, freq << CMU_HRCACR_FREQ_POS); - SET_BIT(tmp, CMU_HRCACR_EN_MSK); - WRITE_REG(CMU->HRCACR, tmp); + MODIFY_REG(tmp, CMU_HRCACR_AC_MSK, 1 << CMU_HRCACR_AC_POSS); + MODIFY_REG(tmp, CMU_HRCACR_RFSEL_MSK, input << CMU_HRCACR_RFSEL_POS); + MODIFY_REG(tmp, CMU_HRCACR_FREQ_MSK, freq << CMU_HRCACR_FREQ_POS); + SET_BIT(tmp, CMU_HRCACR_EN_MSK); + WRITE_REG(CMU->HRCACR, tmp); - while (cnt--); + while (cnt--); + cnt = 30000; + while ((READ_BIT(CMU->HRCACR, CMU_HRCACR_BUSY_MSK)) && (--cnt)); - cnt = 30000; + if (READ_BITS(CMU->HRCACR, CMU_HRCACR_STA_MSK, CMU_HRCACR_STA_POSS) != 1) { + CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK); + SYSCFG_LOCK(); + return -1; + } - while ((READ_BIT(CMU->HRCACR, CMU_HRCACR_BUSY_MSK)) && (--cnt)); + SET_BIT(CMU->HRCACR, CMU_HRCACR_WRTRG_MSK); + CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK); + SYSCFG_LOCK(); - if (READ_BITS(CMU->HRCACR, CMU_HRCACR_STA_MSK, CMU_HRCACR_STA_POSS) != 1) - { - CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK); - SYSCFG_LOCK(); - return -1; - } - - SET_BIT(CMU->HRCACR, CMU_HRCACR_WRTRG_MSK); - CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK); - SYSCFG_LOCK(); - - return 0; + return 0; } /** * @} @@ -586,46 +539,43 @@ int32_t ald_cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_ou */ void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div) { - assert_param(IS_CMU_BUS(bus)); - assert_param(IS_CMU_DIV(div)); - - SYSCFG_UNLOCK(); - - switch (bus) - { - case CMU_HCLK_1: - MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS); - break; - - case CMU_SYS: - MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); - - if ((__system_clock >> div) <= 1000000) - { - /* Close SysTick interrupt in lower clock */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - } - else - { - ald_tick_init(TICK_INT_PRIORITY); - } - - break; - - case CMU_PCLK_1: - MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS); - break; - - case CMU_PCLK_2: - MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS); - break; - - default: - break; - } - - SYSCFG_LOCK(); - return; + assert_param(IS_CMU_BUS(bus)); + assert_param(IS_CMU_DIV(div)); + + SYSCFG_UNLOCK(); + + switch (bus) { + case CMU_HCLK_1: + MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS); + break; + + case CMU_SYS: + MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); + + if ((__system_clock >> div) <= 1000000) { + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + } + else { + ald_tick_init(TICK_INT_PRIORITY); + } + + break; + + case CMU_PCLK_1: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS); + break; + + case CMU_PCLK_2: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS); + break; + + default: + break; + } + + SYSCFG_LOCK(); + return; } /** @@ -634,10 +584,10 @@ void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div) */ uint32_t ald_cmu_get_hclk1_clock(void) { - uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); - uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, CMU_CFGR_HCLK1DIV_POSS); + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, CMU_CFGR_HCLK1DIV_POSS); - return (__system_clock >> sys_div) >> ahb_div; + return (__system_clock >> sys_div) >> ahb_div; } /** @@ -646,9 +596,9 @@ uint32_t ald_cmu_get_hclk1_clock(void) */ uint32_t ald_cmu_get_sys_clock(void) { - uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); - return __system_clock >> sys_div; + return __system_clock >> sys_div; } /** @@ -657,10 +607,10 @@ uint32_t ald_cmu_get_sys_clock(void) */ uint32_t ald_cmu_get_pclk1_clock(void) { - uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); - uint32_t apb1_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, CMU_CFGR_PCLK1DIV_POSS); + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t apb1_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, CMU_CFGR_PCLK1DIV_POSS); - return (__system_clock >> sys_div) >> apb1_div; + return (__system_clock >> sys_div) >> apb1_div; } /** @@ -669,10 +619,10 @@ uint32_t ald_cmu_get_pclk1_clock(void) */ uint32_t ald_cmu_get_pclk2_clock(void) { - uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); - uint32_t apb2_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, CMU_CFGR_PCLK2DIV_POSS); + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t apb2_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, CMU_CFGR_PCLK2DIV_POSS); - return (__system_clock >> sys_div) >> apb2_div; + return (__system_clock >> sys_div) >> apb2_div; } /** * @} @@ -703,31 +653,29 @@ uint32_t ald_cmu_get_pclk2_clock(void) */ void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) { - assert_param(IS_CMU_HOSC_RANGE(clock)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (status) - { - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); - MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clock << CMU_HOSMCR_FRQS_POSS); - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); - - ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); - } - else - { - CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); - CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); - - if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) - ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_CMU_HOSC_RANGE(clock)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); + MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clock << CMU_HOSMCR_FRQS_POSS); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); + } + else { + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); + + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; } /** @@ -737,28 +685,26 @@ void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) */ void ald_cmu_losc_safe_config(type_func_t status) { - assert_param(IS_FUNC_STATE(status)); - SYSCFG_UNLOCK(); - - if (status) - { - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); - - ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); - } - else - { - CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); - CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); - - if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) - ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_FUNC_STATE(status)); + SYSCFG_UNLOCK(); + + if (status) { + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); + } + else { + CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); + CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); + + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; } /** @@ -768,29 +714,46 @@ void ald_cmu_losc_safe_config(type_func_t status) */ void ald_cmu_pll_safe_config(type_func_t status) { - assert_param(IS_FUNC_STATE(status)); - SYSCFG_UNLOCK(); - - if (status) - { - SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); - MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS); - SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); - SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); - - ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); - } - else - { - CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); - CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); - - if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0) - ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_FUNC_STATE(status)); + SYSCFG_UNLOCK(); + + if (status) { + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); + MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS); + SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); + } + else { + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); + + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Get current clock source. + * @param type: Type of source: HOSC/LOSC/PLL. + * @retval Status: + * - 0: Current clock is HOSC, LOSC or PLL + * - 1: Current clock is HRC, LRC or HRC + */ +uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type) +{ + assert_param(IS_CMU_SAFE_CLOCK_TYPE(type)); + + if (type == CMU_SAFE_CLK_HOSC) + return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK, CMU_HOSMCR_CLKS_POS); + else if (type == CMU_SAFE_CLK_LOSC) + return READ_BITS(CMU->LOSMCR, CMU_LOSMCR_CLKS_MSK, CMU_LOSMCR_CLKS_POS); + else + return READ_BITS(CMU->PULMCR, CMU_PULMCR_CLKS_MSK, CMU_PULMCR_CLKS_POS); } /** @@ -800,12 +763,12 @@ void ald_cmu_pll_safe_config(type_func_t status) */ flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr) { - assert_param(IS_CMU_CLOCK_STATE(sr)); + assert_param(IS_CMU_CLOCK_STATE(sr)); - if (READ_BIT(CMU->CLKSR, sr)) - return SET; + if (READ_BIT(CMU->CLKSR, sr)) + return SET; - return RESET; + return RESET; } /** @@ -816,7 +779,7 @@ flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr) */ __weak void ald_cmu_irq_cbk(cmu_security_t se) { - return; + return; } /** * @} @@ -861,27 +824,25 @@ __weak void ald_cmu_irq_cbk(cmu_security_t se) * @retval None */ void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, - cmu_output_high_div_t div, type_func_t status) + cmu_output_high_div_t div, type_func_t status) { - assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel)); - assert_param(IS_CMU_OUTPUT_HIGH_DIV(div)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (status) - { - MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS); - MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, div << CMU_CLKOCR_HSCODIV_POSS); - SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); - } - else - { - CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel)); + assert_param(IS_CMU_OUTPUT_HIGH_DIV(div)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS); + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, div << CMU_CLKOCR_HSCODIV_POSS); + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); + } + else { + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); + } + + SYSCFG_LOCK(); + return; } /** @@ -897,23 +858,21 @@ void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, */ void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status) { - assert_param(IS_CMU_OUTPUT_LOW_SEL(sel)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (status) - { - MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS); - SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); - } - else - { - CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_CMU_OUTPUT_LOW_SEL(sel)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS); + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); + } + else { + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); + } + + SYSCFG_LOCK(); + return; } /** * @} @@ -947,24 +906,22 @@ void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t statu */ void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status) { - assert_param(IS_CMU_BUZZ_DIV(div)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (status) - { - MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS); - MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS); - SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); - } - else - { - CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_CMU_BUZZ_DIV(div)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS); + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS); + SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); + } + else { + CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); + } + + SYSCFG_LOCK(); + return; } /** @@ -986,13 +943,13 @@ void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status) */ void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock) { - assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); + assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); - SYSCFG_UNLOCK(); - MODIFY_REG(CMU->PERICR, CMU_PERICR_LPTIM0_MSK, clock << CMU_PERICR_LPTIM0_POSS); - SYSCFG_LOCK(); + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LPTIM0_MSK, clock << CMU_PERICR_LPTIM0_POSS); + SYSCFG_LOCK(); - return; + return; } /** @@ -1014,13 +971,13 @@ void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock) */ void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock) { - assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); + assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); - SYSCFG_UNLOCK(); - MODIFY_REG(CMU->PERICR, CMU_PERICR_LPUART0_MSK, clock << CMU_PERICR_LPUART0_POSS); - SYSCFG_LOCK(); + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LPUART0_MSK, clock << CMU_PERICR_LPUART0_POSS); + SYSCFG_LOCK(); - return; + return; } /** @@ -1036,13 +993,13 @@ void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock) */ void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock) { - assert_param(IS_CMU_LCD_CLOCK_SEL(clock)); + assert_param(IS_CMU_LCD_CLOCK_SEL(clock)); - SYSCFG_UNLOCK(); - MODIFY_REG(CMU->PERICR, CMU_PERICR_LCD_MSK, clock << CMU_PERICR_LCD_POSS); - SYSCFG_LOCK(); + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LCD_MSK, clock << CMU_PERICR_LCD_POSS); + SYSCFG_LOCK(); - return; + return; } /** @@ -1053,78 +1010,71 @@ void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock) */ void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status) { - uint32_t idx, pos; - - assert_param(IS_CMU_PERH(perh)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (perh == CMU_PERH_ALL) - { - if (status) - { - WRITE_REG(CMU->AHB1ENR, ~0); - WRITE_REG(CMU->APB1ENR, ~0); - WRITE_REG(CMU->APB2ENR, ~0); - } - else - { - WRITE_REG(CMU->AHB1ENR, 0); - WRITE_REG(CMU->APB1ENR, 0); - WRITE_REG(CMU->APB2ENR, 0); - } - - SYSCFG_LOCK(); - return; - } - - idx = (perh >> 27) & 0x3; - pos = perh & ~(0x3 << 27); - - if (status) - { - switch (idx) - { - case 0: - SET_BIT(CMU->AHB1ENR, pos); - break; - - case 1: - SET_BIT(CMU->APB1ENR, pos); - break; - - case 2: - SET_BIT(CMU->APB2ENR, pos); - break; - - default: - break; - } - } - else - { - switch (idx) - { - case 0: - CLEAR_BIT(CMU->AHB1ENR, pos); - break; - - case 1: - CLEAR_BIT(CMU->APB1ENR, pos); - break; - - case 2: - CLEAR_BIT(CMU->APB2ENR, pos); - break; - - default: - break; - } - } - - SYSCFG_LOCK(); - return; + uint32_t idx, pos; + + assert_param(IS_CMU_PERH(perh)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (perh == CMU_PERH_ALL) { + if (status) { + WRITE_REG(CMU->AHB1ENR, ~0); + WRITE_REG(CMU->APB1ENR, ~0); + WRITE_REG(CMU->APB2ENR, ~0); + } + else { + WRITE_REG(CMU->AHB1ENR, 0); + WRITE_REG(CMU->APB1ENR, 0); + WRITE_REG(CMU->APB2ENR, 0); + } + + SYSCFG_LOCK(); + return; + } + + idx = (perh >> 27) & 0x3; + pos = perh & ~(0x3 << 27); + + if (status) { + switch (idx) { + case 0: + SET_BIT(CMU->AHB1ENR, pos); + break; + + case 1: + SET_BIT(CMU->APB1ENR, pos); + break; + + case 2: + SET_BIT(CMU->APB2ENR, pos); + break; + + default: + break; + } + } + else { + switch (idx) { + case 0: + CLEAR_BIT(CMU->AHB1ENR, pos); + break; + + case 1: + CLEAR_BIT(CMU->APB1ENR, pos); + break; + + case 2: + CLEAR_BIT(CMU->APB2ENR, pos); + break; + + default: + break; + } + } + + SYSCFG_LOCK(); + return; } /** diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crc.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crc.c index d49b39fe564f2522393158e2de1dbe9be88a49c3..bf6fde037c11c63e8fe3d8a6f92bb69239211e3e 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crc.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crc.c @@ -31,8 +31,8 @@ */ void ald_crc_reset(crc_handle_t *hperh); #ifdef ALD_DMA - static void crc_dma_calculate_cplt(void *arg); - static void crc_dma_error(void *arg); +static void crc_dma_calculate_cplt(void *arg); +static void crc_dma_error(void *arg); #endif /** * @} @@ -57,38 +57,38 @@ void ald_crc_reset(crc_handle_t *hperh); */ ald_status_t ald_crc_init(crc_handle_t *hperh) { - uint32_t tmp = 0; + uint32_t tmp = 0; - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - assert_param(IS_CRC(hperh->perh)); - assert_param(IS_CRC_MODE(hperh->init.mode)); - assert_param(IS_FUNC_STATE(hperh->init.chs_rev)); - assert_param(IS_FUNC_STATE(hperh->init.data_inv)); - assert_param(IS_FUNC_STATE(hperh->init.data_rev)); - assert_param(IS_FUNC_STATE(hperh->init.chs_inv)); + assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC_MODE(hperh->init.mode)); + assert_param(IS_FUNC_STATE(hperh->init.chs_rev)); + assert_param(IS_FUNC_STATE(hperh->init.data_inv)); + assert_param(IS_FUNC_STATE(hperh->init.data_rev)); + assert_param(IS_FUNC_STATE(hperh->init.chs_inv)); - ald_crc_reset(hperh); - __LOCK(hperh); + ald_crc_reset(hperh); + __LOCK(hperh); - CRC_ENABLE(hperh); + CRC_ENABLE(hperh); - tmp = hperh->perh->CR; + tmp = hperh->perh->CR; - tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) | - (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) | - (CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) | - (0 << CRC_CR_BYTORD_POS)); + tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) | + (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) | + (CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) | + (0 << CRC_CR_BYTORD_POS)); - hperh->perh->CR = tmp; - hperh->perh->SEED = hperh->init.seed; - CRC_RESET(hperh); + hperh->perh->CR = tmp; + hperh->perh->SEED = hperh->init.seed; + CRC_RESET(hperh); - hperh->state = CRC_STATE_READY; + hperh->state = CRC_STATE_READY; - __UNLOCK(hperh); - return OK; + __UNLOCK(hperh); + return OK; } /** @@ -110,26 +110,26 @@ ald_status_t ald_crc_init(crc_handle_t *hperh) */ uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) { - uint32_t i; - uint32_t ret; + uint32_t i; + uint32_t ret; - assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC(hperh->perh)); - if (buf == NULL || size == 0) - return 0; + if (buf == NULL || size == 0) + return 0; - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; - for (i = 0; i < size; i++) - *((volatile uint8_t *) & (hperh->perh->DATA)) = buf[i]; + for (i = 0; i < size; i++) + *((volatile uint8_t *)&(hperh->perh->DATA)) = buf[i]; - ret = CRC->CHECKSUM; - hperh->state = CRC_STATE_READY; - __UNLOCK(hperh); + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); - return ret; + return ret; } /** @@ -142,26 +142,26 @@ uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) */ uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size) { - uint32_t i; - uint32_t ret; + uint32_t i; + uint32_t ret; - assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC(hperh->perh)); - if (buf == NULL || size == 0) - return 0; + if (buf == NULL || size == 0) + return 0; - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; - for (i = 0; i < size; i++) - *((volatile uint16_t *) & (hperh->perh->DATA)) = buf[i]; + for (i = 0; i < size; i++) + *((volatile uint16_t *)&(hperh->perh->DATA)) = buf[i]; - ret = CRC->CHECKSUM; - hperh->state = CRC_STATE_READY; - __UNLOCK(hperh); + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); - return ret; + return ret; } /** @@ -174,26 +174,26 @@ uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t */ uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size) { - uint32_t i; - uint32_t ret; + uint32_t i; + uint32_t ret; - assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC(hperh->perh)); - if (buf == NULL || size == 0) - return 0; + if (buf == NULL || size == 0) + return 0; - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; - for (i = 0; i < size; i++) - CRC->DATA = buf[i]; + for (i = 0; i < size; i++) + CRC->DATA = buf[i]; - ret = CRC->CHECKSUM; - hperh->state = CRC_STATE_READY; - __UNLOCK(hperh); + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); - return ret; + return ret; } /** @@ -218,44 +218,44 @@ uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t siz */ ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel) { - if (hperh->state != CRC_STATE_READY) - return BUSY; + if (hperh->state != CRC_STATE_READY) + return BUSY; - if (buf == NULL || size == 0) - return ERROR; + if (buf == NULL || size == 0) + return ERROR; - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; + hperh->state = CRC_STATE_BUSY; - hperh->cal_buf = buf; - hperh->cal_res = res; + hperh->cal_buf = buf; + hperh->cal_res = res; - if (hperh->hdma.perh == NULL) - hperh->hdma.perh = DMA0; + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; - hperh->hdma.cplt_arg = (void *)hperh; - hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; - hperh->hdma.err_arg = (void *)hperh; - hperh->hdma.err_cbk = &crc_dma_error; + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; - ald_dma_config_struct(&(hperh->hdma.config)); - hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdma.config.src = (void *)buf; - hperh->hdma.config.dst = (void *)&hperh->perh->DATA; - hperh->hdma.config.size = size; - hperh->hdma.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.msel = DMA_MSEL_CRC; - hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; - hperh->hdma.config.channel = channel; - ald_dma_config_basic(&(hperh->hdma)); + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); - __UNLOCK(hperh); - CRC_DMA_ENABLE(hperh); + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); - return OK; + return OK; } /** @@ -270,44 +270,44 @@ ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_ */ ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel) { - if (hperh->state != CRC_STATE_READY) - return BUSY; + if (hperh->state != CRC_STATE_READY) + return BUSY; - if (buf == NULL || size == 0) - return ERROR; + if (buf == NULL || size == 0) + return ERROR; - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; + hperh->state = CRC_STATE_BUSY; - hperh->cal_buf = (uint8_t *)buf; - hperh->cal_res = res; + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; - if (hperh->hdma.perh == NULL) - hperh->hdma.perh = DMA0; + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; - hperh->hdma.cplt_arg = (void *)hperh; - hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; - hperh->hdma.err_arg = (void *)hperh; - hperh->hdma.err_cbk = &crc_dma_error; + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; - ald_dma_config_struct(&(hperh->hdma.config)); - hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma.config.src = (void *)buf; - hperh->hdma.config.dst = (void *)&hperh->perh->DATA; - hperh->hdma.config.size = size; - hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.msel = DMA_MSEL_CRC; - hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; - hperh->hdma.config.channel = channel; - ald_dma_config_basic(&(hperh->hdma)); + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); - __UNLOCK(hperh); - CRC_DMA_ENABLE(hperh); + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); - return OK; + return OK; } /** @@ -322,44 +322,44 @@ ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *bu */ ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel) { - if (hperh->state != CRC_STATE_READY) - return BUSY; + if (hperh->state != CRC_STATE_READY) + return BUSY; - if (buf == NULL || size == 0) - return ERROR; + if (buf == NULL || size == 0) + return ERROR; - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; + hperh->state = CRC_STATE_BUSY; - hperh->cal_buf = (uint8_t *)buf; - hperh->cal_res = res; + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; - if (hperh->hdma.perh == NULL) - hperh->hdma.perh = DMA0; + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; - hperh->hdma.cplt_arg = (void *)hperh; - hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; - hperh->hdma.err_arg = (void *)hperh; - hperh->hdma.err_cbk = &crc_dma_error; + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; - ald_dma_config_struct(&(hperh->hdma.config)); - hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma.config.src = (void *)buf; - hperh->hdma.config.dst = (void *)&hperh->perh->DATA; - hperh->hdma.config.size = size; - hperh->hdma.config.src_inc = DMA_DATA_INC_WORD; - hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.msel = DMA_MSEL_CRC; - hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; - hperh->hdma.config.channel = channel; - ald_dma_config_basic(&(hperh->hdma)); + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); - __UNLOCK(hperh); - CRC_DMA_ENABLE(hperh); + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); - return OK; + return OK; } @@ -371,11 +371,11 @@ ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, u */ ald_status_t ald_crc_dma_pause(crc_handle_t *hperh) { - __LOCK(hperh); - CRC_DMA_DISABLE(hperh); - __UNLOCK(hperh); + __LOCK(hperh); + CRC_DMA_DISABLE(hperh); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -386,11 +386,11 @@ ald_status_t ald_crc_dma_pause(crc_handle_t *hperh) */ ald_status_t ald_crc_dma_resume(crc_handle_t *hperh) { - __LOCK(hperh); - CRC_DMA_ENABLE(hperh); - __UNLOCK(hperh); + __LOCK(hperh); + CRC_DMA_ENABLE(hperh); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -401,12 +401,12 @@ ald_status_t ald_crc_dma_resume(crc_handle_t *hperh) */ ald_status_t ald_crc_dma_stop(crc_handle_t *hperh) { - __LOCK(hperh); - CRC_DMA_DISABLE(hperh); - __UNLOCK(hperh); + __LOCK(hperh); + CRC_DMA_DISABLE(hperh); + __UNLOCK(hperh); - hperh->state = CRC_STATE_READY; - return OK; + hperh->state = CRC_STATE_READY; + return OK; } /** @@ -427,9 +427,9 @@ ald_status_t ald_crc_dma_stop(crc_handle_t *hperh) */ crc_state_t ald_crc_get_state(crc_handle_t *hperh) { - assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC(hperh->perh)); - return hperh->state; + return hperh->state; } /** * @} @@ -452,13 +452,13 @@ crc_state_t ald_crc_get_state(crc_handle_t *hperh) */ void ald_crc_reset(crc_handle_t *hperh) { - hperh->perh->DATA = 0x0; - hperh->perh->CR = 0x2; - hperh->perh->SEED = 0xFFFFFFFF; + hperh->perh->DATA = 0x0; + hperh->perh->CR = 0x2; + hperh->perh->SEED = 0xFFFFFFFF; - hperh->state = CRC_STATE_READY; - __UNLOCK(hperh); - return; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + return; } #ifdef ALD_DMA @@ -470,15 +470,15 @@ void ald_crc_reset(crc_handle_t *hperh) */ static void crc_dma_calculate_cplt(void *arg) { - crc_handle_t *hperh = (crc_handle_t *)arg; + crc_handle_t *hperh = (crc_handle_t *)arg; - *(hperh->cal_res) = CRC->CHECKSUM; - CRC_DMA_DISABLE(hperh); + *(hperh->cal_res) = CRC->CHECKSUM; + CRC_DMA_DISABLE(hperh); - hperh->state = CRC_STATE_READY; + hperh->state = CRC_STATE_READY; - if (hperh->cal_cplt_cbk) - hperh->cal_cplt_cbk(hperh); + if (hperh->cal_cplt_cbk) + hperh->cal_cplt_cbk(hperh); } /** @@ -489,15 +489,15 @@ static void crc_dma_calculate_cplt(void *arg) */ static void crc_dma_error(void *arg) { - crc_handle_t *hperh = (crc_handle_t *)arg; + crc_handle_t *hperh = (crc_handle_t *)arg; - CRC_CLEAR_ERROR_FLAG(hperh); - CRC_DMA_DISABLE(hperh); + CRC_CLEAR_ERROR_FLAG(hperh); + CRC_DMA_DISABLE(hperh); - hperh->state = CRC_STATE_READY; + hperh->state = CRC_STATE_READY; - if (hperh->err_cplt_cbk) - hperh->err_cplt_cbk(hperh); + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); } #endif /** diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crypt.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crypt.c index 30d7f1e3ef8e6d1aed5f9e25f2ed997384684955..ff8f92d9d53fbfe537bc677a23b259573019294a 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crypt.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crypt.c @@ -34,8 +34,8 @@ */ void crypt_reset(crypt_handle_t *hperh); #ifdef ALD_DMA - static void crypt_dma_crypt_cplt(void *arg); - static void crypt_dma_error(void *arg); +static void crypt_dma_crypt_cplt(void *arg); +static void crypt_dma_error(void *arg); #endif /** * @} @@ -60,29 +60,29 @@ void crypt_reset(crypt_handle_t *hperh); */ ald_status_t ald_crypt_init(crypt_handle_t *hperh) { - uint32_t tmp = 0; + uint32_t tmp = 0; - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - assert_param(IS_CRYPT(hperh->perh)); - assert_param(IS_CRYPT_MODE(hperh->init.mode)); + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_MODE(hperh->init.mode)); - __LOCK(hperh); - crypt_reset(hperh); + __LOCK(hperh); + crypt_reset(hperh); - if (hperh->state == CRYPT_STATE_RESET) - __UNLOCK(hperh); + if (hperh->state == CRYPT_STATE_RESET) + __UNLOCK(hperh); - tmp = hperh->perh->CON; - hperh->step = 4; - tmp |= ((1 << CRYPT_CON_FIFOODR_POS) | (hperh->init.mode << CRYPT_CON_MODE_POSS) | \ - (hperh->init.type << CRYPT_CON_TYPE_POSS) | (1 << CRYPT_CON_FIFOEN_POS)); - WRITE_REG(hperh->perh->CON, tmp); - hperh->state = CRYPT_STATE_READY; - __UNLOCK(hperh); + tmp = hperh->perh->CON; + hperh->step = 4; + tmp |= ((1 << CRYPT_CON_FIFOODR_POS) | (hperh->init.mode << CRYPT_CON_MODE_POSS) | \ + (hperh->init.type << CRYPT_CON_TYPE_POSS) | (1 << CRYPT_CON_FIFOEN_POS)); + WRITE_REG(hperh->perh->CON, tmp); + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -94,26 +94,25 @@ ald_status_t ald_crypt_init(crypt_handle_t *hperh) */ ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key) { - uint32_t *temp = key; - uint32_t i; + uint32_t *temp = key; + uint32_t i; - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; + if ((hperh == NULL) || (key == NULL)) + return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; - if ((hperh == NULL) || (key == NULL)) - return ERROR; + assert_param(IS_CRYPT(hperh->perh)); - assert_param(IS_CRYPT(hperh->perh)); + hperh->perh->KEY[3] = *temp++; + hperh->perh->KEY[2] = *temp++; + hperh->perh->KEY[1] = *temp++; + hperh->perh->KEY[0] = *temp; - hperh->perh->KEY[3] = *temp++; - hperh->perh->KEY[2] = *temp++; - hperh->perh->KEY[1] = *temp++; - hperh->perh->KEY[0] = *temp; + for (i = 0; i < 4; i++) + hperh->key[i] = *key++; - for (i = 0; i < 4; i++) - hperh->key[i] = *key++; - - return OK; + return OK; } /** @@ -125,22 +124,21 @@ ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key) */ ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t *key) { - uint32_t *temp = key; - - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; + uint32_t *temp = key; - if ((hperh == NULL) || (key == NULL)) - return ERROR; + if ((hperh == NULL) || (key == NULL)) + return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; - assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT(hperh->perh)); - *temp++ = hperh->perh->KEY[3]; - *temp++ = hperh->perh->KEY[2]; - *temp++ = hperh->perh->KEY[1]; - *temp = hperh->perh->KEY[0]; + *temp++ = hperh->perh->KEY[3]; + *temp++ = hperh->perh->KEY[2]; + *temp++ = hperh->perh->KEY[1]; + *temp = hperh->perh->KEY[0]; - return OK; + return OK; } /** @@ -152,27 +150,26 @@ ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t *key) */ ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv) { - uint32_t *temp = iv; - uint32_t i; + uint32_t *temp = iv; + uint32_t i; - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; + if ((hperh == NULL) || (iv == NULL)) + return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; - if ((hperh == NULL) || (iv == NULL)) - return ERROR; + assert_param(IS_CRYPT(hperh->perh)); - assert_param(IS_CRYPT(hperh->perh)); + hperh->perh->IV[3] = *temp++; + hperh->perh->IV[2] = *temp++; + hperh->perh->IV[1] = *temp++; + hperh->perh->IV[0] = *temp; - hperh->perh->IV[3] = *temp++; - hperh->perh->IV[2] = *temp++; - hperh->perh->IV[1] = *temp++; - hperh->perh->IV[0] = *temp; + for (i = 0; i < 4; i++) + hperh->iv[i] = *iv++; - for (i = 0; i < 4; i++) - hperh->iv[i] = *iv++; - - CRYPT_IVEN_ENABLE(hperh); - return OK; + CRYPT_IVEN_ENABLE(hperh); + return OK; } /** @@ -184,22 +181,21 @@ ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv) */ ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv) { - uint32_t *temp = iv; - - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; + uint32_t *temp = iv; - if ((hperh == NULL) || (iv == NULL)) - return ERROR; + if ((hperh == NULL) || (iv == NULL)) + return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; - assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT(hperh->perh)); - *temp++ = hperh->perh->IV[3]; - *temp++ = hperh->perh->IV[2]; - *temp++ = hperh->perh->IV[1]; - *temp = hperh->perh->IV[0]; + *temp++ = hperh->perh->IV[3]; + *temp++ = hperh->perh->IV[2]; + *temp++ = hperh->perh->IV[1]; + *temp = hperh->perh->IV[0]; - return OK; + return OK; } /** @@ -223,45 +219,42 @@ ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv) */ ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) { - uint32_t count = 0; - uint32_t i; - uint32_t *plain_buf = (uint32_t *)plain_text; - uint32_t *cipher_buf = (uint32_t *)cipher_text; + uint32_t count = 0; + uint32_t i; + uint32_t *plain_buf = (uint32_t *)plain_text; + uint32_t *cipher_buf = (uint32_t *)cipher_text; - if (hperh->state != CRYPT_STATE_READY) - return ERROR; + if (hperh->state != CRYPT_STATE_READY) + return ERROR; - if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) - return ERROR; + if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) + return ERROR; - assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT(hperh->perh)); - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); - count = size / (4 * hperh->step); + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + count = size / (4 * hperh->step); - while (count--) - { - for (i = 0; i < hperh->step; i++) - { - CRYPT_WRITE_FIFO(hperh, *plain_buf); - plain_buf++; - } + while (count--) { + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *plain_buf); + plain_buf++; + } - while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); + while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); - for (i = 0; i < hperh->step; i++) - { - *cipher_buf = CRYPT_READ_FIFO(hperh); - cipher_buf++; - } - } + for (i = 0; i < hperh->step; i++) { + *cipher_buf = CRYPT_READ_FIFO(hperh); + cipher_buf++; + } + } - hperh->state = CRYPT_STATE_READY; - __UNLOCK(hperh); + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -276,75 +269,71 @@ ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8 */ ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) { - uint32_t count = 0; - uint32_t i; - uint32_t *plain_buf = (uint32_t *)plain_text; - uint32_t *cipher_buf = (uint32_t *)cipher_text; - - if (hperh->init.mode == CRYPT_MODE_CTR) - { - return ald_crypt_encrypt(hperh, cipher_text, plain_text, size); - } - - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) - return ERROR; - - assert_param(IS_CRYPT(hperh->perh)); - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - CRYPT_SETDIR(hperh, CRYPT_DECRYPT); - count = size / (4 * hperh->step); - - while (count--) - { - for (i = 0; i < hperh->step; i++) - { - CRYPT_WRITE_FIFO(hperh, *cipher_buf); - cipher_buf++; - } - - while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); - - for (i = 0; i < hperh->step; i++) - { - *plain_buf = CRYPT_READ_FIFO(hperh); - plain_buf++; - } - } - - hperh->state = CRYPT_STATE_READY; - __UNLOCK(hperh); - - return OK; + uint32_t count = 0; + uint32_t i; + uint32_t *plain_buf = (uint32_t*)plain_text; + uint32_t *cipher_buf = (uint32_t*)cipher_text; + + if (hperh->init.mode == CRYPT_MODE_CTR) { + return ald_crypt_encrypt(hperh, cipher_text, plain_text, size); + } + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + count = size / (4 * hperh->step); + + while (count--) { + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *cipher_buf); + cipher_buf++; + } + + while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); + + for (i = 0; i < hperh->step; i++) { + *plain_buf = CRYPT_READ_FIFO(hperh); + plain_buf++; + } + } + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); + + return OK; } void gcm_mul(uint32_t *res, uint32_t *data, uint32_t *iv) { - CRYPT->CON = 0; - CRYPT->DATA[0] = data[3]; - CRYPT->DATA[1] = data[2]; - CRYPT->DATA[2] = data[1]; - CRYPT->DATA[3] = data[0]; - CRYPT->IV[0] = iv[3]; - CRYPT->IV[1] = iv[2]; - CRYPT->IV[2] = iv[1]; - CRYPT->IV[3] = iv[0]; - CRYPT->CON |= ((1 << CRYPT_CON_RESCLR_POS) | (3 << CRYPT_CON_MODE_POSS) | \ - (1 << CRYPT_CON_GO_POS)); - - while (READ_BIT(CRYPT->IF, CRYPT_IF_MULTHIF_MSK) == 0); - - res[3] = CRYPT->RES[0]; - res[2] = CRYPT->RES[1]; - res[1] = CRYPT->RES[2]; - res[0] = CRYPT->RES[3]; - - WRITE_REG(CRYPT->IFC, CRYPT_IFC_MULTHIFC_MSK); - return; + CRYPT->CON = 0; + CRYPT->DATA[0] = data[3]; + CRYPT->DATA[1] = data[2]; + CRYPT->DATA[2] = data[1]; + CRYPT->DATA[3] = data[0]; + CRYPT->IV[0] = iv[3]; + CRYPT->IV[1] = iv[2]; + CRYPT->IV[2] = iv[1]; + CRYPT->IV[3] = iv[0]; + CRYPT->CON |= ((1 << CRYPT_CON_RESCLR_POS) | (3 << CRYPT_CON_MODE_POSS) | \ + (1 << CRYPT_CON_GO_POS)); + + while (READ_BIT(CRYPT->IF, CRYPT_IF_MULTHIF_MSK) == 0); + + res[3] = CRYPT->RES[0]; + res[2] = CRYPT->RES[1]; + res[1] = CRYPT->RES[2]; + res[0] = CRYPT->RES[3]; + + WRITE_REG(CRYPT->IFC, CRYPT_IFC_MULTHIFC_MSK); + return; } /** @@ -360,114 +349,90 @@ void gcm_mul(uint32_t *res, uint32_t *data, uint32_t *iv) */ ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag) { - uint8_t GCM_HASH_in[0x60] = {0}; - uint8_t ecb[16] = {0}; - uint32_t x_temp[4]; - uint64_t u, v; - uint32_t len = 0; - uint32_t j, i, k; - uint32_t *tag_temp, *cipher_text_temp; - - /* calculate u and v */ - u = 128 * ((size % 16) ? (size / 16 + 1) : size / 16) - size * 8; - v = 128 * ((alen % 16) ? (alen / 16 + 1) : alen / 16) - alen * 8; - - /* get the input of GHASH algorithm,the input:A||0^v||C||0^u||[len(A)]_64||[len(C)]_64 */ - for (i = 0; i < alen; i++) - { - GCM_HASH_in [i] = * (aadata + i); - } - - len += alen; - - for (i = 0; i < v / 8; i++) - { - GCM_HASH_in[i + len] = 0; - } - - len += v / 8; - - for (i = 0; i < size; i++) - { - GCM_HASH_in[i + len] = * (cipher_text + i); - } - - len += size; - - for (i = 0; i < u / 8; i++) - { - GCM_HASH_in[i + len] = 0; - } - - len += u / 8; - - for (i = 0; i < 4; i++) - { - GCM_HASH_in[i + len] = 0; - } - - len += 4; - - for (i = 0; i < 4; i++) - { - GCM_HASH_in[i + len] = ((alen * 8) >> (8 * i)) & 0xFF; - } - - len += 4; - - for (i = 0; i < 4; i++) - { - GCM_HASH_in[i + len] = 0; - } - - len += 4; - - for (i = 0; i < 4; i++) - { - GCM_HASH_in[i + len] = ((size * 8) >> (8 * i)) & 0xFF; - } - - len += 4; - - CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS); - CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS); - - ald_crypt_encrypt(hperh, ecb, ecb, 16); - - k = len / 16; - - for (i = 0; i < 16; i++) - { - tag[i] = 0; - } - - cipher_text_temp = (uint32_t *)GCM_HASH_in; - tag_temp = (uint32_t *)tag; - - for (i = 0; i < k; i++) - { - for (j = 0; j < 4; j++) - { - x_temp[j] = (*cipher_text_temp) ^ tag_temp[j]; - ++cipher_text_temp; - } - - gcm_mul((uint32_t *)tag_temp, x_temp, (uint32_t *)ecb); - } - - /* calculate the authentication tag T, - * T = CIPH_K(J0)^S,J0=IV||0^31||1,CIPH_K is the algorithm of AES in ECB mode - */ - tag_temp = (uint32_t *)tag; - ald_crypt_init(hperh); - CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS); - CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS); - ald_crypt_write_key(hperh, hperh->key); - hperh->iv[3] = 1; - ald_crypt_write_ivr(hperh, hperh->iv); - ald_crypt_encrypt(hperh, tag, tag, 16); - - return OK; + uint8_t GCM_HASH_in[0x60] = {0}; + uint8_t ecb[16] = {0}; + uint32_t x_temp[4]; + uint64_t u, v; + uint32_t len = 0; + uint32_t j, i, k; + uint32_t *tag_temp, *cipher_text_temp; + + /* calculate u and v */ + u = 128 * ((size % 16) ? (size / 16 + 1) : size / 16) - size * 8; + v = 128 * ((alen % 16) ? (alen / 16 + 1): alen / 16) - alen * 8; + + /* get the input of GHASH algorithm,the input:A||0^v||C||0^u||[len(A)]_64||[len(C)]_64 */ + for (i = 0; i < alen; i++) { + GCM_HASH_in [i] = * (aadata + i); + } + len += alen; + for (i = 0; i < v / 8; i++) { + GCM_HASH_in[i + len] = 0; + } + len += v / 8; + for (i = 0; i < size; i++) { + GCM_HASH_in[i + len] = * (cipher_text + i); + } + len += size; + for (i = 0; i < u / 8; i++) { + GCM_HASH_in[i + len] = 0; + } + len += u / 8; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = 0; + } + len += 4; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = ((alen * 8) >> (8 * i)) & 0xFF; + } + len += 4; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = 0; + } + len += 4; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = ((size * 8) >> (8 * i)) & 0xFF; + } + len += 4; + + CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS); + CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS); + + ald_crypt_encrypt(hperh, ecb, ecb, 16); + + k = len / 16; + for (i = 0; i < 16; i++) { + tag[i] = 0; + } + + cipher_text_temp = (uint32_t *)GCM_HASH_in; + tag_temp = (uint32_t *)tag; + for (i = 0; i < k; i++) { + for (j = 0; j < 4; j++) { + x_temp[j] = (*cipher_text_temp) ^ tag_temp[j]; + ++cipher_text_temp; + } + + gcm_mul((uint32_t *)tag_temp, x_temp, (uint32_t *)ecb); + } + + /* calculate the authentication tag T, + * T = CIPH_K(J0)^S,J0=IV||0^31||1,CIPH_K is the algorithm of AES in ECB mode + */ + tag_temp = (uint32_t *)tag; + ald_crypt_init(hperh); + CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS); + CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS); + ald_crypt_write_key(hperh, hperh->key); + hperh->iv[3] = 1; + ald_crypt_write_ivr(hperh, hperh->iv); + ald_crypt_encrypt(hperh, tag, tag, 16); + + return OK; } /** @@ -480,36 +445,35 @@ ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, u * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) +ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t *cipher_text, uint32_t size) { - uint32_t i; - uint32_t *plain_buf = (uint32_t *)plain_text; - - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) - return ERROR; - - assert_param(IS_CRYPT(hperh->perh)); - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); - hperh->count = hperh->step; - hperh->plain_text = plain_text; - hperh->cipher_text = cipher_text; - hperh->size = size; - ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); - - for (i = 0; i < hperh->step; i++) - { - CRYPT_WRITE_FIFO(hperh, *plain_buf); - ++plain_buf; - } - - __UNLOCK(hperh); - return OK; + uint32_t i; + uint32_t *plain_buf = (uint32_t *)plain_text; + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + hperh->count = hperh->step; + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); + + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *plain_buf); + ++plain_buf; + } + + __UNLOCK(hperh); + return OK; } /** @@ -524,39 +488,37 @@ ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, */ ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) { - uint32_t i; - uint32_t *cipher_buf = (uint32_t *)cipher_text; - - if (hperh->init.mode == CRYPT_MODE_CTR) - { - return ald_crypt_decrypt_by_it(hperh, cipher_text, plain_text, size); - } - - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) - return ERROR; - - assert_param(IS_CRYPT(hperh->perh)); - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - CRYPT_SETDIR(hperh, CRYPT_DECRYPT); - hperh->count = hperh->step; - hperh->plain_text = plain_text; - hperh->cipher_text = cipher_text; - hperh->size = size; - ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); - - for (i = 0; i < hperh->step; i++) - { - CRYPT_WRITE_FIFO(hperh, *cipher_buf); - cipher_buf++; - } - - __UNLOCK(hperh); - return OK; + uint32_t i; + uint32_t *cipher_buf = (uint32_t*)cipher_text; + + if (hperh->init.mode == CRYPT_MODE_CTR) { + return ald_crypt_decrypt_by_it(hperh, cipher_text, plain_text, size); + } + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + hperh->count = hperh->step; + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); + + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *cipher_buf); + cipher_buf++; + } + + __UNLOCK(hperh); + return OK; } #ifdef ALD_DMA @@ -572,71 +534,70 @@ ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, - uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) +ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t * plain_text, + uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) { - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if (plain_text == NULL || cipher_text == NULL || size == 0) - return ERROR; - - assert_param(IS_CRYPT(hperh->perh)); - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - - hperh->plain_text = plain_text; - hperh->cipher_text = cipher_text; - hperh->size = size; - hperh->count = size; - - if (hperh->hdma_m2p.perh == NULL) - hperh->hdma_m2p.perh = DMA0; - - if (hperh->hdma_p2m.perh == NULL) - hperh->hdma_p2m.perh = DMA0; - - hperh->hdma_m2p.cplt_arg = NULL; - hperh->hdma_m2p.cplt_cbk = NULL; - hperh->hdma_m2p.err_arg = NULL; - hperh->hdma_m2p.err_cbk = NULL; - - hperh->hdma_p2m.cplt_arg = (void *)hperh; - hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; - hperh->hdma_p2m.err_arg = (void *)hperh; - hperh->hdma_p2m.err_cbk = &crypt_dma_error; - - CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); - - ald_dma_config_struct(&hperh->hdma_m2p.config); - hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma_m2p.config.src = (void *)hperh->plain_text; - hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; - hperh->hdma_m2p.config.size = size / 4; - hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; - hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; - hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; - hperh->hdma_m2p.config.channel = channel_m2p; - ald_dma_config_basic(&(hperh->hdma_m2p)); - - ald_dma_config_struct(&hperh->hdma_p2m.config); - hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; - hperh->hdma_p2m.config.dst = (void *)hperh->cipher_text; - hperh->hdma_p2m.config.size = size / 4; - hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; - hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; - hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; - hperh->hdma_p2m.config.channel = channel_p2m; - ald_dma_config_basic(&(hperh->hdma_p2m)); - - CRYPT_DMA_ENABLE(hperh); - __UNLOCK(hperh); - - return OK; + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if (plain_text == NULL || cipher_text == NULL || size == 0) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + hperh->count = size; + + if (hperh->hdma_m2p.perh == NULL) + hperh->hdma_m2p.perh = DMA0; + if (hperh->hdma_p2m.perh == NULL) + hperh->hdma_p2m.perh = DMA0; + + hperh->hdma_m2p.cplt_arg = NULL; + hperh->hdma_m2p.cplt_cbk = NULL; + hperh->hdma_m2p.err_arg = NULL; + hperh->hdma_m2p.err_cbk = NULL; + + hperh->hdma_p2m.cplt_arg = (void *)hperh; + hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; + hperh->hdma_p2m.err_arg = (void *)hperh; + hperh->hdma_p2m.err_cbk = &crypt_dma_error; + + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + + ald_dma_config_struct(&hperh->hdma_m2p.config); + hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_m2p.config.src = (void *)hperh->plain_text; + hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; + hperh->hdma_m2p.config.size = size / 4; + hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; + hperh->hdma_m2p.config.channel = channel_m2p; + ald_dma_config_basic(&(hperh->hdma_m2p)); + + ald_dma_config_struct(&hperh->hdma_p2m.config); + hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; + hperh->hdma_p2m.config.dst = (void *)hperh->cipher_text; + hperh->hdma_p2m.config.size = size / 4; + hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; + hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; + hperh->hdma_p2m.config.channel = channel_p2m; + ald_dma_config_basic(&(hperh->hdma_p2m)); + + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; } /** @@ -651,73 +612,71 @@ ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, - uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) +ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t * cipher_text, + uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) { - if (hperh->init.mode == CRYPT_MODE_CTR) - return ald_crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m); - - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if (plain_text == NULL || cipher_text == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - - hperh->plain_text = plain_text; - hperh->cipher_text = cipher_text; - hperh->size = size; - hperh->count = size; - - if (hperh->hdma_m2p.perh == NULL) - hperh->hdma_m2p.perh = DMA0; - - if (hperh->hdma_p2m.perh == NULL) - hperh->hdma_p2m.perh = DMA0; - - - hperh->hdma_m2p.cplt_arg = NULL; - hperh->hdma_m2p.cplt_cbk = NULL; - hperh->hdma_m2p.err_arg = NULL; - hperh->hdma_m2p.err_cbk = NULL; - - hperh->hdma_p2m.cplt_arg = (void *)hperh; - hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; - hperh->hdma_p2m.err_arg = (void *)hperh; - hperh->hdma_p2m.err_cbk = &crypt_dma_error; - - CRYPT_SETDIR(hperh, CRYPT_DECRYPT); - - ald_dma_config_struct(&hperh->hdma_m2p.config); - hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma_m2p.config.src = (void *)hperh->cipher_text; - hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; - hperh->hdma_m2p.config.size = size / 4; - hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; - hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; - hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; - hperh->hdma_m2p.config.channel = channel_m2p; - ald_dma_config_basic(&(hperh->hdma_m2p)); - - ald_dma_config_struct(&hperh->hdma_p2m.config); - hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; - hperh->hdma_p2m.config.dst = (void *)hperh->plain_text; - hperh->hdma_p2m.config.size = size / 4; - hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; - hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; - hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; - hperh->hdma_p2m.config.channel = channel_p2m; - ald_dma_config_basic(&(hperh->hdma_p2m)); - - CRYPT_DMA_ENABLE(hperh); - __UNLOCK(hperh); - - return OK; + if (hperh->init.mode == CRYPT_MODE_CTR) + return ald_crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m); + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + if (plain_text == NULL || cipher_text == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + hperh->count = size; + + if (hperh->hdma_m2p.perh == NULL) + hperh->hdma_m2p.perh = DMA0; + if (hperh->hdma_p2m.perh == NULL) + hperh->hdma_p2m.perh = DMA0; + + + hperh->hdma_m2p.cplt_arg = NULL; + hperh->hdma_m2p.cplt_cbk = NULL; + hperh->hdma_m2p.err_arg = NULL; + hperh->hdma_m2p.err_cbk = NULL; + + hperh->hdma_p2m.cplt_arg = (void *)hperh; + hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; + hperh->hdma_p2m.err_arg = (void *)hperh; + hperh->hdma_p2m.err_cbk = &crypt_dma_error; + + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + + ald_dma_config_struct(&hperh->hdma_m2p.config); + hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_m2p.config.src = (void *)hperh->cipher_text; + hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; + hperh->hdma_m2p.config.size = size / 4; + hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; + hperh->hdma_m2p.config.channel = channel_m2p; + ald_dma_config_basic(&(hperh->hdma_m2p)); + + ald_dma_config_struct(&hperh->hdma_p2m.config); + hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; + hperh->hdma_p2m.config.dst = (void *)hperh->plain_text; + hperh->hdma_p2m.config.size = size / 4; + hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; + hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; + hperh->hdma_p2m.config.channel = channel_p2m; + ald_dma_config_basic(&(hperh->hdma_p2m)); + + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; } /** @@ -737,11 +696,11 @@ ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_tex */ ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh) { - __LOCK(hperh); - CRYPT_DMA_DISABLE(hperh); - __UNLOCK(hperh); + __LOCK(hperh); + CRYPT_DMA_DISABLE(hperh); + __UNLOCK(hperh); - return OK; + return OK; } @@ -753,11 +712,11 @@ ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh) */ ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh) { - __LOCK(hperh); - CRYPT_DMA_ENABLE(hperh); - __UNLOCK(hperh); + __LOCK(hperh); + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -768,12 +727,12 @@ ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh) */ ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh) { - __LOCK(hperh); - CRYPT_DMA_DISABLE(hperh); - __UNLOCK(hperh); + __LOCK(hperh); + CRYPT_DMA_DISABLE(hperh); + __UNLOCK(hperh); - hperh->state = CRYPT_STATE_READY; - return OK; + hperh->state = CRYPT_STATE_READY; + return OK; } #endif @@ -785,46 +744,39 @@ ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh) */ void ald_crypt_irq_handler(crypt_handle_t *hperh) { - uint32_t i; - uint32_t *in_buf; - uint32_t *out_buf; - - if (READ_BIT(hperh->perh->CON, CRYPT_CON_ENCS_MSK)) - { - in_buf = (uint32_t *)hperh->plain_text + hperh->count; - out_buf = (uint32_t *)hperh->cipher_text + hperh->count - hperh->step; - } - else - { - in_buf = (uint32_t *)hperh->cipher_text + hperh->count; - out_buf = (uint32_t *)hperh->plain_text + hperh->count - hperh->step; - } - - if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) - { - ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF); - } - - for (i = 0; i < hperh->step; i++) - *out_buf++ = CRYPT_READ_FIFO(hperh); - - hperh->count += hperh->step; - - if (hperh->count > (hperh->size / 4)) - { - hperh->count = 0; - hperh->state = CRYPT_STATE_READY; - - if (hperh->crypt_cplt_cbk) - hperh->crypt_cplt_cbk(hperh); - } - else - { - for (i = 0; i < hperh->step; i++) - { - CRYPT_WRITE_FIFO(hperh, *in_buf++); - } - } + uint32_t i; + uint32_t *in_buf; + uint32_t *out_buf; + + if (READ_BIT(hperh->perh->CON, CRYPT_CON_ENCS_MSK)) { + in_buf = (uint32_t *)hperh->plain_text + hperh->count; + out_buf = (uint32_t *)hperh->cipher_text + hperh->count - hperh->step; + } + else { + in_buf = (uint32_t *)hperh->cipher_text + hperh->count; + out_buf = (uint32_t *)hperh->plain_text + hperh->count - hperh->step; + } + + if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) { + ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF); + } + + for (i = 0; i < hperh->step; i++) + *out_buf++ = CRYPT_READ_FIFO(hperh); + + hperh->count += hperh->step; + if (hperh->count > (hperh->size / 4)) { + hperh->count = 0; + hperh->state = CRYPT_STATE_READY; + + if (hperh->crypt_cplt_cbk) + hperh->crypt_cplt_cbk(hperh); + } + else { + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *in_buf++); + } + } } /** * @} @@ -849,15 +801,14 @@ void ald_crypt_irq_handler(crypt_handle_t *hperh) */ void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state) { - assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT(hperh->perh)); - if (it == CRYPT_IT_IT) - { - CLEAR_BIT(CRYPT->CON, CRYPT_CON_IE_MSK); - CRYPT->CON |= (state << CRYPT_CON_IE_POS); - } + if (it == CRYPT_IT_IT) { + CLEAR_BIT(CRYPT->CON, CRYPT_CON_IE_MSK); + CRYPT->CON |= (state << CRYPT_CON_IE_POS); + } - return; + return; } /** @brief Check whether the specified CRYPT flag is set or not. @@ -871,13 +822,13 @@ void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_ */ flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) { - assert_param(IS_CRYPT(hperh->perh)); - assert_param(IS_CRYPT_FLAG(flag)); + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_FLAG(flag)); - if (CRYPT->IF & flag) - return SET; + if (CRYPT->IF & flag) + return SET; - return RESET; + return RESET; } /** @brief Clear the specified CRYPT pending flags. @@ -891,11 +842,11 @@ flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag */ void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) { - assert_param(IS_CRYPT(hperh->perh)); - assert_param(IS_CRYPT_FLAG(flag)); + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_FLAG(flag)); - WRITE_REG(CRYPT->IFC, flag); - return; + WRITE_REG(CRYPT->IFC, flag); + return; } /** @@ -911,12 +862,12 @@ void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) */ it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it) { - assert_param(IS_CRYPT_IT(it)); + assert_param(IS_CRYPT_IT(it)); - if (READ_BIT(CRYPT->CON, CRYPT_CON_IE_MSK)) - return SET; + if (READ_BIT(CRYPT->CON, CRYPT_CON_IE_MSK)) + return SET; - return RESET; + return RESET; } @@ -937,10 +888,10 @@ it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it) */ crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh) { - assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT(hperh->perh)); - return hperh->state; + return hperh->state; } /** @@ -964,26 +915,26 @@ crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh) */ void crypt_reset(crypt_handle_t *hperh) { - hperh->perh->DATA[0] = 0x0; - hperh->perh->DATA[1] = 0x0; - hperh->perh->DATA[2] = 0x0; - hperh->perh->DATA[3] = 0x0; - hperh->perh->KEY[0] = 0x0; - hperh->perh->KEY[1] = 0x0; - hperh->perh->KEY[2] = 0x0; - hperh->perh->KEY[3] = 0x0; - hperh->perh->KEY[4] = 0x0; - hperh->perh->KEY[5] = 0x0; - hperh->perh->KEY[6] = 0x0; - hperh->perh->KEY[7] = 0x0; - hperh->perh->IV[0] = 0x0; - hperh->perh->IV[1] = 0x0; - hperh->perh->IV[2] = 0x0; - hperh->perh->IV[3] = 0x0; - hperh->perh->CON = 0x0; - - hperh->state = CRYPT_STATE_READY; - __UNLOCK(hperh); + hperh->perh->DATA[0] = 0x0; + hperh->perh->DATA[1] = 0x0; + hperh->perh->DATA[2] = 0x0; + hperh->perh->DATA[3] = 0x0; + hperh->perh->KEY[0] = 0x0; + hperh->perh->KEY[1] = 0x0; + hperh->perh->KEY[2] = 0x0; + hperh->perh->KEY[3] = 0x0; + hperh->perh->KEY[4] = 0x0; + hperh->perh->KEY[5] = 0x0; + hperh->perh->KEY[6] = 0x0; + hperh->perh->KEY[7] = 0x0; + hperh->perh->IV[0] = 0x0; + hperh->perh->IV[1] = 0x0; + hperh->perh->IV[2] = 0x0; + hperh->perh->IV[3] = 0x0; + hperh->perh->CON = 0x0; + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); } #ifdef ALD_DMA @@ -995,18 +946,18 @@ void crypt_reset(crypt_handle_t *hperh) */ static void crypt_dma_crypt_cplt(void *arg) { - crypt_handle_t *hperh = (crypt_handle_t *)arg; + crypt_handle_t *hperh = (crypt_handle_t *)arg; - CRYPT_DMA_DISABLE(hperh); - hperh->count = 0; - hperh->plain_text = NULL; - hperh->cipher_text = NULL; - hperh->size = 0; + CRYPT_DMA_DISABLE(hperh); + hperh->count = 0; + hperh->plain_text = NULL; + hperh->cipher_text = NULL; + hperh->size = 0; - hperh->state = CRYPT_STATE_READY; + hperh->state = CRYPT_STATE_READY; - if (hperh->crypt_cplt_cbk) - hperh->crypt_cplt_cbk(hperh); + if (hperh->crypt_cplt_cbk) + hperh->crypt_cplt_cbk(hperh); } /** @@ -1017,18 +968,18 @@ static void crypt_dma_crypt_cplt(void *arg) */ static void crypt_dma_error(void *arg) { - crypt_handle_t *hperh = (crypt_handle_t *)arg; - CRYPT_DMA_DISABLE(hperh); + crypt_handle_t *hperh = (crypt_handle_t *)arg; + CRYPT_DMA_DISABLE(hperh); - hperh->count = 0; - hperh->plain_text = NULL; - hperh->cipher_text = NULL; - hperh->size = 0; + hperh->count = 0; + hperh->plain_text = NULL; + hperh->cipher_text = NULL; + hperh->size = 0; - hperh->state = CRYPT_STATE_READY; + hperh->state = CRYPT_STATE_READY; - if (hperh->err_cplt_cbk) - hperh->err_cplt_cbk(hperh); + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); } #endif /** diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_dma.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_dma.c index 5847fa627dd02189c59ee19a0fd597cd703c20f6..f3c125578de145f3f890eaacf04392e482439abf 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_dma.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_dma.c @@ -73,7 +73,7 @@ /** @defgroup DMA_Private_Variables DMA Private Variables * @{ */ -dma_descriptor_t dma0_ctrl_base[28] __attribute__((aligned(512))); +dma_descriptor_t dma0_ctrl_base[28] __attribute__ ((aligned(512))); dma_call_back_t dma0_cbk[6]; /** * @} @@ -93,74 +93,74 @@ dma_call_back_t dma0_cbk[6]; */ static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config_t *p) { - dma_descriptor_t *descr; - - assert_param(IS_DMA(DMAx)); - assert_param(IS_CYCLECTRL_TYPE(mode)); - assert_param(p->src != NULL); - assert_param(p->dst != NULL); - assert_param(IS_DMA_DATA_SIZE(p->size)); - assert_param(IS_DMA_DATASIZE_TYPE(p->data_width)); - assert_param(IS_DMA_DATAINC_TYPE(p->src_inc)); - assert_param(IS_DMA_DATAINC_TYPE(p->dst_inc)); - assert_param(IS_DMA_ARBITERCONFIG_TYPE(p->R_power)); - assert_param(IS_FUNC_STATE(p->primary)); - assert_param(IS_FUNC_STATE(p->burst)); - assert_param(IS_FUNC_STATE(p->high_prio)); - assert_param(IS_FUNC_STATE(p->iterrupt)); - assert_param(IS_DMA_MSEL_TYPE(p->msel)); - assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel)); - assert_param(IS_DMA_CHANNEL(p->channel)); - - if (p->primary) - descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + p->channel; - else - descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + p->channel; - - if (p->src_inc == DMA_DATA_INC_NONE) - descr->src = p->src; - else - descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << p->data_width)); - - if (p->dst_inc == DMA_DATA_INC_NONE) - descr->dst = p->dst; - else - descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << p->data_width)); - - descr->ctrl.cycle_ctrl = mode; - descr->ctrl.next_useburst = 0; - descr->ctrl.n_minus_1 = p->size - 1; - descr->ctrl.R_power = p->R_power; - descr->ctrl.src_prot_ctrl = 0, - descr->ctrl.dst_prot_ctrl = 0, - descr->ctrl.src_size = p->data_width; - descr->ctrl.src_inc = p->src_inc; - descr->ctrl.dst_size = p->data_width; - descr->ctrl.dst_inc = p->dst_inc; - - if (p->primary) - WRITE_REG(DMAx->CHPRIALTCLR, (1 << p->channel)); - else - WRITE_REG(DMAx->CHPRIALTSET, (1 << p->channel)); - - if (p->burst) - WRITE_REG(DMAx->CHUSEBURSTSET, (1 << p->channel)); - else - WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << p->channel)); - - if (p->high_prio) - WRITE_REG(DMAx->CHPRSET, (1 << p->channel)); - else - WRITE_REG(DMAx->CHPRCLR, (1 << p->channel)); - - if (p->iterrupt) - SET_BIT(DMAx->IER, (1 << p->channel)); - else - CLEAR_BIT(DMAx->IER, (1 << p->channel)); - - MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSEL_MSK, p->msel << DMA_CH0_SELCON_MSEL_POSS); - MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSIGSEL_MSK, p->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); - return; + dma_descriptor_t *descr; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_CYCLECTRL_TYPE(mode)); + assert_param(p->src != NULL); + assert_param(p->dst != NULL); + assert_param(IS_DMA_DATA_SIZE(p->size)); + assert_param(IS_DMA_DATASIZE_TYPE(p->data_width)); + assert_param(IS_DMA_DATAINC_TYPE(p->src_inc)); + assert_param(IS_DMA_DATAINC_TYPE(p->dst_inc)); + assert_param(IS_DMA_ARBITERCONFIG_TYPE(p->R_power)); + assert_param(IS_FUNC_STATE(p->primary)); + assert_param(IS_FUNC_STATE(p->burst)); + assert_param(IS_FUNC_STATE(p->high_prio)); + assert_param(IS_FUNC_STATE(p->interrupt)); + assert_param(IS_DMA_MSEL_TYPE(p->msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel)); + assert_param(IS_DMA_CHANNEL(p->channel)); + + if (p->primary) + descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + p->channel; + else + descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + p->channel; + + if (p->src_inc == DMA_DATA_INC_NONE) + descr->src = p->src; + else + descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << (uint32_t)p->src_inc)); + + if (p->dst_inc == DMA_DATA_INC_NONE) + descr->dst = p->dst; + else + descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << (uint32_t)p->dst_inc)); + + descr->ctrl.cycle_ctrl = mode; + descr->ctrl.next_useburst = 0; + descr->ctrl.n_minus_1 = p->size - 1; + descr->ctrl.R_power = p->R_power; + descr->ctrl.src_prot_ctrl = 0, + descr->ctrl.dst_prot_ctrl = 0, + descr->ctrl.src_size = p->data_width; + descr->ctrl.src_inc = p->src_inc; + descr->ctrl.dst_size = p->data_width; + descr->ctrl.dst_inc = p->dst_inc; + + if (p->primary) + WRITE_REG(DMAx->CHPRIALTCLR, (1 << p->channel)); + else + WRITE_REG(DMAx->CHPRIALTSET, (1 << p->channel)); + + if (p->burst) + WRITE_REG(DMAx->CHUSEBURSTSET, (1 << p->channel)); + else + WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << p->channel)); + + if (p->high_prio) + WRITE_REG(DMAx->CHPRSET, (1 << p->channel)); + else + WRITE_REG(DMAx->CHPRCLR, (1 << p->channel)); + + if (p->interrupt) + SET_BIT(DMAx->IER, (1 << p->channel)); + else + CLEAR_BIT(DMAx->IER, (1 << p->channel)); + + MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSEL_MSK, p->msel << DMA_CH0_SELCON_MSEL_POSS); + MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSIGSEL_MSK, p->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); + return; } /** @@ -169,31 +169,27 @@ static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config */ void ald_dma_irq_handler(void) { - uint32_t i, reg = DMA0->IFLAG; - - for (i = 0; i < DMA_CH_COUNT; ++i) - { - if (READ_BIT(reg, (1 << i))) - { - if (dma0_cbk[i].cplt_cbk != NULL) - dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg); - - ald_dma_clear_flag_status(DMA0, i); - } - } - - if (READ_BIT(reg, (1U << DMA_ERR))) - { - ald_dma_clear_flag_status(DMA0, DMA_ERR); - - for (i = 0; i < DMA_CH_COUNT; ++i) - { - if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL)) - dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg); - } - } - - return; + uint32_t i, reg = DMA0->IFLAG; + + for (i = 0; i < DMA_CH_COUNT; ++i) { + if (READ_BIT(reg, (1 << i))) { + if (dma0_cbk[i].cplt_cbk != NULL) + dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg); + + ald_dma_clear_flag_status(DMA0, i); + } + } + + if (READ_BIT(reg, (1U << DMA_ERR))) { + ald_dma_clear_flag_status(DMA0, DMA_ERR); + + for (i = 0; i < DMA_CH_COUNT; ++i) { + if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL)) + dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg); + } + } + + return; } /** * @} @@ -230,6 +226,9 @@ void ald_dma_irq_handler(void) (+) ald_dma_config_struct(): Configure dma_config_t structure using default parameter. + (+) ald_dma_config_sg_alt_desc(): Configure dma_descriptor_t + structure using specified parameter. This function used + in scatter-gather mode(memory or peripheral). @endverbatim * @{ */ @@ -241,24 +240,24 @@ void ald_dma_irq_handler(void) */ void ald_dma_reset(DMA_TypeDef *DMAx) { - uint32_t i; + uint32_t i; - assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA(DMAx)); - WRITE_REG(DMAx->CFG, 0x0); - WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF); - WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF); - WRITE_REG(DMAx->CHENCLR, 0xFFF); - WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF); - WRITE_REG(DMAx->CHPRCLR, 0xFFF); - WRITE_REG(DMAx->ERRCLR, 0x1); - WRITE_REG(DMAx->IER, 0x0); - WRITE_REG(DMAx->ICFR, 0x80000FFF); + WRITE_REG(DMAx->CFG, 0x0); + WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF); + WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF); + WRITE_REG(DMAx->CHENCLR, 0xFFF); + WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF); + WRITE_REG(DMAx->CHPRCLR, 0xFFF); + WRITE_REG(DMAx->ERRCLR, 0x1); + WRITE_REG(DMAx->IER, 0x0); + WRITE_REG(DMAx->ICFR, 0x80000FFF); - for (i = 0; i < DMA_CH_COUNT; ++i) - WRITE_REG(DMAx->CH_SELCON[i], 0x0); + for (i = 0; i < DMA_CH_COUNT; ++i) + WRITE_REG(DMAx->CH_SELCON[i], 0x0); - return; + return; } /** @@ -269,20 +268,20 @@ void ald_dma_reset(DMA_TypeDef *DMAx) */ void ald_dma_init(DMA_TypeDef *DMAx) { - assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA(DMAx)); - memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base)); - memset(dma0_cbk, 0x0, sizeof(dma0_cbk)); + memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base)); + memset(dma0_cbk, 0x0, sizeof(dma0_cbk)); - ald_dma_reset(DMAx); - NVIC_SetPriority(DMA_IRQn, 2); - NVIC_EnableIRQ(DMA_IRQn); - SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK); + ald_dma_reset(DMAx); + NVIC_SetPriority(DMA_IRQn, 2); + NVIC_EnableIRQ(DMA_IRQn); + SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK); - WRITE_REG(DMAx->CTRLBASE, (uint32_t)&dma0_ctrl_base); - SET_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE_MSK); + WRITE_REG(DMAx->CTRLBASE, (uint32_t)&dma0_ctrl_base); + SET_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE_MSK); - return; + return; } /** @@ -293,16 +292,53 @@ void ald_dma_init(DMA_TypeDef *DMAx) */ void ald_dma_config_struct(dma_config_t *p) { - p->data_width = DMA_DATA_SIZE_BYTE; - p->src_inc = DMA_DATA_INC_BYTE; - p->dst_inc = DMA_DATA_INC_BYTE; - p->R_power = DMA_R_POWER_1; - p->primary = ENABLE; - p->burst = DISABLE; - p->high_prio = DISABLE; - p->iterrupt = ENABLE; - - return; + p->data_width = DMA_DATA_SIZE_BYTE; + p->src_inc = DMA_DATA_INC_BYTE; + p->dst_inc = DMA_DATA_INC_BYTE; + p->R_power = DMA_R_POWER_1; + p->primary = ENABLE; + p->burst = DISABLE; + p->high_prio = DISABLE; + p->interrupt = ENABLE; + + return; +} + +/** + * @brief Configure dma_descriptor_t structure using specified parameter. + * @note This function used in scatter-gather mode(memory or peripheral). + * @param desc: Address of the alternate descriptor. + * @param config: Pointer to the dma_config_t structure. + * @param memory: Memory or peripheral scatter-gather. + * @retval None + */ +void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory) +{ + if ((desc == NULL) || (config == NULL)) + return; + + if (config->src_inc == DMA_DATA_INC_NONE) + desc->src = config->src; + else + desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width)); + + if (config->dst_inc == DMA_DATA_INC_NONE) + desc->dst = config->dst; + else + desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width)); + + desc->ctrl.cycle_ctrl = memory ? DMA_CYCLE_CTRL_MEM_SG_ALTERNATE : DMA_CYCLE_CTRL_PER_SG_ALTERNATE; + desc->ctrl.next_useburst = memory ? 0 : 1; + desc->ctrl.n_minus_1 = config->size - 1; + desc->ctrl.R_power = config->R_power; + desc->ctrl.src_prot_ctrl = 0; + desc->ctrl.dst_prot_ctrl = 0; + desc->ctrl.src_size = config->data_width; + desc->ctrl.src_inc = config->src_inc; + desc->ctrl.dst_size = config->data_width; + desc->ctrl.dst_inc = config->dst_inc; + + return; } /** @@ -328,6 +364,7 @@ void ald_dma_config_struct(dma_config_t *p) (++) ald_dma_config_auto_easy(): Configure DMA channel according to the specified parameter. If you want use the dma easily, you can invoke this function. + (++) ald_dma_config_sg_mem(): Carry data used scatter-gather mode. (+) Carry data from peripheral to memory or from memory to peripheral, this mode APIs are: (++) ald_dma_config_basic(): Configure DMA channel according to @@ -336,6 +373,8 @@ void ald_dma_config_struct(dma_config_t *p) (++) ald_dma_config_basic_easy(): Configure DMA channel according to the specified parameter. If you want use the dma easily, you can invoke this function. + (++) ald_dma_ping_pong(): Carry data used ping-pong mode. + (++) ald_dma_config_sg_per(): Carry data used scatter-gather mode. @endverbatim * @{ @@ -351,17 +390,17 @@ void ald_dma_config_struct(dma_config_t *p) */ void ald_dma_config_auto(dma_handle_t *hperh) { - dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; - dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; - dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; - dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; - dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config); + dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; + dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; + dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; + dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; + dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config); - ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); - WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); - SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); - return; + return; } /** @@ -376,39 +415,35 @@ void ald_dma_config_auto(dma_handle_t *hperh) */ void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size) { - dma_descriptor_t *descr; - - if (hperh->config.primary) - descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; - else - descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; - - if (src) - { - if (hperh->config.src_inc == DMA_DATA_INC_NONE) - descr->src = src; - else - descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width)); - } - - if (dst) - { - if (hperh->config.dst_inc == DMA_DATA_INC_NONE) - descr->dst = dst; - else - descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width)); - } - - ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); - descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; - descr->ctrl.n_minus_1 = size - 1; - WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); - SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); - return; + dma_descriptor_t *descr; + + if (hperh->config.primary) + descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; + else + descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; + + if (src) { + if (hperh->config.src_inc == DMA_DATA_INC_NONE) + descr->src = src; + else + descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width)); + } + + if (dst) { + if (hperh->config.dst_inc == DMA_DATA_INC_NONE) + descr->dst = dst; + else + descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width)); + } + + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; + descr->ctrl.n_minus_1 = size - 1; + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); + return; } - - /** * @brief Configure DMA channel according to the specified parameter. * The DMA mode is automatic. This mode is used to carry data @@ -420,33 +455,32 @@ void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t si * @param size: The total number of DMA transfers that DMA cycle contains * @param channel: Channel index which will be used. * @param cbk: DMA complete callback function - * * @retval None */ void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, - uint16_t size, uint8_t channel, void (*cbk)(void *arg)) + uint16_t size, uint8_t channel, void (*cbk)(void *arg)) { - dma_handle_t hperh; + dma_handle_t hperh; - assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA(DMAx)); - ald_dma_config_struct(&hperh.config); - hperh.config.src = src; - hperh.config.dst = dst; - hperh.config.size = size; - hperh.config.msel = DMA_MSEL_NONE; - hperh.config.msigsel = DMA_MSIGSEL_NONE; - hperh.config.channel = channel; + ald_dma_config_struct(&hperh.config); + hperh.config.src = src; + hperh.config.dst = dst; + hperh.config.size = size; + hperh.config.msel = DMA_MSEL_NONE; + hperh.config.msigsel = DMA_MSIGSEL_NONE; + hperh.config.channel = channel; - hperh.perh = DMAx; - hperh.cplt_cbk = cbk; - hperh.cplt_arg = NULL; - hperh.err_cbk = NULL; + hperh.perh = DMAx; + hperh.cplt_cbk = cbk; + hperh.cplt_arg = NULL; + hperh.err_cbk = NULL; - ald_dma_clear_flag_status(DMAx, channel); - ald_dma_config_auto(&hperh); + ald_dma_clear_flag_status(DMAx, channel); + ald_dma_config_auto(&hperh); - return; + return; } /** @@ -460,16 +494,16 @@ void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, */ void ald_dma_config_basic(dma_handle_t *hperh) { - dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; - dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; - dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; - dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; + dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; + dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; + dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; + dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; - ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); - dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config); - WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config); + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); - return; + return; } /** @@ -484,35 +518,33 @@ void ald_dma_config_basic(dma_handle_t *hperh) */ void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size) { - dma_descriptor_t *descr; - - if (hperh->config.primary) - descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; - else - descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; - - if (src) - { - if (hperh->config.src_inc == DMA_DATA_INC_NONE) - descr->src = src; - else - descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width)); - } - - if (dst) - { - if (hperh->config.dst_inc == DMA_DATA_INC_NONE) - descr->dst = dst; - else - descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width)); - } - - ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); - descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; - descr->ctrl.n_minus_1 = size - 1; - WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); - - return; + dma_descriptor_t *descr; + + if (hperh->config.primary) + descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; + else + descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; + + if (src) { + if (hperh->config.src_inc == DMA_DATA_INC_NONE) + descr->src = src; + else + descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width)); + } + + if (dst) { + if (hperh->config.dst_inc == DMA_DATA_INC_NONE) + descr->dst = dst; + else + descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width)); + } + + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; + descr->ctrl.n_minus_1 = size - 1; + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + + return; } /** @@ -528,42 +560,248 @@ void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t s * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t * @param channel: Channel index which will be used * @param cbk: DMA complete callback function - * * @retval None - * - */ + */ void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, - dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) + dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) { - dma_handle_t hperh; + dma_handle_t hperh; + + assert_param(IS_DMA(DMAx)); + ald_dma_config_struct(&hperh.config); - assert_param(IS_DMA(DMAx)); - ald_dma_config_struct(&hperh.config); + if (((uint32_t)src) >= 0x40000000) + hperh.config.src_inc = DMA_DATA_INC_NONE; - if (((uint32_t)src) >= 0x40000000) - hperh.config.src_inc = DMA_DATA_INC_NONE; + if (((uint32_t)dst) >= 0x40000000) + hperh.config.dst_inc = DMA_DATA_INC_NONE; - if (((uint32_t)dst) >= 0x40000000) - hperh.config.dst_inc = DMA_DATA_INC_NONE; + hperh.config.src = src; + hperh.config.dst = dst; + hperh.config.size = size; + hperh.config.msel = msel; + hperh.config.msigsel = msigsel; + hperh.config.channel = channel; - hperh.config.src = src; - hperh.config.dst = dst; - hperh.config.size = size; - hperh.config.msel = msel; - hperh.config.msigsel = msigsel; - hperh.config.channel = channel; + hperh.perh = DMAx; + hperh.cplt_cbk = cbk; + hperh.cplt_arg = NULL; + hperh.err_cbk = NULL; - hperh.perh = DMAx; - hperh.cplt_cbk = cbk; - hperh.cplt_arg = NULL; - hperh.err_cbk = NULL; + ald_dma_clear_flag_status(DMAx, channel); + ald_dma_config_basic(&hperh); - ald_dma_clear_flag_status(DMAx, channel); - ald_dma_config_basic(&hperh); + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is ping-pong. + * @note The ping-pong mode does not support memory to memory. + * @param DMAx: Pointer to DMA peripheral. + * @param config: Pointer to the dma_config_t structure which contains + * the specified parameters. + * @param first: Whether it is the first transmission. 1-first, 0-not first. + * @param cbk: DMA complete callback function. + * @retval None + */ +void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config, + uint8_t first, void (*cbk)(void *arg)) +{ + dma_descriptor_t *desc; + + assert_param(IS_DMA(DMAx)); + assert_param(config->src != NULL); + assert_param(config->dst != NULL); + assert_param(IS_DMA_DATA_SIZE(config->size)); + assert_param(IS_DMA_DATASIZE_TYPE(config->data_width)); + assert_param(IS_DMA_DATAINC_TYPE(config->src_inc)); + assert_param(IS_DMA_DATAINC_TYPE(config->dst_inc)); + assert_param(IS_DMA_ARBITERCONFIG_TYPE(config->R_power)); + assert_param(IS_FUNC_STATE(config->primary)); + assert_param(IS_FUNC_STATE(config->burst)); + assert_param(IS_FUNC_STATE(config->high_prio)); + assert_param(IS_FUNC_STATE(config->interrupt)); + assert_param(IS_DMA_MSEL_TYPE(config->msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(config->msigsel)); + assert_param(IS_DMA_CHANNEL(config->channel)); + + dma0_cbk[config->channel].cplt_cbk = cbk; + dma0_cbk[config->channel].err_cbk = NULL; + dma0_cbk[config->channel].cplt_arg = NULL; + dma0_cbk[config->channel].err_arg = NULL; + + if (config->primary) + desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + config->channel; + else + desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + config->channel; + + if (config->src_inc == DMA_DATA_INC_NONE) + desc->src = config->src; + else + desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width)); + + if (config->dst_inc == DMA_DATA_INC_NONE) + desc->dst = config->dst; + else + desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width)); + + desc->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PINGPONG; + desc->ctrl.next_useburst = 0; + desc->ctrl.n_minus_1 = config->size - 1; + desc->ctrl.R_power = config->R_power; + desc->ctrl.src_prot_ctrl = 0, + desc->ctrl.dst_prot_ctrl = 0, + desc->ctrl.src_size = config->data_width; + desc->ctrl.src_inc = config->src_inc; + desc->ctrl.dst_size = config->data_width; + desc->ctrl.dst_inc = config->dst_inc; + + if (!first) + return; + + if (config->primary) + WRITE_REG(DMAx->CHPRIALTCLR, (1 << config->channel)); + else + WRITE_REG(DMAx->CHPRIALTSET, (1 << config->channel)); + + if (config->burst) + WRITE_REG(DMAx->CHUSEBURSTSET, (1 << config->channel)); + else + WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << config->channel)); + + if (config->high_prio) + WRITE_REG(DMAx->CHPRSET, (1 << config->channel)); + else + WRITE_REG(DMAx->CHPRCLR, (1 << config->channel)); + + if (config->interrupt) + SET_BIT(DMAx->IER, (1 << config->channel)); + else + CLEAR_BIT(DMAx->IER, (1 << config->channel)); + + MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSEL_MSK, config->msel << DMA_CH0_SELCON_MSEL_POSS); + MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSIGSEL_MSK, config->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); + + WRITE_REG(DMAx->ICFR, (1 << config->channel)); + WRITE_REG(DMAx->CHENSET, (1 << config->channel)); + + return; +} - return; +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is memory scatter-gather. + * @param DMAx: Pointer to DMA peripheral. + * @param desc: Pointer to first alternate descriptor. + * @param nr: Number of the alternate descriptor. + * @param channel: Channel index which will be used. + * @param cbk: DMA complete callback function. + * @retval None + */ +void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, + uint8_t channel, void (*cbk)(void *arg)) +{ + dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_CHANNEL(channel)); + + if ((desc == NULL) || (nr == 0)) + return; + + dma0_cbk[channel].cplt_cbk = cbk; + dma0_cbk[channel].err_cbk = NULL; + dma0_cbk[channel].cplt_arg = NULL; + dma0_cbk[channel].err_arg = NULL; + + tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD)); + tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD)); + tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_MEM_SG_PRIMARY; + tmp->ctrl.next_useburst = 0; + tmp->ctrl.n_minus_1 = (nr << 2) - 1; + tmp->ctrl.R_power = DMA_R_POWER_4; + tmp->ctrl.src_prot_ctrl = 0, + tmp->ctrl.dst_prot_ctrl = 0, + tmp->ctrl.src_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.src_inc = DMA_DATA_INC_WORD; + tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.dst_inc = DMA_DATA_INC_WORD; + + desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; + WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel)); + WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << channel)); + WRITE_REG(DMAx->CHPRCLR, (1 << channel)); + + WRITE_REG(DMAx->ICFR, (1 << channel)); + SET_BIT(DMAx->IER, (1 << channel)); + WRITE_REG(DMAx->CHENSET, (1 << channel)); + SET_BIT(DMAx->CHSWREQ, (1 << channel)); + + return; } +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is peripheral scatter-gather. + * @note The size of the first transmission must be 5. + * @param DMAx: Pointer to DMA peripheral. + * @param desc: Pointer to first alternate descriptor. + * @param nr: Number of the alternate descriptor. + * @param burst: 1-Enable burst, 0-Disable burst. + * @param msel: Input source to DMA channel @ref dma_msel_t + * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t + * @param channel: Channel index which will be used. + * @param cbk: DMA complete callback function. + * @retval None + */ +void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, + dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) +{ + dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_MSEL_TYPE(msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(msigsel)); + assert_param(IS_DMA_CHANNEL(channel)); + + if ((desc == NULL) || (nr == 0)) + return; + + dma0_cbk[channel].cplt_cbk = cbk; + dma0_cbk[channel].err_cbk = NULL; + dma0_cbk[channel].cplt_arg = NULL; + dma0_cbk[channel].err_arg = NULL; + + tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD)); + tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD)); + tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PER_SG_PRIMARY; + tmp->ctrl.next_useburst = 0; + tmp->ctrl.n_minus_1 = (nr << 2) - 1; + tmp->ctrl.R_power = DMA_R_POWER_4; + tmp->ctrl.src_prot_ctrl = 0, + tmp->ctrl.dst_prot_ctrl = 0, + tmp->ctrl.src_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.src_inc = DMA_DATA_INC_WORD; + tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.dst_inc = DMA_DATA_INC_WORD; + + desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; + WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel)); + burst ? (DMAx->CHUSEBURSTSET = (1 << channel)) : (DMAx->CHUSEBURSTCLR, (1 << channel)); + WRITE_REG(DMAx->CHPRCLR, (1 << channel)); + + MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSEL_MSK, msel << DMA_CH0_SELCON_MSEL_POSS); + MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSIGSEL_MSK, msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); + + WRITE_REG(DMAx->ICFR, (1 << channel)); + SET_BIT(DMAx->IER, (1 << channel)); + WRITE_REG(DMAx->CHENSET, (1 << channel)); + + return; +} /** * @} */ @@ -605,28 +843,26 @@ void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t */ void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) { - dma_descriptor_t *descr, *alt_descr; - - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_CHANNEL(channel)); - assert_param(IS_FUNC_STATE(state)); - - descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; - alt_descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; - - if (state) - { - WRITE_REG(DMAx->CHENSET, (1 << channel)); - } - else - { - memset(descr, 0x00, sizeof(dma_descriptor_t)); - memset(alt_descr, 0x00, sizeof(dma_descriptor_t)); - WRITE_REG(DMAx->CH_SELCON[channel], 0x0); - WRITE_REG(DMAx->CHENCLR, (1 << channel)); - } - - return; + dma_descriptor_t *descr, *alt_descr; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_FUNC_STATE(state)); + + descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + alt_descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + + if (state) { + WRITE_REG(DMAx->CHENSET, (1 << channel)); + } + else { + memset(descr, 0x00, sizeof(dma_descriptor_t)); + memset(alt_descr, 0x00, sizeof(dma_descriptor_t)); + WRITE_REG(DMAx->CH_SELCON[channel], 0x0); + WRITE_REG(DMAx->CHENCLR, (1 << channel)); + } + + return; } /** @@ -643,16 +879,16 @@ void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t stat */ void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) { - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_IT_TYPE(channel)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + assert_param(IS_FUNC_STATE(state)); - if (state) - SET_BIT(DMAx->IER, (1 << channel)); - else - CLEAR_BIT(DMAx->IER, (1 << channel)); + if (state) + SET_BIT(DMAx->IER, (1 << channel)); + else + CLEAR_BIT(DMAx->IER, (1 << channel)); - return; + return; } /** @@ -668,13 +904,13 @@ void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t st */ it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel) { - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_IT_TYPE(channel)); + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); - if (READ_BIT(DMAx->IER, (1 << channel))) - return SET; + if (READ_BIT(DMAx->IER, (1 << channel))) + return SET; - return RESET; + return RESET; } /** @@ -690,13 +926,13 @@ it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel) */ flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel) { - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_IT_TYPE(channel)); + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); - if (READ_BIT(DMAx->IFLAG, (1 << channel))) - return SET; + if (READ_BIT(DMAx->IFLAG, (1 << channel))) + return SET; - return RESET; + return RESET; } /** @@ -709,11 +945,42 @@ flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel) */ void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel) { - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_IT_TYPE(channel)); + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + WRITE_REG(DMAx->ICFR, (1 << channel)); + return; +} + +/** + * @brief Get the completion status of the descriptor + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index + * @retval Completion status: + * - DMA_DESCP_CPLT_PRI: Primary descriptor has been completed + * - DMA_DESCP_CPLT_ALT: Alternate descriptor has been completed + * - DMA_DESCP_CPLT_ALL: Both primary and alternate descriptors have been completed + */ +dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel) +{ + uint8_t pri, alt; + dma_descriptor_t *desc; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + pri = desc->ctrl.cycle_ctrl; + desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + alt = desc->ctrl.cycle_ctrl; + + if ((pri == 0) && (alt == 0)) + return DMA_DESCP_CPLT_ALL; - WRITE_REG(DMAx->ICFR, (1 << channel)); - return; + if (pri == 0) + return DMA_DESCP_CPLT_PRI; + else + return DMA_DESCP_CPLT_ALT; } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash.c index b7a3e128c93200e3a8dc5c710403900aefbe5be8..44d25a7f7638ec90b8cb4781c7388b66fd134245 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash.c @@ -27,9 +27,9 @@ #ifdef ALD_FLASH #if defined ( __ICCARM__ ) - #define __RAMFUNC __ramfunc +#define __RAMFUNC __ramfunc #else - #define __RAMFUNC +#define __RAMFUNC #endif /** @defgroup Flash_Private_Variables Flash Private Variables @@ -51,23 +51,22 @@ static op_cmd_type OP_CMD = OP_FLASH; */ __RAMFUNC static ald_status_t flash_unlock(void) { - uint16_t i; - uint16_t op_cmd = OP_CMD; + uint16_t i; + uint16_t op_cmd = OP_CMD; - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - return ERROR; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + return ERROR; - FLASH_REG_UNLOCK(); - FLASH_IAP_ENABLE(); - FLASH_REQ(); + FLASH_REG_UNLOCK(); + FLASH_IAP_ENABLE(); + FLASH_REQ(); - for (i = 0; i < 0xFFFF; i++) - { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)) - break; - } + for (i = 0; i < 0xFFFF; i++) { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)) + break; + } - return i == 0xFFFF ? ERROR : OK; + return i == 0xFFFF ? ERROR : OK; } /** @@ -76,19 +75,18 @@ __RAMFUNC static ald_status_t flash_unlock(void) */ __RAMFUNC static ald_status_t flash_lock(void) { - uint16_t i; - uint16_t op_cmd = OP_CMD; + uint16_t i; + uint16_t op_cmd = OP_CMD; - FLASH_REG_UNLOCK(); - WRITE_REG(MSC->FLASHCR, 0x0); + FLASH_REG_UNLOCK(); + WRITE_REG(MSC->FLASHCR, 0x0); - for (i = 0; i < 0xFFFF; i++) - { - if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))) - break; - } + for (i = 0; i < 0xFFFF; i++) { + if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))) + break; + } - return i == 0xFFFF ? ERROR : OK; + return i == 0xFFFF ? ERROR : OK; } /** @@ -98,50 +96,44 @@ __RAMFUNC static ald_status_t flash_lock(void) */ __RAMFUNC ald_status_t flash_page_erase(uint32_t addr) { - uint32_t i; - uint16_t op_cmd = OP_CMD; - - if (flash_unlock() != OK) - goto end; - - if (op_cmd == OP_FLASH) - { - CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); - } - else - { - SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); - } - - WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE); - - for (i = 0; i < 0xFFFF; i++) - { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - continue; - - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK)) - goto end; - - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK)) - goto end; - - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK)) - break; - } - - if (i == 0xFFFF) - goto end; - - if (flash_lock() == ERROR) - goto end; - - return OK; + uint32_t i; + uint16_t op_cmd = OP_CMD; + + if (flash_unlock() != OK) + goto end; + + if (op_cmd == OP_FLASH) { + CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); + } + else { + SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); + } + + WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE); + + for (i = 0; i < 0xFFFF; i++) { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + continue; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK)) + goto end; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK)) + goto end; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK)) + break; + } + + if (i == 0xFFFF) + goto end; + + if (flash_lock() == ERROR) + goto end; + + return OK; end: - flash_lock(); - return ERROR; + flash_lock(); + return ERROR; } /** @@ -154,58 +146,52 @@ end: */ __RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo) { - uint16_t i; - uint16_t prog_len; - uint32_t *p_data = data; - uint16_t op_cmd = OP_CMD; - - if (flash_unlock() != OK) - goto end; - - if (op_cmd == OP_FLASH) - CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - else - SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS); - MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS); - - for (prog_len = 0; prog_len < len; prog_len++) - { - if (fifo) - { - WRITE_REG(MSC->FLASHFIFO, p_data[0]); - WRITE_REG(MSC->FLASHFIFO, p_data[1]); - } - else - { - WRITE_REG(MSC->FLASHDL, p_data[0]); - WRITE_REG(MSC->FLASHDH, p_data[1]); - WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP); - } - - p_data += 2; - - for (i = 0; i < 0xFFFF; i++) - { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - continue; - - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK)) - break; - } - } - - if (i == 0xFFFF) - goto end; - - if (flash_lock() == ERROR) - goto end; - - return OK; + uint16_t i = 0; + uint16_t prog_len; + uint32_t *p_data = data; + uint16_t op_cmd = OP_CMD; + + if (flash_unlock() != OK) + goto end; + + if (op_cmd == OP_FLASH) + CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + else + SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS); + MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS); + + for (prog_len = 0; prog_len < len; prog_len++) { + if (fifo) { + WRITE_REG(MSC->FLASHFIFO, p_data[0]); + WRITE_REG(MSC->FLASHFIFO, p_data[1]); + } + else { + WRITE_REG(MSC->FLASHDL, p_data[0]); + WRITE_REG(MSC->FLASHDH, p_data[1]); + WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP); + } + + p_data += 2; + + for (i = 0; i < 0xFFFF; i++) { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + continue; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK)) + break; + } + } + if (i == 0xFFFF) + goto end; + + if (flash_lock() == ERROR) + goto end; + + return OK; end: - flash_lock(); - return ERROR; + flash_lock(); + return ERROR; } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c index 87595d3ce9af2c9d59bd519618a354a849c231a2..44e8fe7d9c7d6ae18a1d55a6486ef8ba9787bb73 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c @@ -84,30 +84,29 @@ static uint8_t write_buf[FLASH_PAGE_SIZE]; */ static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr) { - uint8_t *addr_to_read; - uint8_t value; - uint32_t index; + uint8_t* addr_to_read; + uint8_t value; + uint32_t index; - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(begin_addr)); - assert_param(IS_FLASH_ADDRESS(end_addr)); + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(begin_addr)); + assert_param(IS_FLASH_ADDRESS(end_addr)); - addr_to_read = (uint8_t *)begin_addr; - index = begin_addr; - value = 0xFF; + addr_to_read = (uint8_t *)begin_addr; + index = begin_addr; + value = 0xFF; - if (begin_addr > end_addr) - return FALSE; + if (begin_addr > end_addr) + return FALSE; - while (index++ <= end_addr) - { - value = *addr_to_read++; + while (index++ <= end_addr) { + value = *addr_to_read++; - if (value != 0xFF) - break; - } + if (value != 0xFF) + break; + } - return value == 0xFF ? FALSE : TRUE; + return value == 0xFF ? FALSE : TRUE; } /** * @} @@ -134,24 +133,23 @@ static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr) */ ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) { - uint32_t i; - uint32_t temp; + uint32_t i; + uint32_t temp; - assert_param(IS_4BYTES_ALIGN(ram_addr)); - assert_param(IS_FLASH_ADDRESS(addr)); - assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + assert_param(IS_4BYTES_ALIGN(ram_addr)); + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); - temp = (uint32_t)ram_addr; + temp = (uint32_t)ram_addr; - if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0)) - return ERROR; + if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0)) + return ERROR; - for (i = 0; i < len; i++) - { - ram_addr[i] = ((uint32_t *)addr)[i]; - } + for (i = 0; i < len; i++) { + ram_addr[i] = ((uint32_t *)addr)[i]; + } - return OK; + return OK; } /** @@ -164,92 +162,84 @@ ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) { - uint32_t index = 0; - uint32_t para = 0; - uint32_t index2 = 0; - uint32_t start_write_addr; - uint32_t end_write_addr; - uint32_t start_word_addr; - uint32_t end_word_addr; - uint16_t len_to_write; - uint32_t len_index; - type_bool_t need_erase_page; - - assert_param(IS_FLASH_ADDRESS(addr)); - assert_param(IS_FLASH_ADDRESS(addr + len - 1)); - - len_to_write = len; - - __disable_irq(); - - while (len_to_write > 0) - { - need_erase_page = FALSE; - - for (index = 0; index < FLASH_PAGE_SIZE; index++) - write_buf[index] = 0xFF; - - start_write_addr = addr + (len - len_to_write); - end_write_addr = addr + len - 1; - end_write_addr = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr) - ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr); - need_erase_page = page_have_writen(FLASH_WORD_ADDR(start_write_addr), - FLASH_WORDEND_ADDR(end_write_addr)); - - if (need_erase_page) - { - if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr), - FLASH_PAGE_SIZE >> 2)) - { - __enable_irq(); - return ERROR; - } - - if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) - { - __enable_irq(); - return ERROR; - } - - para = end_write_addr & (FLASH_PAGE_SIZE - 1); - index = start_write_addr & (FLASH_PAGE_SIZE - 1); - index2 = len - len_to_write; - - while (index <= para) - write_buf[index++] = buf[index2++]; - - index2 = 0; - index = FLASH_PAGE_ADDR(start_write_addr); - para = FLASH_PAGE_ADDR(start_write_addr) + FLASH_PAGE_SIZE; - len_index = FLASH_PAGE_SIZE; - } - else - { - para = end_write_addr & (FLASH_PAGE_SIZE - 1); - index = start_write_addr & (FLASH_PAGE_SIZE - 1); - index2 = len - len_to_write; - - while (index <= para) - write_buf[index++] = buf[index2++]; - - start_word_addr = FLASH_WORD_ADDR(start_write_addr); - end_word_addr = FLASH_WORDEND_ADDR(end_write_addr); - index2 = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr)); - index = start_word_addr; - len_index = end_word_addr - start_word_addr + 1; - } - - if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) - { - __enable_irq(); - return ERROR; - } - - len_to_write = len_to_write - (end_write_addr - start_write_addr + 1); - } - - __enable_irq(); - return OK; + uint32_t index = 0; + uint32_t para = 0; + uint32_t index2 = 0; + uint32_t start_write_addr; + uint32_t end_write_addr; + uint32_t start_word_addr; + uint32_t end_word_addr; + uint16_t len_to_write; + uint32_t len_index; + type_bool_t need_erase_page; + + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + len_to_write = len; + + __disable_irq(); + while (len_to_write > 0) { + need_erase_page = FALSE; + + for (index = 0; index < FLASH_PAGE_SIZE; index++) + write_buf[index] = 0xFF; + + start_write_addr = addr + (len - len_to_write); + end_write_addr = addr + len - 1; + end_write_addr = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr) + ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr); + need_erase_page = page_have_writen(FLASH_WORD_ADDR(start_write_addr), + FLASH_WORDEND_ADDR(end_write_addr)); + + if (need_erase_page) { + if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr), + FLASH_PAGE_SIZE >> 2)) { + __enable_irq(); + return ERROR; + } + + if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) { + __enable_irq(); + return ERROR; + } + + para = end_write_addr & (FLASH_PAGE_SIZE - 1); + index = start_write_addr & (FLASH_PAGE_SIZE - 1); + index2 = len - len_to_write; + + while (index <= para) + write_buf[index++] = buf[index2++]; + + index2 = 0; + index = FLASH_PAGE_ADDR(start_write_addr); + len_index = FLASH_PAGE_SIZE; + } + else { + para = end_write_addr & (FLASH_PAGE_SIZE - 1); + index = start_write_addr & (FLASH_PAGE_SIZE - 1); + index2 = len - len_to_write; + + while (index <= para) + write_buf[index++] = buf[index2++]; + + start_word_addr = FLASH_WORD_ADDR(start_write_addr); + end_word_addr = FLASH_WORDEND_ADDR(end_write_addr); + index2 = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr)); + index = start_word_addr; + len_index = end_word_addr - start_word_addr + 1; + } + + if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) { + __enable_irq(); + return ERROR; + } + + len_to_write = len_to_write - (end_write_addr - start_write_addr + 1); + } + + __enable_irq(); + return OK; } /** @@ -260,81 +250,69 @@ ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) */ ald_status_t ald_flash_erase(uint32_t addr, uint16_t len) { - int32_t index; - int32_t para; - int32_t start_erase_addr; - int32_t end_erase_addr; - uint16_t len_not_erase; - uint32_t len_index; - type_bool_t page_need_save; - - assert_param(IS_FLASH_ADDRESS(addr)); - assert_param(IS_FLASH_ADDRESS(addr + len - 1)); - - len_not_erase = len; - - __disable_irq(); - - while (len_not_erase > 0) - { - page_need_save = FALSE; - - start_erase_addr = addr + len - len_not_erase; - end_erase_addr = addr + len - 1; - end_erase_addr = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr)) - ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr); - - if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) - { - if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1))) - page_need_save = TRUE; - } - - if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) - { - if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr))) - page_need_save = TRUE; - } - - if (page_need_save) - { - if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr), - FLASH_PAGE_SIZE >> 2)) - { - __enable_irq(); - return ERROR; - } - } - - if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) - { - __enable_irq(); - return ERROR; - } - - if (page_need_save) - { - para = end_erase_addr & (FLASH_PAGE_SIZE - 1); - index = start_erase_addr & (FLASH_PAGE_SIZE - 1); - - while (index <= para) - write_buf[index++] = 0xFF; - - index = FLASH_PAGE_ADDR(start_erase_addr); - len_index = FLASH_PAGE_SIZE; - - if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) - { - __enable_irq(); - return ERROR; - } - } - - len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1); - } - - __enable_irq(); - return OK; + uint32_t index; + int32_t para; + int32_t start_erase_addr; + int32_t end_erase_addr; + uint16_t len_not_erase; + uint32_t len_index; + type_bool_t page_need_save; + + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + len_not_erase = len; + + __disable_irq(); + while (len_not_erase > 0) { + page_need_save = FALSE; + + start_erase_addr = addr + len - len_not_erase; + end_erase_addr = addr + len - 1; + end_erase_addr = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr)) + ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr); + + if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) { + if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1))) + page_need_save = TRUE; + } + if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) { + if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr))) + page_need_save = TRUE; + } + + if (page_need_save) { + if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr), + FLASH_PAGE_SIZE >> 2)) { + __enable_irq(); + return ERROR; + } + } + + if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) { + __enable_irq(); + return ERROR; + } + + if (page_need_save) { + para = end_erase_addr & (FLASH_PAGE_SIZE - 1); + index = start_erase_addr & (FLASH_PAGE_SIZE - 1); + + while (index <= para) + write_buf[index++] = 0xFF; + + index = FLASH_PAGE_ADDR(start_erase_addr); + len_index = FLASH_PAGE_SIZE; + if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) { + __enable_irq(); + return ERROR; + } + } + len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1); + } + + __enable_irq(); + return OK; } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_gpio.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_gpio.c index 17b4464ac161953b72512091f191abb41915731f..08366e93502bc9ec126ced29cc7ecb4bd57f6e9e 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_gpio.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_gpio.c @@ -168,77 +168,76 @@ */ void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) { - uint32_t i, pos, mask, tmp; - - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); - assert_param(IS_GPIO_MODE(init->mode)); - assert_param(IS_GPIO_ODOS(init->odos)); - assert_param(IS_GPIO_PUPD(init->pupd)); - assert_param(IS_GPIO_ODRV(init->odrv)); - assert_param(IS_GPIO_FLT(init->flt)); - assert_param(IS_GPIO_TYPE(init->type)); - assert_param(IS_GPIO_FUNC(init->func)); - - for (i = 0; i < 16; ++i) - { - if (((pin >> i) & 0x1) == 0) - continue; - - /* Get position and 2-bits mask */ - pos = i << 1; - mask = 0x3 << pos; - - /* Set PIN mode */ - tmp = READ_REG(GPIOx->MODE); - tmp &= ~mask; - tmp |= (init->mode << pos); - WRITE_REG(GPIOx->MODE, tmp); - - /* Set PIN open-drain or push-pull */ - tmp = READ_REG(GPIOx->ODOS); - tmp &= ~mask; - tmp |= (init->odos << pos); - WRITE_REG(GPIOx->ODOS, tmp); - - /* Set PIN push-up or/and push-down */ - tmp = READ_REG(GPIOx->PUPD); - tmp &= ~mask; - tmp |= (init->pupd << pos); - WRITE_REG(GPIOx->PUPD, tmp); - - /* Set PIN output driver */ - tmp = READ_REG(GPIOx->ODRV); - tmp &= ~mask; - tmp |= (init->odrv << pos); - WRITE_REG(GPIOx->ODRV, tmp); - - /* Get position and 1-bit mask */ - pos = i; - mask = 0x1 << pos; - - /* Set PIN filter enable or disable */ - tmp = READ_REG(GPIOx->FLT); - tmp &= ~mask; - tmp |= (init->flt << pos); - WRITE_REG(GPIOx->FLT, tmp); - - /* Set PIN type ttl or smit */ - tmp = READ_REG(GPIOx->TYPE); - tmp &= ~mask; - tmp |= (init->type << pos); - WRITE_REG(GPIOx->TYPE, tmp); - - /* Configure PIN function */ - pos = i < 8 ? (i << 2) : ((i - 8) << 2); - mask = 0xF << pos; - tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); - tmp &= ~mask; - tmp |= (init->func << pos); - i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); - } - - return; + uint32_t i, pos, mask, tmp; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_MODE(init->mode)); + assert_param(IS_GPIO_ODOS(init->odos)); + assert_param(IS_GPIO_PUPD(init->pupd)); + assert_param(IS_GPIO_ODRV(init->odrv)); + assert_param(IS_GPIO_FLT(init->flt)); + assert_param(IS_GPIO_TYPE(init->type)); + assert_param(IS_GPIO_FUNC(init->func)); + + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Set PIN mode */ + tmp = READ_REG(GPIOx->MODE); + tmp &= ~mask; + tmp |= (init->mode << pos); + WRITE_REG(GPIOx->MODE, tmp); + + /* Set PIN open-drain or push-pull */ + tmp = READ_REG(GPIOx->ODOS); + tmp &= ~mask; + tmp |= (init->odos << pos); + WRITE_REG(GPIOx->ODOS, tmp); + + /* Set PIN push-up or/and push-down */ + tmp = READ_REG(GPIOx->PUPD); + tmp &= ~mask; + tmp |= (init->pupd << pos); + WRITE_REG(GPIOx->PUPD, tmp); + + /* Set PIN output driver */ + tmp = READ_REG(GPIOx->ODRV); + tmp &= ~mask; + tmp |= (init->odrv << pos); + WRITE_REG(GPIOx->ODRV, tmp); + + /* Get position and 1-bit mask */ + pos = i; + mask = 0x1 << pos; + + /* Set PIN filter enable or disable */ + tmp = READ_REG(GPIOx->FLT); + tmp &= ~mask; + tmp |= (init->flt << pos); + WRITE_REG(GPIOx->FLT, tmp); + + /* Set PIN type ttl or smit */ + tmp = READ_REG(GPIOx->TYPE); + tmp &= ~mask; + tmp |= (init->type << pos); + WRITE_REG(GPIOx->TYPE, tmp); + + /* Configure PIN function */ + pos = i < 8 ? (i << 2) : ((i - 8) << 2); + mask = 0xF << pos; + tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); + tmp &= ~mask; + tmp |= (init->func << pos); + i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); + } + + return; } /** @@ -249,19 +248,19 @@ void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) */ void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) { - gpio_init_t init; - - /* Fill GPIO_init_t structure with default parameter */ - init.mode = GPIO_MODE_OUTPUT; - init.odos = GPIO_PUSH_PULL; - init.pupd = GPIO_PUSH_UP; - init.odrv = GPIO_OUT_DRIVE_NORMAL; - init.flt = GPIO_FILTER_DISABLE; - init.type = GPIO_TYPE_CMOS; - init.func = GPIO_FUNC_1; - - ald_gpio_init(GPIOx, pin, &init); - return; + gpio_init_t init; + + /* Fill GPIO_init_t structure with default parameter */ + init.mode = GPIO_MODE_OUTPUT; + init.odos = GPIO_PUSH_PULL; + init.pupd = GPIO_PUSH_UP; + init.odrv = GPIO_OUT_DRIVE_NORMAL; + init.flt = GPIO_FILTER_DISABLE; + init.type = GPIO_TYPE_CMOS; + init.func = GPIO_FUNC_1; + + ald_gpio_init(GPIOx, pin, &init); + return; } /** @@ -271,10 +270,10 @@ void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) */ void ald_gpio_func_default(GPIO_TypeDef *GPIOx) { - WRITE_REG(GPIOx->FUNC0, 0x00); - WRITE_REG(GPIOx->FUNC1, 0x00); + WRITE_REG(GPIOx->FUNC0, 0x00); + WRITE_REG(GPIOx->FUNC1, 0x00); - return; + return; } /** @@ -288,67 +287,62 @@ void ald_gpio_func_default(GPIO_TypeDef *GPIOx) */ void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) { - uint8_t i; - uint8_t port; - - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); - assert_param(IS_FUNC_STATE(init->filter)); - assert_param(IS_EXTI_FLTCKS_TYPE(init->cks)); - - /* Get GPIO port */ - if (GPIOx == GPIOA) - port = 0x0; - else if (GPIOx == GPIOB) - port = 0x1; - else if (GPIOx == GPIOC) - port = 2; - else if (GPIOx == GPIOD) - port = 3; - else if (GPIOx == GPIOE) - port = 4; - else if (GPIOx == GPIOF) - port = 5; - else if (GPIOx == GPIOG) - port = 6; - else if (GPIOx == GPIOH) - port = 7; - else - port = 0; - - /* Get Pin index */ - for (i = 0; i < 16; ++i) - { - if (((pin >> i) & 0x1) == 0x1) - break; - } - - /* Select external interrupt line */ - if (i <= 7) - { - EXTI->EXTIPSR0 &= ~(0x7 << (i * 4)); - EXTI->EXTIPSR0 |= (port << (i * 4)); - } - else - { - i -= 8; - EXTI->EXTIPSR1 &= ~(0x7 << (i * 4)); - EXTI->EXTIPSR1 |= (port << (i * 4)); - } - - /* Configure filter parameter */ - if (init->filter == ENABLE) - { - SET_BIT(EXTI->EXTIFLTCR, pin); - MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS); - MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS); - } - else - { - CLEAR_BIT(EXTI->EXTIFLTCR, pin); - } - - return; + uint8_t i; + uint8_t port; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_FUNC_STATE(init->filter)); + assert_param(IS_EXTI_FLTCKS_TYPE(init->cks)); + + /* Get GPIO port */ + if (GPIOx == GPIOA) + port = 0x0; + else if (GPIOx == GPIOB) + port = 0x1; + else if (GPIOx == GPIOC) + port = 2; + else if (GPIOx == GPIOD) + port = 3; + else if (GPIOx == GPIOE) + port = 4; + else if (GPIOx == GPIOF) + port = 5; + else if (GPIOx == GPIOG) + port = 6; + else if (GPIOx == GPIOH) + port = 7; + else + port = 0; + + /* Get Pin index */ + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0x1) + break; + } + + /* Select external interrupt line */ + if (i <= 7) { + EXTI->EXTIPSR0 &= ~(0x7U << (i * 4)); + EXTI->EXTIPSR0 |= (port << (i * 4)); + } + else { + i -= 8; + EXTI->EXTIPSR1 &= ~(0x7U << (i * 4)); + EXTI->EXTIPSR1 |= (port << (i * 4)); + } + + /* Configure filter parameter */ + if (init->filter == ENABLE) { + SET_BIT(EXTI->EXTIFLTCR, pin); + MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS); + MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS); + } + else { + CLEAR_BIT(EXTI->EXTIFLTCR, pin); + } + + return; } /** * @} @@ -373,19 +367,16 @@ void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. * @param pin: Specifies the pin to read. * @retval The input pin value - * - BIT_SET - * - BIT_RESET */ uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) { - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); - if (READ_BIT(GPIOx->DIN, pin)) - return BIT_SET; - - else - return BIT_RESET; + if (READ_BIT(GPIOx->DIN, pin)) + return 1; + else + return 0; } /** @@ -397,15 +388,15 @@ uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) */ void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) { - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); - if ((val & (0x01)) == 0x00) - CLEAR_BIT(GPIOx->DOUT, pin); - else - SET_BIT(GPIOx->DOUT, pin); + if ((val & (0x01)) == 0x00) + CLEAR_BIT(GPIOx->DOUT, pin); + else + SET_BIT(GPIOx->DOUT, pin); - return; + return; } /** @@ -416,11 +407,11 @@ void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) */ void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) { - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); - WRITE_REG(GPIOx->BIR, pin); - return; + WRITE_REG(GPIOx->BIR, pin); + return; } /** @@ -431,42 +422,39 @@ void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) */ void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) { - uint32_t i, pos, mask, tmp, value; - - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); - - for (i = 0; i < 16; ++i) - { - if (((pin >> i) & 0x1) == 0) - continue; - - /* Get position and 2-bits mask */ - pos = i << 1; - mask = 0x3 << pos; - - /* Get the new direction */ - tmp = READ_REG(GPIOx->MODE); - value = (tmp >> pos) & 0x3; - - if ((value == 2) || (value == 3)) - value = 1; - else if (value == 1) - { - value = 2; - } - else - { - continue; /* do nothing */ - } - - /* Set PIN mode */ - tmp &= ~mask; - tmp |= (value << pos); - WRITE_REG(GPIOx->MODE, tmp); - } - - return; + uint32_t i, pos, mask, tmp, value; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Get the new direction */ + tmp = READ_REG(GPIOx->MODE); + value = (tmp >> pos) & 0x3; + + if ((value == 2) || (value == 3)) + value = 1; + else if (value == 1) { + value = 2; + } + else { + continue; /* do nothing */ + } + + /* Set PIN mode */ + tmp &= ~mask; + tmp |= (value << pos); + WRITE_REG(GPIOx->MODE, tmp); + } + + return; } /** @@ -479,13 +467,13 @@ void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) */ void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) { - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); - MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, UNLOCK_KEY << GPIO_LOCK_KEY_POSS); - WRITE_REG(GPIOx->LOCK, pin); + MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, UNLOCK_KEY << GPIO_LOCK_KEY_POSS); + WRITE_REG(GPIOx->LOCK, pin); - return; + return; } /** @@ -495,9 +483,9 @@ void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) */ uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx) { - assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PORT(GPIOx)); - return READ_REG(GPIOx->DIN); + return READ_REG(GPIOx->DIN); } /** @@ -508,10 +496,10 @@ uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx) */ void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) { - assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PORT(GPIOx)); - WRITE_REG(GPIOx->DOUT, val); - return; + WRITE_REG(GPIOx->DOUT, val); + return; } @@ -545,57 +533,47 @@ void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) */ void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status) { - assert_param(IS_GPIO_PIN(pin)); - assert_param(IS_TRIGGER_STYLE(style)); - assert_param(IS_FUNC_STATE(status)); - - if (status == ENABLE) - { - if (style == EXTI_TRIGGER_RISING_EDGE) - { - SET_BIT(EXTI->EXTIRER, pin); - } - else if (style == EXTI_TRIGGER_TRAILING_EDGE) - { - SET_BIT(EXTI->EXTIFER, pin); - } - else if (style == EXTI_TRIGGER_BOTH_EDGE) - { - SET_BIT(EXTI->EXTIRER, pin); - SET_BIT(EXTI->EXTIFER, pin); - } - else - { - ; /* do nothing */ - } - - WRITE_REG(EXTI->EXTICFR, 0xffff); - SET_BIT(EXTI->EXTIEN, pin); - } - else - { - if (style == EXTI_TRIGGER_RISING_EDGE) - { - CLEAR_BIT(EXTI->EXTIRER, pin); - } - else if (style == EXTI_TRIGGER_TRAILING_EDGE) - { - CLEAR_BIT(EXTI->EXTIFER, pin); - } - else if (style == EXTI_TRIGGER_BOTH_EDGE) - { - CLEAR_BIT(EXTI->EXTIRER, pin); - CLEAR_BIT(EXTI->EXTIFER, pin); - } - else - { - ; /* do nothing */ - } - - CLEAR_BIT(EXTI->EXTIEN, pin); - } - - return; + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_TRIGGER_STYLE(style)); + assert_param(IS_FUNC_STATE(status)); + + if (status == ENABLE) { + if (style == EXTI_TRIGGER_RISING_EDGE) { + SET_BIT(EXTI->EXTIRER, pin); + } + else if (style == EXTI_TRIGGER_TRAILING_EDGE) { + SET_BIT(EXTI->EXTIFER, pin); + } + else if (style == EXTI_TRIGGER_BOTH_EDGE) { + SET_BIT(EXTI->EXTIRER, pin); + SET_BIT(EXTI->EXTIFER, pin); + } + else { + ; /* do nothing */ + } + + WRITE_REG(EXTI->EXTICFR, 0xffff); + SET_BIT(EXTI->EXTIEN, pin); + } + else { + if (style == EXTI_TRIGGER_RISING_EDGE) { + CLEAR_BIT(EXTI->EXTIRER, pin); + } + else if (style == EXTI_TRIGGER_TRAILING_EDGE) { + CLEAR_BIT(EXTI->EXTIFER, pin); + } + else if (style == EXTI_TRIGGER_BOTH_EDGE) { + CLEAR_BIT(EXTI->EXTIRER, pin); + CLEAR_BIT(EXTI->EXTIFER, pin); + } + else { + ; /* do nothing */ + } + + CLEAR_BIT(EXTI->EXTIEN, pin); + } + + return; } /** @@ -607,12 +585,12 @@ void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, ty */ flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin) { - assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_PIN(pin)); - if (READ_BIT(EXTI->EXTIFLAG, pin)) - return SET; + if (READ_BIT(EXTI->EXTIFLAG, pin)) + return SET; - return RESET; + return RESET; } /** @@ -622,10 +600,10 @@ flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin) */ void ald_gpio_exti_clear_flag_status(uint16_t pin) { - assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_PIN(pin)); - WRITE_REG(EXTI->EXTICFR, pin); - return; + WRITE_REG(EXTI->EXTICFR, pin); + return; } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_i2c.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_i2c.c index 1e5f32cde1248511f4c36ffcf1eb78c308aaac10..82faa3150285ec98b154dcef97989cf4493cbefa 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_i2c.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_i2c.c @@ -177,13 +177,13 @@ * @{ */ #ifdef ALD_DMA - static void i2c_dma_master_send_cplt(void *argv); - static void i2c_dma_master_recv_cplt(void *argv); - static void i2c_dma_slave_send_cplt(void *argv); - static void i2c_dma_slave_recv_cplt(void *argv); - static void i2c_dma_mem_send_cplt(void *argv); - static void i2c_dma_mem_recv_cplt(void *argv); - static void i2c_dma_error(void *argv); +static void i2c_dma_master_send_cplt(void *argv); +static void i2c_dma_master_recv_cplt(void *argv); +static void i2c_dma_slave_send_cplt(void *argv); +static void i2c_dma_slave_recv_cplt(void *argv); +static void i2c_dma_mem_send_cplt(void *argv); +static void i2c_dma_mem_recv_cplt(void *argv); +static void i2c_dma_error(void *argv); #endif static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); @@ -192,7 +192,7 @@ static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, ui static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout); static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, - flag_status_t status, uint32_t timeout); + flag_status_t status, uint32_t timeout); static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, uint32_t timeout); static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout); static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeout); @@ -256,47 +256,54 @@ static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk); */ ald_status_t ald_i2c_init(i2c_handle_t *hperh) { - uint32_t freqrange = 0; - uint32_t pclk1 = 0; - - if (hperh == NULL) - return ERROR; - - /* Check the parameters */ - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_CLOCK_SPEED(hperh->init.clk_speed)); - assert_param(IS_I2C_DUTY_CYCLE(hperh->init.duty)); - assert_param(IS_I2C_OWN_ADDRESS1(hperh->init.own_addr1)); - assert_param(IS_I2C_ADDRESSING_MODE(hperh->init.addr_mode)); - assert_param(IS_I2C_GENERAL_CALL(hperh->init.general_call)); - assert_param(IS_I2C_NO_STRETCH(hperh->init.no_stretch)); - - if (hperh->init.dual_addr == I2C_DUALADDR_ENABLE) - assert_param(IS_I2C_OWN_ADDRESS2(hperh->init.own_addr2)); - - if (hperh->state == I2C_STATE_RESET) - hperh->lock = UNLOCK; - - hperh->state = I2C_STATE_BUSY; - pclk1 = ald_cmu_get_pclk1_clock(); - I2C_DISABLE(hperh); - - freqrange = I2C_FREQ_RANGE(pclk1); - WRITE_REG(hperh->perh->CON2, freqrange); - WRITE_REG(hperh->perh->RT, I2C_RISE_TIME(freqrange, hperh->init.clk_speed)); - WRITE_REG(hperh->perh->CKCFG, i2c_configure_speed(hperh, pclk1)); - WRITE_REG(hperh->perh->CON1, hperh->init.general_call); - SET_BIT(hperh->perh->CON1, hperh->init.no_stretch); - WRITE_REG(hperh->perh->ADDR1, (hperh->init.addr_mode | hperh->init.own_addr1)); - WRITE_REG(hperh->perh->ADDR2, (hperh->init.dual_addr | hperh->init.own_addr2)); - - I2C_ENABLE(hperh); - - hperh->error_code = I2C_ERROR_NONE; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - return OK; + uint32_t freqrange = 0; + uint32_t pclk1 = 0; + + if (hperh == NULL) + return ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_CLOCK_SPEED(hperh->init.clk_speed)); + assert_param(IS_I2C_DUTY_CYCLE(hperh->init.duty)); + assert_param(IS_I2C_OWN_ADDRESS1(hperh->init.own_addr1)); + assert_param(IS_I2C_ADDRESSING_MODE(hperh->init.addr_mode)); + assert_param(IS_I2C_GENERAL_CALL(hperh->init.general_call)); + assert_param(IS_I2C_NO_STRETCH(hperh->init.no_stretch)); + + if (hperh->init.dual_addr == I2C_DUALADDR_ENABLE) + assert_param(IS_I2C_OWN_ADDRESS2(hperh->init.own_addr2)); + + if (hperh->state == I2C_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = I2C_STATE_BUSY; + pclk1 = ald_cmu_get_pclk1_clock(); + I2C_DISABLE(hperh); + + freqrange = I2C_FREQ_RANGE(pclk1); + WRITE_REG(hperh->perh->CON2, freqrange); + WRITE_REG(hperh->perh->RT, I2C_RISE_TIME(freqrange, hperh->init.clk_speed)); + WRITE_REG(hperh->perh->CKCFG, i2c_configure_speed(hperh, pclk1)); + WRITE_REG(hperh->perh->CON1, hperh->init.general_call); + SET_BIT(hperh->perh->CON1, hperh->init.no_stretch); + + if (hperh->init.addr_mode == I2C_ADDR_7BIT) { + WRITE_REG(hperh->perh->ADDR1, (0x7FFF & hperh->init.own_addr1)); + } + else { + WRITE_REG(hperh->perh->ADDR1, (0x8000 | hperh->init.own_addr1)); + } + + WRITE_REG(hperh->perh->ADDR2, (hperh->init.dual_addr | hperh->init.own_addr2)); + + I2C_ENABLE(hperh); + + hperh->error_code = I2C_ERROR_NONE; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + return OK; } /** @@ -307,21 +314,21 @@ ald_status_t ald_i2c_init(i2c_handle_t *hperh) */ ald_status_t ald_i2c_reset(i2c_handle_t *hperh) { - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_TYPE(hperh->perh)); - hperh->state = I2C_STATE_BUSY; - I2C_DISABLE(hperh); + hperh->state = I2C_STATE_BUSY; + I2C_DISABLE(hperh); - hperh->error_code = I2C_ERROR_NONE; - hperh->state = I2C_STATE_RESET; - hperh->mode = I2C_MODE_NONE; + hperh->error_code = I2C_ERROR_NONE; + hperh->state = I2C_STATE_RESET; + hperh->mode = I2C_MODE_NONE; - __UNLOCK(hperh); + __UNLOCK(hperh); - return OK; + return OK; } /** * @} @@ -399,86 +406,75 @@ ald_status_t ald_i2c_reset(i2c_handle_t *hperh) ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size, uint32_t timeout) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - - if (i2c_master_req_write(hperh, dev_addr, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - I2C_CLEAR_ADDRFLAG(hperh); - - while (size > 0) - { - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - hperh->perh->DATA = (*buf++); - --size; - - if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) - { - hperh->perh->DATA = (*buf++); - --size; - } - } - - if (i2c_wait_btf_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + + if (i2c_master_req_write(hperh, dev_addr, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + I2C_CLEAR_ADDRFLAG(hperh); + + while (size > 0) { + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->perh->DATA = (*buf++); + --size; + + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { + hperh->perh->DATA = (*buf++); + --size; + } + } + + if (i2c_wait_btf_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return OK; } @@ -493,154 +489,136 @@ ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint32_t timeout) + uint16_t size, uint32_t timeout) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - __LOCK(hperh); - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - - if (i2c_master_req_read(hperh, dev_addr, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (size == 1) - { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __enable_irq(); - } - else if (size == 2) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - __disable_irq(); - I2C_CLEAR_ADDRFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __enable_irq(); - } - else - { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - } - - while (size > 3) - { - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_TIMEOUT) - { - __UNLOCK(hperh); - return TIMEOUT; - } - else - { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - --size; - - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) - { - (*buf++) = hperh->perh->DATA; - --size; - } - } - - switch (size) - { - case 1: - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_TIMEOUT) - { - __UNLOCK(hperh); - return TIMEOUT; - } - else - { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - break; - - case 2: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - __disable_irq(); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; - - case 3: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - (*buf++) = hperh->perh->DATA; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - __enable_irq(); - return TIMEOUT; - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; - - default : - break; - } - - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + + if (i2c_master_req_read(hperh, dev_addr, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (size == 1) { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __enable_irq(); + } + else if (size == 2) { + SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + __disable_irq(); + I2C_CLEAR_ADDRFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __enable_irq(); + } + else { + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + } + + while (size > 3) { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_TIMEOUT) { + __UNLOCK(hperh); + return TIMEOUT; + } + else { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + --size; + + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) { + (*buf++) = hperh->perh->DATA; + --size; + } + } + + switch (size) { + case 1: + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_TIMEOUT) { + __UNLOCK(hperh); + return TIMEOUT; + } + else { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + break; + + case 2: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + __disable_irq(); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; + + case 3: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + (*buf++) = hperh->perh->DATA; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { + __UNLOCK(hperh); + __enable_irq(); + return TIMEOUT; + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; + + default : + break; + } + + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + return OK; } /** @@ -654,85 +632,76 @@ ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t */ ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - - if (hperh->init.addr_mode == I2C_ADDR_10BIT) - { - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - } - - while (size > 0) - { - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - hperh->perh->DATA = (*buf++); - --size; - - if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) - { - hperh->perh->DATA = (*buf++); - --size; - } - } - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + + if (hperh->init.addr_mode == I2C_ADDR_10BIT) { + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + } + + while (size > 0) { + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->perh->DATA = (*buf++); + --size; + + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { + hperh->perh->DATA = (*buf++); + --size; + } + } + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + return OK; } /** @@ -746,83 +715,73 @@ ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size */ ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - - while (size > 0) - { - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) - { - hperh->perh->CON1 &= ~I2C_CON1_ACKEN; - - if (hperh->error_code == I2C_ERROR_TIMEOUT) - { - __UNLOCK(hperh); - return TIMEOUT; - } - else - { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - --size; - - if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) - { - (*buf++) = hperh->perh->DATA; - --size; - } - } - - if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) - { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - __I2C_CLEAR_STOPFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + + while (size > 0) { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { + hperh->perh->CON1 &= (uint32_t)(~I2C_CON1_ACKEN); + + if (hperh->error_code == I2C_ERROR_TIMEOUT) { + __UNLOCK(hperh); + return TIMEOUT; + } + else { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + --size; + + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { + (*buf++) = hperh->perh->DATA; + --size; + } + } + + if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + __I2C_CLEAR_STOPFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + return OK; } /** @@ -836,52 +795,49 @@ ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size */ ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - I2C_CLEAR_ADDRFLAG(hperh); - - __UNLOCK(hperh); - - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + I2C_CLEAR_ADDRFLAG(hperh); + + __UNLOCK(hperh); + + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + return OK; } /** @@ -895,68 +851,62 @@ ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, u */ ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (hperh->xfer_count == 1) - { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - } - else if (hperh->xfer_count == 2) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - I2C_CLEAR_ADDRFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - } - else - { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - } - - __UNLOCK(hperh); - - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (hperh->xfer_count == 1) { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + } + else if (hperh->xfer_count == 2) { + SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + I2C_CLEAR_ADDRFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + } + else { + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + } + + __UNLOCK(hperh); + + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + return OK; } /** @@ -969,37 +919,37 @@ ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, u */ ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) { - if (hperh->state != I2C_STATE_READY) - return BUSY; + if (hperh->state != I2C_STATE_READY) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL) || (size == 0)) + return ERROR; - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; - assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_TYPE(hperh->perh)); - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __UNLOCK(hperh); + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __UNLOCK(hperh); - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - return OK; + return OK; } /** @@ -1012,37 +962,37 @@ ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_ */ ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) { - if (hperh->state != I2C_STATE_READY) - return BUSY; + if (hperh->state != I2C_STATE_READY) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL) || (size == 0)) + return ERROR; - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; - assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_TYPE(hperh->perh)); - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __UNLOCK(hperh); + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __UNLOCK(hperh); - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - return OK; + return OK; } #ifdef ALD_DMA @@ -1057,67 +1007,64 @@ ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_ * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint8_t channel) + uint16_t size, uint8_t channel) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = i2c_dma_master_send_cplt; - hperh->hdmatx.cplt_arg = hperh; - hperh->hdmatx.err_cbk = i2c_dma_error; - hperh->hdmatx.err_arg = hperh; - - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmatx); - - if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - I2C_CLEAR_ADDRFLAG(hperh); - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_master_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + I2C_CLEAR_ADDRFLAG(hperh); + __UNLOCK(hperh); + return OK; } /** @@ -1131,72 +1078,69 @@ ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint8_t channel) + uint16_t size, uint8_t channel) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = i2c_dma_master_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = i2c_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmarx); - - if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (size == 1) - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - else - SET_BIT(hperh->perh->CON2, I2C_CON2_LDMA); - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - I2C_CLEAR_ADDRFLAG(hperh); - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_master_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (size == 1) + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + else + SET_BIT(hperh->perh->CON2, I2C_CON2_LDMA); + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + I2C_CLEAR_ADDRFLAG(hperh); + __UNLOCK(hperh); + return OK; } /** @@ -1210,76 +1154,72 @@ ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, */ ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = i2c_dma_slave_send_cplt; - hperh->hdmatx.cplt_arg = hperh; - hperh->hdmatx.err_cbk = i2c_dma_error; - hperh->hdmatx.err_arg = hperh; - - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmatx); - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.addr_mode == I2C_ADDR_7BIT) - { - I2C_CLEAR_ADDRFLAG(hperh); - } - else - { - I2C_CLEAR_ADDRFLAG(hperh); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - } - - __UNLOCK(hperh); - - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_slave_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.addr_mode == I2C_ADDR_7BIT) { + I2C_CLEAR_ADDRFLAG(hperh); + } + else { + I2C_CLEAR_ADDRFLAG(hperh); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + } + + __UNLOCK(hperh); + + return OK; } /** @@ -1293,59 +1233,58 @@ ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16 */ ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = i2c_dma_slave_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = i2c_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmarx); - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_slave_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + __UNLOCK(hperh); + return OK; } #endif @@ -1362,89 +1301,78 @@ ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16 * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout) + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - - if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - while (size > 0) - { - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - hperh->perh->DATA = (*buf++); - --size; - - if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) - { - hperh->perh->DATA = (*buf++); - --size; - } - } - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - ald_delay_ms(10); - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + while (size > 0) { + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->perh->DATA = (*buf++); + --size; + + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { + hperh->perh->DATA = (*buf++); + --size; + } + } + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + ald_delay_ms(10); + __UNLOCK(hperh); + return OK; } /** @@ -1460,155 +1388,137 @@ ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint32_t timeout) + uint8_t *buf, uint16_t size, uint32_t timeout) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - - if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (size == 1) - { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __enable_irq(); - } - else if (size == 2) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - __disable_irq(); - I2C_CLEAR_ADDRFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __enable_irq(); - } - else - { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - } - - while (size > 3) - { - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_TIMEOUT) - { - __UNLOCK(hperh); - return TIMEOUT; - } - else - { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - --size; - - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) - { - (*buf++) = hperh->perh->DATA; - --size; - } - } - - switch (size) - { - case 1: - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_TIMEOUT) - { - __UNLOCK(hperh); - return TIMEOUT; - } - else - { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - break; - - case 2: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - __disable_irq(); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; - - case 3: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - (*buf++) = hperh->perh->DATA; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - __enable_irq(); - return TIMEOUT; - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; - - default: - break; - } - - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + + if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (size == 1) { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __enable_irq(); + } + else if (size == 2) { + SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + __disable_irq(); + I2C_CLEAR_ADDRFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __enable_irq(); + } + else { + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + } + + while (size > 3) { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_TIMEOUT) { + __UNLOCK(hperh); + return TIMEOUT; + } + else { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + --size; + + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) { + (*buf++) = hperh->perh->DATA; + --size; + } + } + + switch (size) { + case 1: + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_TIMEOUT) { + __UNLOCK(hperh); + return TIMEOUT; + } + else { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + break; + + case 2: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + __disable_irq(); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; + + case 3: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + (*buf++) = hperh->perh->DATA; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { + __UNLOCK(hperh); + __enable_irq(); + return TIMEOUT; + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; + + default: + break; + } + + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + return OK; } /** @@ -1623,54 +1533,51 @@ ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t m * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - __UNLOCK(hperh); - - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + __UNLOCK(hperh); + + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + + return OK; } /** @@ -1685,72 +1592,66 @@ ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uin * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (hperh->xfer_count == 1) - { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - } - else if (hperh->xfer_count == 2) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - I2C_CLEAR_ADDRFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - } - else - { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - } - - __UNLOCK(hperh); - - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (hperh->xfer_count == 1) { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + } + else if (hperh->xfer_count == 2) { + SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + I2C_CLEAR_ADDRFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + } + else { + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + } + + __UNLOCK(hperh); + + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + + return OK; } #ifdef ALD_DMA @@ -1767,67 +1668,64 @@ ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel) + uint8_t *buf, uint16_t size, uint8_t channel) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = i2c_dma_mem_send_cplt; - hperh->hdmatx.cplt_arg = hperh; - hperh->hdmatx.err_cbk = i2c_dma_error; - hperh->hdmatx.err_arg = hperh; - ald_dma_config_struct(&hperh->hdmatx.config); - - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmatx); - - if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_mem_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + ald_dma_config_struct(&hperh->hdmatx.config); + + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + __UNLOCK(hperh); + return OK; } /** @@ -1843,73 +1741,70 @@ ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, ui * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel) + uint8_t *buf, uint16_t size, uint8_t channel) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = i2c_dma_mem_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = i2c_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - ald_dma_config_struct(&hperh->hdmarx.config); - - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmarx); - - if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (size == 1) - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - else - SET_BIT(hperh->perh->CON2, I2C_CON2_LDMA); - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - I2C_CLEAR_ADDRFLAG(hperh); - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_mem_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + ald_dma_config_struct(&hperh->hdmarx.config); + + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (size == 1) + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + else + SET_BIT(hperh->perh->CON2, I2C_CON2_LDMA); + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + I2C_CLEAR_ADDRFLAG(hperh); + __UNLOCK(hperh); + return OK; } #endif @@ -1925,88 +1820,79 @@ ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uin */ ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout) { - uint32_t tickstart = 0; - uint32_t tmp1 = 0; - uint32_t tmp2 = 0; - uint32_t tmp3 = 0; - uint32_t I2C_Trials = 1; - - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY; - hperh->error_code = I2C_ERROR_NONE; - - do - { - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); - tickstart = ald_get_tick(); - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); - tmp2 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); - tmp3 = hperh->state; - - while ((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != I2C_STATE_TIMEOUT)) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - hperh->state = I2C_STATE_TIMEOUT; - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); - tmp2 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); - tmp3 = hperh->state; - } - - hperh->state = I2C_STATE_READY; - - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR) == SET) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - I2C_CLEAR_ADDRFLAG(hperh); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, - I2C_TIMEOUT_BUSY_FLAG) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return OK; - } - else - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, - I2C_TIMEOUT_BUSY_FLAG) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - while (I2C_Trials++ < trials); - - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return OK; + uint32_t tickstart = 0; + uint32_t tmp1 = 0; + uint32_t tmp2 = 0; + uint32_t tmp3 = 0; + uint32_t I2C_Trials = 1; + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY; + hperh->error_code = I2C_ERROR_NONE; + + do { + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); + tickstart = ald_get_tick(); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); + tmp2 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); + tmp3 = hperh->state; + + while ((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != I2C_STATE_TIMEOUT)) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) + hperh->state = I2C_STATE_TIMEOUT; + + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); + tmp2 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); + tmp3 = hperh->state; + } + hperh->state = I2C_STATE_READY; + + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR) == SET) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + I2C_CLEAR_ADDRFLAG(hperh); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, + I2C_TIMEOUT_BUSY_FLAG) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return OK; + } + else { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, + I2C_TIMEOUT_BUSY_FLAG) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + } + } while (I2C_Trials++ < trials); + + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return OK; } /** * @} @@ -2040,16 +1926,16 @@ ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uin */ void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state) { - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_IT_TYPE(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - SET_BIT((hperh)->perh->CON2, (it)); - else - CLEAR_BIT((hperh)->perh->CON2, (it)); + if (state == ENABLE) + SET_BIT((hperh)->perh->CON2, (it)); + else + CLEAR_BIT((hperh)->perh->CON2, (it)); - return; + return; } /** @@ -2063,23 +1949,21 @@ void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func */ flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) { - flag_status_t state = RESET; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_FLAG(flag)); - - if ((flag & 0xFF0000) == 0) - { - if ((hperh->perh->STAT1 & flag) == flag) - state = SET; - } - else - { - if ((hperh->perh->STAT2 & (flag >> 16)) == (flag >> 16)) - state = SET; - } - - return state; + flag_status_t state = RESET; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_FLAG(flag)); + + if ((flag & 0xFF0000) == 0) { + if ((hperh->perh->STAT1 & flag) == flag) + state = SET; + } + else { + if ((hperh->perh->STAT2 & (flag >> 16)) == (flag >> 16)) + state = SET; + } + + return state; } /** @@ -2093,13 +1977,13 @@ flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) */ flag_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it) { - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_IT_TYPE(it)); + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT_TYPE(it)); - if ((hperh->perh->CON2 & it) == it) - return SET; - else - return RESET; + if ((hperh->perh->CON2 & it) == it) + return SET; + else + return RESET; } /** @@ -2111,15 +1995,15 @@ flag_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it) */ void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) { - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_FLAG(flag)); + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_FLAG(flag)); - if (flag > 65535) - return; + if (flag > 65535) + return; - hperh->perh->STAT1 = (hperh->perh->STAT1 & (~flag)); + hperh->perh->STAT1 = (hperh->perh->STAT1 & (uint32_t)(~flag)); - return; + return; } @@ -2131,7 +2015,7 @@ void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) */ i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** @@ -2142,7 +2026,7 @@ i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh) */ uint32_t ald_i2c_get_error(i2c_handle_t *hperh) { - return hperh->error_code; + return hperh->error_code; } /** * @} @@ -2160,86 +2044,40 @@ uint32_t ald_i2c_get_error(i2c_handle_t *hperh) */ void ald_i2c_ev_irq_handler(i2c_handle_t *hperh) { - uint32_t tmp1 = 0; - uint32_t tmp2 = 0; - uint32_t tmp3 = 0; - uint32_t tmp4 = 0; - - if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) - { - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_TRA) == SET) - { - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); - - if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) - i2c_master_send_txe(hperh); - else if ((tmp3 == SET) && (tmp4 == SET)) - i2c_master_send_btf(hperh); - } - - /* I2C in mode Receiver */ - else - { - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); - - if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) - i2c_master_recv_rxne(hperh); - else if ((tmp3 == SET) && (tmp4 == SET)) - i2c_master_recv_btf(hperh); - } - } - - /* Slave mode selected */ - else - { - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); - tmp2 = ald_i2c_get_it_status(hperh, (I2C_IT_EVT)); - tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF); - tmp4 = ald_i2c_get_flag_status(hperh, I2C_FLAG_TRA); - - if ((tmp1 == SET) && (tmp2 == SET)) - { - i2c_slave_addr(hperh); - } - else if ((tmp3 == SET) && (tmp2 == SET)) - { - i2c_slave_stopf(hperh); - } - - /* I2C in mode Transmitter */ - else if (tmp4 == SET) - { - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); - - if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) - i2c_slave_send_txe(hperh); - else if ((tmp3 == SET) && (tmp4 == SET)) - i2c_slave_send_btf(hperh); - } - - /* I2C in mode Receiver */ - else - { - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); - - if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) - i2c_slave_recv_rxne(hperh); - else if ((tmp3 == SET) && (tmp4 == SET)) - i2c_slave_recv_btf(hperh); - } - } + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR) == SET) + i2c_slave_addr(hperh); + + if ((ald_i2c_get_it_status(hperh, I2C_IT_BUF) == SET) && (ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE) == SET)) { + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) + i2c_master_send_txe(hperh); + else + i2c_slave_send_txe(hperh); + } + + if ((ald_i2c_get_it_status(hperh, I2C_IT_BUF) == SET) && (ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE) == SET)) { + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) + i2c_master_recv_rxne(hperh); + else + i2c_slave_recv_rxne(hperh); + } + + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) { + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_TRA) == SET) { + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) + i2c_master_send_btf(hperh); + else + i2c_slave_send_btf(hperh); + } + else { + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) + i2c_master_recv_btf(hperh); + else + i2c_slave_recv_btf(hperh); + } + } + + if ((hperh->mode == I2C_MODE_SLAVE) && (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == SET)) + i2c_slave_stopf(hperh); } /** @@ -2250,72 +2088,63 @@ void ald_i2c_ev_irq_handler(i2c_handle_t *hperh) */ void ald_i2c_er_irq_handler(i2c_handle_t *hperh) { - uint32_t tmp1 = 0; - uint32_t tmp2 = 0; - uint32_t tmp3 = 0; - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BERR); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); - - /* I2C Bus error interrupt occurred */ - if ((tmp1 == SET) && (tmp2 == SET)) - { - hperh->error_code |= I2C_ERROR_BERR; - ald_i2c_clear_flag_status(hperh, I2C_FLAG_BERR); - SET_BIT(hperh->perh->CON1, I2C_CON1_SRST); - } - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ARLO); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); - - /* I2C Arbitration Loss error interrupt occurred */ - if ((tmp1 == SET) && (tmp2 == SET)) - { - hperh->error_code |= I2C_ERROR_ARLO; - ald_i2c_clear_flag_status(hperh, I2C_FLAG_ARLO); - } - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); - - /* I2C Acknowledge failure error interrupt occurred */ - if ((tmp1 == SET) && (tmp2 == SET)) - { - tmp1 = hperh->mode; - tmp2 = hperh->xfer_count; - tmp3 = hperh->state; - - if ((tmp1 == I2C_MODE_SLAVE) && (tmp2 == 0) && \ - (tmp3 == I2C_STATE_BUSY_TX)) - { - i2c_slave_af(hperh); - } - else - { - hperh->error_code |= I2C_ERROR_AF; - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - } - } - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_OVR); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); - - /* I2C Over-Run/Under-Run interrupt occurred */ - if ((tmp1 == SET) && (tmp2 == SET)) - { - hperh->error_code |= I2C_ERROR_OVR; - ald_i2c_clear_flag_status(hperh, I2C_FLAG_OVR); - } - - if (hperh->error_code != I2C_ERROR_NONE) - { - hperh->state = I2C_STATE_READY; - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - if (hperh->error_callback) - hperh->error_callback(hperh); - } + uint32_t tmp1 = 0; + uint32_t tmp2 = 0; + uint32_t tmp3 = 0; + + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BERR); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); + + /* I2C Bus error interrupt occurred */ + if ((tmp1 == SET) && (tmp2 == SET)) { + hperh->error_code |= I2C_ERROR_BERR; + ald_i2c_clear_flag_status(hperh, I2C_FLAG_BERR); + SET_BIT(hperh->perh->CON1, I2C_CON1_SRST); + } + + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ARLO); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); + + /* I2C Arbitration Loss error interrupt occurred */ + if ((tmp1 == SET) && (tmp2 == SET)) { + hperh->error_code |= I2C_ERROR_ARLO; + ald_i2c_clear_flag_status(hperh, I2C_FLAG_ARLO); + } + + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); + + /* I2C Acknowledge failure error interrupt occurred */ + if ((tmp1 == SET) && (tmp2 == SET)) { + tmp1 = hperh->mode; + tmp2 = hperh->xfer_count; + tmp3 = hperh->state; + if ((tmp1 == I2C_MODE_SLAVE) && (tmp2 == 0) && \ + (tmp3 == I2C_STATE_BUSY_TX)) { + i2c_slave_af(hperh); + } + else { + hperh->error_code |= I2C_ERROR_AF; + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); + } + } + + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_OVR); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); + + /* I2C Over-Run/Under-Run interrupt occurred */ + if ((tmp1 == SET) && (tmp2 == SET)) { + hperh->error_code |= I2C_ERROR_OVR; + ald_i2c_clear_flag_status(hperh, I2C_FLAG_OVR); + } + + if (hperh->error_code != I2C_ERROR_NONE) { + hperh->state = I2C_STATE_READY; + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + if (hperh->error_callback) + hperh->error_callback(hperh); + } } /** * @} @@ -2337,17 +2166,15 @@ void ald_i2c_er_irq_handler(i2c_handle_t *hperh) */ static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh) { - if (hperh->xfer_count == 0) - { - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - } - else - { - hperh->perh->DATA = (*hperh->p_buff++); - hperh->xfer_count--; - } - - return OK; + if (hperh->xfer_count == 0) { + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + } + else { + hperh->perh->DATA = (*hperh->p_buff++); + hperh->xfer_count--; + } + + return OK; } /** @@ -2358,35 +2185,27 @@ static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh) */ static ald_status_t i2c_master_send_btf(i2c_handle_t *hperh) { - if (hperh->xfer_count != 0) - { - hperh->perh->DATA = (*hperh->p_buff++); - hperh->xfer_count--; - } - else - { - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - - if (hperh->mode == I2C_MODE_MEM) - { - hperh->state = I2C_STATE_READY; - - if (hperh->mem_tx_cplt_cbk) - hperh->mem_tx_cplt_cbk(hperh); - } - else - { - hperh->state = I2C_STATE_READY; - - if (hperh->master_tx_cplt_cbk) - hperh->master_tx_cplt_cbk(hperh); - } - } - - return OK; + if (hperh->xfer_count != 0) { + hperh->perh->DATA = (*hperh->p_buff++); + hperh->xfer_count--; + } + else { + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + if (hperh->mode == I2C_MODE_MEM) { + hperh->state = I2C_STATE_READY; + if (hperh->mem_tx_cplt_cbk) + hperh->mem_tx_cplt_cbk(hperh); + } + else { + hperh->state = I2C_STATE_READY; + if (hperh->master_tx_cplt_cbk) + hperh->master_tx_cplt_cbk(hperh); + } + } + return OK; } /** @@ -2397,44 +2216,35 @@ static ald_status_t i2c_master_send_btf(i2c_handle_t *hperh) */ static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh) { - uint32_t tmp = 0; - - tmp = hperh->xfer_count; - - if (tmp > 3) - { - (*hperh->p_buff++) = hperh->perh->DATA; - hperh->xfer_count--; - } - else if ((tmp == 2) || (tmp == 3)) - { - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - } - else - { - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - (*hperh->p_buff++) = hperh->perh->DATA; - hperh->xfer_count--; - - if (hperh->mode == I2C_MODE_MEM) - { - hperh->state = I2C_STATE_READY; - - if (hperh->mem_rx_cplt_cbk) - hperh->mem_rx_cplt_cbk(hperh); - } - else - { - hperh->state = I2C_STATE_READY; - - if (hperh->master_rx_cplt_cbk) - hperh->master_rx_cplt_cbk(hperh); - } - } - - return OK; + uint32_t tmp = 0; + + tmp = hperh->xfer_count; + if (tmp > 3) { + (*hperh->p_buff++) = hperh->perh->DATA; + hperh->xfer_count--; + } + else if ((tmp == 2) || (tmp == 3)) { + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + } + else { + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + (*hperh->p_buff++) = hperh->perh->DATA; + hperh->xfer_count--; + + if (hperh->mode == I2C_MODE_MEM) { + hperh->state = I2C_STATE_READY; + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } + else { + hperh->state = I2C_STATE_READY; + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } + } + return OK; } /** @@ -2445,45 +2255,37 @@ static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh) */ static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh) { - if (hperh->xfer_count == 3) - { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } - else if (hperh->xfer_count == 2) - { - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - - if (hperh->mode == I2C_MODE_MEM) - { - hperh->state = I2C_STATE_READY; - - if (hperh->mem_rx_cplt_cbk) - hperh->mem_rx_cplt_cbk(hperh); - } - else - { - hperh->state = I2C_STATE_READY; - - if (hperh->master_rx_cplt_cbk) - hperh->master_rx_cplt_cbk(hperh); - } - } - else - { - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } - - return OK; + if (hperh->xfer_count == 3) { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } + else if (hperh->xfer_count == 2) { + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + + if (hperh->mode == I2C_MODE_MEM) { + hperh->state = I2C_STATE_READY; + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } + else { + hperh->state = I2C_STATE_READY; + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } + } + else { + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } + return OK; } /** @@ -2494,13 +2296,11 @@ static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh) { - if (hperh->xfer_count != 0) - { - hperh->perh->DATA = (*hperh->p_buff++); - --hperh->xfer_count; - } - - return OK; + if (hperh->xfer_count != 0) { + hperh->perh->DATA = (*hperh->p_buff++); + --hperh->xfer_count; + } + return OK; } /** @@ -2511,13 +2311,11 @@ static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_send_btf(i2c_handle_t *hperh) { - if (hperh->xfer_count != 0) - { - hperh->perh->DATA = (*hperh->p_buff++); - --hperh->xfer_count; - } - - return OK; + if (hperh->xfer_count != 0) { + hperh->perh->DATA = (*hperh->p_buff++); + --hperh->xfer_count; + } + return OK; } /** @@ -2528,13 +2326,11 @@ static ald_status_t i2c_slave_send_btf(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh) { - if (hperh->xfer_count != 0) - { - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } - - return OK; + if (hperh->xfer_count != 0) { + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } + return OK; } /** @@ -2545,13 +2341,11 @@ static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_recv_btf(i2c_handle_t *hperh) { - if (hperh->xfer_count != 0) - { - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } - - return OK; + if (hperh->xfer_count != 0) { + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } + return OK; } /** @@ -2562,9 +2356,9 @@ static ald_status_t i2c_slave_recv_btf(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_addr(i2c_handle_t *hperh) { - I2C_CLEAR_ADDRFLAG(hperh); + I2C_CLEAR_ADDRFLAG(hperh); - return OK; + return OK; } /** @@ -2575,24 +2369,23 @@ static ald_status_t i2c_slave_addr(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh) { - if (hperh->xfer_count != 0) - { - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } + if (hperh->xfer_count != 0) { + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - __I2C_CLEAR_STOPFLAG(hperh); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + __I2C_CLEAR_STOPFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - hperh->state = I2C_STATE_READY; + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + hperh->state = I2C_STATE_READY; - if (hperh->slave_rx_cplt_cbk) - hperh->slave_rx_cplt_cbk(hperh); + if (hperh->slave_rx_cplt_cbk) + hperh->slave_rx_cplt_cbk(hperh); - return OK; + return OK; } /** @@ -2603,18 +2396,18 @@ static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_af(i2c_handle_t *hperh) { - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - hperh->state = I2C_STATE_READY; + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + hperh->state = I2C_STATE_READY; - if (hperh->slave_tx_cplt_cbk) - hperh->slave_tx_cplt_cbk(hperh); + if (hperh->slave_tx_cplt_cbk) + hperh->slave_tx_cplt_cbk(hperh); - return OK; + return OK; } /** @@ -2627,43 +2420,36 @@ static ald_status_t i2c_slave_af(i2c_handle_t *hperh) */ static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) { - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - if (hperh->init.addr_mode == I2C_ADDR_7BIT) - { - hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); - } - else - { - hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - return ERROR; - } - else - { - return TIMEOUT; - } - } - - hperh->perh->DATA = I2C_10BIT_ADDRESS(dev_addr); - } - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - return OK; + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + if (hperh->init.addr_mode == I2C_ADDR_7BIT) { + hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); + } + else { + hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + return ERROR; + } + else { + return TIMEOUT; + } + } + + hperh->perh->DATA = I2C_10BIT_ADDRESS(dev_addr); + } + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + return OK; } /** @@ -2676,57 +2462,51 @@ static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, */ static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - if (hperh->init.addr_mode == I2C_ADDR_7BIT) - { - hperh->perh->DATA = I2C_7BIT_ADD_READ(dev_addr); - } - else - { - hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - hperh->perh->DATA = I2C_10BIT_ADDRESS(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - hperh->perh->DATA = I2C_10BIT_HEADER_READ(dev_addr); - } - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - return OK; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + if (hperh->init.addr_mode == I2C_ADDR_7BIT) { + hperh->perh->DATA = I2C_7BIT_ADD_READ(dev_addr); + } + else { + hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr); + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + hperh->perh->DATA = I2C_10BIT_ADDRESS(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + hperh->perh->DATA = I2C_10BIT_HEADER_READ(dev_addr); + } + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + return OK; } /** @@ -2741,63 +2521,51 @@ static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, */ static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) { - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - { - return TIMEOUT; - } - - hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else - { - return TIMEOUT; - } - } - - if (add_size == I2C_MEMADD_SIZE_8BIT) - { - hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); - } - else - { - hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr); - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else - { - return TIMEOUT; - } - } - - hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); - } - - return OK; + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) { + return TIMEOUT; + } + + hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else { + return TIMEOUT; + } + } + + if (add_size == I2C_MEMADD_SIZE_8BIT) { + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); + } + else { + hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr); + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else { + return TIMEOUT; + } + } + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); + } + + return OK; } /** @@ -2812,90 +2580,76 @@ static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, ui */ static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else - { - return TIMEOUT; - } - } - - if (add_size == I2C_MEMADD_SIZE_8BIT) - { - hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); - } - else - { - hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr); - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else - { - return TIMEOUT; - } - } - - hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); - } - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else - { - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - hperh->perh->DATA = I2C_7BIT_ADD_READ(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - return OK; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else { + return TIMEOUT; + } + } + + if (add_size == I2C_MEMADD_SIZE_8BIT) { + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); + } + else { + hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else { + return TIMEOUT; + } + } + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); + } + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else { + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + hperh->perh->DATA = I2C_7BIT_ADD_READ(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + return OK; } #ifdef ALD_DMA @@ -2906,28 +2660,26 @@ static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uin */ static void i2c_dma_master_send_cplt(void *argv) { - i2c_handle_t *hperh = (i2c_handle_t *)argv; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != OK) - hperh->error_code |= I2C_ERROR_TIMEOUT; - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) - { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else - { - if (hperh->master_tx_cplt_cbk) - hperh->master_tx_cplt_cbk(hperh); - } + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != OK) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->master_tx_cplt_cbk) + hperh->master_tx_cplt_cbk(hperh); + } } /** @@ -2937,30 +2689,28 @@ static void i2c_dma_master_send_cplt(void *argv) */ static void i2c_dma_slave_send_cplt(void *argv) { - i2c_handle_t *hperh = (i2c_handle_t *)argv; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != OK) - hperh->error_code |= I2C_ERROR_TIMEOUT; - - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) - { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else - { - if (hperh->slave_tx_cplt_cbk) - hperh->slave_tx_cplt_cbk(hperh); - } + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != OK) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->slave_tx_cplt_cbk) + hperh->slave_tx_cplt_cbk(hperh); + } } /** @@ -2970,27 +2720,25 @@ static void i2c_dma_slave_send_cplt(void *argv) */ static void i2c_dma_master_recv_cplt(void *argv) { - i2c_handle_t *hperh = (i2c_handle_t *)argv; - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_LDMA); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) - { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else - { - if (hperh->master_rx_cplt_cbk) - hperh->master_rx_cplt_cbk(hperh); - } + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_LDMA); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } } /** @@ -3000,35 +2748,32 @@ static void i2c_dma_master_recv_cplt(void *argv) */ static void i2c_dma_slave_recv_cplt(void *argv) { - i2c_handle_t *hperh = (i2c_handle_t *)argv; - - if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - hperh->error_code |= I2C_ERROR_AF; - else - hperh->error_code |= I2C_ERROR_TIMEOUT; - } - - __I2C_CLEAR_STOPFLAG(hperh); - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) - { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else - { - if (hperh->slave_rx_cplt_cbk) - hperh->slave_rx_cplt_cbk(hperh); - } + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + hperh->error_code |= I2C_ERROR_AF; + else + hperh->error_code |= I2C_ERROR_TIMEOUT; + } + + __I2C_CLEAR_STOPFLAG(hperh); + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->slave_rx_cplt_cbk) + hperh->slave_rx_cplt_cbk(hperh); + } } /** @@ -3038,28 +2783,26 @@ static void i2c_dma_slave_recv_cplt(void *argv) */ static void i2c_dma_mem_send_cplt(void *argv) { - i2c_handle_t *hperh = (i2c_handle_t *)argv; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != OK) - hperh->error_code |= I2C_ERROR_TIMEOUT; - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) - { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else - { - if (hperh->mem_tx_cplt_cbk) - hperh->mem_tx_cplt_cbk(hperh); - } + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != OK) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->mem_tx_cplt_cbk) + hperh->mem_tx_cplt_cbk(hperh); + } } /** @@ -3069,27 +2812,25 @@ static void i2c_dma_mem_send_cplt(void *argv) */ static void i2c_dma_mem_recv_cplt(void *argv) { - i2c_handle_t *hperh = (i2c_handle_t *)argv; - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_LDMA); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) - { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else - { - if (hperh->mem_rx_cplt_cbk) - hperh->mem_rx_cplt_cbk(hperh); - } + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_LDMA); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } } #endif @@ -3102,31 +2843,32 @@ static void i2c_dma_mem_recv_cplt(void *argv) */ static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk) { - uint32_t tmp1 = 0; - - if (hperh->init.clk_speed <= I2C_STANDARD_MODE_MAX_CLK) - { - tmp1 = (i2c_clk / (hperh->init.clk_speed << 1)); - - if ((tmp1 & I2C_CKCFG_CLKSET) < 4) - return 4; - else - return tmp1; - } - else - { - tmp1 = I2C_CKCFG_CLKMOD; - - if (hperh->init.duty == I2C_DUTYCYCLE_2) - tmp1 |= (i2c_clk / (hperh->init.clk_speed * 3)) | I2C_DUTYCYCLE_2; - else - tmp1 |= (i2c_clk / (hperh->init.clk_speed * 25)) | I2C_DUTYCYCLE_16_9; - - if ((tmp1 & I2C_CKCFG_CLKSET) < 1) - return 1; - else - return tmp1; - } + uint32_t tmp1 = 0; + + if (hperh->init.clk_speed <= I2C_STANDARD_MODE_MAX_CLK) { + tmp1 = (i2c_clk / (hperh->init.clk_speed << 1)); + if ((tmp1 & I2C_CKCFG_CLKSET) < 4 ) + return 4; + else + return tmp1; + } + else { + tmp1 = I2C_CKCFG_CLKMOD; + + if (hperh->init.duty == I2C_DUTYCYCLE_2) { + tmp1 |= (i2c_clk / (hperh->init.clk_speed * 3)) | I2C_DUTYCYCLE_2; + CLEAR_BIT(hperh->perh->CKCFG, I2C_CKCFG_CLKMOD_MSK); + } + else { + tmp1 |= (i2c_clk / (hperh->init.clk_speed * 25)) | I2C_DUTYCYCLE_16_9; + SET_BIT(hperh->perh->CKCFG, I2C_CKCFG_CLKMOD_MSK); + } + + if ((tmp1 & I2C_CKCFG_CLKSET) < 1 ) + return 1; + else + return tmp1; + } } #ifdef ALD_DMA @@ -3137,17 +2879,17 @@ static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk) */ static void i2c_dma_error(void *argv) { - i2c_handle_t *hperh = (i2c_handle_t *)argv; + i2c_handle_t* hperh = (i2c_handle_t*)argv; - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - hperh->error_code |= I2C_ERROR_DMA; + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + hperh->error_code |= I2C_ERROR_DMA; - if (hperh->error_callback) - hperh->error_callback(hperh); + if (hperh->error_callback) + hperh->error_callback(hperh); } #endif @@ -3162,36 +2904,29 @@ static void i2c_dma_error(void *argv) */ static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, flag_status_t status, uint32_t timeout) { - uint32_t tickstart = 0; - - tickstart = ald_get_tick(); - - if (status == RESET) - { - while (ald_i2c_get_flag_status(hperh, flag) == RESET) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - else - { - while (ald_i2c_get_flag_status(hperh, flag) != RESET) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - - return OK; + uint32_t tickstart = 0; + + tickstart = ald_get_tick(); + + if (status == RESET) { + while (ald_i2c_get_flag_status(hperh, flag) == RESET) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + else { + while (ald_i2c_get_flag_status(hperh, flag) != RESET) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + return OK; } /** @@ -3204,35 +2939,29 @@ static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t fla */ static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, uint32_t timeout) { - uint32_t tickstart = 0; - - tickstart = ald_get_tick(); - - while (ald_i2c_get_flag_status(hperh, flag) == RESET) - { - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - - hperh->error_code = I2C_ERROR_AF; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return ERROR; - } - - if (timeout != I2C_MAX_DELAY) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - - return OK; + uint32_t tickstart = 0; + + tickstart = ald_get_tick(); + while (ald_i2c_get_flag_status(hperh, flag) == RESET) { + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); + + hperh->error_code = I2C_ERROR_AF; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return ERROR; + } + + if (timeout != I2C_MAX_DELAY) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + return OK; } /** @@ -3244,26 +2973,22 @@ static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_fla */ static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = ald_get_tick(); - - while (ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE) == RESET) - { - if (i2c_is_ack_failed(hperh) != OK) - return ERROR; - - if (timeout != I2C_MAX_DELAY) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->error_code |= I2C_ERROR_TIMEOUT; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - - return OK; + uint32_t tickstart = ald_get_tick(); + + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE) == RESET) { + if (i2c_is_ack_failed(hperh) != OK) + return ERROR; + + if (timeout != I2C_MAX_DELAY) { + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + return OK; } /** @@ -3275,28 +3000,23 @@ static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeou */ static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = ald_get_tick(); - - while (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == RESET) - { - if (i2c_is_ack_failed(hperh) != OK) - { - return ERROR; - } - - if (timeout != I2C_MAX_DELAY) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->error_code |= I2C_ERROR_TIMEOUT; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - - return OK; + uint32_t tickstart = ald_get_tick(); + + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == RESET) { + if (i2c_is_ack_failed(hperh) != OK) { + return ERROR; + } + + if (timeout != I2C_MAX_DELAY) { + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + return OK; } /** @@ -3308,24 +3028,21 @@ static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeou */ static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = 0x00; - tickstart = ald_get_tick(); - - while (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == RESET) - { - if (i2c_is_ack_failed(hperh) != OK) - return ERROR; - - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->error_code |= I2C_ERROR_TIMEOUT; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - - return OK; + uint32_t tickstart = 0x00; + tickstart = ald_get_tick(); + + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == RESET) { + if (i2c_is_ack_failed(hperh) != OK) + return ERROR; + + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + return OK; } /** @@ -3337,30 +3054,26 @@ static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeo */ static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = 0x00; - tickstart = ald_get_tick(); - - while (ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE) == RESET) - { - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == SET) - { - ald_i2c_clear_flag_status(hperh, I2C_FLAG_STOPF); - hperh->error_code = I2C_ERROR_NONE; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return ERROR; - } - - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->error_code |= I2C_ERROR_TIMEOUT; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - - return OK; + uint32_t tickstart = 0x00; + tickstart = ald_get_tick(); + + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE) == RESET) { + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_FLAG_STOPF); + hperh->error_code = I2C_ERROR_NONE; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return ERROR; + } + + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + return OK; } /** @@ -3371,17 +3084,16 @@ static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeo */ static ald_status_t i2c_is_ack_failed(i2c_handle_t *hperh) { - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) - { - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - hperh->error_code = I2C_ERROR_AF; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); + hperh->error_code = I2C_ERROR_AF; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); - return ERROR; - } + return ERROR; + } - return OK; + return OK; } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_iap.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_iap.c index 81b933d6c78acd5a98fc6d6f5a7369c7540c3250..ccb9b5170b58270c550ad1fd5dfef208251db7b5 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_iap.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_iap.c @@ -51,14 +51,14 @@ */ uint32_t ald_iap_erase_page(uint32_t addr) { - uint32_t status; - IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR); + uint32_t status; + IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR); - __disable_irq(); - status = (*iap_pe)(addr); - __enable_irq(); + __disable_irq(); + status = (*iap_pe)(addr); + __enable_irq(); - return !status; + return !status; } /** @@ -72,17 +72,17 @@ uint32_t ald_iap_erase_page(uint32_t addr) */ uint32_t ald_iap_program_word(uint32_t addr, uint32_t data) { - uint32_t status; - IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR); + uint32_t status; + IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR); - if (addr & 0x3) - return 1; + if (addr & 0x3) + return 1; - __disable_irq(); - status = (*iap_wp)(addr, data); - __enable_irq(); + __disable_irq(); + status = (*iap_wp)(addr, data); + __enable_irq(); - return !status; + return !status; } /** @@ -97,17 +97,17 @@ uint32_t ald_iap_program_word(uint32_t addr, uint32_t data) */ uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h) { - uint32_t status; - IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR); + uint32_t status; + IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR); - if (addr & 0x3) - return 1; + if (addr & 0x3) + return 1; - __disable_irq(); - status = (*iap_dwp)(addr, data_l, data_h); - __enable_irq(); + __disable_irq(); + status = (*iap_dwp)(addr, data_l, data_h); + __enable_irq(); - return !status; + return !status; } /** @@ -124,17 +124,17 @@ uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h) */ uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase) { - uint32_t status; - IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR); + uint32_t status; + IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR); - if ((addr & 0x3) || (len & 0x3)) - return 1; + if ((addr & 0x3) || (len & 0x3)) + return 1; - __disable_irq(); - status = (*iap_wsp)(addr, data, len, erase); - __enable_irq(); + __disable_irq(); + status = (*iap_wsp)(addr, data, len, erase); + __enable_irq(); - return !status; + return !status; } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lcd.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lcd.c index 127ae1412a426361a692094d9666d99cb2a0a459..b4d955a98be34a0f4dbbb5a483f50aa06a8d0199 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lcd.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lcd.c @@ -1,18 +1,18 @@ -/** - ********************************************************************************* - * - * @file ald_lcd.c - * @brief LCD module driver. - * - * @version V1.0 - * @date 29 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ + /** + ********************************************************************************* + * + * @file ald_lcd.c + * @brief LCD module driver. + * + * @version V1.0 + * @date 29 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ #include "ald_lcd.h" @@ -44,53 +44,51 @@ */ ald_status_t ald_lcd_init(lcd_handle_t *hperh) { - uint16_t delay = 0; - - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_VCHPS_TYPE(hperh->init.lcd_vchps)); - assert_param(IS_LCD_VSEL_TYPE(hperh->init.lcd_vsel)); - assert_param(IS_LCD_FUNC_TYPE(hperh->init.lcd_vbufld)); - assert_param(IS_LCD_FUNC_TYPE(hperh->init.lcd_vbufhd)); - assert_param(IS_LCD_LEVEL_TYPE(hperh->init.lcd_dsld)); - assert_param(IS_LCD_LEVEL_TYPE(hperh->init.lcd_dshd)); - assert_param(IS_LCD_RES_TYPE(hperh->init.lcd_resld)); - assert_param(IS_LCD_RES_TYPE(hperh->init.lcd_reshd)); - assert_param(IS_LCD_BIAS_TYPE(hperh->init.lcd_bias)); - assert_param(IS_LCD_DUTY_TYPE(hperh->init.lcd_duty)); - assert_param(IS_LCD_WFS_TYPE(hperh->init.lcd_wfs)); - assert_param(IS_LCD_PRS_TYPE(hperh->init.lcd_prs)); - assert_param(IS_LCD_DIV_TYPE(hperh->init.lcd_div)); - assert_param(IS_LCD_DEAD_TYPE(hperh->init.lcd_dead)); - assert_param(IS_LCD_PON_TYPE(hperh->init.lcd_pon)); - assert_param(IS_LCD_VGS_TYPE(hperh->init.lcd_vgs)); - - __LOCK(hperh); - - ald_cmu_lcd_clock_select(hperh->init.clock); - - MODIFY_REG(hperh->perh->FCR, LCD_FCR_WFS_MSK, hperh->init.lcd_wfs << LCD_FCR_WFS_POS); - MODIFY_REG(hperh->perh->FCR, LCD_FCR_PRS_MSK, hperh->init.lcd_prs << LCD_FCR_PRS_POSS); - - for (delay = 0; delay < 3000; delay++); - - MODIFY_REG(hperh->perh->FCR, LCD_FCR_DIV_MSK, hperh->init.lcd_div << LCD_FCR_DIV_POSS); - MODIFY_REG(hperh->perh->FCR, LCD_FCR_DEAD_MSK, hperh->init.lcd_dead << LCD_FCR_DEAD_POSS); - MODIFY_REG(hperh->perh->FCR, LCD_FCR_PON_MSK, hperh->init.lcd_pon << LCD_FCR_PON_POSS); - MODIFY_REG(hperh->perh->FCR, LCD_FCR_VGS_MSK, hperh->init.lcd_vgs << LCD_FCR_VGS_POSS); - - MODIFY_REG(hperh->perh->CR, LCD_CR_DUTY_MSK, hperh->init.lcd_duty << LCD_CR_DUTY_POSS); - MODIFY_REG(hperh->perh->CR, LCD_CR_BIAS_MSK, hperh->init.lcd_bias << LCD_CR_BIAS_POSS); - MODIFY_REG(hperh->perh->CR, LCD_CR_VBUFHD_MSK, hperh->init.lcd_vbufhd << LCD_CR_VBUFHD_POS); - MODIFY_REG(hperh->perh->CR, LCD_CR_VBUFLD_MSK, hperh->init.lcd_vbufld << LCD_CR_VBUFLD_POS); - MODIFY_REG(hperh->perh->CR, LCD_CR_DSHD_MSK, hperh->init.lcd_dshd << LCD_CR_DSHD_POSS); - MODIFY_REG(hperh->perh->CR, LCD_CR_DSLD_MSK, hperh->init.lcd_dsld << LCD_CR_DSLD_POSS); - MODIFY_REG(hperh->perh->CR, LCD_CR_RESHD_MSK, hperh->init.lcd_reshd << LCD_CR_RESHD_POSS); - MODIFY_REG(hperh->perh->CR, LCD_CR_RESLD_MSK, hperh->init.lcd_resld << LCD_CR_RESLD_POSS); - MODIFY_REG(hperh->perh->CR, LCD_CR_VSEL_MSK, hperh->init.lcd_vsel << LCD_CR_VSEL_POSS); - MODIFY_REG(hperh->perh->CR, LCD_CR_VCHPS_MSK, hperh->init.lcd_vchps << LCD_CR_VCHPS_POSS); - - __UNLOCK(hperh); - return OK; + uint16_t delay = 0; + + assert_param(IS_LCD_PERH_TYPE(hperh->perh)); + assert_param(IS_LCD_VCHPS_TYPE(hperh->init.lcd_vchps)); + assert_param(IS_LCD_VSEL_TYPE(hperh->init.lcd_vsel)); + assert_param(IS_LCD_FUNC_TYPE(hperh->init.lcd_vbufld)); + assert_param(IS_LCD_FUNC_TYPE(hperh->init.lcd_vbufhd)); + assert_param(IS_LCD_LEVEL_TYPE(hperh->init.lcd_dsld)); + assert_param(IS_LCD_LEVEL_TYPE(hperh->init.lcd_dshd)); + assert_param(IS_LCD_RES_TYPE(hperh->init.lcd_resld)); + assert_param(IS_LCD_RES_TYPE(hperh->init.lcd_reshd)); + assert_param(IS_LCD_BIAS_TYPE(hperh->init.lcd_bias)); + assert_param(IS_LCD_DUTY_TYPE(hperh->init.lcd_duty)); + assert_param(IS_LCD_WFS_TYPE(hperh->init.lcd_wfs)); + assert_param(IS_LCD_PRS_TYPE(hperh->init.lcd_prs)); + assert_param(IS_LCD_DIV_TYPE(hperh->init.lcd_div)); + assert_param(IS_LCD_DEAD_TYPE(hperh->init.lcd_dead)); + assert_param(IS_LCD_PON_TYPE(hperh->init.lcd_pon)); + assert_param(IS_LCD_VGS_TYPE(hperh->init.lcd_vgs)); + + __LOCK(hperh); + + ald_cmu_lcd_clock_select(hperh->init.clock); + + MODIFY_REG(hperh->perh->FCR, LCD_FCR_WFS_MSK, hperh->init.lcd_wfs << LCD_FCR_WFS_POS); + MODIFY_REG(hperh->perh->FCR, LCD_FCR_PRS_MSK, hperh->init.lcd_prs << LCD_FCR_PRS_POSS); + for (delay = 0; delay < 3000; delay++); + MODIFY_REG(hperh->perh->FCR, LCD_FCR_DIV_MSK, hperh->init.lcd_div << LCD_FCR_DIV_POSS); + MODIFY_REG(hperh->perh->FCR, LCD_FCR_DEAD_MSK, hperh->init.lcd_dead << LCD_FCR_DEAD_POSS); + MODIFY_REG(hperh->perh->FCR, LCD_FCR_PON_MSK, hperh->init.lcd_pon << LCD_FCR_PON_POSS); + MODIFY_REG(hperh->perh->FCR, LCD_FCR_VGS_MSK, hperh->init.lcd_vgs << LCD_FCR_VGS_POSS); + + MODIFY_REG(hperh->perh->CR, LCD_CR_DUTY_MSK, hperh->init.lcd_duty << LCD_CR_DUTY_POSS); + MODIFY_REG(hperh->perh->CR, LCD_CR_BIAS_MSK, hperh->init.lcd_bias << LCD_CR_BIAS_POSS); + MODIFY_REG(hperh->perh->CR, LCD_CR_VBUFHD_MSK, hperh->init.lcd_vbufhd << LCD_CR_VBUFHD_POS); + MODIFY_REG(hperh->perh->CR, LCD_CR_VBUFLD_MSK, hperh->init.lcd_vbufld << LCD_CR_VBUFLD_POS); + MODIFY_REG(hperh->perh->CR, LCD_CR_DSHD_MSK, hperh->init.lcd_dshd << LCD_CR_DSHD_POSS); + MODIFY_REG(hperh->perh->CR, LCD_CR_DSLD_MSK, hperh->init.lcd_dsld << LCD_CR_DSLD_POSS); + MODIFY_REG(hperh->perh->CR, LCD_CR_RESHD_MSK, hperh->init.lcd_reshd << LCD_CR_RESHD_POSS); + MODIFY_REG(hperh->perh->CR, LCD_CR_RESLD_MSK, hperh->init.lcd_resld << LCD_CR_RESLD_POSS); + MODIFY_REG(hperh->perh->CR, LCD_CR_VSEL_MSK, hperh->init.lcd_vsel << LCD_CR_VSEL_POSS); + MODIFY_REG(hperh->perh->CR, LCD_CR_VCHPS_MSK, hperh->init.lcd_vchps << LCD_CR_VCHPS_POSS); + + __UNLOCK(hperh); + return OK; } /** @@ -102,16 +100,16 @@ ald_status_t ald_lcd_init(lcd_handle_t *hperh) */ ald_status_t ald_lcd_cmd(lcd_handle_t *hperh, type_func_t state) { - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_LCD_PERH_TYPE(hperh->perh)); + assert_param(IS_FUNC_STATE(state)); - __LOCK(hperh); + __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, LCD_CR_OE_MSK, state << LCD_CR_OE_POS); - MODIFY_REG(hperh->perh->CR, LCD_CR_EN_MSK, state << LCD_CR_EN_POS); + MODIFY_REG(hperh->perh->CR, LCD_CR_OE_MSK, state << LCD_CR_OE_POS); + MODIFY_REG(hperh->perh->CR, LCD_CR_EN_MSK, state << LCD_CR_EN_POS); - __UNLOCK(hperh); - return OK; + __UNLOCK(hperh); + return OK; } /** * @} @@ -132,21 +130,19 @@ ald_status_t ald_lcd_cmd(lcd_handle_t *hperh, type_func_t state) */ ald_status_t ald_lcd_blink_config(lcd_handle_t *hperh, lcd_blink_t blink_mode, lcd_blfrq_t blink_freq) { - uint16_t delay = 0; - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_BLINK_MODE(blink_mode)); - assert_param(IS_LCD_BLFRQ_TYPE(blink_freq)); - __LOCK(hperh); - - MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLMOD_MSK, blink_mode << LCD_FCR_BLMOD_POSS); + uint16_t delay = 0; + assert_param(IS_LCD_PERH_TYPE(hperh->perh)); + assert_param(IS_LCD_BLINK_MODE(blink_mode)); + assert_param(IS_LCD_BLFRQ_TYPE(blink_freq)); + __LOCK(hperh); - for (delay = 0; delay < 3000; delay++); + MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLMOD_MSK, blink_mode << LCD_FCR_BLMOD_POSS); + for (delay = 0; delay < 3000; delay++); + MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLFRQ_MSK, blink_freq << LCD_FCR_BLFRQ_POSS); - MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLFRQ_MSK, blink_freq << LCD_FCR_BLFRQ_POSS); - - __UNLOCK(hperh); - return OK; -} + __UNLOCK(hperh); + return OK; + } /** * @brief Control segment port enable or disable @@ -158,17 +154,17 @@ ald_status_t ald_lcd_blink_config(lcd_handle_t *hperh, lcd_blink_t blink_mode, l */ ald_status_t ald_lcd_write_seg(lcd_handle_t *hperh, lcd_seg_t seg, uint32_t seg_data) { - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_SEG_TYPE(seg)); - __LOCK(hperh); + assert_param(IS_LCD_PERH_TYPE(hperh->perh)); + assert_param(IS_LCD_SEG_TYPE(seg)); + __LOCK(hperh); - if (seg == SEG_0_TO_31) - WRITE_REG(hperh->perh->SEGCR0, seg_data); - else - WRITE_REG(hperh->perh->SEGCR1, seg_data); + if (seg == SEG_0_TO_31) + WRITE_REG(hperh->perh->SEGCR0, seg_data); + else + WRITE_REG(hperh->perh->SEGCR1, seg_data); - __UNLOCK(hperh); - return OK; + __UNLOCK(hperh); + return OK; } /** @@ -181,14 +177,14 @@ ald_status_t ald_lcd_write_seg(lcd_handle_t *hperh, lcd_seg_t seg, uint32_t seg_ */ ald_status_t ald_lcd_write(lcd_handle_t *hperh, uint8_t buf, uint32_t buf_data) { - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_BUFFER_TYPE(buf)); + assert_param(IS_LCD_PERH_TYPE(hperh->perh)); + assert_param(IS_LCD_BUFFER_TYPE(buf)); - __LOCK(hperh); - WRITE_REG(hperh->perh->BUF[buf], buf_data); - __UNLOCK(hperh); + __LOCK(hperh); + WRITE_REG(hperh->perh->BUF[buf], buf_data); + __UNLOCK(hperh); - return OK; + return OK; } /** * @} @@ -208,13 +204,13 @@ ald_status_t ald_lcd_write(lcd_handle_t *hperh, uint8_t buf, uint32_t buf_data) */ uint32_t ald_lcd_get_status(lcd_handle_t *hperh, lcd_status_t lcd_status) { - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_STATUS_TYPE(lcd_status)); + assert_param(IS_LCD_PERH_TYPE(hperh->perh)); + assert_param(IS_LCD_STATUS_TYPE(lcd_status)); - if (lcd_status == LCD_STATUS_ALL) - return hperh->perh->SR; - else - return hperh->perh->SR & lcd_status ? 1 : 0; + if (lcd_status == LCD_STATUS_ALL) + return hperh->perh->SR; + else + return hperh->perh->SR & lcd_status ? 1 : 0; } /** * @} @@ -238,18 +234,18 @@ uint32_t ald_lcd_get_status(lcd_handle_t *hperh, lcd_status_t lcd_status) */ ald_status_t ald_lcd_interrupt_config(lcd_handle_t *hperh, lcd_it_t it, type_func_t state) { - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_IT_TYPE(it)); - assert_param(IS_FUNC_STATE(state)); - __LOCK(hperh); - - if (state) - SET_BIT(hperh->perh->IE, it); - else - CLEAR_BIT(hperh->perh->IE, it); - - __UNLOCK(hperh); - return OK; + assert_param(IS_LCD_PERH_TYPE(hperh->perh)); + assert_param(IS_LCD_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); + __LOCK(hperh); + + if (state) + SET_BIT(hperh->perh->IE, it); + else + CLEAR_BIT(hperh->perh->IE, it); + + __UNLOCK(hperh); + return OK; } /** @@ -264,10 +260,10 @@ ald_status_t ald_lcd_interrupt_config(lcd_handle_t *hperh, lcd_it_t it, type_fun */ flag_status_t ald_lcd_get_it_status(lcd_handle_t *hperh, lcd_it_t it) { - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_IT_TYPE(it)); + assert_param(IS_LCD_PERH_TYPE(hperh->perh)); + assert_param(IS_LCD_IT_TYPE(it)); - return hperh->perh->IE & it ? SET : RESET; + return hperh->perh->IE & it ? SET : RESET; } /** @@ -282,10 +278,10 @@ flag_status_t ald_lcd_get_it_status(lcd_handle_t *hperh, lcd_it_t it) */ it_status_t ald_lcd_get_flag_status(lcd_handle_t *hperh, lcd_flag_t flag) { - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_FLAG_TYPE(flag)); + assert_param(IS_LCD_PERH_TYPE(hperh->perh)); + assert_param(IS_LCD_FLAG_TYPE(flag)); - return hperh->perh->IF & flag ? SET : RESET; + return hperh->perh->IF & flag ? SET : RESET; } /** @@ -300,14 +296,14 @@ it_status_t ald_lcd_get_flag_status(lcd_handle_t *hperh, lcd_flag_t flag) */ ald_status_t ald_lcd_clear_flag_status(lcd_handle_t *hperh, lcd_flag_t flag) { - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_FLAG_TYPE(flag)); + assert_param(IS_LCD_PERH_TYPE(hperh->perh)); + assert_param(IS_LCD_FLAG_TYPE(flag)); - __LOCK(hperh); - WRITE_REG(hperh->perh->IFCR, flag); - __UNLOCK(hperh); + __LOCK(hperh); + WRITE_REG(hperh->perh->IFCR, flag); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -318,23 +314,21 @@ ald_status_t ald_lcd_clear_flag_status(lcd_handle_t *hperh, lcd_flag_t flag) */ void ald_lcd_irq_handler(lcd_handle_t *hperh) { - if (ald_lcd_get_flag_status(hperh, LCD_FLAG_UDD)) - { - ald_lcd_clear_flag_status(hperh, LCD_FLAG_UDD); + if (ald_lcd_get_flag_status(hperh, LCD_FLAG_UDD)) { + ald_lcd_clear_flag_status(hperh, LCD_FLAG_UDD); - if (hperh->display_cplt_cbk) - hperh->display_cplt_cbk(hperh); - } + if (hperh->display_cplt_cbk) + hperh->display_cplt_cbk(hperh); + } - if (ald_lcd_get_flag_status(hperh, LCD_FLAG_SOF)) - { - ald_lcd_clear_flag_status(hperh, LCD_FLAG_SOF); + if (ald_lcd_get_flag_status(hperh, LCD_FLAG_SOF)) { + ald_lcd_clear_flag_status(hperh, LCD_FLAG_SOF); - if (hperh->frame_start_cbk) - hperh->frame_start_cbk(hperh); - } + if (hperh->frame_start_cbk) + hperh->frame_start_cbk(hperh); + } - return; + return; } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lptim.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lptim.c index 71a94ab21880ed6e42762f5742aae9d392685754..5b615f0b7780dcfe6f08ea21ea962b195305b5be 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lptim.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lptim.c @@ -44,14 +44,14 @@ */ void ald_lptim_reset(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM(hperh->perh)); - hperh->state = LPTIM_STATE_BUSY; - LPTIM_DISABLE(hperh); - hperh->state = LPTIM_STATE_RESET; - __UNLOCK(hperh); + hperh->state = LPTIM_STATE_BUSY; + LPTIM_DISABLE(hperh); + hperh->state = LPTIM_STATE_RESET; + __UNLOCK(hperh); - return; + return; } /** @@ -63,14 +63,14 @@ void ald_lptim_reset(lptim_handle_t *hperh) */ void ald_lptim_trigger_config(lptim_handle_t *hperh, lptim_trigger_init_t *config) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_TRIGEN(config->mode)); - assert_param(IS_LPTIM_TRIGSEL(config->sel)); + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_TRIGEN(config->mode)); + assert_param(IS_LPTIM_TRIGSEL(config->sel)); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRIGEN_MSK, (config->mode) << LP16T_CON0_TRIGEN_POSS); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRIGSEL_MSK, (config->sel) << LP16T_CON0_TRIGSEL_POSS); + MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRIGEN_MSK, (config->mode) << LP16T_CON0_TRIGEN_POSS); + MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRIGSEL_MSK, (config->sel) << LP16T_CON0_TRIGSEL_POSS); - return; + return; } /** @@ -82,14 +82,14 @@ void ald_lptim_trigger_config(lptim_handle_t *hperh, lptim_trigger_init_t *confi */ void ald_lptim_clock_source_config(lptim_handle_t *hperh, lptim_clock_source_init_t *config) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_CKSEL(config->sel)); - assert_param(IS_LPTIM_CKPOL(config->polarity)); + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_CKSEL(config->sel)); + assert_param(IS_LPTIM_CKPOL(config->polarity)); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKSEL_MSK, (config->sel) << LP16T_CON0_CKSEL_POS); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKPOL_MSK, (config->polarity) << LP16T_CON0_CKPOL_POS); + MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKSEL_MSK, (config->sel) << LP16T_CON0_CKSEL_POS); + MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKPOL_MSK, (config->polarity) << LP16T_CON0_CKPOL_POS); - return; + return; } /** @@ -101,12 +101,12 @@ void ald_lptim_clock_source_config(lptim_handle_t *hperh, lptim_clock_source_ini */ void ald_lptim_trigger_filter_config(lptim_handle_t *hperh, lptim_trgflt_t flt) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_TRGFLT(flt)); + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_TRGFLT(flt)); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRGFLT_MSK, flt << LP16T_CON0_TRGFLT_POSS); + MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRGFLT_MSK, flt << LP16T_CON0_TRGFLT_POSS); - return; + return; } /** @@ -118,19 +118,145 @@ void ald_lptim_trigger_filter_config(lptim_handle_t *hperh, lptim_trgflt_t flt) */ void ald_lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_TRGFLT(flt)); + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_CKFLT(flt)); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKFLT_MSK, flt << LP16T_CON0_CKFLT_POSS); + MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKFLT_MSK, flt << LP16T_CON0_CKFLT_POSS); - return; + return; } /** * @} */ -/** @defgroup LPTIM_Public_Functions_Group2 LPTIM output toggle functions - * @brief LPTime output toggle functions +/** @defgroup LPTIM_Public_Functions_Group2 LPTIM base functions + * @brief LPTIM base functions + * + * @verbatim + ============================================================================== + ##### Low Pow Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize the LPTIM . + (+) Start the LPTIM. + (+) Stop the LPTIM. + (+) Start the LPTIM and enable interrupt. + (+) Stop the LPTIM and disable interrupt. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIM according to the specified + * parameters in the tim_handle_t. + * @param hperh: LPTIM handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_lptim_base_init(lptim_handle_t *hperh) +{ + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_PRESC(hperh->init.psc)); + + __LOCK(hperh); + hperh->state = LPTIM_STATE_BUSY; + + ald_cmu_lptim0_clock_select(hperh->init.clock); + + WRITE_REG(hperh->perh->UPDATE, 1); + MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_NONE << LP16T_CON0_WAVE_POSS); + MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS); + WRITE_REG(hperh->perh->ARR, hperh->init.arr); + WRITE_REG(hperh->perh->CMP, hperh->init.cmp); + WRITE_REG(hperh->perh->UPDATE, 0); + + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK)); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK)); + + hperh->state = LPTIM_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Starts the LPTIM. + * @param hperh: LPTIM handle + * @retval None + */ +void ald_lptim_base_start(lptim_handle_t *hperh) +{ + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_MODE(hperh->init.mode)); + + LPTIM_ENABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + + if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) + LPTIM_CNTSTART(hperh); + else + LPTIM_SNGSTART(hperh); + + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + return; +} + +/** + * @brief Stops the LPTIM. + * @param hperh: LPTIM handle + * @retval None + */ +void ald_lptim_base_stop(lptim_handle_t *hperh) +{ + assert_param(IS_LPTIM(hperh->perh)); + + LPTIM_DISABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + return; +} + +/** + * @brief Starts the LPTIM in interrupt mode. + * @param hperh: LPTIM handle + * @retval None + */ +void ald_lptim_base_start_by_it(lptim_handle_t *hperh) +{ + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_MODE(hperh->init.mode)); + + ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE); + LPTIM_ENABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + + if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) + LPTIM_CNTSTART(hperh); + else + LPTIM_SNGSTART(hperh); + + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + return; +} + +/** + * @brief Stops the LPTIM Output toggle in interrupt mode. + * @param hperh: LPTIM handle + * @retval None + */ +void ald_lptim_base_stop_by_it(lptim_handle_t *hperh) +{ + assert_param(IS_LPTIM(hperh->perh)); + + ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE); + LPTIM_DISABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + return; +} +/** + * @} + */ + +/** @defgroup LPTIM_Public_Functions_Group3 LPTIM output toggle functions + * @brief LPTIM output toggle functions * * @verbatim ============================================================================== @@ -155,28 +281,27 @@ void ald_lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt) */ ald_status_t ald_lptim_toggle_init(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_PRESC(hperh->init.psc)); + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_PRESC(hperh->init.psc)); - __LOCK(hperh); - hperh->state = LPTIM_STATE_BUSY; + __LOCK(hperh); + hperh->state = LPTIM_STATE_BUSY; - ald_cmu_lptim0_clock_select(hperh->init.clock); + ald_cmu_lptim0_clock_select(hperh->init.clock); - WRITE_REG(hperh->perh->UPDATE, 1); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_TOGGLE << LP16T_CON0_WAVE_POSS); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS); - WRITE_REG(hperh->perh->ARR, hperh->init.arr); - WRITE_REG(hperh->perh->CMP, hperh->init.cmp); - WRITE_REG(hperh->perh->UPDATE, 0); + WRITE_REG(hperh->perh->UPDATE, 1); + MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_TOGGLE << LP16T_CON0_WAVE_POSS); + MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS); + WRITE_REG(hperh->perh->ARR, hperh->init.arr); + WRITE_REG(hperh->perh->CMP, hperh->init.cmp); + WRITE_REG(hperh->perh->UPDATE, 0); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK)); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK)); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK)); - - hperh->state = LPTIM_STATE_READY; - __UNLOCK(hperh); - return OK; + hperh->state = LPTIM_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -186,21 +311,19 @@ ald_status_t ald_lptim_toggle_init(lptim_handle_t *hperh) */ void ald_lptim_toggle_start(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_MODE(hperh->init.mode)); - - LPTIM_ENABLE(hperh); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_MODE(hperh->init.mode)); - if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) - LPTIM_CNTSTART(hperh); - else - LPTIM_SNGSTART(hperh); + LPTIM_ENABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) + LPTIM_CNTSTART(hperh); + else + LPTIM_SNGSTART(hperh); - return; + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + return; } /** @@ -210,13 +333,11 @@ void ald_lptim_toggle_start(lptim_handle_t *hperh) */ void ald_lptim_toggle_stop(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM(hperh->perh)); - LPTIM_DISABLE(hperh); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - return; + LPTIM_DISABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + return; } /** @@ -226,22 +347,20 @@ void ald_lptim_toggle_stop(lptim_handle_t *hperh) */ void ald_lptim_toggle_start_by_it(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_MODE(hperh->init.mode)); - - ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE); - LPTIM_ENABLE(hperh); + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_MODE(hperh->init.mode)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE); + LPTIM_ENABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) - LPTIM_CNTSTART(hperh); - else - LPTIM_SNGSTART(hperh); + if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) + LPTIM_CNTSTART(hperh); + else + LPTIM_SNGSTART(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - return; + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + return; } /** @@ -251,21 +370,19 @@ void ald_lptim_toggle_start_by_it(lptim_handle_t *hperh) */ void ald_lptim_toggle_stop_by_it(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - - ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE); - LPTIM_DISABLE(hperh); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + assert_param(IS_LPTIM(hperh->perh)); - return; + ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE); + LPTIM_DISABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + return; } /** * @} */ -/** @defgroup LPTIM_Public_Functions_Group3 LPTIM output pulse functions - * @brief LPTime output pulse functions +/** @defgroup LPTIM_Public_Functions_Group4 LPTIM output pulse functions + * @brief LPTIM output pulse functions * * @verbatim ============================================================================== @@ -290,27 +407,26 @@ void ald_lptim_toggle_stop_by_it(lptim_handle_t *hperh) */ ald_status_t ald_lptim_pulse_init(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_PRESC(hperh->init.psc)); - - __LOCK(hperh); - hperh->state = LPTIM_STATE_BUSY; - ald_cmu_lptim0_clock_select(hperh->init.clock); - - WRITE_REG(hperh->perh->UPDATE, 1); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_PULSE << LP16T_CON0_WAVE_POSS); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS); - WRITE_REG(hperh->perh->ARR, hperh->init.arr); - WRITE_REG(hperh->perh->CMP, hperh->init.cmp); - WRITE_REG(hperh->perh->UPDATE, 0); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK)); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK)); - - hperh->state = LPTIM_STATE_READY; - __UNLOCK(hperh); - return OK; + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_PRESC(hperh->init.psc)); + + __LOCK(hperh); + hperh->state = LPTIM_STATE_BUSY; + ald_cmu_lptim0_clock_select(hperh->init.clock); + + WRITE_REG(hperh->perh->UPDATE, 1); + MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_PULSE << LP16T_CON0_WAVE_POSS); + MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS); + WRITE_REG(hperh->perh->ARR, hperh->init.arr); + WRITE_REG(hperh->perh->CMP, hperh->init.cmp); + WRITE_REG(hperh->perh->UPDATE, 0); + + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK)); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK)); + + hperh->state = LPTIM_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -320,21 +436,19 @@ ald_status_t ald_lptim_pulse_init(lptim_handle_t *hperh) */ void ald_lptim_pulse_start(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_MODE(hperh->init.mode)); - - LPTIM_ENABLE(hperh); + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_MODE(hperh->init.mode)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + LPTIM_ENABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) - LPTIM_CNTSTART(hperh); - else - LPTIM_SNGSTART(hperh); + if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) + LPTIM_CNTSTART(hperh); + else + LPTIM_SNGSTART(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - return; + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + return; } /** @@ -344,13 +458,12 @@ void ald_lptim_pulse_start(lptim_handle_t *hperh) */ void ald_lptim_pulse_stop(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - - LPTIM_DISABLE(hperh); + assert_param(IS_LPTIM(hperh->perh)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + LPTIM_DISABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; + return; } /** @@ -360,22 +473,20 @@ void ald_lptim_pulse_stop(lptim_handle_t *hperh) */ void ald_lptim_pulse_start_by_it(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_MODE(hperh->init.mode)); - - ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE); - LPTIM_ENABLE(hperh); + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_MODE(hperh->init.mode)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE); + LPTIM_ENABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) - LPTIM_CNTSTART(hperh); - else - LPTIM_SNGSTART(hperh); + if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) + LPTIM_CNTSTART(hperh); + else + LPTIM_SNGSTART(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - return; + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + return; } /** @@ -385,21 +496,20 @@ void ald_lptim_pulse_start_by_it(lptim_handle_t *hperh) */ void ald_lptim_pulse_stop_by_it(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - - ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE); - LPTIM_DISABLE(hperh); + assert_param(IS_LPTIM(hperh->perh)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE); + LPTIM_DISABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; + return; } /** * @} */ -/** @defgroup LPTIM_Public_Functions_Group4 LPTIM output pwm functions - * @brief LPTime output pwm functions +/** @defgroup LPTIM_Public_Functions_Group5 LPTIM output pwm functions + * @brief LPTIM output pwm functions * * @verbatim ============================================================================== @@ -424,26 +534,25 @@ void ald_lptim_pulse_stop_by_it(lptim_handle_t *hperh) */ ald_status_t ald_lptim_pwm_init(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_PRESC(hperh->init.psc)); - - __LOCK(hperh); - hperh->state = LPTIM_STATE_BUSY; + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_PRESC(hperh->init.psc)); - WRITE_REG(hperh->perh->UPDATE, 1); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_PWM << LP16T_CON0_WAVE_POSS); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS); - WRITE_REG(hperh->perh->ARR, hperh->init.arr); - WRITE_REG(hperh->perh->CMP, hperh->init.cmp); - WRITE_REG(hperh->perh->UPDATE, 0); + __LOCK(hperh); + hperh->state = LPTIM_STATE_BUSY; - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK)); + WRITE_REG(hperh->perh->UPDATE, 1); + MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_PWM << LP16T_CON0_WAVE_POSS); + MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS); + WRITE_REG(hperh->perh->ARR, hperh->init.arr); + WRITE_REG(hperh->perh->CMP, hperh->init.cmp); + WRITE_REG(hperh->perh->UPDATE, 0); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK)); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK)); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK)); - hperh->state = LPTIM_STATE_READY; - __UNLOCK(hperh); - return OK; + hperh->state = LPTIM_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -453,21 +562,19 @@ ald_status_t ald_lptim_pwm_init(lptim_handle_t *hperh) */ void ald_lptim_pwm_start(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_MODE(hperh->init.mode)); + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_MODE(hperh->init.mode)); - LPTIM_ENABLE(hperh); + LPTIM_ENABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) + LPTIM_CNTSTART(hperh); + else + LPTIM_SNGSTART(hperh); - if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) - LPTIM_CNTSTART(hperh); - else - LPTIM_SNGSTART(hperh); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - return; + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + return; } /** @@ -477,13 +584,12 @@ void ald_lptim_pwm_start(lptim_handle_t *hperh) */ void ald_lptim_pwm_stop(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - - LPTIM_DISABLE(hperh); + assert_param(IS_LPTIM(hperh->perh)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + LPTIM_DISABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; + return; } /** @@ -493,22 +599,20 @@ void ald_lptim_pwm_stop(lptim_handle_t *hperh) */ void ald_lptim_pwm_start_by_it(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_MODE(hperh->init.mode)); + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_MODE(hperh->init.mode)); - ald_lptim_interrupt_config(hperh, LPTIM_IT_CMPMAT, ENABLE); - LPTIM_ENABLE(hperh); + ald_lptim_interrupt_config(hperh, LPTIM_IT_CMPMAT, ENABLE); + LPTIM_ENABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) + LPTIM_CNTSTART(hperh); + else + LPTIM_SNGSTART(hperh); - if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) - LPTIM_CNTSTART(hperh); - else - LPTIM_SNGSTART(hperh); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - return; + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + return; } /** @@ -518,21 +622,20 @@ void ald_lptim_pwm_start_by_it(lptim_handle_t *hperh) */ void ald_lptim_pwm_stop_by_it(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - - ald_lptim_interrupt_config(hperh, LPTIM_IT_CMPMAT, DISABLE); - LPTIM_DISABLE(hperh); + assert_param(IS_LPTIM(hperh->perh)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); + ald_lptim_interrupt_config(hperh, LPTIM_IT_CMPMAT, DISABLE); + LPTIM_DISABLE(hperh); + while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; + return; } /** * @} */ -/** @defgroup LPTIM_Public_Functions_Group5 Control functions +/** @defgroup LPTIM_Public_Functions_Group6 Control functions * @brief LPTIM Control functions * * @{ @@ -544,39 +647,36 @@ void ald_lptim_pwm_stop_by_it(lptim_handle_t *hperh) */ void ald_lptim_irq_handler(lptim_handle_t *hperh) { - assert_param(IS_LPTIM(hperh->perh)); - - /* Output compare event */ - if (((ald_lptim_get_it_status(hperh, LPTIM_IT_CMPMAT)) != RESET) && - ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_CMPMAT)) != RESET)) - { - ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_CMPMAT); - - if (hperh->cmp_cbk) - hperh->cmp_cbk(hperh); - } - - /* Output update event */ - if (((ald_lptim_get_it_status(hperh, LPTIM_IT_ARRMAT)) != RESET) && - ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_ARRMAT)) != RESET)) - { - ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_ARRMAT); - - if (hperh->update_cbk) - hperh->update_cbk(hperh); - } - - /* Trigger event */ - if (((ald_lptim_get_it_status(hperh, LPTIM_IT_EXTTRIG)) != RESET) && - ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_EXTTRIG)) != RESET)) - { - ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_EXTTRIG); - - if (hperh->trig_cbk) - hperh->trig_cbk(hperh); - } - - return; + assert_param(IS_LPTIM(hperh->perh)); + + /* Output compare event */ + if (((ald_lptim_get_it_status(hperh, LPTIM_IT_CMPMAT)) != RESET) && + ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_CMPMAT)) != RESET)) { + ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_CMPMAT); + + if (hperh->cmp_cbk) + hperh->cmp_cbk(hperh); + } + + /* Output update event */ + if (((ald_lptim_get_it_status(hperh, LPTIM_IT_ARRMAT)) != RESET) && + ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_ARRMAT)) != RESET)) { + ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_ARRMAT); + + if (hperh->update_cbk) + hperh->update_cbk(hperh); + } + + /* Trigger event */ + if (((ald_lptim_get_it_status(hperh, LPTIM_IT_EXTTRIG)) != RESET) && + ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_EXTTRIG)) != RESET)) { + ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_EXTTRIG); + + if (hperh->trig_cbk) + hperh->trig_cbk(hperh); + } + + return; } /** @@ -592,16 +692,15 @@ void ald_lptim_irq_handler(lptim_handle_t *hperh) */ void ald_lptim_interrupt_config(lptim_handle_t *hperh, lptim_it_t it, type_func_t state) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_IT(it)); - assert_param(IS_FUNC_STATE(state)); - - if (state == ENABLE) - SET_BIT(hperh->perh->IER, (uint32_t)it); - else - CLEAR_BIT(hperh->perh->IER, (uint32_t)it); - - return; + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->IER, (uint32_t)it); + else + CLEAR_BIT(hperh->perh->IER, (uint32_t)it); + return; } /** @@ -616,13 +715,13 @@ void ald_lptim_interrupt_config(lptim_handle_t *hperh, lptim_it_t it, type_func_ */ it_status_t ald_lptim_get_it_status(lptim_handle_t *hperh, lptim_it_t it) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_IT(it)); + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_IT(it)); - if (READ_BIT(hperh->perh->IER, it)) - return SET; + if (READ_BIT(hperh->perh->IER, it)) + return SET; - return RESET; + return RESET; } /** @brief Check whether the specified LPTIM flag is set or not. @@ -636,13 +735,13 @@ it_status_t ald_lptim_get_it_status(lptim_handle_t *hperh, lptim_it_t it) */ flag_status_t ald_lptim_get_flag_status(lptim_handle_t *hperh, lptim_flag_t flag) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_FLAG(flag)); + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_FLAG(flag)); - if (READ_BIT(hperh->perh->ISR, flag)) - return SET; + if (READ_BIT(hperh->perh->ISR, flag)) + return SET; - return RESET; + return RESET; } /** @brief Clear the specified LPTIM pending flags. @@ -654,18 +753,18 @@ flag_status_t ald_lptim_get_flag_status(lptim_handle_t *hperh, lptim_flag_t flag */ void ald_lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag) { - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_FLAG(flag)); + assert_param(IS_LPTIM(hperh->perh)); + assert_param(IS_LPTIM_FLAG(flag)); - WRITE_REG(hperh->perh->IFC, (uint32_t)flag); - return; + WRITE_REG(hperh->perh->IFC, (uint32_t)flag); + return; } /** * @} */ -/** @defgroup LPTIM_Public_Functions_Group6 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup LPTIM_Public_Functions_Group7 Peripheral State functions + * @brief Peripheral State functions * * @verbatim ============================================================================== @@ -685,7 +784,7 @@ void ald_lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag) */ lptim_state_t ald_lptim_get_state(lptim_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lpuart.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lpuart.c index bebc600f6473674c604904b64e193238943f5b47..8a296925c1500f773130c581977517041ad6cb25 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lpuart.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lpuart.c @@ -118,11 +118,11 @@ */ static void lpuart_dma_send_cplt(void *arg) { - lpuart_handle_t *hperh = (lpuart_handle_t *)arg; + lpuart_handle_t *hperh = (lpuart_handle_t *)arg; - hperh->tx_count = 0; - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE); - ald_lpuart_interrupt_config(hperh, LPUART_IT_TC, ENABLE); + hperh->tx_count = 0; + ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE); + ald_lpuart_interrupt_config(hperh, LPUART_IT_TC, ENABLE); } /** @@ -133,14 +133,14 @@ static void lpuart_dma_send_cplt(void *arg) */ static void lpuart_dma_recv_cplt(void *arg) { - lpuart_handle_t *hperh = (lpuart_handle_t *)arg; + lpuart_handle_t *hperh = (lpuart_handle_t *)arg; - hperh->rx_count = 0; - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE); - CLEAR_BIT(hperh->state, LPUART_STATE_RX_MASK); + hperh->rx_count = 0; + ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE); + CLEAR_BIT(hperh->state, LPUART_STATE_RX_MASK); - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); } /** @@ -151,15 +151,15 @@ static void lpuart_dma_recv_cplt(void *arg) */ static void lpuart_dma_error(void *arg) { - lpuart_handle_t *hperh = (lpuart_handle_t *)arg; + lpuart_handle_t *hperh = (lpuart_handle_t *)arg; - hperh->rx_count = 0; - hperh->tx_count = 0; - hperh->state = LPUART_STATE_READY; - hperh->err_code |= LPUART_ERROR_DMA; + hperh->rx_count = 0; + hperh->tx_count = 0; + hperh->state = LPUART_STATE_READY; + hperh->err_code |= LPUART_ERROR_DMA; - if (hperh->error_cbk) - hperh->error_cbk(hperh); + if (hperh->error_cbk) + hperh->error_cbk(hperh); } #endif @@ -174,21 +174,20 @@ static void lpuart_dma_error(void *arg) */ static ald_status_t lpuart_wait_flag(lpuart_handle_t *hperh, lpuart_status_t flag, flag_status_t status, uint32_t timeout) { - uint32_t tick; + uint32_t tick; - if (timeout == 0) - return OK; + if (timeout == 0) + return OK; - tick = ald_get_tick(); + tick = ald_get_tick(); - /* Waiting for flag */ - while ((ald_lpuart_get_status(hperh, flag)) != status) - { - if (((ald_get_tick()) - tick) > timeout) - return TIMEOUT; - } + /* Waiting for flag */ + while ((ald_lpuart_get_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } - return OK; + return OK; } /** @@ -199,18 +198,17 @@ static ald_status_t lpuart_wait_flag(lpuart_handle_t *hperh, lpuart_status_t fla */ static ald_status_t __lpuart_send_by_it(lpuart_handle_t *hperh) { - if ((hperh->state & LPUART_STATE_TX_MASK) == 0x0) - return BUSY; + if ((hperh->state & LPUART_STATE_TX_MASK) == 0x0) + return BUSY; - WRITE_REG(hperh->perh->TXDR, *hperh->tx_buf++); + WRITE_REG(hperh->perh->TXDR, *hperh->tx_buf++); - if (--hperh->tx_count == 0) - { - ald_lpuart_interrupt_config(hperh, LPUART_IT_TBEMP, DISABLE); - ald_lpuart_interrupt_config(hperh, LPUART_IT_TC, ENABLE); - } + if (--hperh->tx_count == 0) { + ald_lpuart_interrupt_config(hperh, LPUART_IT_TBEMP, DISABLE); + ald_lpuart_interrupt_config(hperh, LPUART_IT_TC, ENABLE); + } - return OK; + return OK; } @@ -222,13 +220,13 @@ static ald_status_t __lpuart_send_by_it(lpuart_handle_t *hperh) */ static ald_status_t __lpuart_end_send_by_it(lpuart_handle_t *hperh) { - ald_lpuart_interrupt_config(hperh, LPUART_IT_TC, DISABLE); - CLEAR_BIT(hperh->state, LPUART_STATE_TX_MASK); + ald_lpuart_interrupt_config(hperh, LPUART_IT_TC, DISABLE); + CLEAR_BIT(hperh->state, LPUART_STATE_TX_MASK); - if (hperh->tx_cplt_cbk) - hperh->tx_cplt_cbk(hperh); + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); - return OK; + return OK; } /** @@ -239,39 +237,35 @@ static ald_status_t __lpuart_end_send_by_it(lpuart_handle_t *hperh) */ static ald_status_t __lpuart_recv_by_it(lpuart_handle_t *hperh) { - uint8_t tmp; - uint16_t i; - - if ((hperh->state & LPUART_STATE_RX_MASK) == 0x0) - return BUSY; - - do - { - i = 10000; - tmp = hperh->perh->STAT & LPUART_STAT_RXPTR_MSK; - *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXDR & 0xFF); - --hperh->rx_count; - - while (((hperh->perh->STAT & LPUART_STAT_RXPTR_MSK) != tmp - 1) && (i--)); - } - while (hperh->perh->STAT & LPUART_STAT_RXPTR_MSK); - - if (hperh->rx_count == 0) - { - ald_lpuart_interrupt_config(hperh, LPUART_IT_RBR, DISABLE); - CLEAR_BIT(hperh->state, LPUART_STATE_RX_MASK); - - if (hperh->state == LPUART_STATE_READY) - { - ald_lpuart_interrupt_config(hperh, LPUART_IT_PERR, DISABLE); - ald_lpuart_interrupt_config(hperh, LPUART_IT_FERR, DISABLE); - } - - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - } - - return OK; + uint32_t tmp; + uint16_t i; + + if ((hperh->state & LPUART_STATE_RX_MASK) == 0x0) + return BUSY; + + do { + i = 10000; + tmp = hperh->perh->STAT & LPUART_STAT_RXPTR_MSK; + *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXDR & 0xFF); + --hperh->rx_count; + + while (((hperh->perh->STAT & LPUART_STAT_RXPTR_MSK) != (uint32_t)(tmp - 1)) && (i--)); + } while (hperh->perh->STAT & LPUART_STAT_RXPTR_MSK); + + if (hperh->rx_count == 0) { + ald_lpuart_interrupt_config(hperh, LPUART_IT_RBR, DISABLE); + CLEAR_BIT(hperh->state, LPUART_STATE_RX_MASK); + + if (hperh->state == LPUART_STATE_READY) { + ald_lpuart_interrupt_config(hperh, LPUART_IT_PERR, DISABLE); + ald_lpuart_interrupt_config(hperh, LPUART_IT_FERR, DISABLE); + } + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return OK; } /** * @} @@ -317,16 +311,16 @@ static ald_status_t __lpuart_recv_by_it(lpuart_handle_t *hperh) */ void ald_lpuart_reset(lpuart_handle_t *hperh) { - WRITE_REG(hperh->perh->CON0, 0x3000); - WRITE_REG(hperh->perh->CON1, 0x4); - WRITE_REG(hperh->perh->CLKDIV, 0x0); - WRITE_REG(hperh->perh->FIFOCON, 0x0); - WRITE_REG(hperh->perh->IER, 0x0); - hperh->err_code = LPUART_ERROR_NONE; - hperh->state = LPUART_STATE_RESET; - - __UNLOCK(hperh); - return; + WRITE_REG(hperh->perh->CON0, 0x3000); + WRITE_REG(hperh->perh->CON1, 0x4); + WRITE_REG(hperh->perh->CLKDIV, 0x0); + WRITE_REG(hperh->perh->FIFOCON, 0x0); + WRITE_REG(hperh->perh->IER, 0x0); + hperh->err_code = LPUART_ERROR_NONE; + hperh->state = LPUART_STATE_RESET; + + __UNLOCK(hperh); + return; } /** @@ -338,54 +332,54 @@ void ald_lpuart_reset(lpuart_handle_t *hperh) */ void ald_lpuart_init(lpuart_handle_t *hperh) { - uint32_t tmp; - - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_BAUDRATE(hperh->init.baud)); - assert_param(IS_LPUART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_LPUART_STOPBITS(hperh->init.stop_bits)); - assert_param(IS_LPUART_PARITY(hperh->init.parity)); - assert_param(IS_LPUART_MODE(hperh->init.mode)); - assert_param(IS_LPUART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); - - if ((hperh->init.clock != CMU_LP_PERH_CLOCK_SEL_LOSC) - && (hperh->init.clock != CMU_LP_PERH_CLOCK_SEL_LRC)) - hperh->init.clock = CMU_LP_PERH_CLOCK_SEL_LRC; - - ald_cmu_lpuart0_clock_select(hperh->init.clock); - ald_lpuart_reset(hperh); - LPUART_UPDATE_DISABLE(hperh); - - tmp = READ_REG(hperh->perh->CON0); - MODIFY_REG(tmp, LPUART_CON0_DATLENTH_MSK, hperh->init.word_length << LPUART_CON0_DATLENTH_POSS); - MODIFY_REG(tmp, LPUART_CON0_STPLENTH_MSK, hperh->init.stop_bits << LPUART_CON0_STPLENTH_POS); - - if (hperh->init.parity == LPUART_PARITY_NONE) - CLEAR_BIT(tmp, LPUART_CON0_PARCHKE_MSK); - else - SET_BIT(tmp, LPUART_CON0_PARCHKE_MSK); - - if (hperh->init.parity == LPUART_PARITY_EVEN) - SET_BIT(tmp, LPUART_CON0_EVENPARSEL_MSK); - else - CLEAR_BIT(tmp, LPUART_CON0_EVENPARSEL_MSK); - - MODIFY_REG(tmp, LPUART_CON0_ATRTSE_MSK, (hperh->init.fctl & 1) << LPUART_CON0_ATRTSE_POS); - MODIFY_REG(tmp, LPUART_CON0_ATCTSE_MSK, ((hperh->init.fctl >> 1) & 1) << LPUART_CON0_ATCTSE_POS); - WRITE_REG(hperh->perh->CON0, tmp); - WRITE_REG(hperh->perh->CLKDIV, (32768 << 8) / hperh->init.baud); - - if (hperh->init.mode == LPUART_MODE_IrDA) - CLEAR_BIT(hperh->perh->CON1, LPUART_CON1_IRRXINV_MSK); - - MODIFY_REG(hperh->perh->CON0, LPUART_CON0_MODESEL_MSK, hperh->init.mode << LPUART_CON0_MODESEL_POSS); - LPUART_UPDATE_ENABLE(hperh); - - while (hperh->perh->SYNCSTAT & 0xF) - ; - - hperh->state = LPUART_STATE_READY; - return; + uint32_t tmp; + + assert_param(IS_LPUART(hperh->perh)); + assert_param(IS_LPUART_BAUDRATE(hperh->init.baud)); + assert_param(IS_LPUART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_LPUART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_LPUART_PARITY(hperh->init.parity)); + assert_param(IS_LPUART_MODE(hperh->init.mode)); + assert_param(IS_LPUART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); + + if ((hperh->init.clock != CMU_LP_PERH_CLOCK_SEL_LOSC) + && (hperh->init.clock != CMU_LP_PERH_CLOCK_SEL_LRC)) + hperh->init.clock = CMU_LP_PERH_CLOCK_SEL_LRC; + + ald_cmu_lpuart0_clock_select(hperh->init.clock); + ald_lpuart_reset(hperh); + LPUART_UPDATE_DISABLE(hperh); + + tmp = READ_REG(hperh->perh->CON0); + MODIFY_REG(tmp, LPUART_CON0_DATLENTH_MSK, hperh->init.word_length << LPUART_CON0_DATLENTH_POSS); + MODIFY_REG(tmp, LPUART_CON0_STPLENTH_MSK, hperh->init.stop_bits << LPUART_CON0_STPLENTH_POS); + + if (hperh->init.parity == LPUART_PARITY_NONE) + CLEAR_BIT(tmp, LPUART_CON0_PARCHKE_MSK); + else + SET_BIT(tmp, LPUART_CON0_PARCHKE_MSK); + + if (hperh->init.parity == LPUART_PARITY_EVEN) + SET_BIT(tmp, LPUART_CON0_EVENPARSEL_MSK); + else + CLEAR_BIT(tmp, LPUART_CON0_EVENPARSEL_MSK); + + MODIFY_REG(tmp, LPUART_CON0_ATRTSE_MSK, (hperh->init.fctl & 1) << LPUART_CON0_ATRTSE_POS); + MODIFY_REG(tmp, LPUART_CON0_ATCTSE_MSK, ((hperh->init.fctl >> 1) & 1) << LPUART_CON0_ATCTSE_POS); + WRITE_REG(hperh->perh->CON0, tmp); + WRITE_REG(hperh->perh->CLKDIV, (32768 << 8) / hperh->init.baud); + + if (hperh->init.mode == LPUART_MODE_IrDA) + CLEAR_BIT(hperh->perh->CON1, LPUART_CON1_IRRXINV_MSK); + + MODIFY_REG(hperh->perh->CON0, LPUART_CON0_MODESEL_MSK, hperh->init.mode << LPUART_CON0_MODESEL_POSS); + LPUART_UPDATE_ENABLE(hperh); + + while (hperh->perh->SYNCSTAT & 0xF) + ; + + hperh->state = LPUART_STATE_READY; + return; } /** @@ -398,23 +392,23 @@ void ald_lpuart_init(lpuart_handle_t *hperh) */ void ald_lpuart_rs485_config(lpuart_handle_t *hperh, lpuart_rs485_config_t *config) { - uint32_t tmp; - - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_FUNC_STATE(config->RS485_NMM)); - assert_param(IS_FUNC_STATE(config->RS485_AAD)); - assert_param(IS_FUNC_STATE(config->RS485_AUD)); - assert_param(IS_FUNC_STATE(config->RS485_ADD_DET)); - - tmp = READ_REG(hperh->perh->CON1); - MODIFY_REG(tmp, LPUART_CON1_NMPMOD_MSK, config->RS485_NMM << LPUART_CON1_NMPMOD_POS); - MODIFY_REG(tmp, LPUART_CON1_ATADETE_MSK, config->RS485_AAD << LPUART_CON1_ATADETE_POS); - MODIFY_REG(tmp, LPUART_CON1_ATDIRM_MSK, config->RS485_AUD << LPUART_CON1_ATDIRM_POS); - MODIFY_REG(tmp, LPUART_CON1_ADETE_MSK, config->RS485_ADD_DET << LPUART_CON1_ADETE_POS); - MODIFY_REG(tmp, LPUART_CON1_ADDCMP_MSK, config->RS485_ADDCMP << LPUART_CON1_ADDCMP_POSS); - WRITE_REG(hperh->perh->CON1, tmp); - - return; + uint32_t tmp; + + assert_param(IS_LPUART(hperh->perh)); + assert_param(IS_FUNC_STATE(config->RS485_NMM)); + assert_param(IS_FUNC_STATE(config->RS485_AAD)); + assert_param(IS_FUNC_STATE(config->RS485_AUD)); + assert_param(IS_FUNC_STATE(config->RS485_ADD_DET)); + + tmp = READ_REG(hperh->perh->CON1); + MODIFY_REG(tmp, LPUART_CON1_NMPMOD_MSK, config->RS485_NMM << LPUART_CON1_NMPMOD_POS); + MODIFY_REG(tmp, LPUART_CON1_ATADETE_MSK, config->RS485_AAD << LPUART_CON1_ATADETE_POS); + MODIFY_REG(tmp, LPUART_CON1_ATDIRM_MSK, config->RS485_AUD << LPUART_CON1_ATDIRM_POS); + MODIFY_REG(tmp, LPUART_CON1_ADETE_MSK, config->RS485_ADD_DET << LPUART_CON1_ADETE_POS); + MODIFY_REG(tmp, LPUART_CON1_ADDCMP_MSK, config->RS485_ADDCMP << LPUART_CON1_ADDCMP_POSS); + WRITE_REG(hperh->perh->CON1, tmp); + + return; } /** @@ -480,49 +474,45 @@ void ald_lpuart_rs485_config(lpuart_handle_t *hperh, lpuart_rs485_config_t *conf */ ald_status_t ald_lpuart_send(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - hperh->err_code = LPUART_ERROR_NONE; - SET_BIT(hperh->state, LPUART_STATE_TX_MASK); - - hperh->tx_size = size; - hperh->tx_count = size; - - while (hperh->tx_count-- > 0) - { - if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = LPUART_STATE_READY; - return TIMEOUT; - } - - WRITE_REG(hperh->perh->TXDR, *buf++); - - if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, RESET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = LPUART_STATE_READY; - return TIMEOUT; - } - } - - if (lpuart_wait_flag(hperh, LPUART_STAT_TXIDLE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = LPUART_STATE_READY; - return TIMEOUT; - } - - CLEAR_BIT(hperh->state, LPUART_STATE_TX_MASK); - __UNLOCK(hperh); - - return OK; + if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = LPUART_ERROR_NONE; + SET_BIT(hperh->state, LPUART_STATE_TX_MASK); + + hperh->tx_size = size; + hperh->tx_count = size; + + while (hperh->tx_count-- > 0) { + if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = LPUART_STATE_READY; + return TIMEOUT; + } + + WRITE_REG(hperh->perh->TXDR, *buf++); + + if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, RESET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = LPUART_STATE_READY; + return TIMEOUT; + } + } + + if (lpuart_wait_flag(hperh, LPUART_STAT_TXIDLE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = LPUART_STATE_READY; + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, LPUART_STATE_TX_MASK); + __UNLOCK(hperh); + + return OK; } /** @@ -536,37 +526,35 @@ ald_status_t ald_lpuart_send(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size */ ald_status_t ald_lpuart_recv(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX)) - return BUSY; + if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX)) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL ) || (size == 0)) + return ERROR; - __LOCK(hperh); + __LOCK(hperh); - hperh->err_code = LPUART_ERROR_NONE; - SET_BIT(hperh->state, LPUART_STATE_RX_MASK); + hperh->err_code = LPUART_ERROR_NONE; + SET_BIT(hperh->state, LPUART_STATE_RX_MASK); - hperh->rx_size = size; - hperh->rx_count = size; + hperh->rx_size = size; + hperh->rx_count = size; - /* Check the remain data to be received */ - while (hperh->rx_count-- > 0) - { - if (lpuart_wait_flag(hperh, LPUART_STAT_RXEMP, RESET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = LPUART_STATE_READY; - return TIMEOUT; - } + /* Check the remain data to be received */ + while (hperh->rx_count-- > 0) { + if (lpuart_wait_flag(hperh, LPUART_STAT_RXEMP, RESET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = LPUART_STATE_READY; + return TIMEOUT; + } - *buf++ = (uint8_t)(hperh->perh->RXDR & 0xFF); - } + *buf++ = (uint8_t)(hperh->perh->RXDR & 0xFF); + } - CLEAR_BIT(hperh->state, LPUART_STATE_RX_MASK); - __UNLOCK(hperh); + CLEAR_BIT(hperh->state, LPUART_STATE_RX_MASK); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -579,24 +567,24 @@ ald_status_t ald_lpuart_recv(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size */ ald_status_t ald_lpuart_send_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size) { - if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX)) - return BUSY; + if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX)) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL ) || (size == 0)) + return ERROR; - __LOCK(hperh); + __LOCK(hperh); - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = LPUART_ERROR_NONE; - SET_BIT(hperh->state, LPUART_STATE_TX_MASK); + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = LPUART_ERROR_NONE; + SET_BIT(hperh->state, LPUART_STATE_TX_MASK); - __UNLOCK(hperh); - ald_lpuart_interrupt_config(hperh, LPUART_IT_TBEMP, ENABLE); + __UNLOCK(hperh); + ald_lpuart_interrupt_config(hperh, LPUART_IT_TBEMP, ENABLE); - return OK; + return OK; } /** @@ -609,27 +597,27 @@ ald_status_t ald_lpuart_send_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_ */ ald_status_t ald_lpuart_recv_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size) { - if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX)) - return BUSY; + if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX)) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL ) || (size == 0)) + return ERROR; - __LOCK(hperh); + __LOCK(hperh); - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = LPUART_ERROR_NONE; - SET_BIT(hperh->state, LPUART_STATE_RX_MASK); + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = LPUART_ERROR_NONE; + SET_BIT(hperh->state, LPUART_STATE_RX_MASK); - __UNLOCK(hperh); + __UNLOCK(hperh); - ald_lpuart_interrupt_config(hperh, LPUART_IT_PERR, ENABLE); - ald_lpuart_interrupt_config(hperh, LPUART_IT_FERR, ENABLE); - ald_lpuart_interrupt_config(hperh, LPUART_IT_RBR, ENABLE); + ald_lpuart_interrupt_config(hperh, LPUART_IT_PERR, ENABLE); + ald_lpuart_interrupt_config(hperh, LPUART_IT_FERR, ENABLE); + ald_lpuart_interrupt_config(hperh, LPUART_IT_RBR, ENABLE); - return OK; + return OK; } #ifdef ALD_DMA @@ -644,51 +632,50 @@ ald_status_t ald_lpuart_recv_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_ */ ald_status_t ald_lpuart_send_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = LPUART_ERROR_NONE; - SET_BIT(hperh->state, LPUART_STATE_TX_MASK); - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - /* Set the dma parameters */ - hperh->hdmatx.cplt_cbk = lpuart_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = lpuart_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDR; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = DMA_MSEL_LPUART0; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_LPUART_TXEMPTY; - hperh->hdmatx.config.channel = channel; - - if (hperh->init.mode == LPUART_MODE_RS485) - { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmatx); - ald_lpuart_clear_flag_status(hperh, LPUART_IF_TC); - __UNLOCK(hperh); - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, ENABLE); - - return OK; + if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = LPUART_ERROR_NONE; + SET_BIT(hperh->state, LPUART_STATE_TX_MASK); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + /* Set the dma parameters */ + hperh->hdmatx.cplt_cbk = lpuart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = lpuart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDR; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = DMA_MSEL_LPUART0; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_LPUART_TXEMPTY; + hperh->hdmatx.config.channel = channel; + + if (hperh->init.mode == LPUART_MODE_RS485) { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmatx); + ald_lpuart_clear_flag_status(hperh, LPUART_IF_TC); + __UNLOCK(hperh); + ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, ENABLE); + + return OK; } /** @@ -702,49 +689,48 @@ ald_status_t ald_lpuart_send_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16 */ ald_status_t ald_lpuart_recv_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->err_code = LPUART_ERROR_NONE; - SET_BIT(hperh->state, LPUART_STATE_RX_MASK); - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - /* Set the dma parameters */ - hperh->hdmarx.cplt_cbk = lpuart_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = lpuart_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->RXDR; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = DMA_MSEL_LPUART0; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_LPUART_RNR; - hperh->hdmarx.config.channel = channel; - - if (hperh->init.mode == LPUART_MODE_RS485) - { - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmarx); - __UNLOCK(hperh); - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, ENABLE); - - return OK; + if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->err_code = LPUART_ERROR_NONE; + SET_BIT(hperh->state, LPUART_STATE_RX_MASK); + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + /* Set the dma parameters */ + hperh->hdmarx.cplt_cbk = lpuart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = lpuart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RXDR; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = DMA_MSEL_LPUART0; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_LPUART_RNR; + hperh->hdmarx.config.channel = channel; + + if (hperh->init.mode == LPUART_MODE_RS485) { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmarx); + __UNLOCK(hperh); + ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, ENABLE); + + return OK; } /** @@ -755,29 +741,25 @@ ald_status_t ald_lpuart_recv_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16 */ ald_status_t ald_lpuart_dma_pause(lpuart_handle_t *hperh) { - __LOCK(hperh); - - if (hperh->state == LPUART_STATE_BUSY_TX) - { - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE); - } - else if (hperh->state == LPUART_STATE_BUSY_RX) - { - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE); - } - else if (hperh->state == LPUART_STATE_BUSY_TX_RX) - { - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE); - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE); - } - else - { - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); - return OK; + __LOCK(hperh); + + if (hperh->state == LPUART_STATE_BUSY_TX) { + ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE); + } + else if (hperh->state == LPUART_STATE_BUSY_RX) { + ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE); + } + else if (hperh->state == LPUART_STATE_BUSY_TX_RX) { + ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE); + ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE); + } + else { + __UNLOCK(hperh); + return ERROR; + } + + __UNLOCK(hperh); + return OK; } /** @@ -788,31 +770,27 @@ ald_status_t ald_lpuart_dma_pause(lpuart_handle_t *hperh) */ ald_status_t ald_lpuart_dma_resume(lpuart_handle_t *hperh) { - __LOCK(hperh); - - if (hperh->state == LPUART_STATE_BUSY_TX) - { - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, ENABLE); - } - else if (hperh->state == LPUART_STATE_BUSY_RX) - { - ald_lpuart_clear_flag_status(hperh, LPUART_IF_RXOV); - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, ENABLE); - } - else if (hperh->state == LPUART_STATE_BUSY_TX_RX) - { - ald_lpuart_clear_flag_status(hperh, LPUART_IF_RXOV); - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, ENABLE); - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, ENABLE); - } - else - { - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); - return OK; + __LOCK(hperh); + + if (hperh->state == LPUART_STATE_BUSY_TX) { + ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, ENABLE); + } + else if (hperh->state == LPUART_STATE_BUSY_RX) { + ald_lpuart_clear_flag_status(hperh, LPUART_IF_RXOV); + ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, ENABLE); + } + else if (hperh->state == LPUART_STATE_BUSY_TX_RX) { + ald_lpuart_clear_flag_status(hperh, LPUART_IF_RXOV); + ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, ENABLE); + ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, ENABLE); + } + else { + __UNLOCK(hperh); + return ERROR; + } + + __UNLOCK(hperh); + return OK; } /** @@ -823,11 +801,11 @@ ald_status_t ald_lpuart_dma_resume(lpuart_handle_t *hperh) */ ald_status_t ald_lpuart_dma_stop(lpuart_handle_t *hperh) { - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE); - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE); + ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE); + ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE); - hperh->state = LPUART_STATE_READY; - return OK; + hperh->state = LPUART_STATE_READY; + return OK; } #endif @@ -839,76 +817,67 @@ ald_status_t ald_lpuart_dma_stop(lpuart_handle_t *hperh) */ void ald_lpuart_irq_handler(lpuart_handle_t *hperh) { - uint32_t flag; - uint32_t source; - - /* Handle CTS wakeup */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_CTSWK); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_CTSWK); - - if ((flag != RESET) && (source != RESET)) - ald_lpuart_clear_flag_status(hperh, LPUART_IF_CTSWK); - - /* Handle DATA wakeup */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_DATWK); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_DATWK); - - if ((flag != RESET) && (source != RESET)) - ald_lpuart_clear_flag_status(hperh, LPUART_IF_DATWK); - - /* Handle parity error */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_PERR); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_PERR); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= LPUART_ERROR_PE; - - /* Handle frame error */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_FERR); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_FERR); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= LPUART_ERROR_FE; - - /* Handle overflow error */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_RXOV); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_RXOV); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= LPUART_ERROR_ORE; - - /* Receive */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_RBR); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_RBR); - - if ((flag != RESET) && (source != RESET)) - __lpuart_recv_by_it(hperh); - - /* Transmite */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_TBEMP); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_TBEMP); - - if ((flag != RESET) && (source != RESET)) - __lpuart_send_by_it(hperh); - - /* End Transmite */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_TC); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_TC); - - if ((flag != RESET) && (source != RESET)) - __lpuart_end_send_by_it(hperh); - - /* Handle error state */ - if (hperh->err_code != LPUART_ERROR_NONE) - { - ald_lpuart_clear_flag_status(hperh, LPUART_IF_PERR); - ald_lpuart_clear_flag_status(hperh, LPUART_IF_FERR); - ald_lpuart_clear_flag_status(hperh, LPUART_IF_RXOV); - hperh->state = LPUART_STATE_READY; - - if (hperh->error_cbk) - hperh->error_cbk(hperh); - } + uint32_t flag; + uint32_t source; + + /* Handle CTS wakeup */ + flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_CTSWK); + source = ald_lpuart_get_it_status(hperh, LPUART_IT_CTSWK); + if ((flag != RESET) && (source != RESET)) + ald_lpuart_clear_flag_status(hperh, LPUART_IF_CTSWK); + + /* Handle DATA wakeup */ + flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_DATWK); + source = ald_lpuart_get_it_status(hperh, LPUART_IT_DATWK); + if ((flag != RESET) && (source != RESET)) + ald_lpuart_clear_flag_status(hperh, LPUART_IF_DATWK); + + /* Handle parity error */ + flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_PERR); + source = ald_lpuart_get_it_status(hperh, LPUART_IT_PERR); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= LPUART_ERROR_PE; + + /* Handle frame error */ + flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_FERR); + source = ald_lpuart_get_it_status(hperh, LPUART_IT_FERR); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= LPUART_ERROR_FE; + + /* Handle overflow error */ + flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_RXOV); + source = ald_lpuart_get_it_status(hperh, LPUART_IT_RXOV); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= LPUART_ERROR_ORE; + + /* Receive */ + flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_RBR); + source = ald_lpuart_get_it_status(hperh, LPUART_IT_RBR); + if ((flag != RESET) && (source != RESET)) + __lpuart_recv_by_it(hperh); + + /* Transmite */ + flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_TBEMP); + source = ald_lpuart_get_it_status(hperh, LPUART_IT_TBEMP); + if ((flag != RESET) && (source != RESET)) + __lpuart_send_by_it(hperh); + + /* End Transmite */ + flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_TC); + source = ald_lpuart_get_it_status(hperh, LPUART_IT_TC); + if ((flag != RESET) && (source != RESET)) + __lpuart_end_send_by_it(hperh); + + /* Handle error state */ + if (hperh->err_code != LPUART_ERROR_NONE) { + ald_lpuart_clear_flag_status(hperh, LPUART_IF_PERR); + ald_lpuart_clear_flag_status(hperh, LPUART_IF_FERR); + ald_lpuart_clear_flag_status(hperh, LPUART_IF_RXOV); + hperh->state = LPUART_STATE_READY; + + if (hperh->error_cbk) + hperh->error_cbk(hperh); + } } /** * @} @@ -950,16 +919,16 @@ void ald_lpuart_irq_handler(lpuart_handle_t *hperh) */ void ald_lpuart_interrupt_config(lpuart_handle_t *hperh, lpuart_it_t it, type_func_t status) { - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_IT(it)); - assert_param(IS_FUNC_STATE(status)); + assert_param(IS_LPUART(hperh->perh)); + assert_param(IS_LPUART_IT(it)); + assert_param(IS_FUNC_STATE(status)); - if (status == ENABLE) - SET_BIT(hperh->perh->IER, it); - else - CLEAR_BIT(hperh->perh->IER, it); + if (status == ENABLE) + SET_BIT(hperh->perh->IER, it); + else + CLEAR_BIT(hperh->perh->IER, it); - return; + return; } /** @@ -971,10 +940,10 @@ void ald_lpuart_interrupt_config(lpuart_handle_t *hperh, lpuart_it_t it, type_fu */ void ald_lpuart_tx_interval_config(lpuart_handle_t *hperh, uint8_t val) { - assert_param(IS_LPUART(hperh->perh)); + assert_param(IS_LPUART(hperh->perh)); - MODIFY_REG(hperh->perh->CON0, LPUART_CON0_INTERVAL_MSK, val << LPUART_CON0_INTERVAL_POSS); - return; + MODIFY_REG(hperh->perh->CON0, LPUART_CON0_INTERVAL_MSK, val << LPUART_CON0_INTERVAL_POSS); + return; } /** @@ -992,26 +961,24 @@ void ald_lpuart_tx_interval_config(lpuart_handle_t *hperh, uint8_t val) */ void ald_lpuart_dma_req_config(lpuart_handle_t *hperh, lpuart_dma_req_t req, type_func_t status) { - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_DMAREQ(req)); - assert_param(IS_FUNC_STATE(status)); - - if (req == LPUART_DMA_REQ_TX) - { - if (status == ENABLE) - SET_BIT(hperh->perh->CON0, LPUART_CON0_TXDMAE_MSK); - else - CLEAR_BIT(hperh->perh->CON0, LPUART_CON0_TXDMAE_MSK); - } - else - { - if (status == ENABLE) - SET_BIT(hperh->perh->CON0, LPUART_CON0_RXDMAE_MSK); - else - CLEAR_BIT(hperh->perh->CON0, LPUART_CON0_RXDMAE_MSK); - } - - return; + assert_param(IS_LPUART(hperh->perh)); + assert_param(IS_LPUART_DMAREQ(req)); + assert_param(IS_FUNC_STATE(status)); + + if (req == LPUART_DMA_REQ_TX) { + if (status == ENABLE) + SET_BIT(hperh->perh->CON0, LPUART_CON0_TXDMAE_MSK); + else + CLEAR_BIT(hperh->perh->CON0, LPUART_CON0_TXDMAE_MSK); + } + else { + if (status == ENABLE) + SET_BIT(hperh->perh->CON0, LPUART_CON0_RXDMAE_MSK); + else + CLEAR_BIT(hperh->perh->CON0, LPUART_CON0_RXDMAE_MSK); + } + + return; } /** @@ -1023,11 +990,11 @@ void ald_lpuart_dma_req_config(lpuart_handle_t *hperh, lpuart_dma_req_t req, typ */ void ald_lpuart_rx_fifo_it_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config) { - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_RXFIFO(config)); + assert_param(IS_LPUART(hperh->perh)); + assert_param(IS_LPUART_RXFIFO(config)); - MODIFY_REG(hperh->perh->FIFOCON, LPUART_FIFOCON_RXTRGLVL_MSK, config << LPUART_FIFOCON_RXTRGLVL_POSS); - return; + MODIFY_REG(hperh->perh->FIFOCON, LPUART_FIFOCON_RXTRGLVL_MSK, config << LPUART_FIFOCON_RXTRGLVL_POSS); + return; } /** @@ -1039,11 +1006,11 @@ void ald_lpuart_rx_fifo_it_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config */ void ald_lpuart_rx_fifo_rts_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config) { - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_RXFIFO(config)); + assert_param(IS_LPUART(hperh->perh)); + assert_param(IS_LPUART_RXFIFO(config)); - MODIFY_REG(hperh->perh->FIFOCON, LPUART_FIFOCON_RTSTRGLVL_MSK, config << LPUART_FIFOCON_RTSTRGLVL_POSS); - return; + MODIFY_REG(hperh->perh->FIFOCON, LPUART_FIFOCON_RTSTRGLVL_MSK, config << LPUART_FIFOCON_RTSTRGLVL_POSS); + return; } /** @@ -1056,35 +1023,32 @@ void ald_lpuart_rx_fifo_rts_config(lpuart_handle_t *hperh, lpuart_rxfifo_t confi */ ald_status_t ald_lpuart_rs485_send_addr(lpuart_handle_t *hperh, uint16_t addr, uint32_t timeout) { - assert_param(IS_LPUART(hperh->perh)); + assert_param(IS_LPUART(hperh->perh)); - if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX)) - return BUSY; + if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX)) + return BUSY; - SET_BIT(hperh->state, LPUART_STATE_TX_MASK); + SET_BIT(hperh->state, LPUART_STATE_TX_MASK); - if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, SET, timeout) != OK) - { - hperh->state = LPUART_STATE_READY; - return TIMEOUT; - } + if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, SET, timeout) != OK) { + hperh->state = LPUART_STATE_READY; + return TIMEOUT; + } - WRITE_REG(hperh->perh->TXDR, addr | 0x100); + WRITE_REG(hperh->perh->TXDR, addr | 0x100); - if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, RESET, timeout) != OK) - { - hperh->state = LPUART_STATE_READY; - return TIMEOUT; - } + if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, RESET, timeout) != OK) { + hperh->state = LPUART_STATE_READY; + return TIMEOUT; + } - if (lpuart_wait_flag(hperh, LPUART_STAT_TXIDLE, SET, timeout) != OK) - { - hperh->state = LPUART_STATE_READY; - return TIMEOUT; - } + if (lpuart_wait_flag(hperh, LPUART_STAT_TXIDLE, SET, timeout) != OK) { + hperh->state = LPUART_STATE_READY; + return TIMEOUT; + } - CLEAR_BIT(hperh->state, LPUART_STATE_TX_MASK); - return OK; + CLEAR_BIT(hperh->state, LPUART_STATE_TX_MASK); + return OK; } /** @@ -1099,13 +1063,13 @@ ald_status_t ald_lpuart_rs485_send_addr(lpuart_handle_t *hperh, uint16_t addr, u */ flag_status_t ald_lpuart_get_status(lpuart_handle_t *hperh, lpuart_status_t flag) { - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_STAT(flag)); + assert_param(IS_LPUART(hperh->perh)); + assert_param(IS_LPUART_STAT(flag)); - if (READ_BIT(hperh->perh->STAT, flag)) - return SET; + if (READ_BIT(hperh->perh->STAT, flag)) + return SET; - return RESET; + return RESET; } /** @@ -1120,13 +1084,13 @@ flag_status_t ald_lpuart_get_status(lpuart_handle_t *hperh, lpuart_status_t flag */ flag_status_t ald_lpuart_get_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag) { - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_IF(flag)); + assert_param(IS_LPUART(hperh->perh)); + assert_param(IS_LPUART_IF(flag)); - if (READ_BIT(hperh->perh->IFLAG, flag)) - return SET; + if (READ_BIT(hperh->perh->IFLAG, flag)) + return SET; - return RESET; + return RESET; } /** @@ -1139,11 +1103,11 @@ flag_status_t ald_lpuart_get_flag_status(lpuart_handle_t *hperh, lpuart_flag_t f */ void ald_lpuart_clear_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag) { - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_IF(flag)); + assert_param(IS_LPUART(hperh->perh)); + assert_param(IS_LPUART_IF(flag)); - WRITE_REG(hperh->perh->IFC, flag); - return; + WRITE_REG(hperh->perh->IFC, flag); + return; } /** @@ -1158,13 +1122,13 @@ void ald_lpuart_clear_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag) */ it_status_t ald_lpuart_get_it_status(lpuart_handle_t *hperh, lpuart_it_t it) { - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_IT(it)); + assert_param(IS_LPUART(hperh->perh)); + assert_param(IS_LPUART_IT(it)); - if (READ_BIT(hperh->perh->IER, it)) - return SET; + if (READ_BIT(hperh->perh->IER, it)) + return SET; - return RESET; + return RESET; } /** * @} @@ -1196,7 +1160,7 @@ it_status_t ald_lpuart_get_it_status(lpuart_handle_t *hperh, lpuart_it_t it) */ lpuart_state_t ald_lpuart_get_state(lpuart_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** @@ -1207,7 +1171,7 @@ lpuart_state_t ald_lpuart_get_state(lpuart_handle_t *hperh) */ uint32_t ald_lpuart_get_error(lpuart_handle_t *hperh) { - return hperh->err_code; + return hperh->err_code; } /** diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pis.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pis.c index 0966ea26a28a0794cb8a096e00b92e8ac9dd8cd7..d9067499ea7e2326421aabf3585fbd68920e821a 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pis.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pis.c @@ -44,99 +44,86 @@ */ ald_status_t ald_pis_create(pis_handle_t *hperh) { - pis_divide_t temp; - uint8_t clock_menu = 0; - - if (hperh == NULL) - return ERROR; - - assert_param(IS_PIS_SRC(hperh->init.producer_src)); - assert_param(IS_PIS_TRIG(hperh->init.consumer_trig)); - assert_param(IS_PIS_CLOCK(hperh->init.producer_clk)); - assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk)); - assert_param(IS_PIS_EDGE(hperh->init.producer_edge)); - - __LOCK(hperh); - hperh->perh = PIS; - - /* get location of consumer in channel and position of con0/con1 - * accord to comsumer_trig information */ - temp.HalfWord = (hperh->init.consumer_trig); - hperh->consumer_ch = (pis_ch_t)(temp.ch); - hperh->consumer_con = (pis_con_t)(temp.con); - hperh->consumer_pos = (1 << temp.shift); - - /* union producer clock and consumer clock */ - clock_menu = (hperh->init.producer_clk << 4) | (hperh->init.consumer_clk); - - if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) - { - __UNLOCK(hperh); - return BUSY; - } - - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS); - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS); - - /* configure sync clock, judging by producer clock with consumer clock */ - switch (clock_menu) - { - case 0x00: - case 0x11: - case 0x22: - case 0x33: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS); - break; - - case 0x01: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS); - break; - - case 0x02: - case 0x12: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS); - break; - - case 0x21: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS); - break; - - case 0x30: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS); - break; - - case 0x31: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS); - break; - - case 0x32: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS); - - default: - break; - } - - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS); - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS); - hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch]; - - /* enable consumer bit, switch pin of consumer */ - switch (hperh->consumer_con) - { - case PIS_CON_0: - PIS->TAR_CON0 |= hperh->consumer_pos; - break; - - case PIS_CON_1: - PIS->TAR_CON1 |= hperh->consumer_pos; - break; - - default: - break; - } - - __UNLOCK(hperh); - return OK; + uint8_t clock_menu = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_PIS_SRC(hperh->init.producer_src)); + assert_param(IS_PIS_TRIG(hperh->init.consumer_trig)); + assert_param(IS_PIS_CLOCK(hperh->init.producer_clk)); + assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk)); + assert_param(IS_PIS_EDGE(hperh->init.producer_edge)); + + __LOCK(hperh); + hperh->perh = PIS; + + /* get location of consumer in channel and position of con0/con1 + * accord to comsumer_trig information */ + hperh->consumer_ch = (pis_ch_t)(hperh->init.consumer_trig & 0x0F); + hperh->consumer_con = (pis_con_t)(((uint32_t)hperh->init.consumer_trig >> 4) & 0x0F); + hperh->consumer_pos = (1U << (uint32_t)(((uint32_t)hperh->init.consumer_trig >> 8) & 0xFF)); + + /* union producer clock and consumer clock */ + clock_menu = (hperh->init.producer_clk << 4) | (hperh->init.consumer_clk); + + if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) { + __UNLOCK(hperh); + return BUSY; + } + + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS); + + /* configure sync clock, judging by producer clock with consumer clock */ + switch (clock_menu) { + case 0x00: + case 0x11: + case 0x22: + case 0x33: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x01: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x02: + case 0x12: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x21: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x30: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x31: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x32: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS); + break; + default: + break; + } + + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS); + hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch]; + + /* enable consumer bit, switch pin of consumer */ + switch (hperh->consumer_con) { + case PIS_CON_0: + PIS->TAR_CON0 |= hperh->consumer_pos; + break; + case PIS_CON_1: + PIS->TAR_CON1 |= hperh->consumer_pos; + break; + default: + break; + } + + __UNLOCK(hperh); + return OK; } /** @@ -148,34 +135,31 @@ ald_status_t ald_pis_create(pis_handle_t *hperh) */ ald_status_t ald_pis_destroy(pis_handle_t *hperh) { - assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS(hperh->perh)); - if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch]) - return ERROR; + if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch]) + return ERROR; - __LOCK(hperh); + __LOCK(hperh); - CLEAR_BIT(PIS->CH_OER, (1 << hperh->consumer_ch)); - WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0); + CLEAR_BIT(PIS->CH_OER, (1U << (uint32_t)hperh->consumer_ch)); + WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0); - switch (hperh->consumer_con) - { - case PIS_CON_0: - PIS->TAR_CON0 &= ~(hperh->consumer_pos); - break; + switch (hperh->consumer_con) { + case PIS_CON_0: + PIS->TAR_CON0 &= ~(hperh->consumer_pos); + break; + case PIS_CON_1: + PIS->TAR_CON1 &= ~(hperh->consumer_pos); + break; + default: + break; + } - case PIS_CON_1: - PIS->TAR_CON1 &= ~(hperh->consumer_pos); - break; + hperh->state = PIS_STATE_RESET; + __UNLOCK(hperh); - default: - break; - } - - hperh->state = PIS_STATE_RESET; - __UNLOCK(hperh); - - return OK; + return OK; } /** * @} @@ -200,13 +184,13 @@ ald_status_t ald_pis_destroy(pis_handle_t *hperh) */ ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch) { - assert_param(IS_PIS(hperh->perh)); - assert_param(IS_PIS_OUPUT_CH(ch)); - __LOCK(hperh); - SET_BIT(PIS->CH_OER, (1 << ch)); - __UNLOCK(hperh); + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_OUPUT_CH(ch)); + __LOCK(hperh); + SET_BIT(PIS->CH_OER, (1 << ch)); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -223,13 +207,13 @@ ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch) */ ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch) { - assert_param(IS_PIS(hperh->perh)); - assert_param(IS_PIS_OUPUT_CH(ch)); - __LOCK(hperh); - CLEAR_BIT(PIS->CH_OER, (1 << ch)); - __UNLOCK(hperh); + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_OUPUT_CH(ch)); + __LOCK(hperh); + CLEAR_BIT(PIS->CH_OER, (1 << ch)); + __UNLOCK(hperh); - return OK; + return OK; } /** * @} @@ -248,8 +232,8 @@ ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch) */ pis_state_t ald_pis_get_state(pis_handle_t *hperh) { - assert_param(IS_PIS(hperh->perh)); - return hperh->state; + assert_param(IS_PIS(hperh->perh)); + return hperh->state; } /** @@ -272,51 +256,50 @@ pis_state_t ald_pis_get_state(pis_handle_t *hperh) */ ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config) { - assert_param(IS_PIS(hperh->perh)); - assert_param(IS_PIS_MODU_TARGET(config->target)); - assert_param(IS_PIS_MODU_LEVEL(config->level)); - assert_param(IS_PIS_MODU_SRC(config->src)); - assert_param(IS_PIS_MODU_CHANNEL(config->channel)); - __LOCK(hperh); - - switch (config->target) - { - case PIS_UART0_TX: - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART1_TX: - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART2_TX: - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART3_TX: - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_LPUART0_TX: - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - default: - break; - } - - __UNLOCK(hperh); - return OK; + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_MODU_TARGET(config->target)); + assert_param(IS_PIS_MODU_LEVEL(config->level)); + assert_param(IS_PIS_MODU_SRC(config->src)); + assert_param(IS_PIS_MODU_CHANNEL(config->channel)); + __LOCK(hperh); + + switch (config->target) { + case PIS_UART0_TX: + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART1_TX: + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART2_TX: + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART3_TX: + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_LPUART0_TX: + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + default: + break; + } + + __UNLOCK(hperh); + return OK; } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pmu.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pmu.c index d8d16f57feccd71b10c15e837dd3a22de934ef29..42094fc298a5f01553244fdd94c603e0c92c37e8 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pmu.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pmu.c @@ -15,7 +15,6 @@ */ #include "ald_pmu.h" -#include "ald_bkpc.h" /** @addtogroup ES32FXXX_ALD @@ -39,11 +38,11 @@ */ void ald_lvd_irq_handler(void) { - SYSCFG_UNLOCK(); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); - SYSCFG_LOCK(); + SYSCFG_UNLOCK(); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + SYSCFG_LOCK(); - return; + return; } /** * @} @@ -63,6 +62,7 @@ void ald_lvd_irq_handler(void) [..] This section provides functions allowing to: (+) Enter stop1 mode. (+) Enter stop2 mode. + (+) Enter standby mode. (+) Get wakeup status. (+) Clear wakeup status. @@ -76,17 +76,17 @@ void ald_lvd_irq_handler(void) */ void ald_pmu_stop1_enter(void) { - SYSCFG_UNLOCK(); - SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); - MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP1 << PMU_CR_LPM_POSS); - SYSCFG_LOCK(); + SYSCFG_UNLOCK(); + SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); + MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP1 << PMU_CR_LPM_POSS); + SYSCFG_LOCK(); - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - return; + return; } /** @@ -95,17 +95,40 @@ void ald_pmu_stop1_enter(void) */ void ald_pmu_stop2_enter(void) { - SYSCFG_UNLOCK(); - SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); - MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP2 << PMU_CR_LPM_POSS); - SYSCFG_LOCK(); + SYSCFG_UNLOCK(); + SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); + MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP2 << PMU_CR_LPM_POSS); + SYSCFG_LOCK(); - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - return; + return; +} + +/** + * @brief Enter standby mode + * @param port: The port whick wake up the standby mode. + * @param level: Wakeup level. + * @retval None + */ +void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level) +{ + ald_bkpc_standby_wakeup_config(port, level); + + SYSCFG_UNLOCK(); + SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); + MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STANDBY << PMU_CR_LPM_POSS); + SYSCFG_LOCK(); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + + return; } /** @@ -117,23 +140,21 @@ void ald_pmu_stop2_enter(void) */ void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state) { - assert_param(IS_FUNC_STATE(state)); - SYSCFG_UNLOCK(); - - if (state) - { - assert_param(IS_PMU_LDO_LPMODE_OUTPUT(vol)); - - MODIFY_REG(PMU->CR, PMU_CR_LPVS_MSK, vol << PMU_CR_LPVS_POSS); - SET_BIT(PMU->CR, PMU_CR_LPRUN_MSK); - } - else - { - CLEAR_BIT(PMU->CR, PMU_CR_LPRUN_MSK); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_FUNC_STATE(state)); + SYSCFG_UNLOCK(); + + if (state) { + assert_param(IS_PMU_LDO_LPMODE_OUTPUT(vol)); + + MODIFY_REG(PMU->CR, PMU_CR_LPVS_MSK, vol << PMU_CR_LPVS_POSS); + SET_BIT(PMU->CR, PMU_CR_LPRUN_MSK); + } + else { + CLEAR_BIT(PMU->CR, PMU_CR_LPRUN_MSK); + } + + SYSCFG_LOCK(); + return; } /** @@ -143,12 +164,12 @@ void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state) */ flag_status_t ald_pmu_get_status(pmu_status_t sr) { - assert_param(IS_PMU_STATUS(sr)); + assert_param(IS_PMU_STATUS(sr)); - if (READ_BIT(PMU->SR, sr)) - return SET; + if (READ_BIT(PMU->SR, sr)) + return SET; - return RESET; + return RESET; } /** @@ -158,19 +179,17 @@ flag_status_t ald_pmu_get_status(pmu_status_t sr) */ void ald_pmu_clear_status(pmu_status_t sr) { - assert_param(IS_PMU_STATUS(sr)); - SYSCFG_UNLOCK(); + assert_param(IS_PMU_STATUS(sr)); + SYSCFG_UNLOCK(); - if (sr == PMU_SR_WUF) - SET_BIT(PMU->CR, PMU_CR_CWUF_MSK); - else - SET_BIT(PMU->CR, PMU_CR_CSTANDBYF_MSK); + if (sr == PMU_SR_WUF) + SET_BIT(PMU->CR, PMU_CR_CWUF_MSK); + else + SET_BIT(PMU->CR, PMU_CR_CSTANDBYF_MSK); - SYSCFG_LOCK(); - return; + SYSCFG_LOCK(); + return; } - - /** * @} */ @@ -199,36 +218,32 @@ void ald_pmu_clear_status(pmu_status_t sr) */ void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state) { - assert_param(IS_FUNC_STATE(state)); - SYSCFG_UNLOCK(); - - if (state) - { - assert_param(IS_PMU_LVD_VOL_SEL(sel)); - assert_param(IS_PMU_LVD_TRIGGER_MODE(mode)); - - MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS); - MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); - } - else - { - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); - CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); - CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_FUNC_STATE(state)); + SYSCFG_UNLOCK(); + + if (state) { + assert_param(IS_PMU_LVD_VOL_SEL(sel)); + assert_param(IS_PMU_LVD_TRIGGER_MODE(mode)); + + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS); + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + else { + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + + SYSCFG_LOCK(); + return; } /** * @} */ - - /** * @} */ @@ -236,7 +251,6 @@ void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, /** * @} */ - /** * @} */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rmu.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rmu.c index b896bcf104e7325a1d30f190a0669391a39c40dd..2b04f2719c57d009170a1d0ac5362d748ff52a7e 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rmu.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rmu.c @@ -40,41 +40,42 @@ */ void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state) { - assert_param(IS_FUNC_STATE(state)); - - SYSCFG_UNLOCK(); - - if (state) - { - assert_param(IS_RMU_BORFLT(flt)); - assert_param(IS_RMU_BORVOL(vol)); - - MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS); - MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS); - SET_BIT(RMU->CR, RMU_CR_BOREN_MSK); - } - else - { - CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_FUNC_STATE(state)); + + SYSCFG_UNLOCK(); + + if (state) { + assert_param(IS_RMU_BORFLT(flt)); + assert_param(IS_RMU_BORVOL(vol)); + + MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS); + MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS); + SET_BIT(RMU->CR, RMU_CR_BOREN_MSK); + } + else { + CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK); + } + + SYSCFG_LOCK(); + return; } /** * @brief Get specified reset status * @param state: Speicifies the type of the reset, - * @retval The status: SET/RESET. + * @retval The status. */ -flag_status_t ald_rmu_get_reset_status(rmu_state_t state) +uint32_t ald_rmu_get_reset_status(rmu_state_t state) { - assert_param(IS_RMU_STATE(state)); + assert_param(IS_RMU_STATE(state)); + + if (state == RMU_RST_ALL) + return RMU->RSTSR; - if (READ_BIT(RMU->RSTSR, state)) - return SET; + if (READ_BIT(RMU->RSTSR, state)) + return SET; - return RESET; + return RESET; } /** @@ -84,13 +85,13 @@ flag_status_t ald_rmu_get_reset_status(rmu_state_t state) */ void ald_rmu_clear_reset_status(rmu_state_t state) { - assert_param(IS_RMU_STATE_CLEAR(state)); + assert_param(IS_RMU_STATE_CLEAR(state)); - SYSCFG_UNLOCK(); - WRITE_REG(RMU->CRSTSR, state); - SYSCFG_LOCK(); + SYSCFG_UNLOCK(); + WRITE_REG(RMU->CRSTSR, state); + SYSCFG_LOCK(); - return; + return; } /** * @brief Reset peripheral device @@ -99,38 +100,37 @@ void ald_rmu_clear_reset_status(rmu_state_t state) */ void ald_rmu_reset_periperal(rmu_peripheral_t perh) { - uint32_t idx, pos; + uint32_t idx, pos; - assert_param(IS_RMU_PERH(perh)); + assert_param(IS_RMU_PERH(perh)); - idx = (perh >> 27) & 0x7; - pos = perh & ~(0x7 << 27); - SYSCFG_UNLOCK(); + idx = ((uint32_t)perh >> 27) & 0x7; + pos = perh & ~(0x7 << 27); + SYSCFG_UNLOCK(); - switch (idx) - { - case 0: - WRITE_REG(RMU->AHB1RSTR, pos); - break; + switch (idx) { + case 0: + WRITE_REG(RMU->AHB1RSTR, pos); + break; - case 1: - WRITE_REG(RMU->AHB2RSTR, pos); - break; + case 1: + WRITE_REG(RMU->AHB2RSTR, pos); + break; - case 2: - WRITE_REG(RMU->APB1RSTR, pos); - break; + case 2: + WRITE_REG(RMU->APB1RSTR, pos); + break; - case 4: - WRITE_REG(RMU->APB2RSTR, pos); - break; + case 4: + WRITE_REG(RMU->APB2RSTR, pos); + break; - default: - break; - } + default: + break; + } - SYSCFG_LOCK(); - return; + SYSCFG_LOCK(); + return; } /** diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rtc.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rtc.c index c8294d3ab7d4472daa7ab7e6949501d4757ed4a1..7391045a62dbc821736d01935c5657590924d6fb 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rtc.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rtc.c @@ -142,7 +142,7 @@ */ static uint32_t bcd_to_dec(uint32_t bcd) { - return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10); + return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10); } /** @@ -152,7 +152,7 @@ static uint32_t bcd_to_dec(uint32_t bcd) */ static uint32_t dec_to_bcd(uint32_t dec) { - return (((dec / 10) << 4) | (dec % 10)); + return (((dec / 10) << 4) | (dec % 10)); } /** @@ -166,27 +166,22 @@ static uint32_t dec_to_bcd(uint32_t dec) * 1 - Consistency */ static int32_t rtc_consistency_check(rtc_time_t *t_last, - rtc_date_t *d_last, rtc_time_t *time, rtc_date_t *date) + rtc_date_t *d_last, rtc_time_t *time, rtc_date_t *date) { - if (t_last->second != time->second) - return 0; - - if (t_last->minute != time->minute) - return 0; - - if (t_last->hour != time->hour) - return 0; - - if (d_last->day != date->day) - return 0; - - if (d_last->month != date->month) - return 0; - - if (d_last->year != date->year) - return 0; - - return 1; + if (t_last->second != time->second) + return 0; + if (t_last->minute != time->minute) + return 0; + if (t_last->hour != time->hour) + return 0; + if (d_last->day != date->day) + return 0; + if (d_last->month != date->month) + return 0; + if (d_last->year != date->year) + return 0; + + return 1; } /** * @} @@ -224,16 +219,16 @@ static int32_t rtc_consistency_check(rtc_time_t *t_last, */ void ald_rtc_reset(void) { - RTC_UNLOCK(); + RTC_UNLOCK(); - WRITE_REG(RTC->CON, 0x0); - WRITE_REG(RTC->TAMPCON, 0x0); - WRITE_REG(RTC->WUMAT, 0x0); - WRITE_REG(RTC->IER, 0x0); - WRITE_REG(RTC->IFCR, ~0x0); + WRITE_REG(RTC->CON, 0x0); + WRITE_REG(RTC->TAMPCON, 0x0); + WRITE_REG(RTC->WUMAT, 0x0); + WRITE_REG(RTC->IER, 0x0); + WRITE_REG(RTC->IFCR, ~0x0); - RTC_LOCK(); - return; + RTC_LOCK(); + return; } /** @@ -244,22 +239,22 @@ void ald_rtc_reset(void) */ void ald_rtc_init(rtc_init_t *init) { - assert_param(IS_RTC_HOUR_FORMAT(init->hour_format)); - assert_param(IS_RTC_OUTPUT_SEL(init->output)); - assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); - - ald_rtc_reset(); - RTC_UNLOCK(); - - MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); - MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS); - MODIFY_REG(RTC->CON, RTC_CON_POL_MSK, init->output_polarity << RTC_CON_POL_POS); - MODIFY_REG(RTC->PSR, RTC_PSR_SPRS_MSK, init->synch_pre_div << RTC_PSR_SPRS_POSS); - MODIFY_REG(RTC->PSR, RTC_PSR_APRS_MSK, init->asynch_pre_div << RTC_PSR_APRS_POSS); - SET_BIT(RTC->CON, RTC_CON_GO_MSK); - - RTC_LOCK(); - return; + assert_param(IS_RTC_HOUR_FORMAT(init->hour_format)); + assert_param(IS_RTC_OUTPUT_SEL(init->output)); + assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); + + ald_rtc_reset(); + RTC_UNLOCK(); + + MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); + MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS); + MODIFY_REG(RTC->CON, RTC_CON_POL_MSK, init->output_polarity << RTC_CON_POL_POS); + MODIFY_REG(RTC->PSR, RTC_PSR_SPRS_MSK, init->synch_pre_div << RTC_PSR_SPRS_POSS); + MODIFY_REG(RTC->PSR, RTC_PSR_APRS_MSK, init->asynch_pre_div << RTC_PSR_APRS_POSS); + SET_BIT(RTC->CON, RTC_CON_GO_MSK); + + RTC_LOCK(); + return; } /** @@ -269,26 +264,23 @@ void ald_rtc_init(rtc_init_t *init) */ void ald_rtc_source_select(rtc_source_sel_t sel) { - assert_param(IS_RTC_SOURCE_SEL(sel)); - - BKPC_UNLOCK(); - MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, sel << BKPC_PCCR_RTCCS_POSS); - - if (sel == RTC_SOURCE_LOSC) - { - SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); - } - else if (sel == RTC_SOURCE_LRC) - { - SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); - } - else - { - ; /* do nothing */ - } - - BKPC_LOCK(); - return; + assert_param(IS_RTC_SOURCE_SEL(sel)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, sel << BKPC_PCCR_RTCCS_POSS); + + if (sel == RTC_SOURCE_LOSC) { + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); + } + else if (sel == RTC_SOURCE_LRC) { + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); + } + else { + ; /* do nothing */ + } + + BKPC_LOCK(); + return; } /** * @} @@ -319,45 +311,41 @@ void ald_rtc_source_select(rtc_source_sel_t sel) * @param format: Data format. * @retval ALD status. */ -ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format) +ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format) { - uint32_t tmp; - - assert_param(IS_RTC_FORMAT(format)); - - if (format == RTC_FORMAT_DEC) - { - assert_param(IS_RTC_SECOND(time->second)); - assert_param(IS_RTC_MINUTE(time->minute)); - assert_param(IS_RTC_HOUR(time->hour)); - - tmp = (dec_to_bcd(time->second)) | - (dec_to_bcd(time->minute) << 8) | - (dec_to_bcd(time->hour) << 16); - } - else - { - assert_param(IS_RTC_SECOND(bcd_to_dec(time->second))); - assert_param(IS_RTC_MINUTE(bcd_to_dec(time->minute))); - assert_param(IS_RTC_HOUR(bcd_to_dec(time->hour))); - - tmp = time->second | (time->minute << 8) | (time->hour << 16); - } - - RTC_UNLOCK(); - WRITE_REG(RTC->TIME, tmp); - WRITE_REG(RTC->SSEC, time->sub_sec); - RTC_LOCK(); - - tmp = ald_get_tick(); - - while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) - { - if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) - return TIMEOUT; - } - - return OK; + uint32_t tmp; + + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + assert_param(IS_RTC_SECOND(time->second)); + assert_param(IS_RTC_MINUTE(time->minute)); + assert_param(IS_RTC_HOUR(time->hour)); + + tmp = (dec_to_bcd(time->second)) | + (dec_to_bcd(time->minute) << 8) | + (dec_to_bcd(time->hour) << 16); + } + else { + assert_param(IS_RTC_SECOND(bcd_to_dec(time->second))); + assert_param(IS_RTC_MINUTE(bcd_to_dec(time->minute))); + assert_param(IS_RTC_HOUR(bcd_to_dec(time->hour))); + + tmp = time->second | (time->minute << 8) | (time->hour << 16); + } + + RTC_UNLOCK(); + WRITE_REG(RTC->TIME, tmp); + RTC_LOCK(); + + tmp = ald_get_tick(); + + while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) { + if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } + + return OK; } /** @@ -368,44 +356,41 @@ ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format) */ ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format) { - uint32_t tmp; - - assert_param(IS_RTC_FORMAT(format)); - - if (format == RTC_FORMAT_DEC) - { - assert_param(IS_RTC_DAY(date->day)); - assert_param(IS_RTC_MONTH(date->month)); - assert_param(IS_RTC_YEAR(date->year)); - - tmp = (dec_to_bcd(date->day)) | - (dec_to_bcd(date->month) << 8) | - (dec_to_bcd(date->year) << 16) | - (dec_to_bcd(date->week) << 24); - } - else - { - assert_param(IS_RTC_DAY(bcd_to_dec(date->day))); - assert_param(IS_RTC_MONTH(bcd_to_dec(date->month))); - assert_param(IS_RTC_YEAR(bcd_to_dec(date->year))); - - tmp = date->day | (date->month << 8) | - (date->year << 16) | (date->week << 24); - } - - RTC_UNLOCK(); - WRITE_REG(RTC->DATE, tmp); - RTC_LOCK(); - - tmp = ald_get_tick(); - - while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) - { - if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) - return TIMEOUT; - } - - return OK; + uint32_t tmp; + + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + assert_param(IS_RTC_DAY(date->day)); + assert_param(IS_RTC_MONTH(date->month)); + assert_param(IS_RTC_YEAR(date->year)); + + tmp = (dec_to_bcd(date->day)) | + (dec_to_bcd(date->month) << 8) | + (dec_to_bcd(date->year) << 16) | + (dec_to_bcd(date->week) << 24); + } + else { + assert_param(IS_RTC_DAY(bcd_to_dec(date->day))); + assert_param(IS_RTC_MONTH(bcd_to_dec(date->month))); + assert_param(IS_RTC_YEAR(bcd_to_dec(date->year))); + + tmp = date->day | (date->month << 8) | + (date->year << 16) | (date->week << 24); + } + + RTC_UNLOCK(); + WRITE_REG(RTC->DATE, tmp); + RTC_LOCK(); + + tmp = ald_get_tick(); + + while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) { + if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } + + return OK; } /** @@ -416,28 +401,26 @@ ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format) */ void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format) { - uint32_t tmp; - - assert_param(time != NULL); - assert_param(IS_RTC_FORMAT(format)); - - time->sub_sec = RTC->SSEC & 0xFFFF; - tmp = RTC->TIME; - - if (format == RTC_FORMAT_DEC) - { - time->second = bcd_to_dec(tmp & 0x7F); - time->minute = bcd_to_dec((tmp >> 8) & 0x7F); - time->hour = bcd_to_dec((tmp >> 16) & 0x7F); - } - else - { - time->second = tmp & 0x7F; - time->minute = (tmp >> 8) & 0x7F; - time->hour = (tmp >> 16) & 0x7F; - } - - return; + uint32_t tmp; + + assert_param(time != NULL); + assert_param(IS_RTC_FORMAT(format)); + + time->sub_sec = RTC->SSEC & 0xFFFF; + tmp = RTC->TIME; + + if (format == RTC_FORMAT_DEC) { + time->second = bcd_to_dec(tmp & 0x7F); + time->minute = bcd_to_dec((tmp >> 8) & 0x7F); + time->hour = bcd_to_dec((tmp >> 16) & 0x7F); + } + else { + time->second = tmp & 0x7F; + time->minute = (tmp >> 8) & 0x7F; + time->hour = (tmp >> 16) & 0x7F; + } + + return; } /** @@ -448,27 +431,25 @@ void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format) */ void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format) { - uint32_t tmp = RTC->DATE; - - assert_param(date != NULL); - assert_param(IS_RTC_FORMAT(format)); - - if (format == RTC_FORMAT_DEC) - { - date->day = bcd_to_dec(tmp & 0x3F); - date->month = bcd_to_dec((tmp >> 8) & 0x1F); - date->year = bcd_to_dec((tmp >> 16) & 0xFF); - date->week = bcd_to_dec((tmp >> 24) & 0x7); - } - else - { - date->day = tmp & 0x3F; - date->month = (tmp >> 8) & 0x1F; - date->year = (tmp >> 16) & 0xFF; - date->week = (tmp >> 24) & 0x7; - } - - return; + uint32_t tmp = RTC->DATE; + + assert_param(date != NULL); + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + date->day = bcd_to_dec(tmp & 0x3F); + date->month = bcd_to_dec((tmp >> 8) & 0x1F); + date->year = bcd_to_dec((tmp >> 16) & 0xFF); + date->week = bcd_to_dec((tmp >> 24) & 0x7); + } + else { + date->day = tmp & 0x3F; + date->month = (tmp >> 8) & 0x1F; + date->year = (tmp >> 16) & 0xFF; + date->week = (tmp >> 24) & 0x7; + } + + return; } /** @@ -482,22 +463,21 @@ void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format) */ int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format) { - int32_t nr = 3; - rtc_date_t d_last; - rtc_time_t t_last; - - while (nr--) - { - ald_rtc_get_time(&t_last, format); - ald_rtc_get_date(&d_last, format); - ald_rtc_get_time(time, format); - ald_rtc_get_date(date, format); - - if (rtc_consistency_check(&t_last, &d_last, time, date)) - return 0; - } - - return -1; + int32_t nr = 3; + rtc_date_t d_last; + rtc_time_t t_last; + + while (nr--) { + ald_rtc_get_time(&t_last, format); + ald_rtc_get_date(&d_last, format); + ald_rtc_get_time(time, format); + ald_rtc_get_date(date, format); + + if (rtc_consistency_check(&t_last, &d_last, time, date)) + return 0; + } + + return -1; } /** * @} @@ -528,82 +508,74 @@ int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t f */ void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format) { - unsigned int tmp, ss_tmp; - - assert_param(IS_RTC_ALARM(alarm->idx)); - assert_param(IS_RTC_ALARM_SEL(alarm->sel)); - assert_param(IS_RTC_ALARM_SS_MASK(alarm->ss_mask)); - assert_param(IS_RTC_FORMAT(format)); - - if (format == RTC_FORMAT_DEC) - { - assert_param(IS_RTC_SECOND(alarm->time.second)); - assert_param(IS_RTC_MINUTE(alarm->time.minute)); - assert_param(IS_RTC_HOUR(alarm->time.hour)); - - tmp = (dec_to_bcd(alarm->time.second)) | - (dec_to_bcd(alarm->time.minute) << 8) | - (dec_to_bcd(alarm->time.hour) << 16) | - alarm->mask; - - if (alarm->sel == RTC_SELECT_DAY) - { - assert_param(IS_RTC_DAY(alarm->day)); - - tmp |= (dec_to_bcd(alarm->day) << 24); - tmp &= 0x7FFFFFFF; /* Reset bit31 */ - } - else - { - tmp |= (1 << (alarm->week + 24)); - tmp |= 0x80000000; /* Set bit31 */ - } - } - else - { - assert_param(IS_RTC_SECOND(bcd_to_dec(alarm->time.second))); - assert_param(IS_RTC_MINUTE(bcd_to_dec(alarm->time.minute))); - assert_param(IS_RTC_HOUR(bcd_to_dec(alarm->time.hour))); - - tmp = alarm->time.second | - (alarm->time.minute << 8) | - (alarm->time.hour << 16) | - alarm->mask; - - if (alarm->sel == RTC_SELECT_DAY) - { - assert_param(IS_RTC_DAY(bcd_to_dec(alarm->day))); - - tmp |= (alarm->day << 24); - tmp &= 0x7FFFFFFF; /* Reset bit31 */ - } - else - { - tmp |= (1 << (alarm->week + 24)); - tmp |= 0x80000000; /* Set bit31 */ - } - } - - ss_tmp = (alarm->time.sub_sec & 0x7F) | - (alarm->ss_mask << 24); - - RTC_UNLOCK(); - - if (alarm->idx == RTC_ALARM_A) - { - WRITE_REG(RTC->ALMA, tmp); - WRITE_REG(RTC->ALMASSEC, ss_tmp); - SET_BIT(RTC->CON, RTC_CON_ALMAEN_MSK); - } - else - { - WRITE_REG(RTC->ALMB, tmp); - WRITE_REG(RTC->ALMBSSEC, ss_tmp); - SET_BIT(RTC->CON, RTC_CON_ALMBEN_MSK); - } - - RTC_LOCK(); - return; + unsigned int tmp, ss_tmp; + + assert_param(IS_RTC_ALARM(alarm->idx)); + assert_param(IS_RTC_ALARM_SEL(alarm->sel)); + assert_param(IS_RTC_ALARM_SS_MASK(alarm->ss_mask)); + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + assert_param(IS_RTC_SECOND(alarm->time.second)); + assert_param(IS_RTC_MINUTE(alarm->time.minute)); + assert_param(IS_RTC_HOUR(alarm->time.hour)); + + tmp = (dec_to_bcd(alarm->time.second)) | + (dec_to_bcd(alarm->time.minute) << 8) | + (dec_to_bcd(alarm->time.hour) << 16) | + alarm->mask; + + if (alarm->sel == RTC_SELECT_DAY) { + assert_param(IS_RTC_DAY(alarm->day)); + + tmp |= (dec_to_bcd(alarm->day) << 24); + tmp &= 0x7FFFFFFF; /* Reset bit31 */ + } + else { + tmp |= (1 << (alarm->week + 24)); + tmp |= 0x80000000; /* Set bit31 */ + } + } + else { + assert_param(IS_RTC_SECOND(bcd_to_dec(alarm->time.second))); + assert_param(IS_RTC_MINUTE(bcd_to_dec(alarm->time.minute))); + assert_param(IS_RTC_HOUR(bcd_to_dec(alarm->time.hour))); + + tmp = alarm->time.second | + (alarm->time.minute << 8) | + (alarm->time.hour << 16) | + alarm->mask; + + if (alarm->sel == RTC_SELECT_DAY) { + assert_param(IS_RTC_DAY(bcd_to_dec(alarm->day))); + + tmp |= (alarm->day << 24); + tmp &= 0x7FFFFFFF; /* Reset bit31 */ + } + else { + tmp |= (1 << (alarm->week + 24)); + tmp |= 0x80000000; /* Set bit31 */ + } + } + + ss_tmp = (alarm->time.sub_sec & 0x7F) | + (alarm->ss_mask << 24); + + RTC_UNLOCK(); + + if (alarm->idx == RTC_ALARM_A) { + WRITE_REG(RTC->ALMA, tmp); + WRITE_REG(RTC->ALMASSEC, ss_tmp); + SET_BIT(RTC->CON, RTC_CON_ALMAEN_MSK); + } + else { + WRITE_REG(RTC->ALMB, tmp); + WRITE_REG(RTC->ALMBSSEC, ss_tmp); + SET_BIT(RTC->CON, RTC_CON_ALMBEN_MSK); + } + + RTC_LOCK(); + return; } /** @@ -614,90 +586,76 @@ void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format) */ void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) { - uint8_t week; - uint32_t tmp, ss_tmp; - - assert_param(alarm != NULL); - assert_param(IS_RTC_FORMAT(format)); - - if (alarm->idx == RTC_ALARM_A) - { - tmp = RTC->ALMA; - ss_tmp = RTC->ALMASSEC; - } - else - { - tmp = RTC->ALMB; - ss_tmp = RTC->ALMBSSEC; - } - - if ((tmp >> 31) & 0x1) - { - alarm->sel = RTC_SELECT_WEEK; - week = ((tmp >> 24) & 0x7F); - - switch (week) - { - case 1: - alarm->week = 0; - break; - - case 2: - alarm->week = 1; - break; - - case 4: - alarm->week = 2; - break; - - case 8: - alarm->week = 3; - break; - - case 16: - alarm->week = 4; - break; - - case 32: - alarm->week = 5; - break; - - case 64: - alarm->week = 6; - break; - - default: - break; - } - } - else - { - alarm->sel = RTC_SELECT_DAY; - - if (format == RTC_FORMAT_DEC) - alarm->day = bcd_to_dec((tmp >> 24) & 0x3F); - else - alarm->day = (tmp >> 24) & 0x3F; - } - - if (format == RTC_FORMAT_DEC) - { - alarm->time.second = bcd_to_dec(tmp & 0x7F); - alarm->time.minute = bcd_to_dec((tmp >> 8) & 0x7F); - alarm->time.hour = bcd_to_dec((tmp >> 16) & 0x3F); - } - else - { - alarm->time.second = tmp & 0x7F; - alarm->time.minute = (tmp >> 8) & 0x7F; - alarm->time.hour = (tmp >> 16) & 0x3F; - } - - alarm->time.sub_sec = ss_tmp & 0x7FFF; - alarm->ss_mask = (rtc_sub_second_mask_t)((ss_tmp >> 24) & 0xF); - alarm->mask = tmp & ALARM_MASK_ALL; - - return; + uint8_t week; + uint32_t tmp, ss_tmp; + + assert_param(alarm != NULL); + assert_param(IS_RTC_FORMAT(format)); + + if (alarm->idx == RTC_ALARM_A) { + tmp = RTC->ALMA; + ss_tmp = RTC->ALMASSEC; + } + else { + tmp = RTC->ALMB; + ss_tmp = RTC->ALMBSSEC; + } + + if ((tmp >> 31) & 0x1) { + alarm->sel = RTC_SELECT_WEEK; + week = ((tmp >> 24) & 0x7F); + + switch (week) { + case 1: + alarm->week = 0; + break; + case 2: + alarm->week = 1; + break; + case 4: + alarm->week = 2; + break; + case 8: + alarm->week = 3; + break; + case 16: + alarm->week = 4; + break; + case 32: + alarm->week = 5; + break; + case 64: + alarm->week = 6; + break; + default: + break; + } + } + else { + alarm->sel = RTC_SELECT_DAY; + + if (format == RTC_FORMAT_DEC) + alarm->day = bcd_to_dec((tmp >> 24) & 0x3F); + else + alarm->day = (tmp >> 24) & 0x3F; + } + + if (format == RTC_FORMAT_DEC) { + alarm->time.second = bcd_to_dec(tmp & 0x7F); + alarm->time.minute = bcd_to_dec((tmp >> 8) & 0x7F); + alarm->time.hour = bcd_to_dec((tmp >> 16) & 0x3F); + } + else { + alarm->time.second = tmp & 0x7F; + alarm->time.minute = (tmp >> 8) & 0x7F; + alarm->time.hour = (tmp >> 16) & 0x3F; + } + + alarm->time.sub_sec = ss_tmp & 0x7FFF; + alarm->ss_mask = (rtc_sub_second_mask_t)((ss_tmp >> 24) & 0xF); + alarm->mask = tmp & ALARM_MASK_ALL; + + return; } /** * @} @@ -733,18 +691,18 @@ void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) */ void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style) { - assert_param(IS_RTC_TS_SIGNAL(sel)); - assert_param(IS_RTC_TS_STYLE(style)); + assert_param(IS_RTC_TS_SIGNAL(sel)); + assert_param(IS_RTC_TS_STYLE(style)); - RTC_UNLOCK(); + RTC_UNLOCK(); - CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); - MODIFY_REG(RTC->CON, RTC_CON_TSSEL_MSK, style << RTC_CON_TSSEL_POS); - MODIFY_REG(RTC->CON, RTC_CON_TSPIN_MSK, sel << RTC_CON_TSPIN_POS); - SET_BIT(RTC->CON, RTC_CON_TSEN_MSK); + CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); + MODIFY_REG(RTC->CON, RTC_CON_TSSEL_MSK, style << RTC_CON_TSSEL_POS); + MODIFY_REG(RTC->CON, RTC_CON_TSPIN_MSK, sel << RTC_CON_TSPIN_POS); + SET_BIT(RTC->CON, RTC_CON_TSEN_MSK); - RTC_LOCK(); - return; + RTC_LOCK(); + return; } /** @@ -753,11 +711,11 @@ void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t styl */ void ald_rtc_cancel_time_stamp(void) { - RTC_UNLOCK(); - CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); - RTC_LOCK(); + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); + RTC_LOCK(); - return; + return; } /** @@ -769,38 +727,36 @@ void ald_rtc_cancel_time_stamp(void) */ void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format) { - uint32_t tmp0, tmp1; - - assert_param(ts_time != NULL); - assert_param(ts_date != NULL); - assert_param(IS_RTC_FORMAT(format)); - - ts_time->sub_sec = RTC->TSSSEC & 0xFFFF; - tmp0 = RTC->TSTIME; - tmp1 = RTC->TSDATE; - - if (format == RTC_FORMAT_DEC) - { - ts_time->second = bcd_to_dec(tmp0 & 0x7F); - ts_time->minute = bcd_to_dec((tmp0 >> 8) & 0x7F); - ts_time->hour = bcd_to_dec((tmp0 >> 16) & 0x3F); - ts_date->day = bcd_to_dec(tmp1 & 0x3F); - ts_date->month = bcd_to_dec((tmp1 >> 8) & 0x1F); - ts_date->year = bcd_to_dec((tmp1 >> 16) & 0xFF); - ts_date->week = bcd_to_dec((tmp1 >> 24) & 0x7); - } - else - { - ts_time->second = tmp0 & 0x7F; - ts_time->minute = (tmp0 >> 8) & 0x7F; - ts_time->hour = (tmp0 >> 16) & 0x3F; - ts_date->day = tmp1 & 0x3F; - ts_date->month = (tmp1 >> 8) & 0x1F; - ts_date->year = (tmp1 >> 16) & 0xFF; - ts_date->week = (tmp1 >> 24) & 0x7; - } - - return; + uint32_t tmp0, tmp1; + + assert_param(ts_time != NULL); + assert_param(ts_date != NULL); + assert_param(IS_RTC_FORMAT(format)); + + ts_time->sub_sec = RTC->TSSSEC & 0xFFFF; + tmp0 = RTC->TSTIME; + tmp1 = RTC->TSDATE; + + if (format == RTC_FORMAT_DEC) { + ts_time->second = bcd_to_dec(tmp0 & 0x7F); + ts_time->minute = bcd_to_dec((tmp0 >> 8) & 0x7F); + ts_time->hour = bcd_to_dec((tmp0 >> 16) & 0x3F); + ts_date->day = bcd_to_dec(tmp1 & 0x3F); + ts_date->month = bcd_to_dec((tmp1 >> 8) & 0x1F); + ts_date->year = bcd_to_dec((tmp1 >> 16) & 0xFF); + ts_date->week = bcd_to_dec((tmp1 >> 24) & 0x7); + } + else { + ts_time->second = tmp0 & 0x7F; + ts_time->minute = (tmp0 >> 8) & 0x7F; + ts_time->hour = (tmp0 >> 16) & 0x3F; + ts_date->day = tmp1 & 0x3F; + ts_date->month = (tmp1 >> 8) & 0x1F; + ts_date->year = (tmp1 >> 16) & 0xFF; + ts_date->week = (tmp1 >> 24) & 0x7; + } + + return; } /** * @} @@ -829,30 +785,28 @@ void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format */ void ald_rtc_set_tamper(rtc_tamper_t *tamper) { - assert_param(IS_RTC_TAMPER(tamper->idx)); - assert_param(IS_RTC_TAMPER_TRIGGER(tamper->trig)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(tamper->freq)); - assert_param(IS_RTC_TAMPER_DURATION(tamper->dur)); - assert_param(IS_FUNC_STATE(tamper->ts)); - - RTC_UNLOCK(); - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPTS_MSK, tamper->ts << RTC_TAMPCON_TAMPTS_POS); - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPCKS_MSK, tamper->freq << RTC_TAMPCON_TAMPCKS_POSS); - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPFLT_MSK, tamper->dur << RTC_TAMPCON_TAMPFLT_POSS); - - if (tamper->idx == RTC_TAMPER_0) - { - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP1LV_MSK, tamper->trig << RTC_TAMPCON_TAMP1LV_POS); - SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); - } - else - { - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP2LV_MSK, tamper->trig << RTC_TAMPCON_TAMP2LV_POS); - SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK); - } - - RTC_LOCK(); - return; + assert_param(IS_RTC_TAMPER(tamper->idx)); + assert_param(IS_RTC_TAMPER_TRIGGER(tamper->trig)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(tamper->freq)); + assert_param(IS_RTC_TAMPER_DURATION(tamper->dur)); + assert_param(IS_FUNC_STATE(tamper->ts)); + + RTC_UNLOCK(); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPTS_MSK, tamper->ts << RTC_TAMPCON_TAMPTS_POS); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPCKS_MSK, tamper->freq << RTC_TAMPCON_TAMPCKS_POSS); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPFLT_MSK, tamper->dur << RTC_TAMPCON_TAMPFLT_POSS); + + if (tamper->idx == RTC_TAMPER_0) { + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP0LV_MSK, tamper->trig << RTC_TAMPCON_TAMP0LV_POS); + SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP0EN_MSK); + } + else { + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP1LV_MSK, tamper->trig << RTC_TAMPCON_TAMP1LV_POS); + SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); + } + + RTC_LOCK(); + return; } /** @@ -864,17 +818,17 @@ void ald_rtc_set_tamper(rtc_tamper_t *tamper) */ void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx) { - assert_param(IS_RTC_TAMPER(idx)); + assert_param(IS_RTC_TAMPER(idx)); - RTC_UNLOCK(); + RTC_UNLOCK(); - if (idx == RTC_TAMPER_0) - CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); - else - CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK); + if (idx == RTC_TAMPER_0) + CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP0EN_MSK); + else + CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); - RTC_LOCK(); - return; + RTC_LOCK(); + return; } /** * @} @@ -905,15 +859,15 @@ void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx) */ void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value) { - assert_param(IS_RTC_WAKEUP_CLOCK(clock)); + assert_param(IS_RTC_WAKEUP_CLOCK(clock)); - RTC_UNLOCK(); - MODIFY_REG(RTC->CON, RTC_CON_WUCKS_MSK, clock << RTC_CON_WUCKS_POSS); - WRITE_REG(RTC->WUMAT, value & 0xFFFF); - SET_BIT(RTC->CON, RTC_CON_WUTE_MSK); - RTC_LOCK(); + RTC_UNLOCK(); + MODIFY_REG(RTC->CON, RTC_CON_WUCKS_MSK, clock << RTC_CON_WUCKS_POSS); + WRITE_REG(RTC->WUMAT, value & 0xFFFF); + SET_BIT(RTC->CON, RTC_CON_WUTE_MSK); + RTC_LOCK(); - return; + return; } /** @@ -922,11 +876,11 @@ void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value) */ void ald_rtc_cancel_wakeup(void) { - RTC_UNLOCK(); - CLEAR_BIT(RTC->CON, RTC_CON_WUTE_MSK); - RTC_LOCK(); + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_WUTE_MSK); + RTC_LOCK(); - return; + return; } /** @@ -935,7 +889,7 @@ void ald_rtc_cancel_wakeup(void) */ uint16_t ald_rtc_get_wakeup_timer_value(void) { - return RTC->WUMAT & 0xFFFF; + return RTC->WUMAT & 0xFFFF; } /** * @} @@ -964,33 +918,28 @@ uint16_t ald_rtc_get_wakeup_timer_value(void) */ ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock) { - uint32_t cnt = 4000; - assert_param(IS_RTC_CLOCK_OUTPUT(clock)); - - SYSCFG_UNLOCK(); - - if (clock == RTC_CLOCK_OUTPUT_EXA_1) - { - SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); - - while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2LCKN_MSK)) && (--cnt)); - - cnt = 4000; - - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL2RDY_MSK))) && (--cnt)); - } - else - { - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); - } - - SYSCFG_LOCK(); - RTC_UNLOCK(); - MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, clock << RTC_CON_CKOS_POSS); - SET_BIT(RTC->CON, RTC_CON_CKOE_MSK); - RTC_LOCK(); - - return OK; + uint32_t cnt = 4000; + assert_param(IS_RTC_CLOCK_OUTPUT(clock)); + + SYSCFG_UNLOCK(); + + if (clock == RTC_CLOCK_OUTPUT_EXA_1) { + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2LCKN_MSK)) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL2RDY_MSK))) && (--cnt)); + } + else { + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + } + + SYSCFG_LOCK(); + RTC_UNLOCK(); + MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, clock << RTC_CON_CKOS_POSS); + SET_BIT(RTC->CON, RTC_CON_CKOE_MSK); + RTC_LOCK(); + + return OK; } /** @@ -999,11 +948,11 @@ ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock) */ void ald_rtc_cancel_clock_output(void) { - RTC_UNLOCK(); - CLEAR_BIT(RTC->CON, RTC_CON_CKOE_MSK); - RTC_LOCK(); + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_CKOE_MSK); + RTC_LOCK(); - return; + return; } /** * @} @@ -1042,18 +991,18 @@ void ald_rtc_cancel_clock_output(void) */ void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state) { - assert_param(IS_RTC_IT(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_RTC_IT(it)); + assert_param(IS_FUNC_STATE(state)); - RTC_UNLOCK(); + RTC_UNLOCK(); - if (state == ENABLE) - SET_BIT(RTC->IER, it); - else - CLEAR_BIT(RTC->IER, it); + if (state == ENABLE) + SET_BIT(RTC->IER, it); + else + CLEAR_BIT(RTC->IER, it); - RTC_LOCK(); - return; + RTC_LOCK(); + return; } /** @@ -1068,18 +1017,18 @@ void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state) */ void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state) { - assert_param(IS_RTC_ALARM(idx)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_RTC_ALARM(idx)); + assert_param(IS_FUNC_STATE(state)); - RTC_UNLOCK(); + RTC_UNLOCK(); - if (idx == RTC_ALARM_A) - MODIFY_REG(RTC->CON, RTC_CON_ALMAEN_MSK, state << RTC_CON_ALMAEN_POS); - else - MODIFY_REG(RTC->CON, RTC_CON_ALMBEN_MSK, state << RTC_CON_ALMBEN_POS); + if (idx == RTC_ALARM_A) + MODIFY_REG(RTC->CON, RTC_CON_ALMAEN_MSK, state << RTC_CON_ALMAEN_POS); + else + MODIFY_REG(RTC->CON, RTC_CON_ALMBEN_MSK, state << RTC_CON_ALMBEN_POS); - RTC_LOCK(); - return; + RTC_LOCK(); + return; } /** @@ -1090,25 +1039,24 @@ void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state) */ ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) { - uint32_t tick; + uint32_t tick; - assert_param(IS_FUNC_STATE(add_1s)); - assert_param(IS_SHIFT_SUB_SS(sub_ss)); + assert_param(IS_FUNC_STATE(add_1s)); + assert_param(IS_SHIFT_SUB_SS(sub_ss)); - RTC_UNLOCK(); - MODIFY_REG(RTC->SSECTR, RTC_SSECTR_TRIM_MSK, sub_ss << RTC_SSECTR_TRIM_POSS); - MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS); - RTC_LOCK(); + RTC_UNLOCK(); + MODIFY_REG(RTC->SSECTR, RTC_SSECTR_TRIM_MSK, sub_ss << RTC_SSECTR_TRIM_POSS); + MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS); + RTC_LOCK(); - tick = ald_get_tick(); + tick = ald_get_tick(); - while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK)) - { - if ((ald_get_tick() - tick) > RTC_TIMEOUT_VALUE) - return TIMEOUT; - } + while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK)) { + if ((ald_get_tick() - tick) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } - return OK; + return OK; } /** @@ -1118,26 +1066,26 @@ ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) */ void ald_rtc_set_cali(rtc_cali_t *config) { - assert_param(IS_RTC_CALI_FREQ(config->cali_freq)); - assert_param(IS_RTC_CALI_TC(config->tc)); - assert_param(IS_RTC_CALC_FREQ(config->calc_freq)); - assert_param(IS_RTC_CALI_CALC(config->calc)); - assert_param(IS_FUNC_STATE(config->acc)); - - RTC_UNLOCK(); - RTC_CALI_UNLOCK(); - - MODIFY_REG(RTC->CALCON, RTC_CALCON_CALP_MSK, config->cali_freq << RTC_CALCON_CALP_POSS); - MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, config->tc << RTC_CALCON_TCM_POSS); - MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, config->calc_freq << RTC_CALCON_TCP_POSS); - MODIFY_REG(RTC->CALCON, RTC_CALCON_ALG_MSK, config->calc << RTC_CALCON_ALG_POS); - MODIFY_REG(RTC->CALCON, RTC_CALCON_DCMACC_MSK, config->acc << RTC_CALCON_DCMACC_POS); - SET_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); - - RTC_CALI_LOCK(); - RTC_LOCK(); - - return; + assert_param(IS_RTC_CALI_FREQ(config->cali_freq)); + assert_param(IS_RTC_CALI_TC(config->tc)); + assert_param(IS_RTC_CALC_FREQ(config->calc_freq)); + assert_param(IS_RTC_CALI_CALC(config->calc)); + assert_param(IS_FUNC_STATE(config->acc)); + + RTC_UNLOCK(); + RTC_CALI_UNLOCK(); + + MODIFY_REG(RTC->CALCON, RTC_CALCON_CALP_MSK, config->cali_freq << RTC_CALCON_CALP_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, config->tc << RTC_CALCON_TCM_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, config->calc_freq << RTC_CALCON_TCP_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_ALG_MSK, config->calc << RTC_CALCON_ALG_POS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_DCMACC_MSK, config->acc << RTC_CALCON_DCMACC_POS); + SET_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); + + RTC_CALI_LOCK(); + RTC_LOCK(); + + return; } /** @@ -1146,11 +1094,11 @@ void ald_rtc_set_cali(rtc_cali_t *config) */ void ald_rtc_cancel_cali(void) { - RTC_CALI_UNLOCK(); - CLEAR_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); - RTC_CALI_LOCK(); + RTC_CALI_UNLOCK(); + CLEAR_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); + RTC_CALI_LOCK(); - return; + return; } /** @@ -1159,10 +1107,10 @@ void ald_rtc_cancel_cali(void) */ ald_status_t ald_rtc_get_cali_status(void) { - if (READ_BIT(RTC->CALCON, RTC_CALCON_ERR_MSK)) - return ERROR; - else - return OK; + if (READ_BIT(RTC->CALCON, RTC_CALCON_ERR_MSK)) + return ERROR; + else + return OK; } /** @@ -1172,11 +1120,11 @@ ald_status_t ald_rtc_get_cali_status(void) */ void ald_rtc_write_temp(uint16_t temp) { - RTC_CALI_UNLOCK(); - MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, temp << RTC_TEMPR_VAL_POSS); - RTC_CALI_LOCK(); + RTC_CALI_UNLOCK(); + MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, temp << RTC_TEMPR_VAL_POSS); + RTC_CALI_LOCK(); - return; + return; } /** @@ -1189,12 +1137,12 @@ void ald_rtc_write_temp(uint16_t temp) */ it_status_t ald_rtc_get_it_status(rtc_it_t it) { - assert_param(IS_RTC_IT(it)); + assert_param(IS_RTC_IT(it)); - if (READ_BIT(RTC->IER, it)) - return SET; + if (READ_BIT(RTC->IER, it)) + return SET; - return RESET; + return RESET; } /** @@ -1207,12 +1155,12 @@ it_status_t ald_rtc_get_it_status(rtc_it_t it) */ flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag) { - assert_param(IS_RTC_IF(flag)); + assert_param(IS_RTC_IF(flag)); - if (READ_BIT(RTC->IFR, flag)) - return SET; + if (READ_BIT(RTC->IFR, flag)) + return SET; - return RESET; + return RESET; } /** @brief Clear the specified RTC pending flag. @@ -1221,13 +1169,13 @@ flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag) */ void ald_rtc_clear_flag_status(rtc_flag_t flag) { - assert_param(IS_RTC_IF(flag)); + assert_param(IS_RTC_IF(flag)); - RTC_UNLOCK(); - WRITE_REG(RTC->IFCR, flag); - RTC_LOCK(); + RTC_UNLOCK(); + WRITE_REG(RTC->IFCR, flag); + RTC_LOCK(); - return; + return; } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_smartcard.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_smartcard.c index e7d1f466223fe4b7e4cbd7414e8d89912ede3827..2b3552ab77779cc33c4eff58e7e2a56250066e93 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_smartcard.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_smartcard.c @@ -122,9 +122,9 @@ static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hsmartcard); static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh); static void smartcard_set_config(smartcard_handle_t *hperh); #ifdef ALD_DMA - static void smartcard_dma_send_cplt(void *arg); - static void smartcard_dma_recv_cplt(void *arg); - static void smartcard_dma_error(void *arg); +static void smartcard_dma_send_cplt(void *arg); +static void smartcard_dma_recv_cplt(void *arg); +static void smartcard_dma_error(void *arg); #endif static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout); /** @@ -204,33 +204,33 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t */ ald_status_t ald_smartcard_init(smartcard_handle_t *hperh) { - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); - assert_param(IS_USART_PARITY(hperh->init.parity)); - assert_param(IS_USART(hperh->perh)); - assert_param(IS_FUNC_STATE(hperh->init.nack)); - assert_param(IS_SMARTCARD_PRESCALER(hperh->init.prescaler)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_USART_PARITY(hperh->init.parity)); + assert_param(IS_USART(hperh->perh)); + assert_param(IS_FUNC_STATE(hperh->init.nack)); + assert_param(IS_SMARTCARD_PRESCALER(hperh->init.prescaler)); - if (hperh->state == SMARTCARD_STATE_RESET) - hperh->lock = UNLOCK; + if (hperh->state == SMARTCARD_STATE_RESET) + hperh->lock = UNLOCK; - hperh->state = SMARTCARD_STATE_BUSY; - SMARTCARD_DISABLE(hperh); + hperh->state = SMARTCARD_STATE_BUSY; + SMARTCARD_DISABLE(hperh); - MODIFY_REG(hperh->perh->GP, USART_GP_PSC_MSK, hperh->init.prescaler << USART_GP_PSC_POSS); - MODIFY_REG(hperh->perh->GP, USART_GP_GTVAL_MSK, hperh->init.guard_time << USART_GP_GTVAL_POSS); - smartcard_set_config(hperh); + MODIFY_REG(hperh->perh->GP, USART_GP_PSC_MSK, hperh->init.prescaler << USART_GP_PSC_POSS); + MODIFY_REG(hperh->perh->GP, USART_GP_GTVAL_MSK, hperh->init.guard_time << USART_GP_GTVAL_POSS); + smartcard_set_config(hperh); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - SMARTCARD_ENABLE(hperh); - MODIFY_REG(hperh->perh->CON2, USART_CON2_NACK_MSK, hperh->init.nack << USART_CON2_NACK_POS); - SET_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + SMARTCARD_ENABLE(hperh); + MODIFY_REG(hperh->perh->CON2, USART_CON2_NACK_MSK, hperh->init.nack << USART_CON2_NACK_POS); + SET_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - hperh->err_code = SMARTCARD_ERROR_NONE; - hperh->state = SMARTCARD_STATE_READY; - return OK; + hperh->err_code = SMARTCARD_ERROR_NONE; + hperh->state = SMARTCARD_STATE_READY; + return OK; } /** @@ -241,22 +241,22 @@ ald_status_t ald_smartcard_init(smartcard_handle_t *hperh) */ ald_status_t ald_smartcard_reset(smartcard_handle_t *hperh) { - assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART(hperh->perh)); - hperh->state = SMARTCARD_STATE_BUSY; - SMARTCARD_DISABLE(hperh); + hperh->state = SMARTCARD_STATE_BUSY; + SMARTCARD_DISABLE(hperh); - WRITE_REG(hperh->perh->CON0, 0x0); - WRITE_REG(hperh->perh->CON1, 0x0); - WRITE_REG(hperh->perh->CON2, 0x0); - WRITE_REG(hperh->perh->BAUDCON, 0x0); - WRITE_REG(hperh->perh->GP, 0x0); + WRITE_REG(hperh->perh->CON0, 0x0); + WRITE_REG(hperh->perh->CON1, 0x0); + WRITE_REG(hperh->perh->CON2, 0x0); + WRITE_REG(hperh->perh->BAUDCON, 0x0); + WRITE_REG(hperh->perh->GP, 0x0); - hperh->err_code = SMARTCARD_ERROR_NONE; - hperh->state = SMARTCARD_STATE_RESET; - __UNLOCK(hperh); + hperh->err_code = SMARTCARD_ERROR_NONE; + hperh->state = SMARTCARD_STATE_RESET; + __UNLOCK(hperh); - return OK; + return OK; } /** * @} @@ -322,42 +322,38 @@ ald_status_t ald_smartcard_reset(smartcard_handle_t *hperh) */ ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - hperh->err_code = SMARTCARD_ERROR_NONE; - SET_BIT(hperh->state, USART_STATE_TX_MASK); - - hperh->tx_size = size; - hperh->tx_count = size; - - while (hperh->tx_count-- > 0) - { - if (smartcard_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) - { - hperh->state = SMARTCARD_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - WRITE_REG(hperh->perh->DATA, *buf++); - } - - if (smartcard_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) - { - hperh->state = SMARTCARD_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); - __UNLOCK(hperh); - - return OK; + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = SMARTCARD_ERROR_NONE; + SET_BIT(hperh->state, USART_STATE_TX_MASK); + + hperh->tx_size = size; + hperh->tx_count = size; + + while (hperh->tx_count-- > 0) { + if (smartcard_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { + hperh->state = SMARTCARD_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + WRITE_REG(hperh->perh->DATA, *buf++); + } + + if (smartcard_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) { + hperh->state = SMARTCARD_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); + __UNLOCK(hperh); + + return OK; } /** @@ -371,35 +367,32 @@ ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_ */ ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) - return BUSY; + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; - if ((buf == NULL) || (size == 0)) - return ERROR; + __LOCK(hperh); + hperh->err_code = SMARTCARD_ERROR_NONE; + SET_BIT(hperh->state, USART_STATE_RX_MASK); - __LOCK(hperh); - hperh->err_code = SMARTCARD_ERROR_NONE; - SET_BIT(hperh->state, USART_STATE_RX_MASK); + hperh->rx_size = size; + hperh->rx_count = size; - hperh->rx_size = size; - hperh->rx_count = size; + while (hperh->rx_count-- > 0) { + if (smartcard_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { + hperh->state = SMARTCARD_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } - while (hperh->rx_count-- > 0) - { - if (smartcard_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) - { - hperh->state = SMARTCARD_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } + *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } - *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } + __UNLOCK(hperh); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - __UNLOCK(hperh); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - - return OK; + return OK; } /** @@ -412,25 +405,24 @@ ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_ */ ald_status_t ald_smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) { - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_TX_MASK); + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_TX_MASK); - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = SMARTCARD_ERROR_NONE; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = SMARTCARD_ERROR_NONE; - __UNLOCK(hperh); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, ENABLE); + __UNLOCK(hperh); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, ENABLE); - return OK; + return OK; } /** @@ -443,26 +435,25 @@ ald_status_t ald_smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, u */ ald_status_t ald_smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) { - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = SMARTCARD_ERROR_NONE; + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = SMARTCARD_ERROR_NONE; - __UNLOCK(hperh); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, ENABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); + __UNLOCK(hperh); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); - return OK; + return OK; } #ifdef ALD_DMA @@ -477,44 +468,43 @@ ald_status_t ald_smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, u */ ald_status_t ald_smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_TX_MASK); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = SMARTCARD_ERROR_NONE; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = smartcard_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = smartcard_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmatx); - - ald_usart_clear_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); - __UNLOCK(hperh); - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, ENABLE); - - return OK; + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_TX_MASK); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = SMARTCARD_ERROR_NONE; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = smartcard_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = smartcard_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + ald_usart_clear_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); + __UNLOCK(hperh); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, ENABLE); + + return OK; } /** @@ -529,43 +519,42 @@ ald_status_t ald_smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, */ ald_status_t ald_smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = SMARTCARD_ERROR_NONE; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = smartcard_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = smartcard_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmarx); - - __UNLOCK(hperh); - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, ENABLE); - - return OK; + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = SMARTCARD_ERROR_NONE; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = smartcard_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = smartcard_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + __UNLOCK(hperh); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, ENABLE); + + return OK; } #endif @@ -577,65 +566,57 @@ ald_status_t ald_smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, */ void ald_smartcard_irq_handler(smartcard_handle_t *hperh) { - uint32_t flag; - uint32_t source; - - /* Handle parity error */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_PE); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_PE); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= SMARTCARD_ERROR_PE; - - /* Handle frame error */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_FE); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_ERR); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= SMARTCARD_ERROR_FE; - - /* Handle noise error */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_NE); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= SMARTCARD_ERROR_NE; - - /* Handle overrun error */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_ORE); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= SMARTCARD_ERROR_ORE; - - /* Handle receive */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_RXNE); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_RXNE); - - if ((flag != RESET) && (source != RESET)) - __smartcard_recv_by_it(hperh); - - /* Handle transmit */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TXE); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TXE); - - if ((flag != RESET) && (source != RESET)) - __smartcard_send_by_it(hperh); - - /* Handle transmit complete */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TC); - - if ((flag != RESET) && (source != RESET)) - __smartcard_end_send_by_it(hperh); - - /* Handle error */ - if (hperh->err_code != SMARTCARD_ERROR_NONE) - { - USART_CLEAR_PEFLAG(hperh); - hperh->state = SMARTCARD_STATE_READY; - - if (hperh->error_cbk) - hperh->error_cbk(hperh); - } + uint32_t flag; + uint32_t source; + + /* Handle parity error */ + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_PE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_PE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= SMARTCARD_ERROR_PE; + + /* Handle frame error */ + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_FE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_ERR); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= SMARTCARD_ERROR_FE; + + /* Handle noise error */ + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_NE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= SMARTCARD_ERROR_NE; + + /* Handle overrun error */ + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_ORE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= SMARTCARD_ERROR_ORE; + + /* Handle receive */ + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_RXNE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) + __smartcard_recv_by_it(hperh); + + /* Handle transmit */ + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TXE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) + __smartcard_send_by_it(hperh); + + /* Handle transmit complete */ + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TC); + if ((flag != RESET) && (source != RESET)) + __smartcard_end_send_by_it(hperh); + + /* Handle error */ + if (hperh->err_code != SMARTCARD_ERROR_NONE) { + USART_CLEAR_PEFLAG(hperh); + hperh->state = SMARTCARD_STATE_READY; + + if (hperh->error_cbk) + hperh->error_cbk(hperh); + } } /** * @} @@ -668,7 +649,7 @@ void ald_smartcard_irq_handler(smartcard_handle_t *hperh) */ smartcard_state_t ald_smartcard_get_state(smartcard_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** @@ -679,7 +660,7 @@ smartcard_state_t ald_smartcard_get_state(smartcard_handle_t *hperh) */ uint32_t ald_smartcard_get_error(smartcard_handle_t *hperh) { - return hperh->err_code; + return hperh->err_code; } /** @@ -704,13 +685,13 @@ uint32_t ald_smartcard_get_error(smartcard_handle_t *hperh) */ static void smartcard_dma_send_cplt(void *arg) { - smartcard_handle_t *hperh = (smartcard_handle_t *)arg; + smartcard_handle_t* hperh = ( smartcard_handle_t *)arg; - hperh->tx_count = 0; - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); + hperh->tx_count = 0; + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); - return; + return; } /** @@ -721,16 +702,16 @@ static void smartcard_dma_send_cplt(void *arg) */ static void smartcard_dma_recv_cplt(void *arg) { - smartcard_handle_t *hperh = (smartcard_handle_t *)arg; + smartcard_handle_t* hperh = ( smartcard_handle_t* )arg; - hperh->rx_count = 0; - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + hperh->rx_count = 0; + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); - return; + return; } /** @@ -741,20 +722,20 @@ static void smartcard_dma_recv_cplt(void *arg) */ static void smartcard_dma_error(void *arg) { - smartcard_handle_t *hperh = (smartcard_handle_t *)arg; + smartcard_handle_t* hperh = ( smartcard_handle_t* )arg; - hperh->rx_count = 0; - hperh->tx_count = 0; - hperh->err_code = SMARTCARD_ERROR_DMA; - hperh->state = SMARTCARD_STATE_READY; + hperh->rx_count = 0; + hperh->tx_count = 0; + hperh->err_code = SMARTCARD_ERROR_DMA; + hperh->state = SMARTCARD_STATE_READY; - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); - if (hperh->error_cbk) - hperh->error_cbk(hperh); + if (hperh->error_cbk) + hperh->error_cbk(hperh); - return; + return; } #endif @@ -769,27 +750,25 @@ static void smartcard_dma_error(void *arg) */ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout) { - uint32_t tick; + uint32_t tick; - if (timeout == 0) - return OK; + if (timeout == 0) + return OK; - tick = ald_get_tick(); + tick = ald_get_tick(); - while ((ald_usart_get_flag_status((usart_handle_t *)hperh, flag)) != status) - { - if (((ald_get_tick()) - tick) > timeout) - { - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + while ((ald_usart_get_flag_status((usart_handle_t *)hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) { + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); - return TIMEOUT; - } - } + return TIMEOUT; + } + } - return OK; + return OK; } /** @@ -802,18 +781,17 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t */ static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh) { - if ((hperh->state != SMARTCARD_STATE_BUSY_TX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX)) - return BUSY; + if ((hperh->state != SMARTCARD_STATE_BUSY_TX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX)) + return BUSY; - WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); + WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); - if (--hperh->tx_count == 0) - { - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); - } + if (--hperh->tx_count == 0) { + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); + } - return OK; + return OK; } @@ -825,16 +803,16 @@ static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh) */ static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hperh) { - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); - if (hperh->state == SMARTCARD_STATE_READY) - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + if (hperh->state == SMARTCARD_STATE_READY) + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); - if (hperh->tx_cplt_cbk) - hperh->tx_cplt_cbk(hperh); + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); - return OK; + return OK; } @@ -846,23 +824,22 @@ static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hperh) */ static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh) { - if ((hperh->state != SMARTCARD_STATE_BUSY_RX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX)) - return BUSY; + if ((hperh->state != SMARTCARD_STATE_BUSY_RX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX)) + return BUSY; - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - if (--hperh->rx_count == 0) - { - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + if (--hperh->rx_count == 0) { + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - } + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } - return OK; + return OK; } /** @@ -873,68 +850,65 @@ static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh) */ static void smartcard_set_config(smartcard_handle_t *hperh) { - uint32_t tmp; - uint32_t integer; - uint32_t fractional; - - /* Check the parameters */ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_BAUDRATE(hperh->init.baud)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); - assert_param(IS_USART_PARITY(hperh->init.parity)); - assert_param(IS_USART_MODE(hperh->init.mode)); - - MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS); - tmp = READ_REG(hperh->perh->CON0); - MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS); - - if (hperh->init.parity == USART_PARITY_NONE) - CLEAR_BIT(tmp, USART_CON0_PEN_MSK); - else - SET_BIT(tmp, USART_CON0_PEN_MSK); - - if (hperh->init.parity == USART_PARITY_ODD) - SET_BIT(tmp, USART_CON0_PSEL_MSK); - else - CLEAR_BIT(tmp, USART_CON0_PSEL_MSK); - - WRITE_REG(hperh->perh->CON0, tmp); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RTSEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_CTSEN_MSK); - MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS); - MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS); - tmp = READ_REG(hperh->perh->CON1); - SET_BIT(tmp, USART_CON1_SCKEN_MSK); - MODIFY_REG(tmp, USART_CON1_SCKPOL_MSK, hperh->init.polarity << USART_CON1_SCKPOL_POS); - MODIFY_REG(tmp, USART_CON1_SCKPHA_MSK, hperh->init.phase << USART_CON1_SCKPHA_POS); - MODIFY_REG(tmp, USART_CON1_LBCP_MSK, hperh->init.last_bit << USART_CON1_LBCP_POS); - - /* Determine the integer part */ - if (READ_BIT(hperh->perh->CON0, (1 << 15))) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); - } - else - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); - } - - tmp = (integer / 100) << 4; - - /* Determine the fractional part */ - fractional = integer - (100 * (tmp >> 4)); - - /* Implement the fractional part in the register */ - if (READ_BIT(hperh->perh->CON0, (1 << 15))) - tmp |= ((((fractional * 8) + 50) / 100)) & ((uint8_t)0x07); - else - tmp |= ((((fractional * 16) + 50) / 100)) & ((uint8_t)0x0F); - - WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp); - return; + uint32_t tmp; + uint32_t integer; + uint32_t fractional; + + /* Check the parameters */ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_BAUDRATE(hperh->init.baud)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_USART_PARITY(hperh->init.parity)); + assert_param(IS_USART_MODE(hperh->init.mode)); + + MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS); + tmp = READ_REG(hperh->perh->CON0); + MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS); + + if (hperh->init.parity == USART_PARITY_NONE) + CLEAR_BIT(tmp, USART_CON0_PEN_MSK); + else + SET_BIT(tmp, USART_CON0_PEN_MSK); + + if (hperh->init.parity == USART_PARITY_ODD) + SET_BIT(tmp, USART_CON0_PSEL_MSK); + else + CLEAR_BIT(tmp, USART_CON0_PSEL_MSK); + + WRITE_REG(hperh->perh->CON0, tmp); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RTSEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_CTSEN_MSK); + MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS); + MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS); + tmp = READ_REG(hperh->perh->CON1); + SET_BIT(tmp, USART_CON1_SCKEN_MSK); + MODIFY_REG(tmp, USART_CON1_SCKPOL_MSK, hperh->init.polarity << USART_CON1_SCKPOL_POS); + MODIFY_REG(tmp, USART_CON1_SCKPHA_MSK, hperh->init.phase << USART_CON1_SCKPHA_POS); + MODIFY_REG(tmp, USART_CON1_LBCP_MSK, hperh->init.last_bit << USART_CON1_LBCP_POS); + + /* Determine the integer part */ + if (READ_BIT(hperh->perh->CON0, (1 << 15))) { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); + } + else { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); + } + tmp = (integer / 100) << 4; + + /* Determine the fractional part */ + fractional = integer - (100 * (tmp >> 4)); + + /* Implement the fractional part in the register */ + if (READ_BIT(hperh->perh->CON0, (1 << 15))) + tmp |= ((((fractional * 8) + 50) / 100)) & ((uint8_t)0x07); + else + tmp |= ((((fractional * 16) + 50) / 100)) & ((uint8_t)0x0F); + + WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp); + return; } /** diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_spi.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_spi.c index 9ab99c71a543b0a0d5c353ce8e1850b5d80c29d2..f756f6785df8d12fcb748e9b624d22e96cbc0287 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_spi.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_spi.c @@ -78,10 +78,10 @@ static void __spi_send_by_it(spi_handle_t *hperh); static void __spi_recv_by_it(spi_handle_t *hperh); static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); #ifdef ALD_DMA - static void spi_dma_send_cplt(void *arg); - static void spi_dma_recv_cplt(void *arg); - static void spi_dma_send_recv_cplt(void *arg); - static void spi_dma_error(void *arg); +static void spi_dma_send_cplt(void *arg); +static void spi_dma_recv_cplt(void *arg); +static void spi_dma_send_recv_cplt(void *arg); +static void spi_dma_error(void *arg); #endif /** * @} @@ -131,14 +131,14 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); */ void ald_spi_reset(spi_handle_t *hperh) { - hperh->perh->CON1 = 0x0; - hperh->perh->CON2 = 0x0; - hperh->perh->CRCPOLY = 0x00000007; + hperh->perh->CON1 = 0x0; + hperh->perh->CON2 = 0x0; + hperh->perh->CRCPOLY = 0x00000007; - SPI_RESET_HANDLE_STATE(hperh); - __UNLOCK(hperh); + SPI_RESET_HANDLE_STATE(hperh); + __UNLOCK(hperh); - return; + return; } /** @@ -150,62 +150,59 @@ void ald_spi_reset(spi_handle_t *hperh) */ ald_status_t ald_spi_init(spi_handle_t *hperh) { - uint32_t tmp = 0; - - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_MODE(hperh->init.mode)); - assert_param(IS_SPI_DIRECTION(hperh->init.dir)); - assert_param(IS_SPI_BAUD(hperh->init.baud)); - assert_param(IS_FUNC_STATE(hperh->init.first_bit)); - assert_param(IS_FUNC_STATE(hperh->init.ss_en)); - assert_param(IS_FUNC_STATE(hperh->init.crc_calc)); - assert_param(IS_SPI_DATASIZE(hperh->init.data_size)); - assert_param(IS_SPI_CPHA(hperh->init.phase)); - assert_param(IS_SPI_CPOL(hperh->init.polarity)); - - if (hperh == NULL) - return ERROR; - - ald_spi_reset(hperh); - - tmp = hperh->perh->CON1; - - if (hperh->init.mode == SPI_MODE_MASTER) - tmp |= 1 << SPI_CON1_SSOUT_POS; - - tmp |= ((hperh->init.phase << SPI_CON1_CPHA_POS) | (hperh->init.polarity << SPI_CON1_CPOL_POS) | - (hperh->init.baud << SPI_CON1_BAUD_POSS) | (hperh->init.data_size << SPI_CON1_FLEN_POS) | - (hperh->init.mode << SPI_CON1_MSTREN_POS) | (hperh->init.ss_en << SPI_CON1_SSEN_POS) | - (hperh->init.first_bit << SPI_CON1_LSBFST_POS)); - - hperh->perh->CON1 = tmp; - - if (hperh->init.dir == SPI_DIRECTION_2LINES) - { - CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); - CLEAR_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); - } - else if (hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) - { - CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); - SET_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); - } - else - { - SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); - } - - /* configure CRC */ - hperh->perh->CON1 |= (hperh->init.crc_calc << SPI_CON1_CRCEN_POS); - hperh->perh->CRCPOLY = hperh->init.crc_poly; - - hperh->err_code = SPI_ERROR_NONE; - hperh->state = SPI_STATE_READY; - - if (hperh->init.dir == SPI_DIRECTION_2LINES) - SPI_ENABLE(hperh); - - return OK; + uint32_t tmp = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_MODE(hperh->init.mode)); + assert_param(IS_SPI_DIRECTION(hperh->init.dir)); + assert_param(IS_SPI_BAUD(hperh->init.baud)); + assert_param(IS_SPI_FIRSTBIT(hperh->init.first_bit)); + assert_param(IS_FUNC_STATE(hperh->init.ss_en)); + assert_param(IS_FUNC_STATE(hperh->init.crc_calc)); + assert_param(IS_SPI_DATASIZE(hperh->init.data_size)); + assert_param(IS_SPI_CPHA(hperh->init.phase)); + assert_param(IS_SPI_CPOL(hperh->init.polarity)); + + ald_spi_reset(hperh); + + tmp = hperh->perh->CON1; + + if (hperh->init.mode == SPI_MODE_MASTER) + tmp |= 1 << SPI_CON1_SSOUT_POS; + + tmp |= ((hperh->init.phase << SPI_CON1_CPHA_POS) | (hperh->init.polarity << SPI_CON1_CPOL_POS) | + (hperh->init.baud << SPI_CON1_BAUD_POSS) | (hperh->init.data_size << SPI_CON1_FLEN_POS) | + (hperh->init.mode << SPI_CON1_MSTREN_POS) | (hperh->init.ss_en << SPI_CON1_SSEN_POS) | + (hperh->init.first_bit << SPI_CON1_LSBFST_POS)); + + hperh->perh->CON1 = tmp; + + if (hperh->init.dir == SPI_DIRECTION_2LINES) { + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); + } + else if (hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) { + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + SET_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); + } + else { + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + } + + /* configure CRC */ + hperh->perh->CON1 |= (hperh->init.crc_calc << SPI_CON1_CRCEN_POS); + hperh->perh->CRCPOLY = hperh->init.crc_poly; + + hperh->err_code = SPI_ERROR_NONE; + hperh->state = SPI_STATE_READY; + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + SPI_ENABLE(hperh); + + return OK; } /** * @} @@ -253,20 +250,16 @@ ald_status_t ald_spi_init(spi_handle_t *hperh) */ int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data) { - uint16_t cnt = 2000, temp; + uint16_t cnt = 2000, temp; - hperh->perh->DATA = data; + hperh->perh->DATA = data; + while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); + cnt = 2000; + while ((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0 && (--cnt)); + temp = hperh->perh->DATA; + UNUSED(temp); - while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); - - cnt = 2000; - - while ((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0 && (--cnt)); - - temp = hperh->perh->DATA; - UNUSED(temp); - - return cnt == 0 ? -1 : 0; + return cnt == 0 ? -1 : 0; } /** @@ -279,13 +272,12 @@ int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data) */ int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data) { - uint16_t cnt = 2000; + uint16_t cnt = 2000; - hperh->perh->DATA = data; + hperh->perh->DATA = data; + while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); - while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); - - return cnt == 0 ? -1 : 0; + return cnt == 0 ? -1 : 0; } /** @@ -295,20 +287,16 @@ int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data) */ uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh) { - uint16_t cnt = 2000; - - if (hperh->init.mode == SPI_MODE_MASTER) - { - hperh->perh->DATA = 0xFF; - - while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); - } - - cnt = 2000; + uint16_t cnt = 2000; - while (((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0) && (--cnt)); + if (hperh->init.mode == SPI_MODE_MASTER) { + hperh->perh->DATA = 0xFF; + while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); + } - return (uint8_t)hperh->perh->DATA; + cnt = 2000; + while (((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0) && (--cnt)); + return (uint8_t)hperh->perh->DATA; } /** @@ -321,98 +309,87 @@ uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh) */ ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - - hperh->state = SPI_STATE_BUSY_TX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = NULL; - hperh->rx_size = 0; - hperh->rx_count = 0; - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if (hperh->init.dir == SPI_DIRECTION_1LINE) - SPI_1LINE_TX(hperh); - - if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) - SPI_ENABLE(hperh); - - if ((hperh->init.mode == SPI_MODE_SLAVER) || (hperh->tx_count == 1)) - { - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; - } - else - { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; - } - } - - while (hperh->tx_count > 0) - { - if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; - } - else - { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; - } - } - - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - - if ((spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) - || (spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.dir == SPI_DIRECTION_2LINES) - ald_spi_clear_flag_status(hperh, SPI_IF_OVE); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - - return OK; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + + hperh->state = SPI_STATE_BUSY_TX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + if (hperh->init.dir == SPI_DIRECTION_1LINE) + SPI_1LINE_TX(hperh); + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + SPI_ENABLE(hperh); + + if ((hperh->init.mode == SPI_MODE_SLAVER) || (hperh->tx_count == 1)) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + } + + while (hperh->tx_count > 0) { + if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + } + + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + + if ((spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) + || (spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return OK; } /** @@ -425,124 +402,111 @@ ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint */ ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - uint16_t temp; - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_RX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) - SPI_1LINE_RX(hperh); - - if ((hperh->init.mode == SPI_MODE_MASTER) && (hperh->init.dir == SPI_DIRECTION_2LINES)) - { - __UNLOCK(hperh); - hperh->state = SPI_STATE_READY; - return ald_spi_send_recv(hperh, buf, buf, size, timeout); - } - - if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) - SPI_ENABLE(hperh); - - while (hperh->rx_count > 1) - { - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else - { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; - --hperh->rx_count; - } - } - - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else - { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; - --hperh->rx_count; - } - - if (hperh->init.crc_calc) - { - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - temp = hperh->perh->DATA; - UNUSED(temp); - } - - if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) - { - hperh->err_code |= SPI_ERROR_CRC; - SPI_CRC_RESET(hperh); - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return ERROR; - } - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - - return OK; + uint16_t temp; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) + SPI_1LINE_RX(hperh); + + if ((hperh->init.mode == SPI_MODE_MASTER) && (hperh->init.dir == SPI_DIRECTION_2LINES)) { + __UNLOCK(hperh); + hperh->state = SPI_STATE_READY; + return ald_spi_send_recv(hperh, buf, buf, size, timeout); + } + + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); + + while (hperh->rx_count > 1) { + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + --hperh->rx_count; + } + + if (hperh->init.crc_calc) { + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= SPI_ERROR_CRC; + SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return ERROR; + } + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return OK; } /** @@ -556,199 +520,175 @@ ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint */ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) { - uint16_t temp; - - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - - if (hperh->init.dir != SPI_DIRECTION_2LINES) - return ERROR; - - if (tx_buf == NULL || rx_buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_TX_RX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->rx_count = size; - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if ((hperh->init.mode == SPI_MODE_SLAVER) || ((hperh->init.mode == SPI_MODE_SLAVER) && (hperh->tx_size == 1))) - { - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; - } - else - { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; - } - } - - if (hperh->tx_buf == 0) - { - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - - if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else - { - (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; - hperh->rx_buf += 2; - --hperh->rx_count; - } - } - - while (hperh->tx_count > 0) - { - if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; - } - else - { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; - } - - if ((hperh->tx_count == 0) && (hperh->init.crc_calc)) - SPI_CRCNEXT_ENABLE(hperh); - - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else - { - (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; - - hperh->rx_buf += 2; - --hperh->rx_count; - } - } - - if (hperh->init.mode == SPI_MODE_SLAVER) - { - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else - { - (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; - - hperh->rx_buf += 2; - --hperh->rx_count; - } - } - - if (hperh->init.crc_calc) - { - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - temp = hperh->perh->DATA; - UNUSED(temp); - } - - if ((spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) - { - hperh->err_code |= SPI_ERROR_CRC; - SPI_CRC_RESET(hperh); - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - - return ERROR; - } - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - - return OK; + uint16_t temp; + + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (hperh->init.dir != SPI_DIRECTION_2LINES) + return ERROR; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if ((hperh->init.mode == SPI_MODE_SLAVER) || ((hperh->init.mode == SPI_MODE_SLAVER) && (hperh->tx_size == 1))) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + } + + if (hperh->tx_count == 0) { + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + + if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + while (hperh->tx_count > 0) { + if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + + if ((hperh->tx_count == 0) && (hperh->init.crc_calc)) + SPI_CRCNEXT_ENABLE(hperh); + + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; + + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + if (hperh->init.mode == SPI_MODE_SLAVER) { + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; + + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + if (hperh->init.crc_calc) { + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if ((spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= SPI_ERROR_CRC; + SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return ERROR; + } + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return OK; } /** @@ -760,46 +700,43 @@ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx */ ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) { - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_TX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = NULL; - hperh->rx_size = 0; - hperh->rx_count = 0; - __UNLOCK(hperh); - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if (hperh->init.dir == SPI_DIRECTION_1LINE) - SPI_1LINE_TX(hperh); - - if (hperh->init.dir == SPI_DIRECTION_2LINES) - { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); - } - else - { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); - } - - if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) - SPI_ENABLE(hperh); - - return OK; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + __UNLOCK(hperh); + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->init.dir == SPI_DIRECTION_1LINE) + SPI_1LINE_TX(hperh); + + if (hperh->init.dir == SPI_DIRECTION_2LINES) { + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + } + else { + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); + } + + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + SPI_ENABLE(hperh); + + return OK; } /** @@ -811,42 +748,40 @@ ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size */ ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) { - assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI(hperh->perh)); - if (hperh->state != SPI_STATE_READY) - return BUSY; + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) + return ERROR; /* Please call ald_spi_send_recv_by_it() */ - if (buf == NULL || size == 0) - return ERROR; + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; - if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) - return ERROR; /* Please call ald_spi_send_recv_by_it() */ + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + __UNLOCK(hperh); - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_RX; - hperh->err_code = SPI_ERROR_NONE; + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) + SPI_1LINE_RX(hperh); - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; - __UNLOCK(hperh); + if (hperh->init.crc_calc == ENABLE) + SPI_CRC_RESET(hperh); - if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) - SPI_1LINE_RX(hperh); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); - if (hperh->init.crc_calc == ENABLE) - SPI_CRC_RESET(hperh); + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); - - if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) - SPI_ENABLE(hperh); - - return OK; + return OK; } /** @@ -860,34 +795,33 @@ ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size */ ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) { - assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI(hperh->perh)); - if (hperh->state != SPI_STATE_READY) - return BUSY; + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; - if (tx_buf == NULL || rx_buf == NULL || size == 0) - return ERROR; + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX_RX; + hperh->err_code = SPI_ERROR_NONE; - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_TX_RX; - hperh->err_code = SPI_ERROR_NONE; + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + __UNLOCK(hperh); - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->rx_count = size; - __UNLOCK(hperh); + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); - - return OK; + return OK; } #ifdef ALD_DMA @@ -901,59 +835,57 @@ ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8 */ ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_TX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = NULL; - hperh->rx_size = 0; - hperh->rx_count = 0; - - if (hperh->init.dir == SPI_DIRECTION_1LINE) - SPI_1LINE_TX(hperh); - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.cplt_cbk = spi_dma_send_cplt; - hperh->hdmatx.err_arg = (void *)hperh; - hperh->hdmatx.err_cbk = spi_dma_error; - - /* Configure SPI DMA transmit */ - ald_dma_config_struct(&(hperh->hdmatx.config)); - hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&(hperh->hdmatx)); - - __UNLOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); - - if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) - SPI_ENABLE(hperh); - - return OK; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + if (hperh->init.dir == SPI_DIRECTION_1LINE) + SPI_1LINE_TX(hperh); + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.cplt_cbk = spi_dma_send_cplt; + hperh->hdmatx.err_arg = (void *)hperh; + hperh->hdmatx.err_cbk = spi_dma_error; + + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&(hperh->hdmatx)); + + __UNLOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + SPI_ENABLE(hperh); + + return OK; } /** @@ -966,65 +898,61 @@ ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t siz */ ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_RX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; - - if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) - SPI_1LINE_RX(hperh); - - if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) - { - __UNLOCK(hperh); - return ERROR; /* Please use ald_spi_send_recv_by_dma() */ - } - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.cplt_cbk = spi_dma_recv_cplt; - hperh->hdmarx.err_arg = (void *)hperh; - hperh->hdmarx.err_cbk = spi_dma_error; - - /* Configure DMA Receive */ - ald_dma_config_struct(&(hperh->hdmarx.config)); - hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; - hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&(hperh->hdmarx)); - - __UNLOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); - - if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) - SPI_ENABLE(hperh); - - return OK; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) + SPI_1LINE_RX(hperh); + if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) { + __UNLOCK(hperh); + return ERROR; /* Please use ald_spi_send_recv_by_dma() */ + } + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.cplt_cbk = spi_dma_recv_cplt; + hperh->hdmarx.err_arg = (void *)hperh; + hperh->hdmarx.err_cbk = spi_dma_error; + + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; + hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&(hperh->hdmarx)); + + __UNLOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); + + return OK; } /** @@ -1039,74 +967,72 @@ ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t siz */ ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) { - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY && hperh->state != SPI_STATE_BUSY_RX) - return BUSY; - - if (tx_buf == NULL || rx_buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_RX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->rx_count = size; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmatx.cplt_arg = NULL; - hperh->hdmatx.cplt_cbk = NULL; - hperh->hdmatx.err_arg = (void *)hperh; - hperh->hdmatx.err_cbk = spi_dma_error; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.cplt_cbk = spi_dma_send_recv_cplt; - hperh->hdmarx.err_arg = (void *)hperh; - hperh->hdmarx.err_cbk = spi_dma_error; - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - /* Configure SPI DMA transmit */ - ald_dma_config_struct(&(hperh->hdmatx.config)); - hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; - hperh->hdmatx.config.src = (void *)tx_buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; - hperh->hdmatx.config.channel = tx_channel; - ald_dma_config_basic(&(hperh->hdmatx)); - - /* Configure DMA Receive */ - ald_dma_config_struct(&(hperh->hdmarx.config)); - hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)rx_buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; - hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; - hperh->hdmarx.config.channel = rx_channel; - ald_dma_config_basic(&(hperh->hdmarx)); - - __UNLOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); - - return OK; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY && hperh->state != SPI_STATE_BUSY_RX) + return BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmatx.cplt_arg = NULL; + hperh->hdmatx.cplt_cbk = NULL; + hperh->hdmatx.err_arg = (void *)hperh; + hperh->hdmatx.err_cbk = spi_dma_error; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.cplt_cbk = spi_dma_send_recv_cplt; + hperh->hdmarx.err_arg = (void *)hperh; + hperh->hdmarx.err_cbk = spi_dma_error; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)tx_buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = tx_channel; + ald_dma_config_basic(&(hperh->hdmatx)); + + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)rx_buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; + hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.channel = rx_channel; + ald_dma_config_basic(&(hperh->hdmarx)); + + __UNLOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + + return OK; } /** @@ -1116,14 +1042,14 @@ ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint */ ald_status_t ald_spi_dma_pause(spi_handle_t *hperh) { - assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI(hperh->perh)); - __LOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - __UNLOCK(hperh); + __LOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -1133,14 +1059,14 @@ ald_status_t ald_spi_dma_pause(spi_handle_t *hperh) */ ald_status_t ald_spi_dma_resume(spi_handle_t *hperh) { - assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI(hperh->perh)); - __LOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); - __UNLOCK(hperh); + __LOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -1150,15 +1076,15 @@ ald_status_t ald_spi_dma_resume(spi_handle_t *hperh) */ ald_status_t ald_spi_dma_stop(spi_handle_t *hperh) { - assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI(hperh->perh)); - __LOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - __UNLOCK(hperh); + __LOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); - hperh->state = SPI_STATE_READY; - return OK; + hperh->state = SPI_STATE_READY; + return OK; } #endif /** @@ -1193,66 +1119,65 @@ ald_status_t ald_spi_dma_stop(spi_handle_t *hperh) */ void ald_spi_irq_handler(spi_handle_t *hperh) { - if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX)) - { - if ((ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) - __spi_recv_by_it(hperh); - - if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) - __spi_send_by_it(hperh); - } - - else if (hperh->state == SPI_STATE_BUSY_TX_RX) - { - if (hperh->tx_size == hperh->tx_count) - { - if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) - __spi_send_recv_by_it(hperh, SPI_SR_TXBE); - } - else - { - if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET) - && (ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) - __spi_send_recv_by_it(hperh, SPI_SR_TXBE_RXBNE); - } - } - - if ((ald_spi_get_it_status(hperh, SPI_IT_ERR) != RESET)) - { - if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) - { - hperh->err_code |= SPI_ERROR_CRC; - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - } - - if (ald_spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) - { - hperh->err_code |= SPI_ERROR_MODF; - ald_spi_clear_flag_status(hperh, SPI_IF_MODF); - } - - if (ald_spi_get_flag_status(hperh, SPI_IF_OVE) != RESET) - { - if (hperh->state != SPI_STATE_BUSY_TX) - { - hperh->err_code |= SPI_ERROR_OVE; - ald_spi_clear_flag_status(hperh, SPI_IF_OVE); - } - } - - if (hperh->err_code != SPI_ERROR_NONE) - { - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); - hperh->state = SPI_STATE_READY; - - if (hperh->err_cbk) - hperh->err_cbk(hperh); - } - } - - return; + if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX)) { + if ((ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) + __spi_recv_by_it(hperh); + + if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) + __spi_send_by_it(hperh); + } + + else if (hperh->state == SPI_STATE_BUSY_TX_RX) { + if (hperh->tx_size == hperh->tx_count) { + if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_TXBE); + } + else { + if (hperh->init.mode == SPI_MODE_MASTER) { + if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET) + && (ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_TXBE_RXBNE); + } + else { + if ((ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_RXBNE); + + if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_TXBE); + } + + + } + } + + if ((ald_spi_get_it_status(hperh, SPI_IT_ERR) != RESET)) { + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) { + hperh->err_code |= SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + if (ald_spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) { + hperh->err_code |= SPI_ERROR_MODF; + ald_spi_clear_flag_status(hperh, SPI_IF_MODF); + } + if (ald_spi_get_flag_status(hperh, SPI_IF_OVE) != RESET) { + if ((hperh->state != SPI_STATE_BUSY_TX) && (hperh->state != SPI_STATE_READY)) { + hperh->err_code |= SPI_ERROR_OVE; + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); + } + } + + if (hperh->err_code != SPI_ERROR_NONE) { + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + } + + return; } /** @@ -1267,16 +1192,16 @@ void ald_spi_irq_handler(spi_handle_t *hperh) */ void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state) { - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_IT(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IT(it)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - hperh->perh->CON2 |= (uint32_t)it; - else - hperh->perh->CON2 &= ~((uint32_t)it); + if (state == ENABLE) + hperh->perh->CON2 |= (uint32_t)it; + else + hperh->perh->CON2 &= ~((uint32_t)it); - return; + return; } /** @@ -1288,15 +1213,15 @@ void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t stat */ void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) { - uint32_t tmp = 0; - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_BAUD(speed)); - - tmp = hperh->perh->CON1; - tmp &= ~(0x7 << SPI_CON1_BAUD_POSS); - tmp |= (speed << SPI_CON1_BAUD_POSS); - hperh->perh->CON1 = tmp; - return; + uint32_t tmp = 0; + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_BAUD(speed)); + + tmp = hperh->perh->CON1; + tmp &= ~(0x7U << SPI_CON1_BAUD_POSS); + tmp |= (speed << SPI_CON1_BAUD_POSS); + hperh->perh->CON1 = tmp; + return; } /** @@ -1311,26 +1236,24 @@ void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) */ void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state) { - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_DMA_REQ(req)); - assert_param(IS_FUNC_STATE(state)); - - if (state == ENABLE) - { - if (req == SPI_DMA_REQ_TX) - SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); - else - SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); - } - else - { - if (req == SPI_DMA_REQ_TX) - CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); - else - CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); - } - - return; + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) { + if (req == SPI_DMA_REQ_TX) + SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + else { + if (req == SPI_DMA_REQ_TX) + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + + return; } /** @brief Check whether the specified SPI state flag is set or not. @@ -1343,13 +1266,13 @@ void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t */ flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status) { - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_STATUS(status)); + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_STATUS(status)); - if (hperh->perh->STAT & status) - return SET; + if (hperh->perh->STAT & status) + return SET; - return RESET; + return RESET; } /** @@ -1363,13 +1286,13 @@ flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status) */ it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it) { - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_IT(it)); + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IT(it)); - if (hperh->perh->CON2 & it) - return SET; + if (hperh->perh->CON2 & it) + return SET; - return RESET; + return RESET; } /** @brief Check whether the specified SPI flag is set or not. @@ -1382,13 +1305,13 @@ it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it) */ flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag) { - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_IF(flag)); + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IF(flag)); - if (hperh->perh->STAT & flag) - return SET; + if (hperh->perh->STAT & flag) + return SET; - return RESET; + return RESET; } /** @brief Clear the specified SPI pending flags. @@ -1399,34 +1322,29 @@ flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag) */ void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) { - uint32_t temp; - - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_IF(flag)); - - if (flag == SPI_IF_CRCERR) - { - SET_BIT(hperh->perh->STAT, SPI_STAT_CRCERR_MSK); - return; - } - - if (flag == SPI_IF_OVE) - { - temp = hperh->perh->DATA; - temp = hperh->perh->STAT; - UNUSED(temp); - return; - } - - if (flag == SPI_IF_MODF) - { - temp = hperh->perh->STAT; - UNUSED(temp); - hperh->perh->CON1 = hperh->perh->CON1; - return; - } - - return; + uint32_t temp; + + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IF(flag)); + + if (flag == SPI_IF_CRCERR) { + SET_BIT(hperh->perh->STAT, SPI_STAT_CRCERR_MSK); + return; + } + if (flag == SPI_IF_OVE) { + temp = hperh->perh->DATA; + temp = hperh->perh->STAT; + UNUSED(temp); + return; + } + if (flag == SPI_IF_MODF) { + temp = hperh->perh->STAT; + UNUSED(temp); + hperh->perh->CON1 = hperh->perh->CON1; + return; + } + + return; } /** @@ -1439,22 +1357,20 @@ void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) */ static ald_status_t spi_wait_flag(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout) { - uint32_t tick = ald_get_tick(); - - assert_param(timeout > 0); - - while ((ald_spi_get_flag_status(hperh, flag)) != status) - { - if (((ald_get_tick()) - tick) > timeout) - { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); - return TIMEOUT; - } - } - - return OK; + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + while ((ald_spi_get_flag_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) { + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + return TIMEOUT; + } + } + + return OK; } /** @@ -1467,18 +1383,18 @@ static ald_status_t spi_wait_flag(spi_handle_t *hperh, spi_flag_t flag, flag_sta */ static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout) { - assert_param(timeout > 0); + assert_param(timeout > 0); - while (((ald_spi_get_flag_status(hperh, flag)) != status) && (--timeout)); + while (((ald_spi_get_flag_status(hperh, flag)) != status) && (--timeout)); - if (timeout) - return OK; + if (timeout) + return OK; - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); - return TIMEOUT; + return TIMEOUT; } /** @@ -1508,8 +1424,8 @@ static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag */ spi_state_t ald_spi_get_state(spi_handle_t *hperh) { - assert_param(IS_SPI(hperh->perh)); - return hperh->state; + assert_param(IS_SPI(hperh->perh)); + return hperh->state; } /** @@ -1519,8 +1435,8 @@ spi_state_t ald_spi_get_state(spi_handle_t *hperh) */ uint32_t ald_spi_get_error(spi_handle_t *hperh) { - assert_param(IS_SPI(hperh->perh)); - return hperh->err_code; + assert_param(IS_SPI(hperh->perh)); + return hperh->err_code; } /** * @} @@ -1542,48 +1458,43 @@ uint32_t ald_spi_get_error(spi_handle_t *hperh) */ static void __spi_send_by_it(spi_handle_t *hperh) { - if (hperh->tx_count == 0) - { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - hperh->state = SPI_STATE_READY; - - if (hperh->init.dir == SPI_DIRECTION_2LINES) - ald_spi_clear_flag_status(hperh, SPI_IF_OVE); - - if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) - { - if (hperh->err_cbk) - hperh->err_cbk(hperh); - - return; - } - - if (hperh->tx_cplt_cbk) - hperh->tx_cplt_cbk(hperh); - - return; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - } - else - { - hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; - hperh->tx_buf += 2; - } - - --hperh->tx_count; - - if (hperh->tx_count == 0) - { - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - } - - return; + if (hperh->tx_count == 0) { + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); + + if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else { + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + --hperh->tx_count; + + if (hperh->tx_count == 0) { + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + } + + return; } /** @@ -1593,51 +1504,45 @@ static void __spi_send_by_it(spi_handle_t *hperh) */ static void __spi_recv_by_it(spi_handle_t *hperh) { - uint16_t temp; - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - } - else - { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; - } - - --hperh->rx_count; - - if ((hperh->rx_count == 1) && (hperh->init.crc_calc)) - SPI_CRCNEXT_ENABLE(hperh); - - if (hperh->rx_count == 0) - { - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - hperh->state = SPI_STATE_READY; - - if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) - { - hperh->err_code |= SPI_ERROR_CRC; - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - - if (hperh->err_cbk) - hperh->err_cbk(hperh); - - return; - } - - if (hperh->init.crc_calc) - { - temp = hperh->perh->DATA; - UNUSED(temp); - } - - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - } - - return; + uint16_t temp; + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + --hperh->rx_count; + + if ((hperh->rx_count == 1) && (hperh->init.crc_calc)) + SPI_CRCNEXT_ENABLE(hperh); + + if (hperh->rx_count == 0) { + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + hperh->state = SPI_STATE_READY; + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->init.crc_calc) { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return; } /** @@ -1648,99 +1553,82 @@ static void __spi_recv_by_it(spi_handle_t *hperh) */ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) { - assert_param(IS_SPI_SR_STATUS(status)); - - if (hperh->rx_count != 0) - { - if ((status == SPI_SR_RXBNE) || (status == SPI_SR_TXBE_RXBNE)) - { - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - } - else - { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; - } - - --hperh->rx_count; - } - } - - if (hperh->tx_count != 0) - { - if ((status == SPI_SR_TXBE) || (status == SPI_SR_TXBE_RXBNE)) - { - if (hperh->tx_count == 1) - { - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - } - else - { - hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; - hperh->tx_buf += 2; - } - - --hperh->tx_count; - - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - } - else - { - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - } - else - { - hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; - hperh->tx_buf += 2; - } - - if (--hperh->tx_count == 0) - { - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - } - } - } - } - - if (hperh->rx_count == 0) - { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); - hperh->state = SPI_STATE_READY; - - if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) - { - hperh->err_code |= SPI_ERROR_CRC; - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - - if (hperh->err_cbk) - hperh->err_cbk(hperh); - - return; - } - - if (hperh->tx_rx_cplt_cbk) - hperh->tx_rx_cplt_cbk(hperh); - } - - return; + assert_param(IS_SPI_SR_STATUS(status)); + + if (hperh->rx_count != 0) { + if ((status == SPI_SR_RXBNE) || (status == SPI_SR_TXBE_RXBNE)) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + + --hperh->rx_count; + } + } + + if (hperh->tx_count != 0) { + if ((status == SPI_SR_TXBE) || (status == SPI_SR_TXBE_RXBNE)) { + if (hperh->tx_count == 1) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else { + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + + --hperh->tx_count; + + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + } + else { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else { + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + + if (--hperh->tx_count == 0) { + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + } + } + } + } + + if (hperh->rx_count == 0) { + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + hperh->state = SPI_STATE_READY; + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->tx_rx_cplt_cbk) + hperh->tx_rx_cplt_cbk(hperh); + } + + return; } - #ifdef ALD_DMA /** * @brief DMA SPI transmit process complete callback. @@ -1749,33 +1637,31 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) */ static void spi_dma_send_cplt(void *arg) { - uint16_t delay; - spi_handle_t *hperh = (spi_handle_t *)arg; + uint16_t delay; + spi_handle_t *hperh = (spi_handle_t *)arg; - hperh->tx_count = 0; - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - hperh->state = SPI_STATE_READY; + hperh->tx_count = 0; + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + hperh->state = SPI_STATE_READY; - if (hperh->init.dir == SPI_DIRECTION_2LINES) - ald_spi_clear_flag_status(hperh, SPI_IF_OVE); + if (hperh->init.dir == SPI_DIRECTION_2LINES) + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); - if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) - hperh->err_code |= SPI_ERROR_FLAG; + if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; - for (delay = 0; delay < 3000; delay++); + for (delay = 0; delay < 3000; delay++); - if (hperh->err_code == SPI_ERROR_NONE) - { - if (hperh->tx_cplt_cbk) - hperh->tx_cplt_cbk(hperh); - } - else - { - if (hperh->err_cbk) - hperh->err_cbk(hperh); - } + if (hperh->err_code == SPI_ERROR_NONE) { + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } - return; + return; } /** @@ -1785,42 +1671,38 @@ static void spi_dma_send_cplt(void *arg) */ static void spi_dma_recv_cplt(void *arg) { - uint32_t tmp; - spi_handle_t *hperh = (spi_handle_t *)arg; - - hperh->rx_count = 0; - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - hperh->state = SPI_STATE_READY; - - if (hperh->init.crc_calc) - { - if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK) - hperh->err_code |= SPI_ERROR_FLAG; - - tmp = hperh->perh->DATA; - UNUSED(tmp); - - if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) - { - SET_BIT(hperh->err_code, SPI_ERROR_CRC); - SPI_CRC_RESET(hperh); - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - } - } - - if (hperh->err_code == SPI_ERROR_NONE) - { - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - } - else - { - if (hperh->err_cbk) - hperh->err_cbk(hperh); - } - - return; + uint32_t tmp; + spi_handle_t *hperh = (spi_handle_t *)arg; + + hperh->rx_count = 0; + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->init.crc_calc) { + if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + tmp = hperh->perh->DATA; + UNUSED(tmp); + + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) { + SET_BIT(hperh->err_code, SPI_ERROR_CRC); + SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + } + + if (hperh->err_code == SPI_ERROR_NONE) { + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; } /** @@ -1830,48 +1712,44 @@ static void spi_dma_recv_cplt(void *arg) */ static void spi_dma_send_recv_cplt(void *arg) { - uint32_t tmp; - uint16_t delay; - spi_handle_t *hperh = (spi_handle_t *)arg; - - if (hperh->init.crc_calc) - { - if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK) - hperh->err_code |= SPI_ERROR_FLAG; - - tmp = hperh->perh->DATA; - UNUSED(tmp); - - if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) - { - SET_BIT(hperh->err_code, SPI_ERROR_CRC); - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - } - } - - if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) - hperh->err_code |= SPI_ERROR_FLAG; - - for (delay = 0; delay < 3000; delay++); - - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - hperh->tx_count = 0; - hperh->rx_count = 0; - hperh->state = SPI_STATE_READY; - - if (hperh->err_code == SPI_ERROR_NONE) - { - if (hperh->tx_rx_cplt_cbk) - hperh->tx_rx_cplt_cbk(hperh); - } - else - { - if (hperh->err_cbk) - hperh->err_cbk(hperh); - } - - return; + uint32_t tmp; + uint16_t delay; + spi_handle_t *hperh = (spi_handle_t *)arg; + + if (hperh->init.crc_calc) { + if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + tmp = hperh->perh->DATA; + UNUSED(tmp); + + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) { + SET_BIT(hperh->err_code, SPI_ERROR_CRC); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + } + + if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + for (delay = 0; delay < 3000; delay++); + + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + hperh->tx_count = 0; + hperh->rx_count = 0; + hperh->state = SPI_STATE_READY; + + if (hperh->err_code == SPI_ERROR_NONE) { + if (hperh->tx_rx_cplt_cbk) + hperh->tx_rx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; } /** @@ -1882,20 +1760,20 @@ static void spi_dma_send_recv_cplt(void *arg) */ static void spi_dma_error(void *arg) { - spi_handle_t *hperh = (spi_handle_t *)arg; + spi_handle_t *hperh = (spi_handle_t *)arg; - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - SET_BIT(hperh->err_code, SPI_ERROR_DMA); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + SET_BIT(hperh->err_code, SPI_ERROR_DMA); - hperh->tx_count = 0; - hperh->rx_count = 0; - hperh->state = SPI_STATE_READY; + hperh->tx_count = 0; + hperh->rx_count = 0; + hperh->state = SPI_STATE_READY; - if (hperh->err_cbk) - hperh->err_cbk(hperh); + if (hperh->err_cbk) + hperh->err_cbk(hperh); - return; + return; } #endif /* ALD_DMA */ /** diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_timer.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_timer.c index 677bbdcf86eabab4b48eed0542015e6234580949..dc0a2853686fccd2e5b88e1370955774e14bc139 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_timer.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_timer.c @@ -38,26 +38,26 @@ static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_conf static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); -static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state); -static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state); +static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state); +static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state); static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter); + timer_ic_select_t sel, uint32_t filter); static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter); static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter); + timer_ic_select_t sel, uint32_t filter); static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter); static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter); + timer_ic_select_t sel, uint32_t filter); static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter); -static void timer_etr_set_config(TIMER_TypeDef *TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter); + timer_ic_select_t sel, uint32_t filter); +static void timer_etr_set_config(TIMER_TypeDef* TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter); static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config); #ifdef ALD_DMA - static void timer_dma_oc_cplt(void *arg); - static void timer_dma_capture_cplt(void *arg); - static void timer_dma_period_elapse_cplt(void *arg); - static void timer_dma_error(void *arg); - static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config); +static void timer_dma_oc_cplt(void *arg); +static void timer_dma_capture_cplt(void *arg); +static void timer_dma_period_elapse_cplt(void *arg); +static void timer_dma_error(void *arg); +static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config); #endif /** * @} @@ -96,21 +96,21 @@ static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t * */ ald_status_t ald_timer_base_init(timer_handle_t *hperh) { - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); - assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); - if (hperh->state == TIMER_STATE_RESET) - hperh->lock = UNLOCK; + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; - hperh->state = TIMER_STATE_BUSY; - timer_base_set_config(hperh->perh, &hperh->init); - hperh->state = TIMER_STATE_READY; + hperh->state = TIMER_STATE_BUSY; + timer_base_set_config(hperh->perh, &hperh->init); + hperh->state = TIMER_STATE_READY; - return OK; + return OK; } /** @@ -120,14 +120,14 @@ ald_status_t ald_timer_base_init(timer_handle_t *hperh) */ void ald_timer_base_reset(timer_handle_t *hperh) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - hperh->state = TIMER_STATE_BUSY; - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_RESET; - __UNLOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_RESET; + __UNLOCK(hperh); - return; + return; } /** @@ -137,13 +137,15 @@ void ald_timer_base_reset(timer_handle_t *hperh) */ void ald_timer_base_start(timer_handle_t *hperh) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - hperh->state = TIMER_STATE_BUSY; - TIMER_ENABLE(hperh); - hperh->state = TIMER_STATE_READY; + hperh->state = TIMER_STATE_BUSY; + SET_BIT(hperh->perh->SGE, TIMER_SGE_SGU_MSK); + SET_BIT(hperh->perh->ICR, TIMER_ICR_UEIC_MSK); + TIMER_ENABLE(hperh); + hperh->state = TIMER_STATE_READY; - return; + return; } /** @@ -153,13 +155,13 @@ void ald_timer_base_start(timer_handle_t *hperh) */ void ald_timer_base_stop(timer_handle_t *hperh) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - hperh->state = TIMER_STATE_BUSY; - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; + hperh->state = TIMER_STATE_BUSY; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; - return; + return; } /** @@ -169,12 +171,12 @@ void ald_timer_base_stop(timer_handle_t *hperh) */ void ald_timer_base_start_by_it(timer_handle_t *hperh) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE); - TIMER_ENABLE(hperh); + ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE); + TIMER_ENABLE(hperh); - return; + return; } /** @@ -184,64 +186,61 @@ void ald_timer_base_start_by_it(timer_handle_t *hperh) */ void ald_timer_base_stop_by_it(timer_handle_t *hperh) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE); - TIMER_DISABLE(hperh); + ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE); + TIMER_DISABLE(hperh); - return; + return; } #ifdef ALD_DMA /** * @brief Starts the TIMER Base generation in DMA mode. * @param hperh: TIMER handle - * @param hdma: Pointer to dma_handle_t. * @param buf: The source Buffer address. * @param len: The length of buffer to be transferred from memory to TIMER peripheral * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } - if ((hperh->state == TIMER_STATE_READY)) - { - if (((uint32_t)buf == 0) || (len == 0)) - return ERROR; - } + hperh->state = TIMER_STATE_BUSY; - hperh->state = TIMER_STATE_BUSY; + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; - if (hdma->perh == NULL) - hdma->perh = DMA0; + hperh->hdma1.cplt_cbk = timer_dma_period_elapse_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; - hdma->cplt_cbk = timer_dma_period_elapse_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.dst = (void *)&hperh->perh->AR; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_UPDATE; + hperh->hdma1.config.channel = dma_ch; - ald_dma_config_struct(&hdma->config); - hdma->config.src = (void *)buf; - hdma->config.dst = (void *)&hperh->perh->AR; - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_HALFWORD; - hdma->config.dst_inc = DMA_DATA_INC_NONE; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_UPDATE; - hdma->config.channel = dma_ch; + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE); + TIMER_ENABLE(hperh); - timer_dma_msel(hperh->perh, &hdma->config); - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE); - TIMER_ENABLE(hperh); - - return OK; + return OK; } /** @@ -251,13 +250,13 @@ ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hd */ void ald_timer_base_stop_by_dma(timer_handle_t *hperh) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE); - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; + ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE); + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; - return; + return; } #endif /** @@ -292,7 +291,7 @@ void ald_timer_base_stop_by_dma(timer_handle_t *hperh) */ ald_status_t ald_timer_oc_init(timer_handle_t *hperh) { - return ald_timer_base_init(hperh); + return ald_timer_base_init(hperh); } /** @@ -308,15 +307,15 @@ ald_status_t ald_timer_oc_init(timer_handle_t *hperh) */ void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - return; + TIMER_ENABLE(hperh); + return; } /** @@ -332,16 +331,16 @@ void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; } /** @@ -357,37 +356,36 @@ void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; - case TIMER_CHANNEL_4: - ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); - break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); + break; - default: - break; - } + default: + break; + } - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - return; + TIMER_ENABLE(hperh); + return; } /** @@ -403,38 +401,37 @@ void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; - case TIMER_CHANNEL_4: - ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); - break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); + break; - default: - break; - } + default: + break; + } - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; } @@ -451,92 +448,88 @@ void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The source Buffer address. * @param len: The length of buffer to be transferred from memory to TIMER peripheral * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) + uint16_t *buf, uint32_t len, uint8_t dma_ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - if ((hperh->state == TIMER_STATE_READY)) - { - if (((uint32_t)buf == 0) || (len == 0)) - return ERROR; - } + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } - hperh->state = TIMER_STATE_BUSY; + hperh->state = TIMER_STATE_BUSY; - if (hdma->perh == NULL) - hdma->perh = DMA0; + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; - hdma->cplt_cbk = timer_dma_oc_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; + hperh->hdma1.cplt_cbk = timer_dma_oc_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; - ald_dma_config_struct(&hdma->config); - hdma->config.src = (void *)buf; - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_HALFWORD; - hdma->config.dst_inc = DMA_DATA_INC_NONE; - hdma->config.channel = dma_ch; + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.channel = dma_ch; - timer_dma_msel(hperh->perh, &hdma->config); + timer_dma_msel(hperh->perh, &hperh->hdma1.config); - switch (ch) - { - case TIMER_CHANNEL_1: - hdma->config.dst = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; + switch (ch) { + case TIMER_CHANNEL_1: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; - case TIMER_CHANNEL_2: - hdma->config.dst = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; + case TIMER_CHANNEL_2: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; - case TIMER_CHANNEL_3: - hdma->config.dst = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; + case TIMER_CHANNEL_3: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; - case TIMER_CHANNEL_4: - hdma->config.dst = (void *)&hperh->perh->CCVAL4; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_4; - break; + case TIMER_CHANNEL_4: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL4; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + break; - default: - break; - } + default: + break; + } - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - return OK; + TIMER_ENABLE(hperh); + return OK; } /** @@ -552,38 +545,37 @@ ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch */ void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; - case TIMER_CHANNEL_2: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; - case TIMER_CHANNEL_3: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; - case TIMER_CHANNEL_4: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); - break; + case TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); + break; - default: - break; - } + default: + break; + } - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; } #endif /** @@ -618,7 +610,7 @@ void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) */ ald_status_t ald_timer_pwm_init(timer_handle_t *hperh) { - return ald_timer_base_init(hperh); + return ald_timer_base_init(hperh); } /** @@ -634,8 +626,8 @@ ald_status_t ald_timer_pwm_init(timer_handle_t *hperh) */ void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_oc_start(hperh, ch); - return; + ald_timer_oc_start(hperh, ch); + return; } /** @@ -651,8 +643,8 @@ void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_oc_stop(hperh, ch); - return; + ald_timer_oc_stop(hperh, ch); + return; } /** @@ -668,8 +660,8 @@ void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_oc_start_by_it(hperh, ch); - return; + ald_timer_oc_start_by_it(hperh, ch); + return; } /** @@ -685,8 +677,8 @@ void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_oc_stop_by_it(hperh, ch); - return; + ald_timer_oc_stop_by_it(hperh, ch); + return; } #ifdef ALD_DMA @@ -699,16 +691,15 @@ void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The source Buffer address. * @param len: The length of buffer to be transferred from memory to TIMER peripheral * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) + uint16_t *buf, uint32_t len, uint8_t dma_ch) { - return ald_timer_oc_start_by_dma(hperh, ch, hdma, buf, len, dma_ch); + return ald_timer_oc_start_by_dma(hperh, ch, buf, len, dma_ch); } /** @@ -724,8 +715,8 @@ ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t c */ void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_oc_stop_by_dma(hperh, ch); - return; + ald_timer_oc_stop_by_dma(hperh, ch); + return; } #endif /** @@ -736,10 +727,14 @@ void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) { - uint32_t _arr = ald_cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1; + uint32_t _arr; + + if (freq == 0) + return; - WRITE_REG(hperh->perh->AR, _arr); - hperh->init.period = _arr; + _arr = ald_cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1; + WRITE_REG(hperh->perh->AR, _arr); + hperh->init.period = _arr; } /** @@ -756,20 +751,19 @@ void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) */ void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty) { - uint32_t tmp = (hperh->init.period + 1) * duty / 100 - 1; + uint32_t tmp = (hperh->init.period + 1) * duty / 100 - 1; - if (ch == TIMER_CHANNEL_1) - WRITE_REG(hperh->perh->CCVAL1, tmp); - else if (ch == TIMER_CHANNEL_2) - WRITE_REG(hperh->perh->CCVAL2, tmp); - else if (ch == TIMER_CHANNEL_3) - WRITE_REG(hperh->perh->CCVAL3, tmp); - else if (ch == TIMER_CHANNEL_4) - WRITE_REG(hperh->perh->CCVAL4, tmp); - else - { - ;/* do nothing */ - } + if (ch == TIMER_CHANNEL_1) + WRITE_REG(hperh->perh->CCVAL1, tmp); + else if (ch == TIMER_CHANNEL_2) + WRITE_REG(hperh->perh->CCVAL2, tmp); + else if (ch == TIMER_CHANNEL_3) + WRITE_REG(hperh->perh->CCVAL3, tmp); + else if (ch == TIMER_CHANNEL_4) + WRITE_REG(hperh->perh->CCVAL4, tmp); + else { + ;/* do nothing */ + } } /** @@ -783,42 +777,38 @@ void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t */ void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch)); - - CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); - - switch (ch) - { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); - break; - - default: - break; - } - - SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); - SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2EN_MSK); - - return; + assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch)); + + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2EN_MSK); + + return; } /** * @} @@ -852,7 +842,7 @@ void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch) */ ald_status_t ald_timer_ic_init(timer_handle_t *hperh) { - return ald_timer_base_init(hperh); + return ald_timer_base_init(hperh); } /** @@ -868,11 +858,11 @@ ald_status_t ald_timer_ic_init(timer_handle_t *hperh) */ void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_ENABLE(hperh); - return; + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return; } /** @@ -888,11 +878,11 @@ void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_DISABLE(hperh); - return; + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + return; } /** @@ -908,33 +898,28 @@ void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); + break; + default: + break; + } - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; - - case TIMER_CHANNEL_4: - ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); - break; - - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_ENABLE(hperh); - return; + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return; } /** @@ -950,33 +935,28 @@ void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; - - case TIMER_CHANNEL_4: - ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); - break; - - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_DISABLE(hperh); - return; + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + return; } #ifdef ALD_DMA @@ -989,87 +969,83 @@ void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The destination Buffer address. * @param len: The length of buffer to be transferred TIMER peripheral to memory * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; - - if ((hperh->state == TIMER_STATE_READY)) - { - if (((uint32_t)buf == 0) || (len == 0)) - return ERROR; - } - - hperh->state = TIMER_STATE_BUSY; - - if (hdma->perh == NULL) - hdma->perh = DMA0; - - hdma->cplt_cbk = timer_dma_capture_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; - - ald_dma_config_struct(&hdma->config); - hdma->config.dst = (void *)buf; - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_NONE; - hdma->config.dst_inc = DMA_DATA_INC_HALFWORD; - hdma->config.channel = dma_ch; - - timer_dma_msel(hperh->perh, &hdma->config); - - switch (ch) - { - case TIMER_CHANNEL_1: - hdma->config.src = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; - - case TIMER_CHANNEL_2: - hdma->config.src = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; - - case TIMER_CHANNEL_3: - hdma->config.src = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; - - case TIMER_CHANNEL_4: - hdma->config.src = (void *)&hperh->perh->CCVAL4; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_4; - break; - - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_ENABLE(hperh); - return OK; + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } + + hperh->state = TIMER_STATE_BUSY; + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; + + hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.dst = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.channel = dma_ch; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + switch (ch) { + case TIMER_CHANNEL_1: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + case TIMER_CHANNEL_4: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL4; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return OK; } /** @@ -1085,34 +1061,29 @@ ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch */ void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - - case TIMER_CHANNEL_3: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; - - case TIMER_CHANNEL_4: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); - break; - - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + case TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; } #endif /** @@ -1151,23 +1122,23 @@ void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) */ ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode) { - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); - assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); - assert_param(IS_TIMER_OP_MODE(mode)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_OP_MODE(mode)); - if (hperh->state == TIMER_STATE_RESET) - hperh->lock = UNLOCK; + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; - hperh->state = TIMER_STATE_BUSY; - timer_base_set_config(hperh->perh, &hperh->init); - MODIFY_REG(hperh->perh->CON1, TIMER_CON1_SPMEN_MSK, mode << TIMER_CON1_SPMEN_POS); - hperh->state = TIMER_STATE_READY; + hperh->state = TIMER_STATE_BUSY; + timer_base_set_config(hperh->perh, &hperh->init); + MODIFY_REG(hperh->perh->CON1, TIMER_CON1_SPMEN_MSK, mode << TIMER_CON1_SPMEN_POS); + hperh->state = TIMER_STATE_READY; - return OK; + return OK; } /** @@ -1181,19 +1152,19 @@ ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mod */ void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch) { - /* Enable the Capture compare and the Input Capture channels - * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) - * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and - * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output - * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together - */ - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + /* Enable the Capture compare and the Input Capture channels + * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) + * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and + * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output + * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together + */ + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); - return; + return; } /** @@ -1207,14 +1178,14 @@ void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t */ void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch) { - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); - return; + TIMER_DISABLE(hperh); + return; } /** @@ -1228,21 +1199,21 @@ void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t c */ void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) { - /* Enable the Capture compare and the Input Capture channels - * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) - * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and - * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output - * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together - */ - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + /* Enable the Capture compare and the Input Capture channels + * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) + * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and + * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output + * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together + */ + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); - return; + return; } /** @@ -1256,16 +1227,16 @@ void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_chan */ void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) { - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); - return; + TIMER_DISABLE(hperh); + return; } /** * @} @@ -1299,41 +1270,41 @@ void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_chann */ ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config) { - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_ENCODER_MODE(config->mode)); - assert_param(IS_TIMER_IC_POLARITY(config->ic1_polarity)); - assert_param(IS_TIMER_IC_POLARITY(config->ic2_polarity)); - assert_param(IS_TIMER_IC_SELECT(config->ic1_sel)); - assert_param(IS_TIMER_IC_SELECT(config->ic2_sel)); - assert_param(IS_TIMER_IC_PSC(config->ic1_psc)); - assert_param(IS_TIMER_IC_PSC(config->ic2_psc)); - assert_param(IS_TIMER_IC_FILTER(config->ic1_filter)); - assert_param(IS_TIMER_IC_FILTER(config->ic2_filter)); + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_ENCODER_MODE(config->mode)); + assert_param(IS_TIMER_IC_POLARITY(config->ic1_polarity)); + assert_param(IS_TIMER_IC_POLARITY(config->ic2_polarity)); + assert_param(IS_TIMER_IC_SELECT(config->ic1_sel)); + assert_param(IS_TIMER_IC_SELECT(config->ic2_sel)); + assert_param(IS_TIMER_IC_PSC(config->ic1_psc)); + assert_param(IS_TIMER_IC_PSC(config->ic2_psc)); + assert_param(IS_TIMER_IC_FILTER(config->ic1_filter)); + assert_param(IS_TIMER_IC_FILTER(config->ic2_filter)); - if (hperh->state == TIMER_STATE_RESET) - hperh->lock = UNLOCK; + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; - hperh->state = TIMER_STATE_BUSY; - CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); - timer_base_set_config(hperh->perh, &hperh->init); + hperh->state = TIMER_STATE_BUSY; + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + timer_base_set_config(hperh->perh, &hperh->init); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, config->ic1_sel << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, config->ic2_sel << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->ic1_psc << TIMER_CHMR1_IC1PRES_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->ic2_psc << TIMER_CHMR1_IC2PRES_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->ic1_filter << TIMER_CHMR1_I1FLT_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I2FLT_MSK, config->ic2_filter << TIMER_CHMR1_I2FLT_POSS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, (config->ic1_polarity & 0x1) << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((config->ic1_polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, (config->ic2_polarity & 0x1) << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((config->ic2_polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, config->ic1_sel << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, config->ic2_sel << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->ic1_psc << TIMER_CHMR1_IC1PRES_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->ic2_psc << TIMER_CHMR1_IC2PRES_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->ic1_filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I2FLT_MSK, config->ic2_filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, (config->ic1_polarity & 0x1) << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((config->ic1_polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, (config->ic2_polarity & 0x1) << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((config->ic2_polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); - hperh->state = TIMER_STATE_READY; - return OK; + hperh->state = TIMER_STATE_READY; + return OK; } /** @@ -1348,26 +1319,23 @@ ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t */ void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - switch (ch) - { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - break; - - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - break; + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - break; - } + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + break; + } - TIMER_ENABLE(hperh); - return; + TIMER_ENABLE(hperh); + return; } /** @@ -1382,26 +1350,23 @@ void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - switch (ch) - { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + break; + } - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - break; - - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - break; - } - - TIMER_DISABLE(hperh); - return; + TIMER_DISABLE(hperh); + return; } /** @@ -1416,30 +1381,27 @@ void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - switch (ch) - { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; - - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - } + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + } - TIMER_ENABLE(hperh); - return; + TIMER_ENABLE(hperh); + return; } /** @@ -1454,31 +1416,28 @@ void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - switch (ch) - { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - } - - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + } + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; } #ifdef ALD_DMA @@ -1490,8 +1449,6 @@ void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected - * @param hdma1: Pointer to dma_handle_t. - * @param hdma2: Pointer to dma_handle_t. * @param buf1: The destination Buffer address. Reading data from CCR1. * @param buf2: The destination Buffer address. Reading data from CCR2. * @param len: The length of buffer to be transferred TIMER peripheral to memory @@ -1500,92 +1457,88 @@ void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @retval Status, see @ref ald_status_t. */ ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, - uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2) -{ - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; - - if ((hperh->state == TIMER_STATE_READY)) - { - if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0)) - return ERROR; - } - - if (hdma1->perh == NULL) - hdma1->perh = DMA0; - - if (hdma2->perh == NULL) - hdma2->perh = DMA0; - - hperh->state = TIMER_STATE_BUSY; - hdma1->cplt_cbk = timer_dma_capture_cplt; - hdma1->cplt_arg = (void *)hperh; - hdma1->err_cbk = timer_dma_error; - hdma1->err_arg = (void *)hperh; - - ald_dma_config_struct(&hdma1->config); - hdma1->config.size = len; - hdma1->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma1->config.src_inc = DMA_DATA_INC_NONE; - hdma1->config.dst_inc = DMA_DATA_INC_HALFWORD; - - timer_dma_msel(hperh->perh, &hdma1->config); - - switch (ch) - { - case TIMER_CHANNEL_1: - hdma1->config.src = (void *)&hperh->perh->CCVAL1; - hdma1->config.dst = (void *)buf1; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hdma1->config.channel = dma_ch1; - ald_dma_config_basic(hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - TIMER_ENABLE(hperh); - break; - - case TIMER_CHANNEL_2: - hdma1->config.src = (void *)&hperh->perh->CCVAL2; - hdma1->config.dst = (void *)buf2; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - hdma1->config.channel = dma_ch2; - ald_dma_config_basic(hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - TIMER_ENABLE(hperh); - break; - - default: - hdma2->cplt_cbk = timer_dma_capture_cplt; - hdma2->cplt_arg = (void *)hperh; - hdma2->err_cbk = timer_dma_error; - hdma2->err_arg = (void *)hperh; - memcpy(&hdma2->config, &hdma1->config, sizeof(dma_config_t)); - - hdma1->config.src = (void *)&hperh->perh->CCVAL1; - hdma1->config.dst = (void *)buf1; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hdma1->config.channel = dma_ch1; - ald_dma_config_basic(hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - - hdma2->config.src = (void *)&hperh->perh->CCVAL2; - hdma2->config.dst = (void *)buf2; - hdma2->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - hdma2->config.channel = dma_ch2; - ald_dma_config_basic(hdma2); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - TIMER_ENABLE(hperh); - break; - } - - return OK; + uint16_t *buf1, uint16_t *buf2, uint32_t len, + uint8_t dma_ch1, uint8_t dma_ch2) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0)) + return ERROR; + } + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; + if (hperh->hdma2.perh == NULL) + hperh->hdma2.perh = DMA0; + + hperh->state = TIMER_STATE_BUSY; + hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + switch (ch) { + case TIMER_CHANNEL_1: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + break; + + case TIMER_CHANNEL_2: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.dst = (void *)buf2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hperh->hdma1.config.channel = dma_ch2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + TIMER_ENABLE(hperh); + break; + + default: + hperh->hdma2.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma2.cplt_arg = (void *)hperh; + hperh->hdma2.err_cbk = timer_dma_error; + hperh->hdma2.err_arg = (void *)hperh; + memcpy(&hperh->hdma2.config, &hperh->hdma1.config, sizeof(dma_config_t)); + + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + + hperh->hdma2.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma2.config.dst = (void *)buf2; + hperh->hdma2.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hperh->hdma2.config.channel = dma_ch2; + ald_dma_config_basic(&hperh->hdma2); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + TIMER_ENABLE(hperh); + break; + } + + return OK; } /** @@ -1600,31 +1553,28 @@ ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel */ void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - switch (ch) - { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - } - - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + } + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; } #endif /** @@ -1659,38 +1609,38 @@ void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) */ ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config) { - timer_oc_init_t oc; + timer_oc_init_t oc; - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); - assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); - assert_param(IS_TIMER_IC_POLARITY(config->polarity)); - assert_param(IS_TIMER_IC_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); - if (hperh->state == TIMER_STATE_RESET) - hperh->lock = UNLOCK; + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; - hperh->state = TIMER_STATE_READY; - timer_base_set_config(hperh->perh, &hperh->init); - timer_ti1_set_config(hperh->perh, config->polarity, TIMER_IC_SEL_TRC, config->filter); + hperh->state = TIMER_STATE_READY; + timer_base_set_config(hperh->perh, &hperh->init); + timer_ti1_set_config(hperh->perh, config->polarity, TIMER_IC_SEL_TRC, config->filter); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); - SET_BIT(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + SET_BIT(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); - oc.oc_mode = TIMER_OC_MODE_PWM2; - oc.pulse = config->delay; - oc.oc_polarity = TIMER_OC_POLARITY_HIGH; - oc.ocn_polarity = TIMER_OCN_POLARITY_HIGH; - oc.oc_fast_en = DISABLE; - oc.oc_idle = TIMER_OC_IDLE_RESET; - oc.ocn_idle = TIMER_OCN_IDLE_RESET; - timer_oc2_set_config(hperh->perh, &oc); + oc.oc_mode = TIMER_OC_MODE_PWM2; + oc.pulse = config->delay; + oc.oc_polarity = TIMER_OC_POLARITY_HIGH; + oc.ocn_polarity = TIMER_OCN_POLARITY_HIGH; + oc.oc_fast_en = DISABLE; + oc.oc_idle = TIMER_OC_IDLE_RESET; + oc.ocn_idle = TIMER_OCN_IDLE_RESET; + timer_oc2_set_config(hperh->perh, &oc); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_TRGO_OC2REF << TIMER_SMCON_SMODS_POSS); - return OK; + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_TRGO_OC2REF << TIMER_SMCON_SMODS_POSS); + return OK; } /** * @brief Starts the TIMER hall sensor interface. @@ -1699,12 +1649,12 @@ ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_senso */ void ald_timer_hall_sensor_start(timer_handle_t *hperh) { - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - TIMER_ENABLE(hperh); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); - return; + return; } /** @@ -1714,12 +1664,12 @@ void ald_timer_hall_sensor_start(timer_handle_t *hperh) */ void ald_timer_hall_sensor_stop(timer_handle_t *hperh) { - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - TIMER_DISABLE(hperh); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + TIMER_DISABLE(hperh); - return; + return; } /** @@ -1729,13 +1679,13 @@ void ald_timer_hall_sensor_stop(timer_handle_t *hperh) */ void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh) { - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - TIMER_ENABLE(hperh); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); - return; + return; } /** @@ -1745,66 +1695,63 @@ void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh) */ void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh) { - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - TIMER_DISABLE(hperh); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + TIMER_DISABLE(hperh); - return; + return; } #ifdef ALD_DMA /** * @brief Starts the TIMER hall sensor interface in DMA mode. * @param hperh: TIMER handle - * @param hdma: Pointer to dma_handle_t. * @param buf: The destination Buffer address. Reading data from CCR1. * @param len: The length of buffer to be transferred TIMER peripheral to memory * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch) { - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - if ((hperh->state == TIMER_STATE_READY)) - { - if (((uint32_t)buf == 0) || (len == 0)) - return ERROR; - } + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0) || (len == 0)) + return ERROR; + } - if (hdma->perh == NULL) - hdma->perh = DMA0; + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; - hperh->state = TIMER_STATE_BUSY; - hdma->cplt_cbk = timer_dma_capture_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; + hperh->state = TIMER_STATE_BUSY; + hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; - ald_dma_config_struct(&hdma->config); - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_NONE; - hdma->config.dst_inc = DMA_DATA_INC_HALFWORD; + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; - timer_dma_msel(hperh->perh, &hdma->config); + timer_dma_msel(hperh->perh, &hperh->hdma1.config); - hdma->config.src = (void *)&hperh->perh->CCVAL1; - hdma->config.dst = (void *)buf; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hdma->config.channel = dma_ch; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - TIMER_ENABLE(hperh); + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); - return OK; + return OK; } /** * @brief Stops the TIMER hall sensor interface in DMA mode. @@ -1813,13 +1760,13 @@ ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handl */ void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) { - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - TIMER_DISABLE(hperh); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + TIMER_DISABLE(hperh); - return; + return; } #endif /** @@ -1858,13 +1805,13 @@ void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) */ void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); + timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); - return; + return; } /** @@ -1879,13 +1826,13 @@ void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); - return; + return; } /** @@ -1901,32 +1848,30 @@ void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + default: + break; + } - default: - break; - } + ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE); + timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); - ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE); - timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - - return; + return; } /** @@ -1942,38 +1887,35 @@ void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; - default: - break; - } + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + default: + break; + } - if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NEN_MSK))) - && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NEN_MSK))) - && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NEN_MSK)))) - { - ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE); - } + if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NEN_MSK))) + && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NEN_MSK))) + && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NEN_MSK)))) { + ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE); + } - timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); - return; + return; } #ifdef ALD_DMA @@ -1986,80 +1928,76 @@ void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The destination Buffer address. Reading data from CCRx. * @param len: The length of buffer to be transferred TIMER peripheral to memory * @param dma_ch: Channel of DMA. * @retval None */ -ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) { - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } - if ((hperh->state == TIMER_STATE_READY)) - { - if (((uint32_t)buf == 0) || (len == 0)) - return ERROR; - } + hperh->state = TIMER_STATE_BUSY; - hperh->state = TIMER_STATE_BUSY; + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; - if (hdma->perh == NULL) - hdma->perh = DMA0; + hperh->hdma1.cplt_cbk = timer_dma_oc_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; - hdma->cplt_cbk = timer_dma_oc_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.channel = dma_ch; + hperh->hdma1.config.msel = DMA_MSEL_TIMER0; - ald_dma_config_struct(&hdma->config); - hdma->config.src = (void *)buf; - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_HALFWORD; - hdma->config.dst_inc = DMA_DATA_INC_NONE; - hdma->config.channel = dma_ch; - hdma->config.msel = DMA_MSEL_TIMER0; + switch (ch) { + case TIMER_CHANNEL_1: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; - switch (ch) - { - case TIMER_CHANNEL_1: - hdma->config.dst = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; + case TIMER_CHANNEL_2: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; - case TIMER_CHANNEL_2: - hdma->config.dst = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; + case TIMER_CHANNEL_3: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; - case TIMER_CHANNEL_3: - hdma->config.dst = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; + default: + break; + } - default: - break; - } + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - - return OK; + return OK; } /** @@ -2075,31 +2013,29 @@ ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdm */ void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - case TIMER_CHANNEL_2: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; - case TIMER_CHANNEL_3: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; - default: - break; - } + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + default: + break; + } - timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); - return; + return; } #endif /** @@ -2138,7 +2074,7 @@ void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_start(hperh, ch); + ald_timer_ocn_start(hperh, ch); } /** @@ -2153,7 +2089,7 @@ void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_stop(hperh, ch); + ald_timer_ocn_stop(hperh, ch); } /** @@ -2169,7 +2105,7 @@ void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_start_by_it(hperh, ch); + ald_timer_ocn_start_by_it(hperh, ch); } /** @@ -2185,7 +2121,7 @@ void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_stop_by_it(hperh, ch); + ald_timer_ocn_stop_by_it(hperh, ch); } #ifdef ALD_DMA @@ -2198,16 +2134,15 @@ void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The destination Buffer address. Reading data from CCRx. * @param len: The length of buffer to be transferred TIMER peripheral to memory * @param dma_ch: Channel of DMA. * @retval None */ -ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) { - return ald_timer_ocn_start_by_dma(hperh, hdma, ch, buf, len, dma_ch); + return ald_timer_ocn_start_by_dma(hperh, ch, buf, len, dma_ch); } /** @@ -2223,7 +2158,7 @@ ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hd */ void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_stop_by_dma(hperh, ch); + ald_timer_ocn_stop_by_dma(hperh, ch); } #endif /** @@ -2259,7 +2194,7 @@ void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_start(hperh, ch); + ald_timer_ocn_start(hperh, ch); } /** @@ -2273,7 +2208,7 @@ void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_stop(hperh, ch); + ald_timer_ocn_stop(hperh, ch); } /** @@ -2288,7 +2223,7 @@ void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_start_by_it(hperh, ch); + ald_timer_ocn_start_by_it(hperh, ch); } /** @@ -2303,7 +2238,7 @@ void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch */ void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_stop_by_it(hperh, ch); + ald_timer_ocn_stop_by_it(hperh, ch); } /** * @} @@ -2345,40 +2280,39 @@ void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch) +ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - assert_param(IS_TIMER_OC_MODE(config->oc_mode)); - assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_OC_MODE(config->oc_mode)); + assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; - switch (ch) - { - case TIMER_CHANNEL_1: - timer_oc1_set_config(hperh->perh, config); - break; + switch (ch) { + case TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, config); + break; - case TIMER_CHANNEL_2: - timer_oc2_set_config(hperh->perh, config); - break; + case TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, config); + break; - case TIMER_CHANNEL_3: - timer_oc3_set_config(hperh->perh, config); - break; + case TIMER_CHANNEL_3: + timer_oc3_set_config(hperh->perh, config); + break; - case TIMER_CHANNEL_4: - timer_oc4_set_config(hperh->perh, config); - break; + case TIMER_CHANNEL_4: + timer_oc4_set_config(hperh->perh, config); + break; - default: - break; - } + default: + break; + } - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -2394,46 +2328,45 @@ ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch) +ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_IC_POLARITY(config->polarity)); - assert_param(IS_TIMER_IC_SELECT(config->sel)); - assert_param(IS_TIMER_IC_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_SELECT(config->sel)); + assert_param(IS_TIMER_IC_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; - switch (ch) - { - case TIMER_CHANNEL_1: - timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); - break; + switch (ch) { + case TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + break; - case TIMER_CHANNEL_2: - timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS); - break; + case TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS); + break; - case TIMER_CHANNEL_3: - timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS); - break; + case TIMER_CHANNEL_3: + timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS); + break; - case TIMER_CHANNEL_4: - timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS); - break; + case TIMER_CHANNEL_4: + timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS); + break; - default: - break; - } + default: + break; + } - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -2452,70 +2385,65 @@ ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t * @retval Status, see @ref ald_status_t. */ ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, - timer_channel_t ch_out, timer_channel_t ch_in) -{ - timer_oc_init_t tmp; - - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_OC_MODE(config->mode)); - assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); - assert_param(IS_TIMER_OCN_POLARITY(config->ocn_polarity)); - assert_param(IS_TIMER_OCIDLE_STATE(config->oc_idle)); - assert_param(IS_TIMER_OCNIDLE_STATE(config->ocn_idle)); - assert_param(IS_TIMER_IC_POLARITY(config->polarity)); - assert_param(IS_TIMER_IC_SELECT(config->sel)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); - - if (ch_out == ch_in) - return ERROR; - - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; - - tmp.oc_mode = config->mode; - tmp.pulse = config->pulse; - tmp.oc_polarity = config->oc_polarity; - tmp.ocn_polarity = config->ocn_polarity; - tmp.oc_idle = config->oc_idle; - tmp.ocn_idle = config->ocn_idle; - - switch (ch_out) - { - case TIMER_CHANNEL_1: - timer_oc1_set_config(hperh->perh, &tmp); - break; - - case TIMER_CHANNEL_2: - timer_oc2_set_config(hperh->perh, &tmp); - break; - - default: - break; - } - - switch (ch_in) - { - case TIMER_CHANNEL_1: - timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); - CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_CHANNEL_2: - timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); - CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); - break; - - default: - break; - } - - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; + timer_channel_t ch_out, timer_channel_t ch_in) +{ + timer_oc_init_t tmp; + + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_OC_MODE(config->mode)); + assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); + assert_param(IS_TIMER_OCN_POLARITY(config->ocn_polarity)); + assert_param(IS_TIMER_OCIDLE_STATE(config->oc_idle)); + assert_param(IS_TIMER_OCNIDLE_STATE(config->ocn_idle)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_SELECT(config->sel)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (ch_out == ch_in) + return ERROR; + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + tmp.oc_mode = config->mode; + tmp.pulse = config->pulse; + tmp.oc_polarity = config->oc_polarity; + tmp.ocn_polarity = config->ocn_polarity; + tmp.oc_idle = config->oc_idle; + tmp.ocn_idle = config->ocn_idle; + + switch (ch_out) { + case TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, &tmp); + break; + case TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, &tmp); + break; + default: + break; + } + + switch (ch_in) { + case TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -2533,48 +2461,45 @@ ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one */ ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_FUNC_STATE(config->state)); - assert_param(IS_TIMER_CLEAR_INPUT_SOURCE(config->source)); - assert_param(IS_TIMER_CLEAR_INPUT_POLARITY(config->polarity)); - assert_param(IS_TIMER_ETR_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->state)); + assert_param(IS_TIMER_CLEAR_INPUT_SOURCE(config->source)); + assert_param(IS_TIMER_CLEAR_INPUT_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); - if (config->source == TIMER_INPUT_NONE) - { - timer_etr_set_config(hperh->perh, TIMER_ETR_PSC_DIV1, TIMER_CLK_POLARITY_NO_INV, 0); - } - else - { - timer_etr_set_config(hperh->perh, config->psc, - (timer_clock_polarity_t)config->polarity, config->filter); - } + if (config->source == TIMER_INPUT_NONE) { + timer_etr_set_config(hperh->perh, TIMER_ETR_PSC_DIV1, TIMER_CLK_POLARITY_NO_INV, 0); + } + else { + timer_etr_set_config(hperh->perh, config->psc, + (timer_clock_polarity_t)config->polarity, config->filter); + } - switch (ch) - { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS); - break; + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS); + break; - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS); - break; + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS); + break; - case TIMER_CHANNEL_3: - assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS); - break; + case TIMER_CHANNEL_3: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS); + break; - case TIMER_CHANNEL_4: - assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS); - break; + case TIMER_CHANNEL_4: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS); + break; - default: - break; - } + default: + break; + } - return OK; + return OK; } /** @@ -2586,78 +2511,76 @@ ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_in */ ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_CLOCK_SOURCE(config->source)); - assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); - assert_param(IS_TIMER_ETR_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); - - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; - WRITE_REG(hperh->perh->SMCON, 0x0); - - switch (config->source) - { - case TIMER_SRC_INTER: - CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); - break; - - case TIMER_SRC_ETRMODE1: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ETRMODE2: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK); - break; - - case TIMER_SRC_TI1: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_TI2: - timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_TI1ED: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR0: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR1: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR2: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR3: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - default: - break; - } - - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_CLOCK_SOURCE(config->source)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + WRITE_REG(hperh->perh->SMCON, 0x0); + + switch (config->source) { + case TIMER_SRC_INTER: + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + break; + + case TIMER_SRC_ETRMODE1: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ETRMODE2: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK); + break; + + case TIMER_SRC_TI1: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_TI2: + timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_TI1ED: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR0: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR1: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR2: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR3: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -2674,10 +2597,10 @@ ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_co */ ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - MODIFY_REG(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK, ti1_select << TIMER_CON2_I1FSEL_POS); - return OK; + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK, ti1_select << TIMER_CON2_I1FSEL_POS); + return OK; } /** @@ -2691,23 +2614,23 @@ ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_sele */ ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_SLAVE_MODE(config->mode)); - assert_param(IS_TIMER_TS(config->input)); - assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); - assert_param(IS_TIMER_ETR_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_SLAVE_MODE(config->mode)); + assert_param(IS_TIMER_TS(config->input)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; - timer_slave_set_config(hperh, config); - ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); + timer_slave_set_config(hperh, config); + ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -2721,23 +2644,23 @@ ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_conf */ ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_SLAVE_MODE(config->mode)); - assert_param(IS_TIMER_TS(config->input)); - assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); - assert_param(IS_TIMER_ETR_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_SLAVE_MODE(config->mode)); + assert_param(IS_TIMER_TS(config->input)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; - timer_slave_set_config(hperh, config); - ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); + timer_slave_set_config(hperh, config); + ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -2748,16 +2671,16 @@ ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slav */ ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_EVENT_SOURCE(event)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_EVENT_SOURCE(event)); - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; - WRITE_REG(hperh->perh->SGE, event); - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + WRITE_REG(hperh->perh->SGE, event); + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -2773,36 +2696,32 @@ ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_ */ uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) { - uint32_t tmp; + uint32_t tmp; - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; - switch (ch) - { - case TIMER_CHANNEL_1: - tmp = hperh->perh->CCVAL1; - break; + switch (ch) { + case TIMER_CHANNEL_1: + tmp = hperh->perh->CCVAL1; + break; + case TIMER_CHANNEL_2: + tmp = hperh->perh->CCVAL2; + break; + case TIMER_CHANNEL_3: + tmp = hperh->perh->CCVAL3; + break; + case TIMER_CHANNEL_4: + tmp = hperh->perh->CCVAL4; + break; + default: + tmp = hperh->perh->CCVAL1; + break; + } - case TIMER_CHANNEL_2: - tmp = hperh->perh->CCVAL2; - break; - - case TIMER_CHANNEL_3: - tmp = hperh->perh->CCVAL3; - break; - - case TIMER_CHANNEL_4: - tmp = hperh->perh->CCVAL4; - break; - - default: - break; - } - - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return tmp; + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return tmp; } /** @@ -2819,33 +2738,28 @@ uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_OC_MODE(mode)); - assert_param(IS_TIMER_CHANNELS(ch)); - - switch (ch) - { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS); - break; + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_OC_MODE(mode)); + assert_param(IS_TIMER_CHANNELS(ch)); - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS); - break; + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS); + break; + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS); + break; + case TIMER_CHANNEL_3: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS); + break; + case TIMER_CHANNEL_4: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS); + break; + default: + break; + } - case TIMER_CHANNEL_3: - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS); - break; - - case TIMER_CHANNEL_4: - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS); - break; - - default: - break; - } - - return; + return; } /** @@ -2853,46 +2767,46 @@ void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, time * @param hperh: TIMER handel * @param config: Parameters of the channel. * @retval None - */ + */ void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config) { - uint32_t cm1, cm2, cce; + uint32_t cm1, cm2, cce; - assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); - assert_param(IS_FUNC_STATE(config->ch[0].en)); - assert_param(IS_FUNC_STATE(config->ch[0].n_en)); - assert_param(IS_TIMER_OC_MODE(config->ch[0].mode)); - assert_param(IS_FUNC_STATE(config->ch[1].en)); - assert_param(IS_FUNC_STATE(config->ch[1].n_en)); - assert_param(IS_TIMER_OC_MODE(config->ch[1].mode)); - assert_param(IS_FUNC_STATE(config->ch[2].en)); - assert_param(IS_FUNC_STATE(config->ch[2].n_en)); - assert_param(IS_TIMER_OC_MODE(config->ch[2].mode)); + assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->ch[0].en)); + assert_param(IS_FUNC_STATE(config->ch[0].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[0].mode)); + assert_param(IS_FUNC_STATE(config->ch[1].en)); + assert_param(IS_FUNC_STATE(config->ch[1].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[1].mode)); + assert_param(IS_FUNC_STATE(config->ch[2].en)); + assert_param(IS_FUNC_STATE(config->ch[2].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[2].mode)); - TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); - cm1 = hperh->perh->CHMR1; - cm2 = hperh->perh->CHMR2; - cce = hperh->perh->CCEP; + cm1 = hperh->perh->CHMR1; + cm2 = hperh->perh->CHMR2; + cce = hperh->perh->CCEP; - MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4)); - MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12)); - MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4)); - MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0)); - MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2)); - MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4)); - MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6)); - MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8)); - MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10)); + MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4)); + MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12)); + MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4)); + MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0)); + MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2)); + MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4)); + MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6)); + MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8)); + MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10)); - WRITE_REG(hperh->perh->CHMR1, cm1); - WRITE_REG(hperh->perh->CHMR2, cm2); - WRITE_REG(hperh->perh->CCEP, cce); + WRITE_REG(hperh->perh->CHMR1, cm1); + WRITE_REG(hperh->perh->CHMR2, cm2); + WRITE_REG(hperh->perh->CCEP, cce); - TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - return; + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); + return; } /** @@ -2910,18 +2824,18 @@ void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config * @arg ENABLE: Commutation event source is TRGI * @arg DISABLE: Commutation event source is set by software using the COMG bit * @retval None - */ + */ void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) { - assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_TS(ts)); - assert_param(IS_FUNC_STATE(trgi)); + assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_TS(ts)); + assert_param(IS_FUNC_STATE(trgi)); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ts << TIMER_SMCON_TSSEL_POSS); - SET_BIT(hperh->perh->CON2, TIMER_CON2_CCPCEN_MSK); - MODIFY_REG(hperh->perh->CON2, TIMER_CON2_CCUSEL_MSK, trgi << TIMER_CON2_CCUSEL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ts << TIMER_SMCON_TSSEL_POSS); + SET_BIT(hperh->perh->CON2, TIMER_CON2_CCPCEN_MSK); + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_CCUSEL_MSK, trgi << TIMER_CON2_CCUSEL_POS); - return; + return; } /** @@ -2942,8 +2856,8 @@ void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_ */ void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) { - ald_timer_com_event_config(hperh, ts, trgi); - ald_timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE); + ald_timer_com_event_config(hperh, ts, trgi); + ald_timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE); } /** @@ -2951,32 +2865,32 @@ void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_fu * @param hperh: TIMER handle * @param config: Pointer to the timer_break_dead_timere_t structure. * @retval None - */ + */ void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config) { - uint32_t tmp; + uint32_t tmp; - assert_param(IS_TIMER_BREAK_INSTANCE(hperh->perh)); - assert_param(IS_FUNC_STATE(config->off_run)); - assert_param(IS_FUNC_STATE(config->off_idle)); - assert_param(IS_TIMER_CLOCK_LEVEL(config->lock_level)); - assert_param(IS_TIMER_DEAD_TIMERE(config->dead_time)); - assert_param(IS_FUNC_STATE(config->break_state)); - assert_param(IS_TIMER_BREAK_POLARITY(config->polarity)); - assert_param(IS_FUNC_STATE(config->auto_out)); + assert_param(IS_TIMER_BREAK_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->off_run)); + assert_param(IS_FUNC_STATE(config->off_idle)); + assert_param(IS_TIMER_CLOCK_LEVEL(config->lock_level)); + assert_param(IS_TIMER_DEAD_TIMERE(config->dead_time)); + assert_param(IS_FUNC_STATE(config->break_state)); + assert_param(IS_TIMER_BREAK_POLARITY(config->polarity)); + assert_param(IS_FUNC_STATE(config->auto_out)); - tmp = READ_REG(hperh->perh->BDCFG); - MODIFY_REG(tmp, TIMER_BDCFG_OFFSSR_MSK, config->off_run << TIMER_BDCFG_OFFSSR_POS); - MODIFY_REG(tmp, TIMER_BDCFG_OFFSSI_MSK, config->off_idle << TIMER_BDCFG_OFFSSI_POS); - MODIFY_REG(tmp, TIMER_BDCFG_LOCKLVL_MSK, config->lock_level << TIMER_BDCFG_LOCKLVL_POSS); - MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS); - MODIFY_REG(tmp, TIMER_BDCFG_BRKEN_MSK, config->break_state << TIMER_BDCFG_BRKEN_POS); - MODIFY_REG(tmp, TIMER_BDCFG_BRKP_MSK, config->polarity << TIMER_BDCFG_BRKP_POS); - MODIFY_REG(tmp, TIMER_BDCFG_AOEN_MSK, config->auto_out << TIMER_BDCFG_AOEN_POS); - WRITE_REG(hperh->perh->BDCFG, tmp); + tmp = READ_REG(hperh->perh->BDCFG); + MODIFY_REG(tmp, TIMER_BDCFG_OFFSSR_MSK, config->off_run << TIMER_BDCFG_OFFSSR_POS); + MODIFY_REG(tmp, TIMER_BDCFG_OFFSSI_MSK, config->off_idle << TIMER_BDCFG_OFFSSI_POS); + MODIFY_REG(tmp, TIMER_BDCFG_LOCKLVL_MSK, config->lock_level << TIMER_BDCFG_LOCKLVL_POSS); + MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS); + MODIFY_REG(tmp, TIMER_BDCFG_BRKEN_MSK, config->break_state << TIMER_BDCFG_BRKEN_POS); + MODIFY_REG(tmp, TIMER_BDCFG_BRKP_MSK, config->polarity << TIMER_BDCFG_BRKP_POS); + MODIFY_REG(tmp, TIMER_BDCFG_AOEN_MSK, config->auto_out << TIMER_BDCFG_AOEN_POS); + WRITE_REG(hperh->perh->BDCFG, tmp); - hperh->state = TIMER_STATE_READY; - return; + hperh->state = TIMER_STATE_READY; + return; } /** @@ -2984,19 +2898,19 @@ void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_ti * @param hperh: TIMER handle * @param config: Pointer to the timer_master_config_t structure. * @retval None - */ + */ void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel)); - assert_param(IS_FUNC_STATE(config->master_en)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel)); + assert_param(IS_FUNC_STATE(config->master_en)); - hperh->state = TIMER_STATE_BUSY; - MODIFY_REG(hperh->perh->CON2, TIMER_CON2_TRGOSEL_MSK, config->sel << TIMER_CON2_TRGOSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_MSCFG_MSK, config->master_en << TIMER_SMCON_MSCFG_POS); - hperh->state = TIMER_STATE_READY; + hperh->state = TIMER_STATE_BUSY; + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_TRGOSEL_MSK, config->sel << TIMER_CON2_TRGOSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_MSCFG_MSK, config->master_en << TIMER_SMCON_MSCFG_POS); + hperh->state = TIMER_STATE_READY; - return; + return; } /** @@ -3006,141 +2920,118 @@ void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t * */ void ald_timer_irq_handler(timer_handle_t *hperh) { - uint32_t reg = hperh->perh->IFM; - - /* Capture or compare 1 event */ - if (READ_BIT(reg, TIMER_FLAG_CC1)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC1); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK)) - { - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); - } - else /* Output compare event */ - { - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); - - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); - } - - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - } - - /* Capture or compare 2 event */ - if (READ_BIT(reg, TIMER_FLAG_CC2)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC2); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - - /* Input capture event */ - if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK)) - { - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); - } - else /* Output compare event */ - { - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); - - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); - } - - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - } - - /* Capture or compare 3 event */ - if (READ_BIT(reg, TIMER_FLAG_CC3)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC3); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - - /* Input capture event */ - if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC3SSEL_MSK)) - { - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); - } - else /* Output compare event */ - { - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); - - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); - } - - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - } - - /* Capture or compare 4 event */ - if (READ_BIT(reg, TIMER_FLAG_CC4)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC4); - hperh->ch = TIMER_ACTIVE_CHANNEL_4; - - /* Input capture event */ - if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC4SSEL_MSK)) - { - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); - } - else /* Output compare event */ - { - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); - - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); - } - - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - } - - /* TIMER Update event */ - if (READ_BIT(reg, TIMER_FLAG_UPDATE)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE); - - if (hperh->period_elapse_cbk) - hperh->period_elapse_cbk(hperh); - } - - /* TIMER Break input event */ - if (READ_BIT(reg, TIMER_FLAG_BREAK)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_BREAK); - - if (hperh->break_cbk) - hperh->break_cbk(hperh); - } - - /* TIMER Trigger detection event */ - if (READ_BIT(reg, TIMER_FLAG_TRIGGER)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER); - - if (hperh->trigger_cbk) - hperh->trigger_cbk(hperh); - } - - /* TIMER commutation event */ - if (READ_BIT(reg, TIMER_FLAG_COM)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_COM); - - if (hperh->com_cbk) - hperh->com_cbk(hperh); - } - - return; + uint32_t reg = hperh->perh->IFM; + + /* Capture or compare 1 event */ + if (READ_BIT(reg, TIMER_FLAG_CC1)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC1); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 2 event */ + if (READ_BIT(reg, TIMER_FLAG_CC2)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC2); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 3 event */ + if (READ_BIT(reg, TIMER_FLAG_CC3)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC3); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC3SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 4 event */ + if (READ_BIT(reg, TIMER_FLAG_CC4)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC4); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC4SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + + /* TIMER Update event */ + if (READ_BIT(reg, TIMER_FLAG_UPDATE)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE); + + if (hperh->period_elapse_cbk) + hperh->period_elapse_cbk(hperh); + } + + /* TIMER Break input event */ + if (READ_BIT(reg, TIMER_FLAG_BREAK)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_BREAK); + + if (hperh->break_cbk) + hperh->break_cbk(hperh); + } + + /* TIMER Trigger detection event */ + if (READ_BIT(reg, TIMER_FLAG_TRIGGER)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER); + + if (hperh->trigger_cbk) + hperh->trigger_cbk(hperh); + } + + /* TIMER commutation event */ + if (READ_BIT(reg, TIMER_FLAG_COM)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_COM); + + if (hperh->com_cbk) + hperh->com_cbk(hperh); + } + + return; } /** @@ -3152,16 +3043,16 @@ void ald_timer_irq_handler(timer_handle_t *hperh) */ void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_DMA_REQ(req)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - SET_BIT(hperh->perh->DIER, req); - else - CLEAR_BIT(hperh->perh->DIER, req); + if (state == ENABLE) + SET_BIT(hperh->perh->DIER, req); + else + SET_BIT(hperh->perh->DIDR, req); - return; + return; } /** @@ -3177,16 +3068,16 @@ void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_f */ void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_IT(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IT(it)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - SET_BIT(hperh->perh->DIER, it); - else - CLEAR_BIT(hperh->perh->DIER, it); + if (state == ENABLE) + SET_BIT(hperh->perh->DIER, it); + else + SET_BIT(hperh->perh->DIDR, it); - return; + return; } /** @@ -3200,13 +3091,13 @@ void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_ */ it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_IT(it)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IT(it)); - if (hperh->perh->DIVS & it) - return SET; + if (hperh->perh->DIVS & it) + return SET; - return RESET; + return RESET; } /** @@ -3220,13 +3111,13 @@ it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it) */ flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_FLAG(flag)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_FLAG(flag)); - if (hperh->perh->RIF & flag) - return SET; + if (hperh->perh->RIF & flag) + return SET; - return RESET; + return RESET; } /** @@ -3238,11 +3129,11 @@ flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag */ void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_FLAG(flag)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_FLAG(flag)); - hperh->perh->ICR = flag; - return; + hperh->perh->ICR = flag; + return; } /** * @} @@ -3270,7 +3161,7 @@ void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag) */ timer_state_t ald_timer_get_state(timer_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** * @} @@ -3291,16 +3182,16 @@ timer_state_t ald_timer_get_state(timer_handle_t *hperh) */ void timer_dma_oc_cplt(void *arg) { - timer_handle_t *hperh = (timer_handle_t *)arg; + timer_handle_t *hperh = (timer_handle_t *)arg; - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - return; + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + return; } /** @@ -3310,13 +3201,13 @@ void timer_dma_oc_cplt(void *arg) */ void timer_dma_capture_cplt(void *arg) { - timer_handle_t *hperh = (timer_handle_t *)arg; + timer_handle_t *hperh = (timer_handle_t *)arg; - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - return; + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + return; } /** @@ -3326,13 +3217,13 @@ void timer_dma_capture_cplt(void *arg) */ void timer_dma_period_elapse_cplt(void *arg) { - timer_handle_t *hperh = (timer_handle_t *)arg; + timer_handle_t *hperh = (timer_handle_t *)arg; - if (hperh->period_elapse_cbk) - hperh->period_elapse_cbk(hperh); + if (hperh->period_elapse_cbk) + hperh->period_elapse_cbk(hperh); - hperh->state = TIMER_STATE_READY; - return; + hperh->state = TIMER_STATE_READY; + return; } /** @@ -3342,14 +3233,13 @@ void timer_dma_period_elapse_cplt(void *arg) */ void timer_dma_error(void *arg) { - timer_handle_t *hperh = (timer_handle_t *)arg; + timer_handle_t *hperh = (timer_handle_t *)arg; - hperh->state = TIMER_STATE_READY; + hperh->state = TIMER_STATE_READY; + if (hperh->error_cbk) + hperh->error_cbk(hperh); - if (hperh->error_cbk) - hperh->error_cbk(hperh); - - return; + return; } #endif @@ -3361,29 +3251,27 @@ void timer_dma_error(void *arg) */ static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init) { - assert_param(IS_TIMER_COUNTER_MODE(init->mode)); - assert_param(IS_TIMER_CLOCK_DIVISION(init->clk_div)); + assert_param(IS_TIMER_COUNTER_MODE(init->mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(init->clk_div)); - if (init->mode == TIMER_CNT_MODE_UP || init->mode == TIMER_CNT_MODE_DOWN) - { - CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CMSEL_MSK); - MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, init->mode << TIMER_CON1_DIRSEL_POS); - } - else - { - MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, (init->mode - 1) << TIMER_CON1_CMSEL_POSS); - } + if (init->mode == TIMER_CNT_MODE_UP || init->mode == TIMER_CNT_MODE_DOWN) { + CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CMSEL_MSK); + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, init->mode << TIMER_CON1_DIRSEL_POS); + } + else { + MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, (init->mode - 1) << TIMER_CON1_CMSEL_POSS); + } - if (IS_TIMER_CLOCK_DIVISION_INSTANCE(TIMERx)) - MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, init->clk_div << TIMER_CON1_DFCKSEL_POSS); + if (IS_TIMER_CLOCK_DIVISION_INSTANCE(TIMERx)) + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, init->clk_div << TIMER_CON1_DFCKSEL_POSS); - WRITE_REG(TIMERx->AR, init->period); - WRITE_REG(TIMERx->PRES, init->prescaler); + WRITE_REG(TIMERx->AR, init->period); + WRITE_REG(TIMERx->PRES, init->prescaler); - if (IS_TIMER_REPETITION_COUNTER_INSTANCE(TIMERx)) - WRITE_REG(TIMERx->REPAR, init->re_cnt); + if (IS_TIMER_REPETITION_COUNTER_INSTANCE(TIMERx)) + WRITE_REG(TIMERx->REPAR, init->re_cnt); - return; + return; } /** @@ -3394,29 +3282,27 @@ static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init */ static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); - CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK); - CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH1OMOD_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC1POL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH1OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC1POL_POS); - if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_1)) - { - assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC1NPOL_POS); - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK); - } + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_1)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC1NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK); + } - if (IS_TIMER_BREAK_INSTANCE(TIMERx)) - { - assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); - assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1_MSK, oc_config->oc_idle << TIMER_CON2_OISS1_POS); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS1N_POS); - } + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1_MSK, oc_config->oc_idle << TIMER_CON2_OISS1_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS1N_POS); + } - WRITE_REG(TIMERx->CCVAL1, oc_config->pulse); + WRITE_REG(TIMERx->CCVAL1, oc_config->pulse); } /** @@ -3427,29 +3313,27 @@ static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_conf */ static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); - CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK); - CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH2OMOD_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC2POL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH2OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC2POL_POS); - if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_2)) - { - assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC2NPOL_POS); - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK); - } + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_2)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC2NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK); + } - if (IS_TIMER_BREAK_INSTANCE(TIMERx)) - { - assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); - assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2_MSK, oc_config->oc_idle << TIMER_CON2_OISS2_POS); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS2N_POS); - } + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2_MSK, oc_config->oc_idle << TIMER_CON2_OISS2_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS2N_POS); + } - WRITE_REG(TIMERx->CCVAL2, oc_config->pulse); + WRITE_REG(TIMERx->CCVAL2, oc_config->pulse); } /** @@ -3460,29 +3344,27 @@ static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_conf */ static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); - CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK); - CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH3OMOD_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC3POL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH3OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC3POL_POS); - if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_3)) - { - assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC3NPOL_POS); - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK); - } + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_3)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC3NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK); + } - if (IS_TIMER_BREAK_INSTANCE(TIMERx)) - { - assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); - assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3_MSK, oc_config->oc_idle << TIMER_CON2_OISS3_POS); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS3N_POS); - } + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3_MSK, oc_config->oc_idle << TIMER_CON2_OISS3_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS3N_POS); + } - WRITE_REG(TIMERx->CCVAL3, oc_config->pulse); + WRITE_REG(TIMERx->CCVAL3, oc_config->pulse); } /** @@ -3493,19 +3375,18 @@ static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_conf */ static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); - CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK); - CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH4OMOD_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC4POL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH4OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC4POL_POS); - if (IS_TIMER_BREAK_INSTANCE(TIMERx)) - { - assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS4_MSK, oc_config->oc_idle << TIMER_CON2_OISS4_POS); - } + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS4_MSK, oc_config->oc_idle << TIMER_CON2_OISS4_POS); + } - WRITE_REG(TIMERx->CCVAL4, oc_config->pulse); + WRITE_REG(TIMERx->CCVAL4, oc_config->pulse); } /** @@ -3520,32 +3401,31 @@ static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_conf * @param state: specifies the TIMER Channel CCxE bit new state. * @retval None */ -static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state) +static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state) { - assert_param(IS_TIMER_CC2_INSTANCE(TIMERx)); - assert_param(IS_TIMER_CHANNELS(ch)); + assert_param(IS_TIMER_CC2_INSTANCE(TIMERx)); + assert_param(IS_TIMER_CHANNELS(ch)); - switch (ch) - { - case TIMER_CHANNEL_1: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS); - break; + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS); + break; - case TIMER_CHANNEL_2: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS); - break; + case TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS); + break; - case TIMER_CHANNEL_3: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS); - break; + case TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS); + break; - case TIMER_CHANNEL_4: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS); - break; + case TIMER_CHANNEL_4: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS); + break; - default: - break; - } + default: + break; + } } /** * @brief Enables or disables the TIMER Capture Compare Channel xN. @@ -3558,25 +3438,24 @@ static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, typ * @param state: specifies the TIMER Channel CCxNE bit new state. * @retval None */ -static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state) +static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state) { - switch (ch) - { - case TIMER_CHANNEL_1: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS); - break; + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS); + break; - case TIMER_CHANNEL_2: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS); - break; + case TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS); + break; - case TIMER_CHANNEL_3: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS); - break; + case TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS); + break; - default: - break; - } + default: + break; + } } @@ -3590,14 +3469,14 @@ static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, ty * @retval None */ static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter) + timer_ic_select_t sel, uint32_t filter) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); - return; + return; } /** @@ -3610,11 +3489,11 @@ static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola */ static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) { - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); - return; + return; } /** @@ -3627,15 +3506,15 @@ static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_ * @retval None */ static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter) + timer_ic_select_t sel, uint32_t filter) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); - return; + return; } /** @@ -3648,9 +3527,9 @@ static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola */ static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) { - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); - return; + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); + return; } /** @@ -3663,14 +3542,14 @@ static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_ * @retval None */ static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter) + timer_ic_select_t sel, uint32_t filter) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, polarity << TIMER_CCEP_CC3POL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, polarity << TIMER_CCEP_CC3POL_POS); - return; + return; } /** @@ -3683,13 +3562,13 @@ static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola * @retval None */ static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter) + timer_ic_select_t sel, uint32_t filter) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, polarity << TIMER_CCEP_CC4POL_POS); - return; + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, polarity << TIMER_CCEP_CC4POL_POS); + return; } /** @@ -3701,13 +3580,13 @@ static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola * This parameter must be a value between 0x00 and 0x0F * @retval None */ -static void timer_etr_set_config(TIMER_TypeDef *TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter) +static void timer_etr_set_config(TIMER_TypeDef* TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter) { - MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETFLT_MSK, filter << TIMER_SMCON_ETFLT_POSS); - MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, psc << TIMER_SMCON_ETPSEL_POSS); - CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK); - MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, polarity << TIMER_SMCON_ETPOL_POS); - return; + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETFLT_MSK, filter << TIMER_SMCON_ETFLT_POSS); + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, psc << TIMER_SMCON_ETPSEL_POSS); + CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK); + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, polarity << TIMER_SMCON_ETPOL_POS); + return; } /** @@ -3719,31 +3598,30 @@ static void timer_etr_set_config(TIMER_TypeDef *TIMERx, timer_etr_psc_t psc, tim */ static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config) { - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, config->input << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, config->input << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); - switch (config->input) - { - case TIMER_TS_ETRF: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - break; + switch (config->input) { + case TIMER_TS_ETRF: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + break; - case TIMER_TS_TI1F_ED: - CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS); - break; + case TIMER_TS_TI1F_ED: + CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS); + break; - case TIMER_TS_TI1FP1: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - break; + case TIMER_TS_TI1FP1: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + break; - case TIMER_TS_TI2FP2: - timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - break; + case TIMER_TS_TI2FP2: + timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + break; - default: - break; - } + default: + break; + } } #ifdef ALD_DMA @@ -3757,41 +3635,30 @@ static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t * */ static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config) { -#if defined (ES32F065x) - - if (hperh == AD16C4T0) - config->msel = DMA_MSEL_TIMER0; - - if (hperh == GP16C4T0) - config->msel = DMA_MSEL_TIMER6; - -#elif defined (ES32F033x) || defined (ES32F093x) - - if (hperh == GP16C4T0) - config->msel = DMA_MSEL_TIMER0; - - if (hperh == GP16C4T1) - config->msel = DMA_MSEL_TIMER6; - -#endif - - if (hperh == GP16C2T0) - config->msel = DMA_MSEL_TIMER2; - - if (hperh == GP16C2T1) - config->msel = DMA_MSEL_TIMER3; - - if (hperh == BS16T0) - config->msel = DMA_MSEL_TIMER1; - - if (hperh == BS16T1) - config->msel = DMA_MSEL_TIMER4; - - if (hperh == BS16T2) - config->msel = DMA_MSEL_TIMER5; - - if (hperh == BS16T3) - config->msel = DMA_MSEL_TIMER7; + #if defined (ES32F065x) + if (hperh == AD16C4T0) + config->msel = DMA_MSEL_TIMER0; + if (hperh == GP16C4T0) + config->msel = DMA_MSEL_TIMER6; + #elif defined (ES32F033x) || defined (ES32F093x) + if (hperh == GP16C4T0) + config->msel = DMA_MSEL_TIMER0; + if (hperh == GP16C4T1) + config->msel = DMA_MSEL_TIMER6; + #endif + + if (hperh == GP16C2T0) + config->msel = DMA_MSEL_TIMER2; + if (hperh == GP16C2T1) + config->msel = DMA_MSEL_TIMER3; + if (hperh == BS16T0) + config->msel = DMA_MSEL_TIMER1; + if (hperh == BS16T1) + config->msel = DMA_MSEL_TIMER4; + if (hperh == BS16T2) + config->msel = DMA_MSEL_TIMER5; + if (hperh == BS16T3) + config->msel = DMA_MSEL_TIMER7; } #endif diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_trng.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_trng.c index 85539e815a0131bfe4fc4ace236de042e51dbc2b..8e4d13a4d0711aa3b03250562b5579d73f73a6bf 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_trng.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_trng.c @@ -33,7 +33,7 @@ void trng_reset(trng_handle_t *hperh); /** * @} - */ + */ /** @defgroup TRNG_Public_Functions TRNG Public Functions * @{ @@ -68,40 +68,42 @@ void trng_reset(trng_handle_t *hperh); */ ald_status_t ald_trng_init(trng_handle_t *hperh) { - uint32_t tmp = 0; + uint32_t tmp = 0; - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width)); - assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type)); - assert_param(IS_TRNG_ADJC(hperh->init.adjc)); + assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width)); + assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type)); + assert_param(IS_TRNG_ADJC(hperh->init.adjc)); + assert_param(IS_FUNC_STATE(hperh->init.posten)); + assert_param(IS_TRNG_T_START(hperh->init.t_start)); - __LOCK(hperh); - trng_reset(hperh); + __LOCK(hperh); + trng_reset(hperh); - if (hperh->state == TRNG_STATE_RESET) - __UNLOCK(hperh); + if (hperh->state == TRNG_STATE_RESET) + __UNLOCK(hperh); - tmp = TRNG->CR; + tmp = TRNG->CR; - if (hperh->init.adjc == 0) - tmp = (0 << TRNG_CR_ADJM_POS); - else - tmp = (1 << TRNG_CR_ADJM_POS); + if (hperh->init.adjc == 0) + tmp = (0 << TRNG_CR_ADJM_POS); + else + tmp = (1 << TRNG_CR_ADJM_POS); - tmp |= ((1 << TRNG_CR_TRNGSEL_POS) | (hperh->init.data_width << TRNG_CR_DSEL_POSS) | - (hperh->init.seed_type << TRNG_CR_SDSEL_POSS) | (hperh->init.adjc << TRNG_CR_ADJC_POSS) | - (hperh->init.posten << TRNG_CR_POSTEN_MSK)); + tmp |= ((1 << TRNG_CR_TRNGSEL_POS) | (hperh->init.data_width << TRNG_CR_DSEL_POSS) | + (hperh->init.seed_type << TRNG_CR_SDSEL_POSS) | (hperh->init.adjc << TRNG_CR_ADJC_POSS) | + (hperh->init.posten << TRNG_CR_POSTEN_MSK)); - TRNG->CR = tmp; + TRNG->CR = tmp; - WRITE_REG(TRNG->SEED, hperh->init.seed); - MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (hperh->init.t_start) << TRNG_CFGR_TSTART_POSS); + WRITE_REG(TRNG->SEED, hperh->init.seed); + MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (hperh->init.t_start) << TRNG_CFGR_TSTART_POSS); - hperh->state = TRNG_STATE_READY; - __UNLOCK(hperh); - return OK; + hperh->state = TRNG_STATE_READY; + __UNLOCK(hperh); + return OK; } /** * @} @@ -134,9 +136,9 @@ ald_status_t ald_trng_init(trng_handle_t *hperh) */ uint32_t ald_trng_get_result(trng_handle_t *hperh) { - hperh->state = TRNG_STATE_READY; - hperh->data = hperh->perh->DR; - return (uint32_t)hperh->perh->DR; + hperh->state = TRNG_STATE_READY; + hperh->data = hperh->perh->DR; + return (uint32_t)hperh->perh->DR; } /** @@ -153,15 +155,15 @@ uint32_t ald_trng_get_result(trng_handle_t *hperh) */ void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state) { - assert_param(IS_TRNG_IT(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_TRNG_IT(it)); + assert_param(IS_FUNC_STATE(state)); - if (state) - SET_BIT(hperh->perh->IER, it); - else - CLEAR_BIT(hperh->perh->IER, it); + if (state) + SET_BIT(hperh->perh->IER, it); + else + CLEAR_BIT(hperh->perh->IER, it); - return; + return; } /** @@ -176,12 +178,12 @@ void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t s */ flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status) { - assert_param(IS_TRNG_STATUS(status)); + assert_param(IS_TRNG_STATUS(status)); - if (READ_BIT(hperh->perh->SR, status)) - return SET; + if (READ_BIT(hperh->perh->SR, status)) + return SET; - return RESET; + return RESET; } /** @@ -196,12 +198,12 @@ flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status) */ it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it) { - assert_param(IS_TRNG_IT(it)); + assert_param(IS_TRNG_IT(it)); - if (READ_BIT(hperh->perh->IER, it)) - return SET; + if (READ_BIT(hperh->perh->IER, it)) + return SET; - return RESET; + return RESET; } /** @@ -216,12 +218,12 @@ it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it) */ flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag) { - assert_param(IS_TRNG_FLAG(flag)); + assert_param(IS_TRNG_FLAG(flag)); - if (READ_BIT(hperh->perh->IFR, flag)) - return SET; + if (READ_BIT(hperh->perh->IFR, flag)) + return SET; - return RESET; + return RESET; } /** @@ -234,10 +236,10 @@ flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag) */ void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag) { - assert_param(IS_TRNG_FLAG(flag)); - WRITE_REG(hperh->perh->IFCR, flag); + assert_param(IS_TRNG_FLAG(flag)); + WRITE_REG(hperh->perh->IFCR, flag); - return; + return; } /** @@ -248,15 +250,15 @@ void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag) */ void trng_reset(trng_handle_t *hperh) { - TRNG->CR = 0; - TRNG->SEED = 0; - TRNG->CFGR = 0x1FF0707; - TRNG->IER = 0; - TRNG->IFCR = 0xFFFFFFFF; - - hperh->state = TRNG_STATE_READY; - __UNLOCK(hperh); - return; + TRNG->CR = 0; + TRNG->SEED = 0; + TRNG->CFGR = 0x1FF0707; + TRNG->IER = 0; + TRNG->IFCR = 0xFFFFFFFF; + + hperh->state = TRNG_STATE_READY; + __UNLOCK(hperh); + return; } /** @@ -267,35 +269,28 @@ void trng_reset(trng_handle_t *hperh) */ void ald_trng_irq_handler(trng_handle_t *hperh) { - if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET) - { - hperh->state = TRNG_STATE_ERROR; - ald_trng_clear_flag_status(hperh, TRNG_IF_SERR); - - if (hperh->err_cplt_cbk) - hperh->err_cplt_cbk(hperh); - - return; - } - - if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET) - { - hperh->data = hperh->perh->DR; - hperh->state = TRNG_STATE_READY; - ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD); - - if (hperh->trng_cplt_cbk) - hperh->trng_cplt_cbk(hperh); - } - - if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET) - { - hperh->state = TRNG_STATE_BUSY; - ald_trng_clear_flag_status(hperh, TRNG_IF_START); - - if (hperh->init_cplt_cbk) - hperh->init_cplt_cbk(hperh); - } + if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET) { + hperh->state = TRNG_STATE_ERROR; + ald_trng_clear_flag_status(hperh, TRNG_IF_SERR); + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); + return; + } + + if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET) { + hperh->data = hperh->perh->DR; + hperh->state = TRNG_STATE_READY; + ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD); + if (hperh->trng_cplt_cbk) + hperh->trng_cplt_cbk(hperh); + } + + if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET) { + hperh->state = TRNG_STATE_BUSY; + ald_trng_clear_flag_status(hperh, TRNG_IF_START); + if (hperh->init_cplt_cbk) + hperh->init_cplt_cbk(hperh); + } } /** diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_tsense.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_tsense.c index b31d5084cb5e0a7b114a0553bfdadcb7667c9de5..5fcd8311f1eaa82fdb8429232ace60736b199867 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_tsense.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_tsense.c @@ -61,26 +61,39 @@ tsense_cbk __tsense_cbk; /** * @brief Initializes the TSENSE according to the specified - * parameters in the tsense_init_t. - * @param init: Pointer to a tsense_init_t structure that contains - * the configuration information. * @retval None */ -void ald_tsense_init(tsense_init_t *init) +void ald_tsense_init(void) { - assert_param(IS_TSENSE_UPDATE_CYCLE(init->cycle)); - assert_param(IS_TSENSE_OUTPUT_MODE(init->mode)); - - TSENSE_UNLOCK(); - TSENSE->CR = 0; - - MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, init->cycle << TSENSE_CR_TSU_POSS); - MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, init->mode << TSENSE_CR_TOM_POSS); - MODIFY_REG(TSENSE->CR, TSENSE_CR_CTN_MSK, init->ctn << TSENSE_CR_CTN_POS); - MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, init->psc << TSENSE_PSR_PRS_POSS); - TSENSE_LOCK(); - - return; + uint16_t tempt, temptinv; + uint32_t tscic, tscicinv; + + TSENSE_UNLOCK(); + TSENSE->CR = 0; + + MODIFY_REG(TSENSE->CR, TSENSE_CR_CTN_MSK, 0x1 << TSENSE_CR_CTN_POS); + MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, 0x4 << TSENSE_CR_TSU_POSS); + MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, 0x3 << TSENSE_CR_TOM_POSS); + MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, 0x1 << TSENSE_PSR_PRS_POSS); + + TSENSE->HTGR = 0x88F18; + TSENSE->LTGR = 0x85C39; + tempt = *(volatile uint16_t *)0x40348; + temptinv = *(volatile uint16_t *)0x4034A; + tscic = *(volatile uint32_t *)0x40350; + tscicinv = *(volatile uint32_t *)0x40358; + + if ((tempt == (uint16_t)(~temptinv)) && (tscic == (~tscicinv))) { + TSENSE->TBDR = tempt; + TSENSE->TCALBDR = (tscic & 0x1FFFFFF) >> 6; + } + else { + TSENSE->TBDR = 0x1E00; + TSENSE->TCALBDR = 0x1FE70; + } + + TSENSE_LOCK(); + return; } /** @@ -90,26 +103,23 @@ void ald_tsense_init(tsense_init_t *init) */ void ald_tsense_source_select(tsense_source_sel_t sel) { - assert_param(IS_TSENSE_SOURCE_SEL(sel)); - - BKPC_UNLOCK(); - MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS); - - if (sel == TSENSE_SOURCE_LOSC) - { - SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); - } - else if (sel == TSENSE_SOURCE_LRC) - { - SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); - } - else - { - ; /* do nothing */ - } - - BKPC_LOCK(); - return; + assert_param(IS_TSENSE_SOURCE_SEL(sel)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS); + + if (sel == TSENSE_SOURCE_LOSC) { + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); + } + else if (sel == TSENSE_SOURCE_LRC) { + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); + } + else { + ; /* do nothing */ + } + + BKPC_LOCK(); + return; } /** * @} @@ -140,27 +150,40 @@ void ald_tsense_source_select(tsense_source_sel_t sel) */ ald_status_t ald_tsense_get_value(uint16_t *tsense) { - uint32_t tmp = 0; + uint32_t tmp = 0; + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + + while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000)); - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); - TSENSE_LOCK(); + if (tmp >= 1000000) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + return TIMEOUT; + } - while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000)); + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + TSENSE_LOCK(); - if (tmp >= 1000000) - return TIMEOUT; + if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + return ERROR; + } - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - TSENSE_LOCK(); + *tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS); - if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) - return ERROR; + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); - *tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS); - return OK; + return OK; } /** @@ -170,15 +193,15 @@ ald_status_t ald_tsense_get_value(uint16_t *tsense) */ void ald_tsense_get_value_by_it(tsense_cbk cbk) { - __tsense_cbk = cbk; + __tsense_cbk = cbk; - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - SET_BIT(TSENSE->IE, TSENSE_IE_TSENSE_MSK); - SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); - TSENSE_LOCK(); + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + SET_BIT(TSENSE->IE, TSENSE_IE_TSENSE_MSK); + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); - return; + return; } /** @@ -187,25 +210,32 @@ void ald_tsense_get_value_by_it(tsense_cbk cbk) */ void ald_tsense_irq_handler(void) { - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - TSENSE_LOCK(); - - if (__tsense_cbk == NULL) - return; - - if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) - { - __tsense_cbk(0, ERROR); - return; - } - - __tsense_cbk(READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS), OK); - - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - TSENSE_LOCK(); - return; + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + TSENSE_LOCK(); + + if (__tsense_cbk == NULL) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + return; + } + + if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + __tsense_cbk(0, ERROR); + return; + } + + __tsense_cbk(READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS), OK); + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + return; } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_uart.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_uart.c index ee0751ad8d07847a8406b11a7f8f0036fae5036a..ee4bd1bbd21aeca0b612e3a6ce8f2dc2a2b88954 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_uart.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_uart.c @@ -112,14 +112,14 @@ */ static void uart_dma_send_cplt(void *arg) { - uart_handle_t *hperh = (uart_handle_t *)arg; + uart_handle_t *hperh = (uart_handle_t *)arg; - if (hperh->state == UART_STATE_BUSY_TX) - ald_uart_dma_req_config(hperh, DISABLE); + if (hperh->state == UART_STATE_BUSY_TX) + ald_uart_dma_req_config(hperh, DISABLE); - hperh->tx_count = 0; - ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); - return; + hperh->tx_count = 0; + ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + return; } /** @@ -129,18 +129,18 @@ static void uart_dma_send_cplt(void *arg) */ static void uart_dma_recv_cplt(void *arg) { - uart_handle_t *hperh = (uart_handle_t *)arg; + uart_handle_t *hperh = (uart_handle_t *)arg; - if (hperh->state == UART_STATE_BUSY_RX) - ald_uart_dma_req_config(hperh, DISABLE); + if (hperh->state == UART_STATE_BUSY_RX) + ald_uart_dma_req_config(hperh, DISABLE); - hperh->rx_count = 0; - CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + hperh->rx_count = 0; + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); - return; + return; } /** @@ -150,18 +150,18 @@ static void uart_dma_recv_cplt(void *arg) */ static void uart_dma_error(void *arg) { - uart_handle_t *hperh = (uart_handle_t *)arg; + uart_handle_t *hperh = (uart_handle_t *)arg; - hperh->rx_count = 0; - hperh->tx_count = 0; - hperh->state = UART_STATE_READY; - hperh->err_code |= UART_ERROR_DMA; - ald_uart_dma_req_config(hperh, DISABLE); + hperh->rx_count = 0; + hperh->tx_count = 0; + hperh->state = UART_STATE_READY; + hperh->err_code |= UART_ERROR_DMA; + ald_uart_dma_req_config(hperh, DISABLE); - if (hperh->error_cbk) - hperh->error_cbk(hperh); + if (hperh->error_cbk) + hperh->error_cbk(hperh); - return; + return; } #endif @@ -175,21 +175,20 @@ static void uart_dma_error(void *arg) */ static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout) { - uint32_t tick; + uint32_t tick; - if (timeout == 0) - return ERROR; + if (timeout == 0) + return ERROR; - tick = ald_get_tick(); + tick = ald_get_tick(); - /* Waiting for flag */ - while ((ald_uart_get_status(hperh, flag)) != status) - { - if (((ald_get_tick()) - tick) > timeout) - return TIMEOUT; - } + /* Waiting for flag */ + while ((ald_uart_get_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } - return OK; + return OK; } /** @@ -199,19 +198,18 @@ static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, fla */ static ald_status_t __uart_send_by_it(uart_handle_t *hperh) { - if ((hperh->state & UART_STATE_TX_MASK) == 0x0) - return BUSY; + if ((hperh->state & UART_STATE_TX_MASK) == 0x0) + return BUSY; - WRITE_REG(hperh->perh->TBR, (uint8_t)(*hperh->tx_buf++ & 0x00FF)); + WRITE_REG(hperh->perh->TBR, (uint8_t)(*hperh->tx_buf++ & 0x00FF)); - if (--hperh->tx_count == 0) - { - ald_uart_clear_flag_status(hperh, UART_IF_TC); - ald_uart_interrupt_config(hperh, UART_IT_TXS, DISABLE); - ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); - } + if (--hperh->tx_count == 0) { + ald_uart_clear_flag_status(hperh, UART_IF_TC); + ald_uart_interrupt_config(hperh, UART_IT_TXS, DISABLE); + ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + } - return OK; + return OK; } /** @@ -221,16 +219,15 @@ static ald_status_t __uart_send_by_it(uart_handle_t *hperh) */ static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh) { - if (!(READ_BIT(hperh->perh->SR, UART_SR_TEM_MSK))) - return OK; + if (!(READ_BIT(hperh->perh->SR, UART_SR_TEM_MSK))) + return OK; - ald_uart_interrupt_config(hperh, UART_IT_TC, DISABLE); - CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + ald_uart_interrupt_config(hperh, UART_IT_TC, DISABLE); + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); - if (hperh->tx_cplt_cbk) - hperh->tx_cplt_cbk(hperh); - - return OK; + return OK; } /** @@ -240,21 +237,20 @@ static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh) */ static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) { - if ((hperh->state & UART_STATE_RX_MASK) == 0x0) - return BUSY; + if ((hperh->state & UART_STATE_RX_MASK) == 0x0) + return BUSY; - *hperh->rx_buf++ = (uint8_t)(hperh->perh->RBR & 0xFF); + *hperh->rx_buf++ = (uint8_t)(hperh->perh->RBR & 0xFF); - if (--hperh->rx_count == 0) - { - ald_uart_interrupt_config(hperh, UART_IT_RXRD, DISABLE); - CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + if (--hperh->rx_count == 0) { + ald_uart_interrupt_config(hperh, UART_IT_RXRD, DISABLE); + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - } + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } - return OK; + return OK; } /** * @} @@ -299,21 +295,21 @@ static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) */ void ald_uart_reset(uart_handle_t *hperh) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - WRITE_REG(hperh->perh->BRR, 0x0); - WRITE_REG(hperh->perh->LCR, 0x0); - WRITE_REG(hperh->perh->MCR, 0x0); - WRITE_REG(hperh->perh->CR, 0x0); - WRITE_REG(hperh->perh->RTOR, 0x0); - WRITE_REG(hperh->perh->FCR, 0x0); - WRITE_REG(hperh->perh->IDR, 0xFFF); + WRITE_REG(hperh->perh->BRR, 0x0); + WRITE_REG(hperh->perh->LCR, 0x0); + WRITE_REG(hperh->perh->MCR, 0x0); + WRITE_REG(hperh->perh->CR, 0x0); + WRITE_REG(hperh->perh->RTOR, 0x0); + WRITE_REG(hperh->perh->FCR, 0x0); + WRITE_REG(hperh->perh->IDR, 0xFFF); - hperh->err_code = UART_ERROR_NONE; - hperh->state = UART_STATE_RESET; + hperh->err_code = UART_ERROR_NONE; + hperh->state = UART_STATE_RESET; - __UNLOCK(hperh); - return; + __UNLOCK(hperh); + return; } /** @@ -325,55 +321,54 @@ void ald_uart_reset(uart_handle_t *hperh) */ void ald_uart_init(uart_handle_t *hperh) { - uint32_t tmp; - - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_BAUDRATE(hperh->init.baud)); - assert_param(IS_UART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_UART_STOPBITS(hperh->init.stop_bits)); - assert_param(IS_UART_PARITY(hperh->init.parity)); - assert_param(IS_UART_MODE(hperh->init.mode)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); - - ald_uart_reset(hperh); - - tmp = READ_REG(hperh->perh->LCR); - MODIFY_REG(tmp, UART_LCR_DLS_MSK, hperh->init.word_length << UART_LCR_DLS_POSS); - MODIFY_REG(tmp, UART_LCR_STOP_MSK, hperh->init.stop_bits << UART_LCR_STOP_POS); - MODIFY_REG(tmp, UART_LCR_PEN_MSK, (hperh->init.parity == UART_PARITY_NONE ? 0 : 1) << UART_LCR_PEN_POS); - MODIFY_REG(tmp, UART_LCR_PS_MSK, (hperh->init.parity == UART_PARITY_EVEN ? 1 : 0) << UART_LCR_PS_POS); - WRITE_REG(hperh->perh->LCR, tmp); - MODIFY_REG(hperh->perh->MCR, UART_MCR_AFCEN_MSK, hperh->init.fctl << UART_MCR_AFCEN_POS); - SET_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); - WRITE_REG(hperh->perh->BRR, ald_cmu_get_pclk1_clock() / hperh->init.baud); - CLEAR_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); - SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); - SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); - SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK); - MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, 0 << UART_FCR_RXTL_POSS); - MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, 0 << UART_FCR_TXTL_POSS); - SET_BIT(hperh->perh->LCR, UART_LCR_RXEN_MSK); - - if (hperh->init.mode == UART_MODE_LIN) - SET_BIT(hperh->perh->MCR, UART_MCR_LINEN_MSK); - else if (hperh->init.mode == UART_MODE_IrDA) - SET_BIT(hperh->perh->MCR, UART_MCR_IREN_MSK); - else if (hperh->init.mode == UART_MODE_RS485) - SET_BIT(hperh->perh->MCR, UART_MCR_AADEN_MSK); - else if (hperh->init.mode == UART_MODE_HDSEL) - SET_BIT(hperh->perh->MCR, UART_MCR_HDSEL_MSK); - else - ;/* do nothing */ - - if (hperh->init.fctl) - SET_BIT(hperh->perh->MCR, UART_MCR_RTSCTRL_MSK); - - if (hperh->init.mode == UART_MODE_IrDA) - SET_BIT(hperh->perh->LCR, UART_LCR_RXINV_MSK); - - hperh->state = UART_STATE_READY; - hperh->err_code = UART_ERROR_NONE; - return; + uint32_t tmp; + + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_BAUDRATE(hperh->init.baud)); + assert_param(IS_UART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_UART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_UART_PARITY(hperh->init.parity)); + assert_param(IS_UART_MODE(hperh->init.mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); + + ald_uart_reset(hperh); + + tmp = READ_REG(hperh->perh->LCR); + MODIFY_REG(tmp, UART_LCR_DLS_MSK, hperh->init.word_length << UART_LCR_DLS_POSS); + MODIFY_REG(tmp, UART_LCR_STOP_MSK, hperh->init.stop_bits << UART_LCR_STOP_POS); + MODIFY_REG(tmp, UART_LCR_PEN_MSK, (hperh->init.parity == UART_PARITY_NONE ? 0 : 1) << UART_LCR_PEN_POS); + MODIFY_REG(tmp, UART_LCR_PS_MSK, (hperh->init.parity == UART_PARITY_EVEN ? 1 : 0) << UART_LCR_PS_POS); + WRITE_REG(hperh->perh->LCR, tmp); + MODIFY_REG(hperh->perh->MCR, UART_MCR_AFCEN_MSK, hperh->init.fctl << UART_MCR_AFCEN_POS); + SET_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); + WRITE_REG(hperh->perh->BRR, ald_cmu_get_pclk1_clock() / hperh->init.baud); + CLEAR_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); + SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); + SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); + SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK); + MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, 0 << UART_FCR_RXTL_POSS); + MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, 0 << UART_FCR_TXTL_POSS); + SET_BIT(hperh->perh->LCR, UART_LCR_RXEN_MSK); + + if (hperh->init.mode == UART_MODE_LIN) + SET_BIT(hperh->perh->MCR, UART_MCR_LINEN_MSK); + else if (hperh->init.mode == UART_MODE_IrDA) + SET_BIT(hperh->perh->MCR, UART_MCR_IREN_MSK); + else if (hperh->init.mode == UART_MODE_RS485) + SET_BIT(hperh->perh->MCR, UART_MCR_AADEN_MSK); + else if (hperh->init.mode == UART_MODE_HDSEL) + SET_BIT(hperh->perh->MCR, UART_MCR_HDSEL_MSK); + else + ;/* do nothing */ + + if (hperh->init.fctl) + SET_BIT(hperh->perh->MCR, UART_MCR_RTSCTRL_MSK); + if (hperh->init.mode == UART_MODE_IrDA) + SET_BIT(hperh->perh->LCR, UART_LCR_RXINV_MSK); + + hperh->state = UART_STATE_READY; + hperh->err_code = UART_ERROR_NONE; + return; } /** @@ -386,17 +381,17 @@ void ald_uart_init(uart_handle_t *hperh) */ void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_FUNC_STATE(config->normal)); - assert_param(IS_FUNC_STATE(config->dir)); - assert_param(IS_FUNC_STATE(config->invert)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_FUNC_STATE(config->normal)); + assert_param(IS_FUNC_STATE(config->dir)); + assert_param(IS_FUNC_STATE(config->invert)); - MODIFY_REG(hperh->perh->MCR, UART_MCR_AADNOR_MSK, config->normal << UART_MCR_AADNOR_POS); - MODIFY_REG(hperh->perh->MCR, UART_MCR_AADDIR_MSK, config->dir << UART_MCR_AADDIR_POS); - MODIFY_REG(hperh->perh->MCR, UART_MCR_AADINV_MSK, config->invert << UART_MCR_AADINV_POS); - MODIFY_REG(hperh->perh->CR, UART_CR_ADDR_MSK, config->addr << UART_CR_ADDR_POSS); + MODIFY_REG(hperh->perh->MCR, UART_MCR_AADNOR_MSK, config->normal << UART_MCR_AADNOR_POS); + MODIFY_REG(hperh->perh->MCR, UART_MCR_AADDIR_MSK, config->dir << UART_MCR_AADDIR_POS); + MODIFY_REG(hperh->perh->MCR, UART_MCR_AADINV_MSK, config->invert << UART_MCR_AADINV_POS); + MODIFY_REG(hperh->perh->CR, UART_CR_ADDR_MSK, config->addr << UART_CR_ADDR_POSS); - return; + return; } /** * @} @@ -460,44 +455,41 @@ void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) */ ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) - return BUSY; + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL) || (size == 0)) + return ERROR; - __LOCK(hperh); - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_TX_MASK); + __LOCK(hperh); + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); - hperh->tx_size = size; - hperh->tx_count = size; + hperh->tx_size = size; + hperh->tx_count = size; - while (hperh->tx_count-- > 0) - { - if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = UART_STATE_READY; - return TIMEOUT; - } + while (hperh->tx_count-- > 0) { + if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } - WRITE_REG(hperh->perh->TBR, (*buf++ & 0xFF)); - } + WRITE_REG(hperh->perh->TBR, (*buf++ & 0xFF)); + } - if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = UART_STATE_READY; - return TIMEOUT; - } + if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } - CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); - __UNLOCK(hperh); + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -510,38 +502,36 @@ ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, ui */ ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) - return BUSY; + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL ) || (size == 0)) + return ERROR; - __LOCK(hperh); + __LOCK(hperh); - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_RX_MASK); + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); - hperh->rx_size = size; - hperh->rx_count = size; + hperh->rx_size = size; + hperh->rx_count = size; - while (hperh->rx_count-- > 0) - { - if (uart_wait_flag(hperh, UART_STATUS_DR, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = UART_STATE_READY; - return TIMEOUT; - } + while (hperh->rx_count-- > 0) { + if (uart_wait_flag(hperh, UART_STATUS_DR, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } - *buf++ = (uint8_t)(hperh->perh->RBR & 0xFF); - } + *buf++ = (uint8_t)(hperh->perh->RBR & 0xFF); + } - CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); - __UNLOCK(hperh); + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -553,38 +543,36 @@ ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, ui */ ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) { - assert_param(IS_UART_ALL(hperh->perh)); - - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_TX_MASK); - __UNLOCK(hperh); - - if (((ald_uart_get_status(hperh, UART_STATUS_TBEM)) == SET) - && ((ald_uart_get_flag_status(hperh, UART_IF_TXS)) == RESET)) - { - WRITE_REG(hperh->perh->TBR, (*hperh->tx_buf++ & 0xFF)); - --hperh->tx_count; - } - - if (hperh->tx_count == 0) - { - ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); - return OK; - } - - ald_uart_interrupt_config(hperh, UART_IT_TXS, ENABLE); - return OK; + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + __UNLOCK(hperh); + + if (((ald_uart_get_status(hperh, UART_STATUS_TBEM)) == SET) + && ((ald_uart_get_flag_status(hperh, UART_IF_TXS)) == RESET)) { + WRITE_REG(hperh->perh->TBR, (*hperh->tx_buf++ & 0xFF)); + --hperh->tx_count; + } + + if (hperh->tx_count == 0) { + ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + return OK; + } + + ald_uart_interrupt_config(hperh, UART_IT_TXS, ENABLE); + return OK; } /** @@ -596,24 +584,24 @@ ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t si */ ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) - return BUSY; + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL ) || (size == 0)) + return ERROR; - __LOCK(hperh); - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_RX_MASK); - __UNLOCK(hperh); + __LOCK(hperh); + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + __UNLOCK(hperh); - ald_uart_interrupt_config(hperh, UART_IT_RXRD, ENABLE); - return OK; + ald_uart_interrupt_config(hperh, UART_IT_RXRD, ENABLE); + return OK; } #ifdef ALD_DMA /** @@ -626,64 +614,63 @@ ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t si */ ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - assert_param(IS_UART_ALL(hperh->perh)); - - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_TX_MASK); - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = uart_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = uart_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->TBR; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART_TXEMPTY; - hperh->hdmatx.config.burst = ENABLE; - hperh->hdmatx.config.channel = channel; - - if (hperh->init.mode == UART_MODE_RS485) - { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - if (hperh->perh == UART0) - hperh->hdmatx.config.msel = DMA_MSEL_UART0; - else if (hperh->perh == UART1) - hperh->hdmatx.config.msel = DMA_MSEL_UART1; - else if (hperh->perh == UART2) - hperh->hdmatx.config.msel = DMA_MSEL_UART2; - else if (hperh->perh == UART3) - hperh->hdmatx.config.msel = DMA_MSEL_UART3; - else - ; /* do nothing */ - - ald_dma_config_basic(&hperh->hdmatx); - - __UNLOCK(hperh); - ald_uart_clear_flag_status(hperh, UART_IF_TC); - ald_uart_dma_req_config(hperh, ENABLE); - - return OK; + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = uart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = uart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TBR; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART_TXEMPTY; + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.channel = channel; + + if (hperh->init.mode == UART_MODE_RS485) { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + if (hperh->perh == UART0) + hperh->hdmatx.config.msel = DMA_MSEL_UART0; + else if (hperh->perh == UART1) + hperh->hdmatx.config.msel = DMA_MSEL_UART1; + else if (hperh->perh == UART2) + hperh->hdmatx.config.msel = DMA_MSEL_UART2; + else if (hperh->perh == UART3) + hperh->hdmatx.config.msel = DMA_MSEL_UART3; + else + ; /* do nothing */ + + ald_dma_config_basic(&hperh->hdmatx); + + __UNLOCK(hperh); + ald_uart_clear_flag_status(hperh, UART_IF_TC); + ald_uart_dma_req_config(hperh, ENABLE); + + return OK; } /** @@ -696,61 +683,60 @@ ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t s */ ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - assert_param(IS_UART_ALL(hperh->perh)); - - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_RX_MASK); - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = uart_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = uart_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->RBR; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART_RNR; - hperh->hdmarx.config.burst = ENABLE; - hperh->hdmarx.config.channel = channel; - - if (hperh->init.mode == UART_MODE_RS485) - { - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - if (hperh->perh == UART0) - hperh->hdmarx.config.msel = DMA_MSEL_UART0; - else if (hperh->perh == UART1) - hperh->hdmarx.config.msel = DMA_MSEL_UART1; - else if (hperh->perh == UART2) - hperh->hdmarx.config.msel = DMA_MSEL_UART2; - else if (hperh->perh == UART3) - hperh->hdmarx.config.msel = DMA_MSEL_UART3; - else - ; - - ald_dma_config_basic(&hperh->hdmarx); - __UNLOCK(hperh); - ald_uart_dma_req_config(hperh, ENABLE); - - return OK; + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = uart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = uart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RBR; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART_RNR; + hperh->hdmarx.config.burst = ENABLE; + hperh->hdmarx.config.channel = channel; + + if (hperh->init.mode == UART_MODE_RS485) { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + if (hperh->perh == UART0) + hperh->hdmarx.config.msel = DMA_MSEL_UART0; + else if (hperh->perh == UART1) + hperh->hdmarx.config.msel = DMA_MSEL_UART1; + else if (hperh->perh == UART2) + hperh->hdmarx.config.msel = DMA_MSEL_UART2; + else if (hperh->perh == UART3) + hperh->hdmarx.config.msel = DMA_MSEL_UART3; + else + ; + + ald_dma_config_basic(&hperh->hdmarx); + __UNLOCK(hperh); + ald_uart_dma_req_config(hperh, ENABLE); + + return OK; } /** @@ -760,10 +746,10 @@ ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t s */ ald_status_t ald_uart_dma_pause(uart_handle_t *hperh) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - ald_uart_dma_req_config(hperh, DISABLE); - return OK; + ald_uart_dma_req_config(hperh, DISABLE); + return OK; } /** @@ -773,10 +759,10 @@ ald_status_t ald_uart_dma_pause(uart_handle_t *hperh) */ ald_status_t ald_uart_dma_resume(uart_handle_t *hperh) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - ald_uart_dma_req_config(hperh, ENABLE); - return OK; + ald_uart_dma_req_config(hperh, ENABLE); + return OK; } /** @@ -786,11 +772,11 @@ ald_status_t ald_uart_dma_resume(uart_handle_t *hperh) */ ald_status_t ald_uart_dma_stop(uart_handle_t *hperh) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - ald_uart_dma_req_config(hperh, DISABLE); - hperh->state = UART_STATE_READY; - return OK; + ald_uart_dma_req_config(hperh, DISABLE); + hperh->state = UART_STATE_READY; + return OK; } #endif @@ -801,49 +787,45 @@ ald_status_t ald_uart_dma_stop(uart_handle_t *hperh) */ void ald_uart_irq_handler(uart_handle_t *hperh) { - assert_param(IS_UART_ALL(hperh->perh)); - - /* Handle parity error */ - if ((ald_uart_get_status(hperh, UART_STATUS_PE)) != RESET) - hperh->err_code |= UART_ERROR_PE; - - /* Handle frame error */ - if ((ald_uart_get_status(hperh, UART_STATUS_FE)) != RESET) - hperh->err_code |= UART_ERROR_FE; - - /* Handle overflow error */ - if ((ald_uart_get_status(hperh, UART_STATUS_OE)) != RESET) - hperh->err_code |= UART_ERROR_ORE; - - /* Receive */ - if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RXRD)) != RESET) - { - ald_uart_clear_flag_status(hperh, UART_IF_RXRD); - __uart_recv_by_it(hperh); - } - - /* Transmit */ - if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TXS)) != RESET) - { - ald_uart_clear_flag_status(hperh, UART_IF_TXS); - __uart_send_by_it(hperh); - } - - /* End Transmit */ - if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TC)) != RESET) - { - ald_uart_clear_flag_status(hperh, UART_IF_TC); - __uart_end_send_by_it(hperh); - } - - /* Handle error state */ - if (hperh->err_code != UART_ERROR_NONE) - { - hperh->state = UART_STATE_READY; - - if (hperh->error_cbk) - hperh->error_cbk(hperh); - } + assert_param(IS_UART_ALL(hperh->perh)); + + /* Handle parity error */ + if ((ald_uart_get_status(hperh, UART_STATUS_PE)) != RESET) + hperh->err_code |= UART_ERROR_PE; + + /* Handle frame error */ + if ((ald_uart_get_status(hperh, UART_STATUS_FE)) != RESET) + hperh->err_code |= UART_ERROR_FE; + + /* Handle overflow error */ + if ((ald_uart_get_status(hperh, UART_STATUS_OE)) != RESET) + hperh->err_code |= UART_ERROR_ORE; + + /* Receive */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RXRD)) != RESET) { + __uart_recv_by_it(hperh); + ald_uart_clear_flag_status(hperh, UART_IF_RXRD); + } + + /* Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TXS)) != RESET) { + __uart_send_by_it(hperh); + ald_uart_clear_flag_status(hperh, UART_IF_TXS); + } + + /* End Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TC)) != RESET) { + __uart_end_send_by_it(hperh); + ald_uart_clear_flag_status(hperh, UART_IF_TC); + } + + /* Handle error state */ + if (hperh->err_code != UART_ERROR_NONE) { + hperh->state = UART_STATE_READY; + + if (hperh->error_cbk) + hperh->error_cbk(hperh); + } } /** * @} @@ -888,16 +870,16 @@ void ald_uart_irq_handler(uart_handle_t *hperh) */ void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IT(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IT(it)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - WRITE_REG(hperh->perh->IER, it); - else - WRITE_REG(hperh->perh->IDR, it); + if (state == ENABLE) + WRITE_REG(hperh->perh->IER, it); + else + WRITE_REG(hperh->perh->IDR, it); - return; + return; } /** @@ -911,55 +893,51 @@ void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t s */ void ald_uart_dma_req_config(uart_handle_t *hperh, type_func_t state) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - SET_BIT(hperh->perh->MCR, UART_MCR_DMAEN_MSK); - else - CLEAR_BIT(hperh->perh->MCR, UART_MCR_DMAEN_MSK); + if (state == ENABLE) + SET_BIT(hperh->perh->MCR, UART_MCR_DMAEN_MSK); + else + CLEAR_BIT(hperh->perh->MCR, UART_MCR_DMAEN_MSK); - return; + return; } /** * @brief Configure transmit fifo parameters. * @param hperh: Pointer to a uart_handle_t structure. * @param config: Transmit fifo trigger level. - * @param level: Transmit fifo level. * @retval None */ -void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) +void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_TXFIFO_TYPE(config)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_TXFIFO_TYPE(config)); - SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK); - MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, config << UART_FCR_TXTL_POSS); - MODIFY_REG(hperh->perh->FCR, UART_FCR_TXFL_MSK, level << UART_FCR_TXFL_POSS); - SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); + SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK); + MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, config << UART_FCR_TXTL_POSS); + SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); - return; + return; } /** * @brief Configure receive fifo parameters. * @param hperh: Pointer to a uart_handle_t structure. * @param config: Receive fifo trigger level. - * @param level: Receive fifo level. * @retval None */ -void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) +void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_RXFIFO_TYPE(config)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_RXFIFO_TYPE(config)); - SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); - MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, config << UART_FCR_RXTL_POSS); - MODIFY_REG(hperh->perh->FCR, UART_FCR_RXFL_MSK, level << UART_FCR_RXFL_POSS); - SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); + SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); + MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, config << UART_FCR_RXTL_POSS); + SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); - return; + return; } /** @@ -969,10 +947,10 @@ void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t */ void ald_uart_lin_send_break(uart_handle_t *hperh) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - SET_BIT(hperh->perh->MCR, UART_MCR_BKREQ_MSK); - return; + SET_BIT(hperh->perh->MCR, UART_MCR_BKREQ_MSK); + return; } /** @@ -985,11 +963,11 @@ void ald_uart_lin_send_break(uart_handle_t *hperh) */ void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_LIN_BREAK_LEN(len)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_LIN_BREAK_LEN(len)); - MODIFY_REG(hperh->perh->MCR, UART_MCR_LINBDL_MSK, len << UART_MCR_LINBDL_POS); - return; + MODIFY_REG(hperh->perh->MCR, UART_MCR_LINBDL_MSK, len << UART_MCR_LINBDL_POS); + return; } /** @@ -1003,11 +981,11 @@ void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_l */ void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_AUTO_BAUD_MODE(mode)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_AUTO_BAUD_MODE(mode)); - MODIFY_REG(hperh->perh->MCR, UART_MCR_ABRMOD_MSK, mode << UART_MCR_ABRMOD_POSS); - return; + MODIFY_REG(hperh->perh->MCR, UART_MCR_ABRMOD_MSK, mode << UART_MCR_ABRMOD_POSS); + return; } /** @@ -1020,30 +998,28 @@ void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode) */ ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) - return BUSY; + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; - SET_BIT(hperh->state, UART_STATE_TX_MASK); + SET_BIT(hperh->state, UART_STATE_TX_MASK); - if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) - { - hperh->state = UART_STATE_READY; - return TIMEOUT; - } + if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } - WRITE_REG(hperh->perh->TBR, (addr | 0x100)); + WRITE_REG(hperh->perh->TBR, (addr | 0x100)); - if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) - { - hperh->state = UART_STATE_READY; - return TIMEOUT; - } + if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } - CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); - return OK; + return OK; } /** @@ -1057,13 +1033,13 @@ ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint3 */ it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IT(it)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IT(it)); - if (READ_BIT(hperh->perh->IVS, it)) - return SET; + if (READ_BIT(hperh->perh->IVS, it)) + return SET; - return RESET; + return RESET; } /** @@ -1077,13 +1053,13 @@ it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it) */ flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_STATUS(status)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_STATUS(status)); - if (READ_BIT(hperh->perh->SR, status)) - return SET; + if (READ_BIT(hperh->perh->SR, status)) + return SET; - return RESET; + return RESET; } @@ -1098,13 +1074,13 @@ flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status) */ flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IF(flag)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); - if (READ_BIT(hperh->perh->RIF, flag)) - return SET; + if (READ_BIT(hperh->perh->RIF, flag)) + return SET; - return RESET; + return RESET; } /** @@ -1118,13 +1094,13 @@ flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag) */ flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IF(flag)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); - if (READ_BIT(hperh->perh->IFM, flag)) - return SET; + if (READ_BIT(hperh->perh->IFM, flag)) + return SET; - return RESET; + return RESET; } /** @@ -1136,11 +1112,11 @@ flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t fl */ void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IF(flag)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); - WRITE_REG(hperh->perh->ICR, flag); - return; + WRITE_REG(hperh->perh->ICR, flag); + return; } /** * @} @@ -1171,7 +1147,7 @@ void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) */ uart_state_t ald_uart_get_state(uart_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** @@ -1181,7 +1157,7 @@ uart_state_t ald_uart_get_state(uart_handle_t *hperh) */ uint32_t ald_uart_get_error(uart_handle_t *hperh) { - return hperh->err_code; + return hperh->err_code; } /** diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_usart.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_usart.c index 18672dd07e84908f68354d78175bd40443cc26e1..1e9ed5c50147b929c9c3fb21f03428f3ec91bb67 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_usart.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_usart.c @@ -173,7 +173,7 @@ uint8_t __frame_mode = 0; /** @addtogroup USART_Private_Functions USART Private Functions * @{ */ -static void usart_set_config(usart_handle_t *hperh); +static void usart_set_config (usart_handle_t *hperh); static ald_status_t __usart_send_by_it(usart_handle_t *hperh); static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh); static ald_status_t __usart_recv_by_it(usart_handle_t *hperh); @@ -181,9 +181,9 @@ static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh); static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh); static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh); #ifdef ALD_DMA - static void usart_dma_send_cplt(void *arg); - static void usart_dma_recv_cplt(void *arg); - static void usart_dma_error(void *arg); +static void usart_dma_send_cplt(void *arg); +static void usart_dma_recv_cplt(void *arg); +static void usart_dma_error(void *arg); #endif static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout); /** @@ -247,20 +247,20 @@ static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, fl */ void ald_usart_reset(usart_handle_t *hperh) { - assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART(hperh->perh)); - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); - WRITE_REG(hperh->perh->CON0, 0x0); - WRITE_REG(hperh->perh->CON1, 0x0); - WRITE_REG(hperh->perh->CON2, 0x0); + WRITE_REG(hperh->perh->CON0, 0x0); + WRITE_REG(hperh->perh->CON1, 0x0); + WRITE_REG(hperh->perh->CON2, 0x0); - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_RESET; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_RESET; - __UNLOCK(hperh); - return; + __UNLOCK(hperh); + return; } /** @@ -272,30 +272,29 @@ void ald_usart_reset(usart_handle_t *hperh) */ ald_status_t ald_usart_init(usart_handle_t *hperh) { - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - - ald_usart_reset(hperh); - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); - usart_set_config(hperh); - - /* In asynchronous mode, the following bits must be kept cleared: - * - LINEN and CLKEN bits in the USART_CR2 register, - * - SCEN, HDSEL and IREN bits in the USART_CR3 register. - */ - CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_READY; - USART_ENABLE(hperh); - - return OK; + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + + ald_usart_reset(hperh); + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); + usart_set_config(hperh); + + /* In asynchronous mode, the following bits must be kept cleared: + * - LINEN and CLKEN bits in the USART_CR2 register, + * - SCEN, HDSEL and IREN bits in the USART_CR3 register. + */ + CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_READY; + USART_ENABLE(hperh); + + return OK; } /** @@ -307,28 +306,27 @@ ald_status_t ald_usart_init(usart_handle_t *hperh) */ ald_status_t ald_usart_half_duplex_init(usart_handle_t *hperh) { - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - - ald_usart_reset(hperh); - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); - usart_set_config(hperh); - - /* In half-duplex mode, the following bits must be kept cleared: - * - LINEN and CLKEN bits in the USART_CR2 register, - * - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - SET_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_READY; - USART_ENABLE(hperh); - - return OK; + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + + ald_usart_reset(hperh); + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); + usart_set_config(hperh); + + /* In half-duplex mode, the following bits must be kept cleared: + * - LINEN and CLKEN bits in the USART_CR2 register, + * - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + SET_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_READY; + USART_ENABLE(hperh); + + return OK; } /** @@ -345,32 +343,31 @@ ald_status_t ald_usart_half_duplex_init(usart_handle_t *hperh) */ ald_status_t ald_usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup) { - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_WAKEUP(wakeup)); - assert_param(IS_USART_ADDRESS(addr)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - - ald_usart_reset(hperh); - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); - usart_set_config(hperh); - - /* In Multi-Processor mode, the following bits must be kept cleared: - * - LINEN and CLKEN bits in the USART_CR2 register, - * - SCEN, HDSEL and IREN bits in the USART_CR3 register */ - CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - MODIFY_REG(hperh->perh->CON1, USART_CON1_ADDR_MSK, addr << USART_CON1_ADDR_POSS); - MODIFY_REG(hperh->perh->CON0, USART_CON0_WKMOD_MSK, wakeup << USART_CON0_WKMOD_POS); - - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_READY; - USART_ENABLE(hperh); - - return OK; + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_WAKEUP(wakeup)); + assert_param(IS_USART_ADDRESS(addr)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + + ald_usart_reset(hperh); + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); + usart_set_config(hperh); + + /* In Multi-Processor mode, the following bits must be kept cleared: + * - LINEN and CLKEN bits in the USART_CR2 register, + * - SCEN, HDSEL and IREN bits in the USART_CR3 register */ + CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + MODIFY_REG(hperh->perh->CON1, USART_CON1_ADDR_MSK, addr << USART_CON1_ADDR_POSS); + MODIFY_REG(hperh->perh->CON0, USART_CON0_WKMOD_MSK, wakeup << USART_CON0_WKMOD_POS); + + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_READY; + USART_ENABLE(hperh); + + return OK; } /** @@ -383,31 +380,30 @@ ald_status_t ald_usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, */ ald_status_t ald_usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init) { - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - - ald_usart_reset(hperh); - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); - usart_set_config(hperh); - - /* In Multi-Processor mode, the following bits must be kept cleared: - * - LINEN and CLKEN bits in the USART_CR2 register, - * - SCEN, HDSEL and IREN bits in the USART_CR3 register */ - CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKEN_MSK, init->clk << USART_CON1_SCKEN_POS); - MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKPOL_MSK, init->polarity << USART_CON1_SCKPOL_POS); - MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKPHA_MSK, init->phase << USART_CON1_SCKPHA_POS); - MODIFY_REG(hperh->perh->CON1, USART_CON1_LBCP_MSK, init->last_bit << USART_CON1_LBCP_POS); - - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_READY; - USART_ENABLE(hperh); - - return OK; + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + + ald_usart_reset(hperh); + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); + usart_set_config(hperh); + + /* In Multi-Processor mode, the following bits must be kept cleared: + * - LINEN and CLKEN bits in the USART_CR2 register, + * - SCEN, HDSEL and IREN bits in the USART_CR3 register */ + CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKEN_MSK, init->clk << USART_CON1_SCKEN_POS); + MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKPOL_MSK, init->polarity << USART_CON1_SCKPOL_POS); + MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKPHA_MSK, init->phase << USART_CON1_SCKPHA_POS); + MODIFY_REG(hperh->perh->CON1, USART_CON1_LBCP_MSK, init->last_bit << USART_CON1_LBCP_POS); + + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_READY; + USART_ENABLE(hperh); + + return OK; } /** @@ -485,57 +481,50 @@ ald_status_t ald_usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *ini */ ald_status_t ald_usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - hperh->err_code = USART_ERROR_NONE; - SET_BIT(hperh->state, USART_STATE_TX_MASK); - - hperh->tx_size = size; - hperh->tx_count = size; - - while (hperh->tx_count-- > 0) - { - if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - if (hperh->init.parity == USART_PARITY_NONE) - { - WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & (uint16_t)0x01FF)); - buf += 2; - } - else - { - WRITE_REG(hperh->perh->DATA, *buf++); - } - } - else - { - WRITE_REG(hperh->perh->DATA, *buf++); - } - } - - if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); - __UNLOCK(hperh); - - return OK; + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = USART_ERROR_NONE; + SET_BIT(hperh->state, USART_STATE_TX_MASK); + + hperh->tx_size = size; + hperh->tx_count = size; + + while (hperh->tx_count-- > 0) { + if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + if (hperh->init.parity == USART_PARITY_NONE) { + WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & (uint16_t)0x01FF)); + buf += 2; + } + else { + WRITE_REG(hperh->perh->DATA, *buf++); + } + } + else { + WRITE_REG(hperh->perh->DATA, *buf++); + } + } + + if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); + __UNLOCK(hperh); + + return OK; } /** @@ -549,54 +538,48 @@ ald_status_t ald_usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, */ ald_status_t ald_usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - hperh->err_code = USART_ERROR_NONE; - SET_BIT(hperh->state, USART_STATE_RX_MASK); - - hperh->rx_size = size; - hperh->rx_count = size; - - while (hperh->rx_count-- > 0) - { - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - if (hperh->init.parity == USART_PARITY_NONE) - { - *(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - buf += 2; - } - else - { - *buf = (uint8_t)(hperh->perh->DATA & 0xFF); - buf += 1; - } - } - else - { - if (hperh->init.parity == USART_PARITY_NONE) - *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - } - - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - __UNLOCK(hperh); - - return OK; + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = USART_ERROR_NONE; + SET_BIT(hperh->state, USART_STATE_RX_MASK); + + hperh->rx_size = size; + hperh->rx_count = size; + + while (hperh->rx_count-- > 0) { + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + if (hperh->init.parity == USART_PARITY_NONE) { + *(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + buf += 2; + } + else { + *buf = (uint8_t)(hperh->perh->DATA & 0xFF); + buf += 1; + } + } + else { + if (hperh->init.parity == USART_PARITY_NONE) + *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + } + + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + __UNLOCK(hperh); + + return OK; } /** @@ -609,24 +592,24 @@ ald_status_t ald_usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, */ ald_status_t ald_usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) - return BUSY; + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL ) || (size == 0)) + return ERROR; - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_TX_MASK); + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_TX_MASK); - hperh->tx_buf = buf; - hperh->rx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + __UNLOCK(hperh); + ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); - return OK; + return OK; } /** @@ -639,26 +622,26 @@ ald_status_t ald_usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t */ ald_status_t ald_usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) - return BUSY; + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL ) || (size == 0)) + return ERROR; - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = USART_ERROR_NONE; + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = USART_ERROR_NONE; - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + __UNLOCK(hperh); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - return OK; + return OK; } /** @@ -671,27 +654,27 @@ ald_status_t ald_usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t */ ald_status_t ald_usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) - return BUSY; + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL ) || (size == 0)) + return ERROR; - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = USART_ERROR_NONE; + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = USART_ERROR_NONE; - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - __frame_mode = 1; + __UNLOCK(hperh); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + __frame_mode = 1; - return OK; + return OK; } #ifdef ALD_DMA @@ -706,54 +689,53 @@ ald_status_t ald_usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uin */ ald_status_t ald_usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_TX_MASK); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - /* Configure callback function */ - hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = usart_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - - /* Configure USART DMA transmit */ - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) - { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmatx); - - __UNLOCK(hperh); - ald_usart_clear_flag_status(hperh, USART_FLAG_TC); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - - return OK; + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_TX_MASK); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + /* Configure callback function */ + hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = usart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + /* Configure USART DMA transmit */ + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmatx); + + __UNLOCK(hperh); + ald_usart_clear_flag_status(hperh, USART_FLAG_TC); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + + return OK; } /** @@ -769,52 +751,51 @@ ald_status_t ald_usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t */ ald_status_t ald_usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->err_code = USART_ERROR_NONE; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - /* Configure callback function */ - hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = usart_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - /* Configure DMA Receive */ - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; - hperh->hdmarx.config.channel = channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) - { - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmarx); - - __UNLOCK(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - - return OK; + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->err_code = USART_ERROR_NONE; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + /* Configure callback function */ + hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = usart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + /* Configure DMA Receive */ + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; + hperh->hdmarx.config.channel = channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmarx); + + __UNLOCK(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + + return OK; } #endif /** @@ -890,50 +871,45 @@ ald_status_t ald_usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t */ ald_status_t ald_usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX; - - while (hperh->tx_count-- > 0) - { - if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) - { - WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & 0x1FF)); - buf += 2; - } - else - { - WRITE_REG(hperh->perh->DATA, *buf++); - } - } - - if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - - return OK; + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX; + + while (hperh->tx_count-- > 0) { + if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) { + WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & 0x1FF)); + buf += 2; + } + else { + WRITE_REG(hperh->perh->DATA, *buf++); + } + } + + if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + hperh->state = USART_STATE_READY; + __UNLOCK(hperh); + + return OK; } /** @@ -947,71 +923,63 @@ ald_status_t ald_usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t s */ ald_status_t ald_usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_RX; - - while (hperh->rx_count-- > 0) - { - if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF)); - - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.parity == USART_PARITY_NONE) - { - *(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - buf += 2; - } - else - { - *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - } - else - { - WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0xFF)); - - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.parity == USART_PARITY_NONE) - *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - } - - hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - - return OK; + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_RX; + + while (hperh->rx_count-- > 0) { + if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF)); + + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.parity == USART_PARITY_NONE) { + *(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + buf += 2; + } + else { + *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + } + else { + WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0xFF)); + + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.parity == USART_PARITY_NONE) + *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + } + + hperh->state = USART_STATE_READY; + __UNLOCK(hperh); + + return OK; } /** @@ -1026,83 +994,73 @@ ald_status_t ald_usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t s */ ald_status_t ald_usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) { - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_RX; - - while (hperh->tx_count-- > 0) - { - --hperh->rx_count; - - if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - if (hperh->init.parity == USART_PARITY_NONE) - { - WRITE_REG(hperh->perh->DATA, (*(uint16_t *)tx_buf & 0x1FF)); - tx_buf += 2; - } - else - { - WRITE_REG(hperh->perh->DATA, *tx_buf++); - } - - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.parity == USART_PARITY_NONE) - { - *(uint16_t *)rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - rx_buf += 2; - } - else - { - *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - } - else - { - WRITE_REG(hperh->perh->DATA, *tx_buf++); - - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.parity == USART_PARITY_NONE) - *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - } - - hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - - return OK; + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_RX; + + while (hperh->tx_count-- > 0) { + --hperh->rx_count; + + if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + if (hperh->init.parity == USART_PARITY_NONE) { + WRITE_REG(hperh->perh->DATA, (*(uint16_t *)tx_buf & 0x1FF)); + tx_buf += 2; + } + else { + WRITE_REG(hperh->perh->DATA, *tx_buf++); + } + + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.parity == USART_PARITY_NONE) { + *(uint16_t *)rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + rx_buf += 2; + } + else { + *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + } + else { + WRITE_REG(hperh->perh->DATA, *tx_buf++); + + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.parity == USART_PARITY_NONE) + *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + } + + hperh->state = USART_STATE_READY; + __UNLOCK(hperh); + + return OK; } /** @@ -1116,33 +1074,33 @@ ald_status_t ald_usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, ui */ ald_status_t ald_usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { - if (hperh->state != USART_STATE_READY) - return BUSY; + if (hperh->state != USART_STATE_READY) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL) || (size == 0)) + return ERROR; - __LOCK(hperh); + __LOCK(hperh); - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX; - /* The USART Error Interrupts: (Frame error, Noise error, Overrun error) - * are not managed by the USART transmit process to avoid the overrun interrupt - * when the USART mode is configured for transmit and receive "USART_MODE_TX_RX" - * to benefit for the frame error and noise interrupts the USART mode should be - * configured only for transmit "USART_MODE_TX" - * The __ALD_USART_ENABLE_IT(hperh, USART_IT_ERR) can be used to enable the Frame error, - * Noise error interrupt - */ + /* The USART Error Interrupts: (Frame error, Noise error, Overrun error) + * are not managed by the USART transmit process to avoid the overrun interrupt + * when the USART mode is configured for transmit and receive "USART_MODE_TX_RX" + * to benefit for the frame error and noise interrupts the USART mode should be + * configured only for transmit "USART_MODE_TX" + * The __ALD_USART_ENABLE_IT(hperh, USART_IT_ERR) can be used to enable the Frame error, + * Noise error interrupt + */ - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + __UNLOCK(hperh); + ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); - return OK; + return OK; } /** @@ -1155,27 +1113,27 @@ ald_status_t ald_usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint */ ald_status_t ald_usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { - if (hperh->state != USART_STATE_READY) - return BUSY; + if (hperh->state != USART_STATE_READY) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL) || (size == 0)) + return ERROR; - __LOCK(hperh); + __LOCK(hperh); - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_RX; + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_RX; - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + __UNLOCK(hperh); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & (uint16_t)0x01FF)); - return OK; + WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & (uint16_t)0x01FF)); + return OK; } /** @@ -1189,30 +1147,30 @@ ald_status_t ald_usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint */ ald_status_t ald_usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) { - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX_RX; - - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); - - return OK; + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX_RX; + + __UNLOCK(hperh); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + + return OK; } #ifdef ALD_DMA @@ -1227,54 +1185,53 @@ ald_status_t ald_usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_b */ ald_status_t ald_usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - /* Configure callback function */ - hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = usart_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - - /* Configure DMA transmit */ - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) - { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmatx); - - __UNLOCK(hperh); - ald_usart_clear_flag_status(hperh, USART_FLAG_TC); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - - return OK; + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + /* Configure callback function */ + hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = usart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + /* Configure DMA transmit */ + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmatx); + + __UNLOCK(hperh); + ald_usart_clear_flag_status(hperh, USART_FLAG_TC); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + + return OK; } /** @@ -1291,82 +1248,79 @@ ald_status_t ald_usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uin */ ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) { - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_RX; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - /* Configure DMA callback function */ - hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = usart_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - /* Configure DMA receive*/ - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; - hperh->hdmarx.config.channel = rx_channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) - { - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmarx); - - /* Enable the USART transmit DMA channel: the transmit channel is used in order - * to generate in the non-blocking mode the clock to the slave device, - * this mode isn't a simplex receive mode but a full-duplex receive one - */ - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = tx_channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) - { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmatx); - - USART_CLEAR_OREFLAG(hperh); - __UNLOCK(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - - return OK; + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_RX; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + /* Configure DMA callback function */ + hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = usart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + /* Configure DMA receive*/ + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; + hperh->hdmarx.config.channel = rx_channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmarx); + + /* Enable the USART transmit DMA channel: the transmit channel is used in order + * to generate in the non-blocking mode the clock to the slave device, + * this mode isn't a simplex receive mode but a full-duplex receive one + */ + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = tx_channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmatx); + + USART_CLEAR_OREFLAG(hperh); + __UNLOCK(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + + return OK; } /** @@ -1382,86 +1336,83 @@ ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uin * @retval Status, see @ref ald_status_t. */ ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, - uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) + uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) { - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX_RX; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - /* Configure DMA callback function */ - hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = usart_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - hperh->hdmarx.err_cbk = usart_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - /* Configure DMA receive */ - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)rx_buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; - hperh->hdmarx.config.channel = rx_channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) - { - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmarx); - - /* Configure DMA transmit*/ - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)tx_buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = tx_channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) - { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmatx); - - ald_usart_clear_flag_status(hperh, USART_FLAG_TC); - USART_CLEAR_OREFLAG(hperh); - __UNLOCK(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - - return OK; + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX_RX; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + /* Configure DMA callback function */ + hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = usart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + hperh->hdmarx.err_cbk = usart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + /* Configure DMA receive */ + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)rx_buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; + hperh->hdmarx.config.channel = rx_channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmarx); + + /* Configure DMA transmit*/ + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)tx_buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = tx_channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmatx); + + ald_usart_clear_flag_status(hperh, USART_FLAG_TC); + USART_CLEAR_OREFLAG(hperh); + __UNLOCK(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + + return OK; } #endif /** @@ -1481,29 +1432,25 @@ ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_ */ ald_status_t ald_usart_dma_pause(usart_handle_t *hperh) { - __LOCK(hperh); - - if (hperh->state == USART_STATE_BUSY_TX) - { - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - } - else if (hperh->state == USART_STATE_BUSY_RX) - { - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - } - else if (hperh->state == USART_STATE_BUSY_TX_RX) - { - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - } - else - { - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); - return OK; + __LOCK(hperh); + + if (hperh->state == USART_STATE_BUSY_TX) { + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + } + else if (hperh->state == USART_STATE_BUSY_RX) { + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + } + else if (hperh->state == USART_STATE_BUSY_TX_RX) { + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + } + else { + __UNLOCK(hperh); + return ERROR; + } + + __UNLOCK(hperh); + return OK; } /** @@ -1514,31 +1461,27 @@ ald_status_t ald_usart_dma_pause(usart_handle_t *hperh) */ ald_status_t ald_usart_dma_resume(usart_handle_t *hperh) { - __LOCK(hperh); - - if (hperh->state == USART_STATE_BUSY_TX) - { - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - } - else if (hperh->state == USART_STATE_BUSY_RX) - { - USART_CLEAR_OREFLAG(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - } - else if (hperh->state == USART_STATE_BUSY_TX_RX) - { - USART_CLEAR_OREFLAG(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - } - else - { - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); - return OK; + __LOCK(hperh); + + if (hperh->state == USART_STATE_BUSY_TX) { + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + } + else if (hperh->state == USART_STATE_BUSY_RX) { + USART_CLEAR_OREFLAG(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + } + else if (hperh->state == USART_STATE_BUSY_TX_RX) { + USART_CLEAR_OREFLAG(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + } + else { + __UNLOCK(hperh); + return ERROR; + } + + __UNLOCK(hperh); + return OK; } /** @@ -1549,11 +1492,11 @@ ald_status_t ald_usart_dma_resume(usart_handle_t *hperh) */ ald_status_t ald_usart_dma_stop(usart_handle_t *hperh) { - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - hperh->state = USART_STATE_READY; - return OK; + hperh->state = USART_STATE_READY; + return OK; } #endif /** @@ -1564,102 +1507,87 @@ ald_status_t ald_usart_dma_stop(usart_handle_t *hperh) */ void ald_usart_irq_handler(usart_handle_t *hperh) { - uint32_t flag; - uint32_t source; - - /* Handle parity error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_PE); - source = ald_usart_get_it_status(hperh, USART_IT_PE); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= USART_ERROR_PE; - - /* Handle frame error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_FE); - source = ald_usart_get_it_status(hperh, USART_IT_ERR); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= USART_ERROR_FE; - - /* Handle noise error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_NE); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= USART_ERROR_NE; - - /* Handle overrun error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_ORE); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= USART_ERROR_ORE; - - /* Handle idle error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_IDLE); - source = ald_usart_get_it_status(hperh, USART_IT_IDLE); - - if ((flag != RESET) && (source != RESET)) - __usart_recv_frame_cplt(hperh); - - /* Handle asynchronous */ - if (READ_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK) == 0) - { - /* Receiver */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE); - source = ald_usart_get_it_status(hperh, USART_IT_RXNE); - - if ((flag != RESET) && (source != RESET)) - __usart_recv_by_it(hperh); - - /* Transmitter */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE); - source = ald_usart_get_it_status(hperh, USART_IT_TXE); - - if ((flag != RESET) && (source != RESET)) - __usart_send_by_it(hperh); - } - else /* Handle synchronous */ - { - /* Receiver */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE); - source = ald_usart_get_it_status(hperh, USART_IT_RXNE); - - if ((flag != RESET) && (source != RESET)) - { - if (hperh->state == USART_STATE_BUSY_RX) - __usart_recv_by_it_sync(hperh); - else - __usart_send_recv_by_it_sync(hperh); - } - - /* Transmitter */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE); - source = ald_usart_get_it_status(hperh, USART_IT_TXE); - - if ((flag != RESET) && (source != RESET)) - { - if (hperh->state == USART_STATE_BUSY_TX) - __usart_send_by_it(hperh); - else - __usart_send_recv_by_it_sync(hperh); - } - } - - /* Handle transmitter end */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_TC); - source = ald_usart_get_it_status(hperh, USART_IT_TC); - - if ((flag != RESET) && (source != RESET)) - __usart_end_send_by_it(hperh); - - /* Handle error */ - if (hperh->err_code != USART_ERROR_NONE) - { - USART_CLEAR_PEFLAG(hperh); - hperh->state = USART_STATE_READY; - - if (hperh->error_cbk != NULL) - hperh->error_cbk(hperh); - } + uint32_t flag; + uint32_t source; + + /* Handle parity error */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_PE); + source = ald_usart_get_it_status(hperh, USART_IT_PE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= USART_ERROR_PE; + + /* Handle frame error */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_FE); + source = ald_usart_get_it_status(hperh, USART_IT_ERR); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= USART_ERROR_FE; + + /* Handle noise error */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_NE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= USART_ERROR_NE; + + /* Handle overrun error */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_ORE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= USART_ERROR_ORE; + + /* Handle idle error */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_IDLE); + source = ald_usart_get_it_status(hperh, USART_IT_IDLE); + if ((flag != RESET) && (source != RESET)) + __usart_recv_frame_cplt(hperh); + + /* Handle asynchronous */ + if (READ_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK) == 0) { + /* Receiver */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE); + source = ald_usart_get_it_status(hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) + __usart_recv_by_it(hperh); + + /* Transmitter */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE); + source = ald_usart_get_it_status(hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) + __usart_send_by_it(hperh); + } + else { /* Handle synchronous */ + /* Receiver */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE); + source = ald_usart_get_it_status(hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) { + if (hperh->state == USART_STATE_BUSY_RX) + __usart_recv_by_it_sync(hperh); + else + __usart_send_recv_by_it_sync(hperh); + } + + /* Transmitter */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE); + source = ald_usart_get_it_status(hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) { + if (hperh->state == USART_STATE_BUSY_TX) + __usart_send_by_it(hperh); + else + __usart_send_recv_by_it_sync(hperh); + } + } + + /* Handle transmitter end */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_TC); + source = ald_usart_get_it_status(hperh, USART_IT_TC); + if ((flag != RESET) && (source != RESET)) + __usart_end_send_by_it(hperh); + + /* Handle error */ + if (hperh->err_code != USART_ERROR_NONE) { + USART_CLEAR_PEFLAG(hperh); + hperh->state = USART_STATE_READY; + + if (hperh->error_cbk != NULL) + hperh->error_cbk(hperh); + } } /** @@ -1701,16 +1629,16 @@ void ald_usart_irq_handler(usart_handle_t *hperh) */ ald_status_t ald_usart_multi_processor_enter_mute_mode(usart_handle_t *hperh) { - assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART(hperh->perh)); - __LOCK(hperh); + __LOCK(hperh); - hperh->state = USART_STATE_BUSY; - SET_BIT(hperh->perh->CON0, USART_CON0_RXWK_MSK); - hperh->state = USART_STATE_READY; + hperh->state = USART_STATE_BUSY; + SET_BIT(hperh->perh->CON0, USART_CON0_RXWK_MSK); + hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - return OK; + __UNLOCK(hperh); + return OK; } /** @@ -1721,16 +1649,16 @@ ald_status_t ald_usart_multi_processor_enter_mute_mode(usart_handle_t *hperh) */ ald_status_t ald_usart_multi_processor_exit_mute_mode(usart_handle_t *hperh) { - assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART(hperh->perh)); - __LOCK(hperh); + __LOCK(hperh); - hperh->state = USART_STATE_BUSY; - CLEAR_BIT(hperh->perh->CON0, USART_CON0_RXWK_MSK); - hperh->state = USART_STATE_READY; + hperh->state = USART_STATE_BUSY; + CLEAR_BIT(hperh->perh->CON0, USART_CON0_RXWK_MSK); + hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - return OK; + __UNLOCK(hperh); + return OK; } /** @@ -1741,15 +1669,15 @@ ald_status_t ald_usart_multi_processor_exit_mute_mode(usart_handle_t *hperh) */ ald_status_t ald_usart_half_duplex_enable_send(usart_handle_t *hperh) { - __LOCK(hperh); + __LOCK(hperh); - hperh->state = USART_STATE_BUSY; - SET_BIT(hperh->perh->CON0, USART_CON0_RXEN_MSK); - SET_BIT(hperh->perh->CON0, USART_CON0_TXEN_MSK); - hperh->state = USART_STATE_READY; + hperh->state = USART_STATE_BUSY; + SET_BIT(hperh->perh->CON0, USART_CON0_RXEN_MSK); + SET_BIT(hperh->perh->CON0, USART_CON0_TXEN_MSK); + hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - return OK; + __UNLOCK(hperh); + return OK; } /** @@ -1760,15 +1688,15 @@ ald_status_t ald_usart_half_duplex_enable_send(usart_handle_t *hperh) */ ald_status_t ald_usart_half_duplex_enable_recv(usart_handle_t *hperh) { - __LOCK(hperh); + __LOCK(hperh); - hperh->state = USART_STATE_BUSY; - SET_BIT(hperh->perh->CON0, USART_CON0_RXEN_MSK); - SET_BIT(hperh->perh->CON0, USART_CON0_TXEN_MSK); - hperh->state = USART_STATE_READY; + hperh->state = USART_STATE_BUSY; + SET_BIT(hperh->perh->CON0, USART_CON0_RXEN_MSK); + SET_BIT(hperh->perh->CON0, USART_CON0_TXEN_MSK); + hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - return OK; + __UNLOCK(hperh); + return OK; } /** @@ -1785,16 +1713,16 @@ ald_status_t ald_usart_half_duplex_enable_recv(usart_handle_t *hperh) */ void ald_usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state) { - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_DMAREQ(req)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_DMAREQ(req)); + assert_param(IS_FUNC_STATE(state)); - if (state != DISABLE) - SET_BIT(hperh->perh->CON2, req); - else - CLEAR_BIT(hperh->perh->CON2, req); + if (state != DISABLE) + SET_BIT(hperh->perh->CON2, req); + else + CLEAR_BIT(hperh->perh->CON2, req); - return; + return; } /** @@ -1818,39 +1746,37 @@ void ald_usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_f */ void ald_usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state) { - uint8_t idx; - - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_CONFIG_IT(it)); - assert_param(IS_FUNC_STATE(state)); - - idx = (it >> 16) & 0x7; - it &= 0xFFFF; - - if (state) - { - if (idx == 1) - SET_BIT(hperh->perh->CON0, it); - else if (idx == 2) - SET_BIT(hperh->perh->CON1, it); - else if (idx == 4) - SET_BIT(hperh->perh->CON2, it); - else - ; - } - else - { - if (idx == 1) - CLEAR_BIT(hperh->perh->CON0, it); - else if (idx == 2) - CLEAR_BIT(hperh->perh->CON1, it); - else if (idx == 4) - CLEAR_BIT(hperh->perh->CON2, it); - else - ; - } - - return; + uint8_t idx; + + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_CONFIG_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + idx = (it >> 16) & 0x7; + it &= 0xFFFF; + + if (state) { + if (idx == 1) + SET_BIT(hperh->perh->CON0, it); + else if (idx == 2) + SET_BIT(hperh->perh->CON1, it); + else if (idx == 4) + SET_BIT(hperh->perh->CON2, it); + else + ; + } + else { + if (idx == 1) + CLEAR_BIT(hperh->perh->CON0, it); + else if (idx == 2) + CLEAR_BIT(hperh->perh->CON1, it); + else if (idx == 4) + CLEAR_BIT(hperh->perh->CON2, it); + else + ; + } + + return; } /** @brief Check whether the specified USART flag is set or not. @@ -1864,15 +1790,15 @@ void ald_usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_ */ flag_status_t ald_usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag) { - flag_status_t status = RESET; + flag_status_t status = RESET; - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_FLAG(flag)); + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_FLAG(flag)); - if (READ_BIT(hperh->perh->STAT, flag)) - status = SET; + if (READ_BIT(hperh->perh->STAT, flag)) + status = SET; - return status; + return status; } /** @brief Clear the specified USART pending flags. @@ -1894,10 +1820,10 @@ flag_status_t ald_usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag */ void ald_usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag) { - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_CLEAR_FLAG(flag)); + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_CLEAR_FLAG(flag)); - CLEAR_BIT(hperh->perh->STAT, flag); + CLEAR_BIT(hperh->perh->STAT, flag); } /** @@ -1922,42 +1848,37 @@ void ald_usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag) */ it_status_t ald_usart_get_it_status(usart_handle_t *hperh, usart_it_t it) { - uint8_t idx; - it_status_t status = RESET; - - /* Check the parameters */ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_GET_IT(it)); - - idx = (it >> 16) & 0x7; - it &= 0xFFFF; - - if (idx == 0) - { - if (READ_BIT(hperh->perh->STAT, it)) - status = SET; - } - else if (idx == 1) - { - if (READ_BIT(hperh->perh->CON0, it)) - status = SET; - } - else if (idx == 2) - { - if (READ_BIT(hperh->perh->CON1, it)) - status = SET; - } - else if (idx == 4) - { - if (READ_BIT(hperh->perh->CON2, it)) - status = SET; - } - else - { - /* do nothing */ - } - - return status; + uint8_t idx; + it_status_t status = RESET; + + /* Check the parameters */ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_GET_IT(it)); + + idx = (it >> 16) & 0x7; + it &= 0xFFFF; + + if (idx == 0) { + if (READ_BIT(hperh->perh->STAT, it)) + status = SET; + } + else if (idx == 1) { + if (READ_BIT(hperh->perh->CON0, it)) + status = SET; + } + else if (idx == 2) { + if (READ_BIT(hperh->perh->CON1, it)) + status = SET; + } + else if (idx == 4) { + if (READ_BIT(hperh->perh->CON2, it)) + status = SET; + } + else { + /* do nothing */ + } + + return status; } /** @@ -1990,7 +1911,7 @@ it_status_t ald_usart_get_it_status(usart_handle_t *hperh, usart_it_t it) */ usart_state_t ald_usart_get_state(usart_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** @@ -2001,7 +1922,7 @@ usart_state_t ald_usart_get_state(usart_handle_t *hperh) */ uint32_t ald_usart_get_error(usart_handle_t *hperh) { - return hperh->err_code; + return hperh->err_code; } /** @@ -2025,11 +1946,11 @@ uint32_t ald_usart_get_error(usart_handle_t *hperh) */ static void usart_dma_send_cplt(void *arg) { - usart_handle_t *hperh = (usart_handle_t *)arg; + usart_handle_t *hperh = (usart_handle_t *)arg; - hperh->tx_count = 0; - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE); + hperh->tx_count = 0; + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE); } /** @@ -2040,14 +1961,14 @@ static void usart_dma_send_cplt(void *arg) */ static void usart_dma_recv_cplt(void *arg) { - usart_handle_t *hperh = (usart_handle_t *)arg; + usart_handle_t *hperh = (usart_handle_t *)arg; - hperh->rx_count = 0; - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + hperh->rx_count = 0; + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - if (hperh->rx_cplt_cbk != NULL) - hperh->rx_cplt_cbk(hperh); + if (hperh->rx_cplt_cbk != NULL) + hperh->rx_cplt_cbk(hperh); } /** @@ -2058,18 +1979,18 @@ static void usart_dma_recv_cplt(void *arg) */ static void usart_dma_error(void *arg) { - usart_handle_t *hperh = (usart_handle_t *)arg; + usart_handle_t *hperh = (usart_handle_t *)arg; - hperh->rx_count = 0; - hperh->tx_count = 0; - hperh->state = USART_STATE_READY; - hperh->err_code |= USART_ERROR_DMA; + hperh->rx_count = 0; + hperh->tx_count = 0; + hperh->state = USART_STATE_READY; + hperh->err_code |= USART_ERROR_DMA; - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - if (hperh->error_cbk != NULL) - hperh->error_cbk(hperh); + if (hperh->error_cbk != NULL) + hperh->error_cbk(hperh); } #endif /** @@ -2083,27 +2004,25 @@ static void usart_dma_error(void *arg) */ static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout) { - uint32_t tick; + uint32_t tick; - if (timeout == 0) - return OK; + if (timeout == 0) + return OK; - tick = ald_get_tick(); + tick = ald_get_tick(); - while ((ald_usart_get_flag_status(hperh, flag)) != status) - { - if (((ald_get_tick()) - tick) > timeout) - { - ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + while ((ald_usart_get_flag_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) { + ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - return TIMEOUT; - } - } + return TIMEOUT; + } + } - return OK; + return OK; } /** @@ -2114,26 +2033,23 @@ static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, fl */ static ald_status_t __usart_send_by_it(usart_handle_t *hperh) { - if ((hperh->state != USART_STATE_BUSY_TX) && (hperh->state != USART_STATE_BUSY_TX_RX)) - return BUSY; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) - { - WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & (uint16_t)0x01FF)); - hperh->tx_buf += 2; - } - else - { - WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); - } - - if (--hperh->tx_count == 0) - { - ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE); - } - - return OK; + if ((hperh->state != USART_STATE_BUSY_TX) && (hperh->state != USART_STATE_BUSY_TX_RX)) + return BUSY; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) { + WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & (uint16_t)0x01FF)); + hperh->tx_buf += 2; + } + else { + WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); + } + + if (--hperh->tx_count == 0) { + ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE); + } + + return OK; } @@ -2145,13 +2061,13 @@ static ald_status_t __usart_send_by_it(usart_handle_t *hperh) */ static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh) { - ald_usart_interrupt_config(hperh, USART_IT_TC, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); + ald_usart_interrupt_config(hperh, USART_IT_TC, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); - if (hperh->tx_cplt_cbk != NULL) - hperh->tx_cplt_cbk(hperh); + if (hperh->tx_cplt_cbk != NULL) + hperh->tx_cplt_cbk(hperh); - return OK; + return OK; } /** @@ -2162,49 +2078,43 @@ static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh) */ static ald_status_t __usart_recv_by_it(usart_handle_t *hperh) { - if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX)) - return BUSY; - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - if (hperh->init.parity == USART_PARITY_NONE) - { - *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & (uint16_t)0x01FF); - hperh->rx_buf += 2; - } - else - { - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - } - else - { - if (hperh->init.parity == USART_PARITY_NONE) - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - - if (__frame_mode && ((ald_usart_get_it_status(hperh, USART_IT_IDLE)) == RESET)) - ald_usart_interrupt_config(hperh, USART_IT_IDLE, ENABLE); - - if (--hperh->rx_count == 0) - { - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - __frame_mode = 0; - - if (hperh->state == USART_STATE_READY) - { - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - } - - if (hperh->rx_cplt_cbk != NULL) - hperh->rx_cplt_cbk(hperh); - } - - return OK; + if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX)) + return BUSY; + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + if (hperh->init.parity == USART_PARITY_NONE) { + *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & (uint16_t)0x01FF); + hperh->rx_buf += 2; + } + else { + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + } + else { + if (hperh->init.parity == USART_PARITY_NONE) + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + + if (__frame_mode && ((ald_usart_get_it_status(hperh, USART_IT_IDLE)) == RESET)) + ald_usart_interrupt_config(hperh, USART_IT_IDLE, ENABLE); + + if (--hperh->rx_count == 0) { + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + __frame_mode = 0; + + if (hperh->state == USART_STATE_READY) { + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + } + + if (hperh->rx_cplt_cbk != NULL) + hperh->rx_cplt_cbk(hperh); + } + + return OK; } /** @@ -2215,26 +2125,25 @@ static ald_status_t __usart_recv_by_it(usart_handle_t *hperh) */ static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh) { - if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX)) - return BUSY; + if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX)) + return BUSY; - ald_usart_interrupt_config(hperh, USART_IT_IDLE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + ald_usart_interrupt_config(hperh, USART_IT_IDLE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - __frame_mode = 0; - hperh->rx_size -= hperh->rx_count; + __frame_mode = 0; + hperh->rx_size -= hperh->rx_count; - if (hperh->state == USART_STATE_READY) - { - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - } + if (hperh->state == USART_STATE_READY) { + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + } - if (hperh->rx_cplt_cbk != NULL) - hperh->rx_cplt_cbk(hperh); + if (hperh->rx_cplt_cbk != NULL) + hperh->rx_cplt_cbk(hperh); - return OK; + return OK; } @@ -2247,48 +2156,43 @@ static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh) */ static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh) { - if (hperh->state != USART_STATE_BUSY_RX) - return BUSY; - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - - if (hperh->init.parity == USART_PARITY_NONE) - { - *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - hperh->rx_buf += 2; - } - else - { - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - - if (--hperh->rx_count != 0x00) - WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF)); - } - else - { - if (hperh->init.parity == USART_PARITY_NONE) - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - - if (--hperh->rx_count != 0x00) - hperh->perh->DATA = (DUMMY_DATA & 0xFF); - } - - if (hperh->rx_count == 0) - { - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - hperh->state = USART_STATE_READY; - - if (hperh->rx_cplt_cbk != NULL) - hperh->rx_cplt_cbk(hperh); - } - - return OK; + if (hperh->state != USART_STATE_BUSY_RX) + return BUSY; + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + + if (hperh->init.parity == USART_PARITY_NONE) { + *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + hperh->rx_buf += 2; + } + else { + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + + if (--hperh->rx_count != 0x00) + WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF)); + } + else { + if (hperh->init.parity == USART_PARITY_NONE) + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + + if (--hperh->rx_count != 0x00) + hperh->perh->DATA = (DUMMY_DATA & 0xFF); + } + + if (hperh->rx_count == 0) { + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + hperh->state = USART_STATE_READY; + + if (hperh->rx_cplt_cbk != NULL) + hperh->rx_cplt_cbk(hperh); + } + + return OK; } /** @@ -2299,76 +2203,63 @@ static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh) */ static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh) { - if (hperh->state != USART_STATE_BUSY_TX_RX) - return BUSY; - - if (hperh->tx_count != 0) - { - if (ald_usart_get_flag_status(hperh, USART_FLAG_TXE) != RESET) - { - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - if (hperh->init.parity == USART_PARITY_NONE) - { - WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & 0x1FF)); - hperh->tx_buf += 2; - } - else - { - WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); - } - } - else - { - WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); - } - - if (--hperh->tx_count == 0) - ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); - } - } - - if (hperh->rx_count != 0) - { - if (ald_usart_get_flag_status(hperh, USART_FLAG_RXNE) != RESET) - { - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - if (hperh->init.parity == USART_PARITY_NONE) - { - *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - hperh->rx_buf += 2; - } - else - { - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - } - else - { - if (hperh->init.parity == USART_PARITY_NONE) - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - - --hperh->rx_count; - } - } - - if (hperh->rx_count == 0) - { - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - - hperh->state = USART_STATE_READY; - - if (hperh->tx_rx_cplt_cbk != NULL) - hperh->tx_rx_cplt_cbk(hperh); - } - - return OK; + if (hperh->state != USART_STATE_BUSY_TX_RX) + return BUSY; + + if (hperh->tx_count != 0) { + if (ald_usart_get_flag_status(hperh, USART_FLAG_TXE) != RESET) { + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + if (hperh->init.parity == USART_PARITY_NONE) { + WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & 0x1FF)); + hperh->tx_buf += 2; + } + else { + WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); + } + } + else { + WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); + } + + if (--hperh->tx_count == 0) + ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + } + } + + if (hperh->rx_count != 0) { + if (ald_usart_get_flag_status(hperh, USART_FLAG_RXNE) != RESET) { + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + if (hperh->init.parity == USART_PARITY_NONE) { + *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + hperh->rx_buf += 2; + } + else { + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + } + else { + if (hperh->init.parity == USART_PARITY_NONE) + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + + --hperh->rx_count; + } + } + + if (hperh->rx_count == 0) { + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + + hperh->state = USART_STATE_READY; + + if (hperh->tx_rx_cplt_cbk != NULL) + hperh->tx_rx_cplt_cbk(hperh); + } + + return OK; } /** @@ -2377,79 +2268,59 @@ static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval None */ -static void usart_set_config(usart_handle_t *hperh) +static void usart_set_config (usart_handle_t *hperh) { - uint32_t tmp; - uint32_t integer; - uint32_t fractional; - - /* Check the parameters */ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_BAUDRATE(hperh->init.baud)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); - assert_param(IS_USART_PARITY(hperh->init.parity)); - assert_param(IS_USART_MODE(hperh->init.mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); - - MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS); - tmp = READ_REG(hperh->perh->CON0); - MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS); - - if (hperh->init.parity == USART_PARITY_NONE) - CLEAR_BIT(tmp, USART_CON0_PEN_MSK); - else - SET_BIT(tmp, USART_CON0_PEN_MSK); - - if (hperh->init.parity == USART_PARITY_ODD) - SET_BIT(tmp, USART_CON0_PSEL_MSK); - else - CLEAR_BIT(tmp, USART_CON0_PSEL_MSK); - - WRITE_REG(hperh->perh->CON0, tmp); - MODIFY_REG(hperh->perh->CON2, USART_CON2_RTSEN_MSK, (hperh->init.fctl & 0x1) << USART_CON2_RTSEN_POS); - MODIFY_REG(hperh->perh->CON2, USART_CON2_CTSEN_MSK, ((hperh->init.fctl >> 1) & 0x1) << USART_CON2_CTSEN_POS); - MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS); - MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS); - - if (hperh->init.over_sampling) - SET_BIT(hperh->perh->CON0, (1 << 15)); - - /* Determine the integer part */ - if (READ_BIT(hperh->perh->CON0, (1 << 15))) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); - } - else - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); - } - - tmp = (integer / 100) << 4; - - /* Determine the fractional part */ - fractional = integer - (100 * (tmp >> 4)); - - /* Implement the fractional part in the register */ - if (READ_BIT(hperh->perh->CON0, (1 << 15))) - tmp |= ((((fractional * 8) + 50) / 100) & ((uint8_t)0x07)); - else - tmp |= ((((fractional * 16) + 50) / 100) & ((uint8_t)0x0F)); - - WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp); - return; + uint32_t tmp; + uint32_t integer; + uint32_t fractional; + + /* Check the parameters */ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_BAUDRATE(hperh->init.baud)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_USART_PARITY(hperh->init.parity)); + assert_param(IS_USART_MODE(hperh->init.mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); + + MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS); + tmp = READ_REG(hperh->perh->CON0); + MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS); + + if (hperh->init.parity == USART_PARITY_NONE) + CLEAR_BIT(tmp, USART_CON0_PEN_MSK); + else + SET_BIT(tmp, USART_CON0_PEN_MSK); + + if (hperh->init.parity == USART_PARITY_ODD) + SET_BIT(tmp, USART_CON0_PSEL_MSK); + else + CLEAR_BIT(tmp, USART_CON0_PSEL_MSK); + + WRITE_REG(hperh->perh->CON0, tmp); + MODIFY_REG(hperh->perh->CON2, USART_CON2_RTSEN_MSK, (hperh->init.fctl & 0x1) << USART_CON2_RTSEN_POS); + MODIFY_REG(hperh->perh->CON2, USART_CON2_CTSEN_MSK, ((hperh->init.fctl >> 1) & 0x1) << USART_CON2_CTSEN_POS); + MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS); + MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS); + + /* Determine the integer part */ + integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); + tmp = (integer / 100) << 4; + + /* Determine the fractional part */ + fractional = integer - (100 * (tmp >> 4)); + tmp |= ((((fractional * 16) + 50) / 100) & ((uint8_t)0x0F)); + WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp); + + return; } /** * @} */ - #endif /* ALD_USART */ /** * @} */ - /** * @} */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_wdt.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_wdt.c index acf092a2788b3ff79ca0e9ede781eeb8985f1077..d19a0397abb031fdf8ba01842863540051966999 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_wdt.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_wdt.c @@ -46,18 +46,18 @@ */ void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt) { - assert_param(IS_WWDT_WIN_TYPE(win)); - assert_param(IS_FUNC_STATE(interrupt)); - - WWDT_UNLOCK(); - WRITE_REG(WWDT->LOAD, load); - MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS); - SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK); - SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK); - MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS); - WWDT_LOCK(); - - return; + assert_param(IS_WWDT_WIN_TYPE(win)); + assert_param(IS_FUNC_STATE(interrupt)); + + WWDT_UNLOCK(); + WRITE_REG(WWDT->LOAD, load); + MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS); + SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK); + SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK); + MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS); + WWDT_LOCK(); + + return; } /** @@ -66,11 +66,11 @@ void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt) */ void ald_wwdt_start(void) { - WWDT_UNLOCK(); - SET_BIT(WWDT->CON, WWDT_CON_EN_MSK); - WWDT_LOCK(); + WWDT_UNLOCK(); + SET_BIT(WWDT->CON, WWDT_CON_EN_MSK); + WWDT_LOCK(); - return; + return; } /** @@ -79,7 +79,7 @@ void ald_wwdt_start(void) */ uint32_t ald_wwdt_get_value(void) { - return WWDT->VALUE; + return WWDT->VALUE; } /** @@ -88,10 +88,10 @@ uint32_t ald_wwdt_get_value(void) */ it_status_t ald_wwdt_get_flag_status(void) { - if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK)) - return SET; + if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK)) + return SET; - return RESET; + return RESET; } /** @@ -100,8 +100,8 @@ it_status_t ald_wwdt_get_flag_status(void) */ void ald_wwdt_clear_flag_status(void) { - WRITE_REG(WWDT->INTCLR, 1); - return; + WRITE_REG(WWDT->INTCLR, 1); + return; } /** @@ -110,11 +110,11 @@ void ald_wwdt_clear_flag_status(void) */ void ald_wwdt_feed_dog(void) { - WWDT_UNLOCK(); - WRITE_REG(WWDT->INTCLR, 0x1); - WWDT_LOCK(); + WWDT_UNLOCK(); + WRITE_REG(WWDT->INTCLR, 0x1); + WWDT_LOCK(); - return; + return; } /** * @} @@ -132,16 +132,16 @@ void ald_wwdt_feed_dog(void) */ void ald_iwdt_init(uint32_t load, type_func_t interrupt) { - assert_param(IS_FUNC_STATE(interrupt)); + assert_param(IS_FUNC_STATE(interrupt)); - IWDT_UNLOCK(); - WRITE_REG(IWDT->LOAD, load); - SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK); - SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK); - MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS); - IWDT_LOCK(); + IWDT_UNLOCK(); + WRITE_REG(IWDT->LOAD, load); + SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK); + SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK); + MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS); + IWDT_LOCK(); - return; + return; } /** @@ -150,11 +150,11 @@ void ald_iwdt_init(uint32_t load, type_func_t interrupt) */ void ald_iwdt_start(void) { - IWDT_UNLOCK(); - SET_BIT(IWDT->CON, IWDT_CON_EN_MSK); - IWDT_LOCK(); + IWDT_UNLOCK(); + SET_BIT(IWDT->CON, IWDT_CON_EN_MSK); + IWDT_LOCK(); - return; + return; } /** @@ -163,7 +163,7 @@ void ald_iwdt_start(void) */ uint32_t ald_iwdt_get_value(void) { - return IWDT->VALUE; + return IWDT->VALUE; } /** @@ -172,10 +172,10 @@ uint32_t ald_iwdt_get_value(void) */ it_status_t ald_iwdt_get_flag_status(void) { - if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK)) - return SET; + if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK)) + return SET; - return RESET; + return RESET; } /** @@ -184,8 +184,8 @@ it_status_t ald_iwdt_get_flag_status(void) */ void ald_iwdt_clear_flag_status(void) { - WRITE_REG(IWDT->INTCLR, 1); - return; + WRITE_REG(IWDT->INTCLR, 1); + return; } /** @@ -194,11 +194,11 @@ void ald_iwdt_clear_flag_status(void) */ void ald_iwdt_feed_dog(void) { - IWDT_UNLOCK(); - WRITE_REG(IWDT->INTCLR, 1); - IWDT_LOCK(); + IWDT_UNLOCK(); + WRITE_REG(IWDT->INTCLR, 1); + IWDT_LOCK(); - return; + return; } /** * @} diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/utils.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/utils.c index 596bc38fbf686078a559693810e977ca37da7955..e406c53afc91cc9edf514b0fcd85761325f24f7f 100644 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/utils.c +++ b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/utils.c @@ -14,6 +14,7 @@ ********************************************************************************* */ +#include #include "utils.h" #include "ald_dma.h" #include "ald_cmu.h" @@ -42,9 +43,9 @@ #define __ALD_VERSION_SUB2 (0x00) /**< [15:8] sub2 version */ #define __ALD_VERSION_RC (0x00) /**< [7:0] release candidate */ #define __ALD_VERSION ((__ALD_VERSION_MAIN << 24) | \ - (__ALD_VERSION_SUB1 << 16) | \ - (__ALD_VERSION_SUB2 << 8 ) | \ - (__ALD_VERSION_RC)) + (__ALD_VERSION_SUB1 << 16) | \ + (__ALD_VERSION_SUB2 << 8 ) | \ + (__ALD_VERSION_RC)) /** * @} */ @@ -110,12 +111,12 @@ uint32_t __systick_interval = SYSTICK_INTERVAL_1MS; */ void ald_cmu_init(void) { - ald_cmu_clock_config_default(); - ald_tick_init(TICK_INT_PRIORITY); + ald_cmu_clock_config_default(); + ald_tick_init(TICK_INT_PRIORITY); #ifdef ALD_DMA - ald_dma_init(DMA0); + ald_dma_init(DMA0); #endif - return; + return; } /** @@ -134,13 +135,13 @@ void ald_cmu_init(void) */ __weak void ald_tick_init(uint32_t prio) { - /* Configure the SysTick IRQ */ - SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS); + /* Configure the SysTick IRQ */ + SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS); - if (prio != 3) - NVIC_SetPriority(SysTick_IRQn, prio); + if (prio != 3) + NVIC_SetPriority(SysTick_IRQn, prio); - return; + return; } /** @@ -154,15 +155,15 @@ __weak void ald_tick_init(uint32_t prio) */ void ald_systick_interval_select(systick_interval_t value) { - assert_param(IS_SYSTICK_INTERVAL(value)); + assert_param(IS_SYSTICK_INTERVAL(value)); - SysTick_Config(ald_cmu_get_sys_clock() / value); - __systick_interval = value; + SysTick_Config(ald_cmu_get_sys_clock() / value); + __systick_interval = value; - if (TICK_INT_PRIORITY != 3) - NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY); + if (TICK_INT_PRIORITY != 3) + NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY); - return; + return; } /** * @} @@ -185,6 +186,9 @@ void ald_systick_interval_select(systick_interval_t value) (+) Configure the interrupt (+) Provide system tick value (+) Get CPU ID + (+) Get UID + (+) Get CHIPID + @endverbatim * @{ */ @@ -200,7 +204,7 @@ void ald_systick_interval_select(systick_interval_t value) */ __weak void ald_inc_tick_weak(void) { - ++lib_tick; + ++lib_tick; } /** @@ -211,8 +215,8 @@ __weak void ald_inc_tick_weak(void) */ __weak void ald_systick_irq_cbk(void) { - /* do nothing */ - return; + /* do nothing */ + return; } /** @@ -221,10 +225,10 @@ __weak void ald_systick_irq_cbk(void) */ __isr__ void ald_inc_tick(void) { - ald_inc_tick_weak(); - ald_systick_irq_cbk(); + ald_inc_tick_weak(); + ald_systick_irq_cbk(); - return; + return; } /** @@ -235,7 +239,7 @@ __isr__ void ald_inc_tick(void) */ __weak uint32_t ald_get_tick(void) { - return lib_tick; + return lib_tick; } /** @@ -251,36 +255,35 @@ __weak uint32_t ald_get_tick(void) */ __weak void ald_delay_ms(__IO uint32_t delay) { - uint32_t tick, __delay; + uint32_t tick, __delay; - switch (__systick_interval) - { - case SYSTICK_INTERVAL_1MS: - __delay = delay; - break; + switch (__systick_interval) { + case SYSTICK_INTERVAL_1MS: + __delay = delay; + break; - case SYSTICK_INTERVAL_10MS: - __delay = delay / 10; - break; + case SYSTICK_INTERVAL_10MS: + __delay = delay / 10; + break; - case SYSTICK_INTERVAL_100MS: - __delay = delay / 100; - break; + case SYSTICK_INTERVAL_100MS: + __delay = delay / 100; + break; - case SYSTICK_INTERVAL_1000MS: - __delay = delay / 1000; - break; + case SYSTICK_INTERVAL_1000MS: + __delay = delay / 1000; + break; - default: - __delay = delay; - break; - } + default: + __delay = delay; + break; + } - tick = ald_get_tick(); - __delay = __delay == 0 ? 1 : __delay; + tick = ald_get_tick(); + __delay = __delay == 0 ? 1 : __delay; - while ((ald_get_tick() - tick) < __delay) - ; + while ((ald_get_tick() - tick) < __delay) + ; } /** @@ -295,7 +298,7 @@ __weak void ald_delay_ms(__IO uint32_t delay) */ __weak void ald_suspend_tick(void) { - CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } /** @@ -310,7 +313,7 @@ __weak void ald_suspend_tick(void) */ __weak void ald_resume_tick(void) { - SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } /** @@ -319,7 +322,7 @@ __weak void ald_resume_tick(void) */ uint32_t ald_get_ald_version(void) { - return __ALD_VERSION; + return __ALD_VERSION; } /** @@ -332,28 +335,24 @@ uint32_t ald_get_ald_version(void) */ ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout) { - uint32_t tick = ald_get_tick(); - - assert_param(timeout > 0); - - if (status == SET) - { - while (!(IS_BIT_SET(*reg, bit))) - { - if (((ald_get_tick()) - tick) > timeout) - return TIMEOUT; - } - } - else - { - while ((IS_BIT_SET(*reg, bit))) - { - if (((ald_get_tick()) - tick) > timeout) - return TIMEOUT; - } - } - - return OK; + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + if (status == SET) { + while (!(IS_BIT_SET(*reg, bit))) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + else { + while ((IS_BIT_SET(*reg, bit))) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + + return OK; } /** @@ -367,20 +366,18 @@ ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, ui */ void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) { - assert_param(IS_FUNC_STATE(status)); - assert_param(IS_PRIO(prio)); - - if (status == ENABLE) - { - NVIC_SetPriority(irq, prio); - NVIC_EnableIRQ(irq); - } - else - { - NVIC_DisableIRQ(irq); - } - - return; + assert_param(IS_FUNC_STATE(status)); + assert_param(IS_PRIO(prio)); + + if (status == ENABLE) { + NVIC_SetPriority(irq, prio); + NVIC_EnableIRQ(irq); + } + else { + NVIC_DisableIRQ(irq); + } + + return; } /** @@ -389,10 +386,10 @@ void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) */ uint32_t ald_mcu_get_tick(void) { - uint32_t load = SysTick->LOAD; - uint32_t val = SysTick->VAL; + uint32_t load = SysTick->LOAD; + uint32_t val = SysTick->VAL; - return (load - val); + return (load - val); } /** @@ -401,9 +398,31 @@ uint32_t ald_mcu_get_tick(void) */ uint32_t ald_mcu_get_cpu_id(void) { - return SCB->CPUID; + return SCB->CPUID; +} + +/** + * @brief Get the UID. + * @param buf: Pointer to UID, len: 12Bytes(96-bits) + * @retval None + */ +void ald_mcu_get_uid(uint8_t *buf) +{ + memcpy(&buf[0], (void *)MCU_UID0_ADDR, 4); + memcpy(&buf[4], (void *)MCU_UID1_ADDR, 4); + memcpy(&buf[8], (void *)MCU_UID2_ADDR, 4); + + return; } +/** + * @brief Get the CHIPID + * @retval CHPID + */ +uint32_t ald_mcu_get_chipid(void) +{ + return (uint32_t)*(uint32_t *)MCU_CHIPID_ADDR; +} /** * @} */ diff --git a/bsp/essemi/es32f0334/project.uvoptx b/bsp/essemi/es32f0334/project.uvoptx index d064f068ab9f123e43b6e7a082f87b395342e1d2..1282ebe1958a185ec5f1a68bc87994fa4b554bd7 100644 --- a/bsp/essemi/es32f0334/project.uvoptx +++ b/bsp/essemi/es32f0334/project.uvoptx @@ -73,7 +73,7 @@ 0 - 0 + 1 0 1 @@ -101,7 +101,9 @@ 0 0 1 - 2 + 0 + 0 + 3 @@ -118,7 +120,7 @@ 0 CMSIS_AGDI - -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0ES32F033x.FLM -FS00 -FL040000 -FP0($$Device:ES32F0334LT$Flash\ES32F033x.FLM) + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0ES32F033x.FLM -FS00 -FL040000 -FP0($$Device:ES32F0334LT$Flash\ES32F033x.FLM) 0 @@ -170,7 +172,967 @@ + + + + + + Applications + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + cpu + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + cpuport.c + 0 + 0 + + + 2 + 6 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + context_rvds.S + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\hwtimer\hwtimer.c + hwtimer.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\i2c\i2c_core.c + i2c_core.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\i2c\i2c_dev.c + i2c_dev.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\i2c\i2c-bit-ops.c + i2c-bit-ops.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\adc.c + adc.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\rt_drv_pwm.c + rt_drv_pwm.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\pm\pm.c + pm.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\rtc\rtc.c + rtc.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\spi\spi_core.c + spi_core.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\spi\spi_dev.c + spi_dev.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 4 + 26 + 1 + 0 + 0 + 0 + drivers\board.c + board.c + 0 + 0 + + + 4 + 27 + 1 + 0 + 0 + 0 + drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 4 + 28 + 1 + 0 + 0 + 0 + drivers\drv_uart.c + drv_uart.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 5 + 29 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 6 + 32 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 6 + 33 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\..\src\device.c + device.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + ..\..\..\src\signal.c + signal.c + 0 + 0 + + + 6 + 44 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 6 + 45 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 7 + 46 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_acmp.c + ald_acmp.c + 0 + 0 + + + 7 + 47 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_adc.c + ald_adc.c + 0 + 0 + + + 7 + 48 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_bkpc.c + ald_bkpc.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_calc.c + ald_calc.c + 0 + 0 + + + 7 + 50 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_cmu.c + ald_cmu.c + 0 + 0 + + + 7 + 51 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_crc.c + ald_crc.c + 0 + 0 + + + 7 + 52 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_crypt.c + ald_crypt.c + 0 + 0 + + + 7 + 53 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_dma.c + ald_dma.c + 0 + 0 + + + 7 + 54 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_flash.c + ald_flash.c + 0 + 0 + + + 7 + 55 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + ald_flash_ext.c + 0 + 0 + + + 7 + 56 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_gpio.c + ald_gpio.c + 0 + 0 + + + 7 + 57 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_i2c.c + ald_i2c.c + 0 + 0 + + + 7 + 58 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_iap.c + ald_iap.c + 0 + 0 + + + 7 + 59 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lcd.c + ald_lcd.c + 0 + 0 + + + 7 + 60 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lptim.c + ald_lptim.c + 0 + 0 + + + 7 + 61 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lpuart.c + ald_lpuart.c + 0 + 0 + + + 7 + 62 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_pis.c + ald_pis.c + 0 + 0 + + + 7 + 63 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_pmu.c + ald_pmu.c + 0 + 0 + + + 7 + 64 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_rmu.c + ald_rmu.c + 0 + 0 + + + 7 + 65 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_rtc.c + ald_rtc.c + 0 + 0 + + + 7 + 66 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_smartcard.c + ald_smartcard.c + 0 + 0 + + + 7 + 67 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_spi.c + ald_spi.c + 0 + 0 + + + 7 + 68 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_timer.c + ald_timer.c + 0 + 0 + + + 7 + 69 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_trng.c + ald_trng.c + 0 + 0 + + + 7 + 70 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_tsense.c + ald_tsense.c + 0 + 0 + + + 7 + 71 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_uart.c + ald_uart.c + 0 + 0 + + + 7 + 72 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_usart.c + ald_usart.c + 0 + 0 + + + 7 + 73 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_wdt.c + ald_wdt.c + 0 + 0 + + + 7 + 74 + 1 + 0 + 0 + 0 + libraries\ES32F033x_ALD_StdPeriph_Driver\Source\utils.c + utils.c + 0 + 0 + + + 7 + 75 + 2 + 0 + 0 + 0 + libraries\CMSIS\Device\EastSoft\es32f033x\Startup\keil\startup_es32f033x.s + startup_es32f033x.s + 0 + 0 + + + diff --git a/bsp/essemi/es32f0334/project.uvprojx b/bsp/essemi/es32f0334/project.uvprojx index d5f76bed8f14fb0ea82d5d157e9b130ec7325110..6e1b30253a3deb4eb268eaaa39804ab5f5fda302 100644 --- a/bsp/essemi/es32f0334/project.uvprojx +++ b/bsp/essemi/es32f0334/project.uvprojx @@ -1,41 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread 0x4 ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 ES32F0334LT Eastsoft - Eastsoft.ES32_DFP.1.0.1 + Eastsoft.ES32_DFP.7.2350 http://www.essemi.com IRAM(0x20000000,0x00008000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0ES32F033x -FS00 -FL040000 -FP0($$Device:ES32F0334LT$Flash\ES32F033x.FLM)) 0 $$Device:ES32F0334LT$Device\Include\es32f033x.h - - - - - - - - - + + + + + + + + + $$Device:ES32F0334LT$SVD\es32f0xx.svd 0 0 - - - - - + + + + + 0 0 @@ -57,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -67,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -78,14 +83,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -99,8 +104,8 @@ 0 0 3 - - + + 1 @@ -134,10 +139,10 @@ 1 BIN\UL2CM3.DLL "" () - - - - + + + + 0 @@ -170,7 +175,7 @@ 0 0 "Cortex-M0" - + 0 0 0 @@ -179,6 +184,7 @@ 0 0 0 + 0 0 0 8 @@ -302,7 +308,7 @@ 0x0 - + 1 @@ -319,6 +325,7 @@ 0 0 1 + 0 0 1 1 @@ -328,10 +335,10 @@ 0 0 - + ES32F033x - - .;..\..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\es32f033x\Include;libraries\CMSIS\Include;libraries\ES32F033x_ALD_StdPeriph_Driver\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common + + applications;.;drivers;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;libraries\CMSIS\Device\EastSoft\es32f033x\Include;libraries\CMSIS\Include;libraries\ES32F033x_ALD_StdPeriph_Driver\Include @@ -346,10 +353,10 @@ 0 0 - - - - + + + + @@ -361,17 +368,266 @@ 0 0x08000000 0x20000000 - - - - - - - + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + cpu + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + hwtimer.c + 1 + ..\..\..\components\drivers\hwtimer\hwtimer.c + + + i2c_core.c + 1 + ..\..\..\components\drivers\i2c\i2c_core.c + + + i2c_dev.c + 1 + ..\..\..\components\drivers\i2c\i2c_dev.c + + + i2c-bit-ops.c + 1 + ..\..\..\components\drivers\i2c\i2c-bit-ops.c + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + adc.c + 1 + ..\..\..\components\drivers\misc\adc.c + + + rt_drv_pwm.c + 1 + ..\..\..\components\drivers\misc\rt_drv_pwm.c + + + pm.c + 1 + ..\..\..\components\drivers\pm\pm.c + + + rtc.c + 1 + ..\..\..\components\drivers\rtc\rtc.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + spi_core.c + 1 + ..\..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\..\components\drivers\spi\spi_dev.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + Kernel @@ -380,92 +636,66 @@ 1 ..\..\..\src\clock.c - - components.c 1 ..\..\..\src\components.c - - device.c 1 ..\..\..\src\device.c - - idle.c 1 ..\..\..\src\idle.c - - ipc.c 1 ..\..\..\src\ipc.c - - irq.c 1 ..\..\..\src\irq.c - - kservice.c 1 ..\..\..\src\kservice.c - - mem.c 1 ..\..\..\src\mem.c - - mempool.c 1 ..\..\..\src\mempool.c - - object.c 1 ..\..\..\src\object.c - - scheduler.c 1 ..\..\..\src\scheduler.c - - signal.c 1 ..\..\..\src\signal.c - - thread.c 1 ..\..\..\src\thread.c - - timer.c 1 @@ -473,40 +703,6 @@ - - Applications - - - main.c - 1 - applications\main.c - - - - - Drivers - - - board.c - 1 - drivers\board.c - - - - - drv_gpio.c - 1 - drivers\drv_gpio.c - - - - - drv_uart.c - 1 - drivers\drv_uart.c - - - Libraries @@ -515,204 +711,146 @@ 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_acmp.c - - ald_adc.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_adc.c - - ald_bkpc.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_bkpc.c - - ald_calc.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_calc.c - - ald_cmu.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_cmu.c - - ald_crc.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_crc.c - - ald_crypt.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_crypt.c - - ald_dma.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_dma.c - - ald_flash.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_flash.c - - ald_flash_ext.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c - - ald_gpio.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_gpio.c - - ald_i2c.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_i2c.c - - ald_iap.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_iap.c - - ald_lcd.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lcd.c - - ald_lptim.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lptim.c - - ald_lpuart.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lpuart.c - - ald_pis.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_pis.c - - ald_pmu.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_pmu.c - - ald_rmu.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_rmu.c - - ald_rtc.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_rtc.c - - ald_smartcard.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_smartcard.c - - ald_spi.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_spi.c - - ald_timer.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_timer.c - - ald_trng.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_trng.c - - ald_tsense.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_tsense.c - - ald_uart.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_uart.c - - ald_usart.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_usart.c - - ald_wdt.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_wdt.c - - utils.c 1 libraries\ES32F033x_ALD_StdPeriph_Driver\Source\utils.c - - startup_es32f033x.s 2 @@ -720,140 +858,14 @@ - - cpu - - - backtrace.c - 1 - ..\..\..\libcpu\arm\common\backtrace.c - - - - - div0.c - 1 - ..\..\..\libcpu\arm\common\div0.c - - - - - showmem.c - 1 - ..\..\..\libcpu\arm\common\showmem.c - - - - - cpuport.c - 1 - ..\..\..\libcpu\arm\cortex-m0\cpuport.c - - - - - context_rvds.S - 2 - ..\..\..\libcpu\arm\cortex-m0\context_rvds.S - - - - - DeviceDrivers - - - pin.c - 1 - ..\..\..\components\drivers\misc\pin.c - - - - - serial.c - 1 - ..\..\..\components\drivers\serial\serial.c - - - - - completion.c - 1 - ..\..\..\components\drivers\src\completion.c - - - - - dataqueue.c - 1 - ..\..\..\components\drivers\src\dataqueue.c - - - - - pipe.c - 1 - ..\..\..\components\drivers\src\pipe.c - - - - - ringblk_buf.c - 1 - ..\..\..\components\drivers\src\ringblk_buf.c - - - - - ringbuffer.c - 1 - ..\..\..\components\drivers\src\ringbuffer.c - - - - - waitqueue.c - 1 - ..\..\..\components\drivers\src\waitqueue.c - - - - - workqueue.c - 1 - ..\..\..\components\drivers\src\workqueue.c - - - - - finsh - - - shell.c - 1 - ..\..\..\components\finsh\shell.c - - - - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - - - - - msh.c - 1 - ..\..\..\components\finsh\msh.c - - - + - - - + + + + diff --git a/bsp/essemi/es32f0334/rtconfig.h b/bsp/essemi/es32f0334/rtconfig.h index 0e536bba08d9c52e47354cbbbc277e61a3869512..7354c8d7d8e45307f2a17368ef7e81463b1114ea 100644 --- a/bsp/essemi/es32f0334/rtconfig.h +++ b/bsp/essemi/es32f0334/rtconfig.h @@ -39,7 +39,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40002 +#define RT_VER_NUM 0x40003 /* RT-Thread Components */ @@ -76,7 +76,15 @@ #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_HWTIMER +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS #define RT_USING_PIN +#define RT_USING_ADC +#define RT_USING_PWM +#define RT_USING_PM +#define RT_USING_RTC +#define RT_USING_SPI /* Using USB */ @@ -180,6 +188,8 @@ /* Offboard Peripheral Drivers */ +/* Peripheral Drivers test example */ + #define SOC_ES32F0334LT #endif diff --git a/bsp/essemi/es32f0334/template.uvoptx b/bsp/essemi/es32f0334/template.uvoptx index d064f068ab9f123e43b6e7a082f87b395342e1d2..1b420d49992aab2951332189687ed76c2ebd9220 100644 --- a/bsp/essemi/es32f0334/template.uvoptx +++ b/bsp/essemi/es32f0334/template.uvoptx @@ -101,7 +101,9 @@ 0 0 1 - 2 + 0 + 0 + 3 @@ -170,6 +172,10 @@ + + + + diff --git a/bsp/essemi/es32f0334/template.uvprojx b/bsp/essemi/es32f0334/template.uvprojx index 151702acd3553aeb46e69bc13c8de2ab575ea8be..37ac22a68debe18d201c181a3fd55e7e3e2913f4 100644 --- a/bsp/essemi/es32f0334/template.uvprojx +++ b/bsp/essemi/es32f0334/template.uvprojx @@ -10,11 +10,12 @@ rt-thread 0x4 ARM-ADS + 0 ES32F0334LT Eastsoft - Eastsoft.ES32_DFP.1.0.1 + Eastsoft.ES32_DFP.7.2350 http://www.essemi.com IRAM(0x20000000,0x00008000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE @@ -182,6 +183,7 @@ 0 0 0 + 0 0 0 8 @@ -322,6 +324,7 @@ 0 0 1 + 0 0 1 1 diff --git a/bsp/essemi/es32f0654/.config b/bsp/essemi/es32f0654/.config index 56a52e8087befe972a89219b5be2a16eb17e682b..3a014cefdd917f285c1934902e601c16bb9f859b 100644 --- a/bsp/essemi/es32f0654/.config +++ b/bsp/essemi/es32f0654/.config @@ -9,7 +9,7 @@ CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=4 +CONFIG_RT_ALIGN_SIZE=8 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set @@ -64,7 +64,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" -CONFIG_RT_VER_NUM=0x40002 +CONFIG_RT_VER_NUM=0x40003 # CONFIG_RT_USING_CPU_FFS is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set @@ -114,19 +114,31 @@ CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set +CONFIG_RT_USING_CAN=y +# CONFIG_RT_CAN_USING_HDR is not set +CONFIG_RT_USING_HWTIMER=y # CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_PWM is not set +CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_PWM=y # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_RTC is not set +CONFIG_RT_USING_PM=y +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -192,10 +204,15 @@ CONFIG_RT_USING_PIN=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -222,6 +239,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -234,8 +252,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set @@ -249,6 +269,16 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_DLT645 is not set # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set # # security packages @@ -256,6 +286,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -272,6 +304,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -286,6 +319,13 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -296,6 +336,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -304,6 +345,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -311,6 +361,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -319,6 +370,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set @@ -332,9 +387,27 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set # CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_LCD_DRIVERS is not set # CONFIG_PKG_USING_MAX17048 is not set # CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -369,8 +442,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set CONFIG_SOC_ES32F0654LT=y # @@ -402,6 +481,11 @@ CONFIG_BSP_USING_UART2=y # CONFIG_BSP_USING_I2C0 is not set # CONFIG_BSP_USING_I2C1 is not set +# +# CAN Drivers +# +# CONFIG_BSP_USING_CAN is not set + # # PWM Drivers # @@ -414,6 +498,7 @@ CONFIG_BSP_USING_UART2=y # HWtimer Drivers # # CONFIG_BSP_USING_HWTIMER0 is not set +# CONFIG_BSP_USING_HWTIMER1 is not set # CONFIG_BSP_USING_HWTIMER2 is not set # CONFIG_BSP_USING_HWTIMER3 is not set @@ -440,3 +525,18 @@ CONFIG_BSP_USING_UART2=y # # Offboard Peripheral Drivers # + +# +# Peripheral Drivers test example +# +# CONFIG_BSP_USING_EXAMPLE_ADC_VOL is not set +# CONFIG_BSP_USING_EXAMPLE_HWTIMER is not set +# CONFIG_BSP_USING_EXAMPLE_I2C is not set +# CONFIG_BSP_USING_EXAMPLE_LED_BLINK is not set +# CONFIG_BSP_USING_EXAMPLE_PIN_BEEP is not set +# CONFIG_BSP_USING_EXAMPLE_PWM_LED is not set +# CONFIG_BSP_USING_EXAMPLE_RTC is not set +# CONFIG_BSP_USING_EXAMPLE_SPI is not set +# CONFIG_BSP_USING_EXAMPLE_UART is not set +# CONFIG_BSP_USING_EXAMPLE_CAN is not set +# CONFIG_BSP_USING_EXAMPLE_PM is not set diff --git a/bsp/essemi/es32f0654/README.md b/bsp/essemi/es32f0654/README.md index 120cf0f4798abcf7a494d5deab8d37490e80f83c..e7c006e46b17b244c25572e7a6f854f6b721e4ec 100644 --- a/bsp/essemi/es32f0654/README.md +++ b/bsp/essemi/es32f0654/README.md @@ -90,6 +90,24 @@ msh > 2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + a）如果需要使用内核用例，先配置rt-thread内核，如图： + + ![kernel_config](figures/k_conf.jpg) + + 然后配置内核用例，如图： + + ![kernel_sample](figures/k_ex.jpg) + + b）如果需要使用驱动用例：先使能驱动，如图： + + ![driver_config](figures/d_conf.jpg) + + 然后配置驱动用例，如图： + + ![driver_sample](figures/d_ex.jpg) + + + 3. 输入`pkgs --update`命令更新软件包。 4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 @@ -98,7 +116,7 @@ msh > ## 4. 联系人信息 -- [wangyongquan](https://github.com/wangyq2018) +- [liuhongyan](https://gitee.com/liuhongyan98) ## 5. 参考 diff --git a/bsp/essemi/es32f0654/drivers/Kconfig b/bsp/essemi/es32f0654/drivers/Kconfig index 888308497ae24c4c7a45bad8e58e01f353ba27de..3c3cf9e9e590b45bf1f8443b7ad6167edb129a2f 100644 --- a/bsp/essemi/es32f0654/drivers/Kconfig +++ b/bsp/essemi/es32f0654/drivers/Kconfig @@ -148,4 +148,53 @@ menu "Hardware Drivers Config" endmenu + + menu "Peripheral Drivers test example" + + config BSP_USING_EXAMPLE_ADC_VOL + bool "BSP_USING_EXAMPLE_ADC_VOL" + default n + + config BSP_USING_EXAMPLE_HWTIMER + bool "BSP_USING_EXAMPLE_HWTIMER" + default n + + config BSP_USING_EXAMPLE_I2C + bool "BSP_USING_EXAMPLE_I2C" + default n + + config BSP_USING_EXAMPLE_LED_BLINK + bool "BSP_USING_EXAMPLE_LED_BLINK" + default y + + config BSP_USING_EXAMPLE_PIN_BEEP + bool "BSP_USING_EXAMPLE_PIN_BEEP" + default y + + config BSP_USING_EXAMPLE_PWM_LED + bool "BSP_USING_EXAMPLE_PWM_LED" + default n + + config BSP_USING_EXAMPLE_RTC + bool "BSP_USING_EXAMPLE_RTC" + default n + + config BSP_USING_EXAMPLE_SPI + bool "BSP_USING_EXAMPLE_SPI" + default n + + config BSP_USING_EXAMPLE_UART + bool "BSP_USING_EXAMPLE_UART" + default y + + config BSP_USING_EXAMPLE_CAN + bool "BSP_USING_EXAMPLE_CAN" + default n + + config BSP_USING_EXAMPLE_PM + bool "BSP_USING_EXAMPLE_PM" + default n + + endmenu + endmenu diff --git a/bsp/essemi/es32f0654/drivers/SConscript b/bsp/essemi/es32f0654/drivers/SConscript index ad5cf3c7836b27f4741ae3c66f922ad2be01f446..280c6f5c90bb30c4148729a37dd04c725d123fd8 100644 --- a/bsp/essemi/es32f0654/drivers/SConscript +++ b/bsp/essemi/es32f0654/drivers/SConscript @@ -2,6 +2,8 @@ from building import * cwd = GetCurrentDir() +objs = [] + # add the general drivers. src = Split(''' board.c @@ -53,5 +55,47 @@ if GetDepend(['BSP_USING_ADC']): CPPPATH = [cwd] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) +objs = objs + group + +src = [] +cwd = GetCurrentDir() +include_path = [cwd] + +if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'): + src += ['bsp_driver_example/adc_vol_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_HWTIMER'): + src += ['bsp_driver_example/hwtimer_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_I2C'): + src += ['bsp_driver_example/i2c_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'): + src += ['bsp_driver_example/led_blink_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_PIN_BEEP'): + src += ['bsp_driver_example/pin_beep_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_PWM_LED'): + src += ['bsp_driver_example/pwm_led_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_RTC'): + src += ['bsp_driver_example/rtc_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_UART'): + src += ['bsp_driver_example/uart_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_SPI'): + src += ['bsp_driver_example/spi_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_CAN'): + src += ['bsp_driver_example/can_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_PM'): + src += ['bsp_driver_example/pm_sample.c'] + +group = DefineGroup('bsp-drivers-test-samples', src, depend = [''], CPPPATH = include_path) + +objs = objs + group +Return('objs') -Return('group') diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/.gitignore b/bsp/essemi/es32f0654/drivers/bsp_driver_example/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..c6127b38c1aa25968a88db3940604d41529e4cf5 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/.gitignore @@ -0,0 +1,52 @@ +# Prerequisites +*.d + +# Object files +*.o +*.ko +*.obj +*.elf + +# Linker output +*.ilk +*.map +*.exp + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex + +# Debug files +*.dSYM/ +*.su +*.idb +*.pdb + +# Kernel Module Compile Results +*.mod* +*.cmd +.tmp_versions/ +modules.order +Module.symvers +Mkfile.old +dkms.conf diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/README.md b/bsp/essemi/es32f0654/drivers/bsp_driver_example/README.md new file mode 100644 index 0000000000000000000000000000000000000000..80f12e1949235d15811415581686d64f623599f0 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/README.md @@ -0,0 +1,47 @@ +# 外设驱动测试用例 + +## 1、介绍 + +这个软件包包含一些外设设备操作的例程。 + +### 1.1 例程说明 + +| 文件 | 说明 | +| ---------------- | ------------------------------- | +| adc_vol_sample.c | 使用 ADC 设备转换电压数据 | +| can_sample.c | 通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。 | +| hwtimer_sample.c | 使用 硬件定时器定时 | +| i2c_sample.c | 使用 i2c 设备进行读写 | +| pm.c | 反复进入不同程度的睡眠。 | +| led_blink_sample.c | 使用 pin 设备控制 LED 闪烁 | +| pin_beep_sample.c | 使用 pin 设备控制蜂鸣器 | +| pwm_led_sample.c | 使用 pwm 设备控制 LED 的亮度 | +| rtc_sample.c | 使用 rtc 设备设置年月日时分秒信息 | +| spi_sample.c | 使用 spi 设备进行读写 | +| uart_sample.c | 使用 serial 设备中断接收及轮询发送模式收发数据 | + +### 1.2 依赖 + +依赖设备管理模块提供的设备驱动。 + +## 2、如何打开 外设驱动测试用例 + +使用 外设驱动测试用例 需要在 RT-Thread 的menuconfig中选择它，具体路径如下： + +``` +Hardware Driver Config ---> + Peripheral Driver test example---> +``` + +## 3、使用 外设驱动测试用例 + +在打开 Peripheral Driver test example 后，当进行 BSP 编译时，选择的软件包相关源代码会被加入到 BSP 工程中进行编译。 + +## 4、注意事项 + +暂无。 + +## 5、联系方式 & 感谢 + +* 维护：[misonyo](https://github.com/misonyo) +* 主页：https://github.com/RT-Thread-packages/peripheral-sample diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/adc_vol_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/adc_vol_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..19eed3f35d66592b76bf99d1d9acb247113847ca --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/adc_vol_sample.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-29 misonyo first implementation. + */ +/* + * 程序清单： ADC 设备使用例程 + * 例程导出了 adc_sample 命令到控制终端 + * 命令调用格式：adc_sample + * 程序功能：通过 ADC 设备采样电压值并转换为数值。 + * 示例代码参考电压为3.3V,转换位数为12位。 +*/ + +#include +#include + +#define ADC_DEV_NAME "adc0" /* ADC 设备名称 */ +#define ADC_DEV_CHANNEL 5 /* PA1 ADC 通道 */ +#define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/ +#define CONVERT_BITS (1 << 12) /* 转换位数为12位 */ + +static int adc_vol_sample(int argc, char *argv[]) +{ + rt_adc_device_t adc_dev; + rt_uint32_t value, vol; + rt_err_t ret = RT_EOK; + + /* 查找设备 */ + adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME); + if (adc_dev == RT_NULL) + { + rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME); + return RT_ERROR; + } + + /* 使能设备 */ + ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL); + + /* 读取采样值 */ + value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL); + rt_kprintf("the value is :%d \n", value); + + /* 转换为对应电压值 */ + vol = value * REFER_VOLTAGE / CONVERT_BITS; + rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); + + /* 关闭通道 */ + ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL); + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/can_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/can_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..4c16d1d555bf1eb02bfa620baf43d0b4234f2be2 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/can_sample.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-06-25 misonyo first implementation. + */ +/* + * 程序清单：这是一个 CAN 设备使用例程 + * 例程导出了 can_sample 命令到控制终端 + * 命令调用格式：can_sample can2 + * 命令解释：命令第二个参数是要使用的 CAN 设备名称，为空则使用默认的 CAN 设备 + * 程序功能：通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。 +*/ + +#include +#include "rtdevice.h" + +#define CAN_DEV_NAME "can" /* CAN 设备名称 */ + +static struct rt_semaphore rx_sem; /* 用于接收消息的信号量 */ +static rt_device_t can_dev; /* CAN 设备句柄 */ + +/* 接收数据回调函数 */ +static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size) +{ + /* CAN 接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */ + rt_sem_release(&rx_sem); + + return RT_EOK; +} + +static void can_rx_thread(void *parameter) +{ + int i; + struct rt_can_msg rxmsg = {0}; + + /* 设置接收回调函数 */ + rt_device_set_rx_indicate(can_dev, can_rx_call); + +#ifdef RT_CAN_USING_HDR + + rt_err_t res; + + struct rt_can_filter_item items[5] = + { + RT_CAN_FILTER_ITEM_INIT(0x100, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x100~0x1ff，hdr为-1，设置默认过滤表 */ + RT_CAN_FILTER_ITEM_INIT(0x300, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x300~0x3ff，hdr为-1 */ + RT_CAN_FILTER_ITEM_INIT(0x211, 0, 0, 0, 0x7ff, RT_NULL, RT_NULL), /* std,match ID:0x211，hdr为-1 */ + RT_CAN_FILTER_STD_INIT(0x486, RT_NULL, RT_NULL), /* std,match ID:0x486，hdr为-1 */ + {0x555, 0, 0, 0, 0x7ff, 7,} /* std,match ID:0x555，hdr为7，指定设置7号过滤表 */ + }; + struct rt_can_filter_config cfg = {5, 1, items}; /* 一共有5个过滤表 */ + /* 设置硬件过滤表 */ + res = rt_device_control(can_dev, RT_CAN_CMD_SET_FILTER, &cfg); + RT_ASSERT(res == RT_EOK); +#endif + + while (1) + { + /* hdr值为-1，表示直接从uselist链表读取数据 */ + rxmsg.hdr = -1; + /* 阻塞等待接收信号量 */ + rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + /* 从CAN读取一帧数据 */ + rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg)); + /* 打印数据ID及内容 */ + rt_kprintf("ID:%x ", rxmsg.id); + for (i = 0; i < 8; i++) + { + rt_kprintf("%2x ", rxmsg.data[i]); + } + + rt_kprintf("\n"); + } +} + +int can_sample(int argc, char *argv[]) +{ + struct rt_can_msg msg = {0}; + rt_err_t res; + rt_size_t size; + rt_thread_t thread; + char can_name[RT_NAME_MAX]; + + if (argc == 2) + { + rt_strncpy(can_name, argv[1], RT_NAME_MAX); + } + else + { + rt_strncpy(can_name, CAN_DEV_NAME, RT_NAME_MAX); + } + + can_dev = rt_device_find(can_name); + if (!can_dev) + { + rt_kprintf("find %s failed!\n", can_name); + return RT_ERROR; + } + + /* 初始化CAN接收信号量 */ + rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); + + /* 以中断接收及发送方式打开CAN设备 */ + res = rt_device_open(can_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX); + RT_ASSERT(res == RT_EOK); + + thread = rt_thread_create("can_rx", can_rx_thread, RT_NULL, 1024, 25, 10); + if (thread != RT_NULL) + { + rt_thread_startup(thread); + } + else + { + rt_kprintf("create can_rx thread failed!\n"); + } + + msg.id = 0x78; /* ID为0x78 */ + msg.ide = RT_CAN_STDID; /* 标准格式 */ + msg.rtr = RT_CAN_DTR; /* 数据帧 */ + msg.len = 8; /* 数据长度为8 */ + /* 待发送的8字节数据 */ + msg.data[0] = 0x00; + msg.data[1] = 0x11; + msg.data[2] = 0x22; + msg.data[3] = 0x33; + msg.data[4] = 0x44; + msg.data[5] = 0x55; + msg.data[6] = 0x66; + msg.data[7] = 0x77; + /* 发送一帧CAN数据 */ + size = rt_device_write(can_dev, 0, &msg, sizeof(msg)); + if (size == 0) + { + rt_kprintf("can dev write data failed!\n"); + } + + return res; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(can_sample, can device sample); diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/hwtimer_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/hwtimer_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..e2e39664f3a5f7cd1c09f4a1e6dcf6d30e050e57 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/hwtimer_sample.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-30 misonyo first implementation. + */ +/* + * 程序清单：这是一个 hwtimer 设备使用例程 + * 例程导出了 hwtimer_sample 命令到控制终端 + * 命令调用格式：hwtimer_sample + * 程序功能：硬件定时器超时回调函数周期性的打印当前tick值，2次tick值之差换算为时间等同于定时时间值。 +*/ + +#include +#include + +#define HWTIMER_DEV_NAME "timer0" /* 定时器名称 */ + +/* 定时器超时回调函数 */ +static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) +{ + rt_kprintf("tick is :%d !\n", rt_tick_get()); + + return 0; +} + +static int hwtimer_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + rt_hwtimerval_t timeout_s; /* 定时器超时值 */ + rt_device_t hw_dev = RT_NULL; /* 定时器设备句柄 */ + rt_hwtimer_mode_t mode; /* 定时器模式 */ + + /* 查找定时器设备 */ + hw_dev = rt_device_find(HWTIMER_DEV_NAME); + if (hw_dev == RT_NULL) + { + rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + return RT_ERROR; + } + + /* 以读写方式打开设备 */ + ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); + if (ret != RT_EOK) + { + rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + return ret; + } + + /* 设置超时回调函数 */ + rt_device_set_rx_indicate(hw_dev, timeout_cb); + + /* 设置模式为周期性定时器 */ + mode = HWTIMER_MODE_PERIOD; + ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + if (ret != RT_EOK) + { + rt_kprintf("set mode failed! ret is :%d\n", ret); + return ret; + } + + /* 设置定时器超时值为5s并启动定时器 */ + timeout_s.sec = 5; /* 秒 */ + timeout_s.usec = 0; /* 微秒 */ + + if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s)) + { + rt_kprintf("set timeout value failed\n"); + return RT_ERROR; + } + + /* 延时3500ms */ + rt_thread_mdelay(3500); + + /* 读取定时器当前值 */ + rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); + rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..2d386433c63a7a1a1cb61ab1a7891adf632c7b9e --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy first implementation. + */ +/* + * 程序清单：这是一个 I2C 设备使用例程 + * 例程导出了 i2c_io_sample 命令到控制终端 + * 命令调用格式：i2c_io_sample + * 命令解释：使用默认的I2C总线设备 + * 程序功能：通过 I2C 设备接收数据并打印，然后将接收的字符加1输出。 +*/ + +#include +#include + +#define I2C_BUS_NAME "i2c1" /* I2C总线设备名称 */ +#define SLAVE_ADDR 0x2D /* 从机地址 */ +#define STR_LEN 16 /* 接收发送的数据长度 */ + +static void i2c_io_sample(int argc, char *argv[]) +{ + + struct rt_i2c_bus_device *i2c_bus = RT_NULL; /* I2C总线设备句柄 */ + struct rt_i2c_msg temp_msg; /* I2C消息 */ + rt_uint8_t buffer[STR_LEN] = { 0U }; + rt_uint32_t i,num_msg; + rt_size_t s_stat; + + i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(I2C_BUS_NAME); /* 通过名字获取I2C总线设备的句柄 */ + + if( i2c_bus == RT_NULL) + { + rt_kprintf("can't find i2c device :%s !\n",I2C_BUS_NAME); + + return; + } + + /*初始化消息*/ + temp_msg.addr = SLAVE_ADDR; /* 从机地址 */ + temp_msg.len = STR_LEN; /* 传输的数据长度 */ + temp_msg.buf = buffer; /* 读写缓存器 */ + + num_msg = 1; /* 传输一条消息 */ + + temp_msg.flags = RT_I2C_RD; /* I2C读 */ + s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输消息 */ + + rt_thread_mdelay(400); + + if( s_stat == num_msg ) + { + rt_kprintf("receive successful. \n receive messege : %s \n:",buffer); + + for( i = 0 ; i < STR_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + } + else + { + rt_kprintf("device s% recieve fail \n buffer : s%\n",I2C_BUS_NAME,buffer); + return; + } + + for( i = 0 ; i < STR_LEN ; i++) + buffer[i]++; + + temp_msg.flags = RT_I2C_WR; /* I2C写 */ + s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输一条 */ + + rt_thread_mdelay(400); + + if( s_stat == num_msg ) + { + rt_kprintf(" send successful \n messege : %s \n:",buffer); + + for( i = 0 ; i < STR_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + } + else + { + rt_kprintf("device s% send fail \n",I2C_BUS_NAME); + return; + } + + return; + +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(i2c_io_sample, i2c io sample); diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/led_blink_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/led_blink_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..42c956a0602719b829d754037e11d491632c4bc4 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/led_blink_sample.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-09-25 misonyo first edition. + */ +/* + * 程序清单：这是一个通过PIN脚控制LED亮灭的使用例程 + * 例程导出了 led_sample 命令到控制终端 + * 命令调用格式：led_sample 41 + * 命令解释：命令第二个参数是要使用的PIN脚编号，为空则使用例程默认的引脚编号。 + * 程序功能：程序创建一个led线程，线程每隔1000ms改变PIN脚状态，达到控制led灯 + * 亮灭的效果。 +*/ + +#include +#include +#include + +/* PIN脚编号，查看驱动文件drv_gpio.c确定 */ +#define LED_PIN_NUM 40 /*PB9*/ +static int pin_num; + +static void led_entry(void *parameter) +{ + int count = 0; + /* 设置PIN脚模式为输出 */ + rt_pin_mode(pin_num, PIN_MODE_OUTPUT); + + while (1) + { + count++; + rt_kprintf("thread run count : %d\r\n", count); + /* 拉低PIN脚 */ + rt_pin_write(pin_num, PIN_LOW); + rt_kprintf("led on!\r\n"); + /* 延时1000ms */ + rt_thread_mdelay(1000); + + /* 拉高PIN脚 */ + rt_pin_write(pin_num, PIN_HIGH); + rt_kprintf("led off!\r\n"); + rt_thread_mdelay(1000); + } +} + +static int led_sample(int argc, char *argv[]) +{ + rt_thread_t tid; + rt_err_t ret = RT_EOK; + + /* 判断命令行参数是否给定了PIN脚编号 */ + if (argc == 2) + { + pin_num = atoi(argv[1]); + } + else + { + pin_num = LED_PIN_NUM; + } + + tid = rt_thread_create("led", + led_entry, + RT_NULL, + 512, + RT_THREAD_PRIORITY_MAX / 3, + 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + ret = RT_ERROR; + } + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(led_sample, led sample); diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pin_beep_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pin_beep_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..29dfbe1b2ff1fd3f7bb847afb4408fabeec62068 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pin_beep_sample.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-15 misonyo first implementation. + */ +/* + * 程序清单：这是一个 PIN 设备使用例程 + * 例程导出了 pin_beep_sample 命令到控制终端 + * 命令调用格式：pin_beep_sample + * 程序功能：通过按键控制蜂鸣器对应引脚的电平状态控制蜂鸣器 +*/ + +#include +#include + +/* 引脚编号，通过查看驱动文件drv_gpio.c确定 */ +#ifndef BEEP_PIN_NUM + #define BEEP_PIN_NUM 40 /* PB9 */ +#endif +#ifndef KEY0_PIN_NUM + #define KEY0_PIN_NUM 18 /* PF0 */ +#endif +#ifndef KEY1_PIN_NUM + #define KEY1_PIN_NUM 19 /* PF1 */ +#endif + +void beep_on(void *args) +{ + rt_kprintf("turn on beep!\n"); + + rt_pin_write(BEEP_PIN_NUM, PIN_HIGH); +} + +void beep_off(void *args) +{ + rt_kprintf("turn off beep!\n"); + + rt_pin_write(BEEP_PIN_NUM, PIN_LOW); +} + +static void pin_beep_sample(void) +{ + /* 蜂鸣器引脚为输出模式 */ + rt_pin_mode(BEEP_PIN_NUM, PIN_MODE_OUTPUT); + /* 默认低电平 */ + rt_pin_write(BEEP_PIN_NUM, PIN_LOW); + + /* 按键0引脚为输入模式 */ + rt_pin_mode(KEY0_PIN_NUM, PIN_MODE_INPUT_PULLUP); + /* 绑定中断，下降沿模式，回调函数名为beep_on */ + rt_pin_attach_irq(KEY0_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_on, RT_NULL); + /* 使能中断 */ + rt_pin_irq_enable(KEY0_PIN_NUM, PIN_IRQ_ENABLE); + + /* 按键1引脚为输入模式 */ + rt_pin_mode(KEY1_PIN_NUM, PIN_MODE_INPUT_PULLUP); + /* 绑定中断，下降沿模式，回调函数名为beep_off */ + rt_pin_attach_irq(KEY1_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_off, RT_NULL); + /* 使能中断 */ + rt_pin_irq_enable(KEY1_PIN_NUM, PIN_IRQ_ENABLE); +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(pin_beep_sample, pin beep sample); diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..f7287e36ac581d955cef5834f4e89cca4f0fd9f9 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c @@ -0,0 +1,183 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy first implementation. + */ +/* + * 程序清单：这是一个 pm睡眠唤醒的使用例程 + * 例程导出了 pm_sample 命令到控制终端 + * 命令调用格式：pm_sample + * 命令解释：进入不同的睡眠模式，然后用按键唤醒 + * 程序功能：通过串口输出字符串，告知进入睡眠和唤醒睡眠的情况。 +*/ + +#include +#include + +#define PM_NAME "pm" /* 设备名称 */ +#define WAKE_UP_PIN 18 /* 唤醒源 */ +#define SLEEP_TIMES 12 /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */ + + +struct pm_callback_t +{ + volatile int in_fun_times; /*进入函数的次数*/ + volatile char flag; /*标志*/ + volatile int mode; /*需要打印的模式*/ +}; + +volatile struct pm_callback_t g_pm_data; + +/*进入睡眠前，睡眠唤醒后，都会进入。*/ +/*函数打印睡眠相关的信息*/ +void sleep_in_out_callback(rt_uint8_t event, rt_uint8_t mode, void *data) +{ + /*没有标志，不处理*/ + if(!(g_pm_data.flag)) + { + return; + } + + /*标志不正常，清空标志*/ + if((g_pm_data.flag) > 2) + { + (g_pm_data.flag) = 0; + return; + } + + /*模式不匹配*/ + if(g_pm_data.mode != mode ) + { + return; + } + + /*进入的事件*/ + switch(event) + { + /*进入睡眠前*/ + case RT_PM_ENTER_SLEEP: g_pm_data.flag = 1; + rt_kprintf("\n\r##%d : ENTER ",g_pm_data.in_fun_times); + g_pm_data.in_fun_times++; /*进入睡眠次数+1*/ + break; + /*睡眠唤醒后*/ + case RT_PM_EXIT_SLEEP: g_pm_data.flag = 0; /*睡眠唤醒后*/ + rt_kprintf("\n\rEXIT\n\r"); + rt_pm_release(mode); /*释放休眠模式*/ + return; + + default: break; + + }; + + /*当前的睡眠模式*/ + switch(mode) + { + case PM_SLEEP_MODE_NONE: rt_kprintf("PM_SLEEP_MODE_NONE\n\r"); + break; + case PM_SLEEP_MODE_IDLE: rt_kprintf("PM_SLEEP_MODE_IDLE\n\r"); + break; + case PM_SLEEP_MODE_LIGHT: rt_kprintf("PM_SLEEP_MODE_LIGHT\n\r"); + break; + case PM_SLEEP_MODE_DEEP: rt_kprintf("PM_SLEEP_MODE_DEEP\n\r"); + break; + case PM_SLEEP_MODE_STANDBY: rt_kprintf("PM_SLEEP_MODE_STANDBY\n\r"); + break; + case PM_SLEEP_MODE_SHUTDOWN: rt_kprintf("PM_SLEEP_MODE_SHUTDOWN\n\r"); + break; + case PM_SLEEP_MODE_MAX: rt_kprintf("PM_SLEEP_MODE_MAX\n\r"); + break; + default: break; + } + +} + +/* pm测试函数 */ +static void pm_test(void *parameter) +{ + int in_mode[7],i = 0; + + g_pm_data.in_fun_times = 0; + g_pm_data.flag = 0; + + in_mode[0] = PM_SLEEP_MODE_NONE; + in_mode[1] = PM_SLEEP_MODE_IDLE; + in_mode[2] = PM_SLEEP_MODE_LIGHT; + in_mode[3] = PM_SLEEP_MODE_DEEP; + in_mode[4] = PM_SLEEP_MODE_STANDBY; + in_mode[5] = PM_SLEEP_MODE_SHUTDOWN; + in_mode[6] = PM_SLEEP_MODE_MAX; + + /*设置回调函数和私有数据*/ + rt_pm_notify_set(sleep_in_out_callback,RT_NULL); + + while(i < SLEEP_TIMES) + { + + g_pm_data.mode = in_mode[i%6]; + + /*无休眠模式，不赋予标志*/ + if(g_pm_data.mode != PM_SLEEP_MODE_NONE) + { + g_pm_data.flag = 2; + + } + + /*请求选择的休眠模式*/ + rt_pm_request(in_mode[i%6]); + + rt_thread_mdelay(500); + + /*无休眠模式，不需要额外的等待*/ + while(( g_pm_data.flag != 0 )&&(g_pm_data.mode != PM_SLEEP_MODE_NONE)) + { + rt_thread_mdelay(500); + } + + /*释放选择的休眠模式*/ + rt_pm_release(in_mode[i%6]); + + i++; + + } + /*清除回调函数和私有数据*/ + rt_pm_notify_set(RT_NULL,RT_NULL); + rt_kprintf("thread pm_test close\n\r"); +} + +/*按键唤醒的回调函数*/ +void wake_by_pin(void *args) +{ + +} + +static int pm_sample(int argc, char *argv[]) +{ + rt_thread_t thread; + + /* 按键引脚为输入模式 */ + rt_pin_mode(WAKE_UP_PIN, PIN_MODE_INPUT_PULLUP); + + /* 绑定中断，下降沿模式，回调函数名为wake_by_pin */ + rt_pin_attach_irq(WAKE_UP_PIN, PIN_IRQ_MODE_RISING, wake_by_pin, RT_NULL); + /* 使能中断 */ + rt_pin_irq_enable(WAKE_UP_PIN, PIN_IRQ_ENABLE); + + thread = rt_thread_create("pm_test", pm_test, RT_NULL, 1024, 25, 10); + + if (thread != RT_NULL) + { + rt_thread_startup(thread); + } + else + { + rt_kprintf("create pm_test thread failed!\n\r"); + } + + return RT_EOK; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(pm_sample, pm sample); diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..ce1573aa5599a5120fada507b59466687f11c457 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-25 misonyo first implementation. + */ +/* + * 程序清单：这是一个 PWM 设备使用例程 + * 例程导出了 pwm_led_sample 命令到控制终端 + * 命令调用格式：pwm_led_sample + * 程序功能：通过 PWM 设备控制 LED 灯的亮度，可以看到LED不停的由暗变到亮，然后又从亮变到暗。 +*/ + +#include +#include + +#define LED_PIN_NUM 16 /* LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ +#define PWM_DEV_NAME "pwm1" /* PWM设备名称 */ +#define PWM_DEV_CHANNEL 4 /* PB9 PWM通道 */ + +struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */ + +static int pwm_led_sample(int argc, char *argv[]) +{ + rt_uint32_t period, pulse, dir; + + period = 500000; /* 周期为0.5ms，单位为纳秒ns */ + dir = 1; /* PWM脉冲宽度值的增减方向 */ + pulse = 0; /* PWM脉冲宽度值，单位为纳秒ns */ + + /* 查找设备 */ + pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME); + if (pwm_dev == RT_NULL) + { + rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME); + return RT_ERROR; + } + + /* 设置PWM周期和脉冲宽度默认值 */ + rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); + /* 使能设备 */ + rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL); + + while (1) + { + rt_thread_mdelay(50); + if (dir) + { + pulse += 5000; /* 从0值开始每次增加5000ns */ + } + else + { + pulse -= 5000; /* 从最大值开始每次减少5000ns */ + } + if (pulse >= period) + { + dir = 0; + } + if (0 == pulse) + { + dir = 1; + } + + /* 设置PWM周期和脉冲宽度 */ + rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); + } +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(pwm_led_sample, pwm sample); diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/rtc_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/rtc_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..711a3a0ebb497521114bbd24dd99933dbbd786a2 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/rtc_sample.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-30 misonyo first implementation. + */ +/* + * 程序清单：这是一个 RTC 设备使用例程 + * 例程导出了 rtc_sample 命令到控制终端 + * 命令调用格式：rtc_sample + * 程序功能：设置RTC设备的日期和时间，延时一段时间后获取当前时间并打印显示。 +*/ + +#include +#include + +static int rtc_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + time_t now; + + /* 设置日期 */ + ret = set_date(2018, 12, 3); + if (ret != RT_EOK) + { + rt_kprintf("set RTC date failed\n"); + return ret; + } + + /* 设置时间 */ + ret = set_time(11, 15, 50); + if (ret != RT_EOK) + { + rt_kprintf("set RTC time failed\n"); + return ret; + } + + /* 延时3秒 */ + rt_thread_mdelay(3000); + + /* 获取时间 */ + now = time(RT_NULL); + rt_kprintf("%s\n", ctime(&now)); + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(rtc_sample, rtc sample); diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/spi_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/spi_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..994888cdb0d8a52bebf6bcd89f29df291db6dbe1 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/spi_sample.c @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy first implementation. + */ +/* + * 程序清单：这是一个 SPI 设备使用例程 + * 例程导出了 spi_io_sample 命令到控制终端 + * 命令调用格式：spi_io_sample + * 程序功能：通过SPI设备先读取数据，然后每个字符加1后输出。 +*/ + +#include +#include + +#define SPI_DEVICE_NAME "spi00" +#define BUF_LEN 16 + +static void spi_io_sample(int argc, char *argv[]) +{ + struct rt_spi_device * spi_dev; /* spi设备的句柄 */ + struct rt_spi_configuration spi_config; + rt_uint8_t i,buffer[BUF_LEN] = { 0U }; + rt_err_t s_stat; + rt_err_t result; + + /* 查找 spi设备 获取spi设备句柄 */ + spi_dev = (struct rt_spi_device *)rt_device_find(SPI_DEVICE_NAME); + + if (spi_dev == RT_NULL) + { + rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_DEVICE_NAME); + return; + } + + + /* 清空配置结构体 */ + rt_memset(&spi_config,0,sizeof(struct rt_spi_configuration)); + + spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ + spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ + spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ + spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ + spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ + spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ + + spi_config.data_width = 8; /* 数据长度：8 */ + + spi_config.max_hz = 2000000; /* 最快时钟频率 */ + + /* 配置SPI设备 */ + s_stat = rt_spi_configure(spi_dev,&spi_config); + + if(s_stat != RT_EOK) + { + rt_kprintf(" spi config fail !\n "); + return; + } + + + /* 获取总线 ，防止总线被多个线程同时使用 */ + result = rt_spi_take_bus(spi_dev); + + if (result != RT_EOK) + { + rt_kprintf(" %s take spi bus failed! \n", SPI_DEVICE_NAME); + return; + } + + /* 选中片选 */ + result = rt_spi_take(spi_dev); + + if (result != RT_EOK) + { + rt_kprintf(" %s take spi cs failed! \n", SPI_DEVICE_NAME); + return; + } + + + /*接收一次数据*/ + result = rt_spi_recv(spi_dev,buffer,BUF_LEN); + + if(result != BUF_LEN) + { + rt_kprintf("receive fail. \n buffer is : %s \n:",buffer); + + for( i = 0 ; i < BUF_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + + return; + } + + rt_kprintf("receive successful. \n buffer is : %s \n:",buffer); + + for( i = 0 ; i < BUF_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + + /* 将接收到的数据加1 */ + for( i = 0 ; i < BUF_LEN ; i++) + buffer[i]++; + + /*发送数据*/ + result = rt_spi_send(spi_dev,buffer,BUF_LEN); + + if(result != BUF_LEN) + { + rt_kprintf("send fail. \n buffer is : %s \n:",buffer); + + for( i = 0 ; i < BUF_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + + return; + } + + rt_kprintf("send successful. \n buffer is : %s \n:",buffer); + + for( i = 0 ; i < BUF_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + + /* 释放片选 */ + result = rt_spi_release(spi_dev); + + if (result != RT_EOK) + { + rt_kprintf(" %s release spi cs failed! \n", SPI_DEVICE_NAME); + return; + } + + /* 释放总线 */ + result = rt_spi_release_bus(spi_dev); + + if (result != RT_EOK) + { + rt_kprintf(" %s release spi bus failed! \n", SPI_DEVICE_NAME); + return; + } + +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(spi_io_sample, spi sample); diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/uart_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/uart_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..cb750efe6e85bb6df03a93deaa052189112c2491 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/uart_sample.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-15 misonyo first implementation. + */ +/* + * 程序清单：这是一个 串口 设备使用例程 + * 例程导出了 uart_sample 命令到控制终端 + * 命令调用格式：uart_sample uart2 + * 命令解释：命令第二个参数是要使用的串口设备名称，为空则使用默认的串口设备 + * 程序功能：通过串口输出字符串"hello RT-Thread!"，然后错位输出输入的字符 +*/ + +#include + +#define SAMPLE_UART_NAME "uart2" /* 串口设备名称 */ + +/* 用于接收消息的信号量 */ +static struct rt_semaphore rx_sem; +static rt_device_t serial; + +/* 接收数据回调函数 */ +static rt_err_t uart_input(rt_device_t dev, rt_size_t size) +{ + /* 串口接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */ + rt_sem_release(&rx_sem); + + return RT_EOK; +} + +static void serial_thread_entry(void *parameter) +{ + char ch; + + while (1) + { + /* 从串口读取一个字节的数据，没有读取到则等待接收信号量 */ + while (rt_device_read(serial, -1, &ch, 1) != 1) + { + /* 阻塞等待接收信号量，等到信号量后再次读取数据 */ + rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + } + /* 读取到的数据通过串口错位输出 */ + ch = ch + 1; + rt_device_write(serial, 0, &ch, 1); + } +} + +static int uart_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + char uart_name[RT_NAME_MAX]; + char str[] = "hello RT-Thread!\r\n"; + + if (argc == 2) + { + rt_strncpy(uart_name, argv[1], RT_NAME_MAX); + } + else + { + rt_strncpy(uart_name, SAMPLE_UART_NAME, RT_NAME_MAX); + } + + /* 查找串口设备 */ + serial = rt_device_find(uart_name); + if (!serial) + { + rt_kprintf("find %s failed!\n", uart_name); + return RT_ERROR; + } + + /* 初始化信号量 */ + rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); + /* 以中断接收及轮询发送方式打开串口设备 */ + rt_device_open(serial, RT_DEVICE_FLAG_INT_RX); + /* 设置接收回调函数 */ + rt_device_set_rx_indicate(serial, uart_input); + /* 发送字符串 */ + rt_device_write(serial, 0, str, (sizeof(str) - 1)); + + /* 创建 serial 线程 */ + rt_thread_t thread = rt_thread_create("serial", serial_thread_entry, RT_NULL, 1024, 25, 10); + /* 创建成功则启动线程 */ + if (thread != RT_NULL) + { + rt_thread_startup(thread); + } + else + { + ret = RT_ERROR; + } + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(uart_sample, uart device sample); diff --git a/bsp/essemi/es32f0654/drivers/drv_adc.c b/bsp/essemi/es32f0654/drivers/drv_adc.c index 81a269d5c3eb5a9e9a874120bc395d10855cdce6..bc26b058020c68af87c735015f62d76250b565fa 100644 --- a/bsp/essemi/es32f0654/drivers/drv_adc.c +++ b/bsp/essemi/es32f0654/drivers/drv_adc.c @@ -146,9 +146,9 @@ static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t c RT_ASSERT(value != RT_NULL); /* config adc channel */ - nm_config.channel = es32f0_adc_get_channel(channel); - nm_config.rank = ADC_NCH_RANK_1; - nm_config.samp_time = ADC_SAMPLETIME_4; + nm_config.ch = es32f0_adc_get_channel(channel); + nm_config.idx = ADC_NCH_IDX_1; + nm_config.samp = ADC_SAMPLETIME_4; ald_adc_normal_channel_config(_hadc, &nm_config); ald_adc_normal_start(_hadc); @@ -172,16 +172,16 @@ int rt_hw_adc_init(void) /* adc function initialization */ _h_adc0.perh = ADC0; - _h_adc0.init.data_align = ADC_DATAALIGN_RIGHT; - _h_adc0.init.scan_mode = DISABLE; - _h_adc0.init.cont_mode = DISABLE; - _h_adc0.init.disc_mode = ADC_ALL_DISABLE; - _h_adc0.init.disc_nbr = ADC_DISC_NBR_1; - _h_adc0.init.conv_res = ADC_CONV_RES_10; - _h_adc0.init.clk_div = ADC_CKDIV_128; + _h_adc0.init.align = ADC_DATAALIGN_RIGHT; + _h_adc0.init.scan = DISABLE; + _h_adc0.init.cont = DISABLE; + _h_adc0.init.disc = ADC_ALL_DISABLE; + _h_adc0.init.disc_nr = ADC_DISC_NR_1; + _h_adc0.init.data_bit = ADC_CONV_BIT_12; + _h_adc0.init.div = ADC_CKDIV_128; _h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL; - _h_adc0.init.neg_ref = ADC_NEG_REF_VSS; - _h_adc0.init.pos_ref = ADC_POS_REF_VDD; + _h_adc0.init.n_ref = ADC_NEG_REF_VSS; + _h_adc0.init.p_ref = ADC_POS_REF_VDD; ald_adc_init(&_h_adc0); rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, &_h_adc0); diff --git a/bsp/essemi/es32f0654/drivers/drv_can.c b/bsp/essemi/es32f0654/drivers/drv_can.c index 0524fdaf07aa909a1d7c9b9e5f2d5ee6f4168cdd..cefddd997c68bef6f9317e9c8b9d3a52f928a3a7 100644 --- a/bsp/essemi/es32f0654/drivers/drv_can.c +++ b/bsp/essemi/es32f0654/drivers/drv_can.c @@ -248,7 +248,7 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t RT_ASSERT(IS_CAN_DATA_LEN(pmsg->len)); if ((state == CAN_STATE_READY) || - (state == CAN_STATE_BUSY_RX)) + (state == CAN_STATE_BUSY_RX0)) { /*check select mailbox is empty */ switch (1 << box_num) @@ -591,7 +591,6 @@ int rt_hw_can_init(void) filter.mode = CAN_FILTER_MODE_MASK; filter.scale = CAN_FILTER_SCALE_32; filter.active = ENABLE; - filter.bank_number = 14; can.FilterConfig = filter; can.device.config = config; diff --git a/bsp/essemi/es32f0654/drivers/drv_i2c.c b/bsp/essemi/es32f0654/drivers/drv_i2c.c index 6fa01034bf33c2fa4c844dd30a740e373d9b539e..399e1427efd2b42cf8481d69805d41062450530a 100644 --- a/bsp/essemi/es32f0654/drivers/drv_i2c.c +++ b/bsp/essemi/es32f0654/drivers/drv_i2c.c @@ -7,6 +7,7 @@ * Date Author Notes * 2019-01-24 wangyq the first version * 2019-11-01 wangyq update libraries + * 2020-12-15 liuhy update libraries */ #include @@ -29,7 +30,7 @@ static void _i2c_init(void) /* Initialize I2C Pin */ gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; + gpio_instruct.odos = GPIO_OPEN_DRAIN; gpio_instruct.pupd = GPIO_PUSH_UP; gpio_instruct.odrv = GPIO_OUT_DRIVE_NORMAL; gpio_instruct.flt = GPIO_FILTER_DISABLE; diff --git a/bsp/essemi/es32f0654/drivers/drv_pm.c b/bsp/essemi/es32f0654/drivers/drv_pm.c index 821d3bc843f138cbbeb73715912e17d5972e6de0..669514c7b89a280d92145ecdc2469403306b4db7 100644 --- a/bsp/essemi/es32f0654/drivers/drv_pm.c +++ b/bsp/essemi/es32f0654/drivers/drv_pm.c @@ -9,6 +9,7 @@ * 2019-11-01 wangyq adapt to the new power management interface */ +#include #include #include #include @@ -23,6 +24,21 @@ static void uart_console_reconfig(void) rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config); } +static void delay(void) +{ + long i; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + i = 0; + do{ + i++; + } + while (i < 10000); + + rt_hw_interrupt_enable(level); +} + /** * This function will put ES32F033x into sleep mode. * @@ -42,21 +58,25 @@ static void sleep(struct rt_pm *pm, uint8_t mode) case PM_SLEEP_MODE_LIGHT: /* Enter SLEEP Mode, Main regulator is ON */ ald_pmu_stop1_enter(); + delay(); break; case PM_SLEEP_MODE_DEEP: /* Enter STOP 2 mode */ ald_pmu_stop2_enter(); + delay(); break; case PM_SLEEP_MODE_STANDBY: /* Enter STANDBY mode */ ald_pmu_stop2_enter(); + delay(); break; case PM_SLEEP_MODE_SHUTDOWN: /* Enter SHUTDOWNN mode */ ald_pmu_stop2_enter(); + delay(); break; default: diff --git a/bsp/essemi/es32f0654/drivers/drv_spi.c b/bsp/essemi/es32f0654/drivers/drv_spi.c index a029c6c772849e6809371425574ecaf7dd86a7e8..dd376911259142c4dcfc22be6f6be16fd1ddfce1 100644 --- a/bsp/essemi/es32f0654/drivers/drv_spi.c +++ b/bsp/essemi/es32f0654/drivers/drv_spi.c @@ -7,6 +7,7 @@ * Date Author Notes * 2019-01-24 wangyq the first version * 2019-11-01 wangyq update libraries + * 2020-12-15 liuhy update libraries */ #include @@ -146,19 +147,21 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * RT_ASSERT(device != RT_NULL); RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(device->bus->parent.user_data != RT_NULL); - RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL); hspi = (spi_handle_t *)device->bus->parent.user_data; cs = device->parent.user_data; - - /* only send data */ - if (message->recv_buf == RT_NULL) + + if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL) + { + /* send & receive */ + if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL)) { if (message->cs_take) { rt_pin_write(cs->pin, 0); } - res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); + res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, + (rt_int32_t)message->length, SPITIMEOUT); if (message->cs_release) { rt_pin_write(cs->pin, 1); @@ -166,41 +169,56 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * if (res != RT_EOK) return RT_ERROR; } - - /* only receive data */ - if (message->send_buf == RT_NULL) + else { - if (message->cs_take) + /* only send data */ + if (message->recv_buf == RT_NULL) { - rt_pin_write(cs->pin, 0); + if (message->cs_take) + { + rt_pin_write(cs->pin, 0); + } + res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) + { + rt_pin_write(cs->pin, 1); + } + if (res != RT_EOK) + return RT_ERROR; } - res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) + /* only receive data */ + if (message->send_buf == RT_NULL) { - rt_pin_write(cs->pin, 1); + if (message->cs_take) + { + rt_pin_write(cs->pin, 0); + } + res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) + { + rt_pin_write(cs->pin, 1); + } + if (res != RT_EOK) + return RT_ERROR; } - if (res != RT_EOK) - return RT_ERROR; } - /* send & receive */ + } else { - if (message->cs_take) + if (message->cs_take) { rt_pin_write(cs->pin, 0); } - res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, - (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) { rt_pin_write(cs->pin, 1); } - if (res != RT_EOK) - return RT_ERROR; + return RT_EOK; } - return message->length; + } const struct rt_spi_ops es32f0_spi_ops = @@ -209,21 +227,45 @@ const struct rt_spi_ops es32f0_spi_ops = spixfer, }; -static struct rt_spi_bus _spi_bus0, _spi_bus1; -static spi_handle_t _spi0, _spi1; -int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name) + +rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name) +{ + /* define spi Instance */ + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + struct es32f0_hw_spi_cs *cs_pin = (struct es32f0_hw_spi_cs *)rt_malloc(sizeof(struct es32f0_hw_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + cs_pin->pin = pin; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, 1); + return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); +} + +#ifdef BSP_USING_SPI0 + static struct rt_spi_bus _spi_bus0; + static spi_handle_t _spi0; +#endif + +#ifdef BSP_USING_SPI1 + static struct rt_spi_bus _spi_bus1; + static spi_handle_t _spi1; +#endif + +int rt_hw_spi_init(void) { + int result = RT_EOK; + struct rt_spi_bus *spi_bus; spi_handle_t *spi; gpio_init_t gpio_instruct; - if (SPIx == SPI0) - { - _spi0.perh = SPI0; - spi_bus = &_spi_bus0; - spi = &_spi0; +#ifdef BSP_USING_SPI0 + _spi0.perh = SPI0; + spi_bus = &_spi_bus0; + spi = &_spi0; + rt_device_t spi_bus_dev0; - /* SPI0 gpio init */ + /* SPI0 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; gpio_instruct.odos = GPIO_PUSH_PULL; gpio_instruct.func = GPIO_FUNC_4; @@ -236,14 +278,33 @@ int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name) /* PB4->SPI0_MISO */ gpio_instruct.mode = GPIO_MODE_INPUT; ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct); + + spi_bus->parent.user_data = spi; + result = rt_spi_bus_register(spi_bus, "spi0", &es32f0_spi_ops); + if (result != RT_EOK) + { + return result; } - else if (SPIx == SPI1) + + rt_device_register(spi_bus_dev0, "spi00", RT_DEVICE_FLAG_RDWR); + + /* SPI0_NSS = PA15 = PIN 50 */ + result = es32f0_spi_device_attach(50, "spi0", "spi00"); + + if (result != RT_EOK) { - _spi1.perh = SPI1; - spi_bus = &_spi_bus1; - spi = &_spi1; + return result; + } + +#endif - /* SPI1 gpio init */ +#ifdef BSP_USING_SPI1 + _spi1.perh = SPI1; + spi_bus = &_spi_bus1; + spi = &_spi1; + rt_device_t spi_bus_dev0; + + /* SPI1 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; gpio_instruct.odos = GPIO_PUSH_PULL; gpio_instruct.func = GPIO_FUNC_4; @@ -256,39 +317,24 @@ int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name) /* PB14->SPI1_MISO */ gpio_instruct.mode = GPIO_MODE_INPUT; ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct); + + spi_bus->parent.user_data = spi; + result = rt_spi_bus_register(spi_bus, "spi1", &es32f0_spi_ops); + if (result != RT_EOK) + { + return result; } - else + + rt_device_register(spi_bus_dev0, "spi10", RT_DEVICE_FLAG_RDWR); + + /* SPI1_NSS = PC00 = PIN 8 */ + result = es32f0_spi_device_attach(8, "spi1", "spi10"); + + if (result != RT_EOK) { - return -1; + return result; } - spi_bus->parent.user_data = spi; - - return rt_spi_bus_register(spi_bus, name, &es32f0_spi_ops); -} - -rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name) -{ - /* define spi Instance */ - struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); - RT_ASSERT(spi_device != RT_NULL); - struct es32f0_hw_spi_cs *cs_pin = (struct es32f0_hw_spi_cs *)rt_malloc(sizeof(struct es32f0_hw_spi_cs)); - RT_ASSERT(cs_pin != RT_NULL); - cs_pin->pin = pin; - rt_pin_mode(pin, PIN_MODE_OUTPUT); - rt_pin_write(pin, 1); - return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); -} - -int rt_hw_spi_init(void) -{ - int result = 0; - -#ifdef BSP_USING_SPI0 - result = es32f0_spi_register_bus(SPI0, "spi0"); -#endif - -#ifdef BSP_USING_SPI1 - result = es32f0_spi_register_bus(SPI1, "spi1"); + #endif return result; diff --git a/bsp/essemi/es32f0654/figures/d_conf.jpg b/bsp/essemi/es32f0654/figures/d_conf.jpg new file mode 100644 index 0000000000000000000000000000000000000000..b6b206ea69341c910a63c45596bd1f55ea04c7a8 Binary files /dev/null and b/bsp/essemi/es32f0654/figures/d_conf.jpg differ diff --git a/bsp/essemi/es32f0654/figures/d_ex.jpg b/bsp/essemi/es32f0654/figures/d_ex.jpg new file mode 100644 index 0000000000000000000000000000000000000000..dc8854cd2d998d2560c02d99047753221f2d3bcc Binary files /dev/null and b/bsp/essemi/es32f0654/figures/d_ex.jpg differ diff --git a/bsp/essemi/es32f0654/figures/k_conf.jpg b/bsp/essemi/es32f0654/figures/k_conf.jpg new file mode 100644 index 0000000000000000000000000000000000000000..d900bd825105f3147d9f38919ca1e239cf55149c Binary files /dev/null and b/bsp/essemi/es32f0654/figures/k_conf.jpg differ diff --git a/bsp/essemi/es32f0654/figures/k_ex.jpg b/bsp/essemi/es32f0654/figures/k_ex.jpg new file mode 100644 index 0000000000000000000000000000000000000000..a4b1d3874d47f06a80cc6328322eaba41d62571a Binary files /dev/null and b/bsp/essemi/es32f0654/figures/k_ex.jpg differ diff --git a/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h index 645d1ff801340d0295408f37f927435cc5648918..d7e2ae7e36c145e53f8e23feae5b1f5c23ec40bc 100644 --- a/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h +++ b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h @@ -40,7 +40,7 @@ typedef enum IRQn { /* es32f0xx specific interrupt index */ WWDG_IWDG_IRQn = 0, LVD_IRQn = 1, - RTC_TSENSE_IRQn = 2, + RTC_TSENSE_IRQn = 2, CRYPT_TRNG_IRQn = 3, CMU_IRQn = 4, EXTI0_3_IRQn = 5, @@ -284,21 +284,11 @@ typedef struct #define BKPC_PCCR_RTCCS_POSE 1U #define BKPC_PCCR_RTCCS_MSK BITS(BKPC_PCCR_RTCCS_POSS,BKPC_PCCR_RTCCS_POSE) -/****************** Bit definition for BKPC_PCR register ************************/ - -#define BKPC_PCR_BORS_POSS 1U -#define BKPC_PCR_BORS_POSE 4U -#define BKPC_PCR_BORS_MSK BITS(BKPC_PCR_BORS_POSS,BKPC_PCR_BORS_POSE) - -#define BKPC_PCR_BOREN_POS 0U -#define BKPC_PCR_BOREN_MSK BIT(BKPC_PCR_BOREN_POS) - typedef struct { __IO uint32_t PROT; __IO uint32_t CR; __IO uint32_t PCCR; - __IO uint32_t PCR; } BKPC_TypeDef; /****************** Bit definition for PMU_CR register ************************/ @@ -1847,18 +1837,18 @@ typedef struct #define RTC_TAMPCON_TAMPTS_POS 16U #define RTC_TAMPCON_TAMPTS_MSK BIT(RTC_TAMPCON_TAMPTS_POS) -#define RTC_TAMPCON_TAMP2LV_POS 9U -#define RTC_TAMPCON_TAMP2LV_MSK BIT(RTC_TAMPCON_TAMP2LV_POS) - -#define RTC_TAMPCON_TAMP2EN_POS 8U -#define RTC_TAMPCON_TAMP2EN_MSK BIT(RTC_TAMPCON_TAMP2EN_POS) - -#define RTC_TAMPCON_TAMP1LV_POS 1U +#define RTC_TAMPCON_TAMP1LV_POS 9U #define RTC_TAMPCON_TAMP1LV_MSK BIT(RTC_TAMPCON_TAMP1LV_POS) -#define RTC_TAMPCON_TAMP1EN_POS 0U +#define RTC_TAMPCON_TAMP1EN_POS 8U #define RTC_TAMPCON_TAMP1EN_MSK BIT(RTC_TAMPCON_TAMP1EN_POS) +#define RTC_TAMPCON_TAMP0LV_POS 1U +#define RTC_TAMPCON_TAMP0LV_MSK BIT(RTC_TAMPCON_TAMP0LV_POS) + +#define RTC_TAMPCON_TAMP0EN_POS 0U +#define RTC_TAMPCON_TAMP0EN_MSK BIT(RTC_TAMPCON_TAMP0EN_POS) + /****************** Bit definition for RTC_TIME register ************************/ #define RTC_TIME_PM_POS 22U @@ -2151,12 +2141,12 @@ typedef struct #define RTC_IER_RSC_POS 16U #define RTC_IER_RSC_MSK BIT(RTC_IER_RSC_POS) -#define RTC_IER_TAMP2_POS 13U -#define RTC_IER_TAMP2_MSK BIT(RTC_IER_TAMP2_POS) - -#define RTC_IER_TAMP1_POS 12U +#define RTC_IER_TAMP1_POS 13U #define RTC_IER_TAMP1_MSK BIT(RTC_IER_TAMP1_POS) +#define RTC_IER_TAMP0_POS 12U +#define RTC_IER_TAMP0_MSK BIT(RTC_IER_TAMP0_POS) + #define RTC_IER_TSOV_POS 11U #define RTC_IER_TSOV_MSK BIT(RTC_IER_TSOV_POS) @@ -2204,12 +2194,12 @@ typedef struct #define RTC_IFR_RSCF_POS 16U #define RTC_IFR_RSCF_MSK BIT(RTC_IFR_RSCF_POS) -#define RTC_IFR_TAMP2F_POS 13U -#define RTC_IFR_TAMP2F_MSK BIT(RTC_IFR_TAMP2F_POS) - -#define RTC_IFR_TAMP1F_POS 12U +#define RTC_IFR_TAMP1F_POS 13U #define RTC_IFR_TAMP1F_MSK BIT(RTC_IFR_TAMP1F_POS) +#define RTC_IFR_TAMP0F_POS 12U +#define RTC_IFR_TAMP0F_MSK BIT(RTC_IFR_TAMP0F_POS) + #define RTC_IFR_TSOVF_POS 11U #define RTC_IFR_TSOVF_MSK BIT(RTC_IFR_TSOVF_POS) @@ -2257,17 +2247,17 @@ typedef struct #define RTC_IFCR_RSCFC_POS 16U #define RTC_IFCR_RSCFC_MSK BIT(RTC_IFCR_RSCFC_POS) -#define RTC_IFCR_TAMP2FC_POS 13U -#define RTC_IFCR_TAMP2FC_MSK BIT(RTC_IFCR_TAMP2FC_POS) - -#define RTC_IFCR_TAMP1FC_POS 12U +#define RTC_IFCR_TAMP1FC_POS 13U #define RTC_IFCR_TAMP1FC_MSK BIT(RTC_IFCR_TAMP1FC_POS) +#define RTC_IFCR_TAMP0FC_POS 12U +#define RTC_IFCR_TAMP0FC_MSK BIT(RTC_IFCR_TAMP0FC_POS) + #define RTC_IFCR_TSOVFC_POS 11U #define RTC_IFCR_TSOVFC_MSK BIT(RTC_IFCR_TSOVFC_POS) -#define RTC_IFCR_TSSTC_POS 10U -#define RTC_IFCR_TSSTC_MSK BIT(RTC_IFCR_TSSTC_POS) +#define RTC_IFCR_TSFC_POS 10U +#define RTC_IFCR_TSFC_MSK BIT(RTC_IFCR_TSFC_POS) #define RTC_IFCR_ALMBFC_POS 9U #define RTC_IFCR_ALMBFC_MSK BIT(RTC_IFCR_ALMBFC_POS) @@ -2310,12 +2300,12 @@ typedef struct #define RTC_ISR_RSCF_POS 16U #define RTC_ISR_RSCF_MSK BIT(RTC_ISR_RSCF_POS) -#define RTC_ISR_TAMP2F_POS 13U -#define RTC_ISR_TAMP2F_MSK BIT(RTC_ISR_TAMP2F_POS) - -#define RTC_ISR_TAMP1F_POS 12U +#define RTC_ISR_TAMP1F_POS 13U #define RTC_ISR_TAMP1F_MSK BIT(RTC_ISR_TAMP1F_POS) +#define RTC_ISR_TAMP0F_POS 12U +#define RTC_ISR_TAMP0F_MSK BIT(RTC_ISR_TAMP0F_POS) + #define RTC_ISR_TSOVF_POS 11U #define RTC_ISR_TSOVF_MSK BIT(RTC_ISR_TSOVF_POS) @@ -3689,360 +3679,6 @@ typedef struct __O uint32_t ICR; } UART_TypeDef; -/****************** Bit definition for LPUART_CON0 register ************************/ - -#define LPUART_CON0_MODESEL_POSS 30U -#define LPUART_CON0_MODESEL_POSE 31U -#define LPUART_CON0_MODESEL_MSK BITS(LPUART_CON0_MODESEL_POSS,LPUART_CON0_MODESEL_POSE) - -#define LPUART_CON0_TXDMAE_POS 29U -#define LPUART_CON0_TXDMAE_MSK BIT(LPUART_CON0_TXDMAE_POS) - -#define LPUART_CON0_RXDMAE_POS 28U -#define LPUART_CON0_RXDMAE_MSK BIT(LPUART_CON0_RXDMAE_POS) - -#define LPUART_CON0_INTERVAL_POSS 16U -#define LPUART_CON0_INTERVAL_POSE 23U -#define LPUART_CON0_INTERVAL_MSK BITS(LPUART_CON0_INTERVAL_POSS,LPUART_CON0_INTERVAL_POSE) - -#define LPUART_CON0_SYNCBP_POS 15U -#define LPUART_CON0_SYNCBP_MSK BIT(LPUART_CON0_SYNCBP_POS) - -#define LPUART_CON0_CTSPOL_POS 13U -#define LPUART_CON0_CTSPOL_MSK BIT(LPUART_CON0_CTSPOL_POS) - -#define LPUART_CON0_RTSPOL_POS 12U -#define LPUART_CON0_RTSPOL_MSK BIT(LPUART_CON0_RTSPOL_POS) - -#define LPUART_CON0_ATCTSE_POS 11U -#define LPUART_CON0_ATCTSE_MSK BIT(LPUART_CON0_ATCTSE_POS) - -#define LPUART_CON0_ATRTSE_POS 10U -#define LPUART_CON0_ATRTSE_MSK BIT(LPUART_CON0_ATRTSE_POS) - -#define LPUART_CON0_BRKCE_POS 8U -#define LPUART_CON0_BRKCE_MSK BIT(LPUART_CON0_BRKCE_POS) - -#define LPUART_CON0_LPBMOD_POS 7U -#define LPUART_CON0_LPBMOD_MSK BIT(LPUART_CON0_LPBMOD_POS) - -#define LPUART_CON0_STICKPARSEL_POS 6U -#define LPUART_CON0_STICKPARSEL_MSK BIT(LPUART_CON0_STICKPARSEL_POS) - -#define LPUART_CON0_EVENPARSEL_POS 5U -#define LPUART_CON0_EVENPARSEL_MSK BIT(LPUART_CON0_EVENPARSEL_POS) - -#define LPUART_CON0_PARCHKE_POS 4U -#define LPUART_CON0_PARCHKE_MSK BIT(LPUART_CON0_PARCHKE_POS) - -#define LPUART_CON0_STPLENTH_POS 3U -#define LPUART_CON0_STPLENTH_MSK BIT(LPUART_CON0_STPLENTH_POS) - -#define LPUART_CON0_DATLENTH_POSS 0U -#define LPUART_CON0_DATLENTH_POSE 2U -#define LPUART_CON0_DATLENTH_MSK BITS(LPUART_CON0_DATLENTH_POSS,LPUART_CON0_DATLENTH_POSE) - -/****************** Bit definition for LPUART_CON1 register ************************/ - -#define LPUART_CON1_ADDCMP_POSS 24U -#define LPUART_CON1_ADDCMP_POSE 31U -#define LPUART_CON1_ADDCMP_MSK BITS(LPUART_CON1_ADDCMP_POSS,LPUART_CON1_ADDCMP_POSE) - -#define LPUART_CON1_ADETE_POS 23U -#define LPUART_CON1_ADETE_MSK BIT(LPUART_CON1_ADETE_POS) - -#define LPUART_CON1_ATDIRM_POS 22U -#define LPUART_CON1_ATDIRM_MSK BIT(LPUART_CON1_ATDIRM_POS) - -#define LPUART_CON1_ATADETE_POS 21U -#define LPUART_CON1_ATADETE_MSK BIT(LPUART_CON1_ATADETE_POS) - -#define LPUART_CON1_NMPMOD_POS 20U -#define LPUART_CON1_NMPMOD_MSK BIT(LPUART_CON1_NMPMOD_POS) - -#define LPUART_CON1_IRWIDTH_POS 16U -#define LPUART_CON1_IRWIDTH_MSK BIT(LPUART_CON1_IRWIDTH_POS) - -#define LPUART_CON1_TOICMP_POSS 8U -#define LPUART_CON1_TOICMP_POSE 15U -#define LPUART_CON1_TOICMP_MSK BITS(LPUART_CON1_TOICMP_POSS,LPUART_CON1_TOICMP_POSE) - -#define LPUART_CON1_TOCNTE_POS 7U -#define LPUART_CON1_TOCNTE_MSK BIT(LPUART_CON1_TOCNTE_POS) - -#define LPUART_CON1_IRTXINV_POS 3U -#define LPUART_CON1_IRTXINV_MSK BIT(LPUART_CON1_IRTXINV_POS) - -#define LPUART_CON1_IRRXINV_POS 2U -#define LPUART_CON1_IRRXINV_MSK BIT(LPUART_CON1_IRRXINV_POS) - -#define LPUART_CON1_IRTXE_POS 1U -#define LPUART_CON1_IRTXE_MSK BIT(LPUART_CON1_IRTXE_POS) - -#define LPUART_CON1_RTS_POS 0U -#define LPUART_CON1_RTS_MSK BIT(LPUART_CON1_RTS_POS) - -/****************** Bit definition for LPUART_CLKDIV register ************************/ - -#define LPUART_CLKDIV_CLKDIV_POSS 0U -#define LPUART_CLKDIV_CLKDIV_POSE 19U -#define LPUART_CLKDIV_CLKDIV_MSK BITS(LPUART_CLKDIV_CLKDIV_POSS,LPUART_CLKDIV_CLKDIV_POSE) - -/****************** Bit definition for LPUART_FIFOCON register ************************/ - -#define LPUART_FIFOCON_RTSTRGLVL_POSS 12U -#define LPUART_FIFOCON_RTSTRGLVL_POSE 15U -#define LPUART_FIFOCON_RTSTRGLVL_MSK BITS(LPUART_FIFOCON_RTSTRGLVL_POSS,LPUART_FIFOCON_RTSTRGLVL_POSE) - -#define LPUART_FIFOCON_RXTRGLVL_POSS 8U -#define LPUART_FIFOCON_RXTRGLVL_POSE 11U -#define LPUART_FIFOCON_RXTRGLVL_MSK BITS(LPUART_FIFOCON_RXTRGLVL_POSS,LPUART_FIFOCON_RXTRGLVL_POSE) - -#define LPUART_FIFOCON_NMPMRXDIS_POS 2U -#define LPUART_FIFOCON_NMPMRXDIS_MSK BIT(LPUART_FIFOCON_NMPMRXDIS_POS) - -#define LPUART_FIFOCON_TXRESET_POS 1U -#define LPUART_FIFOCON_TXRESET_MSK BIT(LPUART_FIFOCON_TXRESET_POS) - -#define LPUART_FIFOCON_RXRESET_POS 0U -#define LPUART_FIFOCON_RXRESET_MSK BIT(LPUART_FIFOCON_RXRESET_POS) - -/****************** Bit definition for LPUART_RXDR register ************************/ - -#define LPUART_RXDR_FERR_POS 15U -#define LPUART_RXDR_FERR_MSK BIT(LPUART_RXDR_FERR_POS) - -#define LPUART_RXDR_PERR_POS 14U -#define LPUART_RXDR_PERR_MSK BIT(LPUART_RXDR_PERR_POS) - -#define LPUART_RXDR_RXDR_POSS 0U -#define LPUART_RXDR_RXDR_POSE 8U -#define LPUART_RXDR_RXDR_MSK BITS(LPUART_RXDR_RXDR_POSS,LPUART_RXDR_RXDR_POSE) - -/****************** Bit definition for LPUART_TXDR register ************************/ - -#define LPUART_TXDR_TXDR_POSS 0U -#define LPUART_TXDR_TXDR_POSE 8U -#define LPUART_TXDR_TXDR_MSK BITS(LPUART_TXDR_TXDR_POSS,LPUART_TXDR_TXDR_POSE) - -/****************** Bit definition for LPUART_STAT register ************************/ - -#define LPUART_STAT_RTSSTAT_POS 18U -#define LPUART_STAT_RTSSTAT_MSK BIT(LPUART_STAT_RTSSTAT_POS) - -#define LPUART_STAT_CTSSTAT_POS 17U -#define LPUART_STAT_CTSSTAT_MSK BIT(LPUART_STAT_CTSSTAT_POS) - -#define LPUART_STAT_TXIDLE_POS 16U -#define LPUART_STAT_TXIDLE_MSK BIT(LPUART_STAT_TXIDLE_POS) - -#define LPUART_STAT_TXFULL_POS 15U -#define LPUART_STAT_TXFULL_MSK BIT(LPUART_STAT_TXFULL_POS) - -#define LPUART_STAT_TXEMP_POS 14U -#define LPUART_STAT_TXEMP_MSK BIT(LPUART_STAT_TXEMP_POS) - -#define LPUART_STAT_TXPTR_POSS 8U -#define LPUART_STAT_TXPTR_POSE 13U -#define LPUART_STAT_TXPTR_MSK BITS(LPUART_STAT_TXPTR_POSS,LPUART_STAT_TXPTR_POSE) - -#define LPUART_STAT_RXFULL_POS 7U -#define LPUART_STAT_RXFULL_MSK BIT(LPUART_STAT_RXFULL_POS) - -#define LPUART_STAT_RXEMP_POS 6U -#define LPUART_STAT_RXEMP_MSK BIT(LPUART_STAT_RXEMP_POS) - -#define LPUART_STAT_RXPTR_POSS 0U -#define LPUART_STAT_RXPTR_POSE 5U -#define LPUART_STAT_RXPTR_MSK BITS(LPUART_STAT_RXPTR_POSS,LPUART_STAT_RXPTR_POSE) - -/****************** Bit definition for LPUART_IER register ************************/ - -#define LPUART_IER_TCIE_POS 15U -#define LPUART_IER_TCIE_MSK BIT(LPUART_IER_TCIE_POS) - -#define LPUART_IER_ADETIE_POS 12U -#define LPUART_IER_ADETIE_MSK BIT(LPUART_IER_ADETIE_POS) - -#define LPUART_IER_BRKERRIE_POS 11U -#define LPUART_IER_BRKERRIE_MSK BIT(LPUART_IER_BRKERRIE_POS) - -#define LPUART_IER_FERRIE_POS 10U -#define LPUART_IER_FERRIE_MSK BIT(LPUART_IER_FERRIE_POS) - -#define LPUART_IER_PERRIE_POS 9U -#define LPUART_IER_PERRIE_MSK BIT(LPUART_IER_PERRIE_POS) - -#define LPUART_IER_DATWKIE_POS 8U -#define LPUART_IER_DATWKIE_MSK BIT(LPUART_IER_DATWKIE_POS) - -#define LPUART_IER_CTSWKIE_POS 7U -#define LPUART_IER_CTSWKIE_MSK BIT(LPUART_IER_CTSWKIE_POS) - -#define LPUART_IER_TXOVIE_POS 5U -#define LPUART_IER_TXOVIE_MSK BIT(LPUART_IER_TXOVIE_POS) - -#define LPUART_IER_RXOVIE_POS 4U -#define LPUART_IER_RXOVIE_MSK BIT(LPUART_IER_RXOVIE_POS) - -#define LPUART_IER_RXTOIE_POS 3U -#define LPUART_IER_RXTOIE_MSK BIT(LPUART_IER_RXTOIE_POS) - -#define LPUART_IER_CTSDETIE_POS 2U -#define LPUART_IER_CTSDETIE_MSK BIT(LPUART_IER_CTSDETIE_POS) - -#define LPUART_IER_TBEMPIE_POS 1U -#define LPUART_IER_TBEMPIE_MSK BIT(LPUART_IER_TBEMPIE_POS) - -#define LPUART_IER_RBRIE_POS 0U -#define LPUART_IER_RBRIE_MSK BIT(LPUART_IER_RBRIE_POS) - -/****************** Bit definition for LPUART_IFLAG register ************************/ - -#define LPUART_IFLAG_TCIF_POS 15U -#define LPUART_IFLAG_TCIF_MSK BIT(LPUART_IFLAG_TCIF_POS) - -#define LPUART_IFLAG_ADETIF_POS 12U -#define LPUART_IFLAG_ADETIF_MSK BIT(LPUART_IFLAG_ADETIF_POS) - -#define LPUART_IFLAG_BRKERRIF_POS 11U -#define LPUART_IFLAG_BRKERRIF_MSK BIT(LPUART_IFLAG_BRKERRIF_POS) - -#define LPUART_IFLAG_FERRIF_POS 10U -#define LPUART_IFLAG_FERRIF_MSK BIT(LPUART_IFLAG_FERRIF_POS) - -#define LPUART_IFLAG_PERRIF_POS 9U -#define LPUART_IFLAG_PERRIF_MSK BIT(LPUART_IFLAG_PERRIF_POS) - -#define LPUART_IFLAG_DATWKIF_POS 8U -#define LPUART_IFLAG_DATWKIF_MSK BIT(LPUART_IFLAG_DATWKIF_POS) - -#define LPUART_IFLAG_CTSWKIF_POS 7U -#define LPUART_IFLAG_CTSWKIF_MSK BIT(LPUART_IFLAG_CTSWKIF_POS) - -#define LPUART_IFLAG_TXOVIF_POS 5U -#define LPUART_IFLAG_TXOVIF_MSK BIT(LPUART_IFLAG_TXOVIF_POS) - -#define LPUART_IFLAG_RXOVIF_POS 4U -#define LPUART_IFLAG_RXOVIF_MSK BIT(LPUART_IFLAG_RXOVIF_POS) - -#define LPUART_IFLAG_RXTOIF_POS 3U -#define LPUART_IFLAG_RXTOIF_MSK BIT(LPUART_IFLAG_RXTOIF_POS) - -#define LPUART_IFLAG_CTSDETIF_POS 2U -#define LPUART_IFLAG_CTSDETIF_MSK BIT(LPUART_IFLAG_CTSDETIF_POS) - -#define LPUART_IFLAG_TBEMPIF_POS 1U -#define LPUART_IFLAG_TBEMPIF_MSK BIT(LPUART_IFLAG_TBEMPIF_POS) - -#define LPUART_IFLAG_RBRIF_POS 0U -#define LPUART_IFLAG_RBRIF_MSK BIT(LPUART_IFLAG_RBRIF_POS) - -/****************** Bit definition for LPUART_IFC register ************************/ - -#define LPUART_IFC_TCIFC_POS 15U -#define LPUART_IFC_TCIFC_MSK BIT(LPUART_IFC_TCIFC_POS) - -#define LPUART_IFC_ADETIFC_POS 12U -#define LPUART_IFC_ADETIFC_MSK BIT(LPUART_IFC_ADETIFC_POS) - -#define LPUART_IFC_BRKERRIFC_POS 11U -#define LPUART_IFC_BRKERRIFC_MSK BIT(LPUART_IFC_BRKERRIFC_POS) - -#define LPUART_IFC_FERRIFC_POS 10U -#define LPUART_IFC_FERRIFC_MSK BIT(LPUART_IFC_FERRIFC_POS) - -#define LPUART_IFC_PERRIFC_POS 9U -#define LPUART_IFC_PERRIFC_MSK BIT(LPUART_IFC_PERRIFC_POS) - -#define LPUART_IFC_DATWKIFC_POS 8U -#define LPUART_IFC_DATWKIFC_MSK BIT(LPUART_IFC_DATWKIFC_POS) - -#define LPUART_IFC_CTSWKIFC_POS 7U -#define LPUART_IFC_CTSWKIFC_MSK BIT(LPUART_IFC_CTSWKIFC_POS) - -#define LPUART_IFC_TXOVIFC_POS 5U -#define LPUART_IFC_TXOVIFC_MSK BIT(LPUART_IFC_TXOVIFC_POS) - -#define LPUART_IFC_RXOVIFC_POS 4U -#define LPUART_IFC_RXOVIFC_MSK BIT(LPUART_IFC_RXOVIFC_POS) - -#define LPUART_IFC_CTSDETIFC_POS 2U -#define LPUART_IFC_CTSDETIFC_MSK BIT(LPUART_IFC_CTSDETIFC_POS) - -#define LPUART_IFC_TBEMPIFC_POS 1U -#define LPUART_IFC_TBEMPIFC_MSK BIT(LPUART_IFC_TBEMPIFC_POS) - -#define LPUART_IFC_RBRIFC_POS 0U -#define LPUART_IFC_RBRIFC_MSK BIT(LPUART_IFC_RBRIFC_POS) - -/****************** Bit definition for LPUART_ISTAT register ************************/ - -#define LPUART_ISTAT_TCINT_POS 15U -#define LPUART_ISTAT_TCINT_MSK BIT(LPUART_ISTAT_TCINT_POS) - -#define LPUART_ISTAT_RXSTATINT_POS 9U -#define LPUART_ISTAT_RXSTATINT_MSK BIT(LPUART_ISTAT_RXSTATINT_POS) - -#define LPUART_ISTAT_DATWKINT_POS 8U -#define LPUART_ISTAT_DATWKINT_MSK BIT(LPUART_ISTAT_DATWKINT_POS) - -#define LPUART_ISTAT_CTSWKINT_POS 7U -#define LPUART_ISTAT_CTSWKINT_MSK BIT(LPUART_ISTAT_CTSWKINT_POS) - -#define LPUART_ISTAT_BUFERRINT_POS 4U -#define LPUART_ISTAT_BUFERRINT_MSK BIT(LPUART_ISTAT_BUFERRINT_POS) - -#define LPUART_ISTAT_RXTOINT_POS 3U -#define LPUART_ISTAT_RXTOINT_MSK BIT(LPUART_ISTAT_RXTOINT_POS) - -#define LPUART_ISTAT_CTSDETINT_POS 2U -#define LPUART_ISTAT_CTSDETINT_MSK BIT(LPUART_ISTAT_CTSDETINT_POS) - -#define LPUART_ISTAT_TBEMPINT_POS 1U -#define LPUART_ISTAT_TBEMPINT_MSK BIT(LPUART_ISTAT_TBEMPINT_POS) - -#define LPUART_ISTAT_RBRINT_POS 0U -#define LPUART_ISTAT_RBRINT_MSK BIT(LPUART_ISTAT_RBRINT_POS) - -/****************** Bit definition for LPUART_UPDATE register ************************/ - -#define LPUART_UPDATE_UDIS_POS 0U -#define LPUART_UPDATE_UDIS_MSK BIT(LPUART_UPDATE_UDIS_POS) - -/****************** Bit definition for LPUART_SYNCSTAT register ************************/ - -#define LPUART_SYNCSTAT_FIFOCONWBSY_POS 3U -#define LPUART_SYNCSTAT_FIFOCONWBSY_MSK BIT(LPUART_SYNCSTAT_FIFOCONWBSY_POS) - -#define LPUART_SYNCSTAT_CLKDIVWBSY_POS 2U -#define LPUART_SYNCSTAT_CLKDIVWBSY_MSK BIT(LPUART_SYNCSTAT_CLKDIVWBSY_POS) - -#define LPUART_SYNCSTAT_CON1WBSY_POS 1U -#define LPUART_SYNCSTAT_CON1WBSY_MSK BIT(LPUART_SYNCSTAT_CON1WBSY_POS) - -#define LPUART_SYNCSTAT_CON0WBSY_POS 0U -#define LPUART_SYNCSTAT_CON0WBSY_MSK BIT(LPUART_SYNCSTAT_CON0WBSY_POS) - -typedef struct -{ - __IO uint32_t CON0; - __IO uint32_t CON1; - __IO uint32_t CLKDIV; - __IO uint32_t FIFOCON; - uint32_t RESERVED0 ; - __I uint32_t RXDR; - __O uint32_t TXDR; - __I uint32_t STAT; - __IO uint32_t IER; - __I uint32_t IFLAG; - __O uint32_t IFC; - __I uint32_t ISTAT; - uint32_t RESERVED1[2] ; - __IO uint32_t UPDATE; - __I uint32_t SYNCSTAT; -} LPUART_TypeDef; - /****************** Bit definition for SPI_CON1 register ************************/ #define SPI_CON1_BIDEN_POS 15U @@ -5246,158 +4882,6 @@ typedef struct __IO uint32_t FIFO; } CRYPT_TypeDef; -/****************** Bit definition for LCD_CR register ************************/ - -#define LCD_CR_VCHPS_POSS 24U -#define LCD_CR_VCHPS_POSE 25U -#define LCD_CR_VCHPS_MSK BITS(LCD_CR_VCHPS_POSS,LCD_CR_VCHPS_POSE) - -#define LCD_CR_DSLD_POSS 20U -#define LCD_CR_DSLD_POSE 23U -#define LCD_CR_DSLD_MSK BITS(LCD_CR_DSLD_POSS,LCD_CR_DSLD_POSE) - -#define LCD_CR_DSHD_POSS 16U -#define LCD_CR_DSHD_POSE 19U -#define LCD_CR_DSHD_MSK BITS(LCD_CR_DSHD_POSS,LCD_CR_DSHD_POSE) - -#define LCD_CR_VBUFLD_POS 15U -#define LCD_CR_VBUFLD_MSK BIT(LCD_CR_VBUFLD_POS) - -#define LCD_CR_VBUFHD_POS 14U -#define LCD_CR_VBUFHD_MSK BIT(LCD_CR_VBUFHD_POS) - -#define LCD_CR_RESLD_POSS 12U -#define LCD_CR_RESLD_POSE 13U -#define LCD_CR_RESLD_MSK BITS(LCD_CR_RESLD_POSS,LCD_CR_RESLD_POSE) - -#define LCD_CR_RESHD_POSS 10U -#define LCD_CR_RESHD_POSE 11U -#define LCD_CR_RESHD_MSK BITS(LCD_CR_RESHD_POSS,LCD_CR_RESHD_POSE) - -#define LCD_CR_BIAS_POSS 8U -#define LCD_CR_BIAS_POSE 9U -#define LCD_CR_BIAS_MSK BITS(LCD_CR_BIAS_POSS,LCD_CR_BIAS_POSE) - -#define LCD_CR_DUTY_POSS 4U -#define LCD_CR_DUTY_POSE 6U -#define LCD_CR_DUTY_MSK BITS(LCD_CR_DUTY_POSS,LCD_CR_DUTY_POSE) - -#define LCD_CR_OE_POS 3U -#define LCD_CR_OE_MSK BIT(LCD_CR_OE_POS) - -#define LCD_CR_VSEL_POSS 1U -#define LCD_CR_VSEL_POSE 2U -#define LCD_CR_VSEL_MSK BITS(LCD_CR_VSEL_POSS,LCD_CR_VSEL_POSE) - -#define LCD_CR_EN_POS 0U -#define LCD_CR_EN_MSK BIT(LCD_CR_EN_POS) - -/****************** Bit definition for LCD_FCR register ************************/ - -#define LCD_FCR_WFS_POS 31U -#define LCD_FCR_WFS_MSK BIT(LCD_FCR_WFS_POS) - -#define LCD_FCR_PRS_POSS 24U -#define LCD_FCR_PRS_POSE 27U -#define LCD_FCR_PRS_MSK BITS(LCD_FCR_PRS_POSS,LCD_FCR_PRS_POSE) - -#define LCD_FCR_DIV_POSS 20U -#define LCD_FCR_DIV_POSE 23U -#define LCD_FCR_DIV_MSK BITS(LCD_FCR_DIV_POSS,LCD_FCR_DIV_POSE) - -#define LCD_FCR_BLMOD_POSS 16U -#define LCD_FCR_BLMOD_POSE 17U -#define LCD_FCR_BLMOD_MSK BITS(LCD_FCR_BLMOD_POSS,LCD_FCR_BLMOD_POSE) - -#define LCD_FCR_BLFRQ_POSS 12U -#define LCD_FCR_BLFRQ_POSE 14U -#define LCD_FCR_BLFRQ_MSK BITS(LCD_FCR_BLFRQ_POSS,LCD_FCR_BLFRQ_POSE) - -#define LCD_FCR_DEAD_POSS 8U -#define LCD_FCR_DEAD_POSE 10U -#define LCD_FCR_DEAD_MSK BITS(LCD_FCR_DEAD_POSS,LCD_FCR_DEAD_POSE) - -#define LCD_FCR_HD_POS 7U -#define LCD_FCR_HD_MSK BIT(LCD_FCR_HD_POS) - -#define LCD_FCR_PON_POSS 4U -#define LCD_FCR_PON_POSE 6U -#define LCD_FCR_PON_MSK BITS(LCD_FCR_PON_POSS,LCD_FCR_PON_POSE) - -#define LCD_FCR_VGS_POSS 0U -#define LCD_FCR_VGS_POSE 3U -#define LCD_FCR_VGS_MSK BITS(LCD_FCR_VGS_POSS,LCD_FCR_VGS_POSE) - -/****************** Bit definition for LCD_SEGCR0 register ************************/ - -#define LCD_SEGCR0_SEG_OE_POSS 0U -#define LCD_SEGCR0_SEG_OE_POSE 31U -#define LCD_SEGCR0_SEG_OE_MSK BITS(LCD_SEGCR0_SEG_OE_POSS,LCD_SEGCR0_SEG_OE_POSE) - -/****************** Bit definition for LCD_SEGCR1 register ************************/ - -#define LCD_SEGCR1_SEG_OE_POSS 0U -#define LCD_SEGCR1_SEG_OE_POSE 11U -#define LCD_SEGCR1_SEG_OE_MSK BITS(LCD_SEGCR1_SEG_OE_POSS,LCD_SEGCR1_SEG_OE_POSE) - -/****************** Bit definition for LCD_IE register ************************/ - -#define LCD_IE_UDDIE_POS 1U -#define LCD_IE_UDDIE_MSK BIT(LCD_IE_UDDIE_POS) - -#define LCD_IE_SOFIE_POS 0U -#define LCD_IE_SOFIE_MSK BIT(LCD_IE_SOFIE_POS) - -/****************** Bit definition for LCD_IF register ************************/ - -#define LCD_IF_UDDIF_POS 1U -#define LCD_IF_UDDIF_MSK BIT(LCD_IF_UDDIF_POS) - -#define LCD_IF_SOFIF_POS 0U -#define LCD_IF_SOFIF_MSK BIT(LCD_IF_SOFIF_POS) - -/****************** Bit definition for LCD_IFCR register ************************/ - -#define LCD_IFCR_UDDIFC_POS 1U -#define LCD_IFCR_UDDIFC_MSK BIT(LCD_IFCR_UDDIFC_POS) - -#define LCD_IFCR_SOFIFC_POS 0U -#define LCD_IFCR_SOFIFC_MSK BIT(LCD_IFCR_SOFIFC_POS) - -/****************** Bit definition for LCD_SR register ************************/ - -#define LCD_SR_FCRSF_POS 3U -#define LCD_SR_FCRSF_MSK BIT(LCD_SR_FCRSF_POS) - -#define LCD_SR_UDR_POS 2U -#define LCD_SR_UDR_MSK BIT(LCD_SR_UDR_POS) - -#define LCD_SR_ENS_POS 1U -#define LCD_SR_ENS_MSK BIT(LCD_SR_ENS_POS) - -#define LCD_SR_RDY_POS 0U -#define LCD_SR_RDY_MSK BIT(LCD_SR_RDY_POS) - -/****************** Bit definition for LCD_BUF register ************************/ - -#define LCD_BUF_SEG_DATA_POSS 0U -#define LCD_BUF_SEG_DATA_POSE 31U -#define LCD_BUF_SEG_DATA_MSK BITS(LCD_BUF_SEG_DATA_POSS,LCD_BUF_SEG_DATA_POSE) - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t FCR; - __IO uint32_t SEGCR0; - __IO uint32_t SEGCR1; - __IO uint32_t IE; - __I uint32_t IF; - __O uint32_t IFCR; - __I uint32_t SR; - uint32_t RESERVED0[8] ; - __IO uint32_t BUF[16]; -} LCD_TypeDef; - /****************** Bit definition for ADC_STAT register ************************/ #define ADC_STAT_ICHS_POS 9U @@ -6282,138 +5766,6 @@ typedef struct __IO uint32_t LOCK; } WWDT_TypeDef; -/****************** Bit definition for LP16T_CON0 register ************************/ - -#define LP16T_CON0_PRELOAD_POS 22U -#define LP16T_CON0_PRELOAD_MSK BIT(LP16T_CON0_PRELOAD_POS) - -#define LP16T_CON0_WAVEPOL_POS 21U -#define LP16T_CON0_WAVEPOL_MSK BIT(LP16T_CON0_WAVEPOL_POS) - -#define LP16T_CON0_WAVE_POSS 19U -#define LP16T_CON0_WAVE_POSE 20U -#define LP16T_CON0_WAVE_MSK BITS(LP16T_CON0_WAVE_POSS,LP16T_CON0_WAVE_POSE) - -#define LP16T_CON0_TRIGEN_POSS 17U -#define LP16T_CON0_TRIGEN_POSE 18U -#define LP16T_CON0_TRIGEN_MSK BITS(LP16T_CON0_TRIGEN_POSS,LP16T_CON0_TRIGEN_POSE) - -#define LP16T_CON0_TRIGSEL_POSS 13U -#define LP16T_CON0_TRIGSEL_POSE 15U -#define LP16T_CON0_TRIGSEL_MSK BITS(LP16T_CON0_TRIGSEL_POSS,LP16T_CON0_TRIGSEL_POSE) - -#define LP16T_CON0_PRESC_POSS 9U -#define LP16T_CON0_PRESC_POSE 11U -#define LP16T_CON0_PRESC_MSK BITS(LP16T_CON0_PRESC_POSS,LP16T_CON0_PRESC_POSE) - -#define LP16T_CON0_TRGFLT_POSS 6U -#define LP16T_CON0_TRGFLT_POSE 7U -#define LP16T_CON0_TRGFLT_MSK BITS(LP16T_CON0_TRGFLT_POSS,LP16T_CON0_TRGFLT_POSE) - -#define LP16T_CON0_CKFLT_POSS 3U -#define LP16T_CON0_CKFLT_POSE 4U -#define LP16T_CON0_CKFLT_MSK BITS(LP16T_CON0_CKFLT_POSS,LP16T_CON0_CKFLT_POSE) - -#define LP16T_CON0_CKPOL_POS 1U -#define LP16T_CON0_CKPOL_MSK BIT(LP16T_CON0_CKPOL_POS) - -#define LP16T_CON0_CKSEL_POS 0U -#define LP16T_CON0_CKSEL_MSK BIT(LP16T_CON0_CKSEL_POS) - -/****************** Bit definition for LP16T_CON1 register ************************/ - -#define LP16T_CON1_CNTSTRT_POS 2U -#define LP16T_CON1_CNTSTRT_MSK BIT(LP16T_CON1_CNTSTRT_POS) - -#define LP16T_CON1_SNGSTRT_POS 1U -#define LP16T_CON1_SNGSTRT_MSK BIT(LP16T_CON1_SNGSTRT_POS) - -#define LP16T_CON1_ENABLE_POS 0U -#define LP16T_CON1_ENABLE_MSK BIT(LP16T_CON1_ENABLE_POS) - -/****************** Bit definition for LP16T_ARR register ************************/ - -#define LP16T_ARR_ARR_POSS 0U -#define LP16T_ARR_ARR_POSE 15U -#define LP16T_ARR_ARR_MSK BITS(LP16T_ARR_ARR_POSS,LP16T_ARR_ARR_POSE) - -/****************** Bit definition for LP16T_CNT register ************************/ - -#define LP16T_CNT_CNT_POSS 0U -#define LP16T_CNT_CNT_POSE 15U -#define LP16T_CNT_CNT_MSK BITS(LP16T_CNT_CNT_POSS,LP16T_CNT_CNT_POSE) - -/****************** Bit definition for LP16T_CMP register ************************/ - -#define LP16T_CMP_CMP_POSS 0U -#define LP16T_CMP_CMP_POSE 15U -#define LP16T_CMP_CMP_MSK BITS(LP16T_CMP_CMP_POSS,LP16T_CMP_CMP_POSE) - -/****************** Bit definition for LP16T_IER register ************************/ - -#define LP16T_IER_EXTTRIGIE_POS 2U -#define LP16T_IER_EXTTRIGIE_MSK BIT(LP16T_IER_EXTTRIGIE_POS) - -#define LP16T_IER_ARRMIE_POS 1U -#define LP16T_IER_ARRMIE_MSK BIT(LP16T_IER_ARRMIE_POS) - -#define LP16T_IER_CMPMIE_POS 0U -#define LP16T_IER_CMPMIE_MSK BIT(LP16T_IER_CMPMIE_POS) - -/****************** Bit definition for LP16T_ISR register ************************/ - -#define LP16T_ISR_EXTTRIG_POS 2U -#define LP16T_ISR_EXTTRIG_MSK BIT(LP16T_ISR_EXTTRIG_POS) - -#define LP16T_ISR_ARRM_POS 1U -#define LP16T_ISR_ARRM_MSK BIT(LP16T_ISR_ARRM_POS) - -#define LP16T_ISR_CMPM_POS 0U -#define LP16T_ISR_CMPM_MSK BIT(LP16T_ISR_CMPM_POS) - -/****************** Bit definition for LP16T_IFC register ************************/ - -#define LP16T_IFC_EXTTRIG_POS 2U -#define LP16T_IFC_EXTTRIG_MSK BIT(LP16T_IFC_EXTTRIG_POS) - -#define LP16T_IFC_ARRM_POS 1U -#define LP16T_IFC_ARRM_MSK BIT(LP16T_IFC_ARRM_POS) - -#define LP16T_IFC_CMPM_POS 0U -#define LP16T_IFC_CMPM_MSK BIT(LP16T_IFC_CMPM_POS) - -/****************** Bit definition for LP16T_UPDATE register ************************/ - -#define LP16T_UPDATE_UDIS_POS 0U -#define LP16T_UPDATE_UDIS_MSK BIT(LP16T_UPDATE_UDIS_POS) - -/****************** Bit definition for LP16T_SYNCSTAT register ************************/ - -#define LP16T_SYNCSTAT_CMPWBSY_POS 3U -#define LP16T_SYNCSTAT_CMPWBSY_MSK BIT(LP16T_SYNCSTAT_CMPWBSY_POS) - -#define LP16T_SYNCSTAT_ARRWBSY_POS 2U -#define LP16T_SYNCSTAT_ARRWBSY_MSK BIT(LP16T_SYNCSTAT_ARRWBSY_POS) - -#define LP16T_SYNCSTAT_CON1WBSY_POS 1U -#define LP16T_SYNCSTAT_CON1WBSY_MSK BIT(LP16T_SYNCSTAT_CON1WBSY_POS) - -typedef struct -{ - __IO uint32_t CON0; - __IO uint32_t CON1; - __IO uint32_t ARR; - __I uint32_t CNT; - __IO uint32_t CMP; - uint32_t RESERVED0 ; - __IO uint32_t IER; - __I uint32_t ISR; - __O uint32_t IFC; - uint32_t RESERVED1[3] ; - __IO uint32_t UPDATE; - __I uint32_t SYNCSTAT; -} LPTIM_TypeDef; - /****************** Bit definition for DBGC_IDCODE register ************************/ #define DBGC_IDCODE_REV_ID_POSS 16U @@ -6523,24 +5875,17 @@ typedef struct #define USART1_BASE (APB1_BASE + 0x5400) #define SPI0_BASE (APB1_BASE + 0x6000) #define SPI1_BASE (APB1_BASE + 0x6400) -#define SPI2_BASE (APB1_BASE + 0x6800) #define I2C0_BASE (APB1_BASE + 0x8000) #define I2C1_BASE (APB1_BASE + 0x8400) #define CAN0_BASE (APB1_BASE + 0xB000) #define DMA0_BASE (APB1_BASE + 0xC000) /* APB2 peripherals Base Address */ -#define LPTIM0_BASE (APB2_BASE + 0x0000) -#define LPUART0_BASE (APB2_BASE + 0x1000) #define ADC0_BASE (APB2_BASE + 0x2000) -#define ADC1_BASE (APB2_BASE + 0x2400) #define ACMP0_BASE (APB2_BASE + 0x3000) #define ACMP1_BASE (APB2_BASE + 0x3400) -#define OPAMP_BASE (APB2_BASE + 0x4000) -#define DAC0_BASE (APB2_BASE + 0x5000) #define WWDT_BASE (APB2_BASE + 0x6000) #define IWDT_BASE (APB2_BASE + 0x6400) -#define LCD_BASE (APB2_BASE + 0x7000) #define BKPC_BASE (APB2_BASE + 0x8000) #define RTC_BASE (APB2_BASE + 0x8400) #define TSENSE_BASE (APB2_BASE + 0x8800) @@ -6584,24 +5929,17 @@ typedef struct #define USART1 ((USART_TypeDef *)USART1_BASE) #define SPI0 ((SPI_TypeDef *)SPI0_BASE) #define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define SPI2 ((SPI_TypeDef *)SPI2_BASE) #define I2C0 ((I2C_TypeDef *)I2C0_BASE) #define I2C1 ((I2C_TypeDef *)I2C1_BASE) #define CAN0 ((CAN_TypeDef *)CAN0_BASE) #define DMA0 ((DMA_TypeDef *)DMA0_BASE) /* APB2 peripherals */ -#define LPTIM0 ((LPTIM_TypeDef *)LPTIM0_BASE) -#define LPUART0 ((LPUART_TypeDef *)LPUART0_BASE) #define ADC0 ((ADC_TypeDef *)ADC0_BASE) -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) #define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) #define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) -#define OPAMP ((OPAMP_TypeDef *)OPAMP_BASE) -#define DAC0 ((DAC_TypeDef *)DAC0_BASE) #define WWDT ((WWDT_TypeDef *)WWDT_BASE) #define IWDT ((IWDT_TypeDef *)IWDT_BASE) -#define LCD ((LCD_TypeDef *)LCD_BASE) #define BKPC ((BKPC_TypeDef *)BKPC_BASE) #define RTC ((RTC_TypeDef *)RTC_BASE) #define TSENSE ((TSENSE_TypeDef *)TSENSE_BASE) diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h index 452deaf516b8b6506cc0d1493de5f50411737b21..2bbe7437d0e4485ff9e26c63e18018eef8431a6c 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h @@ -18,7 +18,7 @@ #define __ALD_ACMP_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -38,187 +38,171 @@ extern "C" { /** * @brief Acmp interrupt */ -typedef enum -{ - ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */ - ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */ +typedef enum { + ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */ + ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */ } acmp_it_t; /** * @brief Acmp interrupt */ -typedef enum -{ - ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */ - ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */ +typedef enum { + ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */ + ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */ } acmp_flag_t; /** * @brief Acmp interrupt flag */ -typedef enum -{ - ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */ - ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */ +typedef enum { + ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */ + ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */ } acmp_status_t; /** * @brief Acmp positive input */ -typedef enum -{ - ACMP_POS_CH0 = 0, /**< Channel 0 as positive input */ - ACMP_POS_CH1 = 1, /**< Channel 1 as positive input */ - ACMP_POS_CH2 = 2, /**< Channel 2 as positive input */ - ACMP_POS_CH3 = 3, /**< Channel 3 as positive input */ - ACMP_POS_CH4 = 4, /**< Channel 4 as positive input */ - ACMP_POS_CH5 = 5, /**< Channel 5 as positive input */ - ACMP_POS_CH6 = 6, /**< Channel 6 as positive input */ - ACMP_POS_CH7 = 7, /**< Channel 7 as positive input */ +typedef enum { + ACMP_POS_CH0 = 0U, /**< Channel 0 as positive input */ + ACMP_POS_CH1 = 1U, /**< Channel 1 as positive input */ + ACMP_POS_CH2 = 2U, /**< Channel 2 as positive input */ + ACMP_POS_CH3 = 3U, /**< Channel 3 as positive input */ + ACMP_POS_CH4 = 4U, /**< Channel 4 as positive input */ + ACMP_POS_CH5 = 5U, /**< Channel 5 as positive input */ + ACMP_POS_CH6 = 6U, /**< Channel 6 as positive input */ + ACMP_POS_CH7 = 7U, /**< Channel 7 as positive input */ } acmp_pos_input_t; /** * @brief Acmp negative input */ -typedef enum -{ - ACMP_NEG_CH0 = 0, /**< Channel 0 as negative input */ - ACMP_NEG_CH1 = 1, /**< Channel 1 as negative input */ - ACMP_NEG_CH2 = 2, /**< Channel 2 as negative input */ - ACMP_NEG_CH3 = 3, /**< Channel 3 as negative input */ - ACMP_NEG_CH4 = 4, /**< Channel 4 as negative input */ - ACMP_NEG_CH5 = 5, /**< Channel 5 as negative input */ - ACMP_NEG_CH6 = 6, /**< Channel 6 as negative input */ - ACMP_NEG_CH7 = 7, /**< Channel 7 as negative input */ - ACMP_NEG_1V25 = 8, /**< 1.25v as negative input */ - ACMP_NEG_2V5 = 9, /**< 2.5v as negative input */ - ACMP_NEG_VDD = 10, /**< VDD as negative input */ +typedef enum { + ACMP_NEG_CH0 = 0U, /**< Channel 0 as negative input */ + ACMP_NEG_CH1 = 1U, /**< Channel 1 as negative input */ + ACMP_NEG_CH2 = 2U, /**< Channel 2 as negative input */ + ACMP_NEG_CH3 = 3U, /**< Channel 3 as negative input */ + ACMP_NEG_CH4 = 4U, /**< Channel 4 as negative input */ + ACMP_NEG_CH5 = 5U, /**< Channel 5 as negative input */ + ACMP_NEG_CH6 = 6U, /**< Channel 6 as negative input */ + ACMP_NEG_CH7 = 7U, /**< Channel 7 as negative input */ + ACMP_NEG_1V25 = 8U, /**< 1.25v as negative input */ + ACMP_NEG_2V5 = 9U, /**< 2.5v as negative input */ + ACMP_NEG_VDD = 10U, /**< VDD as negative input */ } acmp_neg_input_t; /** * @brief Acmp mode */ -typedef enum -{ - ACMP_ULTRA_LOW_POWER = 0, /**< Ultra low power mode */ - ACMP_LOW_POWER = 1, /**< Low power mode */ - ACMP_MIDDLE_POWER = 2, /**< Middle power mode */ - ACMP_HIGH_POWER = 3, /**< High power mode */ +typedef enum { + ACMP_ULTRA_LOW_POWER = 0U, /**< Ultra low power mode */ + ACMP_LOW_POWER = 1U, /**< Low power mode */ + ACMP_MIDDLE_POWER = 2U, /**< Middle power mode */ + ACMP_HIGH_POWER = 3U, /**< High power mode */ } acmp_mode_t; /** * @brief Acmp warm-up time */ -typedef enum -{ - ACMP_4_PCLK = 0, /**< 4 hfperclk cycles */ - ACMP_8_PCLK = 1, /**< 4 hfperclk cycles */ - ACMP_16_PCLK = 2, /**< 4 hfperclk cycles */ - ACMP_32_PCLK = 3, /**< 4 hfperclk cycles */ - ACMP_64_PCLK = 4, /**< 4 hfperclk cycles */ - ACMP_128_PCLK = 5, /**< 4 hfperclk cycles */ - ACMP_256_PCLK = 6, /**< 4 hfperclk cycles */ - ACMP_512_PCLK = 7, /**< 4 hfperclk cycles */ +typedef enum { + ACMP_4_PCLK = 0U, /**< 4 hfperclk cycles */ + ACMP_8_PCLK = 1U, /**< 4 hfperclk cycles */ + ACMP_16_PCLK = 2U, /**< 4 hfperclk cycles */ + ACMP_32_PCLK = 3U, /**< 4 hfperclk cycles */ + ACMP_64_PCLK = 4U, /**< 4 hfperclk cycles */ + ACMP_128_PCLK = 5U, /**< 4 hfperclk cycles */ + ACMP_256_PCLK = 6U, /**< 4 hfperclk cycles */ + ACMP_512_PCLK = 7U, /**< 4 hfperclk cycles */ } acmp_warm_time_t; /** * @brief Acmp hysteresis level */ -typedef enum -{ - ACMP_HYST_0 = 0, /**< No hysteresis */ - ACMP_HYST_15 = 1, /**< 15mV hysteresis */ - ACMP_HYST_22 = 2, /**< 22mV hysteresis */ - ACMP_HYST_29 = 3, /**< 29mV hysteresis */ - ACMP_HYST_36 = 4, /**< 36mV hysteresis */ - ACMP_HYST_43 = 5, /**< 43mV hysteresis */ - ACMP_HYST_50 = 6, /**< 50mV hysteresis */ - ACMP_HYST_57 = 7, /**< 57mV hysteresis */ +typedef enum { + ACMP_HYST_0 = 0U, /**< No hysteresis */ + ACMP_HYST_15 = 1U, /**< 15mV hysteresis */ + ACMP_HYST_22 = 2U, /**< 22mV hysteresis */ + ACMP_HYST_29 = 3U, /**< 29mV hysteresis */ + ACMP_HYST_36 = 4U, /**< 36mV hysteresis */ + ACMP_HYST_43 = 5U, /**< 43mV hysteresis */ + ACMP_HYST_50 = 6U, /**< 50mV hysteresis */ + ACMP_HYST_57 = 7U, /**< 57mV hysteresis */ } acmp_hystsel_t; /** * @brief Acmp inactive state */ -typedef enum -{ - ACMP_INACTVAL_LOW = 0, /**< The inactive value is 0 */ - ACMP_INACTVAL_HIGH = 1, /**< The inactive value is 1 */ +typedef enum { + ACMP_INACTVAL_LOW = 0U, /**< The inactive value is 0 */ + ACMP_INACTVAL_HIGH = 1U, /**< The inactive value is 1 */ } acmp_inactval_t; /** * @brief which edges set up interrupt */ -typedef enum -{ - ACMP_EDGE_NONE = 0, /**< Disable EDGE interrupt */ - ACMP_EDGE_FALL = 1, /**< Falling edges set EDGE interrupt */ - ACMP_EDGE_RISE = 2, /**< rise edges set EDGE interrupt */ - ACMP_EDGE_ALL = 3, /**< Falling edges and rise edges set EDGE interrupt */ +typedef enum { + ACMP_EDGE_NONE = 0U, /**< Disable EDGE interrupt */ + ACMP_EDGE_FALL = 1U, /**< Falling edges set EDGE interrupt */ + ACMP_EDGE_RISE = 2U, /**< rise edges set EDGE interrupt */ + ACMP_EDGE_ALL = 3U, /**< Falling edges and rise edges set EDGE interrupt */ } acmp_edge_t; /** * @brief Acmp output function */ -typedef enum -{ - ACMP_OUT_DISABLE = 0, /**< Disable acmp output */ - ACMP_OUT_ENABLE = 1, /**< Enable acmp output */ +typedef enum { + ACMP_OUT_DISABLE = 0U, /**< Disable acmp output */ + ACMP_OUT_ENABLE = 1U, /**< Enable acmp output */ } acmp_out_func_t; /** * @brief Acmp warm-up interrupt function */ -typedef enum -{ - ACMP_WARM_DISABLE = 0, /**< Disable acmp warm-up interrupt */ - ACMP_WARM_ENABLE = 1, /**< Enable acmp warm-up interrupt */ +typedef enum { + ACMP_WARM_DISABLE = 0U, /**< Disable acmp warm-up interrupt */ + ACMP_WARM_ENABLE = 1U, /**< Enable acmp warm-up interrupt */ } acmp_warm_it_func; /** * @brief Acmp gpio output invert */ -typedef enum -{ - ACMP_GPIO_NO_INV = 0, /**< Acmp output to gpio is not inverted */ - ACMP_GPIO_INV = 1, /**< Acmp output to gpio is inverted */ +typedef enum { + ACMP_GPIO_NO_INV = 0U, /**< Acmp output to gpio is not inverted */ + ACMP_GPIO_INV = 1U, /**< Acmp output to gpio is inverted */ } acmp_invert_t; /** * @brief Acmp output config structure definition */ -typedef struct -{ - acmp_out_func_t out_func; /**< Acmp output function */ - acmp_invert_t gpio_inv; /**< If invert gpio output */ +typedef struct { + acmp_out_func_t out_func; /**< Acmp output function */ + acmp_invert_t gpio_inv; /**< If invert gpio output */ } acmp_output_config_t; /** * @brief Acmp init structure definition */ -typedef struct -{ - acmp_mode_t mode; /**< Acmp operation mode */ - acmp_warm_time_t warm_time; /**< Acmp warm up time */ - acmp_hystsel_t hystsel; /**< Acmp hysteresis level */ - acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */ - acmp_pos_input_t pos_port; /**< Acmp positive port select */ - acmp_neg_input_t neg_port; /**< Acmp negative port select */ - acmp_inactval_t inactval; /**< Acmp inavtive output value */ - acmp_edge_t edge; /** Select edges to set interrupt flag */ - uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */ +typedef struct { + acmp_mode_t mode; /**< Acmp operation mode */ + acmp_warm_time_t warm_time; /**< Acmp warm up time */ + acmp_hystsel_t hystsel; /**< Acmp hysteresis level */ + acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */ + acmp_pos_input_t pos_port; /**< Acmp positive port select */ + acmp_neg_input_t neg_port; /**< Acmp negative port select */ + acmp_inactval_t inactval; /**< Acmp inavtive output value */ + acmp_edge_t edge; /** Select edges to set interrupt flag */ + uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */ } acmp_init_t; /** * @brief ACMP Handle Structure definition */ -typedef struct acmp_handle_s -{ - ACMP_TypeDef *perh; /**< Register base address */ - acmp_init_t init; /**< ACMP required parameters */ - lock_state_t lock; /**< Locking object */ +typedef struct acmp_handle_s { + ACMP_TypeDef *perh; /**< Register base address */ + acmp_init_t init; /**< ACMP required parameters */ + lock_state_t lock; /**< Locking object */ - void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */ - void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */ + void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */ + void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */ } acmp_handle_t; /** * @} @@ -237,64 +221,64 @@ typedef struct acmp_handle_s * @{ */ #define IS_ACMP_TYPE(x) (((x) == ACMP0) || \ - ((x) == ACMP1)) + ((x) == ACMP1)) #define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \ - ((x) == ACMP_LOW_POWER) || \ - ((x) == ACMP_MIDDLE_POWER) || \ - ((x) == ACMP_HIGH_POWER)) + ((x) == ACMP_LOW_POWER) || \ + ((x) == ACMP_MIDDLE_POWER) || \ + ((x) == ACMP_HIGH_POWER)) #define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \ - ((x) == ACMP_IT_WARMUP)) + ((x) == ACMP_IT_WARMUP)) #define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \ - ((x) == ACMP_FLAG_WARMUP)) + ((x) == ACMP_FLAG_WARMUP)) #define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_EDGE) || \ - ((x) == ACMP_STATUS_WARMUP)) + ((x) == ACMP_STATUS_WARMUP)) #define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \ - ((x) == ACMP_POS_CH1) || \ - ((x) == ACMP_POS_CH2) || \ - ((x) == ACMP_POS_CH3) || \ - ((x) == ACMP_POS_CH4) || \ - ((x) == ACMP_POS_CH5) || \ - ((x) == ACMP_POS_CH6) || \ - ((x) == ACMP_POS_CH7)) + ((x) == ACMP_POS_CH1) || \ + ((x) == ACMP_POS_CH2) || \ + ((x) == ACMP_POS_CH3) || \ + ((x) == ACMP_POS_CH4) || \ + ((x) == ACMP_POS_CH5) || \ + ((x) == ACMP_POS_CH6) || \ + ((x) == ACMP_POS_CH7)) #define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \ - ((x) == ACMP_NEG_CH1) || \ - ((x) == ACMP_NEG_CH2) || \ - ((x) == ACMP_NEG_CH3) || \ - ((x) == ACMP_NEG_CH4) || \ - ((x) == ACMP_NEG_CH5) || \ - ((x) == ACMP_NEG_CH6) || \ - ((x) == ACMP_NEG_CH7) || \ - ((x) == ACMP_NEG_1V25) || \ - ((x) == ACMP_NEG_2V5) || \ - ((x) == ACMP_NEG_VDD)) + ((x) == ACMP_NEG_CH1) || \ + ((x) == ACMP_NEG_CH2) || \ + ((x) == ACMP_NEG_CH3) || \ + ((x) == ACMP_NEG_CH4) || \ + ((x) == ACMP_NEG_CH5) || \ + ((x) == ACMP_NEG_CH6) || \ + ((x) == ACMP_NEG_CH7) || \ + ((x) == ACMP_NEG_1V25) || \ + ((x) == ACMP_NEG_2V5) || \ + ((x) == ACMP_NEG_VDD)) #define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \ - ((x) == ACMP_8_PCLK) || \ - ((x) == ACMP_16_PCLK) || \ - ((x) == ACMP_32_PCLK) || \ - ((x) == ACMP_64_PCLK) || \ - ((x) == ACMP_128_PCLK) || \ - ((x) == ACMP_256_PCLK) || \ - ((x) == ACMP_512_PCLK)) + ((x) == ACMP_8_PCLK) || \ + ((x) == ACMP_16_PCLK) || \ + ((x) == ACMP_32_PCLK) || \ + ((x) == ACMP_64_PCLK) || \ + ((x) == ACMP_128_PCLK) || \ + ((x) == ACMP_256_PCLK) || \ + ((x) == ACMP_512_PCLK)) #define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \ - ((x) == ACMP_HYST_15) || \ - ((x) == ACMP_HYST_22) || \ - ((x) == ACMP_HYST_29) || \ - ((x) == ACMP_HYST_36) || \ - ((x) == ACMP_HYST_43) || \ - ((x) == ACMP_HYST_50) || \ - ((x) == ACMP_HYST_57)) + ((x) == ACMP_HYST_15) || \ + ((x) == ACMP_HYST_22) || \ + ((x) == ACMP_HYST_29) || \ + ((x) == ACMP_HYST_36) || \ + ((x) == ACMP_HYST_43) || \ + ((x) == ACMP_HYST_50) || \ + ((x) == ACMP_HYST_57)) #define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \ - ((x) == ACMP_INACTVAL_HIGH)) + ((x) == ACMP_INACTVAL_HIGH)) #define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \ - ((x) == ACMP_EDGE_FALL) || \ - ((x) == ACMP_EDGE_RISE) || \ - ((x) == ACMP_EDGE_ALL)) + ((x) == ACMP_EDGE_FALL) || \ + ((x) == ACMP_EDGE_RISE) || \ + ((x) == ACMP_EDGE_ALL)) #define IS_ACMP_OUT_FUNC_TYPE(x) (((x) == ACMP_OUT_DISABLE) || \ - ((x) == ACMP_OUT_ENABLE)) + ((x) == ACMP_OUT_ENABLE)) #define IS_ACMP_INVERT_TYPE(x) (((x) == ACMP_GPIO_NO_INV) || \ - ((x) == ACMP_GPIO_INV)) + ((x) == ACMP_GPIO_INV)) #define IS_ACMP_WARM_FUNC_TYPE(x) (((x) == ACMP_WARM_DISABLE) || \ - ((x) == ACMP_WARM_ENABLE)) + ((x) == ACMP_WARM_ENABLE)) /** * @} */ @@ -348,8 +332,7 @@ uint8_t ald_acmp_out_result(acmp_handle_t *hperh); * @} */ #ifdef __cplusplus -extern "C" -} + extern "C" } #endif #endif diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h index d138f16c88d05e061735d8519e36772fec01a008..b5f9532f8db0dccc1b67a87aeac57eb2ee77ba63 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h @@ -17,7 +17,7 @@ #define __ALD_ADC_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -40,368 +40,342 @@ extern "C" { /** * @brief ADC State structures definition */ -typedef enum -{ - ADC_STATE_RESET = 0x0, /**< ADC not yet initialized or disabled */ - ADC_STATE_READY = 0x1, /**< ADC peripheral ready for use */ - ADC_STATE_BUSY_INTERNAL = 0x2, /**< ADC is busy to internal process */ - ADC_STATE_TIMEOUT = 0x4, /**< TimeOut occurrence */ - ADC_STATE_ERROR = 0x10, /**< Internal error occurrence */ - ADC_STATE_NM_BUSY = 0x100, /**< Conversion on group normal is ongoing or can occur */ - ADC_STATE_NM_EOC = 0x200, /**< Conversion data available on group normal */ - ADC_STATE_IST_BUSY = 0x1000, /**< Conversion on group insert is ongoing or can occur */ - ADC_STATE_IST_EOC = 0x2000, /**< Conversion data available on group insert */ - ADC_STATE_AWD = 0x10000, /**< Out-of-window occurrence of analog watchdog */ +typedef enum { + ADC_STATE_RESET = 0x0U, /**< ADC not yet initialized or disabled */ + ADC_STATE_READY = 0x1U, /**< ADC peripheral ready for use */ + ADC_STATE_BUSY = 0x2U, /**< ADC is busy to internal process */ + ADC_STATE_TIMEOUT = 0x4U, /**< TimeOut occurrence */ + ADC_STATE_ERROR = 0x8U, /**< Internal error occurrence */ + ADC_STATE_BUSY_N = 0x10U, /**< Normal channel busy */ + ADC_STATE_BUSY_I = 0x20U, /**< Insert channel busy */ + ADC_STATE_BUSY_WDG = 0x40U, /**< Insert channel busy */ } adc_state_t; /** *@brief ADC Error Code */ -typedef enum -{ - ADC_ERROR_NONE = 0x0, /**< No error */ - ADC_ERROR_INTERNAL = 0x1, /**< ADC IP internal error*/ - ADC_ERROR_OVR = 0x2, /**< Overrun error */ - ADC_ERROR_DMA = 0x4, /**< DMA transfer error */ +typedef enum { + ADC_ERROR_NONE = 0x0U, /**< No error */ + ADC_ERROR_INTERNAL = 0x1U, /**< ADC IP internal error*/ + ADC_ERROR_OVR = 0x2U, /**< Overrun error */ + ADC_ERROR_DMA = 0x4U, /**< DMA transfer error */ } adc_error_t; /** *@brief ADC data alignment */ -typedef enum -{ - ADC_DATAALIGN_RIGHT = 0x0, /**< ADC data alignment right */ - ADC_DATAALIGN_LEFT = 0x1, /**< ADC data alignment left */ +typedef enum { + ADC_DATAALIGN_RIGHT = 0x0U, /**< ADC data alignment right */ + ADC_DATAALIGN_LEFT = 0x1U, /**< ADC data alignment left */ } adc_align_t; /** *@brief ADC config hannal trigger the EOC IT mode */ -typedef enum -{ - ADC_NCHESEL_MODE_ALL = 0x0, /**< ADC set RCHE after convert sequence finish */ - ADC_NCHESEL_MODE_ONE = 0x1, /**< ADC set RCHE after one convert finish */ +typedef enum { + ADC_NCHESEL_MODE_ALL = 0x0U, /**< ADC set RCHE after convert sequence finish */ + ADC_NCHESEL_MODE_ONE = 0x1U, /**< ADC set RCHE after one convert finish */ } adc_nchesel_t; /** *@brief ADC channels */ -typedef enum -{ - ADC_CHANNEL_0 = 0x0, /**< ADC channel 0 */ - ADC_CHANNEL_1 = 0x1, /**< ADC channel 1 */ - ADC_CHANNEL_2 = 0x2, /**< ADC channel 2 */ - ADC_CHANNEL_3 = 0x3, /**< ADC channel 3 */ - ADC_CHANNEL_4 = 0x4, /**< ADC channel 4 */ - ADC_CHANNEL_5 = 0x5, /**< ADC channel 5 */ - ADC_CHANNEL_6 = 0x6, /**< ADC channel 6 */ - ADC_CHANNEL_7 = 0x7, /**< ADC channel 7 */ - ADC_CHANNEL_8 = 0x8, /**< ADC channel 8 */ - ADC_CHANNEL_9 = 0x9, /**< ADC channel 9 */ - ADC_CHANNEL_10 = 0xA, /**< ADC channel 10 */ - ADC_CHANNEL_11 = 0xB, /**< ADC channel 11 */ - ADC_CHANNEL_12 = 0xC, /**< ADC channel 12 */ - ADC_CHANNEL_13 = 0xD, /**< ADC channel 13 */ - ADC_CHANNEL_14 = 0xE, /**< ADC channel 14 */ - ADC_CHANNEL_15 = 0xF, /**< ADC channel 15 */ - ADC_CHANNEL_16 = 0x10, /**< ADC channel 16 */ - ADC_CHANNEL_17 = 0x11, /**< ADC channel 17 */ - ADC_CHANNEL_18 = 0x12, /**< ADC channel 18 */ - ADC_CHANNEL_19 = 0x13, /**< ADC channel 19 */ +typedef enum { + ADC_CHANNEL_0 = 0x0U, /**< ADC channel 0 */ + ADC_CHANNEL_1 = 0x1U, /**< ADC channel 1 */ + ADC_CHANNEL_2 = 0x2U, /**< ADC channel 2 */ + ADC_CHANNEL_3 = 0x3U, /**< ADC channel 3 */ + ADC_CHANNEL_4 = 0x4U, /**< ADC channel 4 */ + ADC_CHANNEL_5 = 0x5U, /**< ADC channel 5 */ + ADC_CHANNEL_6 = 0x6U, /**< ADC channel 6 */ + ADC_CHANNEL_7 = 0x7U, /**< ADC channel 7 */ + ADC_CHANNEL_8 = 0x8U, /**< ADC channel 8 */ + ADC_CHANNEL_9 = 0x9U, /**< ADC channel 9 */ + ADC_CHANNEL_10 = 0xAU, /**< ADC channel 10 */ + ADC_CHANNEL_11 = 0xBU, /**< ADC channel 11 */ + ADC_CHANNEL_12 = 0xCU, /**< ADC channel 12 */ + ADC_CHANNEL_13 = 0xDU, /**< ADC channel 13 */ + ADC_CHANNEL_14 = 0xEU, /**< ADC channel 14 */ + ADC_CHANNEL_15 = 0xFU, /**< ADC channel 15 */ + ADC_CHANNEL_16 = 0x10U, /**< ADC channel 16 */ + ADC_CHANNEL_17 = 0x11U, /**< ADC channel 17 */ + ADC_CHANNEL_18 = 0x12U, /**< ADC channel 18 */ + ADC_CHANNEL_19 = 0x13U, /**< ADC channel 19 */ } adc_channel_t; /** *@brief ADC sampling times */ -typedef enum -{ - ADC_SAMPLETIME_1 = 0x0, /**< ADC sampling times 1 clk */ - ADC_SAMPLETIME_2 = 0x1, /**< ADC sampling times 2 clk */ - ADC_SAMPLETIME_4 = 0x2, /**< ADC sampling times 4 clk */ - ADC_SAMPLETIME_15 = 0x3, /**< ADC sampling times 15 clk */ +typedef enum { + ADC_SAMPLETIME_1 = 0x0U, /**< ADC sampling times 1 clk */ + ADC_SAMPLETIME_2 = 0x1U, /**< ADC sampling times 2 clk */ + ADC_SAMPLETIME_4 = 0x2U, /**< ADC sampling times 4 clk */ + ADC_SAMPLETIME_15 = 0x3U, /**< ADC sampling times 15 clk */ } adc_samp_t; /** - *@brief ADC rank into normal group - */ -typedef enum -{ - ADC_NCH_RANK_1 = 0x1, /**< ADC normal channel rank 1 */ - ADC_NCH_RANK_2 = 0x2, /**< ADC normal channel rank 2 */ - ADC_NCH_RANK_3 = 0x3, /**< ADC normal channel rank 3 */ - ADC_NCH_RANK_4 = 0x4, /**< ADC normal channel rank 4 */ - ADC_NCH_RANK_5 = 0x5, /**< ADC normal channel rank 5 */ - ADC_NCH_RANK_6 = 0x6, /**< ADC normal channel rank 6 */ - ADC_NCH_RANK_7 = 0x7, /**< ADC normal channel rank 7 */ - ADC_NCH_RANK_8 = 0x8, /**< ADC normal channel rank 8 */ - ADC_NCH_RANK_9 = 0x9, /**< ADC normal channel rank 9 */ - ADC_NCH_RANK_10 = 0xA, /**< ADC normal channel rank 10 */ - ADC_NCH_RANK_11 = 0xB, /**< ADC normal channel rank 11 */ - ADC_NCH_RANK_12 = 0xC, /**< ADC normal channel rank 12 */ - ADC_NCH_RANK_13 = 0xD, /**< ADC normal channel rank 13 */ - ADC_NCH_RANK_14 = 0xE, /**< ADC normal channel rank 14 */ - ADC_NCH_RANK_15 = 0xF, /**< ADC normal channel rank 15 */ - ADC_NCH_RANK_16 = 0x10, /**< ADC normal channel rank 16 */ -} adc_nch_rank_t; - -/** - * @brief ADC rank into insert group - */ -typedef enum -{ - ADC_ICH_RANK_1 = 0x1, /**< ADC insert channel rank 1 */ - ADC_ICH_RANK_2 = 0x2, /**< ADC insert channel rank 2 */ - ADC_ICH_RANK_3 = 0x3, /**< ADC insert channel rank 3 */ - ADC_ICH_RANK_4 = 0x4, /**< ADC insert channel rank 4 */ -} adc_ich_rank_t; + *@brief ADC index channel in normal group + */ +typedef enum { + ADC_NCH_IDX_1 = 0x1U, /**< ADC normal channel index 1 */ + ADC_NCH_IDX_2 = 0x2U, /**< ADC normal channel index 2 */ + ADC_NCH_IDX_3 = 0x3U, /**< ADC normal channel index 3 */ + ADC_NCH_IDX_4 = 0x4U, /**< ADC normal channel index 4 */ + ADC_NCH_IDX_5 = 0x5U, /**< ADC normal channel index 5 */ + ADC_NCH_IDX_6 = 0x6U, /**< ADC normal channel index 6 */ + ADC_NCH_IDX_7 = 0x7U, /**< ADC normal channel index 7 */ + ADC_NCH_IDX_8 = 0x8U, /**< ADC normal channel index 8 */ + ADC_NCH_IDX_9 = 0x9U, /**< ADC normal channel index 9 */ + ADC_NCH_IDX_10 = 0xAU, /**< ADC normal channel index 10 */ + ADC_NCH_IDX_11 = 0xBU, /**< ADC normal channel index 11 */ + ADC_NCH_IDX_12 = 0xCU, /**< ADC normal channel index 12 */ + ADC_NCH_IDX_13 = 0xDU, /**< ADC normal channel index 13 */ + ADC_NCH_IDX_14 = 0xEU, /**< ADC normal channel index 14 */ + ADC_NCH_IDX_15 = 0xFU, /**< ADC normal channel index 15 */ + ADC_NCH_IDX_16 = 0x10U, /**< ADC normal channel index 16 */ +} adc_nch_idx_t; + +/** + * @brief ADC index channel in insert group + */ +typedef enum { + ADC_ICH_IDX_1 = 0x1U, /**< ADC insert channel index 1 */ + ADC_ICH_IDX_2 = 0x2U, /**< ADC insert channel index 2 */ + ADC_ICH_IDX_3 = 0x3U, /**< ADC insert channel index 3 */ + ADC_ICH_IDX_4 = 0x4U, /**< ADC insert channel index 4 */ +} adc_ich_idx_t; /** * @brief ADC analog watchdog mode */ -typedef enum -{ - ADC_ANAWTD_NONE = 0x0, /**< No watch dog */ - ADC_ANAWTD_SING_NM = 0x800200, /**< One normal channel watch dog */ - ADC_ANAWTD_SING_IST = 0x400200, /**< One inset channel Injec watch dog */ - ADC_ANAWTD_SING_NMIST = 0xC00200, /**< One normal and inset channel watch dog */ - ADC_ANAWTD_ALL_NM = 0x800000, /**< All normal channel watch dog */ - ADC_ANAWTD_ALL_IST = 0x400000, /**< All inset channel watch dog */ - ADC_ANAWTD_ALL_NMIST = 0xC00000, /**< All normal and inset channel watch dog */ -} adc_ana_wtd_t; +typedef enum { + ADC_ANAWTD_NONE = 0x0U, /**< No watch dog */ + ADC_ANAWTD_SING_NM = 0x800200U, /**< One normal channel watch dog */ + ADC_ANAWTD_SING_IST = 0x400200U, /**< One insert channel watch dog */ + ADC_ANAWTD_SING_NMIST = 0xC00200U, /**< One normal and insert channel watch dog */ + ADC_ANAWTD_ALL_NM = 0x800000U, /**< All normal channel watch dog */ + ADC_ANAWTD_ALL_IST = 0x400000U, /**< All insert channel watch dog */ + ADC_ANAWTD_ALL_NMIST = 0xC00000U, /**< All normal and insert channel watch dog */ +} adc_ana_wdg_t; /** * @brief ADC Event type */ -typedef enum -{ - ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ +typedef enum { + ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ } adc_event_type_t; /** * @brief ADC interrupts definition */ -typedef enum -{ - ADC_IT_NCH = (1U << 5), /**< ADC it normal */ - ADC_IT_AWD = (1U << 6), /**< ADC it awd */ - ADC_IT_ICH = (1U << 7), /**< ADC it insert */ - ADC_IT_OVR = (1U << 26), /**< ADC it overring */ +typedef enum { + ADC_IT_NCH = (1U << 5), /**< ADC it normal */ + ADC_IT_AWD = (1U << 6), /**< ADC it awd */ + ADC_IT_ICH = (1U << 7), /**< ADC it insert */ + ADC_IT_OVR = (1U << 26), /**< ADC it overring */ } adc_it_t; /** * @brief ADC flags definition */ -typedef enum -{ - ADC_FLAG_AWD = (1U << 0), /**perh->CON1, ADC_CON1_ADCEN_MSK)) -#define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) -#define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) -#define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) -#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) -#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) -#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_ENABLE(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) +#define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) +#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) +#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_SPEED_HIGH_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK)) +#define ADC_SPEED_HIGH_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK)) +#define ADC_CALIBRATE_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK)) +#define ADC_CALIBRATE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK)) /** * @} */ @@ -424,68 +402,65 @@ typedef struct /** @defgroup ADC_Private_Macros ADC Private Macros * @{ */ -#define IS_ADC_ICH_RANK_TYPE(x) ((x) <= ADC_ICH_RANK_4) -#define IS_ADC_NCH_RANK_TYPE(x) ((x) <= ADC_NCH_RANK_16) +#define IS_ADC_ICH_IDX_TYPE(x) ((x) <= ADC_ICH_IDX_4) +#define IS_ADC_NCH_IDX_TYPE(x) ((x) <= ADC_NCH_IDX_16) #define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ADC_SAMPLETIME_1) || \ - ((x) == ADC_SAMPLETIME_2) || \ - ((x) == ADC_SAMPLETIME_4) || \ - ((x) == ADC_SAMPLETIME_15)) + ((x) == ADC_SAMPLETIME_2) || \ + ((x) == ADC_SAMPLETIME_4) || \ + ((x) == ADC_SAMPLETIME_15)) #define IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_19) -#define IS_ADC_SCAN_MODE_TYPE(x) (((x) == DISABLE) || \ - ((x) == ENABLE)) #define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ADC_DATAALIGN_RIGHT) || \ - ((x) == ADC_DATAALIGN_LEFT)) + ((x) == ADC_DATAALIGN_LEFT)) #define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ADC_ANAWTD_NONE) || \ - ((x) == ADC_ANAWTD_SING_NM) || \ - ((x) == ADC_ANAWTD_SING_IST) || \ - ((x) == ADC_ANAWTD_SING_NMIST) || \ - ((x) == ADC_ANAWTD_ALL_NM) || \ - ((x) == ADC_ANAWTD_ALL_IST) || \ - ((x) == ADC_ANAWTD_ALL_NMIST)) + ((x) == ADC_ANAWTD_SING_NM) || \ + ((x) == ADC_ANAWTD_SING_IST) || \ + ((x) == ADC_ANAWTD_SING_NMIST) || \ + ((x) == ADC_ANAWTD_ALL_NM) || \ + ((x) == ADC_ANAWTD_ALL_IST) || \ + ((x) == ADC_ANAWTD_ALL_NMIST)) #define IS_ADC_IT_TYPE(x) (((x) == ADC_IT_NCH) || \ - ((x) == ADC_IT_AWD) || \ - ((x) == ADC_IT_ICH) || \ - ((x) == ADC_IT_OVR )) + ((x) == ADC_IT_AWD) || \ + ((x) == ADC_IT_ICH) || \ + ((x) == ADC_IT_OVR )) #define IS_ADC_FLAGS_TYPE(x) (((x) == ADC_FLAG_AWD) || \ - ((x) == ADC_FLAG_NCH) || \ - ((x) == ADC_FLAG_ICH) || \ - ((x) == ADC_FLAG_OVR) || \ - ((x) == ADC_FLAG_NCHS) || \ - ((x) == ADC_FLAG_ICHS)) + ((x) == ADC_FLAG_NCH) || \ + ((x) == ADC_FLAG_ICH) || \ + ((x) == ADC_FLAG_OVR) || \ + ((x) == ADC_FLAG_NCHS) || \ + ((x) == ADC_FLAG_ICHS)) #define IS_ADC_CLK_DIV_TYPE(x) (((x) == ADC_CKDIV_1) || \ - ((x) == ADC_CKDIV_2) || \ - ((x) == ADC_CKDIV_4) || \ - ((x) == ADC_CKDIV_8) || \ - ((x) == ADC_CKDIV_16) || \ - ((x) == ADC_CKDIV_32) || \ - ((x) == ADC_CKDIV_64) || \ - ((x) == ADC_CKDIV_128)) + ((x) == ADC_CKDIV_2) || \ + ((x) == ADC_CKDIV_4) || \ + ((x) == ADC_CKDIV_8) || \ + ((x) == ADC_CKDIV_16) || \ + ((x) == ADC_CKDIV_32) || \ + ((x) == ADC_CKDIV_64) || \ + ((x) == ADC_CKDIV_128)) #define IS_ADC_NEG_REF_VOLTAGE_TYPE(x) (((x) == ADC_NEG_REF_VSS ) || \ - ((x) == ADC_NEG_REF_VREFN )) + ((x) == ADC_NEG_REF_VREFN )) #define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ADC_POS_REF_VDD) || \ - ((x) == ADC_POS_REF_VREEFP) || \ - ((x) == ADC_POS_REF_VREEFP_BUF)) -#define IS_ADC_NCH_LEN_TYPE(x) ((x) <= ADC_NCH_LEN_16) -#define IS_ADC_NBR_OF_IST_TYPE(x) ((x) <= ADC_ICH_LEN_4) + ((x) == ADC_POS_REF_VREEFP) || \ + ((x) == ADC_POS_REF_VREEFP_BUF)) +#define IS_ADC_NCH_NR_TYPE(x) ((x) <= ADC_NCH_NR_16) +#define IS_ADC_ICH_NR_TYPE(x) ((x) <= ADC_ICH_NR_4) #define IS_ADC_DISC_MODE_TYPE(x) (((x) == ADC_ALL_DISABLE) || \ - ((x) == ADC_NCH_DISC_EN) || \ - ((x) == ADC_ICH_DISC_EN)) -#define IS_ADC_DISC_NBR_TYPE(x) ((x) <= ADC_DISC_NBR_8) -#define IS_ADC_CONV_RES_TYPE(x) (((x) == ADC_CONV_RES_12) || \ - ((x) == ADC_CONV_RES_6) || \ - ((x) == ADC_CONV_RES_8) || \ - ((x) == ADC_CONV_RES_10)) + ((x) == ADC_NCH_DISC_EN) || \ + ((x) == ADC_ICH_DISC_EN)) +#define IS_ADC_DISC_NR_TYPE(x) ((x) <= ADC_DISC_NR_8) +#define IS_ADC_CONV_BIT_TYPE(x) (((x) == ADC_CONV_BIT_12) || \ + ((x) == ADC_CONV_BIT_6) || \ + ((x) == ADC_CONV_BIT_8) || \ + ((x) == ADC_CONV_BIT_10)) #define IS_ADC_TRIG_MODE_TYPE(x) (((x) == ADC_TRIG_SOFT) || \ - ((x) == ADC_TRIG_PIS) || \ - ((x) == ADC_TRIG_PIS_SOFT)) -#define IS_ADC_TYPE(x) (((x) == ADC0) || \ - ((x) == ADC1)) + ((x) == ADC_TRIG_PIS) || \ + ((x) == ADC_TRIG_PIS_SOFT)) +#define IS_ADC_TYPE(x) (((x) == ADC0)) #define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ADC_NCHESEL_MODE_ALL) || \ - ((x) == ADC_NCHESEL_MODE_ONE)) + ((x) == ADC_NCHESEL_MODE_ONE)) #define IS_ADC_EVENT_TYPE(x) ((x) == ADC_AWD_EVENT) -#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff) -#define IS_HTR_TYPE(x) ((x) <= 0xfff) -#define IS_LTR_TYPE(x) ((x) <= 0xfff) +#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xFFF) +#define IS_HTR_TYPE(x) ((x) <= 0xFFF) +#define IS_LTR_TYPE(x) ((x) <= 0xFFF) /** * @} */ @@ -514,7 +489,7 @@ ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh); ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh); #ifdef ALD_DMA ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh); +ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel); ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config); #endif uint32_t ald_adc_normal_get_value(adc_handle_t *hperh); @@ -524,7 +499,7 @@ ald_status_t ald_adc_insert_stop(adc_handle_t *hperh); ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh); ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh); -uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank); +uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t ih_rank); void ald_adc_irq_handler(adc_handle_t *hperh); /** * @} @@ -565,8 +540,7 @@ uint32_t ald_adc_get_error(adc_handle_t *hperh); * @} */ #ifdef __cplusplus -extern "C" -} + extern "C" } #endif -#endif /* __ALD_ADC_H */ +#endif /* __ALD_ADC_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h index 7bac14c70ecbba4ed9a32cebfb28916215252f96..cbaa1c88f8dca5b61c368369d0f88c80dc99e7c4 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h @@ -35,44 +35,44 @@ extern "C" { /** @defgroup BKPC_Public_Macros BKPC Public Macros * @{ */ -#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0)) -#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55)) +#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0U)) +#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55U)) #define BKPC_LRC_ENABLE() \ - do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ - BKPC_LOCK(); \ - } while (0) +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) #define BKPC_LRC_DISABLE() \ - do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ - BKPC_LOCK(); \ - } while (0) +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) #define BKPC_LOSM_ENABLE() \ - do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \ - BKPC_LOCK(); \ - } while (0) +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \ + BKPC_LOCK(); \ +} while (0) #define BKPC_LOSM_DISABLE() \ - do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\ - BKPC_LOCK(); \ - } while (0) +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\ + BKPC_LOCK(); \ +} while (0) #define BKPC_LOSC_ENABLE() \ - do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \ - BKPC_LOCK(); \ - } while (0) +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) #define BKPC_LOSC_DISABLE() \ - do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\ - BKPC_LOCK(); \ - } while (0) +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\ + BKPC_LOCK(); \ +} while (0) /** * @} */ @@ -83,37 +83,31 @@ extern "C" { /** * @brief BKPC ldo output select */ -typedef enum -{ - BKPC_LDO_OUTPUT_1_6 = 0x0, /**< 1.6V */ - BKPC_LDO_OUTPUT_1_3 = 0x1, /**< 1.3V */ - BKPC_LDO_OUTPUT_1_4 = 0x2, /**< 1.4V */ - BKPC_LDO_OUTPUT_1_5 = 0x4, /**< 1.5V */ +typedef enum { + BKPC_LDO_OUTPUT_1_6 = 0x0U, /**< 1.6V */ + BKPC_LDO_OUTPUT_1_3 = 0x1U, /**< 1.3V */ + BKPC_LDO_OUTPUT_1_4 = 0x2U, /**< 1.4V */ + BKPC_LDO_OUTPUT_1_5 = 0x4U, /**< 1.5V */ } bkpc_ldo_output_t; /** - * @brief BKPC BOR voltage select - */ -typedef enum -{ - BKPC_BOR_VOL_1_7 = 0x0, /**< 1.7V */ - BKPC_BOR_VOL_2_0 = 0x1, /**< 2.0V */ - BKPC_BOR_VOL_2_1 = 0x2, /**< 2.1V */ - BKPC_BOR_VOL_2_2 = 0x3, /**< 2.2V */ - BKPC_BOR_VOL_2_3 = 0x4, /**< 2.3V */ - BKPC_BOR_VOL_2_4 = 0x5, /**< 2.4V */ - BKPC_BOR_VOL_2_5 = 0x6, /**< 2.5V */ - BKPC_BOR_VOL_2_6 = 0x7, /**< 2.6V */ - BKPC_BOR_VOL_2_8 = 0x8, /**< 2.8V */ - BKPC_BOR_VOL_3_0 = 0x9, /**< 3.0V */ - BKPC_BOR_VOL_3_1 = 0xA, /**< 3.1V */ - BKPC_BOR_VOL_3_3 = 0xB, /**< 3.3V */ - BKPC_BOR_VOL_3_6 = 0xC, /**< 3.6V */ - BKPC_BOR_VOL_3_7 = 0xD, /**< 3.7V */ - BKPC_BOR_VOL_4_0 = 0xE, /**< 4.0V */ - BKPC_BOR_VOL_4_3 = 0xF, /**< 4.3V */ -} bkpc_bor_vol_t; + * @brief Standby wakeup port select + */ +typedef enum { + PMU_STANDBY_PORT_SEL_PA0 = 0x0U, /**< Wakeup by PA0 */ + PMU_STANDBY_PORT_SEL_PA1 = 0x1U, /**< Wakeup by PA1 */ + PMU_STANDBY_PORT_SEL_PA2 = 0x2U, /**< Wakeup by PA2 */ + PMU_STANDBY_PORT_SEL_PA3 = 0x3U, /**< Wakeup by PA3 */ + PMU_STANDBY_PORT_SEL_NONE = 0xFU, /**< Wakeup by other source */ +} bkpc_wakeup_port_t; +/** + * @brief Standby wakeup level + */ +typedef enum { + PMU_STANDBY_LEVEL_HIGH = 0x0U, /**< High level */ + PMU_STANDBY_LEVEL_LOW = 0x1U, /**< Low level */ +} bkpc_wakeup_level_t; /** * @} */ @@ -126,22 +120,13 @@ typedef enum ((x) == BKPC_LDO_OUTPUT_1_3) || \ ((x) == BKPC_LDO_OUTPUT_1_4) || \ ((x) == BKPC_LDO_OUTPUT_1_5)) -#define IS_BKPC_BOR_VOL(x) (((x) == BKPC_BOR_VOL_1_7) || \ - ((x) == BKPC_BOR_VOL_2_0) || \ - ((x) == BKPC_BOR_VOL_2_1) || \ - ((x) == BKPC_BOR_VOL_2_2) || \ - ((x) == BKPC_BOR_VOL_2_3) || \ - ((x) == BKPC_BOR_VOL_2_4) || \ - ((x) == BKPC_BOR_VOL_2_5) || \ - ((x) == BKPC_BOR_VOL_2_6) || \ - ((x) == BKPC_BOR_VOL_2_8) || \ - ((x) == BKPC_BOR_VOL_3_0) || \ - ((x) == BKPC_BOR_VOL_3_1) || \ - ((x) == BKPC_BOR_VOL_3_3) || \ - ((x) == BKPC_BOR_VOL_3_6) || \ - ((x) == BKPC_BOR_VOL_3_7) || \ - ((x) == BKPC_BOR_VOL_4_0) || \ - ((x) == BKPC_BOR_VOL_4_3)) +#define IS_BKPC_WAKEUP_PORT(x) (((x) == PMU_STANDBY_PORT_SEL_PA0) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA1) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA2) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA3) || \ + ((x) == PMU_STANDBY_PORT_SEL_NONE)) +#define IS_BKPC_WAKEUP_LEVEL(x) (((x) == PMU_STANDBY_LEVEL_HIGH) || \ + ((x) == PMU_STANDBY_LEVEL_LOW)) #define IS_BKPC_RAM_IDX(x) ((x) < 32) /** * @} @@ -154,8 +139,8 @@ typedef enum * @{ */ /* control functions */ +extern void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level); extern void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state); -extern void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state); /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h index 471c20e6acd2067da9b0fe9159c6fb904a8f6690..196094eaaa2f26a761d5c5fc4edd50ff04240070 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h @@ -4,7 +4,7 @@ * @brief Header file of CAN Module driver. * * @version V1.0 - * @date 16 Apr 2017 + * @date 16 Apr 2019 * @author AE Team * @note * @@ -36,288 +36,272 @@ extern "C" { /** * @brief ALD State structures definition */ -typedef enum -{ - CAN_STATE_RESET = 0x00, /**< CAN not yet initialized or disabled */ - CAN_STATE_READY = 0x01, /**< CAN initialized and ready for use */ - CAN_STATE_BUSY = 0x02, /**< CAN process is ongoing */ - CAN_STATE_BUSY_TX = 0x11, /**< CAN process is ongoing */ - CAN_STATE_BUSY_RX = 0x21, /**< CAN process is ongoing */ - CAN_STATE_BUSY_TX_RX = 0x31, /**< CAN process is ongoing */ - CAN_STATE_TIMEOUT = 0x03, /**< CAN in Timeout state */ - CAN_STATE_ERROR = 0x04, /**< CAN error state */ +typedef enum { + CAN_STATE_RESET = 0x00U, /**< CAN not yet initialized or disabled */ + CAN_STATE_READY = 0x01U, /**< CAN initialized and ready for use */ + CAN_STATE_BUSY = 0x02U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX = 0x11U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_RX0 = 0x21U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_RX1 = 0x41U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX_RX0 = 0x31U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX_RX1 = 0x51U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_RX0_RX1 = 0x61U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX_RX0_RX1 = 0x71U, /**< CAN process is ongoing */ + CAN_STATE_TIMEOUT = 0x04U, /**< CAN in Timeout state */ + CAN_STATE_ERROR = 0x08U, /**< CAN error state */ } can_state_t; /** * @brief CAN Error Code */ -typedef enum -{ - CAN_ERROR_NONE = 0x00, /**< No error */ - CAN_ERROR_EWG = 0x01, /**< EWG error */ - CAN_ERROR_EPV = 0x02, /**< EPV error */ - CAN_ERROR_BOF = 0x04, /**< BOF error */ - CAN_ERROR_STF = 0x08, /**< Stuff error */ - CAN_ERROR_FOR = 0x10, /**< Form error */ - CAN_ERROR_ACK = 0x20, /**< Acknowledgment error */ - CAN_ERROR_BR = 0x40, /**< Bit recessive */ - CAN_ERROR_BD = 0x80, /**< LEC dominant */ - CAN_ERROR_CRC = 0x100, /**< LEC transfer error */ - CAN_ERROR_UNK = 0x200, /**< Unknown error */ +typedef enum { + CAN_ERROR_NONE = 0x00U, /**< No error */ + CAN_ERROR_EWG = 0x01U, /**< EWG error */ + CAN_ERROR_EPV = 0x02U, /**< EPV error */ + CAN_ERROR_BOF = 0x04U, /**< BOF error */ + CAN_ERROR_STF = 0x08U, /**< Stuff error */ + CAN_ERROR_FOR = 0x10U, /**< Form error */ + CAN_ERROR_ACK = 0x20U, /**< Acknowledgment error */ + CAN_ERROR_BR = 0x40U, /**< Bit recessive */ + CAN_ERROR_BD = 0x80U, /**< LEC dominant */ + CAN_ERROR_CRC = 0x100U, /**< LEC transfer error */ + CAN_ERROR_UNK = 0x200U, /**< Unknown error */ } can_error_t; /** * @brief CAN Operating Mode */ -typedef enum -{ - CAN_MODE_NORMAL = 0x00, /**< Normal mode */ - CAN_MODE_LOOPBACK = 0x01, /**< Loopback mode */ - CAN_MODE_SILENT = 0x02, /**< Silent mode */ - CAN_MODE_SILENT_LOOPBACK = 0x03, /**< Loopback combined with silent mode */ + typedef enum { + CAN_MODE_NORMAL = 0x00U, /**< Normal mode */ + CAN_MODE_LOOPBACK = 0x01U, /**< Loopback mode */ + CAN_MODE_SILENT = 0x02U, /**< Silent mode */ + CAN_MODE_SILENT_LOOPBACK = 0x03U, /**< Loopback combined with silent mode */ } can_operate_mode_t; /** * @brief CAN Synchronization Jump Width */ -typedef enum -{ - CAN_SJW_1 = 0x0, /**< 1 time quantum */ - CAN_SJW_2 = 0x1, /**< 2 time quantum */ - CAN_SJW_3 = 0x2, /**< 3 time quantum */ - CAN_SJW_4 = 0x3, /**< 4 time quantum */ +typedef enum { + CAN_SJW_1 = 0x0U, /**< 1 time quantum */ + CAN_SJW_2 = 0x1U, /**< 2 time quantum */ + CAN_SJW_3 = 0x2U, /**< 3 time quantum */ + CAN_SJW_4 = 0x3U, /**< 4 time quantum */ } can_sjw_t; /** * @brief CAN Time Quantum in Bit Segment 1 */ -typedef enum -{ - CAN_SEG1_1 = 0x0, /**< 1 time quantum */ - CAN_SEG1_2 = 0x1, /**< 2 time quantum */ - CAN_SEG1_3 = 0x2, /**< 3 time quantum */ - CAN_SEG1_4 = 0x3, /**< 4 time quantum */ - CAN_SEG1_5 = 0x4, /**< 5 time quantum */ - CAN_SEG1_6 = 0x5, /**< 6 time quantum */ - CAN_SEG1_7 = 0x6, /**< 7 time quantum */ - CAN_SEG1_8 = 0x7, /**< 8 time quantum */ - CAN_SEG1_9 = 0x8, /**< 9 time quantum */ - CAN_SEG1_10 = 0x9, /**< 10 time quantum */ - CAN_SEG1_11 = 0xA, /**< 11 time quantum */ - CAN_SEG1_12 = 0xB, /**< 12 time quantum */ - CAN_SEG1_13 = 0xC, /**< 13 time quantum */ - CAN_SEG1_14 = 0xD, /**< 14 time quantum */ - CAN_SEG1_15 = 0xE, /**< 15 time quantum */ - CAN_SEG1_16 = 0xF, /**< 16 time quantum */ +typedef enum { + CAN_SEG1_1 = 0x0U, /**< 1 time quantum */ + CAN_SEG1_2 = 0x1U, /**< 2 time quantum */ + CAN_SEG1_3 = 0x2U, /**< 3 time quantum */ + CAN_SEG1_4 = 0x3U, /**< 4 time quantum */ + CAN_SEG1_5 = 0x4U, /**< 5 time quantum */ + CAN_SEG1_6 = 0x5U, /**< 6 time quantum */ + CAN_SEG1_7 = 0x6U, /**< 7 time quantum */ + CAN_SEG1_8 = 0x7U, /**< 8 time quantum */ + CAN_SEG1_9 = 0x8U, /**< 9 time quantum */ + CAN_SEG1_10 = 0x9U, /**< 10 time quantum */ + CAN_SEG1_11 = 0xAU, /**< 11 time quantum */ + CAN_SEG1_12 = 0xBU, /**< 12 time quantum */ + CAN_SEG1_13 = 0xCU, /**< 13 time quantum */ + CAN_SEG1_14 = 0xDU, /**< 14 time quantum */ + CAN_SEG1_15 = 0xEU, /**< 15 time quantum */ + CAN_SEG1_16 = 0xFU, /**< 16 time quantum */ } can_seg1_t; /** * @brief CAN Time Quantum in Bit Segment 2 */ -typedef enum -{ - CAN_SEG2_1 = 0x0, /**< 1 time quantum */ - CAN_SEG2_2 = 0x1, /**< 2 time quantum */ - CAN_SEG2_3 = 0x2, /**< 3 time quantum */ - CAN_SEG2_4 = 0x3, /**< 4 time quantum */ - CAN_SEG2_5 = 0x4, /**< 5 time quantum */ - CAN_SEG2_6 = 0x5, /**< 6 time quantum */ - CAN_SEG2_7 = 0x6, /**< 7 time quantum */ - CAN_SEG2_8 = 0x7, /**< 8 time quantum */ +typedef enum { + CAN_SEG2_1 = 0x0U, /**< 1 time quantum */ + CAN_SEG2_2 = 0x1U, /**< 2 time quantum */ + CAN_SEG2_3 = 0x2U, /**< 3 time quantum */ + CAN_SEG2_4 = 0x3U, /**< 4 time quantum */ + CAN_SEG2_5 = 0x4U, /**< 5 time quantum */ + CAN_SEG2_6 = 0x5U, /**< 6 time quantum */ + CAN_SEG2_7 = 0x6U, /**< 7 time quantum */ + CAN_SEG2_8 = 0x7U, /**< 8 time quantum */ } can_seg2_t; /** * @brief CAN Filter Mode */ -typedef enum -{ - CAN_FILTER_MODE_MASK = 0x0, /**< Identifier mask mode */ - CAN_FILTER_MODE_LIST = 0x1, /**< Identifier list mode */ +typedef enum { + CAN_FILTER_MODE_MASK = 0x0U, /**< Identifier mask mode */ + CAN_FILTER_MODE_LIST = 0x1U, /**< Identifier list mode */ } can_filter_mode_t; /** * @brief CAN Filter Scale */ -typedef enum -{ - CAN_FILTER_SCALE_16 = 0x0, /**< Two 16-bit filters */ - CAN_FILTER_SCALE_32 = 0x1, /**< One 32-bit filter */ +typedef enum { + CAN_FILTER_SCALE_16 = 0x0U, /**< Two 16-bit filters */ + CAN_FILTER_SCALE_32 = 0x1U, /**< One 32-bit filter */ } can_filter_scale_t; /** * @brief CAN Filter fifo */ -typedef enum -{ - CAN_FILTER_FIFO0 = 0x0, /**< FIFO 0 assignment for filter */ - CAN_FILTER_FIFO1 = 0x1, /**< FIFO 1 assignment for filter */ +typedef enum { + CAN_FILTER_FIFO0 = 0x0U, /**< FIFO 0 assignment for filter */ + CAN_FILTER_FIFO1 = 0x1U, /**< FIFO 1 assignment for filter */ } can_filter_fifo_t; /** * @brief CAN Identifier Type */ -typedef enum -{ - CAN_ID_STD = 0x0, /**< Standard Id */ - CAN_ID_EXT = 0x1, /**< Extended Id */ +typedef enum { + CAN_ID_STD = 0x0U, /**< Standard Id */ + CAN_ID_EXT = 0x1U, /**< Extended Id */ } can_id_type_t; /** * @brief CAN Remote Transmission Request */ -typedef enum -{ - CAN_RTR_DATA = 0x0, /**< Data frame */ - CAN_RTR_REMOTE = 0x1, /**< Remote frame */ +typedef enum { + CAN_RTR_DATA = 0x0U, /**< Data frame */ + CAN_RTR_REMOTE = 0x1U, /**< Remote frame */ } can_remote_req_t; /** * @brief CAN Transmit Constants */ -typedef enum -{ - CAN_TX_MAILBOX_0 = 0x0, /**< TX mailbox index 0 */ - CAN_TX_MAILBOX_1 = 0x1, /**< TX mailbox index 1 */ - CAN_TX_MAILBOX_2 = 0x2, /**< TX mailbox index 2 */ - CAN_TX_MAILBOX_NONE = 0x3, /**< MailBox can't be used */ +typedef enum { + CAN_TX_MAILBOX_0 = 0x0U, /**< TX mailbox index 0 */ + CAN_TX_MAILBOX_1 = 0x1U, /**< TX mailbox index 1 */ + CAN_TX_MAILBOX_2 = 0x2U, /**< TX mailbox index 2 */ + CAN_TX_MAILBOX_NONE = 0x3U, /**< MailBox can't be used */ } can_tx_mailbox_t; /** * @brief CAN Receive fifo Number */ -typedef enum -{ - CAN_RX_FIFO0 = 0x0, /**< CAN fifo 0 used to receive */ - CAN_RX_FIFO1 = 0x1, /**< CAN fifo 1 used to receive */ +typedef enum { + CAN_RX_FIFO0 = 0x0U, /**< CAN fifo 0 used to receive */ + CAN_RX_FIFO1 = 0x1U, /**< CAN fifo 1 used to receive */ } can_rx_fifo_t; /** * @brief CAN Flags */ -typedef enum -{ - CAN_FLAG_SLPS = (1U << 1), /**< Sleep acknowledge flag */ - CAN_FLAG_ERR = (1U << 2), /**< Error flag*/ - CAN_FLAG_WK = (1U << 3), /**< Wake up flag */ - CAN_FLAG_SLP = (1U << 4), /**< Sleep acknowledge flag */ - CAN_FLAG_M0REQC = (1U << 20) | (1U << 0), /**< Request MailBox0 flag */ - CAN_FLAG_M0TXC = (1U << 20) | (1U << 1), /**< Transmission OK MailBox0 flag */ - CAN_FLAG_M1REQC = (1U << 20) | (1U << 8), /**< Request MailBox1 flag */ - CAN_FLAG_M1TXC = (1U << 20) | (1U << 9), /**< Transmission OK MailBox1 flag */ - CAN_FLAG_M2REQC = (1U << 20) | (1U << 16), /**< Request MailBox2 flag */ - CAN_FLAG_M2TXC = (1U << 20) | (1U << 17), /**< Transmission OK MailBox2 flag */ - CAN_FLAG_TXM0 = (1U << 20) | (1U << 26), /**< Transmit mailbox 0 empty flag */ - CAN_FLAG_TXM1 = (1U << 20) | (1U << 27), /**< Transmit mailbox 1 empty flag */ - CAN_FLAG_TXM2 = (1U << 20) | (1U << 28), /**< Transmit mailbox 2 empty flag */ - CAN_FLAG_FF0 = (2U << 20) | (1U << 3), /**< FIFO 0 Full flag */ - CAN_FLAG_FOV0 = (2U << 20) | (1U << 4), /**< FIFO 0 Overrun flag */ - CAN_FLAG_FF1 = (3U << 20) | (1U << 3), /**< FIFO 1 Full flag */ - CAN_FLAG_FOV1 = (3U << 20) | (1U << 4), /**< FIFO 1 Overrun flag */ - CAN_FLAG_WARN = (4U << 20) | (1U << 0), /**< Error warning flag */ - CAN_FLAG_PERR = (4U << 20) | (1U << 1), /**< Error passive flag */ - CAN_FLAG_BOF = (4U << 20) | (1U << 2), /**< Bus-Off flag */ +typedef enum { + CAN_FLAG_SLPS = (1U << 1), /**< Sleep acknowledge flag */ + CAN_FLAG_ERR = (1U << 2), /**< Error flag*/ + CAN_FLAG_WK = (1U << 3), /**< Wake up flag */ + CAN_FLAG_SLP = (1U << 4), /**< Sleep acknowledge flag */ + CAN_FLAG_M0REQC = (1U << 20) | (1U << 0), /**< Request MailBox0 flag */ + CAN_FLAG_M0TXC = (1U << 20) | (1U << 1), /**< Transmission OK MailBox0 flag */ + CAN_FLAG_M1REQC = (1U << 20) | (1U << 8), /**< Request MailBox1 flag */ + CAN_FLAG_M1TXC = (1U << 20) | (1U << 9), /**< Transmission OK MailBox1 flag */ + CAN_FLAG_M2REQC = (1U << 20) | (1U << 16), /**< Request MailBox2 flag */ + CAN_FLAG_M2TXC = (1U << 20) | (1U << 17), /**< Transmission OK MailBox2 flag */ + CAN_FLAG_TXM0 = (1U << 20) | (1U << 26), /**< Transmit mailbox 0 empty flag */ + CAN_FLAG_TXM1 = (1U << 20) | (1U << 27), /**< Transmit mailbox 1 empty flag */ + CAN_FLAG_TXM2 = (1U << 20) | (1U << 28), /**< Transmit mailbox 2 empty flag */ + CAN_FLAG_FF0 = (2U << 20) | (1U << 3), /**< FIFO 0 Full flag */ + CAN_FLAG_FOV0 = (2U << 20) | (1U << 4), /**< FIFO 0 Overrun flag */ + CAN_FLAG_FF1 = (3U << 20) | (1U << 3), /**< FIFO 1 Full flag */ + CAN_FLAG_FOV1 = (3U << 20) | (1U << 4), /**< FIFO 1 Overrun flag */ + CAN_FLAG_WARN = (4U << 20) | (1U << 0), /**< Error warning flag */ + CAN_FLAG_PERR = (4U << 20) | (1U << 1), /**< Error passive flag */ + CAN_FLAG_BOF = (4U << 20) | (1U << 2), /**< Bus-Off flag */ } can_flag_t; /** * @brief CAN Interrupts */ -typedef enum -{ - CAN_IT_TXM = (1U << 0), /**< Transmit mailbox empty interrupt bit */ - CAN_IT_FP0 = (1U << 1), /**< FIFO0 message pending interrupt bit */ - CAN_IT_FF0 = (1U << 2), /**< FIFO0 full interrupt bit */ - CAN_IT_FOV0 = (1U << 3), /**< FIFO0 overrun interrupt bit */ - CAN_IT_FP1 = (1U << 4), /**< FIFO1 message pending interrupt bit */ - CAN_IT_FF1 = (1U << 5), /**< FIFO1 full interrupt bit */ - CAN_IT_FOV1 = (1U << 6), /**< FIFO1 overrun interrupt bit */ - CAN_IT_WARN = (1U << 8), /**< Error warning interrupt bit */ - CAN_IT_PERR = (1U << 9), /**< Error passive interrupt bit */ - CAN_IT_BOF = (1U << 10), /**< Bus-off interrupt bit */ - CAN_IT_PRERR = (1U << 11), /**< Last error code interrupt bit */ - CAN_IT_ERR = (1U << 15), /**< Error interrupt bit */ - CAN_IT_WK = (1U << 16), /**< wake-up interrupt bit */ - CAN_IT_SLP = (1U << 17), /**< sleep interrupt bit */ +typedef enum { + CAN_IT_TXM = (1U << 0), /**< Transmit mailbox empty interrupt bit */ + CAN_IT_FP0 = (1U << 1), /**< FIFO0 message pending interrupt bit */ + CAN_IT_FF0 = (1U << 2), /**< FIFO0 full interrupt bit */ + CAN_IT_FOV0 = (1U << 3), /**< FIFO0 overrun interrupt bit */ + CAN_IT_FP1 = (1U << 4), /**< FIFO1 message pending interrupt bit */ + CAN_IT_FF1 = (1U << 5), /**< FIFO1 full interrupt bit */ + CAN_IT_FOV1 = (1U << 6), /**< FIFO1 overrun interrupt bit */ + CAN_IT_WARN = (1U << 8), /**< Error warning interrupt bit */ + CAN_IT_PERR = (1U << 9), /**< Error passive interrupt bit */ + CAN_IT_BOF = (1U << 10), /**< Bus-off interrupt bit */ + CAN_IT_PRERR = (1U << 11), /**< Last error code interrupt bit */ + CAN_IT_ERR = (1U << 15), /**< Error interrupt bit */ + CAN_IT_WK = (1U << 16), /**< wake-up interrupt bit */ + CAN_IT_SLP = (1U << 17), /**< sleep interrupt bit */ } can_it_t; /** * @brief CAN filter configuration structure definition */ -typedef struct -{ - uint32_t id_high; /**< Specifies the filter identification number */ - uint32_t id_low; /**< Specifies the filter identification number */ - uint32_t mask_id_high; /**< Specifies the filter mask number or identification number */ - uint32_t mask_id_low; /**< Specifies the filter mask number or identification number */ - can_filter_fifo_t fifo; /**< Specifies the fifo (0 or 1) which will be assigned to the filter. */ - uint32_t number; /**< Specifies the filter which will be initialized. */ - can_filter_mode_t mode; /**< Specifies the filter mode to be initialized. */ - can_filter_scale_t scale; /**< Specifies the filter scale. */ - type_func_t active; /**< Enable or disable the filter. */ - uint32_t bank_number; /**< Select the start slave bank filter. */ +typedef struct { + uint32_t id_high; /**< Specifies the filter identification number */ + uint32_t id_low; /**< Specifies the filter identification number */ + uint32_t mask_id_high; /**< Specifies the filter mask number or identification number */ + uint32_t mask_id_low; /**< Specifies the filter mask number or identification number */ + can_filter_fifo_t fifo; /**< Specifies the fifo (0 or 1) which will be assigned to the filter. */ + uint32_t number; /**< Specifies the filter which will be initialized. */ + can_filter_mode_t mode; /**< Specifies the filter mode to be initialized. */ + can_filter_scale_t scale; /**< Specifies the filter scale. */ + type_func_t active; /**< Enable or disable the filter. */ } can_filter_t; /** * @brief CAN init structure definition */ -typedef struct -{ - uint32_t psc; /**< Specifies the length of a time quantum. */ - can_operate_mode_t mode; /**< Specifies the CAN operating mode. */ - can_sjw_t sjw; /**< Specifies the maximum number of time quanta the CAN hardware is +typedef struct { + uint32_t psc; /**< Specifies the length of a time quantum. */ + can_operate_mode_t mode; /**< Specifies the CAN operating mode. */ + can_sjw_t sjw; /**< Specifies the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. */ - can_seg1_t seg1; /**< Specifies the number of time quanta in Bit Segment 1. */ - can_seg2_t seg2; /**< Specifies the number of time quanta in Bit Segment 2. */ - type_func_t ttcm; /**< Enable or disable the time triggered communication mode. */ - type_func_t abom; /**< Enable or disable the automatic bus-off management. */ - type_func_t awk; /**< Enable or disable the automatic wake-up mode. */ - type_func_t artx; /**< Enable or disable the non-automatic retransmission mode. */ - type_func_t rfom; /**< Enable or disable the Receive fifo Locked mode. */ - type_func_t txmp; /**< Enable or disable the transmit fifo priority. */ + can_seg1_t seg1; /**< Specifies the number of time quanta in Bit Segment 1. */ + can_seg2_t seg2; /**< Specifies the number of time quanta in Bit Segment 2. */ + type_func_t ttcm; /**< Enable or disable the time triggered communication mode. */ + type_func_t abom; /**< Enable or disable the automatic bus-off management. */ + type_func_t awk; /**< Enable or disable the automatic wake-up mode. */ + type_func_t artx; /**< Enable or disable the non-automatic retransmission mode. */ + type_func_t rfom; /**< Enable or disable the Receive fifo Locked mode. */ + type_func_t txmp; /**< Enable or disable the transmit fifo priority. */ } can_init_t; /** * @brief CAN Tx message structure definition */ -typedef struct -{ - uint32_t std; /**< Specifies the standard identifier. */ - uint32_t ext; /**< Specifies the extended identifier. */ - can_id_type_t type; /**< Specifies the type of identifier for the message that will be transmitted. */ - can_remote_req_t rtr; /**< Specifies the type of frame for the message that will be transmitted. */ - uint32_t len; /**< Specifies the length of the frame that will be transmitted. */ - uint8_t data[8]; /**< Contains the data to be transmitted. */ +typedef struct { + uint32_t std; /**< Specifies the standard identifier. */ + uint32_t ext; /**< Specifies the extended identifier. */ + can_id_type_t type; /**< Specifies the type of identifier for the message that will be transmitted. */ + can_remote_req_t rtr; /**< Specifies the type of frame for the message that will be transmitted. */ + uint32_t len; /**< Specifies the length of the frame that will be transmitted. */ + uint8_t data[8]; /**< Contains the data to be transmitted. */ } can_tx_msg_t; /** * @brief CAN Rx message structure definition */ -typedef struct -{ - uint32_t std; /**< Specifies the standard identifier. */ - uint32_t ext; /**< Specifies the extended identifier. */ - can_id_type_t type; /**< Specifies the type of identifier for the message that will be received. */ - can_remote_req_t rtr; /**< Specifies the type of frame for the received message. */ - uint32_t len; /**< Specifies the length of the frame that will be received. */ - uint8_t data[8]; /**< Contains the data to be received. */ - uint32_t fmi; /**< Specifies the index of the filter the message stored in the mailbox passes through. */ - can_rx_fifo_t num; /**< Specifies the receive fifo number. */ +typedef struct { + uint32_t std; /**< Specifies the standard identifier. */ + uint32_t ext; /**< Specifies the extended identifier. */ + can_id_type_t type; /**< Specifies the type of identifier for the message that will be received. */ + can_remote_req_t rtr; /**< Specifies the type of frame for the received message. */ + uint32_t len; /**< Specifies the length of the frame that will be received. */ + uint8_t data[8]; /**< Contains the data to be received. */ + uint32_t fmi; /**< Specifies the index of the filter the message stored in the mailbox passes through. */ + can_rx_fifo_t num; /**< Specifies the receive fifo number. */ } can_rx_msg_t; /** * @brief CAN handle Structure definition */ -typedef struct can_handle_s -{ - CAN_TypeDef *perh; /**< Register base address */ - can_init_t init; /**< CAN required parameters */ - can_rx_msg_t *rx_msg; /**< Pointer to receive message */ - lock_state_t lock; /**< CAN locking object */ - can_state_t state; /**< CAN communication state */ - can_error_t err; /**< CAN Error code */ - - void (*tx_cplt_cbk)(struct can_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct can_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct can_handle_s *arg); /**< error callback */ +typedef struct can_handle_s { + CAN_TypeDef *perh; /**< Register base address */ + can_init_t init; /**< CAN required parameters */ + can_rx_msg_t *rx0_msg; /**< Pointer to receive message from FIFO0 */ + can_rx_msg_t *rx1_msg; /**< Pointer to receive message from FIFO1 */ + lock_state_t lock; /**< CAN locking object */ + can_state_t state; /**< CAN communication state */ + can_error_t err; /**< CAN Error code */ + + void (*tx_cplt_cbk)(struct can_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct can_handle_s *arg, can_rx_fifo_t num); /**< Rx completed callback */ + void (*error_cbk)(struct can_handle_s *arg); /**< error callback */ } can_handle_t; /** * @} @@ -328,10 +312,10 @@ typedef struct can_handle_s */ #define CAN_RESET_HANDLE_STATE(x) ((x)->state = CAN_STATE_RESET) #define CAN_RX_MSG_PENDING(x, y) (((y) == CAN_RX_FIFO0) ? \ - (READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK))) + (READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK))) #define CAN_DBG_FREEZE(x, y) (MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS)) -#define CAN_TX_STAMP_ENABLE(x) (SET_BIT(hperh->perh->TxMailBox[(x)].TXFCON, CAN_TXFCON0_TXGT_MSK)) -#define CAN_TX_STAMP_DISABLE(x) (CLEAR_BIT(hperh->perh->TxMailBox[(x)].TXFCON, CAN_TXFCON0_TXGT_MSK)) +#define CAN_TX_STAMP_ENABLE(x, y) (SET_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK)) +#define CAN_TX_STAMP_DISABLE(x, y) (CLEAR_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK)) /** * @} */ @@ -358,62 +342,63 @@ typedef struct can_handle_s #define IS_CAN_FILTER_FIFO(x) (((x) == CAN_FILTER_FIFO0) || \ ((x) == CAN_FILTER_FIFO1)) #define IS_CAN_IDTYPE(x) (((x) == CAN_ID_STD) || \ - ((x) == CAN_ID_EXT)) + ((x) == CAN_ID_EXT)) #define IS_CAN_RTR(x) (((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE)) #define IS_CAN_FIFO(x) (((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1)) -#define IS_CAN_BANKNUMBER(x) ((x) <= 28) #define IS_CAN_TX_MAILBOX(x) ((x) <= CAN_TX_MAILBOX_NONE) #define IS_CAN_STDID(x) ((x) <= ((uint32_t)0x7FF)) #define IS_CAN_EXTID(x) ((x) <= ((uint32_t)0x1FFFFFFF)) #define IS_CAN_DATA_LEN(x) ((x) <= ((uint8_t)0x08)) #define IS_CAN_PRESCALER(x) (((x) >= 1) && ((x) <= 1024)) #define IS_CAN_GET_FLAG(x) (((x) == CAN_FLAG_SLPS) || \ - ((x) == CAN_FLAG_ERR) || \ - ((x) == CAN_FLAG_WK) || \ - ((x) == CAN_FLAG_SLP) || \ - ((x) == CAN_FLAG_M0REQC) || \ - ((x) == CAN_FLAG_M0TXC) || \ - ((x) == CAN_FLAG_M1REQC) || \ - ((x) == CAN_FLAG_M1TXC) || \ - ((x) == CAN_FLAG_M2REQC) || \ - ((x) == CAN_FLAG_M2TXC) || \ - ((x) == CAN_FLAG_TXM0) || \ - ((x) == CAN_FLAG_TXM1) || \ - ((x) == CAN_FLAG_TXM2) || \ - ((x) == CAN_FLAG_FF0) || \ - ((x) == CAN_FLAG_FOV0) || \ - ((x) == CAN_FLAG_FF1) || \ - ((x) == CAN_FLAG_FOV1) || \ - ((x) == CAN_FLAG_WARN) || \ - ((x) == CAN_FLAG_PERR) || \ - ((x) == CAN_FLAG_BOF)) + ((x) == CAN_FLAG_ERR) || \ + ((x) == CAN_FLAG_WK) || \ + ((x) == CAN_FLAG_SLP) || \ + ((x) == CAN_FLAG_M0REQC) || \ + ((x) == CAN_FLAG_M0TXC) || \ + ((x) == CAN_FLAG_M1REQC) || \ + ((x) == CAN_FLAG_M1TXC) || \ + ((x) == CAN_FLAG_M2REQC) || \ + ((x) == CAN_FLAG_M2TXC) || \ + ((x) == CAN_FLAG_TXM0) || \ + ((x) == CAN_FLAG_TXM1) || \ + ((x) == CAN_FLAG_TXM2) || \ + ((x) == CAN_FLAG_FF0) || \ + ((x) == CAN_FLAG_FOV0) || \ + ((x) == CAN_FLAG_FF1) || \ + ((x) == CAN_FLAG_FOV1) || \ + ((x) == CAN_FLAG_WARN) || \ + ((x) == CAN_FLAG_PERR) || \ + ((x) == CAN_FLAG_BOF)) #define IS_CAN_CLEAR_FLAG(x) (((x) == CAN_FLAG_ERR) || \ - ((x) == CAN_FLAG_WK) || \ - ((x) == CAN_FLAG_SLP) || \ - ((x) == CAN_FLAG_M0REQC) || \ - ((x) == CAN_FLAG_M1REQC) || \ - ((x) == CAN_FLAG_M2REQC) || \ - ((x) == CAN_FLAG_FF0) || \ - ((x) == CAN_FLAG_FOV0) || \ - ((x) == CAN_FLAG_FF1) || \ - ((x) == CAN_FLAG_FOV1)) + ((x) == CAN_FLAG_WK) || \ + ((x) == CAN_FLAG_SLP) || \ + ((x) == CAN_FLAG_M0REQC) || \ + ((x) == CAN_FLAG_M1REQC) || \ + ((x) == CAN_FLAG_M2REQC) || \ + ((x) == CAN_FLAG_FF0) || \ + ((x) == CAN_FLAG_FOV0) || \ + ((x) == CAN_FLAG_FF1) || \ + ((x) == CAN_FLAG_FOV1)) #define IS_CAN_IT(x) (((x) == CAN_IT_TXM) || \ - ((x) == CAN_IT_FP0) || \ - ((x) == CAN_IT_FF0) || \ - ((x) == CAN_IT_FOV0) || \ - ((x) == CAN_IT_FP1) || \ - ((x) == CAN_IT_FF1) || \ - ((x) == CAN_IT_FOV1) || \ - ((x) == CAN_IT_WARN) || \ - ((x) == CAN_IT_PERR) || \ - ((x) == CAN_IT_BOF) || \ - ((x) == CAN_IT_PRERR) || \ - ((x) == CAN_IT_ERR) || \ - ((x) == CAN_IT_WK) || \ - ((x) == CAN_IT_SLP)) -#define CAN_TIMEOUT_VALUE 100 + ((x) == CAN_IT_FP0) || \ + ((x) == CAN_IT_FF0) || \ + ((x) == CAN_IT_FOV0) || \ + ((x) == CAN_IT_FP1) || \ + ((x) == CAN_IT_FF1) || \ + ((x) == CAN_IT_FOV1) || \ + ((x) == CAN_IT_WARN) || \ + ((x) == CAN_IT_PERR) || \ + ((x) == CAN_IT_BOF) || \ + ((x) == CAN_IT_PRERR) || \ + ((x) == CAN_IT_ERR) || \ + ((x) == CAN_IT_WK) || \ + ((x) == CAN_IT_SLP)) +#define CAN_TIMEOUT_VALUE 100 #define CAN_STATE_TX_MASK (1U << 4) -#define CAN_STATE_RX_MASK (1U << 5) +#define CAN_STATE_RX0_MASK (1U << 5) +#define CAN_STATE_RX1_MASK (1U << 6) + /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h index 5bcae0bd075aa20383264f2e98295db69d5770b0..648b3c2b50cad804099fcd0216266904e822853f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h @@ -37,91 +37,91 @@ extern "C" { * @{ */ #define CMU_LOSC_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LOSC_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LRC_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LRC_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_ULRC_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_ULRC_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) /* Low power mode control */ #define CMU_LP_LRC_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LP_LRC_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LP_LOSC_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LP_LOSC_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LP_HRC_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LP_HRC_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LP_HOSC_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define CMU_LP_HOSC_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) /** * @} */ @@ -133,287 +133,282 @@ extern "C" { /** * @brief CMU state structure definition */ -typedef enum -{ - CMU_CLOCK_HRC = 0x1, /**< HRC */ - CMU_CLOCK_LRC = 0x2, /**< LRC */ - CMU_CLOCK_LOSC = 0x3, /**< LOSC */ - CMU_CLOCK_PLL1 = 0x4, /**< PLL1 */ - CMU_CLOCK_HOSC = 0x5, /**< HOSC */ +typedef enum { + CMU_CLOCK_HRC = 0x1U, /**< HRC */ + CMU_CLOCK_LRC = 0x2U, /**< LRC */ + CMU_CLOCK_LOSC = 0x3U, /**< LOSC */ + CMU_CLOCK_PLL1 = 0x4U, /**< PLL1 */ + CMU_CLOCK_HOSC = 0x5U, /**< HOSC */ } cmu_clock_t; /** * @brief PLL1 output clock */ -typedef enum -{ - CMU_PLL1_OUTPUT_32M = 0x0, /**< x8 (32MHz) */ - CMU_PLL1_OUTPUT_48M = 0x1, /**< x12 (48MHz) */ +typedef enum { + CMU_PLL1_OUTPUT_32M = 0x0U, /**< x8 (32MHz) */ + CMU_PLL1_OUTPUT_48M = 0x1U, /**< x12 (48MHz) */ } cmu_pll1_output_t; /** * @brief PLL1 referance clock */ -typedef enum -{ - CMU_PLL1_INPUT_HRC_6 = 0x0, /**< HRC / 6 */ - CMU_PLL1_INPUT_PLL2 = 0x1, /**< PLL2 */ - CMU_PLL1_INPUT_HOSC = 0x2, /**< HOSC / 1 */ - CMU_PLL1_INPUT_HOSC_2 = 0x3, /**< HOSC / 2 */ - CMU_PLL1_INPUT_HOSC_3 = 0x4, /**< HOSC / 3 */ - CMU_PLL1_INPUT_HOSC_4 = 0x5, /**< HOSC / 4 */ - CMU_PLL1_INPUT_HOSC_5 = 0x6, /**< HOSC / 5 */ - CMU_PLL1_INPUT_HOSC_6 = 0x7, /**< HOSC / 6 */ +typedef enum { + CMU_PLL1_INPUT_HRC_6 = 0x0U, /**< HRC / 6 */ + CMU_PLL1_INPUT_PLL2 = 0x1U, /**< PLL2 */ + CMU_PLL1_INPUT_HOSC = 0x2U, /**< HOSC / 1 */ + CMU_PLL1_INPUT_HOSC_2 = 0x3U, /**< HOSC / 2 */ + CMU_PLL1_INPUT_HOSC_3 = 0x4U, /**< HOSC / 3 */ + CMU_PLL1_INPUT_HOSC_4 = 0x5U, /**< HOSC / 4 */ + CMU_PLL1_INPUT_HOSC_5 = 0x6U, /**< HOSC / 5 */ + CMU_PLL1_INPUT_HOSC_6 = 0x7U, /**< HOSC / 6 */ } cmu_pll1_input_t; /** * @brief HOSC range */ -typedef enum -{ - CMU_HOSC_2M = 0x0, - CMU_HOSC_4M = 0x1, - CMU_HOSC_8M = 0x2, - CMU_HOSC_16M = 0x3, - CMU_HOSC_24M = 0x4, +typedef enum { + CMU_HOSC_2M = 0x0U, /**< 0~2MHz */ + CMU_HOSC_4M = 0x1U, /**< 2~4MHz */ + CMU_HOSC_8M = 0x2U, /**< 4~8MHz */ + CMU_HOSC_16M = 0x3U, /**< 8~16MHz */ + CMU_HOSC_24M = 0x4U, /**< 16~24MHz */ } cmu_hosc_range_t; /** * @brief Auto-calibrate input */ -typedef enum -{ - CMU_AUTO_CALIB_INPUT_LOSE = 0x0, - CMU_AUTO_CALIB_INPUT_HOSE = 0x1, +typedef enum { + CMU_AUTO_CALIB_INPUT_LOSE = 0x0U, /**< LOSC */ + CMU_AUTO_CALIB_INPUT_HOSE = 0x1U, /**< HOSC */ } cmu_auto_calib_input_t; /** * @brief Auto-calibrate output */ -typedef enum -{ - CMU_AUTO_CALIB_OUTPUT_24M = 0x0, - CMU_AUTO_CALIB_OUTPUT_2M = 0x1, +typedef enum { + CMU_AUTO_CALIB_OUTPUT_24M = 0x0U, /**< HOSC 24MHz */ + CMU_AUTO_CALIB_OUTPUT_2M = 0x1U, /**< HOSC 2MHz */ } cmu_auto_calib_output_t; +/** + * @brief Safe clock source type + */ +typedef enum { + CMU_SAFE_CLK_HOSC = 0x0U, /**< HOSC */ + CMU_SAFE_CLK_LOSC = 0x1U, /**< LOSC */ + CMU_SAFE_CLK_PLL = 0x2U, /**< PLL */ +} cmu_clock_safe_type_t; + /** * @brief Frequency division select bit */ -typedef enum -{ - CMU_DIV_1 = 0x0, /**< Division by 1 */ - CMU_DIV_2 = 0x1, /**< Division by 2 */ - CMU_DIV_4 = 0x2, /**< Division by 4 */ - CMU_DIV_8 = 0x3, /**< Division by 8 */ - CMU_DIV_16 = 0x4, /**< Division by 16 */ - CMU_DIV_32 = 0x5, /**< Division by 32 */ - CMU_DIV_64 = 0x6, /**< Division by 64 */ - CMU_DIV_128 = 0x7, /**< Division by 128 */ - CMU_DIV_256 = 0x8, /**< Division by 256 */ - CMU_DIV_512 = 0x9, /**< Division by 512 */ - CMU_DIV_1024 = 0xA, /**< Division by 1024 */ - CMU_DIV_2048 = 0xB, /**< Division by 2048 */ - CMU_DIV_4096 = 0xC, /**< Division by 4096 */ +typedef enum { + CMU_DIV_1 = 0x0U, /**< Division by 1 */ + CMU_DIV_2 = 0x1U, /**< Division by 2 */ + CMU_DIV_4 = 0x2U, /**< Division by 4 */ + CMU_DIV_8 = 0x3U, /**< Division by 8 */ + CMU_DIV_16 = 0x4U, /**< Division by 16 */ + CMU_DIV_32 = 0x5U, /**< Division by 32 */ + CMU_DIV_64 = 0x6U, /**< Division by 64 */ + CMU_DIV_128 = 0x7U, /**< Division by 128 */ + CMU_DIV_256 = 0x8U, /**< Division by 256 */ + CMU_DIV_512 = 0x9U, /**< Division by 512 */ + CMU_DIV_1024 = 0xAU, /**< Division by 1024 */ + CMU_DIV_2048 = 0xBU, /**< Division by 2048 */ + CMU_DIV_4096 = 0xCU, /**< Division by 4096 */ } cmu_div_t; /** * @brief Bus type */ -typedef enum -{ - CMU_HCLK_1 = 0x0, /**< AHB1 bus */ - CMU_SYS = 0x1, /**< SYS bus */ - CMU_PCLK_1 = 0x2, /**< APB1 bus */ - CMU_PCLK_2 = 0x3, /**< APB2 bus */ +typedef enum { + CMU_HCLK_1 = 0x0U, /**< AHB1 bus */ + CMU_SYS = 0x1U, /**< SYS bus */ + CMU_PCLK_1 = 0x2U, /**< APB1 bus */ + CMU_PCLK_2 = 0x3U, /**< APB2 bus */ } cmu_bus_t; /** * @brief Output high clock select */ -typedef enum -{ - CMU_OUTPUT_HIGH_SEL_HOSC = 0x0, /**< Select HOSC */ - CMU_OUTPUT_HIGH_SEL_LOSC = 0x1, /**< Select LOSC */ - CMU_OUTPUT_HIGH_SEL_HRC = 0x2, /**< Select HRC */ - CMU_OUTPUT_HIGH_SEL_LRC = 0x3, /**< Select LRC */ - CMU_OUTPUT_HIGH_SEL_HOSM = 0x4, /**< Select HOSM */ - CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5, /**< Select PLL1 */ - CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6, /**< Select PLL2 */ - CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7, /**< Select SYSCLK */ +typedef enum { + CMU_OUTPUT_HIGH_SEL_HOSC = 0x0U, /**< Select HOSC */ + CMU_OUTPUT_HIGH_SEL_LOSC = 0x1U, /**< Select LOSC */ + CMU_OUTPUT_HIGH_SEL_HRC = 0x2U, /**< Select HRC */ + CMU_OUTPUT_HIGH_SEL_LRC = 0x3U, /**< Select LRC */ + CMU_OUTPUT_HIGH_SEL_HOSM = 0x4U, /**< Select HOSM */ + CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5U, /**< Select PLL1 */ + CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6U, /**< Select PLL2 */ + CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7U, /**< Select SYSCLK */ } cmu_output_high_sel_t; /** * @brief Output frequency division */ -typedef enum -{ - CMU_OUTPUT_DIV_1 = 0x0, /**< Division by 1 */ - CMU_OUTPUT_DIV_2 = 0x1, /**< Division by 2 */ - CMU_OUTPUT_DIV_4 = 0x2, /**< Division by 4 */ - CMU_OUTPUT_DIV_8 = 0x3, /**< Division by 8 */ - CMU_OUTPUT_DIV_16 = 0x4, /**< Division by 16 */ - CMU_OUTPUT_DIV_32 = 0x5, /**< Division by 32 */ - CMU_OUTPUT_DIV_64 = 0x6, /**< Division by 64 */ - CMU_OUTPUT_DIV_128 = 0x7, /**< Division by 128 */ +typedef enum { + CMU_OUTPUT_DIV_1 = 0x0U, /**< Division by 1 */ + CMU_OUTPUT_DIV_2 = 0x1U, /**< Division by 2 */ + CMU_OUTPUT_DIV_4 = 0x2U, /**< Division by 4 */ + CMU_OUTPUT_DIV_8 = 0x3U, /**< Division by 8 */ + CMU_OUTPUT_DIV_16 = 0x4U, /**< Division by 16 */ + CMU_OUTPUT_DIV_32 = 0x5U, /**< Division by 32 */ + CMU_OUTPUT_DIV_64 = 0x6U, /**< Division by 64 */ + CMU_OUTPUT_DIV_128 = 0x7U, /**< Division by 128 */ } cmu_output_high_div_t; /** * @brief Output low clock select */ -typedef enum -{ - CMU_OUTPUT_LOW_SEL_LOSC = 0x0, /**< Select LOSC */ - CMU_OUTPUT_LOW_SEL_LRC = 0x1, /**< Select LRC */ - CMU_OUTPUT_LOW_SEL_LOSM = 0x2, /**< Select LOSM */ - CMU_OUTPUT_LOW_SEL_BUZZ = 0x3, /**< Select BUZZ */ - CMU_OUTPUT_LOW_SEL_ULRC = 0x4, /**< Select ULRC */ +typedef enum { + CMU_OUTPUT_LOW_SEL_LOSC = 0x0U, /**< Select LOSC */ + CMU_OUTPUT_LOW_SEL_LRC = 0x1U, /**< Select LRC */ + CMU_OUTPUT_LOW_SEL_LOSM = 0x2U, /**< Select LOSM */ + CMU_OUTPUT_LOW_SEL_BUZZ = 0x3U, /**< Select BUZZ */ + CMU_OUTPUT_LOW_SEL_ULRC = 0x4U, /**< Select ULRC */ } cmu_output_low_sel_t; /** * @brief BUZZ frequency division */ -typedef enum -{ - CMU_BUZZ_DIV_2 = 0x0, /**< Division by 2 */ - CMU_BUZZ_DIV_4 = 0x1, /**< Division by 4 */ - CMU_BUZZ_DIV_8 = 0x2, /**< Division by 8 */ - CMU_BUZZ_DIV_16 = 0x3, /**< Division by 16 */ - CMU_BUZZ_DIV_32 = 0x4, /**< Division by 32 */ - CMU_BUZZ_DIV_64 = 0x5, /**< Division by 64 */ - CMU_BUZZ_DIV_128 = 0x6, /**< Division by 128 */ - CMU_BUZZ_DIV_256 = 0x7, /**< Division by 256 */ +typedef enum { + CMU_BUZZ_DIV_2 = 0x0U, /**< Division by 2 */ + CMU_BUZZ_DIV_4 = 0x1U, /**< Division by 4 */ + CMU_BUZZ_DIV_8 = 0x2U, /**< Division by 8 */ + CMU_BUZZ_DIV_16 = 0x3U, /**< Division by 16 */ + CMU_BUZZ_DIV_32 = 0x4U, /**< Division by 32 */ + CMU_BUZZ_DIV_64 = 0x5U, /**< Division by 64 */ + CMU_BUZZ_DIV_128 = 0x6U, /**< Division by 128 */ + CMU_BUZZ_DIV_256 = 0x7U, /**< Division by 256 */ } cmu_buzz_div_t; /** * @brief Low power peripheral clock select */ -typedef enum -{ - CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0, /**< Select PCLK2 */ - CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1, /**< Select PLL1 */ - CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2, /**< Select PLL2 */ - CMU_LP_PERH_CLOCK_SEL_HRC = 0x3, /**< Select HRC */ - CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4, /**< Select HOSC */ - CMU_LP_PERH_CLOCK_SEL_LRC = 0x5, /**< Select LRC */ - CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6, /**< Select LOSC */ - CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7, /**< Select ULRC */ - CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8, /**< Select HRC down to 1MHz */ - CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9, /**< Select HOSC down to 1MHz */ - CMU_LP_PERH_CLOCK_SEL_LOSM = 0xA, /**< Select LOSM */ - CMU_LP_PERH_CLOCK_SEL_HOSM = 0xB, /**< Select HOSM */ +typedef enum { + CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0U, /**< Select PCLK2 */ + CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1U, /**< Select PLL1 */ + CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2U, /**< Select PLL2 */ + CMU_LP_PERH_CLOCK_SEL_HRC = 0x3U, /**< Select HRC */ + CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4U, /**< Select HOSC */ + CMU_LP_PERH_CLOCK_SEL_LRC = 0x5U, /**< Select LRC */ + CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6U, /**< Select LOSC */ + CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7U, /**< Select ULRC */ + CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8U, /**< Select HRC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9U, /**< Select HOSC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_LOSM = 0xAU, /**< Select LOSM */ + CMU_LP_PERH_CLOCK_SEL_HOSM = 0xBU, /**< Select HOSM */ } cmu_lp_perh_clock_sel_t; /** * @brief LCD clock select */ -typedef enum -{ - CMU_LCD_SEL_LOSM = 0x0, /**< Select LOSM */ - CMU_LCD_SEL_LOSC = 0x1, /**< Select LOSC */ - CMU_LCD_SEL_LRC = 0x2, /**< Select LRC */ - CMU_LCD_SEL_ULRC = 0x3, /**< Select ULRC */ - CMU_LCD_SEL_HRC_1M = 0x4, /**< Select HRC down to 1MHz */ - CMU_LCD_SEL_HOSC_1M = 0x5, /**< Select HOSC down to 1MHz */ +typedef enum { + CMU_LCD_SEL_LOSM = 0x0U, /**< Select LOSM */ + CMU_LCD_SEL_LOSC = 0x1U, /**< Select LOSC */ + CMU_LCD_SEL_LRC = 0x2U, /**< Select LRC */ + CMU_LCD_SEL_ULRC = 0x3U, /**< Select ULRC */ + CMU_LCD_SEL_HRC_1M = 0x4U, /**< Select HRC down to 1MHz */ + CMU_LCD_SEL_HOSC_1M = 0x5U, /**< Select HOSC down to 1MHz */ } cmu_lcd_clock_sel_t; /** * @brief Peripheral clock enable/disable - * @note ES32F065x: - * AD16C4T0--TIMER0 - * GP16C4T0--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - * - * ES32F033x: - * ES32F093x: - * GP16C4T0--TIMER0 - * GP16C4T1--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - */ -typedef enum -{ - CMU_PERH_GPIO = (1U << 0), /**< GPIO */ - CMU_PERH_CRC = (1U << 1), /**< CRC */ - CMU_PERH_CALC = (1U << 2), /**< CALC */ - CMU_PERH_CRYPT = (1U << 3), /**< CRYPT */ - CMU_PERH_TRNG = (1U << 4), /**< TRNG */ - CMU_PERH_PIS = (1U << 5), /**< PIS */ - CMU_PERH_TIMER0 = (1U << 0) | (1U << 27), /**< TIMER0 */ - CMU_PERH_TIMER1 = (1U << 1) | (1U << 27), /**< TIMER1 */ - CMU_PERH_TIMER2 = (1U << 2) | (1U << 27), /**< TIMER2 */ - CMU_PERH_TIMER3 = (1U << 3) | (1U << 27), /**< TIMER3 */ - CMU_PERH_TIMER4 = (1U << 4) | (1U << 27), /**< TIMER4 */ - CMU_PERH_TIMER5 = (1U << 5) | (1U << 27), /**< TIMER5 */ - CMU_PERH_TIMER6 = (1U << 6) | (1U << 27), /**< TIMER6 */ - CMU_PERH_TIMER7 = (1U << 7) | (1U << 27), /**< TIMER7 */ - CMU_PERH_UART0 = (1U << 8) | (1U << 27), /**< UART0 */ - CMU_PERH_UART1 = (1U << 9) | (1U << 27), /**< UART1 */ - CMU_PERH_UART2 = (1U << 10) | (1U << 27), /**< UART2 */ - CMU_PERH_UART3 = (1U << 11) | (1U << 27), /**< UART3 */ - CMU_PERH_USART0 = (1U << 12) | (1U << 27), /**< USART0 */ - CMU_PERH_USART1 = (1U << 13) | (1U << 27), /**< USART1 */ - CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ - CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ - CMU_PERH_SPI2 = (1U << 18) | (1U << 27), /**< SPI2 */ - CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ - CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ - CMU_PERH_CAN = (1U << 24) | (1U << 27), /**< CAN */ - CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), /**< LPTIM0 */ - CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), /**< LPUART0 */ - CMU_PERH_ADC0 = (1U << 4) | (1U << 28), /**< ADC0 */ - CMU_PERH_ADC1 = (1U << 5) | (1U << 28), /**< ADC1 */ - CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), /**< ACMP0 */ - CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), /**< ACMP1 */ - CMU_PERH_OPAMP = (1U << 8) | (1U << 28), /**< OPAMP */ - CMU_PERH_DAC0 = (1U << 9) | (1U << 28), /**< DAC0 */ - CMU_PERH_WWDT = (1U << 12) | (1U << 28), /**< WWDT */ - CMU_PERH_LCD = (1U << 13) | (1U << 28), /**< LCD */ - CMU_PERH_IWDT = (1U << 14) | (1U << 28), /**< IWDT */ - CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */ - CMU_PERH_TSENSE = (1U << 16) | (1U << 28), /**< TSENSE */ - CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */ - CMU_PERH_BKRPAM = (1U << 18) | (1U << 28), /**< BKPRAM */ - CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */ - CMU_PERH_ALL = (0x7FFFFFFF), /**< ALL */ + * @verbatim + In this module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F065x series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + TIMER4 ----> BS16T1 + TIMER5 ----> BS16T2 + TIMER6 ----> GP16C4T0 + TIMER7 ----> BS16T3 + + 2. For ES32F033x/ES32F093x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + TIMER4 ----> BS16T1 + TIMER5 ----> BS16T2 + TIMER6 ----> GP16C4T1 + TIMER7 ----> BS16T3 + @endverbatim + */ +typedef enum { + CMU_PERH_GPIO = (1U << 0), /**< GPIO */ + CMU_PERH_CRC = (1U << 1), /**< CRC */ + CMU_PERH_CALC = (1U << 2), /**< CALC */ + CMU_PERH_CRYPT = (1U << 3), /**< CRYPT */ + CMU_PERH_TRNG = (1U << 4), /**< TRNG */ + CMU_PERH_PIS = (1U << 5), /**< PIS */ + CMU_PERH_TIMER0 = (1U << 0) | (1U << 27), /**< TIMER0 */ + CMU_PERH_TIMER1 = (1U << 1) | (1U << 27), /**< TIMER1 */ + CMU_PERH_TIMER2 = (1U << 2) | (1U << 27), /**< TIMER2 */ + CMU_PERH_TIMER3 = (1U << 3) | (1U << 27), /**< TIMER3 */ + CMU_PERH_TIMER4 = (1U << 4) | (1U << 27), /**< TIMER4 */ + CMU_PERH_TIMER5 = (1U << 5) | (1U << 27), /**< TIMER5 */ + CMU_PERH_TIMER6 = (1U << 6) | (1U << 27), /**< TIMER6 */ + CMU_PERH_TIMER7 = (1U << 7) | (1U << 27), /**< TIMER7 */ + CMU_PERH_UART0 = (1U << 8) | (1U << 27), /**< UART0 */ + CMU_PERH_UART1 = (1U << 9) | (1U << 27), /**< UART1 */ + CMU_PERH_UART2 = (1U << 10) | (1U << 27), /**< UART2 */ + CMU_PERH_UART3 = (1U << 11) | (1U << 27), /**< UART3 */ + CMU_PERH_USART0 = (1U << 12) | (1U << 27), /**< USART0 */ + CMU_PERH_USART1 = (1U << 13) | (1U << 27), /**< USART1 */ + CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ + CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ + CMU_PERH_SPI2 = (1U << 18) | (1U << 27), /**< SPI2 */ + CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ + CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ + CMU_PERH_CAN = (1U << 24) | (1U << 27), /**< CAN */ + CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), /**< LPTIM0 */ + CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), /**< LPUART0 */ + CMU_PERH_ADC0 = (1U << 4) | (1U << 28), /**< ADC0 */ + CMU_PERH_ADC1 = (1U << 5) | (1U << 28), /**< ADC1 */ + CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), /**< ACMP0 */ + CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), /**< ACMP1 */ + CMU_PERH_OPAMP = (1U << 8) | (1U << 28), /**< OPAMP */ + CMU_PERH_DAC0 = (1U << 9) | (1U << 28), /**< DAC0 */ + CMU_PERH_WWDT = (1U << 12) | (1U << 28), /**< WWDT */ + CMU_PERH_LCD = (1U << 13) | (1U << 28), /**< LCD */ + CMU_PERH_IWDT = (1U << 14) | (1U << 28), /**< IWDT */ + CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */ + CMU_PERH_TSENSE = (1U << 16) | (1U << 28), /**< TSENSE */ + CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */ + CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */ + CMU_PERH_ALL = (0x7FFFFFFF), /**< ALL */ } cmu_perh_t; /** * @brief CMU interrupt type */ -typedef enum -{ - CMU_LOSC_STOP = 0x0, /**< LOSC STOP INTERRUPT */ - CMU_HOSC_STOP = 0x1, /**< HOSC STOP INTERRUPT */ - CMU_PLL1_UNLOCK = 0x2, /**< PLL1 UNLOCK INTERRUPT */ - CMU_LOSC_START = 0x3, /**< LOSC START INTERRUPT */ - CMU_HOSC_START = 0x4, /**< HOSC START INTERRUPT */ +typedef enum { + CMU_LOSC_STOP = 0x0U, /**< LOSC STOP INTERRUPT */ + CMU_HOSC_STOP = 0x1U, /**< HOSC STOP INTERRUPT */ + CMU_PLL1_UNLOCK = 0x2U, /**< PLL1 UNLOCK INTERRUPT */ + CMU_LOSC_START = 0x3U, /**< LOSC START INTERRUPT */ + CMU_HOSC_START = 0x4U, /**< HOSC START INTERRUPT */ } cmu_security_t; /** * @brief CMU clock state type */ -typedef enum -{ - CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ - CMU_CLOCK_STATE_LOSCACT = (1U << 1), /**< LOSC active */ - CMU_CLOCK_STATE_HRCACT = (1U << 2), /**< HRC active */ - CMU_CLOCK_STATE_LRCACT = (1U << 3), /**< LRC active */ - CMU_CLOCK_STATE_ULRCACT = (1U << 4), /**< ULRC active */ - CMU_CLOCK_STATE_PLLACT = (1U << 8), /**< PLL active */ - CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ - CMU_CLOCK_STATE_LOSCRDY = (1U << 17), /**< LOSC ready */ - CMU_CLOCK_STATE_HRCRDY = (1U << 18), /**< HRC ready */ - CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ - CMU_CLOCK_STATE_PLLRDY = (1U << 24), /**< PLL ready */ +typedef enum { + CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ + CMU_CLOCK_STATE_LOSCACT = (1U << 1), /**< LOSC active */ + CMU_CLOCK_STATE_HRCACT = (1U << 2), /**< HRC active */ + CMU_CLOCK_STATE_LRCACT = (1U << 3), /**< LRC active */ + CMU_CLOCK_STATE_ULRCACT = (1U << 4), /**< ULRC active */ + CMU_CLOCK_STATE_PLLACT = (1U << 8), /**< PLL active */ + CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ + CMU_CLOCK_STATE_LOSCRDY = (1U << 17), /**< LOSC ready */ + CMU_CLOCK_STATE_HRCRDY = (1U << 18), /**< HRC ready */ + CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ + CMU_CLOCK_STATE_PLLRDY = (1U << 24), /**< PLL ready */ } cmu_clock_state_t; /** * @} @@ -424,10 +419,10 @@ typedef enum * @{ */ #define IS_CMU_CLOCK(x) (((x) == CMU_CLOCK_HRC) || \ - ((x) == CMU_CLOCK_LRC) || \ - ((x) == CMU_CLOCK_LOSC) || \ - ((x) == CMU_CLOCK_PLL1) || \ - ((x) == CMU_CLOCK_HOSC)) + ((x) == CMU_CLOCK_LRC) || \ + ((x) == CMU_CLOCK_LOSC) || \ + ((x) == CMU_CLOCK_PLL1) || \ + ((x) == CMU_CLOCK_HOSC)) #define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_32M) || \ ((x) == CMU_PLL1_OUTPUT_48M)) #define IS_CMU_PLL1_INPUT(x) (((x) == CMU_PLL1_INPUT_HRC_6) || \ @@ -444,67 +439,70 @@ typedef enum ((x) == CMU_HOSC_16M) || \ ((x) == CMU_HOSC_24M)) #define IS_CMU_DIV(x) (((x) == CMU_DIV_1) || \ - ((x) == CMU_DIV_2) || \ - ((x) == CMU_DIV_4) || \ - ((x) == CMU_DIV_8) || \ - ((x) == CMU_DIV_16) || \ - ((x) == CMU_DIV_32) || \ - ((x) == CMU_DIV_64) || \ - ((x) == CMU_DIV_128) || \ - ((x) == CMU_DIV_256) || \ - ((x) == CMU_DIV_512) || \ - ((x) == CMU_DIV_1024) || \ - ((x) == CMU_DIV_2048) || \ - ((x) == CMU_DIV_4096)) + ((x) == CMU_DIV_2) || \ + ((x) == CMU_DIV_4) || \ + ((x) == CMU_DIV_8) || \ + ((x) == CMU_DIV_16) || \ + ((x) == CMU_DIV_32) || \ + ((x) == CMU_DIV_64) || \ + ((x) == CMU_DIV_128) || \ + ((x) == CMU_DIV_256) || \ + ((x) == CMU_DIV_512) || \ + ((x) == CMU_DIV_1024) || \ + ((x) == CMU_DIV_2048) || \ + ((x) == CMU_DIV_4096)) #define IS_CMU_BUS(x) (((x) == CMU_HCLK_1) || \ - ((x) == CMU_SYS) || \ - ((x) == CMU_PCLK_1) || \ - ((x) == CMU_PCLK_2)) + ((x) == CMU_SYS) || \ + ((x) == CMU_PCLK_1) || \ + ((x) == CMU_PCLK_2)) #define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_HRC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_LRC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK)) + ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_HRC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_LRC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK)) #define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == CMU_OUTPUT_DIV_1) || \ - ((x) == CMU_OUTPUT_DIV_2) || \ - ((x) == CMU_OUTPUT_DIV_4) || \ - ((x) == CMU_OUTPUT_DIV_8) || \ - ((x) == CMU_OUTPUT_DIV_16) || \ - ((x) == CMU_OUTPUT_DIV_32) || \ - ((x) == CMU_OUTPUT_DIV_64) || \ - ((x) == CMU_OUTPUT_DIV_128)) + ((x) == CMU_OUTPUT_DIV_2) || \ + ((x) == CMU_OUTPUT_DIV_4) || \ + ((x) == CMU_OUTPUT_DIV_8) || \ + ((x) == CMU_OUTPUT_DIV_16) || \ + ((x) == CMU_OUTPUT_DIV_32) || \ + ((x) == CMU_OUTPUT_DIV_64) || \ + ((x) == CMU_OUTPUT_DIV_128)) #define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \ - ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \ - ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \ - ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \ - ((x) == CMU_OUTPUT_LOW_SEL_ULRC)) + ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \ + ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \ + ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \ + ((x) == CMU_OUTPUT_LOW_SEL_ULRC)) #define IS_CMU_AUTO_CALIB_INPUT(x) (((x) == CMU_AUTO_CALIB_INPUT_LOSE) || \ - ((x) == CMU_AUTO_CALIB_INPUT_HOSE)) + ((x) == CMU_AUTO_CALIB_INPUT_HOSE)) #define IS_CMU_AUTO_CALIB_OUTPUT(x) (((x) == CMU_AUTO_CALIB_OUTPUT_24M) || \ - ((x) == CMU_AUTO_CALIB_OUTPUT_2M)) + ((x) == CMU_AUTO_CALIB_OUTPUT_2M)) +#define IS_CMU_SAFE_CLOCK_TYPE(x) (((x) == CMU_SAFE_CLK_HOSC) || \ + ((x) == CMU_SAFE_CLK_LOSC) || \ + ((x) == CMU_SAFE_CLK_PLL)) #define IS_CMU_BUZZ_DIV(x) (((x) == CMU_BUZZ_DIV_2) || \ - ((x) == CMU_BUZZ_DIV_4) || \ - ((x) == CMU_BUZZ_DIV_8) || \ - ((x) == CMU_BUZZ_DIV_16) || \ - ((x) == CMU_BUZZ_DIV_32) || \ - ((x) == CMU_BUZZ_DIV_64) || \ - ((x) == CMU_BUZZ_DIV_128) || \ - ((x) == CMU_BUZZ_DIV_256)) + ((x) == CMU_BUZZ_DIV_4) || \ + ((x) == CMU_BUZZ_DIV_8) || \ + ((x) == CMU_BUZZ_DIV_16) || \ + ((x) == CMU_BUZZ_DIV_32) || \ + ((x) == CMU_BUZZ_DIV_64) || \ + ((x) == CMU_BUZZ_DIV_128) || \ + ((x) == CMU_BUZZ_DIV_256)) #define IS_CMU_LP_PERH_CLOCK_SEL(x) (((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HRC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_LRC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM)) + ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM)) #define IS_CMU_LCD_CLOCK_SEL(x) (((x) == CMU_LCD_SEL_LOSM) || \ ((x) == CMU_LCD_SEL_LOSC) || \ ((x) == CMU_LCD_SEL_LRC) || \ @@ -512,59 +510,58 @@ typedef enum ((x) == CMU_LCD_SEL_HRC_1M) || \ ((x) == CMU_LCD_SEL_HOSC_1M)) #define IS_CMU_PERH(x) (((x) == CMU_PERH_GPIO) || \ - ((x) == CMU_PERH_CRC) || \ - ((x) == CMU_PERH_CALC) || \ - ((x) == CMU_PERH_CRYPT) || \ - ((x) == CMU_PERH_TRNG) || \ - ((x) == CMU_PERH_PIS) || \ - ((x) == CMU_PERH_TIMER0) || \ - ((x) == CMU_PERH_TIMER1) || \ - ((x) == CMU_PERH_TIMER2) || \ - ((x) == CMU_PERH_TIMER3) || \ - ((x) == CMU_PERH_TIMER4) || \ - ((x) == CMU_PERH_TIMER5) || \ - ((x) == CMU_PERH_TIMER6) || \ - ((x) == CMU_PERH_TIMER7) || \ - ((x) == CMU_PERH_UART0) || \ - ((x) == CMU_PERH_UART1) || \ - ((x) == CMU_PERH_UART2) || \ - ((x) == CMU_PERH_UART3) || \ - ((x) == CMU_PERH_USART0) || \ - ((x) == CMU_PERH_USART1) || \ - ((x) == CMU_PERH_SPI0) || \ - ((x) == CMU_PERH_SPI1) || \ - ((x) == CMU_PERH_SPI2) || \ - ((x) == CMU_PERH_I2C0) || \ - ((x) == CMU_PERH_I2C1) || \ - ((x) == CMU_PERH_CAN) || \ - ((x) == CMU_PERH_LPTIM0) || \ - ((x) == CMU_PERH_LPUART0) || \ - ((x) == CMU_PERH_ADC0) || \ - ((x) == CMU_PERH_ADC1) || \ - ((x) == CMU_PERH_ACMP0) || \ - ((x) == CMU_PERH_ACMP1) || \ - ((x) == CMU_PERH_OPAMP) || \ - ((x) == CMU_PERH_DAC0) || \ - ((x) == CMU_PERH_WWDT) || \ - ((x) == CMU_PERH_LCD) || \ - ((x) == CMU_PERH_IWDT) || \ - ((x) == CMU_PERH_RTC) || \ - ((x) == CMU_PERH_TSENSE) || \ - ((x) == CMU_PERH_BKPC) || \ - ((x) == CMU_PERH_BKRPAM ) || \ - ((x) == CMU_PERH_DBGC) || \ - ((x) == CMU_PERH_ALL)) + ((x) == CMU_PERH_CRC) || \ + ((x) == CMU_PERH_CALC) || \ + ((x) == CMU_PERH_CRYPT) || \ + ((x) == CMU_PERH_TRNG) || \ + ((x) == CMU_PERH_PIS) || \ + ((x) == CMU_PERH_TIMER0) || \ + ((x) == CMU_PERH_TIMER1) || \ + ((x) == CMU_PERH_TIMER2) || \ + ((x) == CMU_PERH_TIMER3) || \ + ((x) == CMU_PERH_TIMER4) || \ + ((x) == CMU_PERH_TIMER5) || \ + ((x) == CMU_PERH_TIMER6) || \ + ((x) == CMU_PERH_TIMER7) || \ + ((x) == CMU_PERH_UART0) || \ + ((x) == CMU_PERH_UART1) || \ + ((x) == CMU_PERH_UART2) || \ + ((x) == CMU_PERH_UART3) || \ + ((x) == CMU_PERH_USART0) || \ + ((x) == CMU_PERH_USART1) || \ + ((x) == CMU_PERH_SPI0) || \ + ((x) == CMU_PERH_SPI1) || \ + ((x) == CMU_PERH_SPI2) || \ + ((x) == CMU_PERH_I2C0) || \ + ((x) == CMU_PERH_I2C1) || \ + ((x) == CMU_PERH_CAN) || \ + ((x) == CMU_PERH_LPTIM0) || \ + ((x) == CMU_PERH_LPUART0) || \ + ((x) == CMU_PERH_ADC0) || \ + ((x) == CMU_PERH_ADC1) || \ + ((x) == CMU_PERH_ACMP0) || \ + ((x) == CMU_PERH_ACMP1) || \ + ((x) == CMU_PERH_OPAMP) || \ + ((x) == CMU_PERH_DAC0) || \ + ((x) == CMU_PERH_WWDT) || \ + ((x) == CMU_PERH_LCD) || \ + ((x) == CMU_PERH_IWDT) || \ + ((x) == CMU_PERH_RTC) || \ + ((x) == CMU_PERH_TSENSE) || \ + ((x) == CMU_PERH_BKPC) || \ + ((x) == CMU_PERH_DBGC) || \ + ((x) == CMU_PERH_ALL)) #define IS_CMU_CLOCK_STATE(x) (((x) == CMU_CLOCK_STATE_HOSCACT) || \ ((x) == CMU_CLOCK_STATE_LOSCACT) || \ - ((x) == CMU_CLOCK_STATE_HRCACT) || \ - ((x) == CMU_CLOCK_STATE_LRCACT) || \ - ((x) == CMU_CLOCK_STATE_ULRCACT) || \ - ((x) == CMU_CLOCK_STATE_PLLACT) || \ - ((x) == CMU_CLOCK_STATE_HOSCRDY) || \ - ((x) == CMU_CLOCK_STATE_LOSCRDY) || \ - ((x) == CMU_CLOCK_STATE_HRCRDY) || \ - ((x) == CMU_CLOCK_STATE_LRCRDY) || \ - ((x) == CMU_CLOCK_STATE_PLLRDY)) + ((x) == CMU_CLOCK_STATE_HRCACT) || \ + ((x) == CMU_CLOCK_STATE_LRCACT) || \ + ((x) == CMU_CLOCK_STATE_ULRCACT) || \ + ((x) == CMU_CLOCK_STATE_PLLACT) || \ + ((x) == CMU_CLOCK_STATE_HOSCRDY) || \ + ((x) == CMU_CLOCK_STATE_LOSCRDY) || \ + ((x) == CMU_CLOCK_STATE_HRCRDY) || \ + ((x) == CMU_CLOCK_STATE_LRCRDY) || \ + ((x) == CMU_CLOCK_STATE_PLLRDY)) /** * @} */ @@ -605,6 +602,7 @@ uint32_t ald_cmu_get_pclk2_clock(void); void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status); void ald_cmu_losc_safe_config(type_func_t status); void ald_cmu_pll_safe_config(type_func_t status); +uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type); flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr); void ald_cmu_irq_handler(void); void ald_cmu_irq_cbk(cmu_security_t se); @@ -617,7 +615,7 @@ void ald_cmu_irq_cbk(cmu_security_t se); */ /* Clock output configure */ void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, - cmu_output_high_div_t div, type_func_t status); + cmu_output_high_div_t div, type_func_t status); void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status); /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h index e3281dc166891a72aae047822aacfed3f1568c26..3ea24ea92734ec25a368dc259bd4b387234f8c8b 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h @@ -18,7 +18,7 @@ #define __ALD_CRC_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -39,75 +39,69 @@ extern "C" { /** * @brief CRC mode */ -typedef enum -{ - CRC_MODE_CCITT = 0, /**< Ccitt */ - CRC_MODE_8 = 1, /**< Crc8 */ - CRC_MODE_16 = 2, /**< Crc16 */ - CRC_MODE_32 = 3, /**< Crc32 */ +typedef enum { + CRC_MODE_CCITT = 0U, /**< Ccitt */ + CRC_MODE_8 = 1U, /**< Crc8 */ + CRC_MODE_16 = 2U, /**< Crc16 */ + CRC_MODE_32 = 3U, /**< Crc32 */ } crc_mode_t; /** * @brief CRC input length */ -typedef enum -{ - CRC_LEN_AUTO = 0, /**< Auto */ - CRC_DATASIZE_8 = 1, /**< Byte */ - CRC_DATASIZE_16 = 2, /**< Half word */ - CRC_DATASIZE_32 = 3, /**< Word */ +typedef enum { + CRC_LEN_AUTO = 0U, /**< Auto */ + CRC_DATASIZE_8 = 1U, /**< Byte */ + CRC_DATASIZE_16 = 2U, /**< Half word */ + CRC_DATASIZE_32 = 3U, /**< Word */ } crc_datasize_t; /** * @brief CRC whether write error or no */ -typedef enum -{ - CRC_WERR_NO = 0, /**< No error */ - CRC_WERR_ERR = 1, /**< Error */ +typedef enum { + CRC_WERR_NO = 0U, /**< No error */ + CRC_WERR_ERR = 1U, /**< Error */ } crc_werr_t; /** * @brief CRC state structures definition */ -typedef enum -{ - CRC_STATE_RESET = 0x0, /**< Peripheral is not initialized */ - CRC_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - CRC_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - CRC_STATE_ERROR = 0x4, /**< Error */ +typedef enum { + CRC_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ + CRC_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + CRC_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + CRC_STATE_ERROR = 0x4U, /**< Error */ } crc_state_t; /** * @brief CRC init structure definition */ -typedef struct -{ - crc_mode_t mode; /**< CRC mode */ - type_func_t data_rev; /**< CRC data reverse or no */ - type_func_t data_inv; /**< CRC data inverse or no */ - type_func_t chs_rev; /**< CRC check sum reverse or no */ - type_func_t chs_inv; /**< CRC check sum inverse or no */ - uint32_t seed; /**< CRC seed */ +typedef struct { + crc_mode_t mode; /**< CRC mode */ + type_func_t data_rev; /**< CRC data reverse or no */ + type_func_t data_inv; /**< CRC data inverse or no */ + type_func_t chs_rev; /**< CRC check sum reverse or no */ + type_func_t chs_inv; /**< CRC check sum inverse or no */ + uint32_t seed; /**< CRC seed */ } crc_init_t; /** * @brief CRC Handle Structure definition */ -typedef struct crc_handle_s -{ - CRC_TypeDef *perh; /**< Register base address */ - crc_init_t init; /**< CRC required parameters */ - uint8_t *cal_buf; /**< The pointer of preparing buffer */ - uint32_t *cal_res; /**< The pointer of result */ +typedef struct crc_handle_s { + CRC_TypeDef *perh; /**< Register base address */ + crc_init_t init; /**< CRC required parameters */ + uint8_t *cal_buf; /**< The pointer of preparing buffer */ + uint32_t *cal_res; /**< The pointer of result */ #ifdef ALD_DMA - dma_handle_t hdma; /**< CRC DMA handle parameters */ + dma_handle_t hdma; /**< CRC DMA handle parameters */ #endif - lock_state_t lock; /**< Locking object */ - crc_state_t state; /**< CRC operation state */ + lock_state_t lock; /**< Locking object */ + crc_state_t state; /**< CRC operation state */ - void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */ - void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */ + void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */ + void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */ } crc_handle_t; /** * @} @@ -131,9 +125,9 @@ typedef struct crc_handle_s */ #define IS_CRC(x) ((x) == CRC) #define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \ - ((x) == CRC_MODE_8) || \ - ((x) == CRC_MODE_16) || \ - ((x) == CRC_MODE_32)) + ((x) == CRC_MODE_8) || \ + ((x) == CRC_MODE_16) || \ + ((x) == CRC_MODE_32)) /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h index 18340558a2d5e6b2c805d2b2035025bcec1b3e6a..483c15a31e674030fe34830bdb712c43238392db 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h @@ -18,7 +18,7 @@ #define __ALD_CRYPT_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -39,105 +39,96 @@ extern "C" { /** * @brief CRYPT encrypt or decrypt select */ -typedef enum -{ - CRYPT_DECRYPT = 0, /**< Decrypt */ - CRYPT_ENCRYPT = 1, /**< Encrypt */ +typedef enum { + CRYPT_DECRYPT = 0U, /**< Decrypt */ + CRYPT_ENCRYPT = 1U, /**< Encrypt */ } crypt_encs_t; /** * @brief CRYPT mode select */ -typedef enum -{ - CRYPT_MODE_ECB = 0, /**< ECB */ - CRYPT_MODE_CBC = 1, /**< CBC */ - CRYPT_MODE_CTR = 2, /**< CTR */ +typedef enum { + CRYPT_MODE_ECB = 0U, /**< ECB */ + CRYPT_MODE_CBC = 1U, /**< CBC */ + CRYPT_MODE_CTR = 2U, /**< CTR */ } crypt_mode_t; /** * @brief CRYPT data type */ -typedef enum -{ - CRYPT_DATA_CHANGE_NO = 0, /**< No exchange */ - CRYPT_DATA_CHANGE_16 = 1, /**< 16bit exchange */ - CRYPT_DATA_CHANGE_8 = 2, /**< 8bit exchange */ - CRYPT_DATA_CHANGE_1 = 3, /**< 1bit exchange */ +typedef enum { + CRYPT_DATA_CHANGE_NO = 0U, /**< No exchange */ + CRYPT_DATA_CHANGE_16 = 1U, /**< 16bit exchange */ + CRYPT_DATA_CHANGE_8 = 2U, /**< 8bit exchange */ + CRYPT_DATA_CHANGE_1 = 3U, /**< 1bit exchange */ } crypt_datatype_t; /** * @brief CRYPT interrupt */ -typedef enum -{ - CRYPT_IT_IT = 0x80, /**< Interrupt */ +typedef enum { + CRYPT_IT_IT = 0x80U, /**< Interrupt */ } crypt_it_t; /** * @brief CRYPT interrupt flag */ -typedef enum -{ - CRYPT_FLAG_AESIF = 0x1, /**< Aes flag */ - CRYPT_FLAG_DONE = 0x100, /**< Complete flag */ +typedef enum { + CRYPT_FLAG_AESIF = 0x1U, /**< Aes flag */ + CRYPT_FLAG_DONE = 0x100U, /**< Complete flag */ } crypt_flag_t; /** * @brief CRYPT state structures definition */ -typedef enum -{ - CRYPT_STATE_RESET = 0x0, /**< Peripheral is not initialized */ - CRYPT_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - CRYPT_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - CRYPT_STATE_ERROR = 0x4, /**< Error */ +typedef enum { + CRYPT_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ + CRYPT_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + CRYPT_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + CRYPT_STATE_ERROR = 0x4U, /**< Error */ } crypt_state_t; /** * @brief CRYPT data type */ -typedef enum -{ - DATA_32_BIT = 0, /**< 32 bit data,don't swap */ - DATA_16_BIT = 1, /**< 16 bit data,swap */ - DATA_8_BIT = 2, /**< 8 bit data,swap */ - DATA_1_BIT = 3, /**< 1 bit data, swap */ +typedef enum { + DATA_32_BIT = 0U, /**< 32 bit data,don't swap */ + DATA_16_BIT = 1U, /**< 16 bit data,swap */ + DATA_8_BIT = 2U, /**< 8 bit data,swap */ + DATA_1_BIT = 3U, /**< 1 bit data, swap */ } crypt_data_t; /** * @brief CRYPT init structure definition */ -typedef struct -{ - crypt_mode_t mode; /**< Crypt mode */ - crypt_data_t type; /**< Data type select */ +typedef struct { + crypt_mode_t mode; /**< Crypt mode */ + crypt_data_t type; /**< Data type select */ } crypt_init_t; /** * @brief CRYPT Handle Structure definition */ -typedef struct crypt_handle_s -{ - CRYPT_TypeDef *perh; /**< Register base address */ - crypt_init_t init; /**< CRYPT required parameters */ +typedef struct crypt_handle_s { + CRYPT_TypeDef *perh; /**< Register base address */ + crypt_init_t init; /**< CRYPT required parameters */ #ifdef ALD_DMA - dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */ - dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */ + dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */ + dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */ #endif - uint8_t *plain_text; /**< Pointer to plain text */ - uint8_t *cipher_text; /**< Pointer to cipher text */ - uint32_t size; /**< The size of crypt data buf */ - uint32_t count; /**< The count of crypt data buf */ - uint32_t step; /**< The step of once crypt 4(aes) */ - uint32_t dir; /**< ENCRYPT or DECRYPT */ - uint32_t iv[4]; /**< The iv of crypt */ - uint32_t key[4]; /**< The key of crypt */ - lock_state_t lock; /**< Locking object */ - crypt_state_t state; /**< CRYPT operation state */ - - void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */ - void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */ + uint8_t *plain_text; /**< Pointer to plain text */ + uint8_t *cipher_text; /**< Pointer to cipher text */ + uint32_t size; /**< The size of crypt data buf */ + uint32_t count; /**< The count of crypt data buf */ + uint32_t step; /**< The step of once crypt 4(aes) */ + uint32_t dir; /**< ENCRYPT or DECRYPT */ + uint32_t iv[4]; /**< The iv of crypt */ + uint32_t key[4]; /**< The key of crypt */ + lock_state_t lock; /**< Locking object */ + crypt_state_t state; /**< CRYPT operation state */ + + void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */ + void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */ } crypt_handle_t; /** * @} @@ -148,7 +139,7 @@ typedef struct crypt_handle_s */ #define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK)) #define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) -#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) +#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) #define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) #define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) #define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) @@ -156,7 +147,7 @@ typedef struct crypt_handle_s #define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) #define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) #define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \ - (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0) + (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0) #define CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data)) #define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO) /** @@ -168,13 +159,13 @@ typedef struct crypt_handle_s */ #define IS_CRYPT(x) ((x) == CRYPT) #define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \ - ((x) == CRYPT_MODE_CBC) || \ - ((x) == CRYPT_MODE_CTR)) + ((x) == CRYPT_MODE_CBC) || \ + ((x) == CRYPT_MODE_CTR)) #define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT) #define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \ - ((x) == CRYPT_FLAG_DONE)) + ((x) == CRYPT_FLAG_DONE)) #define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \ - ((x) == IV_4_LEN)) + ((x) == IV_4_LEN)) /** * @} */ @@ -205,9 +196,9 @@ ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); #ifdef ALD_DMA ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, - uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); + uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, - uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); + uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); #endif /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h index 31b8dc6ca40a811eca70ef4dd86608feec96534b..3f695b7e8f477a5949dcb331ecf9293e27a35c4f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h @@ -18,7 +18,7 @@ #define __ALD_DBGC_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -41,34 +41,32 @@ extern "C" { /** * @brief Debug mode select */ -typedef enum -{ - DEBC_MODE_SLEEP = (1u << 0), /**< Sleep mode */ - DEBC_MODE_STOP1 = (1u << 1), /**< STOP1 mode */ - DEBC_MODE_STOP2 = (1u << 2), /**< STOP2 mode */ - DEBC_MODE_STANDBY = (1u << 3), /**< Standby mode */ +typedef enum { + DEBC_MODE_SLEEP = (1U << 0), /**< Sleep mode */ + DEBC_MODE_STOP1 = (1U << 1), /**< STOP1 mode */ + DEBC_MODE_STOP2 = (1U << 2), /**< STOP2 mode */ + DEBC_MODE_STANDBY = (1U << 3), /**< Standby mode */ } dbgc_mode_t; /** * @brief Debug peripheral select */ -typedef enum -{ - DEBC_PERH_TIMER0 = (1u << 0), /**< AD16C4T0 */ - DEBC_PERH_TIMER1 = (1u << 1), /**< BS16T0 */ - DEBC_PERH_TIMER2 = (1u << 2), /**< GP16C2T0 */ - DEBC_PERH_TIMER3 = (1u << 3), /**< GP16C2T1 */ - DEBC_PERH_TIMER4 = (1u << 4), /**< BS16T1 */ - DEBC_PERH_TIMER5 = (1u << 5), /**< BS16T2 */ - DEBC_PERH_TIMER6 = (1u << 6), /**< GP16C4T0 */ - DEBC_PERH_TIMER7 = (1u << 7), /**< BS16T3 */ - DEBC_PERH_I2C0 = (1u << 8), /**< I2C0 SMBUS */ - DEBC_PERH_I2C1 = (1u << 9), /**< I2C1 SMBUS */ - DEBC_PERH_CAN = (1u << 12), /**< CAN */ - DEBC_PERH_LPTIM0 = (1u << 0) | (1u << 16), /**< LPTIM0 */ - DEBC_PERH_IWDT = (1u << 8) | (1u << 16), /**< IWDT */ - DEBC_PERH_WWDT = (1u << 9) | (1u << 16), /**< WWDT */ - DEBC_PERH_RTC = (1u << 10) | (1u << 16), /**< RTC */ +typedef enum { + DEBC_PERH_TIMER0 = (1U << 0), /**< AD16C4T0 */ + DEBC_PERH_TIMER1 = (1U << 1), /**< BS16T0 */ + DEBC_PERH_TIMER2 = (1U << 2), /**< GP16C2T0 */ + DEBC_PERH_TIMER3 = (1U << 3), /**< GP16C2T1 */ + DEBC_PERH_TIMER4 = (1U << 4), /**< BS16T1 */ + DEBC_PERH_TIMER5 = (1U << 5), /**< BS16T2 */ + DEBC_PERH_TIMER6 = (1U << 6), /**< GP16C4T0 */ + DEBC_PERH_TIMER7 = (1U << 7), /**< BS16T3 */ + DEBC_PERH_I2C0 = (1U << 8), /**< I2C0 SMBUS */ + DEBC_PERH_I2C1 = (1U << 9), /**< I2C1 SMBUS */ + DEBC_PERH_CAN = (1U << 12), /**< CAN */ + DEBC_PERH_LPTIM0 = (1U << 0) | (1U << 16), /**< LPTIM0 */ + DEBC_PERH_IWDT = (1U << 8) | (1U << 16), /**< IWDT */ + DEBC_PERH_WWDT = (1U << 9) | (1U << 16), /**< WWDT */ + DEBC_PERH_RTC = (1U << 10) | (1U << 16), /**< RTC */ } dbgc_perh_t; /** * @} @@ -83,7 +81,7 @@ typedef enum */ __INLINE uint32_t ald_dbgc_get_rev_id(void) { - return (DBGC->IDCODE >> 16); + return (DBGC->IDCODE >> 16); } /** @@ -92,7 +90,7 @@ __INLINE uint32_t ald_dbgc_get_rev_id(void) */ __INLINE uint32_t ald_dbgc_get_core_id(void) { - return (DBGC->IDCODE >> 12) & 0xF; + return (DBGC->IDCODE >> 12) & 0xF; } /** @@ -101,7 +99,7 @@ __INLINE uint32_t ald_dbgc_get_core_id(void) */ __INLINE uint32_t ald_dbgc_get_device_id(void) { - return DBGC->IDCODE & 0xFFF; + return DBGC->IDCODE & 0xFFF; } /** @@ -112,10 +110,10 @@ __INLINE uint32_t ald_dbgc_get_device_id(void) */ __INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state) { - if (state) - SET_BIT(DBGC->CR, mode); - else - CLEAR_BIT(DBGC->CR, mode); + if (state) + SET_BIT(DBGC->CR, mode); + else + CLEAR_BIT(DBGC->CR, mode); } /** @@ -126,20 +124,18 @@ __INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state) */ __INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state) { - if ((perh >> 16) & 0x1) - { - if (state) - SET_BIT(DBGC->APB2FZ, perh); - else - CLEAR_BIT(DBGC->APB2FZ, perh); - } - else - { - if (state) - SET_BIT(DBGC->APB1FZ, perh); - else - CLEAR_BIT(DBGC->APB1FZ, perh); - } + if ((perh >> 16) & 0x1) { + if (state) + SET_BIT(DBGC->APB2FZ, perh); + else + CLEAR_BIT(DBGC->APB2FZ, perh); + } + else { + if (state) + SET_BIT(DBGC->APB1FZ, perh); + else + CLEAR_BIT(DBGC->APB1FZ, perh); + } } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h index 364f9e16cb40498c8e85e6deeb80c3b4a1afd769..1fbebd56bf2bf2da37dc11be653d1287beb041da 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h @@ -18,7 +18,7 @@ #define __ALD_DMA_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -36,8 +36,8 @@ extern "C" { * @defgroup DMA_Public_Macros DMA Public Macros * @{ */ -#define DMA_CH_COUNT 6 -#define DMA_ERR 31 +#define DMA_CH_COUNT 6U +#define DMA_ERR 31U /** * @} */ @@ -49,257 +49,260 @@ extern "C" { /** * @brief Input source to DMA channel - * @note ES32F065x: - * AD16C4T0--TIMER0 - * GP16C4T0--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - * - * ES32F033x: - * ES32F093x: - * GP16C4T0--TIMER0 - * GP16C4T1--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 + * @verbatim + In this module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F065x series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + TIMER4 ----> BS16T1 + TIMER5 ----> BS16T2 + TIMER6 ----> GP16C4T0 + TIMER7 ----> BS16T3 + + 2. For ES32F033x/ES32F093x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + TIMER4 ----> BS16T1 + TIMER5 ----> BS16T2 + TIMER6 ----> GP16C4T1 + TIMER7 ----> BS16T3 + @endverbatim */ -typedef enum -{ - DMA_MSEL_NONE = 0x0, /**< NONE */ - DMA_MSEL_GPIO = 0x1, /**< GPIO */ - DMA_MSEL_CRYPT = 0x2, /**< CRYPT */ - DMA_MSEL_ACMP = 0x3, /**< ACMP */ - DMA_MSEL_DAC0 = 0x4, /**< DAC0 */ - DMA_MSEL_ADC0 = 0x6, /**< ADC0 */ - DMA_MSEL_CRC = 0x7, /**< CRC */ - DMA_MSEL_UART0 = 0x8, /**< UART0 */ - DMA_MSEL_UART1 = 0x9, /**< UART1 */ - DMA_MSEL_UART2 = 0xA, /**< UART2 */ - DMA_MSEL_UART3 = 0xB, /**< UART3 */ - DMA_MSEL_USART0 = 0xC, /**< USART0 */ - DMA_MSEL_USART1 = 0xD, /**< USART1 */ - DMA_MSEL_SPI0 = 0xE, /**< SPI0 */ - DMA_MSEL_SPI1 = 0xF, /**< SPI1 */ - DMA_MSEL_I2C0 = 0x10, /**< I2C0 */ - DMA_MSEL_I2C1 = 0x11, /**< I2C1 */ - DMA_MSEL_TIMER0 = 0x12, /**< TIMER0 */ - DMA_MSEL_TIMER1 = 0x13, /**< TIMER1 */ - DMA_MSEL_TIMER2 = 0x14, /**< TIMER2 */ - DMA_MSEL_TIMER3 = 0x15, /**< TIMER3 */ - DMA_MSEL_RTC = 0x16, /**< RTC */ - DMA_MSEL_LPTIM0 = 0x17, /**< LPTIM0 */ - DMA_MSEL_LPUART0 = 0x18, /**< LPUART0 */ - DMA_MSEL_DMA = 0x19, /**< DMA */ - DMA_MSEL_SPI2 = 0x1A, /**< SPI2 */ - DMA_MSEL_TIMER4 = 0x1B, /**< TIMER4 */ - DMA_MSEL_TIMER5 = 0x1C, /**< TIMER5 */ - DMA_MSEL_TIMER6 = 0x1D, /**< TIMER6 */ - DMA_MSEL_TIMER7 = 0x1E, /**< TIMER7 */ - DMA_MSEL_ADC1 = 0x1F, /**< ADC1 */ - DMA_MSEL_PIS = 0x20, /**< PIS */ - DMA_MSEL_TRNG = 0x21, /**< TRNG */ +typedef enum { + DMA_MSEL_NONE = 0x0U, /**< NONE */ + DMA_MSEL_GPIO = 0x1U, /**< GPIO */ + DMA_MSEL_CRYPT = 0x2U, /**< CRYPT */ + DMA_MSEL_ACMP = 0x3U, /**< ACMP */ + DMA_MSEL_DAC0 = 0x4U, /**< DAC0 */ + DMA_MSEL_ADC0 = 0x6U, /**< ADC0 */ + DMA_MSEL_CRC = 0x7U, /**< CRC */ + DMA_MSEL_UART0 = 0x8U, /**< UART0 */ + DMA_MSEL_UART1 = 0x9U, /**< UART1 */ + DMA_MSEL_UART2 = 0xAU, /**< UART2 */ + DMA_MSEL_UART3 = 0xBU, /**< UART3 */ + DMA_MSEL_USART0 = 0xCU, /**< USART0 */ + DMA_MSEL_USART1 = 0xDU, /**< USART1 */ + DMA_MSEL_SPI0 = 0xEU, /**< SPI0 */ + DMA_MSEL_SPI1 = 0xFU, /**< SPI1 */ + DMA_MSEL_I2C0 = 0x10U, /**< I2C0 */ + DMA_MSEL_I2C1 = 0x11U, /**< I2C1 */ + DMA_MSEL_TIMER0 = 0x12U, /**< TIMER0 */ + DMA_MSEL_TIMER1 = 0x13U, /**< TIMER1 */ + DMA_MSEL_TIMER2 = 0x14U, /**< TIMER2 */ + DMA_MSEL_TIMER3 = 0x15U, /**< TIMER3 */ + DMA_MSEL_RTC = 0x16U, /**< RTC */ + DMA_MSEL_LPTIM0 = 0x17U, /**< LPTIM0 */ + DMA_MSEL_LPUART0 = 0x18U, /**< LPUART0 */ + DMA_MSEL_DMA = 0x19U, /**< DMA */ + DMA_MSEL_SPI2 = 0x1AU, /**< SPI2 */ + DMA_MSEL_TIMER4 = 0x1BU, /**< TIMER4 */ + DMA_MSEL_TIMER5 = 0x1CU, /**< TIMER5 */ + DMA_MSEL_TIMER6 = 0x1DU, /**< TIMER6 */ + DMA_MSEL_TIMER7 = 0x1EU, /**< TIMER7 */ + DMA_MSEL_ADC1 = 0x1FU, /**< ADC1 */ + DMA_MSEL_PIS = 0x20U, /**< PIS */ + DMA_MSEL_TRNG = 0x21U, /**< TRNG */ } dma_msel_t; /** * @brief Input signal to DMA channel */ -typedef enum -{ - DMA_MSIGSEL_NONE = 0x0, /**< NONE */ - DMA_MSIGSEL_EXTI_0 = 0x0, /**< External interrupt 0 */ - DMA_MSIGSEL_EXTI_1 = 0x1, /**< External interrupt 1 */ - DMA_MSIGSEL_EXTI_2 = 0x2, /**< External interrupt 2 */ - DMA_MSIGSEL_EXTI_3 = 0x3, /**< External interrupt 3 */ - DMA_MSIGSEL_EXTI_4 = 0x4, /**< External interrupt 4 */ - DMA_MSIGSEL_EXTI_5 = 0x5, /**< External interrupt 5 */ - DMA_MSIGSEL_EXTI_6 = 0x6, /**< External interrupt 6 */ - DMA_MSIGSEL_EXTI_7 = 0x7, /**< External interrupt 7 */ - DMA_MSIGSEL_EXTI_8 = 0x8, /**< External interrupt 8 */ - DMA_MSIGSEL_EXTI_9 = 0x9, /**< External interrupt 9 */ - DMA_MSIGSEL_EXTI_10 = 0xA, /**< External interrupt 10 */ - DMA_MSIGSEL_EXTI_11 = 0xB, /**< External interrupt 11 */ - DMA_MSIGSEL_EXTI_12 = 0xC, /**< External interrupt 12 */ - DMA_MSIGSEL_EXTI_13 = 0xD, /**< External interrupt 13 */ - DMA_MSIGSEL_EXTI_14 = 0xE, /**< External interrupt 14 */ - DMA_MSIGSEL_EXTI_15 = 0xF, /**< External interrupt 15 */ - DMA_MSIGSEL_CRYPT_WRITE = 0x0, /**< CRYPT write mode */ - DMA_MSIGSEL_CRYPT_READ = 0x1, /**< CRYPT read mode */ - DMA_MSIGSEL_CALC_WRITE = 0x0, /**< CALC write mode */ - DMA_MSIGSEL_CALC_READ = 0x1, /**< CALC read mode */ - DMA_MSIGSEL_DAC0_CH0 = 0x0, /**< DAC0 channel 0 complete */ - DMA_MSIGSEL_DAC0_CH1 = 0x1, /**< DAC0 channel 1 complete */ - DMA_MSIGSEL_ADC = 0x0, /**< ADC mode */ - DMA_MSIGSEL_UART_TXEMPTY = 0x0, /**< UART transmit */ - DMA_MSIGSEL_UART_RNR = 0x1, /**< UART receive */ - DMA_MSIGSEL_USART_RNR = 0x0, /**< USART reveive */ - DMA_MSIGSEL_USART_TXEMPTY = 0x1, /**< USART transmit */ - DMA_MSIGSEL_SPI_RNR = 0x0, /**< SPI receive */ - DMA_MSIGSEL_SPI_TXEMPTY = 0x1, /**< SPI transmit */ - DMA_MSIGSEL_I2C_RNR = 0x0, /**< I2C receive */ - DMA_MSIGSEL_I2C_TXEMPTY = 0x1, /**< I2C transmit */ - DMA_MSIGSEL_TIMER_CH1 = 0x0, /**< TIM channal 1 */ - DMA_MSIGSEL_TIMER_CH2 = 0x1, /**< TIM channal 2 */ - DMA_MSIGSEL_TIMER_CH3 = 0x2, /**< TIM channal 3 */ - DMA_MSIGSEL_TIMER_CH4 = 0x3, /**< TIM channal 4 */ - DMA_MSIGSEL_TIMER_TRI = 0x4, /**< TIM trigger */ - DMA_MSIGSEL_TIMER_COMP = 0x5, /**< TIM compare */ - DMA_MSIGSEL_TIMER_UPDATE = 0x6, /**< TIM update */ - DMA_MSIGSEL_LPUART_RNR = 0x0, /**< LPUART receive */ - DMA_MSIGSEL_LPUART_TXEMPTY = 0x1, /**< LPUART transmit */ - DMA_MSIGSEL_PIS_CH0 = 0x0, /**< PIS channal 0 */ - DMA_MSIGSEL_PIS_CH1 = 0x1, /**< PIS channal 1 */ - DMA_MSIGSEL_PIS_CH2 = 0x2, /**< PIS channal 2 */ - DMA_MSIGSEL_PIS_CH3 = 0x3, /**< PIS channal 3 */ - DMA_MSIGSEL_PIS_CH4 = 0x4, /**< PIS channal 4 */ - DMA_MSIGSEL_PIS_CH5 = 0x5, /**< PIS channal 5 */ - DMA_MSIGSEL_PIS_CH6 = 0x6, /**< PIS channal 6 */ - DMA_MSIGSEL_PIS_CH7 = 0x7, /**< PIS channal 7 */ - DMA_MSIGSEL_PIS_CH8 = 0x8, /**< PIS channal 8 */ - DMA_MSIGSEL_PIS_CH9 = 0x9, /**< PIS channal 9 */ - DMA_MSIGSEL_PIS_CH10 = 0xA, /**< PIS channal 10 */ - DMA_MSIGSEL_PIS_CH11 = 0xB, /**< PIS channal 11 */ - DMA_MSIGSEL_PIS_CH12 = 0xC, /**< PIS channal 12 */ - DMA_MSIGSEL_PIS_CH13 = 0xD, /**< PIS channal 13 */ - DMA_MSIGSEL_PIS_CH14 = 0xE, /**< PIS channal 14 */ - DMA_MSIGSEL_PIS_CH15 = 0xF, /**< PIS channal 15 */ +typedef enum { + DMA_MSIGSEL_NONE = 0x0U, /**< NONE */ + DMA_MSIGSEL_EXTI_0 = 0x0U, /**< External interrupt 0 */ + DMA_MSIGSEL_EXTI_1 = 0x1U, /**< External interrupt 1 */ + DMA_MSIGSEL_EXTI_2 = 0x2U, /**< External interrupt 2 */ + DMA_MSIGSEL_EXTI_3 = 0x3U, /**< External interrupt 3 */ + DMA_MSIGSEL_EXTI_4 = 0x4U, /**< External interrupt 4 */ + DMA_MSIGSEL_EXTI_5 = 0x5U, /**< External interrupt 5 */ + DMA_MSIGSEL_EXTI_6 = 0x6U, /**< External interrupt 6 */ + DMA_MSIGSEL_EXTI_7 = 0x7U, /**< External interrupt 7 */ + DMA_MSIGSEL_EXTI_8 = 0x8U, /**< External interrupt 8 */ + DMA_MSIGSEL_EXTI_9 = 0x9U, /**< External interrupt 9 */ + DMA_MSIGSEL_EXTI_10 = 0xAU, /**< External interrupt 10 */ + DMA_MSIGSEL_EXTI_11 = 0xBU, /**< External interrupt 11 */ + DMA_MSIGSEL_EXTI_12 = 0xCU, /**< External interrupt 12 */ + DMA_MSIGSEL_EXTI_13 = 0xDU, /**< External interrupt 13 */ + DMA_MSIGSEL_EXTI_14 = 0xEU, /**< External interrupt 14 */ + DMA_MSIGSEL_EXTI_15 = 0xFU, /**< External interrupt 15 */ + DMA_MSIGSEL_CRYPT_WRITE = 0x0U, /**< CRYPT write mode */ + DMA_MSIGSEL_CRYPT_READ = 0x1U, /**< CRYPT read mode */ + DMA_MSIGSEL_CALC_WRITE = 0x0U, /**< CALC write mode */ + DMA_MSIGSEL_CALC_READ = 0x1U, /**< CALC read mode */ + DMA_MSIGSEL_DAC0_CH0 = 0x0U, /**< DAC0 channel 0 complete */ + DMA_MSIGSEL_DAC0_CH1 = 0x1U, /**< DAC0 channel 1 complete */ + DMA_MSIGSEL_ADC = 0x0U, /**< ADC mode */ + DMA_MSIGSEL_UART_TXEMPTY = 0x0U, /**< UART transmit */ + DMA_MSIGSEL_UART_RNR = 0x1U, /**< UART receive */ + DMA_MSIGSEL_USART_RNR = 0x0U, /**< USART reveive */ + DMA_MSIGSEL_USART_TXEMPTY = 0x1U, /**< USART transmit */ + DMA_MSIGSEL_SPI_RNR = 0x0U, /**< SPI receive */ + DMA_MSIGSEL_SPI_TXEMPTY = 0x1U, /**< SPI transmit */ + DMA_MSIGSEL_I2C_RNR = 0x0U, /**< I2C receive */ + DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, /**< I2C transmit */ + DMA_MSIGSEL_TIMER_CH1 = 0x0U, /**< TIM channal 1 */ + DMA_MSIGSEL_TIMER_CH2 = 0x1U, /**< TIM channal 2 */ + DMA_MSIGSEL_TIMER_CH3 = 0x2U, /**< TIM channal 3 */ + DMA_MSIGSEL_TIMER_CH4 = 0x3U, /**< TIM channal 4 */ + DMA_MSIGSEL_TIMER_TRI = 0x4U, /**< TIM trigger */ + DMA_MSIGSEL_TIMER_COMP = 0x5U, /**< TIM compare */ + DMA_MSIGSEL_TIMER_UPDATE = 0x6U, /**< TIM update */ + DMA_MSIGSEL_LPUART_RNR = 0x0U, /**< LPUART receive */ + DMA_MSIGSEL_LPUART_TXEMPTY = 0x1U, /**< LPUART transmit */ + DMA_MSIGSEL_PIS_CH0 = 0x0U, /**< PIS channal 0 */ + DMA_MSIGSEL_PIS_CH1 = 0x1U, /**< PIS channal 1 */ + DMA_MSIGSEL_PIS_CH2 = 0x2U, /**< PIS channal 2 */ + DMA_MSIGSEL_PIS_CH3 = 0x3U, /**< PIS channal 3 */ + DMA_MSIGSEL_PIS_CH4 = 0x4U, /**< PIS channal 4 */ + DMA_MSIGSEL_PIS_CH5 = 0x5U, /**< PIS channal 5 */ + DMA_MSIGSEL_PIS_CH6 = 0x6U, /**< PIS channal 6 */ + DMA_MSIGSEL_PIS_CH7 = 0x7U, /**< PIS channal 7 */ + DMA_MSIGSEL_PIS_CH8 = 0x8U, /**< PIS channal 8 */ + DMA_MSIGSEL_PIS_CH9 = 0x9U, /**< PIS channal 9 */ + DMA_MSIGSEL_PIS_CH10 = 0xAU, /**< PIS channal 10 */ + DMA_MSIGSEL_PIS_CH11 = 0xBU, /**< PIS channal 11 */ + DMA_MSIGSEL_PIS_CH12 = 0xCU, /**< PIS channal 12 */ + DMA_MSIGSEL_PIS_CH13 = 0xDU, /**< PIS channal 13 */ + DMA_MSIGSEL_PIS_CH14 = 0xEU, /**< PIS channal 14 */ + DMA_MSIGSEL_PIS_CH15 = 0xFU, /**< PIS channal 15 */ } dma_msigsel_t; /** * @brief DMA Descriptor control type */ -typedef union -{ - struct - { - uint32_t cycle_ctrl : 3; /**< DMA operating mode @ref dma_cycle_ctrl_t */ - uint32_t next_useburst : 1; /**< Uses the alternate data structure when complete a DMA cycle */ - uint32_t n_minus_1 : 10; /**< Represent the total number of DMA transfers that DMA cycle contains. */ - uint32_t R_power : 4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ - uint32_t src_prot_ctrl : 3; /**< Control the state of HPROT when reads the source data. */ - uint32_t dst_prot_ctrl : 3; /**< Control the state of HPROT when writes the destination data */ - uint32_t src_size : 2; /**< Source data size @ref dma_data_size_t */ - uint32_t src_inc : 2; /**< Control the source address increment. @ref dma_data_inc_t */ - uint32_t dst_size : 2; /**< Destination data size. @ref dma_data_size_t */ - uint32_t dst_inc : 2; /**< Destination address increment. @ref dma_data_inc_t */ - }; - uint32_t word; +typedef union { + struct { + uint32_t cycle_ctrl :3; /**< DMA operating mode @ref dma_cycle_ctrl_t */ + uint32_t next_useburst :1; /**< Uses the alternate data structure when complete a DMA cycle */ + uint32_t n_minus_1 :10; /**< Represent the total number of DMA transfers that DMA cycle contains. */ + uint32_t R_power :4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ + uint32_t src_prot_ctrl :3; /**< Control the state of HPROT when reads the source data. */ + uint32_t dst_prot_ctrl :3; /**< Control the state of HPROT when writes the destination data */ + uint32_t src_size :2; /**< Source data size @ref dma_data_size_t */ + uint32_t src_inc :2; /**< Control the source address increment. @ref dma_data_inc_t */ + uint32_t dst_size :2; /**< Destination data size. @ref dma_data_size_t */ + uint32_t dst_inc :2; /**< Destination address increment. @ref dma_data_inc_t */ + }; + uint32_t word; } dma_ctrl_t; /** * @brief Channel control data structure */ -typedef struct -{ - void *src; /**< Source data end pointer */ - void *dst; /**< Destination data end pointer */ - dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */ - uint32_t use; /**< Reserve for user */ +typedef struct { + void *src; /**< Source data end pointer */ + void *dst; /**< Destination data end pointer */ + dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */ + uint32_t use; /**< Reserve for user */ } dma_descriptor_t; /** * @brief data increment */ -typedef enum -{ - DMA_DATA_INC_BYTE = 0x0, /**< Address increment by byte */ - DMA_DATA_INC_HALFWORD = 0x1, /**< Address increment by halfword */ - DMA_DATA_INC_WORD = 0x2, /**< Address increment by word */ - DMA_DATA_INC_NONE = 0x3, /**< No increment */ +typedef enum { + DMA_DATA_INC_BYTE = 0x0U, /**< Address increment by byte */ + DMA_DATA_INC_HALFWORD = 0x1U, /**< Address increment by halfword */ + DMA_DATA_INC_WORD = 0x2U, /**< Address increment by word */ + DMA_DATA_INC_NONE = 0x3U, /**< No increment */ } dma_data_inc_t; /** * @brief Data size */ -typedef enum -{ - DMA_DATA_SIZE_BYTE = 0x0, /**< Byte */ - DMA_DATA_SIZE_HALFWORD = 0x1, /**< Halfword */ - DMA_DATA_SIZE_WORD = 0x2, /**< Word */ +typedef enum { + DMA_DATA_SIZE_BYTE = 0x0U, /**< Byte */ + DMA_DATA_SIZE_HALFWORD = 0x1U, /**< Halfword */ + DMA_DATA_SIZE_WORD = 0x2U, /**< Word */ } dma_data_size_t; /** * @brief The operating mode of the DMA cycle */ -typedef enum -{ - DMA_CYCLE_CTRL_NONE = 0x0, /**< Stop */ - DMA_CYCLE_CTRL_BASIC = 0x1, /**< Basic */ - DMA_CYCLE_CTRL_AUTO = 0x2, /**< Auto-request */ - DMA_CYCLE_CTRL_PINGPONG = 0x3, /**< Ping-pong */ - DMA_CYCLE_CTRL_MEM_SCATTER_GATHER = 0x4, /**< Memory scatter/gather */ - DMA_CYCLE_CTRL_PER_SCATTER_GATHER = 0x6, /**< Peripheral scatter/gather */ +typedef enum { + DMA_CYCLE_CTRL_NONE = 0x0U, /**< Stop */ + DMA_CYCLE_CTRL_BASIC = 0x1U, /**< Basic */ + DMA_CYCLE_CTRL_AUTO = 0x2U, /**< Auto-request */ + DMA_CYCLE_CTRL_PINGPONG = 0x3U, /**< Ping-pong */ + DMA_CYCLE_CTRL_MEM_SG_PRIMARY = 0x4U, /**< Memory scatter-gather using the primary structure */ + DMA_CYCLE_CTRL_MEM_SG_ALTERNATE = 0x5U, /**< Memory scatter-gather using the alternate structure */ + DMA_CYCLE_CTRL_PER_SG_PRIMARY = 0x6U, /**< Peripheral scatter-gather using the primary structure */ + DMA_CYCLE_CTRL_PER_SG_ALTERNATE = 0x7U, /**< Peripheral scatter-gather using the alternate structure */ } dma_cycle_ctrl_t; /** * @brief Control how many DMA transfers can occur * before the controller re-arbitrates */ -typedef enum -{ - DMA_R_POWER_1 = 0x0, /**< Arbitrates after each DMA transfer */ - DMA_R_POWER_2 = 0x1, /**< Arbitrates after 2 DMA transfer */ - DMA_R_POWER_4 = 0x2, /**< Arbitrates after 4 DMA transfer */ - DMA_R_POWER_8 = 0x3, /**< Arbitrates after 8 DMA transfer */ - DMA_R_POWER_16 = 0x4, /**< Arbitrates after 16 DMA transfer */ - DMA_R_POWER_32 = 0x5, /**< Arbitrates after 32 DMA transfer */ - DMA_R_POWER_64 = 0x6, /**< Arbitrates after 64 DMA transfer */ - DMA_R_POWER_128 = 0x7, /**< Arbitrates after 128 DMA transfer */ - DMA_R_POWER_256 = 0x8, /**< Arbitrates after 256 DMA transfer */ - DMA_R_POWER_512 = 0x9, /**< Arbitrates after 512 DMA transfer */ - DMA_R_POWER_1024 = 0xA, /**< Arbitrates after 1024 DMA transfer */ +typedef enum { + DMA_R_POWER_1 = 0x0U, /**< Arbitrates after each DMA transfer */ + DMA_R_POWER_2 = 0x1U, /**< Arbitrates after 2 DMA transfer */ + DMA_R_POWER_4 = 0x2U, /**< Arbitrates after 4 DMA transfer */ + DMA_R_POWER_8 = 0x3U, /**< Arbitrates after 8 DMA transfer */ + DMA_R_POWER_16 = 0x4U, /**< Arbitrates after 16 DMA transfer */ + DMA_R_POWER_32 = 0x5U, /**< Arbitrates after 32 DMA transfer */ + DMA_R_POWER_64 = 0x6U, /**< Arbitrates after 64 DMA transfer */ + DMA_R_POWER_128 = 0x7U, /**< Arbitrates after 128 DMA transfer */ + DMA_R_POWER_256 = 0x8U, /**< Arbitrates after 256 DMA transfer */ + DMA_R_POWER_512 = 0x9U, /**< Arbitrates after 512 DMA transfer */ + DMA_R_POWER_1024 = 0xAU, /**< Arbitrates after 1024 DMA transfer */ } dma_arbiter_config_t; /** * @brief Callback function pointer and param */ -typedef struct -{ - void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ - void (*err_cbk)(void *arg); /**< DMA occurs error callback */ - void *cplt_arg; /**< The parameter of cplt_cbk() */ - void *err_arg; /**< The parameter of err_cbk() */ +typedef struct { + void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*err_cbk)(void* arg); /**< DMA occurs error callback */ + void *cplt_arg; /**< The parameter of cplt_cbk() */ + void *err_arg; /**< The parameter of err_cbk() */ } dma_call_back_t; /** * @brief DMA channal configure structure */ -typedef struct -{ - void *src; /**< Source data begin pointer */ - void *dst; /**< Destination data begin pointer */ - uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ - dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */ - dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */ - dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */ - dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ - type_func_t primary; /**< Use primary descriptor or alternate descriptor */ - type_func_t burst; /**< Uses the alternate data structure when complete a DMA cycle */ - type_func_t high_prio; /**< High priority or default priority */ - type_func_t iterrupt; /**< Enable/disable interrupt */ - dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */ - dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */ - uint8_t channel; /**< Channel index */ +typedef struct { + void *src; /**< Source data begin pointer */ + void *dst; /**< Destination data begin pointer */ + uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ + dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */ + dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */ + dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */ + dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ + type_func_t primary; /**< Use primary descriptor or alternate descriptor */ + type_func_t burst; /**< Enable/Disable the useburst setting for this channel */ + type_func_t high_prio; /**< High priority or default priority */ + type_func_t interrupt; /**< Enable/disable interrupt */ + dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */ + dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */ + uint8_t channel; /**< Channel index */ } dma_config_t; /** * @brief DMA handle structure definition */ -typedef struct -{ - DMA_TypeDef *perh; /**< DMA registers base address */ - dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ - void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ - void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */ - void *cplt_arg; /**< The parameter of cplt_cbk() */ - void *err_arg; /**< The parameter of err_cbk() */ +typedef struct { + DMA_TypeDef *perh; /**< DMA registers base address */ + dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ + void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */ + void *cplt_arg; /**< The parameter of cplt_cbk() */ + void *err_arg; /**< The parameter of err_cbk() */ } dma_handle_t; + +/** + * @brief Descriptor complete state + */ +typedef enum { + DMA_DESCP_CPLT_PRI = 0x0U, /**< Primary descriptor has been completed */ + DMA_DESCP_CPLT_ALT = 0x1U, /**< Alternate descriptor has been completed */ + DMA_DESCP_CPLT_ALL = 0x2U, /**< Both primary and alternate descriptors have been completed */ +} dma_descrp_cplt_t; /** * @} */ @@ -317,12 +320,14 @@ typedef struct #define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \ ((x) == DMA_DATA_SIZE_HALFWORD) || \ ((x) == DMA_DATA_SIZE_WORD)) -#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ - ((x) == DMA_CYCLE_CTRL_BASIC) || \ - ((x) == DMA_CYCLE_CTRL_AUTO) || \ - ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ - ((x) == DMA_CYCLE_CTRL_MEM_SCATTER_GATHER) || \ - ((x) == DMA_CYCLE_CTRL_PER_SCATTER_GATHER)) +#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ + ((x) == DMA_CYCLE_CTRL_BASIC) || \ + ((x) == DMA_CYCLE_CTRL_AUTO) || \ + ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ + ((x) == DMA_CYCLE_CTRL_MEM_SG_PRIMARY) || \ + ((x) == DMA_CYCLE_CTRL_MEM_SG_ALTERNATE) || \ + ((x) == DMA_CYCLE_CTRL_PER_SG_PRIMARY) || \ + ((x) == DMA_CYCLE_CTRL_PER_SG_ALTERNATE)) #define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \ ((x) == DMA_R_POWER_2) || \ ((x) == DMA_R_POWER_4) || \ @@ -354,6 +359,7 @@ typedef struct extern void ald_dma_reset(DMA_TypeDef *DMAx); extern void ald_dma_init(DMA_TypeDef *DMAx); extern void ald_dma_config_struct(dma_config_t *p); +extern void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory); /** * @} */ @@ -366,11 +372,17 @@ extern void ald_dma_config_struct(dma_config_t *p); extern void ald_dma_config_auto(dma_handle_t *hperh); extern void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size); extern void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, - uint16_t size, uint8_t channel, void (*cbk)(void *arg)); + uint16_t size, uint8_t channel, void (*cbk)(void *arg)); extern void ald_dma_config_basic(dma_handle_t *hperh); extern void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size); extern void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, - dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); + dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); +extern void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config, + uint8_t first, void (*cbk)(void *arg)); +extern void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, + uint32_t nr, uint8_t channel, void (*cbk)(void *arg)); +extern void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, + dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); /** * @} */ @@ -384,7 +396,8 @@ extern void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_fu extern it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel); extern flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel); extern void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel); -void ald_dma_irq_handler(void); +extern dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel); +extern void ald_dma_irq_handler(void); /** * @} */ @@ -393,7 +406,6 @@ void ald_dma_irq_handler(void); * @} */ - /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h index 9a4a66b0686fcf6dd519a503252441dc25053be6..8858b8b707fd605d702d32ea63491f19cb0a34a5 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h @@ -36,21 +36,21 @@ extern "C" { * @{ */ #define FLASH_REG_UNLOCK() \ - do { \ - if (op_cmd == OP_FLASH) { \ - WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \ - WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \ - } \ - else { \ - WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \ - WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \ - } \ - } while (0) +do { \ + if (op_cmd == OP_FLASH) { \ + WRITE_REG(MSC->FLASHKEY, 0x8ACE0246U); \ + WRITE_REG(MSC->FLASHKEY, 0x9BDF1357U); \ + } \ + else { \ + WRITE_REG(MSC->INFOKEY, 0x7153BFD9U); \ + WRITE_REG(MSC->INFOKEY, 0x0642CEA8U); \ + } \ +} while (0) #define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) #define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) #define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) #define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) -#define FLASH_BASE_ADDR 0x00000000 +#define FLASH_BASE_ADDR 0x00000000U #define FLASH_PAGE_SIZE 1024UL #define FLASH_WORD_SIZE 8UL #define FLASH_TOTAL_SIZE 256UL @@ -67,9 +67,9 @@ extern "C" { #define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK)) #ifdef USE_FLASH_FIFO -#define FLASH_FIFO 1 + #define FLASH_FIFO 1 #else -#define FLASH_FIFO 0 + #define FLASH_FIFO 0 #endif /** * @} @@ -78,24 +78,22 @@ extern "C" { /** @defgroup FLASH_Private_Types FLASH Private Types * @{ */ -typedef enum -{ - FLASH_CMD_AE = 0x000051AE, /**< Program area erase all */ - FLASH_CMD_PE = 0x00005EA1, /**< Page erase */ - FLASH_CMD_WP = 0x00005DA2, /**< Word program */ - FLASH_CMD_DATAPE = 0x00005BA4, /**< Data flash page page erase */ - FLASH_CMD_DATAWP = 0x00005AA5, /**< Data flash word program */ +typedef enum { + FLASH_CMD_AE = 0x000051AEU, /**< Program area erase all */ + FLASH_CMD_PE = 0x00005EA1U, /**< Page erase */ + FLASH_CMD_WP = 0x00005DA2U, /**< Word program */ + FLASH_CMD_DATAPE = 0x00005BA4U, /**< Data flash page page erase */ + FLASH_CMD_DATAWP = 0x00005AA5U, /**< Data flash word program */ } flash_cmd_type; -typedef enum -{ - OP_FLASH = 0, /**< Operate Pragram area */ - OP_INFO = 1, /**< Operate info area */ +typedef enum { + OP_FLASH = 0U, /**< Operate Pragram area */ + OP_INFO = 1U, /**< Operate info area */ } op_cmd_type; /** * @} - */ + */ /** @addtogroup Flash_Private_Functions * @{ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h index a8a2e9ebe0571b01ebf85abc75c43957e3f85381..336c90f97701ef6fad4ec8d3fdd4a969673d7027 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h @@ -18,7 +18,7 @@ #define __ALD_GPIO_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -52,7 +52,7 @@ extern "C" { #define GPIO_PIN_13 (1U << 13) #define GPIO_PIN_14 (1U << 14) #define GPIO_PIN_15 (1U << 15) -#define GPIO_PIN_ALL (0xFFFF) +#define GPIO_PIN_ALL (0xFFFFU) /** * @} */ @@ -65,125 +65,114 @@ extern "C" { /** * @brief GPIO mode */ -typedef enum -{ - GPIO_MODE_CLOSE = 0x0, /**< Digital close Analog open */ - GPIO_MODE_INPUT = 0x1, /**< Input */ - GPIO_MODE_OUTPUT = 0x2, /**< Output */ +typedef enum { + GPIO_MODE_CLOSE = 0x0U, /**< Digital close Analog open */ + GPIO_MODE_INPUT = 0x1U, /**< Input */ + GPIO_MODE_OUTPUT = 0x2U, /**< Output */ } gpio_mode_t; /** * @brief GPIO open-drain or push-pull */ -typedef enum -{ - GPIO_PUSH_PULL = 0x0, /**< Push-Pull */ - GPIO_OPEN_DRAIN = 0x2, /**< Open-Drain */ - GPIO_OPEN_SOURCE = 0x3, /**< Open-Source */ +typedef enum { + GPIO_PUSH_PULL = 0x0U, /**< Push-Pull */ + GPIO_OPEN_DRAIN = 0x2U, /**< Open-Drain. Can't output high level */ + GPIO_OPEN_SOURCE = 0x3U, /**< Open-Source. Can't output low level */ } gpio_odos_t; /** * @brief GPIO push-up or push-down */ -typedef enum -{ - GPIO_FLOATING = 0x0,/**< Floating */ - GPIO_PUSH_UP = 0x1,/**< Push-Up */ - GPIO_PUSH_DOWN = 0x2,/**< Push-Down */ - GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */ +typedef enum { + GPIO_FLOATING = 0x0U, /**< Floating */ + GPIO_PUSH_UP = 0x1U, /**< Push-Up */ + GPIO_PUSH_DOWN = 0x2U, /**< Push-Down */ + GPIO_PUSH_UP_DOWN = 0x3U, /**< Push-Up and Push-Down */ } gpio_push_t; /** * @brief GPIO output drive */ -typedef enum -{ - GPIO_OUT_DRIVE_NORMAL = 0x0, /**< Normal current flow */ - GPIO_OUT_DRIVE_STRONG = 0x1, /**< Strong current flow */ +typedef enum { + GPIO_OUT_DRIVE_NORMAL = 0x0U, /**< Normal current flow */ + GPIO_OUT_DRIVE_STRONG = 0x1U, /**< Strong current flow */ } gpio_out_drive_t; /** * @brief GPIO filter */ -typedef enum -{ - GPIO_FILTER_DISABLE = 0x0, /**< Disable filter */ - GPIO_FILTER_ENABLE = 0x1, /**< Enable filter */ +typedef enum { + GPIO_FILTER_DISABLE = 0x0U, /**< Disable filter */ + GPIO_FILTER_ENABLE = 0x1U, /**< Enable filter */ } gpio_filter_t; /** * @brief GPIO type */ -typedef enum -{ - GPIO_TYPE_CMOS = 0x0, /**< CMOS Type */ - GPIO_TYPE_TTL = 0x1, /**< TTL Type */ +typedef enum { + GPIO_TYPE_CMOS = 0x0U, /**< CMOS Type */ + GPIO_TYPE_TTL = 0x1U, /**< TTL Type */ } gpio_type_t; /** * @brief GPIO functions */ -typedef enum -{ - GPIO_FUNC_0 = 0, /**< function #0 */ - GPIO_FUNC_1 = 1, /**< function #1 */ - GPIO_FUNC_2 = 2, /**< function #2 */ - GPIO_FUNC_3 = 3, /**< function #3 */ - GPIO_FUNC_4 = 4, /**< function #4 */ - GPIO_FUNC_5 = 5, /**< function #5 */ - GPIO_FUNC_6 = 6, /**< function #6 */ - GPIO_FUNC_7 = 7, /**< function #7 */ +typedef enum { + GPIO_FUNC_0 = 0U, /**< function #0 */ + GPIO_FUNC_1 = 1U, /**< function #1 */ + GPIO_FUNC_2 = 2U, /**< function #2 */ + GPIO_FUNC_3 = 3U, /**< function #3 */ + GPIO_FUNC_4 = 4U, /**< function #4 */ + GPIO_FUNC_5 = 5U, /**< function #5 */ + GPIO_FUNC_6 = 6U, /**< function #6 */ + GPIO_FUNC_7 = 7U, /**< function #7 */ } gpio_func_t; /** * @brief GPIO Init Structure definition */ -typedef struct -{ - gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. +typedef struct { + gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. This parameter can be any value of @ref gpio_mode_t */ - gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins. + gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins. This parameter can be a value of @ref gpio_odos_t */ - gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. + gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. This parameter can be a value of @ref gpio_push_t */ - gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins. + gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins. This parameter can be a value of @ref gpio_out_drive_t */ - gpio_filter_t flt; /**< Specifies the input filter for the selected pins. + gpio_filter_t flt; /**< Specifies the input filter for the selected pins. This parameter can be a value of @ref gpio_filter_t */ - gpio_type_t type; /**< Specifies the type for the selected pins. + gpio_type_t type; /**< Specifies the type for the selected pins. This parameter can be a value of @ref gpio_type_t */ - gpio_func_t func; /**< Specifies the function for the selected pins. + gpio_func_t func; /**< Specifies the function for the selected pins. This parameter can be a value of @ref gpio_func_t */ } gpio_init_t; /** * @brief EXTI trigger style */ -typedef enum -{ - EXTI_TRIGGER_RISING_EDGE = 0, /**< Rising edge trigger */ - EXTI_TRIGGER_TRAILING_EDGE = 1, /**< Trailing edge trigger */ - EXTI_TRIGGER_BOTH_EDGE = 2, /**< Rising and trailing edge trigger */ +typedef enum { + EXTI_TRIGGER_RISING_EDGE = 0U, /**< Rising edge trigger */ + EXTI_TRIGGER_TRAILING_EDGE = 1U, /**< Trailing edge trigger */ + EXTI_TRIGGER_BOTH_EDGE = 2U, /**< Rising and trailing edge trigger */ } exti_trigger_style_t; /** * @brief EXTI filter clock select */ -typedef enum -{ - EXTI_FILTER_CLOCK_10K = 0, /**< cks = 10KHz */ - EXTI_FILTER_CLOCK_32K = 1, /**< cks = 32KHz */ +typedef enum { + EXTI_FILTER_CLOCK_10K = 0U, /**< cks = 10KHz */ + EXTI_FILTER_CLOCK_32K = 1U, /**< cks = 32KHz */ } exti_filter_clock_t; /** * @brief EXTI Init Structure definition */ -typedef struct -{ - type_func_t filter; /**< Enable filter. */ - exti_filter_clock_t cks; /**< Filter clock select. */ - uint8_t filter_time; /**< Filter duration */ +typedef struct { + type_func_t filter; /**< Enable filter. */ + exti_filter_clock_t cks; /**< Filter clock select. */ + uint8_t filter_time; /**< Filter duration */ } exti_init_t; /** * @} @@ -193,37 +182,37 @@ typedef struct * @defgroup GPIO_Private_Macros GPIO Private Macros * @{ */ -#define PIN_MASK 0xFFFF -#define UNLOCK_KEY 0x55AA +#define PIN_MASK 0xFFFFU +#define UNLOCK_KEY 0x55AAU #define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0)) #define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \ - (GPIOx == GPIOB) || \ - (GPIOx == GPIOC) || \ - (GPIOx == GPIOD) || \ - (GPIOx == GPIOE) || \ - (GPIOx == GPIOF) || \ - (GPIOx == GPIOG) || \ - (GPIOx == GPIOH)) + (GPIOx == GPIOB) || \ + (GPIOx == GPIOC) || \ + (GPIOx == GPIOD) || \ + (GPIOx == GPIOE) || \ + (GPIOx == GPIOF) || \ + (GPIOx == GPIOG) || \ + (GPIOx == GPIOH)) #define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \ - ((x) == GPIO_MODE_INPUT) || \ - ((x) == GPIO_MODE_OUTPUT)) + ((x) == GPIO_MODE_INPUT) || \ + ((x) == GPIO_MODE_OUTPUT)) #define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \ - ((x) == GPIO_OPEN_DRAIN) || \ - ((x) == GPIO_OPEN_SOURCE)) + ((x) == GPIO_OPEN_DRAIN) || \ + ((x) == GPIO_OPEN_SOURCE)) #define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \ - ((x) == GPIO_PUSH_UP) || \ - ((x) == GPIO_PUSH_DOWN) || \ - ((x) == GPIO_PUSH_UP_DOWN)) + ((x) == GPIO_PUSH_UP) || \ + ((x) == GPIO_PUSH_DOWN) || \ + ((x) == GPIO_PUSH_UP_DOWN)) #define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_NORMAL) || \ - ((x) == GPIO_OUT_DRIVE_STRONG)) + ((x) == GPIO_OUT_DRIVE_STRONG)) #define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \ - ((x) == GPIO_FILTER_ENABLE)) + ((x) == GPIO_FILTER_ENABLE)) #define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \ - ((x) == GPIO_TYPE_CMOS)) + ((x) == GPIO_TYPE_CMOS)) #define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \ - ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \ - ((x) == EXTI_TRIGGER_BOTH_EDGE)) + ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \ + ((x) == EXTI_TRIGGER_BOTH_EDGE)) #define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \ ((x) == EXTI_FILTER_CLOCK_32K)) #define IS_GPIO_FUNC(x) ((x) <= 7) diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h index a05aaf0ebb357a68831fa28efc094a41bef9601c..f421ff168e0deec6606d21b62f773adf1ccbb6e4 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h @@ -39,111 +39,102 @@ extern "C" { /** * @brief I2C Error Code */ -typedef enum -{ - I2C_ERROR_NONE = 0x0, /**< No error */ - I2C_ERROR_BERR = 0x1, /**< Berr error */ - I2C_ERROR_ARLO = 0x2, /**< Arlo error */ - I2C_ERROR_AF = 0x4, /**< Af error */ - I2C_ERROR_OVR = 0x8, /**< Ovr error */ - I2C_ERROR_DMA = 0x10, /**< Dma error */ - I2C_ERROR_TIMEOUT = 0x20, /**< Timeout error */ +typedef enum { + I2C_ERROR_NONE = 0x0U, /**< No error */ + I2C_ERROR_BERR = 0x1U, /**< Berr error */ + I2C_ERROR_ARLO = 0x2U, /**< Arlo error */ + I2C_ERROR_AF = 0x4U, /**< Af error */ + I2C_ERROR_OVR = 0x8U, /**< Ovr error */ + I2C_ERROR_DMA = 0x10U, /**< Dma error */ + I2C_ERROR_TIMEOUT = 0x20U, /**< Timeout error */ } i2c_error_t; /** * @brief I2C state structure definition */ -typedef enum -{ - I2C_STATE_RESET = 0x0, /**< Peripheral is not yet Initialized */ - I2C_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - I2C_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - I2C_STATE_BUSY_TX = 0x3, /**< Data Transmission process is ongoing */ - I2C_STATE_BUSY_RX = 0x4, /**< Data Reception process is ongoing */ - I2C_STATE_TIMEOUT = 0x5, /**< timeout state */ - I2C_STATE_ERROR = 0x6, /**< Error */ +typedef enum { + I2C_STATE_RESET = 0x0U, /**< Peripheral is not yet Initialized */ + I2C_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + I2C_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + I2C_STATE_BUSY_TX = 0x3U, /**< Data Transmission process is ongoing */ + I2C_STATE_BUSY_RX = 0x4U, /**< Data Reception process is ongoing */ + I2C_STATE_TIMEOUT = 0x5U, /**< timeout state */ + I2C_STATE_ERROR = 0x6U, /**< Error */ } i2c_state_t; /** * @brief I2C Duty Cycle */ -typedef enum -{ - I2C_DUTYCYCLE_2 = 0x0, /**< duty cycle is 2 */ - I2C_DUTYCYCLE_16_9 = 0x4000, /**< duty cycle is 16/9 */ +typedef enum { + I2C_DUTYCYCLE_2 = 0x0U, /**< duty cycle is 2 */ + I2C_DUTYCYCLE_16_9 = 0x4000U, /**< duty cycle is 16/9 */ } i2c_duty_t; /** * @brief I2C Addressing Mode */ -typedef enum -{ - I2C_ADDR_7BIT = 0x1, /**< 7 bit address */ - I2C_ADDR_10BIT = 0x2, /**< 10 bit address */ +typedef enum { + I2C_ADDR_7BIT = 0x1U, /**< 7 bit address */ + I2C_ADDR_10BIT = 0x2U, /**< 10 bit address */ } i2c_addr_t; /** * @brief I2C Dual Addressing Mode */ -typedef enum -{ - I2C_DUALADDR_DISABLE = 0x0, /**< dual address is disable */ - I2C_DUALADDR_ENABLE = 0x1, /**< dual address is enable */ +typedef enum { + I2C_DUALADDR_DISABLE = 0x0U, /**< dual address is disable */ + I2C_DUALADDR_ENABLE = 0x1U, /**< dual address is enable */ } i2c_dual_addr_t; /** * @brief I2C General Call Addressing mode */ -typedef enum -{ - I2C_GENERALCALL_DISABLE = 0x0, /**< feneral call address is disable */ - I2C_GENERALCALL_ENABLE = 0x40, /**< feneral call address is enable */ +typedef enum { + I2C_GENERALCALL_DISABLE = 0x0U, /**< feneral call address is disable */ + I2C_GENERALCALL_ENABLE = 0x40U, /**< feneral call address is enable */ } i2c_general_addr_t; /** * @brief I2C Nostretch Mode */ -typedef enum -{ - I2C_NOSTRETCH_DISABLE = 0x0, /**< Nostretch disable */ - I2C_NOSTRETCH_ENABLE = 0x80, /**< Nostretch enable */ +typedef enum { + I2C_NOSTRETCH_DISABLE = 0x0U, /**< Nostretch disable */ + I2C_NOSTRETCH_ENABLE = 0x80U, /**< Nostretch enable */ } i2c_nostretch_t; /** * @brief I2C Memory Address Size */ -typedef enum -{ - I2C_MEMADD_SIZE_8BIT = 0x1, /**< 8 bit memory address size */ - I2C_MEMADD_SIZE_16BIT = 0x10 /**< 10 bit memory address size */ +typedef enum { + I2C_MEMADD_SIZE_8BIT = 0x1U, /**< 8 bit memory address size */ + I2C_MEMADD_SIZE_16BIT = 0x10U, /**< 10 bit memory address size */ } i2c_addr_size_t; /** * @brief I2C Flag Definition */ -typedef enum -{ - I2C_FLAG_SB = (1U << 0), - I2C_FLAG_ADDR = (1U << 1), - I2C_FLAG_BTF = (1U << 2), - I2C_FLAG_ADD10 = (1U << 3), - I2C_FLAG_STOPF = (1U << 4), - I2C_FLAG_RXNE = (1U << 6), - I2C_FLAG_TXE = (1U << 7), - I2C_FLAG_BERR = (1U << 8), - I2C_FLAG_ARLO = (1U << 9), - I2C_FLAG_AF = (1U << 10), - I2C_FLAG_OVR = (1U << 11), - I2C_FLAG_PECERR = (1U << 12), - I2C_FLAG_TIMEOUT = (1U << 14), - I2C_FLAG_SMBALERT = (1U << 15), - I2C_FLAG_MSL = (1U << 16), - I2C_FLAG_BUSY = (1U << 17), - I2C_FLAG_TRA = (1U << 18), - I2C_FLAG_GENCALL = (1U << 20), - I2C_FLAG_SMBDEFAULT = (1U << 21), - I2C_FLAG_SMBHOST = (1U << 22), - I2C_FLAG_DUALF = (1U << 23), +typedef enum { + I2C_FLAG_SB = (1U << 0), + I2C_FLAG_ADDR = (1U << 1), + I2C_FLAG_BTF = (1U << 2), + I2C_FLAG_ADD10 = (1U << 3), + I2C_FLAG_STOPF = (1U << 4), + I2C_FLAG_RXNE = (1U << 6), + I2C_FLAG_TXE = (1U << 7), + I2C_FLAG_BERR = (1U << 8), + I2C_FLAG_ARLO = (1U << 9), + I2C_FLAG_AF = (1U << 10), + I2C_FLAG_OVR = (1U << 11), + I2C_FLAG_PECERR = (1U << 12), + I2C_FLAG_TIMEOUT = (1U << 14), + I2C_FLAG_SMBALERT = (1U << 15), + I2C_FLAG_MSL = (1U << 16), + I2C_FLAG_BUSY = (1U << 17), + I2C_FLAG_TRA = (1U << 18), + I2C_FLAG_GENCALL = (1U << 20), + I2C_FLAG_SMBDEFAULT = (1U << 21), + I2C_FLAG_SMBHOST = (1U << 22), + I2C_FLAG_DUALF = (1U << 23), } i2c_flag_t; /** @@ -151,193 +142,181 @@ typedef enum */ typedef enum { - I2C_MODE_NONE = 0x0, /**< No I2C communication on going */ - I2C_MODE_MASTER = 0x10, /**< I2C communication is in Master mode */ - I2C_MODE_SLAVE = 0x20, /**< I2C communication is in Slave mode */ - I2C_MODE_MEM = 0x40, /**< I2C communication is in Memory mode */ + I2C_MODE_NONE = 0x0U, /**< No I2C communication on going */ + I2C_MODE_MASTER = 0x10U, /**< I2C communication is in Master mode */ + I2C_MODE_SLAVE = 0x20U, /**< I2C communication is in Slave mode */ + I2C_MODE_MEM = 0x40U, /**< I2C communication is in Memory mode */ } i2c_mode_t; /** * @brief I2C Clock */ -typedef enum -{ - I2C_STANDARD_MODE_MAX_CLK = 100000, /**< Standard mode clock */ - I2C_FAST_MODE_MAX_CLK = 400000, /**< Fast mode clock */ +typedef enum { + I2C_STANDARD_MODE_MAX_CLK = 100000U, /**< Standard mode clock */ + I2C_FAST_MODE_MAX_CLK = 400000U, /**< Fast mode clock */ } i2c_clock_t; /** * @brief Interrupt Configuration Definition */ -typedef enum -{ - I2C_IT_BUF = (1U << 10), /**< Buffer interrupt */ - I2C_IT_EVT = (1U << 9), /**< Event interrupt */ - I2C_IT_ERR = (1U << 8), /**< Error interrupt */ +typedef enum { + I2C_IT_BUF = (1U << 10), /**< Buffer interrupt */ + I2C_IT_EVT = (1U << 9), /**< Event interrupt */ + I2C_IT_ERR = (1U << 8), /**< Error interrupt */ } i2c_interrupt_t; /** * @brief I2C CON1 Register */ -typedef enum -{ - I2C_CON1_PEN = (1U << 0), /**< PEN BIT */ - I2C_CON1_PMOD = (1U << 1), /**< PMOD BIT */ - I2C_CON1_SMBMOD = (1U << 3), /**< SMBMOD BIT */ - I2C_CON1_ARPEN = (1U << 4), /**< ARPEN BIT */ - I2C_CON1_PECEN = (1U << 5), /**< PECEN BIT */ - I2C_CON1_GCEN = (1U << 6), /**< GCEN BIT */ - I2C_CON1_DISCS = (1U << 7), /**< DISCS BIT */ - I2C_CON1_START = (1U << 8), /**< START BIT */ - I2C_CON1_STOP = (1U << 9), /**< STOP BIT */ - I2C_CON1_ACKEN = (1U << 10), /**< ACKEN BIT */ - I2C_CON1_POSAP = (1U << 11), /**< POSAP BIT */ - I2C_CON1_TRPEC = (1U << 12), /**< TRPEC BIT */ - I2C_CON1_ALARM = (1U << 13), /**< ALARM BIT */ - I2C_CON1_SRST = (1U << 15), /**< SRST BIT */ +typedef enum { + I2C_CON1_PEN = (1U << 0), /**< PEN BIT */ + I2C_CON1_PMOD = (1U << 1), /**< PMOD BIT */ + I2C_CON1_SMBMOD = (1U << 3), /**< SMBMOD BIT */ + I2C_CON1_ARPEN = (1U << 4), /**< ARPEN BIT */ + I2C_CON1_PECEN = (1U << 5), /**< PECEN BIT */ + I2C_CON1_GCEN = (1U << 6), /**< GCEN BIT */ + I2C_CON1_DISCS = (1U << 7), /**< DISCS BIT */ + I2C_CON1_START = (1U << 8), /**< START BIT */ + I2C_CON1_STOP = (1U << 9), /**< STOP BIT */ + I2C_CON1_ACKEN = (1U << 10), /**< ACKEN BIT */ + I2C_CON1_POSAP = (1U << 11), /**< POSAP BIT */ + I2C_CON1_TRPEC = (1U << 12), /**< TRPEC BIT */ + I2C_CON1_ALARM = (1U << 13), /**< ALARM BIT */ + I2C_CON1_SRST = (1U << 15), /**< SRST BIT */ } i2c_con1_t; /** * @brief I2C CON2 Register */ -typedef enum -{ - I2C_CON2_CLKF = 0x3F, /**< CLKF BITS */ - I2C_CON2_CLKF_0 = (1U << 0), /**< CLKF_0 BIT */ - I2C_CON2_CLKF_1 = (1U << 1), /**< CLKF_1 BIT */ - I2C_CON2_CLKF_2 = (1U << 2), /**< CLKF_2 BIT */ - I2C_CON2_CLKF_3 = (1U << 3), /**< CLKF_3 BIT */ - I2C_CON2_CLKF_4 = (1U << 4), /**< CLKF_4 BIT */ - I2C_CON2_CLKF_5 = (1U << 5), /**< CLKF_5 BIT */ - I2C_CON2_ERRIE = (1U << 8), /**< ERRIE BIT */ - I2C_CON2_EVTIE = (1U << 9), /**< EVTIE BIT */ - I2C_CON2_BUFIE = (1U << 10), /**< BUFIE BIT */ - I2C_CON2_DMAEN = (1U << 11), /**< DMAEN BIT */ - I2C_CON2_LDMA = (1U << 12), /**< LDMA BIT */ +typedef enum { + I2C_CON2_CLKF = 0x3FU, /**< CLKF BITS */ + I2C_CON2_CLKF_0 = (1U << 0), /**< CLKF_0 BIT */ + I2C_CON2_CLKF_1 = (1U << 1), /**< CLKF_1 BIT */ + I2C_CON2_CLKF_2 = (1U << 2), /**< CLKF_2 BIT */ + I2C_CON2_CLKF_3 = (1U << 3), /**< CLKF_3 BIT */ + I2C_CON2_CLKF_4 = (1U << 4), /**< CLKF_4 BIT */ + I2C_CON2_CLKF_5 = (1U << 5), /**< CLKF_5 BIT */ + I2C_CON2_ERRIE = (1U << 8), /**< ERRIE BIT */ + I2C_CON2_EVTIE = (1U << 9), /**< EVTIE BIT */ + I2C_CON2_BUFIE = (1U << 10), /**< BUFIE BIT */ + I2C_CON2_DMAEN = (1U << 11), /**< DMAEN BIT */ + I2C_CON2_LDMA = (1U << 12), /**< LDMA BIT */ } i2c_con2_t; /** * @brief I2C ADDR1 Register */ -typedef enum -{ - I2C_ADDR1_ADDH0 = (1U << 0), /**< ADDH0 BIT */ - I2C_ADDR1_ADDH1 = (1U << 1), /**< ADDH1 BIT */ - I2C_ADDR1_ADDH2 = (1U << 2), /**< ADDH2 BIT */ - I2C_ADDR1_ADDH3 = (1U << 3), /**< ADDH3 BIT */ - I2C_ADDR1_ADDH4 = (1U << 4), /**< ADDH4 BIT */ - I2C_ADDR1_ADDH5 = (1U << 5), /**< ADDH5 BIT */ - I2C_ADDR1_ADDH6 = (1U << 6), /**< ADDH6 BIT */ - I2C_ADDR1_ADDH7 = (1U << 7), /**< ADDH7 BIT */ - I2C_ADDR1_ADDH8 = (1U << 8), /**< ADDH8 BIT */ - I2C_ADDR1_ADDH9 = (1U << 9), /**< ADDH9 BIT */ - I2C_ADDR1_ADDTYPE = (1U << 15), /**< ADDTYPE BIT */ +typedef enum { + I2C_ADDR1_ADDH0 = (1U << 0), /**< ADDH0 BIT */ + I2C_ADDR1_ADDH1 = (1U << 1), /**< ADDH1 BIT */ + I2C_ADDR1_ADDH2 = (1U << 2), /**< ADDH2 BIT */ + I2C_ADDR1_ADDH3 = (1U << 3), /**< ADDH3 BIT */ + I2C_ADDR1_ADDH4 = (1U << 4), /**< ADDH4 BIT */ + I2C_ADDR1_ADDH5 = (1U << 5), /**< ADDH5 BIT */ + I2C_ADDR1_ADDH6 = (1U << 6), /**< ADDH6 BIT */ + I2C_ADDR1_ADDH7 = (1U << 7), /**< ADDH7 BIT */ + I2C_ADDR1_ADDH8 = (1U << 8), /**< ADDH8 BIT */ + I2C_ADDR1_ADDH9 = (1U << 9), /**< ADDH9 BIT */ + I2C_ADDR1_ADDTYPE = (1U << 15), /**< ADDTYPE BIT */ } i2c_addr1_t; /** * @brief I2C ADDR2 Register */ -typedef enum -{ - I2C_ADDR2_DUALEN = (1U << 0), /**< DUALEN BIT */ - I2C_ADDR2_ADD = (1U << 1), /**< ADD BIT */ +typedef enum { + I2C_ADDR2_DUALEN = (1U << 0), /**< DUALEN BIT */ + I2C_ADDR2_ADD = (1U << 1), /**< ADD BIT */ } i2c_addr2_t; /** * @brief I2C STAT1 Register */ -typedef enum -{ - I2C_STAT1_SB = (1U << 0), /**< SB BIT */ - I2C_STAT1_ADDR = (1U << 1), /**< ADDR BIT */ - I2C_STAT1_BTC = (1U << 2), /**< BTC BIT */ - I2C_STAT1_SENDADD10 = (1U << 3), /**< SENDADD10 BIT */ - I2C_STAT1_DETSTP = (1U << 4), /**< DETSTP BIT */ - I2C_STAT1_RXBNE = (1U << 6), /**< RXBNE BIT */ - I2C_STAT1_TXBE = (1U << 7), /**< TXBE BIT */ - I2C_STAT1_BUSERR = (1U << 8), /**< BUSERR BIT */ - I2C_STAT1_LARB = (1U << 9), /**< LARB BIT */ - I2C_STAT1_ACKERR = (1U << 10), /**< ACKERR BIT */ - I2C_STAT1_ROUERR = (1U << 11), /**< ROUERR BIT */ - I2C_STAT1_PECERR = (1U << 12), /**< PECERR BIT */ - I2C_STAT1_SMBTO = (1U << 14), /**< SMBTO BIT */ - I2C_STAT1_SMBALARM = (1U << 15), /**< SMBALARM BIT */ +typedef enum { + I2C_STAT1_SB = (1U << 0), /**< SB BIT */ + I2C_STAT1_ADDR = (1U << 1), /**< ADDR BIT */ + I2C_STAT1_BTC = (1U << 2), /**< BTC BIT */ + I2C_STAT1_SENDADD10 = (1U << 3), /**< SENDADD10 BIT */ + I2C_STAT1_DETSTP = (1U << 4), /**< DETSTP BIT */ + I2C_STAT1_RXBNE = (1U << 6), /**< RXBNE BIT */ + I2C_STAT1_TXBE = (1U << 7), /**< TXBE BIT */ + I2C_STAT1_BUSERR = (1U << 8), /**< BUSERR BIT */ + I2C_STAT1_LARB = (1U << 9), /**< LARB BIT */ + I2C_STAT1_ACKERR = (1U << 10), /**< ACKERR BIT */ + I2C_STAT1_ROUERR = (1U << 11), /**< ROUERR BIT */ + I2C_STAT1_PECERR = (1U << 12), /**< PECERR BIT */ + I2C_STAT1_SMBTO = (1U << 14), /**< SMBTO BIT */ + I2C_STAT1_SMBALARM = (1U << 15), /**< SMBALARM BIT */ } i2c_stat1_t; /** * @brief I2C STAT2 Register */ -typedef enum -{ - I2C_STAT2_MASTER = (1U << 0), /**< MASTER BIT */ - I2C_STAT2_BSYF = (1U << 1), /**< BSYF BIT */ - I2C_STAT2_TRF = (1U << 2), /**< TRF BIT */ - I2C_STAT2_RXGCF = (1U << 4), /**< RXGCF BIT */ - I2C_STAT2_SMBDEF = (1U << 5), /**< SMBDEF BIT */ - I2C_STAT2_SMBHH = (1U << 6), /**< SMBHH BIT */ - I2C_STAT2_DUALF = (1U << 7), /**< DMF BIT */ - I2C_STAT2_PECV = (1U << 8), /**< PECV BIT */ +typedef enum { + I2C_STAT2_MASTER = (1U << 0), /**< MASTER BIT */ + I2C_STAT2_BSYF = (1U << 1), /**< BSYF BIT */ + I2C_STAT2_TRF = (1U << 2), /**< TRF BIT */ + I2C_STAT2_RXGCF = (1U << 4), /**< RXGCF BIT */ + I2C_STAT2_SMBDEF = (1U << 5), /**< SMBDEF BIT */ + I2C_STAT2_SMBHH = (1U << 6), /**< SMBHH BIT */ + I2C_STAT2_DUALF = (1U << 7), /**< DMF BIT */ + I2C_STAT2_PECV = (1U << 8), /**< PECV BIT */ } i2c_stat2_t; /** * @brief I2C CKCFG Register */ -typedef enum -{ - I2C_CKCFG_CLKSET = 0xFFF, /**< CLKSET BITS */ - I2C_CKCFG_DUTY = (1U << 14), /**< DUTY BIT */ - I2C_CKCFG_CLKMOD = (1U << 15), /**< CLKMOD BIT */ +typedef enum { + I2C_CKCFG_CLKSET = 0xFFFU, /**< CLKSET BITS */ + I2C_CKCFG_DUTY = (1U << 14), /**< DUTY BIT */ + I2C_CKCFG_CLKMOD = (1U << 15), /**< CLKMOD BIT */ } i2c_ckcfg_t; /** * @brief I2C RT Register */ -typedef enum -{ - I2C_RT_RISET = 0x3F, /**< RISET BITS */ +typedef enum { + I2C_RT_RISET = 0x3FU, /**< RISET BITS */ } i2c_trise_t; /** * @brief I2C Configuration Structure definition */ -typedef struct -{ - uint32_t clk_speed; /**< Specifies the clock frequency */ - i2c_duty_t duty; /**< Specifies the I2C fast mode duty cycle */ - uint32_t own_addr1; /**< Specifies the first device own address */ - i2c_addr_t addr_mode; /**< Specifies addressing mode */ - i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ - uint32_t own_addr2; /**< Specifies the second device own address */ - i2c_general_addr_t general_call; /**< Specifies if general call mode is selected */ - i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ +typedef struct { + uint32_t clk_speed; /**< Specifies the clock frequency */ + i2c_duty_t duty; /**< Specifies the I2C fast mode duty cycle */ + uint32_t own_addr1; /**< Specifies the first device own address */ + i2c_addr_t addr_mode; /**< Specifies addressing mode */ + i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ + uint32_t own_addr2; /**< Specifies the second device own address */ + i2c_general_addr_t general_call; /**< Specifies if general call mode is selected */ + i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ } i2c_init_t; /** * @brief I2C handle Structure definition */ -typedef struct i2c_handle_s -{ - I2C_TypeDef *perh; /**< I2C registers base address */ - i2c_init_t init; /**< I2C communication parameters */ - uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ - uint16_t xfer_size; /**< I2C transfer size */ - __IO uint16_t xfer_count; /**< I2C transfer counter */ +typedef struct i2c_handle_s { + I2C_TypeDef *perh; /**< I2C registers base address */ + i2c_init_t init; /**< I2C communication parameters */ + uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ + uint16_t xfer_size; /**< I2C transfer size */ + __IO uint16_t xfer_count; /**< I2C transfer counter */ #ifdef ALD_DMA - dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ + dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ #endif - lock_state_t lock; /**< I2C locking object */ - __IO i2c_state_t state; /**< I2C communication state */ - __IO i2c_mode_t mode; /**< I2C communication mode */ - __IO uint32_t error_code; /**< I2C Error code */ - - void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */ - void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */ - void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Tx completed callback */ - void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Rx completed callback */ - void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Tx to Memory completed callback */ - void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Rx from Memory completed callback */ - void (*error_callback)(struct i2c_handle_s *arg); /**< Error callback */ + lock_state_t lock; /**< I2C locking object */ + __IO i2c_state_t state; /**< I2C communication state */ + __IO i2c_mode_t mode; /**< I2C communication mode */ + __IO uint32_t error_code; /**< I2C Error code */ + + void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */ + void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */ + void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Tx completed callback */ + void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Rx completed callback */ + void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Tx to Memory completed callback */ + void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Rx from Memory completed callback */ + void (*error_callback)(struct i2c_handle_s *arg); /**< Error callback */ } i2c_handle_t; /** @@ -349,19 +328,19 @@ typedef struct i2c_handle_s */ #define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET) #define I2C_CLEAR_ADDRFLAG(x) \ - do { \ - __IO uint32_t tmpreg; \ - tmpreg = (x)->perh->STAT1; \ - tmpreg = (x)->perh->STAT2; \ - UNUSED(tmpreg); \ - } while (0) +do { \ + __IO uint32_t tmpreg; \ + tmpreg = (x)->perh->STAT1; \ + tmpreg = (x)->perh->STAT2; \ + UNUSED(tmpreg); \ +} while (0) #define __I2C_CLEAR_STOPFLAG(x) \ - do { \ - __IO uint32_t tmpreg; \ - tmpreg = (x)->perh->STAT1; \ - tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN); \ - UNUSED(tmpreg); \ - } while (0) +do { \ + __IO uint32_t tmpreg; \ + tmpreg = (x)->perh->STAT1; \ + tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN); \ + UNUSED(tmpreg); \ +} while (0) #define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) #define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) /** @@ -372,56 +351,56 @@ typedef struct i2c_handle_s * @{ */ #define IS_I2C_TYPE(x) (((x) == I2C0) || \ - ((x) == I2C1)) + ((x) == I2C1)) #define IS_I2C_ADDRESSING_MODE(x) (((x) == I2C_ADDR_7BIT) || \ - ((x) == I2C_ADDR_10BIT)) + ((x) == I2C_ADDR_10BIT)) #define IS_I2C_DUAL_ADDRESS(x) (((x) == I2C_DUALADDR_DISABLE) || \ - ((x) == I2C_DUALADDR_ENABLE)) + ((x) == I2C_DUALADDR_ENABLE)) #define IS_I2C_GENERAL_CALL(x) (((x) == I2C_GENERALCALL_DISABLE) || \ - ((x) == I2C_GENERALCALL_ENABLE)) + ((x) == I2C_GENERALCALL_ENABLE)) #define IS_I2C_MEMADD_size(x) (((x) == I2C_MEMADD_SIZE_8BIT) || \ - ((x) == I2C_MEMADD_SIZE_16BIT)) + ((x) == I2C_MEMADD_SIZE_16BIT)) #define IS_I2C_NO_STRETCH(x) (((x) == I2C_NOSTRETCH_DISABLE) || \ - ((x) == I2C_NOSTRETCH_ENABLE)) + ((x) == I2C_NOSTRETCH_ENABLE)) #define IS_I2C_OWN_ADDRESS1(x) (((x) & (uint32_t)(0xFFFFFC00)) == 0) #define IS_I2C_OWN_ADDRESS2(x) (((x) & (uint32_t)(0xFFFFFF01)) == 0) #define IS_I2C_CLOCK_SPEED(x) (((x) > 0) && ((x) <= I2C_FAST_MODE_MAX_CLK)) #define IS_I2C_DUTY_CYCLE(x) (((x) == I2C_DUTYCYCLE_2) || \ - ((x) == I2C_DUTYCYCLE_16_9)) + ((x) == I2C_DUTYCYCLE_16_9)) #define IS_I2C_IT_TYPE(x) (((x) == I2C_IT_BUF) || \ - ((x) == I2C_IT_EVT) || \ - ((x) == I2C_IT_ERR)) + ((x) == I2C_IT_EVT) || \ + ((x) == I2C_IT_ERR)) #define IS_I2C_FLAG(x) (((x) == I2C_FLAG_SB) || \ - ((x) == I2C_FLAG_ADDR) || \ - ((x) == I2C_FLAG_BTF) || \ - ((x) == I2C_FLAG_ADD10) || \ - ((x) == I2C_FLAG_STOPF) || \ - ((x) == I2C_FLAG_RXNE) || \ - ((x) == I2C_FLAG_TXE) || \ - ((x) == I2C_FLAG_BERR) || \ - ((x) == I2C_FLAG_ARLO) || \ - ((x) == I2C_FLAG_AF) || \ - ((x) == I2C_FLAG_OVR) || \ - ((x) == I2C_FLAG_PECERR) || \ - ((x) == I2C_FLAG_TIMEOUT) || \ - ((x) == I2C_FLAG_SMBALERT) || \ - ((x) == I2C_FLAG_MSL) || \ - ((x) == I2C_FLAG_BUSY) || \ - ((x) == I2C_FLAG_TRA) || \ - ((x) == I2C_FLAG_GENCALL) || \ - ((x) == I2C_FLAG_SMBDEFAULT) || \ - ((x) == I2C_FLAG_SMBHOST) || \ - ((x) == I2C_FLAG_DUALF)) + ((x) == I2C_FLAG_ADDR) || \ + ((x) == I2C_FLAG_BTF) || \ + ((x) == I2C_FLAG_ADD10) || \ + ((x) == I2C_FLAG_STOPF) || \ + ((x) == I2C_FLAG_RXNE) || \ + ((x) == I2C_FLAG_TXE) || \ + ((x) == I2C_FLAG_BERR) || \ + ((x) == I2C_FLAG_ARLO) || \ + ((x) == I2C_FLAG_AF) || \ + ((x) == I2C_FLAG_OVR) || \ + ((x) == I2C_FLAG_PECERR) || \ + ((x) == I2C_FLAG_TIMEOUT) || \ + ((x) == I2C_FLAG_SMBALERT) || \ + ((x) == I2C_FLAG_MSL) || \ + ((x) == I2C_FLAG_BUSY) || \ + ((x) == I2C_FLAG_TRA) || \ + ((x) == I2C_FLAG_GENCALL) || \ + ((x) == I2C_FLAG_SMBDEFAULT) || \ + ((x) == I2C_FLAG_SMBHOST) || \ + ((x) == I2C_FLAG_DUALF)) #define I2C_FREQ_RANGE(x) ((x) / 1000000) #define I2C_RISE_TIME(x, u) (((u) <= I2C_STANDARD_MODE_MAX_CLK) ? ((x) + 1) :\ ((((x) * 300) / 1000) + 1)) #define I2C_SPEED_STANDARD(x, y) (((((x) / ((y) << 1)) & I2C_CKCFG_CLKSET) < 4) ? 4:\ - ((x) / ((y) << 1))) + ((x) / ((y) << 1))) #define I2C_SPEED_FAST(x, y, z) (((z) == I2C_DUTYCYCLE_2) ? ((x) / ((y) * 3)) :\ (((x) / ((y) * 25)) | I2C_DUTYCYCLE_16_9)) #define I2C_SPEED(x, y, z) (((y) <= 100000) ? (I2C_SPEED_STANDARD((x), (y))) :\ - ((I2C_SPEED_FAST((x), (y), (z)) & I2C_CKCFG_CLKSET) == 0) ? 1 : \ + ((I2C_SPEED_FAST((x), (y), (z)) & I2C_CKCFG_CLKSET) == 0) ? 1 : \ ((I2C_SPEED_FAST((x), (y), (z))) | I2C_CKCFG_CLKMOD)) #define I2C_MEM_ADD_MSB(x) ((uint8_t)((uint16_t)(((uint16_t)((x) &\ (uint16_t)(0xFF00))) >> 8))) @@ -432,7 +411,7 @@ typedef struct i2c_handle_s #define I2C_10BIT_HEADER_WRITE(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) #define I2C_10BIT_HEADER_READ(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ - (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) + (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) /** * @} */ @@ -454,41 +433,41 @@ ald_status_t ald_i2c_reset(i2c_handle_t *hperh); /** @addtogroup I2C_Public_Functions_Group2 * @{ */ -/** Blocking mode: Polling */ + /** Blocking mode: Polling */ ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint32_t timeout); + uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout); -/** Non-Blocking mode: Interrupt */ + /** Non-Blocking mode: Interrupt */ ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); #ifdef ALD_DMA -/** Non-Blocking mode: DMA */ + /** Non-Blocking mode: DMA */ ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint8_t channel); + uint8_t *buf, uint16_t size, uint8_t channel); ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint8_t channel); + uint8_t *buf, uint16_t size, uint8_t channel); ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel); + uint8_t *buf, uint16_t size, uint8_t channel); ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel); + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel); #endif /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h index 7a841e7c2a32601e2bc3445920576765863ed8dd..a777fca4a9ddc55f06be917d4544a9c71ef16d38 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h @@ -36,10 +36,10 @@ extern "C" { * @defgroup IAP_Private_Macros IAP Private Macros * @{ */ -#define IAP_WSP_ADDR 0x10000000 -#define IAP_PE_ADDR 0x10000004 -#define IAP_WP_ADDR 0x10000008 -#define IAP_DWP_ADDR 0x1000000c +#define IAP_WSP_ADDR 0x10000000U +#define IAP_PE_ADDR 0x10000004U +#define IAP_WP_ADDR 0x10000008U +#define IAP_DWP_ADDR 0x1000000cU /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h index a40bc998d119597634ffde2fca08300e5164b7f6..c17b03cfd96c762dd6a6ab1d514d8e9aea7ae707 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h @@ -18,7 +18,7 @@ #define __ALD_PIS_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -37,327 +37,277 @@ extern "C" { */ /** * @brief Producer entry - * @note ES32F065x: - * AD16C4T0--TIMER0 - * GP16C4T0--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - * - * ES32F033x: - * ES32F093x: - * GP16C4T0--TIMER0 - * GP16C4T1--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - */ -typedef enum -{ - PIS_NON = 0x0, /**< No async */ - PIS_GPIO_PIN0 = 0x10, /**< Pin0, level,support async */ - PIS_GPIO_PIN1 = 0x11, /**< Pin1, level,support async */ - PIS_GPIO_PIN2 = 0x12, /**< Pin2, level,support async */ - PIS_GPIO_PIN3 = 0x13, /**< Pin3, level,support async */ - PIS_GPIO_PIN4 = 0x14, /**< Pin4, level,support async */ - PIS_GPIO_PIN5 = 0x15, /**< Pin5, level,support async */ - PIS_GPIO_PIN6 = 0x16, /**< Pin6, level,support async */ - PIS_GPIO_PIN7 = 0x17, /**< Pin7, level,support async */ - PIS_GPIO_PIN8 = 0x18, /**< Pin8, level,support async */ - PIS_GPIO_PIN9 = 0x19, /**< Pin9, level,support async */ - PIS_GPIO_PIN10 = 0x1a, /**< Pin10, level,support async */ - PIS_GPIO_PIN11 = 0x1b, /**< Pin11, level,support async */ - PIS_GPIO_PIN12 = 0x1c, /**< Pin12, level,support async */ - PIS_GPIO_PIN13 = 0x1d, /**< Pin13, level,support async */ - PIS_GPIO_PIN14 = 0x1e, /**< Pin14, level,support async */ - PIS_GPIO_PIN15 = 0x1f, /**< Pin15, level,support async */ - PIS_ACMP_OUT0 = 0x30, /**< Acmp0 output, level,support async */ - PIS_ACMP_OUT1 = 0x31, /**< Acmp1 output, level,support async */ - PIS_DAC0_CH0 = 0x40, /**< Dac0 channel 0, pclk2 pulse,support async */ - PIS_DAC0_CH1 = 0x41, /**< Dac0 channel 1, pclk2 pulse,support async */ - PIS_ADC0_INJECT = 0x60, /**< Adc0 inject, pclk2 pulse,support async */ - PIS_ADC0_REGULAT = 0x61, /**< Adc0 regulat, pclk2 pulse,support async */ - PIS_ADC0_WINDOW = 0x62, /**< Adc0 window, no have */ - PIS_LVD = 0x70, /**< Lvd, level,support async */ - PIS_UART0_ASY_SEND = 0x80, /**< Uart0 asy send, pulse,support async */ - PIS_UART0_ASY_RECV = 0x81, /**< Uart0 asy recv, pulse,support async */ - PIS_UART0_IRDAOUT = 0x82, /**< Uart0 irdaout, level,support async */ - PIS_UART0_RTSOUT = 0x83, /**< Uart0 rtsout, level,support async */ - PIS_UART0_TXOUT = 0x84, /**< Uart0 txout, level,support async */ - PIS_UART0_SYN_SEND = 0x85, /**< Uart0 syn send, pulse,support async */ - PIS_UART0_SYN_RECV = 0x86, /**< Uart0 syn recv, pulse,support async */ - PIS_UART1_ASY_SEND = 0x90, /**< Uart1 asy send, pulse,support async */ - PIS_UART1_ASY_RECV = 0x91, /**< Uart1 asy recv, pulse,support async */ - PIS_UART1_IRDA = 0x92, /**< Uart1 irdaout, level,support async */ - PIS_UART1_RTS = 0x93, /**< Uart1 rtsout, level,support async */ - PIS_UART1_TXOUT = 0x94, /**< Uart1 txout, level,support async */ - PIS_UART1_SYN_SEND = 0x95, /**< Uart1 syn send, pulse,support async */ - PIS_UART1_SYN_RECV = 0x96, /**< Uart1 syn recv, pulse,support async */ - PIS_UART2_ASY_SEND = 0xa0, /**< Uart2 asy send, pulse,support async */ - PIS_UART2_ASY_RECV = 0xa1, /**< Uart2 asy recv, pulse,support async */ - PIS_UART2_IRDA = 0xa2, /**< Uart2 irdaout, level,support async */ - PIS_UART2_RTS = 0xa3, /**< Uart2 rtsout, level,support async */ - PIS_UART2_TXOUT = 0xa4, /**< Uart2 txout, level,support async */ - PIS_UART2_SYN_SEND = 0xa5, /**< Uart2 syn send, pulse,support async */ - PIS_UART2_SYN_RECV = 0xa6, /**< Uart2 syn recv, pulse,support async */ - PIS_UART3_ASY_SEND = 0xb1, /**< Uart3 asy send, pulse,support async */ - PIS_UART3_ASY_RECV = 0xb2, /**< Uart3 asy recv, pulse,support async */ - PIS_UART3_IRDA = 0xb3, /**< Uart3 irdaout, level,support async */ - PIS_UART3_RTS = 0xb4, /**< Uart3 rtsout, level,support async */ - PIS_UART3_TXOUT = 0xb5, /**< Uart3 txout, level,support async */ - PIS_UART3_SYN_SEND = 0xb6, /**< Uart3 syn send, pulse,support async */ - PIS_UART3_SYN_RECV = 0xb7, /**< Uart3 syn recv, pulse,support async */ - PIS_EUART0_RECV = 0xc0, /**< Euart0 recv, plck1 pulse */ - PIS_EUART0_SEND = 0xc1, /**< Euart0 send, plck1 pulse */ - PIS_EUART0_TXOUT = 0xc2, /**< Euart0 txout, plck1 level */ - PIS_EUART1_RECV = 0xd0, /**< Euart1 recv, plck1 pulse */ - PIS_EUART1_SEND = 0xd1, /**< Euart1 send, plck1 pulse */ - PIS_EUART1_TXOUT = 0xd2, /**< Euart1 txout, plck1 level */ - PIS_SPI0_RECV = 0xe0, /**< Spi0 recv, plck1 pulse */ - PIS_SPI0_SEND = 0xe1, /**< Spi0 send, plck1 pulse */ - PIS_SPI0_NE = 0xe2, /**< Spi0 ne, plck1 level */ - PIS_SPI1_RECV = 0xf0, /**< Spi1 recv, plck1 pulse */ - PIS_SPI1_SEND = 0xf1, /**< Spi1 send, plck1 pulse */ - PIS_SPI1_NE = 0xf2, /**< Spi1 ne, plck1 level */ - PIS_I2C0_RECV = 0x100, /**< I2c0 recv, plck1 level */ - PIS_I2C0_SEND = 0x101, /**< I2c0 send, plck1 level */ - PIS_I2C1_RECV = 0x110, /**< I2c1 recv, plck1 level */ - PIS_I2C1_SEND = 0x111, /**< I2c1 send, plck1 level */ - PIS_TIMER0_UPDATA = 0x120, /**< Timer0 updata, plck1 pulse */ - PIS_TIMER0_TRIG = 0x121, /**< Timer0 trig, plck1 pulse */ - PIS_TIMER0_INPUT = 0x122, /**< Timer0 input, plck1 pulse */ - PIS_TIMER0_OUTPUT = 0x123, /**< Timer0 output, plck1 pulse */ - PIS_TIMER1_UPDATA = 0x130, /**< Timer1 updata, plck1 pulse */ - PIS_TIMER1_TRIG = 0x131, /**< Timer1 trig, plck1 pulse */ - PIS_TIMER1_INPUT = 0x132, /**< Timer1 input, plck1 pulse */ - PIS_TIMER1_OUTPUT = 0x133, /**< Timer1 output, plck1 pulse */ - PIS_TIMER2_UPDATA = 0x140, /**< Timer2 updata, plck1 pulse */ - PIS_TIMER2_TRIG = 0x141, /**< Timer2 trig, plck1 pulse */ - PIS_TIMER2_INPUT = 0x142, /**< Timer2 input, plck1 pulse */ - PIS_TIMER2_OUTPUT = 0x143, /**< Timer2 output, plck1 pulse */ - PIS_TIMER3_UPDATA = 0x150, /**< Timer0 updata, plck1 pulse */ - PIS_TIMER3_TRIG = 0x151, /**< Timer0 trig, plck1 pulse */ - PIS_TIMER3_INPUT = 0x152, /**< Timer0 input, plck1 pulse */ - PIS_TIMER3_OUTPUT = 0x153, /**< Timer0 output, plck1 pulse */ - PIS_RTC_CLOCK = 0x160, /**< Rtc clock, pulse,support async */ - PIS_RTC_ALARM = 0x161, /**< Rtc alarm, pulse,support async */ - PIS_LPTIM0_SYN_UPDATA = 0x170, /**< Lptimer0 syn updata, pulse,support async */ - PIS_LPTIM0_ASY_UPDATA = 0x171, /**< Lptimer0 asy updata, pulse,support async */ - PIS_LPUART0_ASY_RECV = 0x180, /**< Lpuart0 asy recv, pulse,support async */ - PIS_LPUART0_ASY_SEND = 0x181, /**< Lpuart0 asy send, pulse,support async */ - PIS_LPUART0_SYN_RECV = 0x182, /**< Lpuart0 syn recv, pulse,support async */ - PIS_LPUART0_SYN_SEND = 0x183, /**< Lpuart0 syn recv, pulse,support async */ - PIS_DMA = 0x190, /**< Dma, pulse,support async */ - PIS_ADC1_INJECT = 0x1a0, /**< Adc1 inject, pclk2 pulse,support async */ - PIS_ADC1_REGULAT = 0x1a1, /**< Adc1 regulat, pclk2 pulse,support async */ - PIS_ADC1_WINDOW = 0x1a2, /**< Adc1 window, no have */ + * @verbatim + In this module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F065x series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + + 2. For ES32F033x/ES32F093x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + @endverbatim + */ +typedef enum { + PIS_NON = 0x0U, /**< No async */ + PIS_GPIO_PIN0 = 0x10U, /**< Pin0, level,support async */ + PIS_GPIO_PIN1 = 0x11U, /**< Pin1, level,support async */ + PIS_GPIO_PIN2 = 0x12U, /**< Pin2, level,support async */ + PIS_GPIO_PIN3 = 0x13U, /**< Pin3, level,support async */ + PIS_GPIO_PIN4 = 0x14U, /**< Pin4, level,support async */ + PIS_GPIO_PIN5 = 0x15U, /**< Pin5, level,support async */ + PIS_GPIO_PIN6 = 0x16U, /**< Pin6, level,support async */ + PIS_GPIO_PIN7 = 0x17U, /**< Pin7, level,support async */ + PIS_GPIO_PIN8 = 0x18U, /**< Pin8, level,support async */ + PIS_GPIO_PIN9 = 0x19U, /**< Pin9, level,support async */ + PIS_GPIO_PIN10 = 0x1aU, /**< Pin10, level,support async */ + PIS_GPIO_PIN11 = 0x1bU, /**< Pin11, level,support async */ + PIS_GPIO_PIN12 = 0x1cU, /**< Pin12, level,support async */ + PIS_GPIO_PIN13 = 0x1dU, /**< Pin13, level,support async */ + PIS_GPIO_PIN14 = 0x1eU, /**< Pin14, level,support async */ + PIS_GPIO_PIN15 = 0x1fU, /**< Pin15, level,support async */ + PIS_ACMP_OUT0 = 0x30U, /**< Acmp0 output, level,support async */ + PIS_ACMP_OUT1 = 0x31U, /**< Acmp1 output, level,support async */ + PIS_DAC0_CH0 = 0x40U, /**< Dac0 channel 0, pclk2 pulse,support async */ + PIS_DAC0_CH1 = 0x41U, /**< Dac0 channel 1, pclk2 pulse,support async */ + PIS_ADC0_INJECT = 0x60U, /**< Adc0 inject, pclk2 pulse,support async */ + PIS_ADC0_REGULAT = 0x61U, /**< Adc0 regulat, pclk2 pulse,support async */ + PIS_ADC0_WINDOW = 0x62U, /**< Adc0 window, no have */ + PIS_LVD = 0x70U, /**< Lvd, level,support async */ + PIS_UART0_ASY_SEND = 0x80U, /**< Uart0 asy send, pulse,support async */ + PIS_UART0_ASY_RECV = 0x81U, /**< Uart0 asy recv, pulse,support async */ + PIS_UART0_IRDAOUT = 0x82U, /**< Uart0 irdaout, level,support async */ + PIS_UART0_RTSOUT = 0x83U, /**< Uart0 rtsout, level,support async */ + PIS_UART0_TXOUT = 0x84U, /**< Uart0 txout, level,support async */ + PIS_UART0_SYN_SEND = 0x85U, /**< Uart0 syn send, pulse,support async */ + PIS_UART0_SYN_RECV = 0x86U, /**< Uart0 syn recv, pulse,support async */ + PIS_UART1_ASY_SEND = 0x90U, /**< Uart1 asy send, pulse,support async */ + PIS_UART1_ASY_RECV = 0x91U, /**< Uart1 asy recv, pulse,support async */ + PIS_UART1_IRDA = 0x92U, /**< Uart1 irdaout, level,support async */ + PIS_UART1_RTS = 0x93U, /**< Uart1 rtsout, level,support async */ + PIS_UART1_TXOUT = 0x94U, /**< Uart1 txout, level,support async */ + PIS_UART1_SYN_SEND = 0x95U, /**< Uart1 syn send, pulse,support async */ + PIS_UART1_SYN_RECV = 0x96U, /**< Uart1 syn recv, pulse,support async */ + PIS_UART2_ASY_SEND = 0xa0U, /**< Uart2 asy send, pulse,support async */ + PIS_UART2_ASY_RECV = 0xa1U, /**< Uart2 asy recv, pulse,support async */ + PIS_UART2_IRDA = 0xa2U, /**< Uart2 irdaout, level,support async */ + PIS_UART2_RTS = 0xa3U, /**< Uart2 rtsout, level,support async */ + PIS_UART2_TXOUT = 0xa4U, /**< Uart2 txout, level,support async */ + PIS_UART2_SYN_SEND = 0xa5U, /**< Uart2 syn send, pulse,support async */ + PIS_UART2_SYN_RECV = 0xa6U, /**< Uart2 syn recv, pulse,support async */ + PIS_UART3_ASY_SEND = 0xb1U, /**< Uart3 asy send, pulse,support async */ + PIS_UART3_ASY_RECV = 0xb2U, /**< Uart3 asy recv, pulse,support async */ + PIS_UART3_IRDA = 0xb3U, /**< Uart3 irdaout, level,support async */ + PIS_UART3_RTS = 0xb4U, /**< Uart3 rtsout, level,support async */ + PIS_UART3_TXOUT = 0xb5U, /**< Uart3 txout, level,support async */ + PIS_UART3_SYN_SEND = 0xb6U, /**< Uart3 syn send, pulse,support async */ + PIS_UART3_SYN_RECV = 0xb7U, /**< Uart3 syn recv, pulse,support async */ + PIS_EUART0_RECV = 0xc0U, /**< Euart0 recv, plck1 pulse */ + PIS_EUART0_SEND = 0xc1U, /**< Euart0 send, plck1 pulse */ + PIS_EUART0_TXOUT = 0xc2U, /**< Euart0 txout, plck1 level */ + PIS_EUART1_RECV = 0xd0U, /**< Euart1 recv, plck1 pulse */ + PIS_EUART1_SEND = 0xd1U, /**< Euart1 send, plck1 pulse */ + PIS_EUART1_TXOUT = 0xd2U, /**< Euart1 txout, plck1 level */ + PIS_SPI0_RECV = 0xe0U, /**< Spi0 recv, plck1 pulse */ + PIS_SPI0_SEND = 0xe1U, /**< Spi0 send, plck1 pulse */ + PIS_SPI0_NE = 0xe2U, /**< Spi0 ne, plck1 level */ + PIS_SPI1_RECV = 0xf0U, /**< Spi1 recv, plck1 pulse */ + PIS_SPI1_SEND = 0xf1U, /**< Spi1 send, plck1 pulse */ + PIS_SPI1_NE = 0xf2U, /**< Spi1 ne, plck1 level */ + PIS_I2C0_RECV = 0x100U, /**< I2c0 recv, plck1 level */ + PIS_I2C0_SEND = 0x101U, /**< I2c0 send, plck1 level */ + PIS_I2C1_RECV = 0x110U, /**< I2c1 recv, plck1 level */ + PIS_I2C1_SEND = 0x111U, /**< I2c1 send, plck1 level */ + PIS_TIMER0_UPDATA = 0x120U, /**< Timer0 updata, plck1 pulse */ + PIS_TIMER0_TRIG = 0x121U, /**< Timer0 trig, plck1 pulse */ + PIS_TIMER0_INPUT = 0x122U, /**< Timer0 input, plck1 pulse */ + PIS_TIMER0_OUTPUT = 0x123U, /**< Timer0 output, plck1 pulse */ + PIS_TIMER1_UPDATA = 0x130U, /**< Timer1 updata, plck1 pulse */ + PIS_TIMER1_TRIG = 0x131U, /**< Timer1 trig, plck1 pulse */ + PIS_TIMER1_INPUT = 0x132U, /**< Timer1 input, plck1 pulse */ + PIS_TIMER1_OUTPUT = 0x133U, /**< Timer1 output, plck1 pulse */ + PIS_TIMER2_UPDATA = 0x140U, /**< Timer2 updata, plck1 pulse */ + PIS_TIMER2_TRIG = 0x141U, /**< Timer2 trig, plck1 pulse */ + PIS_TIMER2_INPUT = 0x142U, /**< Timer2 input, plck1 pulse */ + PIS_TIMER2_OUTPUT = 0x143U, /**< Timer2 output, plck1 pulse */ + PIS_TIMER3_UPDATA = 0x150U, /**< Timer0 updata, plck1 pulse */ + PIS_TIMER3_TRIG = 0x151U, /**< Timer0 trig, plck1 pulse */ + PIS_TIMER3_INPUT = 0x152U, /**< Timer0 input, plck1 pulse */ + PIS_TIMER3_OUTPUT = 0x153U, /**< Timer0 output, plck1 pulse */ + PIS_RTC_CLOCK = 0x160U, /**< Rtc clock, pulse,support async */ + PIS_RTC_ALARM = 0x161U, /**< Rtc alarm, pulse,support async */ + PIS_LPTIM0_SYN_UPDATA = 0x170U, /**< Lptimer0 syn updata, pulse,support async */ + PIS_LPTIM0_ASY_UPDATA = 0x171U, /**< Lptimer0 asy updata, pulse,support async */ + PIS_LPUART0_ASY_RECV = 0x180U, /**< Lpuart0 asy recv, pulse,support async */ + PIS_LPUART0_ASY_SEND = 0x181U, /**< Lpuart0 asy send, pulse,support async */ + PIS_LPUART0_SYN_RECV = 0x182U, /**< Lpuart0 syn recv, pulse,support async */ + PIS_LPUART0_SYN_SEND = 0x183U, /**< Lpuart0 syn recv, pulse,support async */ + PIS_DMA = 0x190U, /**< Dma, pulse,support async */ + PIS_ADC1_INJECT = 0x1a0U, /**< Adc1 inject, pclk2 pulse,support async */ + PIS_ADC1_REGULAT = 0x1a1U, /**< Adc1 regulat, pclk2 pulse,support async */ + PIS_ADC1_WINDOW = 0x1a2U, /**< Adc1 window, no have */ } pis_src_t; /** * @brief Consumer entry - * @note ES32F065x: - * AD16C4T0--TIMER0 - * GP16C4T0--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - * - * ES32F033x: - * ES32F093x: - * GP16C4T0--TIMER0 - * GP16C4T1--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 */ -typedef enum -{ - PIS_CH0_TIMER0_BRKIN = 0x0400, /**< Timer0 brkin */ - PIS_CH0_SPI1_CLK = 0x0F10, /**< Spi1 clk */ - PIS_CH0_LPTIM0_EXT0 = 0x0030, /**< Lptimer0 ext0 */ - PIS_CH0_ADC1_NORMAL = 0x0030, /**< Adc1 normal */ - PIS_CH1_TIMER0_CH1IN = 0x0001, /**< Timer0 ch1in */ - PIS_CH1_TIMER2_CH1IN = 0x1001, /**< Timer2 ch1in */ - PIS_CH1_TIMER3_CH1IN = 0x1801, /**< Timer3 ch1in */ - PIS_CH1_LPTIM0_EXT1 = 0x0031, /**< Lptime0 ext1 */ - PIS_CH1_UART0_RX_IRDA = 0x0011, /**< Uart0 rx irda */ - PIS_CH1_ADC1_INSERT = 0x0031, /**< Adc1 insert */ - PIS_CH2_TIMER0_CH2IN = 0x0102, /**< Timer0 ch2in */ - PIS_CH2_TIMER2_CH2IN = 0x1102, /**< Timer2 ch2in */ - PIS_CH2_TIMER3_CH2IN = 0x1902, /**< Timer3 ch2in */ - PIS_CH2_LPTIM0_EXT2 = 0x0032, /**< Lptime0 ext2 */ - PIS_CH2_UART1_RX_IRDA = 0x0112, /**< Uart1 rx irda */ - PIS_CH3_TIMER0_CH3IN = 0x0203, /**< Timer0 ch3in */ - PIS_CH3_LPTIM0_EXT3 = 0x0033, /**< Lptime0 ext3 */ - PIS_CH3_UART2_RX_IRDA = 0x0213, /**< Uart2 rx irda */ - PIS_CH4_TIMER0_CH4IN = 0x0004, /**< Timer0 ch4in */ - PIS_CH4_TIMER0_ITR0 = 0x0034, /**< Timer0 itr0 */ - PIS_CH4_TIMER2_ITR0 = 0x0034, /**< Timer2 itr0 */ - PIS_CH4_TIMER3_ITR0 = 0x0034, /**< Timer3 itr0 */ - PIS_CH4_LPTIM0_EXT4 = 0x0434, /**< Lptime0 ext4 */ - PIS_CH4_UART3_RX_IRDA = 0x0314, /**< Uart3 rx irda */ - PIS_CH5_SPI0_RX = 0x0C15, /**< Spi0 rx */ - PIS_CH5_LPTIM0_EXT5 = 0x0035, /**< Lptime0 ext5 */ - PIS_CH5_EUART0_RX = 0x0615, /**< Euart0 rx */ - PIS_CH5_TIMER0_ITR1 = 0x0035, /**< Timer0 itr1 */ - PIS_CH5_TIMER2_ITR1 = 0x0035, /**< Timer2 itr1 */ - PIS_CH5_TIMER3_ITR1 = 0x0035, /**< Timer3 itr1 */ - PIS_CH6_SPI0_CLK = 0x0D16, /**< Spi0 clk */ - PIS_CH6_ADC0_NORMAL = 0x0036, /**< Adc0 normal */ - PIS_CH6_LPTIM0_EXT6 = 0x0036, /**< Lptime0 ext6 */ - PIS_CH6_EUART1_RX = 0x0716, /**< Euart1 rx */ - PIS_CH6_TIMER0_ITR2 = 0x0036, /**< Timer0 itr2 */ - PIS_CH6_TIMER2_ITR2 = 0x0036, /**< Timer2 itr2 */ - PIS_CH6_TIMER3_ITR2 = 0x0036, /**< Timer3 itr2 */ - PIS_CH6_DAC_CH1 = 0x0036, /**< Dac channel 1 */ - PIS_CH7_SPI1_RX = 0x0E17, /**< Spi1 rx */ - PIS_CH7_ADC0_INSERT = 0x0037, /**< Adc0 insert */ - PIS_CH7_LPTIM0_EXT7 = 0x0037, /**< Lptime0 ext7 */ - PIS_CH7_DMA = 0x0037, /**< Dma */ - PIS_CH7_TIMER0_ITR3 = 0x0037, /**< Timer0 itr3 */ - PIS_CH7_TIMER2_ITR3 = 0x0037, /**< Timer2 itr3 */ - PIS_CH7_TIMER3_ITR3 = 0x0037, /**< Timer3 itr3 */ - PIS_CH7_LPUART_RX = 0x0817, /**< Lpuart rx */ - PIS_CH7_DAC_CH0 = 0x0037, /**< Dac channel 0 */ +typedef enum { + PIS_CH0_TIMER0_BRKIN = 0x0400U, /**< Timer0 brkin */ + PIS_CH0_SPI1_CLK = 0x0F10U, /**< Spi1 clk */ + PIS_CH0_LPTIM0_EXT0 = 0x0030U, /**< Lptimer0 ext0 */ + PIS_CH0_ADC1_NORMAL = 0x0030U, /**< Adc1 normal */ + PIS_CH1_TIMER0_CH1IN = 0x0001U, /**< Timer0 ch1in */ + PIS_CH1_TIMER2_CH1IN = 0x1001U, /**< Timer2 ch1in */ + PIS_CH1_TIMER3_CH1IN = 0x1801U, /**< Timer3 ch1in */ + PIS_CH1_LPTIM0_EXT1 = 0x0031U, /**< Lptime0 ext1 */ + PIS_CH1_UART0_RX_IRDA = 0x0011U, /**< Uart0 rx irda */ + PIS_CH1_ADC1_INSERT = 0x0031U, /**< Adc1 insert */ + PIS_CH2_TIMER0_CH2IN = 0x0102U, /**< Timer0 ch2in */ + PIS_CH2_TIMER2_CH2IN = 0x1102U, /**< Timer2 ch2in */ + PIS_CH2_TIMER3_CH2IN = 0x1902U, /**< Timer3 ch2in */ + PIS_CH2_LPTIM0_EXT2 = 0x0032U, /**< Lptime0 ext2 */ + PIS_CH2_UART1_RX_IRDA = 0x0112U, /**< Uart1 rx irda */ + PIS_CH3_TIMER0_CH3IN = 0x0203U, /**< Timer0 ch3in */ + PIS_CH3_LPTIM0_EXT3 = 0x0033U, /**< Lptime0 ext3 */ + PIS_CH3_UART2_RX_IRDA = 0x0213U, /**< Uart2 rx irda */ + PIS_CH4_TIMER0_CH4IN = 0x0004U, /**< Timer0 ch4in */ + PIS_CH4_TIMER0_ITR0 = 0x0034U, /**< Timer0 itr0 */ + PIS_CH4_TIMER2_ITR0 = 0x0034U, /**< Timer2 itr0 */ + PIS_CH4_TIMER3_ITR0 = 0x0034U, /**< Timer3 itr0 */ + PIS_CH4_LPTIM0_EXT4 = 0x0434U, /**< Lptime0 ext4 */ + PIS_CH4_UART3_RX_IRDA = 0x0314U, /**< Uart3 rx irda */ + PIS_CH5_SPI0_RX = 0x0C15U, /**< Spi0 rx */ + PIS_CH5_LPTIM0_EXT5 = 0x0035U, /**< Lptime0 ext5 */ + PIS_CH5_EUART0_RX = 0x0615U, /**< Euart0 rx */ + PIS_CH5_TIMER0_ITR1 = 0x0035U, /**< Timer0 itr1 */ + PIS_CH5_TIMER2_ITR1 = 0x0035U, /**< Timer2 itr1 */ + PIS_CH5_TIMER3_ITR1 = 0x0035U, /**< Timer3 itr1 */ + PIS_CH6_SPI0_CLK = 0x0D16U, /**< Spi0 clk */ + PIS_CH6_ADC0_NORMAL = 0x0036U, /**< Adc0 normal */ + PIS_CH6_LPTIM0_EXT6 = 0x0036U, /**< Lptime0 ext6 */ + PIS_CH6_EUART1_RX = 0x0716U, /**< Euart1 rx */ + PIS_CH6_TIMER0_ITR2 = 0x0036U, /**< Timer0 itr2 */ + PIS_CH6_TIMER2_ITR2 = 0x0036U, /**< Timer2 itr2 */ + PIS_CH6_TIMER3_ITR2 = 0x0036U, /**< Timer3 itr2 */ + PIS_CH6_DAC_CH1 = 0x0036U, /**< Dac channel 1 */ + PIS_CH7_SPI1_RX = 0x0E17U, /**< Spi1 rx */ + PIS_CH7_ADC0_INSERT = 0x0037U, /**< Adc0 insert */ + PIS_CH7_LPTIM0_EXT7 = 0x0037U, /**< Lptime0 ext7 */ + PIS_CH7_DMA = 0x0037U, /**< Dma */ + PIS_CH7_TIMER0_ITR3 = 0x0037U, /**< Timer0 itr3 */ + PIS_CH7_TIMER2_ITR3 = 0x0037U, /**< Timer2 itr3 */ + PIS_CH7_TIMER3_ITR3 = 0x0037U, /**< Timer3 itr3 */ + PIS_CH7_LPUART_RX = 0x0817U, /**< Lpuart rx */ + PIS_CH7_DAC_CH0 = 0x0037U, /**< Dac channel 0 */ } pis_trig_t; /** * @brief Clock select */ -typedef enum -{ - PIS_CLK_PCLK1 = 0, /**< Pclock1 */ - PIS_CLK_PCLK2 = 1, /**< Pclock2 */ - PIS_CLK_SYS = 2, /**< Sys clock */ - PIS_CLK_LP = 3, /**< Low power clock */ +typedef enum { + PIS_CLK_PCLK1 = 0U, /**< Pclock1 */ + PIS_CLK_PCLK2 = 1U, /**< Pclock2 */ + PIS_CLK_SYS = 2U, /**< Sys clock */ + PIS_CLK_LP = 3U, /**< Low power clock */ } pis_clock_t; /** * @brief Level select */ -typedef enum -{ - PIS_EDGE_NONE = 0, /**< None edge */ - PIS_EDGE_UP = 1, /**< Up edge */ - PIS_EDGE_DOWN = 2, /**< Down edge */ - PIS_EDGE_UP_DOWN = 3, /**< Up and down edge */ +typedef enum { + PIS_EDGE_NONE = 0U, /**< None edge */ + PIS_EDGE_UP = 1U, /**< Up edge */ + PIS_EDGE_DOWN = 2U, /**< Down edge */ + PIS_EDGE_UP_DOWN = 3U, /**< Up and down edge */ } pis_edge_t; /** * @brief Output style */ -typedef enum -{ - PIS_OUT_LEVEL = 0, /**< Level */ - PIS_OUT_PULSE = 1, /**< Pulse */ +typedef enum { + PIS_OUT_LEVEL = 0U, /**< Level */ + PIS_OUT_PULSE = 1U, /**< Pulse */ } pis_output_t; /** * @brief Sync select */ -typedef enum -{ - PIS_SYN_DIRECT = 0, /**< Direct */ - PIS_SYN_ASY_PCLK1 = 1, /**< Asy pclk1 */ - PIS_SYN_ASY_PCLK2 = 2, /**< Asy pclk2 */ - PIS_SYN_ASY_PCLK = 3, /**< Asy pclk */ - PIS_SYN_PCLK2_PCLK1 = 4, /**< Pclk2 to pclk1 */ - PIS_SYN_PCLK1_PCLK2 = 5, /**< Pclk1 to pclk2 */ - PIS_SYN_PCLK12_SYS = 6, /**< Pclk1 or pclk2 to sysclk */ +typedef enum { + PIS_SYN_DIRECT = 0U, /**< Direct */ + PIS_SYN_ASY_PCLK1 = 1U, /**< Asy pclk1 */ + PIS_SYN_ASY_PCLK2 = 2U, /**< Asy pclk2 */ + PIS_SYN_ASY_PCLK = 3U, /**< Asy pclk */ + PIS_SYN_PCLK2_PCLK1 = 4U, /**< Pclk2 to pclk1 */ + PIS_SYN_PCLK1_PCLK2 = 5U, /**< Pclk1 to pclk2 */ + PIS_SYN_PCLK12_SYS = 6U, /**< Pclk1 or pclk2 to sysclk */ } pis_syncsel_t; /** * @brief Pis channel */ -typedef enum -{ - PIS_CH_0 = 0, /**< Channel 0 */ - PIS_CH_1 = 1, /**< Channel 1 */ - PIS_CH_2 = 2, /**< Channel 2 */ - PIS_CH_3 = 3, /**< Channel 3 */ - PIS_CH_4 = 4, /**< Channel 4 */ - PIS_CH_5 = 5, /**< Channel 5 */ - PIS_CH_6 = 6, /**< Channel 6 */ - PIS_CH_7 = 7, /**< Channel 7 */ +typedef enum { + PIS_CH_0 = 0U, /**< Channel 0 */ + PIS_CH_1 = 1U, /**< Channel 1 */ + PIS_CH_2 = 2U, /**< Channel 2 */ + PIS_CH_3 = 3U, /**< Channel 3 */ + PIS_CH_4 = 4U, /**< Channel 4 */ + PIS_CH_5 = 5U, /**< Channel 5 */ + PIS_CH_6 = 6U, /**< Channel 6 */ + PIS_CH_7 = 7U, /**< Channel 7 */ } pis_ch_t; /** * @brief Pis output channel */ -typedef enum -{ - PIS_OUT_CH_0 = 0, /**< Channel 0 */ - PIS_OUT_CH_1 = 1, /**< Channel 1 */ - PIS_OUT_CH_2 = 2, /**< Channel 2 */ - PIS_OUT_CH_3 = 3, /**< Channel 3 */ +typedef enum { + PIS_OUT_CH_0 = 0U, /**< Channel 0 */ + PIS_OUT_CH_1 = 1U, /**< Channel 1 */ + PIS_OUT_CH_2 = 2U, /**< Channel 2 */ + PIS_OUT_CH_3 = 3U, /**< Channel 3 */ } pis_out_ch_t; /** * @brief Indirect value,no care of it. */ -typedef enum -{ - PIS_CON_0 = 0, /**< Con 0 */ - PIS_CON_1 = 1, /**< Con 1 */ - PIS_CON_NONE = 2, /**< None */ +typedef enum { + PIS_CON_0 = 0U, /**< Con 0 */ + PIS_CON_1 = 1U, /**< Con 1 */ + PIS_CON_NONE = 2U, /**< None */ } pis_con_t; -/** - * @brief Indirect value,no care of it. - */ -typedef union -{ - struct - { - uint8_t ch : 4; /**< Channel */ - uint8_t con : 4; /**< Contorl */ - uint8_t shift : 8; /**< Shift */ - }; - uint16_t HalfWord; -} pis_divide_t; - /** * @brief PIS state structures definition */ -typedef enum -{ - PIS_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - PIS_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - PIS_STATE_BUSY = 0x02, /**< An internal process is ongoing */ - PIS_STATE_TIMEOUT = 0x03, /**< Timeout state */ - PIS_STATE_ERROR = 0x04, /**< Error */ +typedef enum { + PIS_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + PIS_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + PIS_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ + PIS_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + PIS_STATE_ERROR = 0x04U, /**< Error */ } pis_state_t; /** * @brief PIS modulate target */ -typedef enum -{ - PIS_UART0_TX = 0, /**< Modulate uart0 tx */ - PIS_UART1_TX = 1, /**< Modulate uart1 tx */ - PIS_UART2_TX = 2, /**< Modulate uart2 tx */ - PIS_UART3_TX = 3, /**< Modulate uart3 tx */ - PIS_LPUART0_TX = 4, /**< Modulate lpuart0 tx */ +typedef enum { + PIS_UART0_TX = 0U, /**< Modulate uart0 tx */ + PIS_UART1_TX = 1U, /**< Modulate uart1 tx */ + PIS_UART2_TX = 2U, /**< Modulate uart2 tx */ + PIS_UART3_TX = 3U, /**< Modulate uart3 tx */ + PIS_LPUART0_TX = 4U, /**< Modulate lpuart0 tx */ } pis_modu_targ_t; /** * @brief PIS modulate level */ -typedef enum -{ - PIS_LOW_LEVEL = 0, /**< Modulate low level */ - PIS_HIGH_LEVEL = 1, /**< Modulate high level */ +typedef enum { + PIS_LOW_LEVEL = 0U, /**< Modulate low level */ + PIS_HIGH_LEVEL = 1U, /**< Modulate high level */ } pis_modu_level_t; /** @@ -383,66 +333,61 @@ typedef enum * BS16T2----TIMER5 * BS16T3----TIMER7 */ -typedef enum -{ - PIS_SRC_NONE = 0, /**< Stop modulate */ - PIS_SRC_TIMER0 = 1, /**< Modulate source is TIMER0 */ - PIS_SRC_TIMER1 = 2, /**< Modulate source is TIMER1 */ - PIS_SRC_TIMER2 = 3, /**< Modulate source is TIMER2 */ - PIS_SRC_TIMER3 = 4, /**< Modulate source is TIMER3 */ - PIS_SRC_TIMER6 = 5, /**< Modulate source is TIMER6 */ - PIS_SRC_TIMER7 = 6, /**< Modulate source is TIMER7 */ - PIS_SRC_LPTIM0 = 7, /**< Modulate source is LPTIM0 */ - PIS_SRC_BUZ = 8, /**< Modulate source is buz */ +typedef enum { + PIS_SRC_NONE = 0U, /**< Stop modulate */ + PIS_SRC_TIMER0 = 1U, /**< Modulate source is TIMER0 */ + PIS_SRC_TIMER1 = 2U, /**< Modulate source is TIMER1 */ + PIS_SRC_TIMER2 = 3U, /**< Modulate source is TIMER2 */ + PIS_SRC_TIMER3 = 4U, /**< Modulate source is TIMER3 */ + PIS_SRC_TIMER6 = 5U, /**< Modulate source is TIMER6 */ + PIS_SRC_TIMER7 = 6U, /**< Modulate source is TIMER7 */ + PIS_SRC_LPTIM0 = 7U, /**< Modulate source is LPTIM0 */ + PIS_SRC_BUZ = 8U, /**< Modulate source is buz */ } pis_modu_src_t; /** * @brief PIS modulate channel */ -typedef enum -{ - PIS_TIMER_CH1 = 0, /**< Src is TIMERx and choose channel 1 */ - PIS_TIMER_CH2 = 1, /**< Src is TIMERx and choose channel 2 */ - PIS_TIMER_CH3 = 2, /**< Src is TIMERx and choose channel 3 */ - PIS_TIMER_CH4 = 3, /**< Src is TIMERx and choose channel 4 */ +typedef enum { + PIS_TIMER_CH1 = 0U, /**< Src is TIMERx and choose channel 1 */ + PIS_TIMER_CH2 = 1U, /**< Src is TIMERx and choose channel 2 */ + PIS_TIMER_CH3 = 2U, /**< Src is TIMERx and choose channel 3 */ + PIS_TIMER_CH4 = 3U, /**< Src is TIMERx and choose channel 4 */ } pis_modu_channel_t; /** * @brief PIS init structure definition */ -typedef struct -{ - pis_src_t producer_src; /**< Producer entry */ - pis_clock_t producer_clk; /**< Producer module clock */ - pis_edge_t producer_edge; /**< Producer module pin output edge */ - pis_trig_t consumer_trig; /**< Consumer entry */ - pis_clock_t consumer_clk; /**< Consumer clock */ +typedef struct { + pis_src_t producer_src; /**< Producer entry */ + pis_clock_t producer_clk; /**< Producer module clock */ + pis_edge_t producer_edge; /**< Producer module pin output edge */ + pis_trig_t consumer_trig; /**< Consumer entry */ + pis_clock_t consumer_clk; /**< Consumer clock */ } pis_init_t; /** * @brief PIS modulate config structure definition */ -typedef struct -{ - pis_modu_targ_t target; /**< Modulate target */ - pis_modu_level_t level; /**< Modulate level */ - pis_modu_src_t src; /**< Modulate src */ - pis_modu_channel_t channel; /**< Modulate channel */ +typedef struct { + pis_modu_targ_t target; /**< Modulate target */ + pis_modu_level_t level; /**< Modulate level */ + pis_modu_src_t src; /**< Modulate src */ + pis_modu_channel_t channel; /**< Modulate channel */ } pis_modulate_config_t; /** * @brief PIS Handle Structure definition */ -typedef struct pis_handle_s -{ - PIS_TypeDef *perh; /**< Register base address */ - pis_init_t init; /**< PIS required parameters */ - pis_ch_t consumer_ch; /**< Indirect value, no care of it */ - pis_con_t consumer_con; /**< Indirect value, no care of it */ - uint8_t consumer_pos; /**< Indirect value, no care of it */ - uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ - lock_state_t lock; /**< Locking object */ - pis_state_t state; /**< PIS operation state */ +typedef struct pis_handle_s { + PIS_TypeDef *perh; /**< Register base address */ + pis_init_t init; /**< PIS required parameters */ + pis_ch_t consumer_ch; /**< Indirect value, no care of it */ + pis_con_t consumer_con; /**< Indirect value, no care of it */ + uint8_t consumer_pos; /**< Indirect value, no care of it */ + uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ + lock_state_t lock; /**< Locking object */ + pis_state_t state; /**< PIS operation state */ } pis_handle_t; /** * @} @@ -454,183 +399,183 @@ typedef struct pis_handle_s */ #define IS_PIS(x) (((x) == PIS)) #define IS_PIS_SRC(x) (((x) == PIS_NON) || \ - ((x) == PIS_GPIO_PIN0) || \ - ((x) == PIS_GPIO_PIN1) || \ - ((x) == PIS_GPIO_PIN2) || \ - ((x) == PIS_GPIO_PIN3) || \ - ((x) == PIS_GPIO_PIN4) || \ - ((x) == PIS_GPIO_PIN5) || \ - ((x) == PIS_GPIO_PIN6) || \ - ((x) == PIS_GPIO_PIN7) || \ - ((x) == PIS_GPIO_PIN8) || \ - ((x) == PIS_GPIO_PIN9) || \ - ((x) == PIS_GPIO_PIN10) || \ - ((x) == PIS_GPIO_PIN11) || \ - ((x) == PIS_GPIO_PIN12) || \ - ((x) == PIS_GPIO_PIN13) || \ - ((x) == PIS_GPIO_PIN14) || \ - ((x) == PIS_GPIO_PIN15) || \ - ((x) == PIS_ACMP_OUT0) || \ - ((x) == PIS_ACMP_OUT1) || \ - ((x) == PIS_DAC0_CH1) || \ - ((x) == PIS_ACMP_OUT1) || \ - ((x) == PIS_ADC0_INJECT) || \ - ((x) == PIS_ADC0_REGULAT) || \ - ((x) == PIS_ADC0_WINDOW) || \ - ((x) == PIS_LVD) || \ - ((x) == PIS_UART0_ASY_SEND) || \ - ((x) == PIS_UART0_ASY_RECV) || \ - ((x) == PIS_UART0_IRDAOUT) || \ - ((x) == PIS_UART0_RTSOUT) || \ - ((x) == PIS_UART0_TXOUT) || \ - ((x) == PIS_UART0_SYN_SEND) || \ - ((x) == PIS_UART0_SYN_RECV) || \ - ((x) == PIS_UART1_ASY_SEND) || \ - ((x) == PIS_UART1_ASY_RECV) || \ - ((x) == PIS_UART1_IRDA) || \ - ((x) == PIS_UART1_RTS) || \ - ((x) == PIS_UART1_TXOUT) || \ - ((x) == PIS_UART1_SYN_SEND) || \ - ((x) == PIS_UART1_SYN_RECV) || \ - ((x) == PIS_UART2_ASY_SEND) || \ - ((x) == PIS_UART2_ASY_RECV) || \ - ((x) == PIS_UART2_IRDA) || \ - ((x) == PIS_UART2_RTS) || \ - ((x) == PIS_UART2_TXOUT) || \ - ((x) == PIS_UART2_SYN_SEND) || \ - ((x) == PIS_UART2_SYN_RECV) || \ - ((x) == PIS_UART3_ASY_SEND) || \ - ((x) == PIS_UART3_ASY_RECV) || \ - ((x) == PIS_UART3_IRDA) || \ - ((x) == PIS_UART3_RTS) || \ - ((x) == PIS_UART3_TXOUT) || \ - ((x) == PIS_UART3_SYN_SEND) || \ - ((x) == PIS_UART3_SYN_RECV) || \ - ((x) == PIS_EUART0_RECV) || \ - ((x) == PIS_EUART0_SEND) || \ - ((x) == PIS_EUART0_TXOUT) || \ - ((x) == PIS_EUART1_RECV) || \ - ((x) == PIS_EUART1_SEND) || \ - ((x) == PIS_EUART1_TXOUT) || \ - ((x) == PIS_SPI0_RECV) || \ - ((x) == PIS_SPI0_SEND) || \ - ((x) == PIS_SPI0_NE) || \ - ((x) == PIS_SPI1_RECV) || \ - ((x) == PIS_SPI1_SEND) || \ - ((x) == PIS_SPI1_NE) || \ - ((x) == PIS_I2C0_RECV) || \ - ((x) == PIS_I2C0_SEND) || \ - ((x) == PIS_I2C1_RECV) || \ - ((x) == PIS_I2C1_SEND) || \ - ((x) == PIS_TIMER0_UPDATA) || \ - ((x) == PIS_TIMER0_TRIG) || \ - ((x) == PIS_TIMER0_INPUT) || \ - ((x) == PIS_TIMER0_OUTPUT) || \ - ((x) == PIS_TIMER1_UPDATA) || \ - ((x) == PIS_TIMER1_TRIG) || \ - ((x) == PIS_TIMER1_INPUT) || \ - ((x) == PIS_TIMER1_OUTPUT) || \ - ((x) == PIS_TIMER2_UPDATA) || \ - ((x) == PIS_TIMER2_TRIG) || \ - ((x) == PIS_TIMER2_INPUT) || \ - ((x) == PIS_TIMER2_OUTPUT) || \ - ((x) == PIS_TIMER3_UPDATA) || \ - ((x) == PIS_TIMER3_TRIG) || \ - ((x) == PIS_TIMER3_INPUT) || \ - ((x) == PIS_TIMER3_OUTPUT) || \ - ((x) == PIS_RTC_CLOCK) || \ - ((x) == PIS_RTC_ALARM) || \ - ((x) == PIS_LPTIM0_SYN_UPDATA) || \ - ((x) == PIS_LPTIM0_ASY_UPDATA) || \ - ((x) == PIS_LPUART0_ASY_RECV) || \ - ((x) == PIS_LPUART0_ASY_SEND) || \ - ((x) == PIS_LPUART0_SYN_RECV) || \ - ((x) == PIS_LPUART0_SYN_SEND) || \ - ((x) == PIS_DMA) || \ - ((x) == PIS_ADC1_INJECT) || \ - ((x) == PIS_ADC1_REGULAT) || \ - ((x) == PIS_ADC1_WINDOW)) + ((x) == PIS_GPIO_PIN0) || \ + ((x) == PIS_GPIO_PIN1) || \ + ((x) == PIS_GPIO_PIN2) || \ + ((x) == PIS_GPIO_PIN3) || \ + ((x) == PIS_GPIO_PIN4) || \ + ((x) == PIS_GPIO_PIN5) || \ + ((x) == PIS_GPIO_PIN6) || \ + ((x) == PIS_GPIO_PIN7) || \ + ((x) == PIS_GPIO_PIN8) || \ + ((x) == PIS_GPIO_PIN9) || \ + ((x) == PIS_GPIO_PIN10) || \ + ((x) == PIS_GPIO_PIN11) || \ + ((x) == PIS_GPIO_PIN12) || \ + ((x) == PIS_GPIO_PIN13) || \ + ((x) == PIS_GPIO_PIN14) || \ + ((x) == PIS_GPIO_PIN15) || \ + ((x) == PIS_ACMP_OUT0) || \ + ((x) == PIS_ACMP_OUT1) || \ + ((x) == PIS_DAC0_CH1) || \ + ((x) == PIS_ACMP_OUT1) || \ + ((x) == PIS_ADC0_INJECT) || \ + ((x) == PIS_ADC0_REGULAT) || \ + ((x) == PIS_ADC0_WINDOW) || \ + ((x) == PIS_LVD) || \ + ((x) == PIS_UART0_ASY_SEND) || \ + ((x) == PIS_UART0_ASY_RECV) || \ + ((x) == PIS_UART0_IRDAOUT) || \ + ((x) == PIS_UART0_RTSOUT) || \ + ((x) == PIS_UART0_TXOUT) || \ + ((x) == PIS_UART0_SYN_SEND) || \ + ((x) == PIS_UART0_SYN_RECV) || \ + ((x) == PIS_UART1_ASY_SEND) || \ + ((x) == PIS_UART1_ASY_RECV) || \ + ((x) == PIS_UART1_IRDA) || \ + ((x) == PIS_UART1_RTS) || \ + ((x) == PIS_UART1_TXOUT) || \ + ((x) == PIS_UART1_SYN_SEND) || \ + ((x) == PIS_UART1_SYN_RECV) || \ + ((x) == PIS_UART2_ASY_SEND) || \ + ((x) == PIS_UART2_ASY_RECV) || \ + ((x) == PIS_UART2_IRDA) || \ + ((x) == PIS_UART2_RTS) || \ + ((x) == PIS_UART2_TXOUT) || \ + ((x) == PIS_UART2_SYN_SEND) || \ + ((x) == PIS_UART2_SYN_RECV) || \ + ((x) == PIS_UART3_ASY_SEND) || \ + ((x) == PIS_UART3_ASY_RECV) || \ + ((x) == PIS_UART3_IRDA) || \ + ((x) == PIS_UART3_RTS) || \ + ((x) == PIS_UART3_TXOUT) || \ + ((x) == PIS_UART3_SYN_SEND) || \ + ((x) == PIS_UART3_SYN_RECV) || \ + ((x) == PIS_EUART0_RECV) || \ + ((x) == PIS_EUART0_SEND) || \ + ((x) == PIS_EUART0_TXOUT) || \ + ((x) == PIS_EUART1_RECV) || \ + ((x) == PIS_EUART1_SEND) || \ + ((x) == PIS_EUART1_TXOUT) || \ + ((x) == PIS_SPI0_RECV) || \ + ((x) == PIS_SPI0_SEND) || \ + ((x) == PIS_SPI0_NE) || \ + ((x) == PIS_SPI1_RECV) || \ + ((x) == PIS_SPI1_SEND) || \ + ((x) == PIS_SPI1_NE) || \ + ((x) == PIS_I2C0_RECV) || \ + ((x) == PIS_I2C0_SEND) || \ + ((x) == PIS_I2C1_RECV) || \ + ((x) == PIS_I2C1_SEND) || \ + ((x) == PIS_TIMER0_UPDATA) || \ + ((x) == PIS_TIMER0_TRIG) || \ + ((x) == PIS_TIMER0_INPUT) || \ + ((x) == PIS_TIMER0_OUTPUT) || \ + ((x) == PIS_TIMER1_UPDATA) || \ + ((x) == PIS_TIMER1_TRIG) || \ + ((x) == PIS_TIMER1_INPUT) || \ + ((x) == PIS_TIMER1_OUTPUT) || \ + ((x) == PIS_TIMER2_UPDATA) || \ + ((x) == PIS_TIMER2_TRIG) || \ + ((x) == PIS_TIMER2_INPUT) || \ + ((x) == PIS_TIMER2_OUTPUT) || \ + ((x) == PIS_TIMER3_UPDATA) || \ + ((x) == PIS_TIMER3_TRIG) || \ + ((x) == PIS_TIMER3_INPUT) || \ + ((x) == PIS_TIMER3_OUTPUT) || \ + ((x) == PIS_RTC_CLOCK) || \ + ((x) == PIS_RTC_ALARM) || \ + ((x) == PIS_LPTIM0_SYN_UPDATA) || \ + ((x) == PIS_LPTIM0_ASY_UPDATA) || \ + ((x) == PIS_LPUART0_ASY_RECV) || \ + ((x) == PIS_LPUART0_ASY_SEND) || \ + ((x) == PIS_LPUART0_SYN_RECV) || \ + ((x) == PIS_LPUART0_SYN_SEND) || \ + ((x) == PIS_DMA) || \ + ((x) == PIS_ADC1_INJECT) || \ + ((x) == PIS_ADC1_REGULAT) || \ + ((x) == PIS_ADC1_WINDOW)) #define IS_PIS_TRIG(x) (((x) == PIS_CH0_TIMER0_BRKIN) || \ - ((x) == PIS_CH0_SPI1_CLK) || \ - ((x) == PIS_CH0_LPTIM0_EXT0) || \ - ((x) == PIS_CH0_ADC1_NORMAL) || \ - ((x) == PIS_CH1_TIMER0_CH1IN) || \ - ((x) == PIS_CH1_TIMER2_CH1IN) || \ - ((x) == PIS_CH1_TIMER3_CH1IN) || \ - ((x) == PIS_CH1_UART0_RX_IRDA) || \ - ((x) == PIS_CH1_LPTIM0_EXT1) || \ - ((x) == PIS_CH1_ADC1_INSERT) || \ - ((x) == PIS_CH2_TIMER0_CH2IN) || \ - ((x) == PIS_CH2_TIMER2_CH2IN) || \ - ((x) == PIS_CH2_TIMER3_CH2IN) || \ - ((x) == PIS_CH2_LPTIM0_EXT2) || \ - ((x) == PIS_CH2_UART1_RX_IRDA) || \ - ((x) == PIS_CH3_TIMER0_CH3IN) || \ - ((x) == PIS_CH3_LPTIM0_EXT3) || \ - ((x) == PIS_CH3_UART2_RX_IRDA) || \ - ((x) == PIS_CH4_TIMER0_CH4IN) || \ - ((x) == PIS_CH4_TIMER0_ITR0) || \ - ((x) == PIS_CH4_TIMER2_ITR0) || \ - ((x) == PIS_CH4_TIMER3_ITR0) || \ - ((x) == PIS_CH4_LPTIM0_EXT4) || \ - ((x) == PIS_CH4_UART3_RX_IRDA) || \ - ((x) == PIS_CH5_SPI0_RX) || \ - ((x) == PIS_CH5_LPTIM0_EXT5) || \ - ((x) == PIS_CH5_EUART0_RX) || \ - ((x) == PIS_CH5_TIMER0_ITR1) || \ - ((x) == PIS_CH5_TIMER2_ITR1) || \ - ((x) == PIS_CH5_TIMER3_ITR1) || \ - ((x) == PIS_CH6_SPI0_CLK) || \ - ((x) == PIS_CH6_ADC0_NORMAL) || \ - ((x) == PIS_CH6_LPTIM0_EXT6) || \ - ((x) == PIS_CH6_EUART1_RX) || \ - ((x) == PIS_CH6_TIMER0_ITR2) || \ - ((x) == PIS_CH6_TIMER2_ITR2) || \ - ((x) == PIS_CH6_TIMER3_ITR2) || \ - ((x) == PIS_CH6_DAC_CH1) || \ - ((x) == PIS_CH7_SPI1_RX) || \ - ((x) == PIS_CH7_ADC0_INSERT) || \ - ((x) == PIS_CH7_LPTIM0_EXT7) || \ - ((x) == PIS_CH7_DMA) || \ - ((x) == PIS_CH7_TIMER0_ITR3) || \ - ((x) == PIS_CH7_TIMER2_ITR3) || \ - ((x) == PIS_CH7_TIMER3_ITR3) || \ - ((x) == PIS_CH7_DAC_CH0) || \ - ((x) == PIS_CH7_LPUART_RX)) + ((x) == PIS_CH0_SPI1_CLK) || \ + ((x) == PIS_CH0_LPTIM0_EXT0) || \ + ((x) == PIS_CH0_ADC1_NORMAL) || \ + ((x) == PIS_CH1_TIMER0_CH1IN) || \ + ((x) == PIS_CH1_TIMER2_CH1IN) || \ + ((x) == PIS_CH1_TIMER3_CH1IN) || \ + ((x) == PIS_CH1_UART0_RX_IRDA) || \ + ((x) == PIS_CH1_LPTIM0_EXT1) || \ + ((x) == PIS_CH1_ADC1_INSERT) || \ + ((x) == PIS_CH2_TIMER0_CH2IN) || \ + ((x) == PIS_CH2_TIMER2_CH2IN) || \ + ((x) == PIS_CH2_TIMER3_CH2IN) || \ + ((x) == PIS_CH2_LPTIM0_EXT2) || \ + ((x) == PIS_CH2_UART1_RX_IRDA) || \ + ((x) == PIS_CH3_TIMER0_CH3IN) || \ + ((x) == PIS_CH3_LPTIM0_EXT3) || \ + ((x) == PIS_CH3_UART2_RX_IRDA) || \ + ((x) == PIS_CH4_TIMER0_CH4IN) || \ + ((x) == PIS_CH4_TIMER0_ITR0) || \ + ((x) == PIS_CH4_TIMER2_ITR0) || \ + ((x) == PIS_CH4_TIMER3_ITR0) || \ + ((x) == PIS_CH4_LPTIM0_EXT4) || \ + ((x) == PIS_CH4_UART3_RX_IRDA) || \ + ((x) == PIS_CH5_SPI0_RX) || \ + ((x) == PIS_CH5_LPTIM0_EXT5) || \ + ((x) == PIS_CH5_EUART0_RX) || \ + ((x) == PIS_CH5_TIMER0_ITR1) || \ + ((x) == PIS_CH5_TIMER2_ITR1) || \ + ((x) == PIS_CH5_TIMER3_ITR1) || \ + ((x) == PIS_CH6_SPI0_CLK) || \ + ((x) == PIS_CH6_ADC0_NORMAL) || \ + ((x) == PIS_CH6_LPTIM0_EXT6) || \ + ((x) == PIS_CH6_EUART1_RX) || \ + ((x) == PIS_CH6_TIMER0_ITR2) || \ + ((x) == PIS_CH6_TIMER2_ITR2) || \ + ((x) == PIS_CH6_TIMER3_ITR2) || \ + ((x) == PIS_CH6_DAC_CH1) || \ + ((x) == PIS_CH7_SPI1_RX) || \ + ((x) == PIS_CH7_ADC0_INSERT) || \ + ((x) == PIS_CH7_LPTIM0_EXT7) || \ + ((x) == PIS_CH7_DMA) || \ + ((x) == PIS_CH7_TIMER0_ITR3) || \ + ((x) == PIS_CH7_TIMER2_ITR3) || \ + ((x) == PIS_CH7_TIMER3_ITR3) || \ + ((x) == PIS_CH7_DAC_CH0) || \ + ((x) == PIS_CH7_LPUART_RX)) #define IS_PIS_CLOCK(x) (((x) == PIS_CLK_PCLK1) || \ - ((x) == PIS_CLK_PCLK2) || \ - ((x) == PIS_CLK_SYS) || \ - ((x) == PIS_CLK_LP)) + ((x) == PIS_CLK_PCLK2) || \ + ((x) == PIS_CLK_SYS) || \ + ((x) == PIS_CLK_LP)) #define IS_PIS_EDGE(x) (((x) == PIS_EDGE_NONE) || \ - ((x) == PIS_EDGE_UP) || \ - ((x) == PIS_EDGE_DOWN) || \ - ((x) == PIS_EDGE_UP_DOWN)) + ((x) == PIS_EDGE_UP) || \ + ((x) == PIS_EDGE_DOWN) || \ + ((x) == PIS_EDGE_UP_DOWN)) #define IS_PIS_OUTPUT(x) (((x) == PIS_OUT_LEVEL) || \ - ((x) == PIS_OUT_PULSE)) + ((x) == PIS_OUT_PULSE)) #define IS_PIS_OUPUT_CH(x) (((x) == PIS_OUT_CH_0) || \ - ((x) == PIS_OUT_CH_1) || \ - ((x) == PIS_OUT_CH_2) || \ - ((x) == PIS_OUT_CH_3)) + ((x) == PIS_OUT_CH_1) || \ + ((x) == PIS_OUT_CH_2) || \ + ((x) == PIS_OUT_CH_3)) #define IS_PIS_MODU_TARGET(x) (((x) == PIS_UART0_TX) || \ - ((x) == PIS_UART1_TX) || \ - ((x) == PIS_UART2_TX) || \ - ((x) == PIS_UART3_TX) || \ - ((x) == PIS_LPUART0_TX)) + ((x) == PIS_UART1_TX) || \ + ((x) == PIS_UART2_TX) || \ + ((x) == PIS_UART3_TX) || \ + ((x) == PIS_LPUART0_TX)) #define IS_PIS_MODU_LEVEL(x) (((x) == PIS_LOW_LEVEL) || \ - ((x) == PIS_HIGH_LEVEL)) + ((x) == PIS_HIGH_LEVEL)) #define IS_PIS_MODU_SRC(x) (((x) == PIS_SRC_NONE) || \ - ((x) == PIS_SRC_TIMER0) || \ - ((x) == PIS_SRC_TIMER1) || \ - ((x) == PIS_SRC_TIMER2) || \ - ((x) == PIS_SRC_TIMER3) || \ - ((x) == PIS_SRC_TIMER6) || \ - ((x) == PIS_SRC_TIMER7) || \ - ((x) == PIS_SRC_LPTIM0) || \ - ((x) == PIS_SRC_BUZ)) + ((x) == PIS_SRC_TIMER0) || \ + ((x) == PIS_SRC_TIMER1) || \ + ((x) == PIS_SRC_TIMER2) || \ + ((x) == PIS_SRC_TIMER3) || \ + ((x) == PIS_SRC_TIMER6) || \ + ((x) == PIS_SRC_TIMER7) || \ + ((x) == PIS_SRC_LPTIM0) || \ + ((x) == PIS_SRC_BUZ)) #define IS_PIS_MODU_CHANNEL(x) (((x) == PIS_TIMER_CH1) || \ - ((x) == PIS_TIMER_CH2) || \ - ((x) == PIS_TIMER_CH3) || \ - ((x) == PIS_TIMER_CH4)) + ((x) == PIS_TIMER_CH2) || \ + ((x) == PIS_TIMER_CH3) || \ + ((x) == PIS_TIMER_CH4)) /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h index 85c962657879017c50feae5ab7b9380af454b5c7..264c185b81ff0d45bd51c0ad24b821d43303fe74 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h @@ -23,6 +23,7 @@ extern "C" { #include "utils.h" #include "ald_syscfg.h" +#include "ald_bkpc.h" /** @addtogroup ES32FXXX_ALD @@ -37,41 +38,41 @@ extern "C" { * @{ */ #define PMU_SRAM0_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \ + SYSCFG_LOCK(); \ +} while (0) #define PMU_SRAM0_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\ + SYSCFG_LOCK(); \ +} while (0) #define PMU_SRAM1_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \ + SYSCFG_LOCK(); \ +} while (0) #define PMU_SRAM1_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\ + SYSCFG_LOCK(); \ +} while (0) #define PMU_BXCAN_ENABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define PMU_BXCAN_DISABLE() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS)) /** @@ -85,46 +86,44 @@ extern "C" { /** * @brief Low power mode */ -typedef enum -{ - PMU_LP_STOP1 = 0x0, /**< Stop1 */ - PMU_LP_STOP2 = 0x1, /**< Stop2 */ +typedef enum { + PMU_LP_STOP1 = 0x0U, /**< Stop1 */ + PMU_LP_STOP2 = 0x1U, /**< Stop2 */ + PMU_LP_STANDBY = 0x2U, /**< Standby */ } pmu_lp_mode_t; -typedef enum -{ - PMU_SR_WUF = (1U << 0), +typedef enum { + PMU_SR_WUF = (1U << 0), + PMU_SR_STANDBY = (1U << 1), } pmu_status_t; /** * @brief LVD voltage select */ -typedef enum -{ - PMU_LVD_VOL_SEL_2_0 = 0x0, /**< 2.0V ~ 2.05V */ - PMU_LVD_VOL_SEL_2_1 = 0x1, /**< 2.1V ~ 2.15V */ - PMU_LVD_VOL_SEL_2_2 = 0x2, /**< 2.2V ~ 2.25V */ - PMU_LVD_VOL_SEL_2_4 = 0x3, /**< 2.4V ~ 2.45V */ - PMU_LVD_VOL_SEL_2_6 = 0x4, /**< 2.6V ~ 2.65V */ - PMU_LVD_VOL_SEL_2_8 = 0x5, /**< 2.8V ~ 2.85V */ - PMU_LVD_VOL_SEL_3_0 = 0x6, /**< 3.0V ~ 3.05V */ - PMU_LVD_VOL_SEL_3_6 = 0x7, /**< 3.6V ~ 3.65V */ - PMU_LVD_VOL_SEL_4_0 = 0x8, /**< 4.0V ~ 4.05V */ - PMU_LVD_VOL_SEL_4_6 = 0x9, /**< 4.6V ~ 4.65V */ - PMU_LVD_VOL_SEL_2_3 = 0xA, /**< 2.3V ~ 2.35V */ - PMU_LVD_VOL_SEL_EXT = 0xF, /**< Select external input. It must be 1.2V */ +typedef enum { + PMU_LVD_VOL_SEL_2_0 = 0x0U, /**< 2.0V ~ 2.05V */ + PMU_LVD_VOL_SEL_2_1 = 0x1U, /**< 2.1V ~ 2.15V */ + PMU_LVD_VOL_SEL_2_2 = 0x2U, /**< 2.2V ~ 2.25V */ + PMU_LVD_VOL_SEL_2_4 = 0x3U, /**< 2.4V ~ 2.45V */ + PMU_LVD_VOL_SEL_2_6 = 0x4U, /**< 2.6V ~ 2.65V */ + PMU_LVD_VOL_SEL_2_8 = 0x5U, /**< 2.8V ~ 2.85V */ + PMU_LVD_VOL_SEL_3_0 = 0x6U, /**< 3.0V ~ 3.05V */ + PMU_LVD_VOL_SEL_3_6 = 0x7U, /**< 3.6V ~ 3.65V */ + PMU_LVD_VOL_SEL_4_0 = 0x8U, /**< 4.0V ~ 4.05V */ + PMU_LVD_VOL_SEL_4_6 = 0x9U, /**< 4.6V ~ 4.65V */ + PMU_LVD_VOL_SEL_2_3 = 0xAU, /**< 2.3V ~ 2.35V */ + PMU_LVD_VOL_SEL_EXT = 0xFU, /**< Select external input. It must be 1.2V */ } pmu_lvd_voltage_sel_t; /** * @brief LVD trigger mode */ -typedef enum -{ - PMU_LVD_TRIGGER_RISING_EDGE = 0x0, /**< Rising edge */ - PMU_LVD_TRIGGER_FALLING_EDGE = 0x1, /**< Falling edge */ - PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2, /**< High level */ - PMU_LVD_TRIGGER_LOW_LEVEL = 0x3, /**< Low level */ - PMU_LVD_TRIGGER_RISING_FALLING = 0x4, /**< Rising and falling edge */ +typedef enum { + PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, /**< Rising edge */ + PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, /**< Falling edge */ + PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, /**< High level */ + PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U, /**< Low level */ + PMU_LVD_TRIGGER_RISING_FALLING = 0x4U, /**< Rising and falling edge */ } pmu_lvd_trigger_mode_t; /** @@ -136,25 +135,26 @@ typedef enum * @{ */ #define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \ - ((x) == PMU_LP_STOP2)) -#define IS_PMU_STATUS(x) ((x) == PMU_SR_WUF) + ((x) == PMU_LP_STOP2) || \ + ((x) == PMU_LP_STANDBY)) +#define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || ((x) == PMU_SR_STANDBY)) #define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_0) || \ - ((x) == PMU_LVD_VOL_SEL_2_1) || \ - ((x) == PMU_LVD_VOL_SEL_2_2) || \ - ((x) == PMU_LVD_VOL_SEL_2_4) || \ - ((x) == PMU_LVD_VOL_SEL_2_6) || \ - ((x) == PMU_LVD_VOL_SEL_2_8) || \ - ((x) == PMU_LVD_VOL_SEL_3_0) || \ - ((x) == PMU_LVD_VOL_SEL_3_6) || \ - ((x) == PMU_LVD_VOL_SEL_4_0) || \ - ((x) == PMU_LVD_VOL_SEL_4_6) || \ - ((x) == PMU_LVD_VOL_SEL_2_3) || \ - ((x) == PMU_LVD_VOL_SEL_EXT)) + ((x) == PMU_LVD_VOL_SEL_2_1) || \ + ((x) == PMU_LVD_VOL_SEL_2_2) || \ + ((x) == PMU_LVD_VOL_SEL_2_4) || \ + ((x) == PMU_LVD_VOL_SEL_2_6) || \ + ((x) == PMU_LVD_VOL_SEL_2_8) || \ + ((x) == PMU_LVD_VOL_SEL_3_0) || \ + ((x) == PMU_LVD_VOL_SEL_3_6) || \ + ((x) == PMU_LVD_VOL_SEL_4_0) || \ + ((x) == PMU_LVD_VOL_SEL_4_6) || \ + ((x) == PMU_LVD_VOL_SEL_2_3) || \ + ((x) == PMU_LVD_VOL_SEL_EXT)) #define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \ - ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \ - ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \ - ((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \ - ((x) == PMU_LVD_TRIGGER_RISING_FALLING)) + ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \ + ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \ + ((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \ + ((x) == PMU_LVD_TRIGGER_RISING_FALLING)) /** * @} */ @@ -168,17 +168,18 @@ typedef enum /* Low power mode select */ __STATIC_INLINE__ void ald_pmu_sleep() { - __WFI(); + __WFI(); } __STATIC_INLINE__ void ald_pmu_sleep_deep() { - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); } void ald_pmu_stop1_enter(void); void ald_pmu_stop2_enter(void); +void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level); flag_status_t ald_pmu_get_status(pmu_status_t sr); void ald_pmu_clear_status(pmu_status_t sr); /** diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h index b6a7060e4e0ee60c584355ce62d266ab40cce573..164ebb5e3fe5513ec4dc3c421b13ec85a6cce93b 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h @@ -37,127 +37,128 @@ extern "C" { /** * @brief RMU BOR fliter */ -typedef enum -{ - RMU_BORFLT_1 = 0x1, /**< 1 cycle */ - RMU_BORFLT_2 = 0x2, /**< 2 cycles */ - RMU_BORFLT_3 = 0x3, /**< 3 cycles */ - RMU_BORFLT_4 = 0x4, /**< 4 cycles */ - RMU_BORFLT_5 = 0x5, /**< 5 cycles */ - RMU_BORFLT_6 = 0x6, /**< 6 cycles */ - RMU_BORFLT_7 = 0x7, /**< 7 cycles */ +typedef enum { + RMU_BORFLT_1 = 0x1U, /**< 1 cycle */ + RMU_BORFLT_2 = 0x2U, /**< 2 cycles */ + RMU_BORFLT_3 = 0x3U, /**< 3 cycles */ + RMU_BORFLT_4 = 0x4U, /**< 4 cycles */ + RMU_BORFLT_5 = 0x5U, /**< 5 cycles */ + RMU_BORFLT_6 = 0x6U, /**< 6 cycles */ + RMU_BORFLT_7 = 0x7U, /**< 7 cycles */ } rmu_bor_filter_t; /** * @brief RMU BOR voltage */ -typedef enum -{ - RMU_VOL_1_7 = 0x0, /**< 1.7V */ - RMU_VOL_2_0 = 0x1, /**< 2.0V */ - RMU_VOL_2_1 = 0x2, /**< 2.1V */ - RMU_VOL_2_2 = 0x3, /**< 2.2V */ - RMU_VOL_2_3 = 0x4, /**< 2.3V */ - RMU_VOL_2_4 = 0x5, /**< 2.4V */ - RMU_VOL_2_5 = 0x6, /**< 2.5V */ - RMU_VOL_2_6 = 0x7, /**< 2.6V */ - RMU_VOL_2_8 = 0x8, /**< 2.8V */ - RMU_VOL_3_0 = 0x9, /**< 3.0V */ - RMU_VOL_3_1 = 0xA, /**< 3.1V */ - RMU_VOL_3_3 = 0xB, /**< 3.3V */ - RMU_VOL_3_6 = 0xC, /**< 3.6V */ - RMU_VOL_3_7 = 0xD, /**< 3.7V */ - RMU_VOL_4_0 = 0xE, /**< 4.0V */ - RMU_VOL_4_3 = 0xF, /**< 4.3V */ +typedef enum { + RMU_VOL_1_8 = 0x0U, /**< 1.8V */ + RMU_VOL_2_0 = 0x1U, /**< 2.0V */ + RMU_VOL_2_2 = 0x2U, /**< 2.2V */ + RMU_VOL_2_4 = 0x3U, /**< 2.4V */ + RMU_VOL_2_6 = 0x4U, /**< 2.6V */ + RMU_VOL_2_8 = 0x5U, /**< 2.8V */ + RMU_VOL_3_0 = 0x6U, /**< 3.0V */ + RMU_VOL_3_2 = 0x7U, /**< 3.2V */ + RMU_VOL_3_4 = 0x8U, /**< 3.4V */ + RMU_VOL_3_6 = 0x9U, /**< 3.6V */ + RMU_VOL_3_8 = 0xAU, /**< 3.8V */ + RMU_VOL_4_0 = 0xBU, /**< 4.0V */ + RMU_VOL_4_2 = 0xCU, /**< 4.2V */ + RMU_VOL_4_4 = 0xDU, /**< 4.4V */ + RMU_VOL_4_6 = 0xEU, /**< 4.6V */ + RMU_VOL_4_8 = 0xFU, /**< 4.8V */ } rmu_bor_vol_t; /** * @brief RMU reset status */ -typedef enum -{ - RMU_RST_POR = (1U << 0), /**< POR */ - RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ - RMU_RST_BOR = (1U << 2), /**< BOR */ - RMU_RST_NMRST = (1U << 3), /**< NMRST */ - RMU_RST_IWDT = (1U << 4), /**< IWDT */ - RMU_RST_WWDT = (1U << 5), /**< WWDT */ - RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ - RMU_RST_CHIP = (1U << 7), /**< CHIP */ - RMU_RST_MCU = (1U << 8), /**< MCU */ - RMU_RST_CPU = (1U << 9), /**< CPU */ - RMU_RST_CFG = (1U << 10), /**< CFG */ - RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ +typedef enum { + RMU_RST_POR = (1U << 0), /**< POR */ + RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ + RMU_RST_BOR = (1U << 2), /**< BOR */ + RMU_RST_NMRST = (1U << 3), /**< NMRST */ + RMU_RST_IWDT = (1U << 4), /**< IWDT */ + RMU_RST_WWDT = (1U << 5), /**< WWDT */ + RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ + RMU_RST_CHIP = (1U << 7), /**< CHIP */ + RMU_RST_MCU = (1U << 8), /**< MCU */ + RMU_RST_CPU = (1U << 9), /**< CPU */ + RMU_RST_CFG = (1U << 10), /**< CFG */ + RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ + RMU_RST_ALL = (0xFFFFFU), /**< ALL */ } rmu_state_t; /** * @brief RMU periperal select bit - * @note ES32F065x: - * AD16C4T0--TIMER0 - * GP16C4T0--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - * - * ES32F033x: - * ES32F093x: - * GP16C4T0--TIMER0 - * GP16C4T1--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 + * @verbatim + In this module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F065x series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + TIMER4 ----> BS16T1 + TIMER5 ----> BS16T2 + TIMER6 ----> GP16C4T0 + TIMER7 ----> BS16T3 + + 2. For ES32F033x/ES32F093x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> BS16T0 + TIMER2 ----> GP16C2T0 + TIMER3 ----> GP16C2T1 + TIMER4 ----> BS16T1 + TIMER5 ----> BS16T2 + TIMER6 ----> GP16C4T1 + TIMER7 ----> BS16T3 + @endverbatim */ -typedef enum -{ - RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ - RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ - RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */ - RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */ - RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */ - RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ - RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ - RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ - RMU_PERH_TIMER0 = (1U << 0) | (1U << 28), /**< APB1: TIMER0 */ - RMU_PERH_TIMER1 = (1U << 1) | (1U << 28), /**< APB1: TIMER1 */ - RMU_PERH_TIMER2 = (1U << 2) | (1U << 28), /**< APB1: TIMER2 */ - RMU_PERH_TIMER3 = (1U << 3) | (1U << 28), /**< APB1: TIMER3 */ - RMU_PERH_TIMER4 = (1U << 4) | (1U << 28), /**< APB1: TIMER4 */ - RMU_PERH_TIMER5 = (1U << 5) | (1U << 28), /**< APB1: TIMER5 */ - RMU_PERH_TIMER6 = (1U << 6) | (1U << 28), /**< APB1: TIMER6 */ - RMU_PERH_TIMER7 = (1U << 7) | (1U << 28), /**< APB1: TIMER7 */ - RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */ - RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */ - RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */ - RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */ - RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */ - RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */ - RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */ - RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */ - RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */ - RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */ - RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */ - RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */ - RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */ - RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */ - RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */ - RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */ - RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */ - RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */ - RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */ - RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */ - RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */ - RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */ - RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */ - RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */ - RMU_PERH_TSENSE = (1U << 16) | (1U << 29), /**< APB2: TSENSE */ - RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */ - RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */ +typedef enum { + RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ + RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ + RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */ + RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */ + RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */ + RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ + RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ + RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ + RMU_PERH_TIMER0 = (1U << 0) | (1U << 28), /**< APB1: TIMER0 */ + RMU_PERH_TIMER1 = (1U << 1) | (1U << 28), /**< APB1: TIMER1 */ + RMU_PERH_TIMER2 = (1U << 2) | (1U << 28), /**< APB1: TIMER2 */ + RMU_PERH_TIMER3 = (1U << 3) | (1U << 28), /**< APB1: TIMER3 */ + RMU_PERH_TIMER4 = (1U << 4) | (1U << 28), /**< APB1: TIMER4 */ + RMU_PERH_TIMER5 = (1U << 5) | (1U << 28), /**< APB1: TIMER5 */ + RMU_PERH_TIMER6 = (1U << 6) | (1U << 28), /**< APB1: TIMER6 */ + RMU_PERH_TIMER7 = (1U << 7) | (1U << 28), /**< APB1: TIMER7 */ + RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */ + RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */ + RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */ + RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */ + RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */ + RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */ + RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */ + RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */ + RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */ + RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */ + RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */ + RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */ + RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */ + RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */ + RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */ + RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */ + RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */ + RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */ + RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */ + RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */ + RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */ + RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */ + RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */ + RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */ + RMU_PERH_TSENSE = (1U << 16) | (1U << 29), /**< APB2: TSENSE */ + RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */ + RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */ } rmu_peripheral_t; /** * @} @@ -168,40 +169,41 @@ typedef enum * @{ */ #define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \ - ((x) == RMU_BORFLT_2) || \ - ((x) == RMU_BORFLT_3) || \ - ((x) == RMU_BORFLT_4) || \ - ((x) == RMU_BORFLT_5) || \ - ((x) == RMU_BORFLT_6) || \ - ((x) == RMU_BORFLT_7)) -#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_7) || \ - ((x) == RMU_VOL_2_0) || \ - ((x) == RMU_VOL_2_1) || \ - ((x) == RMU_VOL_2_2) || \ - ((x) == RMU_VOL_2_3) || \ - ((x) == RMU_VOL_2_4) || \ - ((x) == RMU_VOL_2_5) || \ - ((x) == RMU_VOL_2_6) || \ - ((x) == RMU_VOL_2_8) || \ - ((x) == RMU_VOL_3_0) || \ - ((x) == RMU_VOL_3_1) || \ - ((x) == RMU_VOL_3_3) || \ - ((x) == RMU_VOL_3_6) || \ - ((x) == RMU_VOL_3_7) || \ - ((x) == RMU_VOL_4_0) || \ - ((x) == RMU_VOL_4_3)) + ((x) == RMU_BORFLT_2) || \ + ((x) == RMU_BORFLT_3) || \ + ((x) == RMU_BORFLT_4) || \ + ((x) == RMU_BORFLT_5) || \ + ((x) == RMU_BORFLT_6) || \ + ((x) == RMU_BORFLT_7)) +#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_8) || \ + ((x) == RMU_VOL_2_0) || \ + ((x) == RMU_VOL_2_2) || \ + ((x) == RMU_VOL_2_4) || \ + ((x) == RMU_VOL_2_6) || \ + ((x) == RMU_VOL_2_8) || \ + ((x) == RMU_VOL_3_0) || \ + ((x) == RMU_VOL_3_2) || \ + ((x) == RMU_VOL_3_4) || \ + ((x) == RMU_VOL_3_6) || \ + ((x) == RMU_VOL_3_8) || \ + ((x) == RMU_VOL_4_0) || \ + ((x) == RMU_VOL_4_2) || \ + ((x) == RMU_VOL_4_4) || \ + ((x) == RMU_VOL_4_6) || \ + ((x) == RMU_VOL_4_8)) #define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \ - ((x) == RMU_RST_WAKEUP) || \ - ((x) == RMU_RST_BOR) || \ - ((x) == RMU_RST_NMRST) || \ - ((x) == RMU_RST_IWDT) || \ - ((x) == RMU_RST_WWDT) || \ - ((x) == RMU_RST_LOCKUP) || \ - ((x) == RMU_RST_CHIP) || \ - ((x) == RMU_RST_MCU) || \ - ((x) == RMU_RST_CPU) || \ - ((x) == RMU_RST_CFG) || \ - ((x) == RMU_RST_CFGERR)) + ((x) == RMU_RST_WAKEUP) || \ + ((x) == RMU_RST_BOR) || \ + ((x) == RMU_RST_NMRST) || \ + ((x) == RMU_RST_IWDT) || \ + ((x) == RMU_RST_WWDT) || \ + ((x) == RMU_RST_LOCKUP) || \ + ((x) == RMU_RST_CHIP) || \ + ((x) == RMU_RST_MCU) || \ + ((x) == RMU_RST_CPU) || \ + ((x) == RMU_RST_CFG) || \ + ((x) == RMU_RST_CFGERR) || \ + ((x) == RMU_RST_ALL)) #define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \ ((x) == RMU_RST_WAKEUP) || \ ((x) == RMU_RST_BOR) || \ @@ -212,50 +214,51 @@ typedef enum ((x) == RMU_RST_CHIP) || \ ((x) == RMU_RST_MCU) || \ ((x) == RMU_RST_CPU) || \ - ((x) == RMU_RST_CFG)) + ((x) == RMU_RST_CFG) || \ + ((x) == RMU_RST_ALL)) #define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \ - ((x) == RMU_PERH_CRC) || \ - ((x) == RMU_PERH_CALC) || \ - ((x) == RMU_PERH_CRYPT) || \ - ((x) == RMU_PERH_TRNG) || \ - ((x) == RMU_PERH_PIS) || \ - ((x) == RMU_PERH_CHIP) || \ - ((x) == RMU_PERH_CPU) || \ - ((x) == RMU_PERH_TIMER0) || \ - ((x) == RMU_PERH_TIMER1) || \ - ((x) == RMU_PERH_TIMER2) || \ - ((x) == RMU_PERH_TIMER3) || \ - ((x) == RMU_PERH_TIMER4) || \ - ((x) == RMU_PERH_TIMER5) || \ - ((x) == RMU_PERH_TIMER6) || \ - ((x) == RMU_PERH_TIMER7) || \ - ((x) == RMU_PERH_UART0) || \ - ((x) == RMU_PERH_UART1) || \ - ((x) == RMU_PERH_UART2) || \ - ((x) == RMU_PERH_UART3) || \ - ((x) == RMU_PERH_USART0) || \ - ((x) == RMU_PERH_USART1) || \ - ((x) == RMU_PERH_SPI0) || \ - ((x) == RMU_PERH_SPI1) || \ - ((x) == RMU_PERH_SPI2) || \ - ((x) == RMU_PERH_I2C0) || \ - ((x) == RMU_PERH_I2C1) || \ - ((x) == RMU_PERH_CAN0) || \ - ((x) == RMU_PERH_LPTIM0) || \ - ((x) == RMU_PERH_LPUART0) || \ - ((x) == RMU_PERH_ADC0) || \ - ((x) == RMU_PERH_ADC1) || \ - ((x) == RMU_PERH_ACMP0) || \ - ((x) == RMU_PERH_ACMP1) || \ - ((x) == RMU_PERH_OPAMP) || \ - ((x) == RMU_PERH_DAC0) || \ - ((x) == RMU_PERH_WWDT) || \ - ((x) == RMU_PERH_LCD) || \ - ((x) == RMU_PERH_IWDT) || \ - ((x) == RMU_PERH_RTC) || \ - ((x) == RMU_PERH_TSENSE) || \ - ((x) == RMU_PERH_BKPC) || \ - ((x) == RMU_PERH_BKPRAM)) + ((x) == RMU_PERH_CRC) || \ + ((x) == RMU_PERH_CALC) || \ + ((x) == RMU_PERH_CRYPT) || \ + ((x) == RMU_PERH_TRNG) || \ + ((x) == RMU_PERH_PIS) || \ + ((x) == RMU_PERH_CHIP) || \ + ((x) == RMU_PERH_CPU) || \ + ((x) == RMU_PERH_TIMER0) || \ + ((x) == RMU_PERH_TIMER1) || \ + ((x) == RMU_PERH_TIMER2) || \ + ((x) == RMU_PERH_TIMER3) || \ + ((x) == RMU_PERH_TIMER4) || \ + ((x) == RMU_PERH_TIMER5) || \ + ((x) == RMU_PERH_TIMER6) || \ + ((x) == RMU_PERH_TIMER7) || \ + ((x) == RMU_PERH_UART0) || \ + ((x) == RMU_PERH_UART1) || \ + ((x) == RMU_PERH_UART2) || \ + ((x) == RMU_PERH_UART3) || \ + ((x) == RMU_PERH_USART0) || \ + ((x) == RMU_PERH_USART1) || \ + ((x) == RMU_PERH_SPI0) || \ + ((x) == RMU_PERH_SPI1) || \ + ((x) == RMU_PERH_SPI2) || \ + ((x) == RMU_PERH_I2C0) || \ + ((x) == RMU_PERH_I2C1) || \ + ((x) == RMU_PERH_CAN0) || \ + ((x) == RMU_PERH_LPTIM0) || \ + ((x) == RMU_PERH_LPUART0) || \ + ((x) == RMU_PERH_ADC0) || \ + ((x) == RMU_PERH_ADC1) || \ + ((x) == RMU_PERH_ACMP0) || \ + ((x) == RMU_PERH_ACMP1) || \ + ((x) == RMU_PERH_OPAMP) || \ + ((x) == RMU_PERH_DAC0) || \ + ((x) == RMU_PERH_WWDT) || \ + ((x) == RMU_PERH_LCD) || \ + ((x) == RMU_PERH_IWDT) || \ + ((x) == RMU_PERH_RTC) || \ + ((x) == RMU_PERH_TSENSE) || \ + ((x) == RMU_PERH_BKPC) || \ + ((x) == RMU_PERH_BKPRAM)) /** * @} */ @@ -264,7 +267,7 @@ typedef enum * @{ */ void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state); -flag_status_t ald_rmu_get_reset_status(rmu_state_t state); +uint32_t ald_rmu_get_reset_status(rmu_state_t state); void ald_rmu_clear_reset_status(rmu_state_t state); void ald_rmu_reset_periperal(rmu_peripheral_t perh); /** diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h index e14f542363707152db84d1ace5f3a59c874c31b5..dd5d8ad7ee2ed9de3d8e9cdc517e8ea3da7e8700 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h @@ -38,365 +38,335 @@ extern "C" { /** * @brief Hours format */ -typedef enum -{ - RTC_HOUR_FORMAT_24 = 0x0, /**< 24-hours format */ - RTC_HOUR_FORMAT_12 = 0x1, /**< 12-hours format */ +typedef enum { + RTC_HOUR_FORMAT_24 = 0x0U, /**< 24-hours format */ + RTC_HOUR_FORMAT_12 = 0x1U, /**< 12-hours format */ } rtc_hour_format_t; /** * @brief Output mode */ -typedef enum -{ - RTC_OUTPUT_DISABLE = 0x0, /**< Disable output */ - RTC_OUTPUT_ALARM_A = 0x1, /**< Output alarm_a signal */ - RTC_OUTPUT_ALARM_B = 0x2, /**< Output alarm_b signal */ - RTC_OUTPUT_WAKEUP = 0x3, /**< Output wakeup signal */ +typedef enum { + RTC_OUTPUT_DISABLE = 0x0U, /**< Disable output */ + RTC_OUTPUT_ALARM_A = 0x1U, /**< Output alarm_a signal */ + RTC_OUTPUT_ALARM_B = 0x2U, /**< Output alarm_b signal */ + RTC_OUTPUT_WAKEUP = 0x3U, /**< Output wakeup signal */ } rtc_output_select_t; /** * @brief Output polarity */ -typedef enum -{ - RTC_OUTPUT_POLARITY_HIGH = 0x0, /**< Polarity is high */ - RTC_OUTPUT_POLARITY_LOW = 0x0, /**< Polarity is low */ +typedef enum { + RTC_OUTPUT_POLARITY_HIGH = 0x0U, /**< Polarity is high */ + RTC_OUTPUT_POLARITY_LOW = 0x1U, /**< Polarity is low */ } rtc_output_polarity_t; /** * @brief Initialization structure */ -typedef struct -{ - rtc_hour_format_t hour_format; /**< Hours format */ - uint32_t asynch_pre_div; /**< Asynchronous predivider value */ - uint32_t synch_pre_div; /**< Synchronous predivider value */ - rtc_output_select_t output; /**< Output signal type */ - rtc_output_polarity_t output_polarity; /**< Output polarity */ +typedef struct { + rtc_hour_format_t hour_format; /**< Hours format */ + uint32_t asynch_pre_div; /**< Asynchronous predivider value */ + uint32_t synch_pre_div; /**< Synchronous predivider value */ + rtc_output_select_t output; /**< Output signal type */ + rtc_output_polarity_t output_polarity; /**< Output polarity */ } rtc_init_t; /** * @brief Source select */ -typedef enum -{ - RTC_SOURCE_LOSC = 0x0, /**< LOSC */ - RTC_SOURCE_LRC = 0x1, /**< LRC */ - RTC_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ - RTC_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ +typedef enum { + RTC_SOURCE_LOSC = 0x0U, /**< LOSC */ + RTC_SOURCE_LRC = 0x1U, /**< LRC */ + RTC_SOURCE_HRC_DIV_1M = 0x2U, /**< HRC divide to 1MHz */ + RTC_SOURCE_HOSC_DIV_1M = 0x3U, /**< HOSC divide to 1MHz */ } rtc_source_sel_t; /** * @brief Time structure */ -typedef struct -{ - uint8_t hour; /**< Hours */ - uint8_t minute; /**< Minutes */ - uint8_t second; /**< Seconds */ - uint16_t sub_sec; /**< Sub-seconds */ +typedef struct { + uint8_t hour; /**< Hours */ + uint8_t minute; /**< Minutes */ + uint8_t second; /**< Seconds */ + uint16_t sub_sec; /**< Sub-seconds */ } rtc_time_t; /** * @brief Date structure */ -typedef struct -{ - uint8_t week; /**< Weeks */ - uint8_t day; /**< days */ - uint8_t month; /**< months */ - uint8_t year; /**< years */ +typedef struct { + uint8_t week; /**< Weeks */ + uint8_t day; /**< days */ + uint8_t month; /**< months */ + uint8_t year; /**< years */ } rtc_date_t; /** * @brief Data format */ -typedef enum -{ - RTC_FORMAT_DEC = 0, - RTC_FORMAT_BCD = 1, +typedef enum { + RTC_FORMAT_DEC = 0U, /**< DEC format */ + RTC_FORMAT_BCD = 1U, /**< BCD format */ } rtc_format_t; /** * @brief Index of alarm */ -typedef enum -{ - RTC_ALARM_A = 0x0, /**< Alarm-A */ - RTC_ALARM_B = 0x1, /**< Alarm-B */ +typedef enum { + RTC_ALARM_A = 0x0U, /**< Alarm-A */ + RTC_ALARM_B = 0x1U, /**< Alarm-B */ } rtc_alarm_idx_t; /** * @brief Alarm mask */ -typedef enum -{ - RTC_ALARM_MASK_NONE = 0x0, /**< Mask is disable */ - RTC_ALARM_MASK_WEEK_DAY = (1U << 30), /**< Mask week or day */ - RTC_ALARM_MASK_HOUR = (1U << 23), /**< Mask hour */ - RTC_ALARM_MASK_MINUTE = (1U << 15), /**< Mask minute */ - RTC_ALARM_MASK_SECOND = (1U << 7), /**< Mask second */ - RTC_ALARM_MASK_ALL = 0x40808080, /**< Mask all */ +typedef enum { + RTC_ALARM_MASK_NONE = 0x0U, /**< Mask is disable */ + RTC_ALARM_MASK_WEEK_DAY = (1U << 30), /**< Mask week or day */ + RTC_ALARM_MASK_HOUR = (1U << 23), /**< Mask hour */ + RTC_ALARM_MASK_MINUTE = (1U << 15), /**< Mask minute */ + RTC_ALARM_MASK_SECOND = (1U << 7), /**< Mask second */ + RTC_ALARM_MASK_ALL = 0x40808080U, /**< Mask all */ } rtc_alarm_mask_t; /** * @brief Alarm sub-second mask */ -typedef enum -{ - RTC_ALARM_SS_MASK_NONE = 0xF, /**< Mask is disable */ - RTC_ALARM_SS_MASK_14_1 = 0x1, /**< Mask bit(1-14) */ - RTC_ALARM_SS_MASK_14_2 = 0x2, /**< Mask bit(2-14) */ - RTC_ALARM_SS_MASK_14_3 = 0x3, /**< Mask bit(3-14) */ - RTC_ALARM_SS_MASK_14_4 = 0x4, /**< Mask bit(4-14) */ - RTC_ALARM_SS_MASK_14_5 = 0x5, /**< Mask bit(5-14) */ - RTC_ALARM_SS_MASK_14_6 = 0x6, /**< Mask bit(6-14) */ - RTC_ALARM_SS_MASK_14_7 = 0x7, /**< Mask bit(7-14) */ - RTC_ALARM_SS_MASK_14_8 = 0x8, /**< Mask bit(8-14) */ - RTC_ALARM_SS_MASK_14_9 = 0x9, /**< Mask bit(9-14) */ - RTC_ALARM_SS_MASK_14_10 = 0xA, /**< Mask bit(10-14) */ - RTC_ALARM_SS_MASK_14_11 = 0xB, /**< Mask bit(11-14) */ - RTC_ALARM_SS_MASK_14_12 = 0xC, /**< Mask bit(12-14) */ - RTC_ALARM_SS_MASK_14_13 = 0xD, /**< Mask bit(13-14) */ - RTC_ALARM_SS_MASK_14 = 0xE, /**< Mask bit14 */ - RTC_ALARM_SS_MASK_ALL = 0x0, /**< Mask bit(0-14) */ +typedef enum { + RTC_ALARM_SS_MASK_NONE = 0xFU, /**< Mask is disable */ + RTC_ALARM_SS_MASK_14_1 = 0x1U, /**< Mask bit(1-14) */ + RTC_ALARM_SS_MASK_14_2 = 0x2U, /**< Mask bit(2-14) */ + RTC_ALARM_SS_MASK_14_3 = 0x3U, /**< Mask bit(3-14) */ + RTC_ALARM_SS_MASK_14_4 = 0x4U, /**< Mask bit(4-14) */ + RTC_ALARM_SS_MASK_14_5 = 0x5U, /**< Mask bit(5-14) */ + RTC_ALARM_SS_MASK_14_6 = 0x6U, /**< Mask bit(6-14) */ + RTC_ALARM_SS_MASK_14_7 = 0x7U, /**< Mask bit(7-14) */ + RTC_ALARM_SS_MASK_14_8 = 0x8U, /**< Mask bit(8-14) */ + RTC_ALARM_SS_MASK_14_9 = 0x9U, /**< Mask bit(9-14) */ + RTC_ALARM_SS_MASK_14_10 = 0xAU, /**< Mask bit(10-14) */ + RTC_ALARM_SS_MASK_14_11 = 0xBU, /**< Mask bit(11-14) */ + RTC_ALARM_SS_MASK_14_12 = 0xCU, /**< Mask bit(12-14) */ + RTC_ALARM_SS_MASK_14_13 = 0xDU, /**< Mask bit(13-14) */ + RTC_ALARM_SS_MASK_14 = 0xEU, /**< Mask bit14 */ + RTC_ALARM_SS_MASK_ALL = 0x0U, /**< Mask bit(0-14) */ } rtc_sub_second_mask_t; /** * @brief Alarm select week or day */ -typedef enum -{ - RTC_SELECT_DAY = 0x0, /**< Alarm select day */ - RTC_SELECT_WEEK = 0x1, /**< Alarm select week */ +typedef enum { + RTC_SELECT_DAY = 0x0U, /**< Alarm select day */ + RTC_SELECT_WEEK = 0x1U, /**< Alarm select week */ } rtc_week_day_sel_t; /** * @brief Alarm structure */ -typedef struct -{ - rtc_alarm_idx_t idx; /**< Index of alarm */ - rtc_time_t time; /**< Time structure */ - uint32_t mask; /**< Alarm mask */ - rtc_sub_second_mask_t ss_mask; /**< Alarm sub-second mask */ - rtc_week_day_sel_t sel; /**< Select week or day */ - - union - { - uint8_t week; /**< Alarm select week */ - uint8_t day; /**< Alarm select day */ - }; +typedef struct { + rtc_alarm_idx_t idx; /**< Index of alarm */ + rtc_time_t time; /**< Time structure */ + uint32_t mask; /**< Alarm mask */ + rtc_sub_second_mask_t ss_mask; /**< Alarm sub-second mask */ + rtc_week_day_sel_t sel; /**< Select week or day */ + + union { + uint8_t week; /**< Alarm select week */ + uint8_t day; /**< Alarm select day */ + }; } rtc_alarm_t; /** * @brief Time stamp signel select */ -typedef enum -{ - RTC_TS_SIGNAL_SEL_TAMPER0 = 0, /**< Select tamper0 */ - RTC_TS_SIGNAL_SEL_TAMPER1 = 1, /**< Select tamper1 */ +typedef enum { + RTC_TS_SIGNAL_SEL_TAMPER0 = 0U, /**< Select tamper0 */ + RTC_TS_SIGNAL_SEL_TAMPER1 = 1U, /**< Select tamper1 */ } rtc_ts_signal_sel_t; /** * @brief Time stamp trigger style */ -typedef enum -{ - RTC_TS_RISING_EDGE = 0, /**< Rising edge */ - RTC_TS_FALLING_EDGE = 1, /**< Falling edge */ +typedef enum { + RTC_TS_RISING_EDGE = 0U, /**< Rising edge */ + RTC_TS_FALLING_EDGE = 1U, /**< Falling edge */ } rtc_ts_trigger_style_t; /** * @brief Index of tamper */ -typedef enum -{ - RTC_TAMPER_0 = 0, /**< Tamper0 */ - RTC_TAMPER_1 = 1, /**< Tamper1 */ +typedef enum { + RTC_TAMPER_0 = 0U, /**< Tamper0 */ + RTC_TAMPER_1 = 1U, /**< Tamper1 */ } rtc_tamper_idx_t; /** * @brief Tamper trigger type */ -typedef enum -{ - RTC_TAMPER_TRIGGER_LOW = 0, /**< High trigger */ - RTC_TAMPER_TRIGGER_HIGH = 1, /**< Low trigger */ +typedef enum { + RTC_TAMPER_TRIGGER_LOW = 0U, /**< High trigger */ + RTC_TAMPER_TRIGGER_HIGH = 1U, /**< Low trigger */ } rtc_tamper_trigger_t; /** * @brief Tamper sampling frequency */ -typedef enum -{ - RTC_TAMPER_SAMPLING_FREQ_32768 = 0, /**< RTCCLK / 32768 */ - RTC_TAMPER_SAMPLING_FREQ_16384 = 1, /**< RTCCLK / 16384 */ - RTC_TAMPER_SAMPLING_FREQ_8192 = 2, /**< RTCCLK / 8192 */ - RTC_TAMPER_SAMPLING_FREQ_4096 = 3, /**< RTCCLK / 4096 */ - RTC_TAMPER_SAMPLING_FREQ_2048 = 4, /**< RTCCLK / 2048 */ - RTC_TAMPER_SAMPLING_FREQ_1024 = 5, /**< RTCCLK / 1024 */ - RTC_TAMPER_SAMPLING_FREQ_512 = 6, /**< RTCCLK / 512 */ - RTC_TAMPER_SAMPLING_FREQ_256 = 7, /**< RTCCLK / 256 */ +typedef enum { + RTC_TAMPER_SAMPLING_FREQ_32768 = 0U, /**< RTCCLK / 32768 */ + RTC_TAMPER_SAMPLING_FREQ_16384 = 1U, /**< RTCCLK / 16384 */ + RTC_TAMPER_SAMPLING_FREQ_8192 = 2U, /**< RTCCLK / 8192 */ + RTC_TAMPER_SAMPLING_FREQ_4096 = 3U, /**< RTCCLK / 4096 */ + RTC_TAMPER_SAMPLING_FREQ_2048 = 4U, /**< RTCCLK / 2048 */ + RTC_TAMPER_SAMPLING_FREQ_1024 = 5U, /**< RTCCLK / 1024 */ + RTC_TAMPER_SAMPLING_FREQ_512 = 6U, /**< RTCCLK / 512 */ + RTC_TAMPER_SAMPLING_FREQ_256 = 7U, /**< RTCCLK / 256 */ } rtc_tamper_sampling_freq_t; /** * @brief Tamper filter time */ -typedef enum -{ - RTC_TAMPER_DURATION_1 = 0, /**< Duration 1 sampling */ - RTC_TAMPER_DURATION_2 = 1, /**< Duration 2 sampling */ - RTC_TAMPER_DURATION_4 = 2, /**< Duration 4 sampling */ - RTC_TAMPER_DURATION_8 = 3, /**< Duration 8 sampling */ +typedef enum { + RTC_TAMPER_DURATION_1 = 0U, /**< Duration 1 sampling */ + RTC_TAMPER_DURATION_2 = 1U, /**< Duration 2 sampling */ + RTC_TAMPER_DURATION_4 = 2U, /**< Duration 4 sampling */ + RTC_TAMPER_DURATION_8 = 3U, /**< Duration 8 sampling */ } rtc_tamper_duration_t; /** * @brief Tamper structure */ -typedef struct -{ - rtc_tamper_idx_t idx; /**< Index of tamper */ - rtc_tamper_trigger_t trig; /**< Trigger type */ - rtc_tamper_sampling_freq_t freq; /**< Sampling frequency */ - rtc_tamper_duration_t dur; /**< Filter time */ - type_func_t ts; /**< Enable/Disable trigger time stamp event */ +typedef struct { + rtc_tamper_idx_t idx; /**< Index of tamper */ + rtc_tamper_trigger_t trig; /**< Trigger type */ + rtc_tamper_sampling_freq_t freq; /**< Sampling frequency */ + rtc_tamper_duration_t dur; /**< Filter time */ + type_func_t ts; /**< Enable/Disable trigger time stamp event */ } rtc_tamper_t; /** * @brief Wake-up clock */ -typedef enum -{ - RTC_WAKEUP_CLOCK_DIV_16 = 0, /**< RTCCLK / 16 */ - RTC_WAKEUP_CLOCK_DIV_8 = 1, /**< RTCCLK / 8 */ - RTC_WAKEUP_CLOCK_DIV_4 = 2, /**< RTCCLK / 4 */ - RTC_WAKEUP_CLOCK_DIV_2 = 3, /**< RTCCLK / 2 */ - RTC_WAKEUP_CLOCK_1HZ = 4, /**< 1Hz */ - RTC_WAKEUP_CLOCK_1HZ_PULS = 6, /**< 1Hz and WUT + 65536 */ +typedef enum { + RTC_WAKEUP_CLOCK_DIV_16 = 0U, /**< RTCCLK / 16 */ + RTC_WAKEUP_CLOCK_DIV_8 = 1U, /**< RTCCLK / 8 */ + RTC_WAKEUP_CLOCK_DIV_4 = 2U, /**< RTCCLK / 4 */ + RTC_WAKEUP_CLOCK_DIV_2 = 3U, /**< RTCCLK / 2 */ + RTC_WAKEUP_CLOCK_1HZ = 4U, /**< 1Hz */ + RTC_WAKEUP_CLOCK_1HZ_PULS = 6U, /**< 1Hz and WUT + 65536 */ } rtc_wakeup_clock_t; /** * @brief RTC clock output type */ -typedef enum -{ - RTC_CLOCK_OUTPUT_32768 = 0, /**< 32768Hz */ - RTC_CLOCK_OUTPUT_1024 = 1, /**< 1024Hz */ - RTC_CLOCK_OUTPUT_32 = 2, /**< 32Hz */ - RTC_CLOCK_OUTPUT_1 = 3, /**< 1Hz */ - RTC_CLOCK_OUTPUT_CAL_1 = 4, /**< 1Hz after calibration */ - RTC_CLOCK_OUTPUT_EXA_1 = 5, /**< Exact 1Hz */ +typedef enum { + RTC_CLOCK_OUTPUT_32768 = 0U, /**< 32768Hz */ + RTC_CLOCK_OUTPUT_1024 = 1U, /**< 1024Hz */ + RTC_CLOCK_OUTPUT_32 = 2U, /**< 32Hz */ + RTC_CLOCK_OUTPUT_1 = 3U, /**< 1Hz */ + RTC_CLOCK_OUTPUT_CAL_1 = 4U, /**< 1Hz after calibration */ + RTC_CLOCK_OUTPUT_EXA_1 = 5U, /**< Exact 1Hz */ } rtc_clock_output_t; /** * @ Calibration frequency */ -typedef enum -{ - RTC_CALI_FREQ_10_SEC = 0, /**< Calibrate every 10 seconds */ - RTC_CALI_FREQ_20_SEC = 1, /**< Calibrate every 20 seconds */ - RTC_CALI_FREQ_1_MIN = 2, /**< Calibrate every 1 minute */ - RTC_CALI_FREQ_2_MIN = 3, /**< Calibrate every 2 minutes */ - RTC_CALI_FREQ_5_MIN = 4, /**< Calibrate every 5 minutes */ - RTC_CALI_FREQ_10_MIN = 5, /**< Calibrate every 10 minutes */ - RTC_CALI_FREQ_20_MIN = 6, /**< Calibrate every 20 minutes */ - RTC_CALI_FREQ_1_SEC = 7, /**< Calibrate every 1 second */ +typedef enum { + RTC_CALI_FREQ_10_SEC = 0U, /**< Calibrate every 10 seconds */ + RTC_CALI_FREQ_20_SEC = 1U, /**< Calibrate every 20 seconds */ + RTC_CALI_FREQ_1_MIN = 2U, /**< Calibrate every 1 minute */ + RTC_CALI_FREQ_2_MIN = 3U, /**< Calibrate every 2 minutes */ + RTC_CALI_FREQ_5_MIN = 4U, /**< Calibrate every 5 minutes */ + RTC_CALI_FREQ_10_MIN = 5U, /**< Calibrate every 10 minutes */ + RTC_CALI_FREQ_20_MIN = 6U, /**< Calibrate every 20 minutes */ + RTC_CALI_FREQ_1_SEC = 7U, /**< Calibrate every 1 second */ } rtc_cali_freq_t; /** * @brief Temperature compensate type */ -typedef enum -{ - RTC_CALI_TC_NONE = 0, /**< Temperature compensate disable */ - RTC_CALI_TC_AUTO_BY_HW = 1, /**< Temperature compensate by hardware */ - RTC_CALI_TC_AUTO_BY_SF = 2, /**< Temperature compensate by software */ - RTC_CALI_TC_AUTO_BY_HW_SF = 3, /**< Temperature compensate by hardware, trigger by software */ +typedef enum { + RTC_CALI_TC_NONE = 0U, /**< Temperature compensate disable */ + RTC_CALI_TC_AUTO_BY_HW = 1U, /**< Temperature compensate by hardware */ + RTC_CALI_TC_AUTO_BY_SF = 2U, /**< Temperature compensate by software */ + RTC_CALI_TC_AUTO_BY_HW_SF = 3U, /**< Temperature compensate by hardware, trigger by software */ } rtc_cali_tc_t; /** * @ Calculate frequency */ -typedef enum -{ - RTC_CALI_CALC_FREQ_10_SEC = 0, /**< Calculate every 10 seconds */ - RTC_CALI_CALC_FREQ_20_SEC = 1, /**< Calculate every 20 seconds */ - RTC_CALI_CALC_FREQ_1_MIN = 2, /**< Calculate every 1 minute */ - RTC_CALI_CALC_FREQ_2_MIN = 3, /**< Calculate every 2 minutes */ - RTC_CALI_CALC_FREQ_5_MIN = 4, /**< Calculate every 5 minutes */ - RTC_CALI_CALC_FREQ_10_MIN = 5, /**< Calculate every 10 minutes */ - RTC_CALI_CALC_FREQ_20_MIN = 6, /**< Calculate every 20 minutes */ - RTC_CALI_CALC_FREQ_1_HOUR = 7, /**< Calculate every 1 hour */ +typedef enum { + RTC_CALI_CALC_FREQ_10_SEC = 0U, /**< Calculate every 10 seconds */ + RTC_CALI_CALC_FREQ_20_SEC = 1U, /**< Calculate every 20 seconds */ + RTC_CALI_CALC_FREQ_1_MIN = 2U, /**< Calculate every 1 minute */ + RTC_CALI_CALC_FREQ_2_MIN = 3U, /**< Calculate every 2 minutes */ + RTC_CALI_CALC_FREQ_5_MIN = 4U, /**< Calculate every 5 minutes */ + RTC_CALI_CALC_FREQ_10_MIN = 5U, /**< Calculate every 10 minutes */ + RTC_CALI_CALC_FREQ_20_MIN = 6U, /**< Calculate every 20 minutes */ + RTC_CALI_CALC_FREQ_1_HOUR = 7U, /**< Calculate every 1 hour */ } rtc_cali_calc_freq_t; /** * @brief Calibration algorithm */ -typedef enum -{ - RTC_CALI_CALC_4 = 0, /**< 4-polynomial */ - RTC_CALI_CALC_2 = 1, /**< 2-parabola */ +typedef enum { + RTC_CALI_CALC_4 = 0U, /**< 4-polynomial */ + RTC_CALI_CALC_2 = 1U, /**< 2-parabola */ } rtc_cali_calc_t; /** * @brief Calibration structure */ -typedef struct -{ - rtc_cali_freq_t cali_freq; /**< calibrate frequency */ - rtc_cali_tc_t tc; /**< Temperature compensate type */ - rtc_cali_calc_freq_t calc_freq; /**< Calculate frequency */ - rtc_cali_calc_t calc; /**< algorithm */ - type_func_t acc; /**< Enable/Disable decimal accumulate */ +typedef struct { + rtc_cali_freq_t cali_freq; /**< calibrate frequency */ + rtc_cali_tc_t tc; /**< Temperature compensate type */ + rtc_cali_calc_freq_t calc_freq; /**< Calculate frequency */ + rtc_cali_calc_t calc; /**< algorithm */ + type_func_t acc; /**< Enable/Disable decimal accumulate */ } rtc_cali_t; /** * @brief Interrupt type */ -typedef enum -{ - RTC_IT_SEC = (1U << 0), /**< Second */ - RTC_IT_MIN = (1U << 1), /**< Minute */ - RTC_IT_HR = (1U << 2), /**< Hour */ - RTC_IT_DAY = (1U << 3), /**< Day */ - RTC_IT_MON = (1U << 4), /**< Month */ - RTC_IT_YR = (1U << 5), /**< Year */ - RTC_IT_ALMA = (1U << 8), /**< Alarm-A */ - RTC_IT_ALMB = (1U << 9), /**< Alarm-B */ - RTC_IT_TS = (1U << 10), /**< Time stamp */ - RTC_IT_TSOV = (1U << 11), /**< Time stamp overflow */ - RTC_IT_TP0 = (1U << 12), /**< Tamper-0 */ - RTC_IT_TP1 = (1U << 13), /**< Tamper-1 */ - RTC_IT_RSC = (1U << 16), /**< Synchronous complete */ - RTC_IT_SFC = (1U << 17), /**< Shift complete */ - RTC_IT_WU = (1U << 18), /**< Wake-up */ - RTC_IT_TCC = (1U << 24), /**< Temperature compensate complete */ - RTC_IT_TCE = (1U << 25), /**< Temperature compensate error */ +typedef enum { + RTC_IT_SEC = (1U << 0), /**< Second */ + RTC_IT_MIN = (1U << 1), /**< Minute */ + RTC_IT_HR = (1U << 2), /**< Hour */ + RTC_IT_DAY = (1U << 3), /**< Day */ + RTC_IT_MON = (1U << 4), /**< Month */ + RTC_IT_YR = (1U << 5), /**< Year */ + RTC_IT_ALMA = (1U << 8), /**< Alarm-A */ + RTC_IT_ALMB = (1U << 9), /**< Alarm-B */ + RTC_IT_TS = (1U << 10), /**< Time stamp */ + RTC_IT_TSOV = (1U << 11), /**< Time stamp overflow */ + RTC_IT_TP0 = (1U << 12), /**< Tamper-0 */ + RTC_IT_TP1 = (1U << 13), /**< Tamper-1 */ + RTC_IT_RSC = (1U << 16), /**< Synchronous complete */ + RTC_IT_SFC = (1U << 17), /**< Shift complete */ + RTC_IT_WU = (1U << 18), /**< Wake-up */ + RTC_IT_TCC = (1U << 24), /**< Temperature compensate complete */ + RTC_IT_TCE = (1U << 25), /**< Temperature compensate error */ } rtc_it_t; /** * @brief Interrupt flag */ -typedef enum -{ - RTC_IF_SEC = (1U << 0), /**< Second */ - RTC_IF_MIN = (1U << 1), /**< Minute */ - RTC_IF_HR = (1U << 2), /**< Hour */ - RTC_IF_DAY = (1U << 3), /**< Day */ - RTC_IF_MON = (1U << 4), /**< Month */ - RTC_IF_YR = (1U << 5), /**< Year */ - RTC_IF_ALMA = (1U << 8), /**< Alarm-A */ - RTC_IF_ALMB = (1U << 9), /**< Alarm-B */ - RTC_IF_TS = (1U << 10), /**< Time stamp */ - RTC_IF_TSOV = (1U << 11), /**< Time stamp overflow */ - RTC_IF_TP0 = (1U << 12), /**< Tamper-0 */ - RTC_IF_TP1 = (1U << 13), /**< Tamper-1 */ - RTC_IF_RSC = (1U << 16), /**< Synchronous complete */ - RTC_IF_SFC = (1U << 17), /**< Shift complete */ - RTC_IF_WU = (1U << 18), /**< Wake-up */ - RTC_IF_TCC = (1U << 24), /**< Temperature compensate complete */ - RTC_IF_TCE = (1U << 25), /**< Temperature compensate error */ +typedef enum { + RTC_IF_SEC = (1U << 0), /**< Second */ + RTC_IF_MIN = (1U << 1), /**< Minute */ + RTC_IF_HR = (1U << 2), /**< Hour */ + RTC_IF_DAY = (1U << 3), /**< Day */ + RTC_IF_MON = (1U << 4), /**< Month */ + RTC_IF_YR = (1U << 5), /**< Year */ + RTC_IF_ALMA = (1U << 8), /**< Alarm-A */ + RTC_IF_ALMB = (1U << 9), /**< Alarm-B */ + RTC_IF_TS = (1U << 10), /**< Time stamp */ + RTC_IF_TSOV = (1U << 11), /**< Time stamp overflow */ + RTC_IF_TP0 = (1U << 12), /**< Tamper-0 */ + RTC_IF_TP1 = (1U << 13), /**< Tamper-1 */ + RTC_IF_RSC = (1U << 16), /**< Synchronous complete */ + RTC_IF_SFC = (1U << 17), /**< Shift complete */ + RTC_IF_WU = (1U << 18), /**< Wake-up */ + RTC_IF_TCC = (1U << 24), /**< Temperature compensate complete */ + RTC_IF_TCE = (1U << 25), /**< Temperature compensate error */ } rtc_flag_t; /** * @} @@ -405,44 +375,44 @@ typedef enum /** @defgroup RTC_Public_Macro RTC Public Macros * @{ */ -#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55)) -#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0)) +#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55U)) +#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0U)) #define RTC_BY_PASS_ENABLE() \ - do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ - RTC_LOCK(); \ - } while (0) +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ + RTC_LOCK(); \ +} while (0) #define RTC_BY_PASS_DISABLE() \ - do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ - RTC_LOCK(); \ - } while (0) +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ + RTC_LOCK(); \ +} while (0) #define RTC_SUMMER_TIME_ENABLE() \ - do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ - RTC_LOCK(); \ - } while (0) +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ + RTC_LOCK(); \ +} while (0) #define RTC_SUMMER_TIME_DISABLE() \ - do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ - RTC_LOCK(); \ - } while (0) +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ + RTC_LOCK(); \ +} while (0) #define RTC_WINTER_TIME_ENABLE() \ - do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ - RTC_LOCK(); \ - } while (0) +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ + RTC_LOCK(); \ +} while (0) #define RTC_WINTER_TIME_DISABLE() \ - do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ - RTC_LOCK(); \ - } while (0) +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ + RTC_LOCK(); \ +} while (0) /** * @} */ @@ -450,10 +420,10 @@ typedef enum /** @defgroup CAN_Private_Macros CAN Private Macros * @{ */ -#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AA)) -#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0)) -#define ALARM_MASK_ALL 0x40808080 -#define RTC_TIMEOUT_VALUE 100 +#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AAU)) +#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0U)) +#define ALARM_MASK_ALL 0x40808080U +#define RTC_TIMEOUT_VALUE 100U #define IS_SHIFT_SUB_SS(x) ((x) < (1U << 15)) #define IS_RTC_HOUR_FORMAT(x) (((x) == RTC_HOUR_FORMAT_24) || \ @@ -463,15 +433,15 @@ typedef enum ((x) == RTC_OUTPUT_ALARM_B) || \ ((x) == RTC_OUTPUT_WAKEUP)) #define IS_RTC_OUTPUT_POLARITY(x) (((x) == RTC_OUTPUT_POLARITY_HIGH) || \ - ((x) == RTC_OUTPUT_POLARITY_LOW)) + ((x) == RTC_OUTPUT_POLARITY_LOW)) #define IS_RTC_SOURCE_SEL(x) (((x) == RTC_SOURCE_LOSC) || \ ((x) == RTC_SOURCE_LRC) || \ ((x) == RTC_SOURCE_HRC_DIV_1M ) || \ ((x) == RTC_SOURCE_HOSC_DIV_1M)) #define IS_RTC_ALARM(x) (((x) == RTC_ALARM_A) || \ - ((x) == RTC_ALARM_B)) + ((x) == RTC_ALARM_B)) #define IS_RTC_ALARM_SEL(x) (((x) == RTC_SELECT_DAY) || \ - ((x) == RTC_SELECT_WEEK)) + ((x) == RTC_SELECT_WEEK)) #define IS_RTC_ALARM_MASK(x) (((x) == RTC_ALARM_MASK_NONE) || \ ((x) == RTC_ALARM_MASK_WEEK_DAY) || \ ((x) == RTC_ALARM_MASK_HOUR) || \ @@ -495,27 +465,27 @@ typedef enum ((x) == RTC_ALARM_SS_MASK_14) || \ ((x) == RTC_ALARM_SS_MASK_ALL)) #define IS_RTC_TS_SIGNAL(x) (((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \ - ((x) == RTC_TS_SIGNAL_SEL_TAMPER1)) + ((x) == RTC_TS_SIGNAL_SEL_TAMPER1)) #define IS_RTC_TS_STYLE(x) (((x) == RTC_TS_RISING_EDGE) || \ - ((x) == RTC_TS_FALLING_EDGE)) + ((x) == RTC_TS_FALLING_EDGE)) #define IS_RTC_FORMAT(x) (((x) == RTC_FORMAT_DEC) || \ - ((x) == RTC_FORMAT_BCD)) + ((x) == RTC_FORMAT_BCD)) #define IS_RTC_TAMPER(x) (((x) == RTC_TAMPER_0) || \ - ((x) == RTC_TAMPER_1)) + ((x) == RTC_TAMPER_1)) #define IS_RTC_TAMPER_TRIGGER(x) (((x) == RTC_TAMPER_TRIGGER_LOW) || \ - ((x) == RTC_TAMPER_TRIGGER_HIGH)) + ((x) == RTC_TAMPER_TRIGGER_HIGH)) #define IS_RTC_TAMPER_SAMPLING_FREQ(x) (((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_8192) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_4096) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_2048) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_1024) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_512) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_256)) + ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_8192) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_4096) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_2048) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_1024) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_512) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_256)) #define IS_RTC_TAMPER_DURATION(x) (((x) == RTC_TAMPER_DURATION_1) || \ - ((x) == RTC_TAMPER_DURATION_2) || \ - ((x) == RTC_TAMPER_DURATION_4) || \ - ((x) == RTC_TAMPER_DURATION_8)) + ((x) == RTC_TAMPER_DURATION_2) || \ + ((x) == RTC_TAMPER_DURATION_4) || \ + ((x) == RTC_TAMPER_DURATION_8)) #define IS_RTC_WAKEUP_CLOCK(x) (((x) == RTC_WAKEUP_CLOCK_DIV_16) || \ ((x) == RTC_WAKEUP_CLOCK_DIV_8) || \ ((x) == RTC_WAKEUP_CLOCK_DIV_4) || \ @@ -529,61 +499,61 @@ typedef enum ((x) == RTC_CLOCK_OUTPUT_CAL_1) || \ ((x) == RTC_CLOCK_OUTPUT_EXA_1)) #define IS_RTC_CALI_FREQ(x) (((x) == RTC_CALI_FREQ_10_SEC) || \ - ((x) == RTC_CALI_FREQ_20_SEC) || \ - ((x) == RTC_CALI_FREQ_1_MIN) || \ - ((x) == RTC_CALI_FREQ_2_MIN) || \ - ((x) == RTC_CALI_FREQ_5_MIN) || \ - ((x) == RTC_CALI_FREQ_10_MIN) || \ - ((x) == RTC_CALI_FREQ_20_MIN) || \ - ((x) == RTC_CALI_FREQ_1_SEC)) + ((x) == RTC_CALI_FREQ_20_SEC) || \ + ((x) == RTC_CALI_FREQ_1_MIN) || \ + ((x) == RTC_CALI_FREQ_2_MIN) || \ + ((x) == RTC_CALI_FREQ_5_MIN) || \ + ((x) == RTC_CALI_FREQ_10_MIN) || \ + ((x) == RTC_CALI_FREQ_20_MIN) || \ + ((x) == RTC_CALI_FREQ_1_SEC)) #define IS_RTC_CALI_TC(x) (((x) == RTC_CALI_TC_NONE) || \ - ((x) == RTC_CALI_TC_AUTO_BY_HW) || \ - ((x) == RTC_CALI_TC_AUTO_BY_SF) || \ - ((x) == RTC_CALI_TC_AUTO_BY_HW_SF)) + ((x) == RTC_CALI_TC_AUTO_BY_HW) || \ + ((x) == RTC_CALI_TC_AUTO_BY_SF) || \ + ((x) == RTC_CALI_TC_AUTO_BY_HW_SF)) #define IS_RTC_CALC_FREQ(x) (((x) == RTC_CALI_CALC_FREQ_10_SEC) || \ - ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \ - ((x) == RTC_CALI_CALC_FREQ_1_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_2_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_5_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_1_HOUR)) + ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \ + ((x) == RTC_CALI_CALC_FREQ_1_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_2_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_5_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_1_HOUR)) #define IS_RTC_CALI_CALC(x) (((x) == RTC_CALI_CALC_4) || \ - ((x) == RTC_CALI_CALC_2)) + ((x) == RTC_CALI_CALC_2)) #define IS_RTC_IT(x) (((x) == RTC_IT_SEC) || \ - ((x) == RTC_IT_MIN) || \ - ((x) == RTC_IT_HR) || \ - ((x) == RTC_IT_DAY) || \ - ((x) == RTC_IT_MON) || \ - ((x) == RTC_IT_YR) || \ - ((x) == RTC_IT_ALMA) || \ - ((x) == RTC_IT_ALMB) || \ - ((x) == RTC_IT_TS) || \ - ((x) == RTC_IT_TSOV) || \ - ((x) == RTC_IT_TP0) || \ - ((x) == RTC_IT_TP1) || \ - ((x) == RTC_IT_RSC) || \ - ((x) == RTC_IT_SFC) || \ - ((x) == RTC_IT_WU) || \ - ((x) == RTC_IT_TCC) || \ - ((x) == RTC_IT_TCE)) + ((x) == RTC_IT_MIN) || \ + ((x) == RTC_IT_HR) || \ + ((x) == RTC_IT_DAY) || \ + ((x) == RTC_IT_MON) || \ + ((x) == RTC_IT_YR) || \ + ((x) == RTC_IT_ALMA) || \ + ((x) == RTC_IT_ALMB) || \ + ((x) == RTC_IT_TS) || \ + ((x) == RTC_IT_TSOV) || \ + ((x) == RTC_IT_TP0) || \ + ((x) == RTC_IT_TP1) || \ + ((x) == RTC_IT_RSC) || \ + ((x) == RTC_IT_SFC) || \ + ((x) == RTC_IT_WU) || \ + ((x) == RTC_IT_TCC) || \ + ((x) == RTC_IT_TCE)) #define IS_RTC_IF(x) (((x) == RTC_IF_SEC) || \ - ((x) == RTC_IF_MIN) || \ - ((x) == RTC_IF_HR) || \ - ((x) == RTC_IF_DAY) || \ - ((x) == RTC_IF_MON) || \ - ((x) == RTC_IF_YR) || \ - ((x) == RTC_IF_ALMA) || \ - ((x) == RTC_IF_ALMB) || \ - ((x) == RTC_IF_TS) || \ - ((x) == RTC_IF_TSOV) || \ - ((x) == RTC_IF_TP0) || \ - ((x) == RTC_IF_TP1) || \ - ((x) == RTC_IF_RSC) || \ - ((x) == RTC_IF_SFC) || \ - ((x) == RTC_IF_WU) || \ - ((x) == RTC_IF_TCC) || \ - ((x) == RTC_IF_TCE)) + ((x) == RTC_IF_MIN) || \ + ((x) == RTC_IF_HR) || \ + ((x) == RTC_IF_DAY) || \ + ((x) == RTC_IF_MON) || \ + ((x) == RTC_IF_YR) || \ + ((x) == RTC_IF_ALMA) || \ + ((x) == RTC_IF_ALMB) || \ + ((x) == RTC_IF_TS) || \ + ((x) == RTC_IF_TSOV) || \ + ((x) == RTC_IF_TP0) || \ + ((x) == RTC_IF_TP1) || \ + ((x) == RTC_IF_RSC) || \ + ((x) == RTC_IF_SFC) || \ + ((x) == RTC_IF_WU) || \ + ((x) == RTC_IF_TCC) || \ + ((x) == RTC_IF_TCE)) #define IS_RTC_SECOND(x) ((x) < 60) #define IS_RTC_MINUTE(x) ((x) < 60) #define IS_RTC_HOUR(x) ((x) < 24) diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h index b04380ee6d0973f1fc31238a247a07616adce0c3..74401fecc136614fdec18985ba4e61d0efe1deee 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h @@ -18,7 +18,7 @@ #define __ALD_SMARTCARD_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -41,52 +41,50 @@ extern "C" { /** * @brief SMARTCARD error codes */ -typedef enum -{ - SMARTCARD_ERROR_NONE = ((uint32_t)0x00), /**< No error */ - SMARTCARD_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ - SMARTCARD_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ - SMARTCARD_ERROR_FE = ((uint32_t)0x04), /**< frame error */ - SMARTCARD_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ - SMARTCARD_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +typedef enum { + SMARTCARD_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ + SMARTCARD_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ + SMARTCARD_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ + SMARTCARD_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ + SMARTCARD_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ + SMARTCARD_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ } smartcard_error_t; /** * @brief SMARTCARD Prescaler */ -typedef enum -{ - SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1), /**< SYSCLK divided by 2 */ - SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2), /**< SYSCLK divided by 4 */ - SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3), /**< SYSCLK divided by 6 */ - SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4), /**< SYSCLK divided by 8 */ - SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5), /**< SYSCLK divided by 10 */ - SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6), /**< SYSCLK divided by 12 */ - SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7), /**< SYSCLK divided by 14 */ - SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8), /**< SYSCLK divided by 16 */ - SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9), /**< SYSCLK divided by 18 */ - SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xA), /**< SYSCLK divided by 20 */ - SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xB), /**< SYSCLK divided by 22 */ - SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xC), /**< SYSCLK divided by 24 */ - SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xD), /**< SYSCLK divided by 26 */ - SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xE), /**< SYSCLK divided by 28 */ - SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xF), /**< SYSCLK divided by 30 */ - SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10), /**< SYSCLK divided by 32 */ - SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11), /**< SYSCLK divided by 34 */ - SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12), /**< SYSCLK divided by 36 */ - SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13), /**< SYSCLK divided by 38 */ - SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14), /**< SYSCLK divided by 40 */ - SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15), /**< SYSCLK divided by 42 */ - SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16), /**< SYSCLK divided by 44 */ - SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17), /**< SYSCLK divided by 46 */ - SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18), /**< SYSCLK divided by 48 */ - SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19), /**< SYSCLK divided by 50 */ - SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1A), /**< SYSCLK divided by 52 */ - SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1B), /**< SYSCLK divided by 54 */ - SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1C), /**< SYSCLK divided by 56 */ - SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1D), /**< SYSCLK divided by 58 */ - SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1E), /**< SYSCLK divided by 60 */ - SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1F), /**< SYSCLK divided by 62 */ +typedef enum { + SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1U), /**< SYSCLK divided by 2 */ + SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2U), /**< SYSCLK divided by 4 */ + SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3U), /**< SYSCLK divided by 6 */ + SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4U), /**< SYSCLK divided by 8 */ + SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5U), /**< SYSCLK divided by 10 */ + SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6U), /**< SYSCLK divided by 12 */ + SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7U), /**< SYSCLK divided by 14 */ + SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8U), /**< SYSCLK divided by 16 */ + SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9U), /**< SYSCLK divided by 18 */ + SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xAU), /**< SYSCLK divided by 20 */ + SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xBU), /**< SYSCLK divided by 22 */ + SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xCU), /**< SYSCLK divided by 24 */ + SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xDU), /**< SYSCLK divided by 26 */ + SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xEU), /**< SYSCLK divided by 28 */ + SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xFU), /**< SYSCLK divided by 30 */ + SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10U), /**< SYSCLK divided by 32 */ + SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11U), /**< SYSCLK divided by 34 */ + SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12U), /**< SYSCLK divided by 36 */ + SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13U), /**< SYSCLK divided by 38 */ + SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14U), /**< SYSCLK divided by 40 */ + SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15U), /**< SYSCLK divided by 42 */ + SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16U), /**< SYSCLK divided by 44 */ + SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17U), /**< SYSCLK divided by 46 */ + SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18U), /**< SYSCLK divided by 48 */ + SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19U), /**< SYSCLK divided by 50 */ + SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1AU), /**< SYSCLK divided by 52 */ + SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1BU), /**< SYSCLK divided by 54 */ + SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1CU), /**< SYSCLK divided by 56 */ + SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1DU), /**< SYSCLK divided by 58 */ + SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1EU), /**< SYSCLK divided by 60 */ + SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1FU), /**< SYSCLK divided by 62 */ } smartcard_prescaler_t; /** @@ -100,69 +98,66 @@ typedef enum /** * @brief SMARTCARD Init Structure definition */ -typedef struct -{ - uint32_t baud; /**< This member configures the SmartCard communication baud rate. */ - usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ - usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ - usart_parity_t parity; /**< Specifies the parity mode. +typedef struct { + uint32_t baud; /**< This member configures the SmartCard communication baud rate. */ + usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ + usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ + usart_parity_t parity; /**< Specifies the parity mode. @note When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).*/ - usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */ - usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ - usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/ - usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted + usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */ + usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ + usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/ + usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref usart_last_bit_t */ - smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock + smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock to provide the smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency. */ - uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */ - type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */ + uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */ + type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */ } smartcard_init_t; /** * @brief ALD state structures definition */ -typedef enum -{ - SMARTCARD_STATE_RESET = 0x00, /**< Peripheral is not yet Initialized */ - SMARTCARD_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - SMARTCARD_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - SMARTCARD_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - SMARTCARD_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ - SMARTCARD_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission and Reception process is ongoing */ - SMARTCARD_STATE_TIMEOUT = 0x03, /**< Timeout state */ - SMARTCARD_STATE_ERROR = 0x04 /**< Error */ +typedef enum { + SMARTCARD_STATE_RESET = 0x00U, /**< Peripheral is not yet Initialized */ + SMARTCARD_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + SMARTCARD_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + SMARTCARD_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ + SMARTCARD_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ + SMARTCARD_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission and Reception process is ongoing */ + SMARTCARD_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + SMARTCARD_STATE_ERROR = 0x04U, /**< Error */ } smartcard_state_t; /** * @brief SMARTCARD handle structure definition */ -typedef struct smartcard_handle_s -{ - USART_TypeDef *perh; /**< USART registers base address */ - smartcard_init_t init; /**< SmartCard communication parameters */ - uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */ - uint16_t tx_size; /**< SmartCard Tx Transfer size */ - uint16_t tx_count; /**< SmartCard Tx Transfer Counter */ - uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */ - uint16_t rx_size; /**< SmartCard Rx Transfer size */ - uint16_t rx_count; /**< SmartCard Rx Transfer Counter */ +typedef struct smartcard_handle_s { + USART_TypeDef *perh; /**< USART registers base address */ + smartcard_init_t init; /**< SmartCard communication parameters */ + uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */ + uint16_t tx_size; /**< SmartCard Tx Transfer size */ + uint16_t tx_count; /**< SmartCard Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */ + uint16_t rx_size; /**< SmartCard Rx Transfer size */ + uint16_t rx_count; /**< SmartCard Rx Transfer Counter */ #ifdef ALD_DMA - dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */ - dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */ + dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */ + dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */ #endif - lock_state_t lock; /**< Locking object */ - smartcard_state_t state; /**< SmartCard communication state */ - uint32_t err_code; /**< SmartCard Error code */ + lock_state_t lock; /**< Locking object */ + smartcard_state_t state; /**< SmartCard communication state */ + uint32_t err_code; /**< SmartCard Error code */ - void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */ + void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */ } smartcard_handle_t; /** @@ -214,7 +209,7 @@ typedef struct smartcard_handle_s */ #define IS_SMARTCARD_PRESCALER(x) (((x) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \ - ((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62)) + ((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62)) /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h index d92aefb219bd36f88c6b54c2f17eb07cdb7d180a..1a7c7c7e5ead6a5c1d4a196d87897625a86aca89 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h @@ -18,7 +18,7 @@ #define __ALD_SPI_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -39,97 +39,88 @@ extern "C" { /** * @brief clock phase */ -typedef enum -{ - SPI_CPHA_FIRST = 0, /**< Transiting data in the first edge */ - SPI_CPHA_SECOND = 1, /**< Transiting data in the seconde edge */ +typedef enum { + SPI_CPHA_FIRST = 0U, /**< Transiting data in the first edge */ + SPI_CPHA_SECOND = 1U, /**< Transiting data in the seconde edge */ } spi_cpha_t; /** * @brief clock polarity */ -typedef enum -{ - SPI_CPOL_LOW = 0, /**< Polarity hold low when spi-bus is idle */ - SPI_CPOL_HIGH = 1, /**< Polarity hold high when spi-bus is idle */ +typedef enum { + SPI_CPOL_LOW = 0U, /**< Polarity hold low when spi-bus is idle */ + SPI_CPOL_HIGH = 1U, /**< Polarity hold high when spi-bus is idle */ } spi_cpol_t; /** * @brief master selection */ -typedef enum -{ - SPI_MODE_SLAVER = 0, /**< Slave mode */ - SPI_MODE_MASTER = 1, /**< Master mode */ +typedef enum { + SPI_MODE_SLAVER = 0U, /**< Slave mode */ + SPI_MODE_MASTER = 1U, /**< Master mode */ } spi_mode_t; /** * @brief baud rate control */ -typedef enum -{ - SPI_BAUD_2 = 0, /**< fpclk/2 */ - SPI_BAUD_4 = 1, /**< fpclk/4 */ - SPI_BAUD_8 = 2, /**< fpclk/8 */ - SPI_BAUD_16 = 3, /**< fpclk/16 */ - SPI_BAUD_32 = 4, /**< fpclk/32 */ - SPI_BAUD_64 = 5, /**< fpclk/64 */ - SPI_BAUD_128 = 6, /**< fpclk/128 */ - SPI_BAUD_256 = 7, /**< fpclk/256 */ +typedef enum { + SPI_BAUD_2 = 0U, /**< fpclk/2 */ + SPI_BAUD_4 = 1U, /**< fpclk/4 */ + SPI_BAUD_8 = 2U, /**< fpclk/8 */ + SPI_BAUD_16 = 3U, /**< fpclk/16 */ + SPI_BAUD_32 = 4U, /**< fpclk/32 */ + SPI_BAUD_64 = 5U, /**< fpclk/64 */ + SPI_BAUD_128 = 6U, /**< fpclk/128 */ + SPI_BAUD_256 = 7U, /**< fpclk/256 */ } spi_baud_t; /** * @brief frame format */ -typedef enum -{ - SPI_FIRSTBIT_MSB = 0, /**< MSB transmitted first */ - SPI_FIRSTBIT_LSB = 1, /**< LSB transmitted first */ +typedef enum { + SPI_FIRSTBIT_MSB = 0U, /**< MSB transmitted first */ + SPI_FIRSTBIT_LSB = 1U, /**< LSB transmitted first */ } spi_firstbit_t; /** * @brief data frame format */ -typedef enum -{ - SPI_DATA_SIZE_8 = 0, /**< 8-bit data frame format is selected for transmission/reception */ - SPI_DATA_SIZE_16 = 1, /**< 16-bit data frame format is selected for transmission/reception */ +typedef enum { + SPI_DATA_SIZE_8 = 0U, /**< 8-bit data frame format is selected for transmission/reception */ + SPI_DATA_SIZE_16 = 1U, /**< 16-bit data frame format is selected for transmission/reception */ } spi_datasize_t; /** * @brief interrupt control */ -typedef enum -{ - SPI_IT_ERR = (1U << 5), /**< error interrupt */ - SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */ - SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */ +typedef enum { + SPI_IT_ERR = (1U << 5), /**< error interrupt */ + SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */ + SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */ } spi_it_t; /** * @brief interrupt flag */ -typedef enum -{ - SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */ - SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */ - SPI_IF_CRCERR = (1U << 4), /**< crc error flag */ - SPI_IF_MODF = (1U << 5), /**< mode fault */ - SPI_IF_OVE = (1U << 6), /**< overrun flag */ - SPI_IF_BUSY = (1U << 7), /**< busy flag */ +typedef enum { + SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */ + SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */ + SPI_IF_CRCERR = (1U << 4), /**< crc error flag */ + SPI_IF_MODF = (1U << 5), /**< mode fault */ + SPI_IF_OVE = (1U << 6), /**< overrun flag */ + SPI_IF_BUSY = (1U << 7), /**< busy flag */ } spi_flag_t; /** * @brief SPI error status */ -typedef enum -{ - SPI_ERROR_NONE = 0, /**< none */ - SPI_ERROR_MODF = 1, /**< mode fault */ - SPI_ERROR_CRC = 2, /**< crc error */ - SPI_ERROR_OVE = 4, /**< overrun error */ - SPI_ERROR_DMA = 8, /**< dma error */ - SPI_ERROR_FLAG = 0x10, /**< interrupt flag error */ +typedef enum { + SPI_ERROR_NONE = 0U, /**< none */ + SPI_ERROR_MODF = 1U, /**< mode fault */ + SPI_ERROR_CRC = 2U, /**< crc error */ + SPI_ERROR_OVE = 4U, /**< overrun error */ + SPI_ERROR_DMA = 8U, /**< dma error */ + SPI_ERROR_FLAG = 0x10U, /**< interrupt flag error */ } spi_error_t; @@ -137,104 +128,97 @@ typedef enum /** * @brief SPI state structures definition */ -typedef enum -{ - SPI_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - SPI_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - SPI_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - SPI_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */ - SPI_STATE_BUSY_RX = 0x21, /**< receive is ongoing */ - SPI_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */ - SPI_STATE_TIMEOUT = 0x03, /**< Timeout state */ - SPI_STATE_ERROR = 0x04, /**< Error */ +typedef enum { + SPI_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + SPI_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + SPI_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + SPI_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */ + SPI_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */ + SPI_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */ + SPI_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + SPI_STATE_ERROR = 0x04U, /**< Error */ } spi_state_t; /** * @brief SPI status definition */ -typedef enum -{ - SPI_STATUS_RXBNE = (1U << 0), /**< Receive not empty status */ - SPI_STATUS_TXBE = (1U << 1), /**< Transmit empty status */ - SPI_STATUS_CRCERR = (1U << 4), /**< CRC error status */ - SPI_STATUS_MODEERR = (1U << 5), /**< Mode error status */ - SPI_STATUS_OVERR = (1U << 6), /**< Overflow status */ - SPI_STATUS_BUSY = (1U << 7), /**< Busy status */ +typedef enum { + SPI_STATUS_RXBNE = (1U << 0), /**< Receive not empty status */ + SPI_STATUS_TXBE = (1U << 1), /**< Transmit empty status */ + SPI_STATUS_CRCERR = (1U << 4), /**< CRC error status */ + SPI_STATUS_MODEERR = (1U << 5), /**< Mode error status */ + SPI_STATUS_OVERR = (1U << 6), /**< Overflow status */ + SPI_STATUS_BUSY = (1U << 7), /**< Busy status */ } spi_status_t; /** * @brief SPI direction definition */ -typedef enum -{ - SPI_DIRECTION_2LINES = 0, /**< 2 lines */ - SPI_DIRECTION_2LINES_RXONLY = 1, /**< 2 lines only rx */ - SPI_DIRECTION_1LINE = 2, /**< 1 line */ - SPI_DIRECTION_1LINE_RX = 3, /**< 1 line only rx */ +typedef enum { + SPI_DIRECTION_2LINES = 0U, /**< 2 lines */ + SPI_DIRECTION_2LINES_RXONLY = 1U, /**< 2 lines only rx */ + SPI_DIRECTION_1LINE = 2U, /**< 1 line */ + SPI_DIRECTION_1LINE_RX = 3U, /**< 1 line only rx */ } spi_direction_t; /** * @brief SPI dma request definition */ -typedef enum -{ - SPI_DMA_REQ_TX = 0, /**< TX dma request */ - SPI_DMA_REQ_RX = 1, /**< RX dma request */ +typedef enum { + SPI_DMA_REQ_TX = 0U, /**< TX dma request */ + SPI_DMA_REQ_RX = 1U, /**< RX dma request */ } spi_dma_req_t; /** * @brief SPI TXE/RXNE status definition */ -typedef enum -{ - SPI_SR_TXBE = 0, /**< SR.TXE set */ - SPI_SR_RXBNE = 1, /**< SR.RXNE set */ - SPI_SR_TXBE_RXBNE = 2, /**< SR.TXE and SR.RXNE set */ +typedef enum { + SPI_SR_TXBE = 0U, /**< SR.TXE set */ + SPI_SR_RXBNE = 1U, /**< SR.RXNE set */ + SPI_SR_TXBE_RXBNE = 2U, /**< SR.TXE and SR.RXNE set */ } spi_sr_status_t; /** * @brief SPI init structure definition */ -typedef struct -{ - spi_mode_t mode; /**< SPI mode */ - spi_direction_t dir; /**< SPI direction */ - spi_datasize_t data_size; /**< SPI data size */ - spi_baud_t baud; /**< SPI baudrate prescaler */ - spi_cpha_t phase; /**< SPI clock phase */ - spi_cpol_t polarity; /**< SPI clock polarity */ - spi_firstbit_t first_bit; /**< SPI first bit */ - type_func_t ss_en; /**< SPI ssm enable or disable */ - type_func_t crc_calc; /**< SPI crc calculation */ - uint16_t crc_poly; /**< SPI crc polynomial */ +typedef struct { + spi_mode_t mode; /**< SPI mode */ + spi_direction_t dir; /**< SPI direction */ + spi_datasize_t data_size; /**< SPI data size */ + spi_baud_t baud; /**< SPI baudrate prescaler */ + spi_cpha_t phase; /**< SPI clock phase */ + spi_cpol_t polarity; /**< SPI clock polarity */ + spi_firstbit_t first_bit; /**< SPI first bit */ + type_func_t ss_en; /**< SPI ssm enable or disable */ + type_func_t crc_calc; /**< SPI crc calculation */ + uint16_t crc_poly; /**< SPI crc polynomial */ } spi_init_t; /** * @brief SPI handle structure definition */ -typedef struct spi_handle_s -{ - SPI_TypeDef *perh; /**< SPI registers base address */ - spi_init_t init; /**< SPI communication parameters */ - uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */ - uint16_t tx_size; /**< SPI Tx transfer size */ - uint16_t tx_count; /**< SPI Tx transfer counter */ - uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */ - uint16_t rx_size; /**< SPI Rx Transfer size */ - uint16_t rx_count; /**< SPI Rx Transfer Counter */ +typedef struct spi_handle_s { + SPI_TypeDef *perh; /**< SPI registers base address */ + spi_init_t init; /**< SPI communication parameters */ + uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */ + uint16_t tx_size; /**< SPI Tx transfer size */ + uint16_t tx_count; /**< SPI Tx transfer counter */ + uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */ + uint16_t rx_size; /**< SPI Rx Transfer size */ + uint16_t rx_count; /**< SPI Rx Transfer Counter */ #ifdef ALD_DMA - dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */ + dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */ #endif - lock_state_t lock; /**< Locking object */ - spi_state_t state; /**< SPI communication state */ - uint32_t err_code; /**< SPI error code */ - - void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */ - void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */ - void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */ + lock_state_t lock; /**< Locking object */ + spi_state_t state; /**< SPI communication state */ + uint32_t err_code; /**< SPI error code */ + + void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */ + void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */ + void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */ } spi_handle_t; /** * @} @@ -247,10 +231,10 @@ typedef struct spi_handle_s #define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS)) #define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS)) #define SPI_CRC_RESET(x) \ - do { \ - CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ - SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ - } while (0) +do { \ + CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ + SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ +} while (0) #define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) #define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) #define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) @@ -268,9 +252,12 @@ typedef struct spi_handle_s /** @defgroup SPI_Private_Macros SPI Private Macros * @{ */ -#define IS_SPI(x) (((x) == SPI0) || \ - ((x) == SPI1) || \ - ((x) == SPI2)) +#if defined(ES32F065x) || defined(ES32F033x) +#define IS_SPI(x) (((x) == SPI0) || ((x) == SPI1)) +#endif +#if defined(ES32F093x) +#define IS_SPI(x) (((x) == SPI0) || ((x) == SPI1) || ((x) == SPI2)) +#endif #define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \ ((x) == SPI_CPHA_SECOND)) #define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \ @@ -286,20 +273,22 @@ typedef struct spi_handle_s ((x) == SPI_BAUD_128) || \ ((x) == SPI_BAUD_256)) #define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \ - ((x) == SPI_DATA_SIZE_16)) + ((x) == SPI_DATA_SIZE_16)) +#define IS_SPI_FIRSTBIT(x) (((x) == SPI_FIRSTBIT_MSB) || \ + ((x) == SPI_FIRSTBIT_LSB)) #define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \ - ((x) == SPI_BID_TX)) + ((x) == SPI_BID_TX)) #define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \ - ((x) == SPI_BIDMODE_SOLE)) + ((x) == SPI_BIDMODE_SOLE)) #define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \ - ((x) == SPI_DIRECTION_2LINES_RXONLY) || \ - ((x) == SPI_DIRECTION_1LINE) || \ - ((x) == SPI_DIRECTION_1LINE_RX)) + ((x) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((x) == SPI_DIRECTION_1LINE) || \ + ((x) == SPI_DIRECTION_1LINE_RX)) #define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \ - ((x) == SPI_DMA_REQ_RX)) + ((x) == SPI_DMA_REQ_RX)) #define IS_SPI_SR_STATUS(x) (((x) == SPI_SR_TXBE) || \ - ((x) == SPI_SR_RXBNE) || \ - ((x) == SPI_SR_TXBE_RXBNE)) + ((x) == SPI_SR_RXBNE) || \ + ((x) == SPI_SR_TXBE_RXBNE)) #define IS_SPI_IT(x) (((x) == SPI_IT_ERR) || \ ((x) == SPI_IT_RXBNE) || \ ((x) == SPI_IT_TXBE)) @@ -310,11 +299,11 @@ typedef struct spi_handle_s ((x) == SPI_IF_OVE) || \ ((x) == SPI_IF_BUSY)) #define IS_SPI_STATUS(x) (((x) == SPI_STATUS_RXBNE) || \ - ((x) == SPI_STATUS_TXBE) || \ - ((x) == SPI_STATUS_CRCERR) || \ - ((x) == SPI_STATUS_MODEERR) || \ - ((x) == SPI_STATUS_OVERR) || \ - ((x) == SPI_STATUS_BUSY)) + ((x) == SPI_STATUS_TXBE) || \ + ((x) == SPI_STATUS_CRCERR) || \ + ((x) == SPI_STATUS_MODEERR) || \ + ((x) == SPI_STATUS_OVERR) || \ + ((x) == SPI_STATUS_BUSY)) /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h index d173be011f324fc1bfbb603fbef600f7f14bdebe..35844c887edf1c20bb2292ccaecdedc06fa0745a 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h @@ -18,7 +18,7 @@ #define __ALD_SYSCFG_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -36,33 +36,33 @@ extern "C" { /** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros * @{ */ -#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0) -#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996) +#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0U) +#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996U) #define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK) #define BOOT_FROM_BOOT_ROM() \ - do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define BOOT_FROM_BOOT_FLASH() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) #define BOOT_FROM_FLASH() \ - do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ - } while (0) +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) /** * @} */ @@ -73,20 +73,18 @@ extern "C" { */ __STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status) { - SYSCFG_UNLOCK(); - - if (status) - { - MODIFY_REG(SYSCFG->VTOR, SYSCFG_VTOR_VTO_MSK, (offset & ~0x3F)); - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK); - } - else - { - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK); - } - - SYSCFG_LOCK(); - return; + SYSCFG_UNLOCK(); + + if (status) { + MODIFY_REG(SYSCFG->VTOR, SYSCFG_VTOR_VTO_MSK, (offset & ~0x3FU)); + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK); + } + else { + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK); + } + + SYSCFG_LOCK(); + return; } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h index 9fe5ee6d6445ab35e2f8e49becf616b63f24c3c9..538fc0ca0b064ae745aaf0275fe9e0fef2046bf3 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h @@ -19,7 +19,7 @@ #define __ALD_TIMER_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -40,527 +40,488 @@ extern "C" { /** * @brief TIMER counter mode */ -typedef enum -{ - TIMER_CNT_MODE_UP = 0, /**< Counter mode up */ - TIMER_CNT_MODE_DOWN = 1, /**< Counter mode down */ - TIMER_CNT_MODE_CENTER1 = 2, /**< Counter mode center1 */ - TIMER_CNT_MODE_CENTER2 = 3, /**< Counter mode center2 */ - TIMER_CNT_MODE_CENTER3 = 4, /**< Counter mode center3 */ +typedef enum { + TIMER_CNT_MODE_UP = 0U, /**< Counter mode up */ + TIMER_CNT_MODE_DOWN = 1U, /**< Counter mode down */ + TIMER_CNT_MODE_CENTER1 = 2U, /**< Counter mode center1 */ + TIMER_CNT_MODE_CENTER2 = 3U, /**< Counter mode center2 */ + TIMER_CNT_MODE_CENTER3 = 4U, /**< Counter mode center3 */ } timer_cnt_mode_t; /** * @brief TIMER clock division */ -typedef enum -{ - TIMER_CLOCK_DIV1 = 0, /**< No prescaler is used */ - TIMER_CLOCK_DIV2 = 1, /** Clock is divided by 2 */ - TIMER_CLOCK_DIV4 = 2, /** Clock is divided by 4 */ +typedef enum { + TIMER_CLOCK_DIV1 = 0U, /**< No prescaler is used */ + TIMER_CLOCK_DIV2 = 1U, /** Clock is divided by 2 */ + TIMER_CLOCK_DIV4 = 2U, /** Clock is divided by 4 */ } timer_clock_division_t; /** * @brief TIMER output compare and PWM modes */ -typedef enum -{ - TIMER_OC_MODE_TIMERING = 0, /**< Output compare mode is timering */ - TIMER_OC_MODE_ACTIVE = 1, /**< Output compare mode is active */ - TIMER_OC_MODE_INACTIVE = 2, /**< Output compare mode is inactive */ - TIMER_OC_MODE_TOGGLE = 3, /**< Output compare mode is toggle */ - TIMER_OC_MODE_FORCE_INACTIVE = 4, /**< Output compare mode is force inactive */ - TIMER_OC_MODE_FORCE_ACTIVE = 5, /**< Output compare mode is force active */ - TIMER_OC_MODE_PWM1 = 6, /**< Output compare mode is pwm1 */ - TIMER_OC_MODE_PWM2 = 7, /**< Output compare mode is pwm2 */ +typedef enum { + TIMER_OC_MODE_TIMERING = 0U, /**< Output compare mode is timering */ + TIMER_OC_MODE_ACTIVE = 1U, /**< Output compare mode is active */ + TIMER_OC_MODE_INACTIVE = 2U, /**< Output compare mode is inactive */ + TIMER_OC_MODE_TOGGLE = 3U, /**< Output compare mode is toggle */ + TIMER_OC_MODE_FORCE_INACTIVE = 4U, /**< Output compare mode is force inactive */ + TIMER_OC_MODE_FORCE_ACTIVE = 5U, /**< Output compare mode is force active */ + TIMER_OC_MODE_PWM1 = 6U, /**< Output compare mode is pwm1 */ + TIMER_OC_MODE_PWM2 = 7U, /**< Output compare mode is pwm2 */ } timer_oc_mode_t; /** * @brief TIMER output compare polarity */ -typedef enum -{ - TIMER_OC_POLARITY_HIGH = 0, /**< Output compare polarity is high */ - TIMER_OC_POLARITY_LOW = 1, /**< Output compare polarity is low */ +typedef enum { + TIMER_OC_POLARITY_HIGH = 0U, /**< Output compare polarity is high */ + TIMER_OC_POLARITY_LOW = 1U, /**< Output compare polarity is low */ } timer_oc_polarity_t; /** * @brief TIMER complementary output compare polarity */ -typedef enum -{ - TIMER_OCN_POLARITY_HIGH = 0, /**< Complementary output compare polarity is high */ - TIMER_OCN_POLARITY_LOW = 1, /**< Complementary output compare polarity is low */ +typedef enum { + TIMER_OCN_POLARITY_HIGH = 0U, /**< Complementary output compare polarity is high */ + TIMER_OCN_POLARITY_LOW = 1U, /**< Complementary output compare polarity is low */ } timer_ocn_polarity_t; /** * @brief TIMER output compare idle state */ -typedef enum -{ - TIMER_OC_IDLE_RESET = 0, /**< Output compare idle state is reset */ - TIMER_OC_IDLE_SET = 1, /**< Output compare idle state is set */ +typedef enum { + TIMER_OC_IDLE_RESET = 0U, /**< Output compare idle state is reset */ + TIMER_OC_IDLE_SET = 1U, /**< Output compare idle state is set */ } timer_oc_idle_t; /** * @brief TIMER complementary output compare idle state */ -typedef enum -{ - TIMER_OCN_IDLE_RESET = 0, /**< Complementary output compare idle state is reset */ - TIMER_OCN_IDLE_SET = 1, /**< Complementary output compare idle state is set */ +typedef enum { + TIMER_OCN_IDLE_RESET = 0U, /**< Complementary output compare idle state is reset */ + TIMER_OCN_IDLE_SET = 1U, /**< Complementary output compare idle state is set */ } timer_ocn_idle_t; /** * @brief TIMER channel */ -typedef enum -{ - TIMER_CHANNEL_1 = 0, /**< Channel 1 */ - TIMER_CHANNEL_2 = 1, /**< Channel 2 */ - TIMER_CHANNEL_3 = 2, /**< Channel 3 */ - TIMER_CHANNEL_4 = 4, /**< Channel 4 */ - TIMER_CHANNEL_ALL = 0xF, /**< All channel */ +typedef enum { + TIMER_CHANNEL_1 = 0U, /**< Channel 1 */ + TIMER_CHANNEL_2 = 1U, /**< Channel 2 */ + TIMER_CHANNEL_3 = 2U, /**< Channel 3 */ + TIMER_CHANNEL_4 = 4U, /**< Channel 4 */ + TIMER_CHANNEL_ALL = 0xFU, /**< All channel */ } timer_channel_t; /** * @brief TIMER one pulse mode */ -typedef enum -{ - TIMER_OP_MODE_REPEAT = 0, /**< Repetitive */ - TIMER_OP_MODE_SINGLE = 1, /**< single */ +typedef enum { + TIMER_OP_MODE_REPEAT = 0U, /**< Repetitive */ + TIMER_OP_MODE_SINGLE = 1U, /**< single */ } timer_op_mode_t; /** * @brief TIMER one pulse output channel */ -typedef enum -{ - TIMER_OP_OUTPUT_CHANNEL_1 = 0, /**< One pulse output channal 1 */ - TIMER_OP_OUTPUT_CHANNEL_2 = 1, /**< One pulse output channal 2 */ +typedef enum { + TIMER_OP_OUTPUT_CHANNEL_1 = 0U, /**< One pulse output channal 1 */ + TIMER_OP_OUTPUT_CHANNEL_2 = 1U, /**< One pulse output channal 2 */ } timer_op_output_channel_t; /** * @brief TIMER time base configuration structure definition */ -typedef struct -{ - uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ - timer_cnt_mode_t mode; /**< Specifies the counter mode. */ - uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ - timer_clock_division_t clk_div; /**< Specifies the clock division.*/ - uint32_t re_cnt; /**< Specifies the repetition counter value. */ +typedef struct { + uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ + timer_cnt_mode_t mode; /**< Specifies the counter mode. */ + uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ + timer_clock_division_t clk_div; /**< Specifies the clock division.*/ + uint32_t re_cnt; /**< Specifies the repetition counter value. */ } timer_base_init_t; /** * @brief TIMER output compare configuration structure definition */ -typedef struct -{ - timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ - uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ - timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ - timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ - type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ - timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ - timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ +typedef struct { + timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ + uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ + timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ + timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ + type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ + timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ + timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ } timer_oc_init_t; /** * @brief State structures definition */ -typedef enum -{ - TIMER_STATE_RESET = 0x00, /**< Peripheral not yet initialized or disabled */ - TIMER_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - TIMER_STATE_BUSY = 0x02, /**< An internal process is ongoing */ - TIMER_STATE_TIMEREOUT = 0x03, /**< Timeout state */ - TIMER_STATE_ERROR = 0x04, /**< Reception process is ongoing */ +typedef enum { + TIMER_STATE_RESET = 0x00U, /**< Peripheral not yet initialized or disabled */ + TIMER_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + TIMER_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ + TIMER_STATE_TIMEREOUT = 0x03U, /**< Timeout state */ + TIMER_STATE_ERROR = 0x04U, /**< Reception process is ongoing */ } timer_state_t; /** * @brief Active channel structures definition */ -typedef enum -{ - TIMER_ACTIVE_CHANNEL_1 = 0x01, /**< The active channel is 1 */ - TIMER_ACTIVE_CHANNEL_2 = 0x02, /**< The active channel is 2 */ - TIMER_ACTIVE_CHANNEL_3 = 0x04, /**< The active channel is 3 */ - TIMER_ACTIVE_CHANNEL_4 = 0x08, /**< The active channel is 4 */ - TIMER_ACTIVE_CHANNEL_CLEARED = 0x00, /**< All active channels cleared */ +typedef enum { + TIMER_ACTIVE_CHANNEL_1 = 0x01U, /**< The active channel is 1 */ + TIMER_ACTIVE_CHANNEL_2 = 0x02U, /**< The active channel is 2 */ + TIMER_ACTIVE_CHANNEL_3 = 0x04U, /**< The active channel is 3 */ + TIMER_ACTIVE_CHANNEL_4 = 0x08U, /**< The active channel is 4 */ + TIMER_ACTIVE_CHANNEL_CLEARED = 0x00U, /**< All active channels cleared */ } timer_active_channel_t; /** * @brief TIMER time base handle structure definition */ -typedef struct timer_handle_s -{ - TIMER_TypeDef *perh; /**< Register base address */ - timer_base_init_t init; /**< TIMER Time Base required parameters */ - timer_active_channel_t ch; /**< Active channel */ - lock_state_t lock; /**< Locking object */ - timer_state_t state; /**< TIMER operation state */ - - void (*period_elapse_cbk)(struct timer_handle_s *arg); /**< Period elapse callback */ - void (*delay_elapse_cbk)(struct timer_handle_s *arg); /**< Delay_elapse callback */ - void (*capture_cbk)(struct timer_handle_s *arg); /**< Capture callback */ - void (*pwm_pulse_finish_cbk)(struct timer_handle_s *arg); /**< PWM_pulse_finish callback */ - void (*trigger_cbk)(struct timer_handle_s *arg); /**< Trigger callback */ - void (*break_cbk)(struct timer_handle_s *arg); /**< Break callback */ - void (*com_cbk)(struct timer_handle_s *arg); /**< commutation callback */ - void (*error_cbk)(struct timer_handle_s *arg); /**< Error callback */ +typedef struct timer_handle_s { + TIMER_TypeDef *perh; /**< Register base address */ + timer_base_init_t init; /**< TIMER Time Base required parameters */ + timer_active_channel_t ch; /**< Active channel */ + lock_state_t lock; /**< Locking object */ + timer_state_t state; /**< TIMER operation state */ + +#ifdef ALD_DMA + dma_handle_t hdma1; /**< Timer DMA handle parameters */ + dma_handle_t hdma2; +#endif + + void (*period_elapse_cbk)(struct timer_handle_s *arg); /**< Period elapse callback */ + void (*delay_elapse_cbk)(struct timer_handle_s *arg); /**< Delay_elapse callback */ + void (*capture_cbk)(struct timer_handle_s *arg); /**< Capture callback */ + void (*pwm_pulse_finish_cbk)(struct timer_handle_s *arg); /**< PWM_pulse_finish callback */ + void (*trigger_cbk)(struct timer_handle_s *arg); /**< Trigger callback */ + void (*break_cbk)(struct timer_handle_s *arg); /**< Break callback */ + void (*com_cbk)(struct timer_handle_s *arg); /**< commutation callback */ + void (*error_cbk)(struct timer_handle_s *arg); /**< Error callback */ } timer_handle_t; /** * @brief TIMER encoder mode */ -typedef enum -{ - TIMER_ENC_MODE_TI1 = 1, /**< encoder mode 1 */ - TIMER_ENC_MODE_TI2 = 2, /**< encoder mode 2 */ - TIMER_ENC_MODE_TI12 = 3, /**< encoder mode 3 */ +typedef enum { + TIMER_ENC_MODE_TI1 = 1U, /**< encoder mode 1 */ + TIMER_ENC_MODE_TI2 = 2U, /**< encoder mode 2 */ + TIMER_ENC_MODE_TI12 = 3U, /**< encoder mode 3 */ } timer_encoder_mode_t; /** * @brief TIMER input capture polarity */ -typedef enum -{ - TIMER_IC_POLARITY_RISE = 0, /**< Input capture polarity rising */ - TIMER_IC_POLARITY_FALL = 1, /**< Input capture polarity falling */ +typedef enum { + TIMER_IC_POLARITY_RISE = 0U, /**< Input capture polarity rising */ + TIMER_IC_POLARITY_FALL = 1U, /**< Input capture polarity falling */ } timer_ic_polarity_t; /** *@brief TIMER input capture selection */ -typedef enum -{ - TIMER_IC_SEL_DIRECT = 1, /**< IC1 -- TI1 */ - TIMER_IC_SEL_INDIRECT = 2, /**< IC1 -- TI2 */ - TIMER_IC_SEL_TRC = 3, /**< IC1 -- TRC */ +typedef enum { + TIMER_IC_SEL_DIRECT = 1U, /**< IC1 -- TI1 */ + TIMER_IC_SEL_INDIRECT = 2U, /**< IC1 -- TI2 */ + TIMER_IC_SEL_TRC = 3U, /**< IC1 -- TRC */ } timer_ic_select_t; /** * @brief TIMER input capture prescaler */ -typedef enum -{ - TIMER_IC_PSC_DIV1 = 0, /**< Capture performed once every 1 events */ - TIMER_IC_PSC_DIV2 = 1, /**< Capture performed once every 2 events */ - TIMER_IC_PSC_DIV4 = 2, /**< Capture performed once every 4 events */ - TIMER_IC_PSC_DIV8 = 3, /**< Capture performed once every 4 events */ +typedef enum { + TIMER_IC_PSC_DIV1 = 0U, /**< Capture performed once every 1 events */ + TIMER_IC_PSC_DIV2 = 1U, /**< Capture performed once every 2 events */ + TIMER_IC_PSC_DIV4 = 2U, /**< Capture performed once every 4 events */ + TIMER_IC_PSC_DIV8 = 3U, /**< Capture performed once every 4 events */ } timer_ic_prescaler_t; /** * @brief TIMER encoder configuration structure definition */ -typedef struct -{ - timer_encoder_mode_t mode; /**< Specifies the encoder mode */ - timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t ic1_sel; /**< Specifies the input */ - timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ - uint32_t ic1_filter; /**< Specifies the input capture filter */ - timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t ic2_sel; /**< Specifies the input */ - timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ - uint32_t ic2_filter; /**< Specifies the input capture filter */ +typedef struct { + timer_encoder_mode_t mode; /**< Specifies the encoder mode */ + timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t ic1_sel; /**< Specifies the input */ + timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic1_filter; /**< Specifies the input capture filter */ + timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t ic2_sel; /**< Specifies the input */ + timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic2_filter; /**< Specifies the input capture filter */ } timer_encoder_init_t; /** * @brief TIMER input capture configuration structure definition */ -typedef struct -{ - timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t sel; /**< Specifies the input */ - timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ - uint32_t filter; /**< Specifies the input capture filter */ +typedef struct { + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t sel; /**< Specifies the input */ + timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter */ } timer_ic_init_t; /** * @brief TIMER one pulse mode configuration structure definition */ -typedef struct -{ - timer_oc_mode_t mode; /**< Specifies the TIMER mode */ - uint16_t pulse; /**< Specifies the pulse value */ - timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ - timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ - timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ - timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ - timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t sel; /**< Specifies the input */ - uint32_t filter; /**< Specifies the input capture filter */ +typedef struct { + timer_oc_mode_t mode; /**< Specifies the TIMER mode */ + uint16_t pulse; /**< Specifies the pulse value */ + timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ + timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ + timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t sel; /**< Specifies the input */ + uint32_t filter; /**< Specifies the input capture filter */ } timer_one_pulse_init_t; /** @brief TIMER clear input source */ -typedef enum -{ - TIMER_INPUT_NONE = 0, /**< Clear input none */ - TIMER_INPUT_ETR = 1, /**< Clear input etr */ +typedef enum { + TIMER_INPUT_NONE = 0U, /**< Clear input none */ + TIMER_INPUT_ETR = 1U, /**< Clear input etr */ } timer_clear_input_source_t; /** @brief TIMER clear input polarity */ -typedef enum -{ - TIMER_POLARITY_NO_INV = 0, /**< Polarity for ETRx pin */ - TIMER_POLARITY_INV = 1, /**< Polarity for ETRx pin */ +typedef enum { + TIMER_POLARITY_NO_INV = 0U, /**< Polarity for ETRx pin */ + TIMER_POLARITY_INV = 1U, /**< Polarity for ETRx pin */ } timer_clear_input_polarity_t; /** @brief TIMER clear input polarity */ -typedef enum -{ - TIMER_ETR_PSC_DIV1 = 0, /**< No prescaler is used */ - TIMER_ETR_PSC_DIV2 = 1, /**< ETR input source is divided by 2 */ - TIMER_ETR_PSC_DIV4 = 2, /**< ETR input source is divided by 4 */ - TIMER_ETR_PSC_DIV8 = 3, /**< ETR input source is divided by 8 */ +typedef enum { + TIMER_ETR_PSC_DIV1 = 0U, /**< No prescaler is used */ + TIMER_ETR_PSC_DIV2 = 1U, /**< ETR input source is divided by 2 */ + TIMER_ETR_PSC_DIV4 = 2U, /**< ETR input source is divided by 4 */ + TIMER_ETR_PSC_DIV8 = 3U, /**< ETR input source is divided by 8 */ } timer_etr_psc_t; /** * @brief TIMER clear input configuration handle structure definition */ -typedef struct -{ - type_func_t state; /**< TIMER clear Input state */ - timer_clear_input_source_t source; /**< TIMER clear Input sources */ - timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ - timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ - uint32_t filter; /**< TIMER Clear Input filter */ +typedef struct { + type_func_t state; /**< TIMER clear Input state */ + timer_clear_input_source_t source; /**< TIMER clear Input sources */ + timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ + timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ + uint32_t filter; /**< TIMER Clear Input filter */ } timer_clear_input_config_t; /** @brief TIMER clock source */ -typedef enum -{ - TIMER_SRC_ETRMODE2 = 0, /**< Clock source is etr mode2 */ - TIMER_SRC_INTER = 1, /**< Clock source is etr internal */ - TIMER_SRC_ITR0 = 2, /**< Clock source is etr itr0 */ - TIMER_SRC_ITR1 = 3, /**< Clock source is etr itr1 */ - TIMER_SRC_ITR2 = 4, /**< Clock source is etr itr2 */ - TIMER_SRC_ITR3 = 5, /**< Clock source is etr itr3 */ - TIMER_SRC_TI1ED = 6, /**< Clock source is etr ti1ed */ - TIMER_SRC_TI1 = 7, /**< Clock source is etr ti1 */ - TIMER_SRC_TI2 = 8, /**< Clock source is etr ti2 */ - TIMER_SRC_ETRMODE1 = 9, /**< Clock source is etr mode1 */ +typedef enum { + TIMER_SRC_ETRMODE2 = 0U, /**< Clock source is etr mode2 */ + TIMER_SRC_INTER = 1U, /**< Clock source is etr internal */ + TIMER_SRC_ITR0 = 2U, /**< Clock source is etr itr0 */ + TIMER_SRC_ITR1 = 3U, /**< Clock source is etr itr1 */ + TIMER_SRC_ITR2 = 4U, /**< Clock source is etr itr2 */ + TIMER_SRC_ITR3 = 5U, /**< Clock source is etr itr3 */ + TIMER_SRC_TI1ED = 6U, /**< Clock source is etr ti1ed */ + TIMER_SRC_TI1 = 7U, /**< Clock source is etr ti1 */ + TIMER_SRC_TI2 = 8U, /**< Clock source is etr ti2 */ + TIMER_SRC_ETRMODE1 = 9U, /**< Clock source is etr mode1 */ } timer_clock_source_t; /** @brief TIMER clock polarity */ -typedef enum -{ - TIMER_CLK_POLARITY_INV = 1, /**< Polarity for ETRx clock sources */ - TIMER_CLK_POLARITY_NO_INV = 0, /**< Polarity for ETRx clock sources */ - TIMER_CLK_POLARITY_RISE = 0, /**< Polarity for TIx clock sources */ - TIMER_CLK_POLARITY_FALL = 1, /**< Polarity for TIx clock sources */ - TIMER_CLK_POLARITY_BOTH = 3, /**< Polarity for TIx clock sources */ +typedef enum { + TIMER_CLK_POLARITY_INV = 1U, /**< Polarity for ETRx clock sources */ + TIMER_CLK_POLARITY_NO_INV = 0U, /**< Polarity for ETRx clock sources */ + TIMER_CLK_POLARITY_RISE = 0U, /**< Polarity for TIx clock sources */ + TIMER_CLK_POLARITY_FALL = 1U, /**< Polarity for TIx clock sources */ + TIMER_CLK_POLARITY_BOTH = 3U, /**< Polarity for TIx clock sources */ } timer_clock_polarity_t; /** * @brief TIMER clock config structure definition */ -typedef struct -{ - timer_clock_source_t source; /**< TIMER clock sources */ - timer_clock_polarity_t polarity; /**< TIMER clock polarity */ - timer_etr_psc_t psc; /**< TIMER clock prescaler */ - uint32_t filter; /**< TIMER clock filter */ +typedef struct { + timer_clock_source_t source; /**< TIMER clock sources */ + timer_clock_polarity_t polarity; /**< TIMER clock polarity */ + timer_etr_psc_t psc; /**< TIMER clock prescaler */ + uint32_t filter; /**< TIMER clock filter */ } timer_clock_config_t; /** * @brief TIMER slave mode */ -typedef enum -{ - TIMER_MODE_DISABLE = 0, /**< Slave mode is disable */ - TIMER_MODE_ENC1 = 1, /**< Slave mode is encoder1 */ - TIMER_MODE_ENC2 = 2, /**< Slave mode is encoder2 */ - TIMER_MODE_ENC3 = 3, /**< Slave mode is encoder3 */ - TIMER_MODE_RESET = 4, /**< Slave mode is reset */ - TIMER_MODE_GATED = 5, /**< Slave mode is gated */ - TIMER_MODE_TRIG = 6, /**< Slave mode is trigger */ - TIMER_MODE_EXTERNAL1 = 7, /**< Slave mode is external1 */ +typedef enum { + TIMER_MODE_DISABLE = 0U, /**< Slave mode is disable */ + TIMER_MODE_ENC1 = 1U, /**< Slave mode is encoder1 */ + TIMER_MODE_ENC2 = 2U, /**< Slave mode is encoder2 */ + TIMER_MODE_ENC3 = 3U, /**< Slave mode is encoder3 */ + TIMER_MODE_RESET = 4U, /**< Slave mode is reset */ + TIMER_MODE_GATED = 5U, /**< Slave mode is gated */ + TIMER_MODE_TRIG = 6U, /**< Slave mode is trigger */ + TIMER_MODE_EXTERNAL1 = 7U, /**< Slave mode is external1 */ } timer_slave_mode_t; /** * @brief TIMER ts definition */ -typedef enum -{ - TIMER_TS_ITR0 = 0, /**< ITR0 */ - TIMER_TS_ITR1 = 1, /**< ITR1 */ - TIMER_TS_ITR2 = 2, /**< ITR2 */ - TIMER_TS_ITR3 = 3, /**< ITR3 */ - TIMER_TS_TI1F_ED = 4, /**< TI1F_ED */ - TIMER_TS_TI1FP1 = 5, /**< TI1FP1 */ - TIMER_TS_TI2FP2 = 6, /**< TI2FP2 */ - TIMER_TS_ETRF = 7, /**< ETRF */ +typedef enum { + TIMER_TS_ITR0 = 0U, /**< ITR0 */ + TIMER_TS_ITR1 = 1U, /**< ITR1 */ + TIMER_TS_ITR2 = 2U, /**< ITR2 */ + TIMER_TS_ITR3 = 3U, /**< ITR3 */ + TIMER_TS_TI1F_ED = 4U, /**< TI1F_ED */ + TIMER_TS_TI1FP1 = 5U, /**< TI1FP1 */ + TIMER_TS_TI2FP2 = 6U, /**< TI2FP2 */ + TIMER_TS_ETRF = 7U, /**< ETRF */ } timer_ts_t; /** * @brief TIMER slave configuration structure definition */ -typedef struct -{ - timer_slave_mode_t mode; /**< Slave mode selection */ - timer_ts_t input; /**< Input Trigger source */ - timer_clock_polarity_t polarity; /**< Input Trigger polarity */ - timer_etr_psc_t psc; /**< Input trigger prescaler */ - uint32_t filter; /**< Input trigger filter */ +typedef struct { + timer_slave_mode_t mode; /**< Slave mode selection */ + timer_ts_t input; /**< Input Trigger source */ + timer_clock_polarity_t polarity; /**< Input Trigger polarity */ + timer_etr_psc_t psc; /**< Input trigger prescaler */ + uint32_t filter; /**< Input trigger filter */ } timer_slave_config_t; /** * @brief TIMER hall sensor configuretion structure definition */ -typedef struct -{ - timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ - timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ - uint32_t filter; /**< Specifies the input capture filter [0x0, 0xF] */ - uint32_t delay; /**< Specifies the pulse value to be loaded into the register [0x0, 0xFFFF] */ +typedef struct { + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter [0x0, 0xF] */ + uint32_t delay; /**< Specifies the pulse value to be loaded into the register [0x0, 0xFFFF] */ } timer_hall_sensor_init_t; /** * @brief TIMER lock level */ -typedef enum -{ - TIMER_LOCK_LEVEL_OFF = 0, /**< Lock off */ - TIMER_LOCK_LEVEL_1 = 1, /**< Lock level 1 */ - TIMER_LOCK_LEVEL_2 = 2, /**< Lock level 2 */ - TIMER_LOCK_LEVEL_3 = 3, /**< Lock level 3 */ +typedef enum { + TIMER_LOCK_LEVEL_OFF = 0U, /**< Lock off */ + TIMER_LOCK_LEVEL_1 = 1U, /**< Lock level 1 */ + TIMER_LOCK_LEVEL_2 = 2U, /**< Lock level 2 */ + TIMER_LOCK_LEVEL_3 = 3U, /**< Lock level 3 */ } timer_lock_level_t; /** * @brief TIMER break polarity */ -typedef enum -{ - TIMER_BREAK_POLARITY_LOW = 0, /**< LOW */ - TIMER_BREAK_POLARITY_HIGH = 1, /**< HIGH */ +typedef enum { + TIMER_BREAK_POLARITY_LOW = 0U, /**< LOW */ + TIMER_BREAK_POLARITY_HIGH = 1U, /**< HIGH */ } timer_break_polarity_t; /** * @brief TIMER break and dead time configuretion structure definition */ -typedef struct -{ - type_func_t off_run; /**< Enalbe/Disable off state in run mode */ - type_func_t off_idle; /**< Enalbe/Disable off state in idle mode */ - timer_lock_level_t lock_level; /**< Lock level */ - uint32_t dead_time; /**< Dead time, [0x0, 0xFF] */ - type_func_t break_state; /**< Break state */ - timer_break_polarity_t polarity; /**< Break input polarity */ - type_func_t auto_out; /**< Enalbe/Disable automatic output */ +typedef struct { + type_func_t off_run; /**< Enalbe/Disable off state in run mode */ + type_func_t off_idle; /**< Enalbe/Disable off state in idle mode */ + timer_lock_level_t lock_level; /**< Lock level */ + uint32_t dead_time; /**< Dead time, [0x0, 0xFF] */ + type_func_t break_state; /**< Break state */ + timer_break_polarity_t polarity; /**< Break input polarity */ + type_func_t auto_out; /**< Enalbe/Disable automatic output */ } timer_break_dead_time_t; /** * @brief TIMER commutation event channel configuretion structure definition */ -typedef struct -{ - type_func_t en; /**< Enalbe/Disable the channel */ - type_func_t n_en; /**< Enalbe/Disable the complementary channel */ - timer_oc_mode_t mode; /**< Mode of the channel */ +typedef struct { + type_func_t en; /**< Enalbe/Disable the channel */ + type_func_t n_en; /**< Enalbe/Disable the complementary channel */ + timer_oc_mode_t mode; /**< Mode of the channel */ } timer_channel_config_t; /** * @brief TIMER commutation event configuretion structure definition */ -typedef struct -{ - timer_channel_config_t ch[3]; /**< Configure of channel */ +typedef struct { + timer_channel_config_t ch[3]; /**< Configure of channel */ } timer_com_channel_config_t; /** * @brief TIMER master mode selection */ -typedef enum -{ - TIMER_TRGO_RESET = 0, /**< RESET */ - TIMER_TRGO_ENABLE = 1, /**< ENABLE */ - TIMER_TRGO_UPDATE = 2, /**< UPDATE */ - TIMER_TRGO_OC1 = 3, /**< OC1 */ - TIMER_TRGO_OC1REF = 4, /**< OC1REF */ - TIMER_TRGO_OC2REF = 5, /**< OC2REF */ - TIMER_TRGO_OC3REF = 6, /**< OC3REF */ - TIMER_TRGO_OC4REF = 7, /**< OC4REF */ +typedef enum { + TIMER_TRGO_RESET = 0U, /**< RESET */ + TIMER_TRGO_ENABLE = 1U, /**< ENABLE */ + TIMER_TRGO_UPDATE = 2U, /**< UPDATE */ + TIMER_TRGO_OC1 = 3U, /**< OC1 */ + TIMER_TRGO_OC1REF = 4U, /**< OC1REF */ + TIMER_TRGO_OC2REF = 5U, /**< OC2REF */ + TIMER_TRGO_OC3REF = 6U, /**< OC3REF */ + TIMER_TRGO_OC4REF = 7U, /**< OC4REF */ } timer_master_mode_sel_t; /** * @brief TIMER master configuretion structure definition */ -typedef struct -{ - timer_master_mode_sel_t sel; /**< Specifies the active edge of the input signal */ - type_func_t master_en; /**< Master/Slave mode selection */ +typedef struct { + timer_master_mode_sel_t sel; /**< Specifies the active edge of the input signal */ + type_func_t master_en; /**< Master/Slave mode selection */ } timer_master_config_t; /** * @brief Specifies the event source */ -typedef enum -{ - TIMER_SRC_UPDATE = (1U << 0), /**< Event source is update */ - TIMER_SRC_CC1 = (1U << 1), /**< Event source is channel1 */ - TIMER_SRC_CC2 = (1U << 2), /**< Event source is channel2 */ - TIMER_SRC_CC3 = (1U << 3), /**< Event source is channel3 */ - TIMER_SRC_CC4 = (1U << 4), /**< Event source is channel4 */ - TIMER_SRC_COM = (1U << 5), /**< Event source is compare */ - TIMER_SRC_TRIG = (1U << 6), /**< Event source is trigger */ - TIMER_SRC_BREAK = (1U << 7), /**< Event source is break */ +typedef enum { + TIMER_SRC_UPDATE = (1U << 0), /**< Event source is update */ + TIMER_SRC_CC1 = (1U << 1), /**< Event source is channel1 */ + TIMER_SRC_CC2 = (1U << 2), /**< Event source is channel2 */ + TIMER_SRC_CC3 = (1U << 3), /**< Event source is channel3 */ + TIMER_SRC_CC4 = (1U << 4), /**< Event source is channel4 */ + TIMER_SRC_COM = (1U << 5), /**< Event source is compare */ + TIMER_SRC_TRIG = (1U << 6), /**< Event source is trigger */ + TIMER_SRC_BREAK = (1U << 7), /**< Event source is break */ } timer_event_source_t; /** * @brief TIMER interrupt definition */ -typedef enum -{ - TIMER_IT_UPDATE = (1U << 0), /**< Update interrupt bit */ - TIMER_IT_CC1 = (1U << 1), /**< Channel1 interrupt bit */ - TIMER_IT_CC2 = (1U << 2), /**< Channel2 interrupt bit */ - TIMER_IT_CC3 = (1U << 3), /**< Channel3 interrupt bit */ - TIMER_IT_CC4 = (1U << 4), /**< Channel4 interrupt bit */ - TIMER_IT_COM = (1U << 5), /**< compare interrupt bit */ - TIMER_IT_TRIGGER = (1U << 6), /**< Trigger interrupt bit */ - TIMER_IT_BREAK = (1U << 7), /**< Break interrupt bit */ +typedef enum { + TIMER_IT_UPDATE = (1U << 0), /**< Update interrupt bit */ + TIMER_IT_CC1 = (1U << 1), /**< Channel1 interrupt bit */ + TIMER_IT_CC2 = (1U << 2), /**< Channel2 interrupt bit */ + TIMER_IT_CC3 = (1U << 3), /**< Channel3 interrupt bit */ + TIMER_IT_CC4 = (1U << 4), /**< Channel4 interrupt bit */ + TIMER_IT_COM = (1U << 5), /**< compare interrupt bit */ + TIMER_IT_TRIGGER = (1U << 6), /**< Trigger interrupt bit */ + TIMER_IT_BREAK = (1U << 7), /**< Break interrupt bit */ } timer_it_t; /** * @brief TIMER DMA request */ -typedef enum -{ - TIMER_DMA_UPDATE = (1U << 8), /**< DMA request from update */ - TIMER_DMA_CC1 = (1U << 9), /**< DMA request from channel1 */ - TIMER_DMA_CC2 = (1U << 10), /**< DMA request from channel2 */ - TIMER_DMA_CC3 = (1U << 11), /**< DMA request from channel3 */ - TIMER_DMA_CC4 = (1U << 12), /**< DMA request from channel4 */ - TIMER_DMA_COM = (1U << 13), /**< DMA request from compare */ - TIMER_DMA_TRIGGER = (1U << 14), /**< DMA request from trigger */ +typedef enum { + TIMER_DMA_UPDATE = (1U << 8), /**< DMA request from update */ + TIMER_DMA_CC1 = (1U << 9), /**< DMA request from channel1 */ + TIMER_DMA_CC2 = (1U << 10), /**< DMA request from channel2 */ + TIMER_DMA_CC3 = (1U << 11), /**< DMA request from channel3 */ + TIMER_DMA_CC4 = (1U << 12), /**< DMA request from channel4 */ + TIMER_DMA_COM = (1U << 13), /**< DMA request from compare */ + TIMER_DMA_TRIGGER = (1U << 14), /**< DMA request from trigger */ } timer_dma_req_t; /** * @brief TIMER flag definition */ -typedef enum -{ - TIMER_FLAG_UPDATE = (1U << 0), /**< Update interrupt flag */ - TIMER_FLAG_CC1 = (1U << 1), /**< Channel1 interrupt flag */ - TIMER_FLAG_CC2 = (1U << 2), /**< Channel2 interrupt flag */ - TIMER_FLAG_CC3 = (1U << 3), /**< Channel3 interrupt flag */ - TIMER_FLAG_CC4 = (1U << 4), /**< Channel4 interrupt flag */ - TIMER_FLAG_COM = (1U << 5), /**< Compare interrupt flag */ - TIMER_FLAG_TRIGGER = (1U << 6), /**< Trigger interrupt flag */ - TIMER_FLAG_BREAK = (1U << 7), /**< Break interrupt flag */ - TIMER_FLAG_CC1OF = (1U << 9), /**< Channel1 override state flag */ - TIMER_FLAG_CC2OF = (1U << 10), /**< Channel2 override state flag */ - TIMER_FLAG_CC3OF = (1U << 11), /**< Channel3 override state flag */ - TIMER_FLAG_CC4OF = (1U << 12), /**< Channel4 override state flag */ +typedef enum { + TIMER_FLAG_UPDATE = (1U << 0), /**< Update interrupt flag */ + TIMER_FLAG_CC1 = (1U << 1), /**< Channel1 interrupt flag */ + TIMER_FLAG_CC2 = (1U << 2), /**< Channel2 interrupt flag */ + TIMER_FLAG_CC3 = (1U << 3), /**< Channel3 interrupt flag */ + TIMER_FLAG_CC4 = (1U << 4), /**< Channel4 interrupt flag */ + TIMER_FLAG_COM = (1U << 5), /**< Compare interrupt flag */ + TIMER_FLAG_TRIGGER = (1U << 6), /**< Trigger interrupt flag */ + TIMER_FLAG_BREAK = (1U << 7), /**< Break interrupt flag */ + TIMER_FLAG_CC1OF = (1U << 9), /**< Channel1 override state flag */ + TIMER_FLAG_CC2OF = (1U << 10), /**< Channel2 override state flag */ + TIMER_FLAG_CC3OF = (1U << 11), /**< Channel3 override state flag */ + TIMER_FLAG_CC4OF = (1U << 12), /**< Channel4 override state flag */ } timer_flag_t; /** * @} @@ -591,11 +552,11 @@ typedef enum * @brief Disable the TIMER peripheral. */ #define TIMER_DISABLE(hperh) \ - do { \ - if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ - && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ - CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ - } while (0) +do { \ + if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ +} while (0) /** * @brief Disable the TIMER main output. @@ -603,21 +564,21 @@ typedef enum * all the CCx and CCxN channels have been disabled */ #define TIMER_MOE_DISABLE(hperh) \ - do { \ - if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ - && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ - CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ - } while (0) +do { \ + if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ +} while (0) /** * @brief Sets the TIMER autoreload register value on runtime without calling * another time any Init function. */ #define TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \ - do { \ - (handle)->perh->AR = (AUTORELOAD); \ - (handle)->init.period = (AUTORELOAD); \ - } while (0) +do { \ + (handle)->perh->AR = (AUTORELOAD); \ + (handle)->init.period = (AUTORELOAD); \ +} while (0) /** * @brief Gets the TIMER autoreload register value on runtime @@ -654,7 +615,7 @@ typedef enum * TIMER_CHANNEL_4 */ #define TIMER_CCx_ENABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ - (SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2)))))) +(SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2)))))) /** * @brief Disable channel @@ -666,7 +627,7 @@ typedef enum * TIMER_CHANNEL_4 */ #define TIMER_CCx_DISABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ - (CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2)))) +(CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2)))) /** * @brief Enable complementary channel @@ -706,55 +667,55 @@ typedef enum #define IS_ADTIMER_INSTANCE(x) ((x) == AD16C4T0) #define IS_TIMER_XOR_INSTANCE(x) (((x) == AD16C4T0) || ((x) == GP16C4T0)) #define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) #define IS_TIMER_CC2_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) + ((x) == GP16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) #define IS_TIMER_CC4_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C4T0)) + ((x) == GP16C4T0)) #define IS_TIMER_BREAK_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) #define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == AD16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == AD16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2)))) + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == AD16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2)))) #define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == AD16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) || \ - (((x) == GP16C2T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4)))) + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4)))) #define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == AD16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) #define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) #define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) #elif defined (ES32F033x) || defined (ES32F093x) @@ -770,128 +731,128 @@ typedef enum #define IS_ADTIMER_INSTANCE(x) ((x) == AD16C4T0) #define IS_TIMER_XOR_INSTANCE(x) (((x) == GP16C4T0) || ((x) == GP16C4T1)) #define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) #define IS_TIMER_CC2_INSTANCE(x) (((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1) || \ - ((x) == GP16C4T1)) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1) || \ + ((x) == GP16C4T1)) #define IS_TIMER_CC4_INSTANCE(x) (((x) == GP16C4T0) || \ - ((x) == GP16C4T1)) + ((x) == GP16C4T1)) #define IS_TIMER_BREAK_INSTANCE(x) (((x) == GP16C4T0)) #define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == GP16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C4T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2)))) + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2)))) #define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == GP16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) || \ - (((x) == GP16C2T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C4T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4)))) + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4)))) #define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) #define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) #define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) #endif #define IS_TIMER_COUNTER_MODE(x) (((x) == TIMER_CNT_MODE_UP) || \ - ((x) == TIMER_CNT_MODE_DOWN) || \ - ((x) == TIMER_CNT_MODE_CENTER1) || \ - ((x) == TIMER_CNT_MODE_CENTER2) || \ - ((x) == TIMER_CNT_MODE_CENTER3)) + ((x) == TIMER_CNT_MODE_DOWN) || \ + ((x) == TIMER_CNT_MODE_CENTER1) || \ + ((x) == TIMER_CNT_MODE_CENTER2) || \ + ((x) == TIMER_CNT_MODE_CENTER3)) #define IS_TIMER_CLOCK_DIVISION(x) (((x) == TIMER_CLOCK_DIV1) || \ - ((x) == TIMER_CLOCK_DIV2) || \ - ((x) == TIMER_CLOCK_DIV4)) + ((x) == TIMER_CLOCK_DIV2) || \ + ((x) == TIMER_CLOCK_DIV4)) #define IS_TIMER_PWM_MODE(x) (((x) == TIMER_OC_MODE_PWM1) || \ - ((x) == TIMER_OC_MODE_PWM2)) + ((x) == TIMER_OC_MODE_PWM2)) #define IS_TIMER_OC_MODE(x) (((x) == TIMER_OC_MODE_TIMERING) || \ - ((x) == TIMER_OC_MODE_ACTIVE) || \ - ((x) == TIMER_OC_MODE_INACTIVE) || \ - ((x) == TIMER_OC_MODE_TOGGLE) || \ - ((x) == TIMER_OC_MODE_FORCE_ACTIVE) || \ - ((x) == TIMER_OC_MODE_FORCE_INACTIVE) || \ - ((x) == TIMER_OC_MODE_PWM1) || \ - ((x) == TIMER_OC_MODE_PWM2)) + ((x) == TIMER_OC_MODE_ACTIVE) || \ + ((x) == TIMER_OC_MODE_INACTIVE) || \ + ((x) == TIMER_OC_MODE_TOGGLE) || \ + ((x) == TIMER_OC_MODE_FORCE_ACTIVE) || \ + ((x) == TIMER_OC_MODE_FORCE_INACTIVE) || \ + ((x) == TIMER_OC_MODE_PWM1) || \ + ((x) == TIMER_OC_MODE_PWM2)) #define IS_TIMER_OC_POLARITY(x) (((x) == TIMER_OC_POLARITY_HIGH) || \ - ((x) == TIMER_OC_POLARITY_LOW)) + ((x) == TIMER_OC_POLARITY_LOW)) #define IS_TIMER_OCN_POLARITY(x) (((x) == TIMER_OCN_POLARITY_HIGH) || \ - ((x) == TIMER_OCN_POLARITY_LOW)) + ((x) == TIMER_OCN_POLARITY_LOW)) #define IS_TIMER_OCIDLE_STATE(x) (((x) == TIMER_OC_IDLE_RESET) || \ - ((x) == TIMER_OC_IDLE_SET)) + ((x) == TIMER_OC_IDLE_SET)) #define IS_TIMER_OCNIDLE_STATE(x) (((x) == TIMER_OCN_IDLE_RESET) || \ - ((x) == TIMER_OCN_IDLE_SET)) + ((x) == TIMER_OCN_IDLE_SET)) #define IS_TIMER_CHANNELS(x) (((x) == TIMER_CHANNEL_1) || \ - ((x) == TIMER_CHANNEL_2) || \ - ((x) == TIMER_CHANNEL_3) || \ - ((x) == TIMER_CHANNEL_4) || \ - ((x) == TIMER_CHANNEL_ALL)) + ((x) == TIMER_CHANNEL_2) || \ + ((x) == TIMER_CHANNEL_3) || \ + ((x) == TIMER_CHANNEL_4) || \ + ((x) == TIMER_CHANNEL_ALL)) #define IS_TIMER_OP_MODE(x) (((x) == TIMER_OP_MODE_REPEAT) || \ - ((x) == TIMER_OP_MODE_SINGLE)) + ((x) == TIMER_OP_MODE_SINGLE)) #define IS_TIMER_OP_OUTPUT_CH(x) (((x) == TIMER_OP_OUTPUT_CHANNEL_1) || \ - ((x) == TIMER_OP_OUTPUT_CHANNEL_2)) + ((x) == TIMER_OP_OUTPUT_CHANNEL_2)) #define IS_TIMER_ENCODER_MODE(x) (((x) == TIMER_ENC_MODE_TI1) || \ - ((x) == TIMER_ENC_MODE_TI2) || \ - ((x) == TIMER_ENC_MODE_TI12)) + ((x) == TIMER_ENC_MODE_TI2) || \ + ((x) == TIMER_ENC_MODE_TI12)) #define IS_TIMER_IC_POLARITY(x) (((x) == TIMER_IC_POLARITY_RISE) || \ - ((x) == TIMER_IC_POLARITY_FALL)) + ((x) == TIMER_IC_POLARITY_FALL)) #define IS_TIMER_IC_SELECT(x) (((x) == TIMER_IC_SEL_DIRECT) || \ - ((x) == TIMER_IC_SEL_INDIRECT) || \ - ((x) == TIMER_IC_SEL_TRC)) + ((x) == TIMER_IC_SEL_INDIRECT) || \ + ((x) == TIMER_IC_SEL_TRC)) #define IS_TIMER_IC_PSC(x) (((x) == TIMER_IC_PSC_DIV1) || \ - ((x) == TIMER_IC_PSC_DIV2) || \ - ((x) == TIMER_IC_PSC_DIV4) || \ - ((x) == TIMER_IC_PSC_DIV8)) + ((x) == TIMER_IC_PSC_DIV2) || \ + ((x) == TIMER_IC_PSC_DIV4) || \ + ((x) == TIMER_IC_PSC_DIV8)) #define IS_TIMER_IC_FILTER(x) ((x) <= 0xF) #define IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF) #define IS_TIMER_CLEAR_INPUT_SOURCE(x) (((x) == TIMER_INPUT_NONE) || \ - ((x) == TIMER_INPUT_ETR)) + ((x) == TIMER_INPUT_ETR)) #define IS_TIMER_CLEAR_INPUT_POLARITY(x) (((x) == TIMER_POLARITY_NO_INV) || \ - ((x) == TIMER_POLARITY_INV)) + ((x) == TIMER_POLARITY_INV)) #define IS_TIMER_ETR_PSC(x) (((x) == TIMER_ETR_PSC_DIV1) || \ - ((x) == TIMER_ETR_PSC_DIV2) || \ - ((x) == TIMER_ETR_PSC_DIV4) || \ - ((x) == TIMER_ETR_PSC_DIV8)) + ((x) == TIMER_ETR_PSC_DIV2) || \ + ((x) == TIMER_ETR_PSC_DIV4) || \ + ((x) == TIMER_ETR_PSC_DIV8)) #define IS_TIMER_CLOCK_SOURCE(x) (((x) == TIMER_SRC_ETRMODE2) || \ - ((x) == TIMER_SRC_INTER) || \ - ((x) == TIMER_SRC_ITR0) || \ - ((x) == TIMER_SRC_ITR1) || \ - ((x) == TIMER_SRC_ITR2) || \ - ((x) == TIMER_SRC_ITR3) || \ - ((x) == TIMER_SRC_TI1ED) || \ - ((x) == TIMER_SRC_TI1) || \ - ((x) == TIMER_SRC_TI2) || \ - ((x) == TIMER_SRC_ETRMODE1)) + ((x) == TIMER_SRC_INTER) || \ + ((x) == TIMER_SRC_ITR0) || \ + ((x) == TIMER_SRC_ITR1) || \ + ((x) == TIMER_SRC_ITR2) || \ + ((x) == TIMER_SRC_ITR3) || \ + ((x) == TIMER_SRC_TI1ED) || \ + ((x) == TIMER_SRC_TI1) || \ + ((x) == TIMER_SRC_TI2) || \ + ((x) == TIMER_SRC_ETRMODE1)) #define IS_TIMER_CLOCK_POLARITY(x) (((x) == TIMER_CLK_POLARITY_INV) || \ - ((x) == TIMER_CLK_POLARITY_NO_INV) || \ - ((x) == TIMER_CLK_POLARITY_RISE) || \ - ((x) == TIMER_CLK_POLARITY_FALL) || \ - ((x) == TIMER_CLK_POLARITY_BOTH)) + ((x) == TIMER_CLK_POLARITY_NO_INV) || \ + ((x) == TIMER_CLK_POLARITY_RISE) || \ + ((x) == TIMER_CLK_POLARITY_FALL) || \ + ((x) == TIMER_CLK_POLARITY_BOTH)) #define IS_TIMER_SLAVE_MODE(x) (((x) == TIMER_MODE_DISABLE) || \ ((x) == TIMER_MODE_ENC1) || \ ((x) == TIMER_MODE_ENC2) || \ @@ -901,35 +862,35 @@ typedef enum ((x) == TIMER_MODE_TRIG) || \ ((x) == TIMER_MODE_EXTERNAL1)) #define IS_TIMER_EVENT_SOURCE(x) (((x) == TIMER_SRC_UPDATE) || \ - ((x) == TIMER_SRC_CC1) || \ - ((x) == TIMER_SRC_CC2) || \ - ((x) == TIMER_SRC_CC3) || \ - ((x) == TIMER_SRC_CC4) || \ - ((x) == TIMER_SRC_COM) || \ - ((x) == TIMER_SRC_TRIG) || \ - ((x) == TIMER_SRC_BREAK)) + ((x) == TIMER_SRC_CC1) || \ + ((x) == TIMER_SRC_CC2) || \ + ((x) == TIMER_SRC_CC3) || \ + ((x) == TIMER_SRC_CC4) || \ + ((x) == TIMER_SRC_COM) || \ + ((x) == TIMER_SRC_TRIG) || \ + ((x) == TIMER_SRC_BREAK)) #define IS_TIMER_TS(x) (((x) == TIMER_TS_ITR0) || \ - ((x) == TIMER_TS_ITR1) || \ - ((x) == TIMER_TS_ITR2) || \ - ((x) == TIMER_TS_ITR3) || \ - ((x) == TIMER_TS_TI1F_ED) || \ - ((x) == TIMER_TS_TI1FP1) || \ - ((x) == TIMER_TS_TI2FP2) || \ - ((x) == TIMER_TS_ETRF)) + ((x) == TIMER_TS_ITR1) || \ + ((x) == TIMER_TS_ITR2) || \ + ((x) == TIMER_TS_ITR3) || \ + ((x) == TIMER_TS_TI1F_ED) || \ + ((x) == TIMER_TS_TI1FP1) || \ + ((x) == TIMER_TS_TI2FP2) || \ + ((x) == TIMER_TS_ETRF)) #define IS_TIMER_CLOCK_LEVEL(x) (((x) == TIMER_LOCK_LEVEL_OFF) || \ ((x) == TIMER_LOCK_LEVEL_1) || \ ((x) == TIMER_LOCK_LEVEL_2) || \ ((x) == TIMER_LOCK_LEVEL_3)) #define IS_TIMER_BREAK_POLARITY(x) (((x) == TIMER_BREAK_POLARITY_LOW) || \ - ((x) == TIMER_BREAK_POLARITY_HIGH)) + ((x) == TIMER_BREAK_POLARITY_HIGH)) #define IS_TIMER_MASTER_MODE_SEL(x) (((x) == TIMER_TRGO_RESET) || \ - ((x) == TIMER_TRGO_ENABLE) || \ - ((x) == TIMER_TRGO_UPDATE) || \ - ((x) == TIMER_TRGO_OC1) || \ - ((x) == TIMER_TRGO_OC1REF) || \ - ((x) == TIMER_TRGO_OC2REF) || \ - ((x) == TIMER_TRGO_OC3REF) || \ - ((x) == TIMER_TRGO_OC4REF)) + ((x) == TIMER_TRGO_ENABLE) || \ + ((x) == TIMER_TRGO_UPDATE) || \ + ((x) == TIMER_TRGO_OC1) || \ + ((x) == TIMER_TRGO_OC1REF) || \ + ((x) == TIMER_TRGO_OC2REF) || \ + ((x) == TIMER_TRGO_OC3REF) || \ + ((x) == TIMER_TRGO_OC4REF)) #define IS_TIMER_IT(x) (((x) == TIMER_IT_UPDATE) || \ ((x) == TIMER_IT_CC1) || \ ((x) == TIMER_IT_CC2) || \ @@ -939,24 +900,24 @@ typedef enum ((x) == TIMER_IT_TRIGGER) || \ ((x) == TIMER_IT_BREAK)) #define IS_TIMER_DMA_REQ(x) (((x) == TIMER_DMA_UPDATE) || \ - ((x) == TIMER_DMA_CC1) || \ - ((x) == TIMER_DMA_CC2) || \ - ((x) == TIMER_DMA_CC3) || \ - ((x) == TIMER_DMA_CC4) || \ - ((x) == TIMER_DMA_COM) || \ - ((x) == TIMER_DMA_TRIGGER)) + ((x) == TIMER_DMA_CC1) || \ + ((x) == TIMER_DMA_CC2) || \ + ((x) == TIMER_DMA_CC3) || \ + ((x) == TIMER_DMA_CC4) || \ + ((x) == TIMER_DMA_COM) || \ + ((x) == TIMER_DMA_TRIGGER)) #define IS_TIMER_FLAG(x) (((x) == TIMER_FLAG_UPDATE) || \ - ((x) == TIMER_FLAG_CC1) || \ - ((x) == TIMER_FLAG_CC2) || \ - ((x) == TIMER_FLAG_CC3) || \ - ((x) == TIMER_FLAG_CC4) || \ - ((x) == TIMER_FLAG_COM) || \ - ((x) == TIMER_FLAG_TRIGGER) || \ - ((x) == TIMER_FLAG_BREAK) || \ - ((x) == TIMER_FLAG_CC1OF) || \ - ((x) == TIMER_FLAG_CC2OF) || \ - ((x) == TIMER_FLAG_CC3OF) || \ - ((x) == TIMER_FLAG_CC4OF)) + ((x) == TIMER_FLAG_CC1) || \ + ((x) == TIMER_FLAG_CC2) || \ + ((x) == TIMER_FLAG_CC3) || \ + ((x) == TIMER_FLAG_CC4) || \ + ((x) == TIMER_FLAG_COM) || \ + ((x) == TIMER_FLAG_TRIGGER) || \ + ((x) == TIMER_FLAG_BREAK) || \ + ((x) == TIMER_FLAG_CC1OF) || \ + ((x) == TIMER_FLAG_CC2OF) || \ + ((x) == TIMER_FLAG_CC3OF) || \ + ((x) == TIMER_FLAG_CC4OF)) /** * @} */ @@ -975,8 +936,8 @@ void ald_timer_base_stop(timer_handle_t *hperh); void ald_timer_base_start_by_it(timer_handle_t *hperh); void ald_timer_base_stop_by_it(timer_handle_t *hperh); #ifdef ALD_DMA -ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - uint16_t *buf, uint32_t len, uint8_t dma_ch); +ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_base_stop_by_dma(timer_handle_t *hperh); #endif /** @@ -994,7 +955,7 @@ void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); + uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1015,7 +976,7 @@ void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); + uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1033,7 +994,7 @@ void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); + uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1064,8 +1025,8 @@ void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, - uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2); + uint16_t *buf1, uint16_t *buf2, uint32_t len, + uint8_t dma_ch1, uint8_t dma_ch2); void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1082,8 +1043,8 @@ void ald_timer_hall_sensor_stop(timer_handle_t *hperh); void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh); void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh); #ifdef ALD_DMA -ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - uint16_t *buf, uint32_t len, uint8_t dma_ch); +ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh); #endif /** @@ -1099,8 +1060,8 @@ void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA -ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1116,8 +1077,8 @@ void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA -ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1140,10 +1101,10 @@ void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @{ */ /* Control functions */ -ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch); -ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch); +ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch); +ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch); ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, - timer_channel_t ch_out, timer_channel_t ch_in); + timer_channel_t ch_out, timer_channel_t ch_in); ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch); ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config); ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select); diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h index a1142838eb5fe1e247e0e5fea1e0fc93381d77ae..635cb1a90abfb3f21ad0f6ecc9b4e60ebda49a97 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h @@ -38,93 +38,85 @@ extern "C" { /** * @brief Data width */ -typedef enum -{ - TRNG_DSEL_1B = 0x0, /**< 1-bit */ - TRNG_DSEL_8B = 0x1, /**< 8-bit */ - TRNG_DSEL_16B = 0x2, /**< 16-bit */ - TRNG_DSEL_32B = 0x3, /**< 32-bit */ +typedef enum { + TRNG_DSEL_1B = 0x0U, /**< 1-bit */ + TRNG_DSEL_8B = 0x1U, /**< 8-bit */ + TRNG_DSEL_16B = 0x2U, /**< 16-bit */ + TRNG_DSEL_32B = 0x3U, /**< 32-bit */ } trng_data_width_t; /** * @brief seed type */ -typedef enum -{ - TRNG_SEED_TYPE_0 = 0x0, /**< Using 0 as seed */ - TRNG_SEED_TYPE_1 = 0x1, /**< Using 1 as seed */ - TRNG_SEED_TYPE_LAST = 0x2, /**< Using last seed */ - TRNG_SEED_TYPE_SEED = 0x3, /**< Using value of register */ +typedef enum { + TRNG_SEED_TYPE_0 = 0x0U, /**< Using 0 as seed */ + TRNG_SEED_TYPE_1 = 0x1U, /**< Using 1 as seed */ + TRNG_SEED_TYPE_LAST = 0x2U, /**< Using last seed */ + TRNG_SEED_TYPE_SEED = 0x3U, /**< Using value of register */ } trng_seed_type_t; /** * @brief TRNG init structure definition */ -typedef struct -{ - trng_data_width_t data_width; /**< The width of data */ - trng_seed_type_t seed_type; /**< The seed type */ - uint32_t seed; /**< The value of seed */ - uint16_t t_start; /**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */ - uint8_t adjc; /**< Adjust parameter */ - type_func_t posten; /**< Data back handle function */ +typedef struct { + trng_data_width_t data_width; /**< The width of data */ + trng_seed_type_t seed_type; /**< The seed type */ + uint32_t seed; /**< The value of seed */ + uint16_t t_start; /**< T(start) = T(trng) * 2 ^ (t_start + 1), T(start) > 1ms */ + uint8_t adjc; /**< Adjust parameter */ + type_func_t posten; /**< Data back handle function */ } trng_init_t; /** * @brief TRNG state structures definition */ -typedef enum -{ - TRNG_STATE_RESET = 0x0, /**< Peripheral is not initialized */ - TRNG_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - TRNG_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - TRNG_STATE_ERROR = 0x4, /**< Error */ +typedef enum { + TRNG_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ + TRNG_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + TRNG_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + TRNG_STATE_ERROR = 0x4U, /**< Error */ } trng_state_t; /** * @brief State type */ -typedef enum -{ - TRNG_STATUS_START = (1U << 0), /**< Start state */ - TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */ - TRNG_STATUS_SERR = (1U << 2), /**< Error state */ +typedef enum { + TRNG_STATUS_START = (1U << 0), /**< Start state */ + TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */ + TRNG_STATUS_SERR = (1U << 2), /**< Error state */ } trng_status_t; /** * @brief Interrupt type */ -typedef enum -{ - TRNG_IT_START = (1U << 0), /**< Start */ - TRNG_IT_DAVLD = (1U << 1), /**< Data valid */ - TRNG_IT_SERR = (1U << 2), /**< Error */ +typedef enum { + TRNG_IT_START = (1U << 0), /**< Start */ + TRNG_IT_DAVLD = (1U << 1), /**< Data valid */ + TRNG_IT_SERR = (1U << 2), /**< Error */ } trng_it_t; /** * @brief Interrupt flag type */ -typedef enum -{ - TRNG_IF_START = (1U << 0), /**< Start */ - TRNG_IF_DAVLD = (1U << 1), /**< Data valid */ - TRNG_IF_SERR = (1U << 2), /**< Error */ +typedef enum { + TRNG_IF_START = (1U << 0), /**< Start */ + TRNG_IF_DAVLD = (1U << 1), /**< Data valid */ + TRNG_IF_SERR = (1U << 2), /**< Error */ } trng_flag_t; /** * @brief TRNG Handle Structure definition */ -typedef struct trng_handle_s -{ - TRNG_TypeDef *perh; /**< Register base address */ - trng_init_t init; /**< TRNG required parameters */ - uint32_t data; /**< result data */ - lock_state_t lock; /**< Locking object */ - trng_state_t state; /**< TRNG operation state */ - - void (*trng_cplt_cbk)(struct trng_handle_s *arg); /**< Trng completed callback */ - void (*err_cplt_cbk)(struct trng_handle_s *arg); /**< Trng error callback */ - void (*init_cplt_cbk)(struct trng_handle_s *arg); /**< Trng init completed callback */ +typedef struct trng_handle_s { + TRNG_TypeDef *perh; /**< Register base address */ + trng_init_t init; /**< TRNG required parameters */ + uint32_t data; /**< result data */ + lock_state_t lock; /**< Locking object */ + trng_state_t state; /**< TRNG operation state */ + + void (*trng_cplt_cbk)(struct trng_handle_s *arg); /**< Trng completed callback */ + void (*err_cplt_cbk)(struct trng_handle_s *arg); /**< Trng error callback */ + void (*init_cplt_cbk)(struct trng_handle_s *arg); /**< Trng init completed callback */ } trng_handle_t; /** * @} @@ -154,15 +146,16 @@ typedef struct trng_handle_s ((x) == TRNG_SEED_TYPE_LAST) || \ ((x) == TRNG_SEED_TYPE_SEED)) #define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \ - ((x) == TRNG_STATUS_DAVLD) || \ - ((x) == TRNG_STATUS_SERR)) -#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \ - ((x) == TRNG_IT_DAVLD) || \ - ((x) == TRNG_IT_SERR)) -#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \ - ((x) == TRNG_IF_DAVLD) || \ - ((x) == TRNG_IF_SERR)) -#define IS_TRNG_ADJC(x) ((x) < 4) + ((x) == TRNG_STATUS_DAVLD) || \ + ((x) == TRNG_STATUS_SERR)) +#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \ + ((x) == TRNG_IT_DAVLD) || \ + ((x) == TRNG_IT_SERR)) +#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \ + ((x) == TRNG_IF_DAVLD) || \ + ((x) == TRNG_IF_SERR)) +#define IS_TRNG_ADJC(x) ((x) < 4) +#define IS_TRNG_T_START(x) ((x) < 8) /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h index 0f55db2a2981f546e323e3ff1d7417558b01ed50..410dcb7ff6b51d2a1a0cc0b8fa7bf5c6fb347245 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h @@ -35,74 +35,74 @@ extern "C" { /** @defgroup TSENSE_Public_Macros TSENSE Public Macros * @{ */ -#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0)) -#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669)) +#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U)) +#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U)) #define TSENSE_ENABLE() \ - do { \ - TSENSE_UNLOCK(); \ - SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ - TSENSE_LOCK(); \ - } while (0) +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_DISABLE() \ - do { \ - TSENSE_UNLOCK(); \ - CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ - TSENSE_LOCK(); \ - } while (0) +do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_REQ_ENABLE() \ - do { \ - TSENSE_UNLOCK(); \ - SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ - TSENSE_LOCK(); \ - } while (0) +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_REQ_DISABLE() \ - do { \ - TSENSE_UNLOCK(); \ - CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ - TSENSE_LOCK(); \ - } while (0) +do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_CTN_ENABLE() \ - do { \ - TSENSE_UNLOCK(); \ - SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ - TSENSE_LOCK(); \ - } while (0) +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_CTN_DISABLE() \ - do { \ - TSENSE_UNLOCK(); \ - CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ - TSENSE_LOCK(); \ - } while (0) +do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_RESET() \ - do { \ - TSENSE_UNLOCK(); \ - SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK); \ - TSENSE_LOCK(); \ - } while (0) +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_LTGR_WR(data) \ - do { \ - TSENSE_UNLOCK(); \ - WRITE_REG(TSENSE->LTGR, (data)); \ - TSENSE_LOCK(); \ - } while(0) +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->LTGR, (data)); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_HTGR_WR(data) \ - do { \ - TSENSE_UNLOCK(); \ - WRITE_REG(TSENSE->HTGR, (data)); \ - TSENSE_LOCK(); \ - } while(0) +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->HTGR, (data)); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_TBDR_WR(data) \ - do { \ - TSENSE_UNLOCK(); \ - WRITE_REG(TSENSE->TBDR, (data)); \ - TSENSE_LOCK(); \ - } while(0) +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->TBDR, (data)); \ + TSENSE_LOCK(); \ +} while (0) #define TSENSE_TCALBDR_WR(data) \ - do { \ - TSENSE_UNLOCK(); \ - WRITE_REG(TSENSE->TCALBDR, (data)); \ - TSENSE_LOCK(); \ - } while(0) +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->TCALBDR, (data)); \ + TSENSE_LOCK(); \ +} while (0) /** * @} */ @@ -113,50 +113,34 @@ extern "C" { /** * @brief Temperature update time */ -typedef enum -{ - TSENSE_UPDATE_CYCLE_3 = 0x3, /**< 3 Cycles */ - TSENSE_UPDATE_CYCLE_4 = 0x4, /**< 4 Cycles */ - TSENSE_UPDATE_CYCLE_5 = 0x5, /**< 5 Cycles */ - TSENSE_UPDATE_CYCLE_6 = 0x6, /**< 6 Cycles */ - TSENSE_UPDATE_CYCLE_7 = 0x7, /**< 7 Cycles */ +typedef enum { + TSENSE_UPDATE_CYCLE_3 = 0x3U, /**< 3 Cycles */ + TSENSE_UPDATE_CYCLE_4 = 0x4U, /**< 4 Cycles */ + TSENSE_UPDATE_CYCLE_5 = 0x5U, /**< 5 Cycles */ + TSENSE_UPDATE_CYCLE_6 = 0x6U, /**< 6 Cycles */ + TSENSE_UPDATE_CYCLE_7 = 0x7U, /**< 7 Cycles */ } tsense_update_cycle_t; /** * @brief Temperature output mode */ -typedef enum -{ - TSENSE_OUTPUT_MODE_200 = 0x0, /**< 200 cycles update one temperature */ - TSENSE_OUTPUT_MODE_400 = 0x1, /**< 400 cycles update one temperature */ - TSENSE_OUTPUT_MODE_800 = 0x2, /**< 800 cycles update one temperature */ - TSENSE_OUTPUT_MODE_1600 = 0x3, /**< 1600 cycles update one temperature */ - TSENSE_OUTPUT_MODE_3200 = 0x4, /**< 3200 cycles update one temperature */ +typedef enum { + TSENSE_OUTPUT_MODE_200 = 0x0U, /**< 200 cycles update one temperature */ + TSENSE_OUTPUT_MODE_400 = 0x1U, /**< 400 cycles update one temperature */ + TSENSE_OUTPUT_MODE_800 = 0x2U, /**< 800 cycles update one temperature */ + TSENSE_OUTPUT_MODE_1600 = 0x3U, /**< 1600 cycles update one temperature */ + TSENSE_OUTPUT_MODE_3200 = 0x4U, /**< 3200 cycles update one temperature */ } tsense_output_mode_t; /** * @brief Source select */ -typedef enum -{ - TSENSE_SOURCE_LOSC = 0x0, /**< LOSC */ - TSENSE_SOURCE_LRC = 0x1, /**< LRC */ - TSENSE_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ - TSENSE_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ +typedef enum { + TSENSE_SOURCE_LOSC = 0x0U, /**< LOSC */ + TSENSE_SOURCE_LRC = 0x1U, /**< LRC */ } tsense_source_sel_t; -/** - * @brief TSENSE init structure definition - */ -typedef struct -{ - tsense_update_cycle_t cycle; /**< Temperature update time */ - tsense_output_mode_t mode; /**< Temperature output mode */ - type_func_t ctn; /**< Continue mode */ - uint8_t psc; /**< Perscaler */ -} tsense_init_t; - /** * @brief Define callback function type */ @@ -169,20 +153,8 @@ typedef void (*tsense_cbk)(uint16_t value, ald_status_t status); * @defgroup TSENSE_Private_Macros TSENSE Private Macros * @{ */ -#define IS_TSENSE_UPDATE_CYCLE(x) (((x) == TSENSE_UPDATE_CYCLE_3) || \ - ((x) == TSENSE_UPDATE_CYCLE_4) || \ - ((x) == TSENSE_UPDATE_CYCLE_5) || \ - ((x) == TSENSE_UPDATE_CYCLE_6) || \ - ((x) == TSENSE_UPDATE_CYCLE_7)) -#define IS_TSENSE_OUTPUT_MODE(x) (((x) == TSENSE_OUTPUT_MODE_200) || \ - ((x) == TSENSE_OUTPUT_MODE_400) || \ - ((x) == TSENSE_OUTPUT_MODE_800) || \ - ((x) == TSENSE_OUTPUT_MODE_1600) || \ - ((x) == TSENSE_OUTPUT_MODE_3200)) -#define IS_TSENSE_SOURCE_SEL(x) (((x) == TSENSE_SOURCE_LOSC) || \ - ((x) == TSENSE_SOURCE_LRC) || \ - ((x) == TSENSE_SOURCE_HRC_DIV_1M ) || \ - ((x) == TSENSE_SOURCE_HOSC_DIV_1M)) +#define IS_TSENSE_SOURCE_SEL(x) (((x) == TSENSE_SOURCE_LOSC) || \ + ((x) == TSENSE_SOURCE_LRC)) /** * @} */ @@ -194,7 +166,7 @@ typedef void (*tsense_cbk)(uint16_t value, ald_status_t status); * @{ */ /* Initialization functions */ -extern void ald_tsense_init(tsense_init_t *init); +extern void ald_tsense_init(void); extern void ald_tsense_source_select(tsense_source_sel_t sel); /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h index 49cc24d9efb9d72fa7ce911da99613ccd353f702..10a351ca19371befb32b6e80701b564b5f343c10 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h @@ -74,233 +74,216 @@ extern "C" { /** * @brief UART word length */ -typedef enum -{ - UART_WORD_LENGTH_5B = 0x0, /**< 5-bits */ - UART_WORD_LENGTH_6B = 0x1, /**< 6-bits */ - UART_WORD_LENGTH_7B = 0x2, /**< 7-bits */ - UART_WORD_LENGTH_8B = 0x3, /**< 8-bits */ +typedef enum { + UART_WORD_LENGTH_5B = 0x0U, /**< 5-bits */ + UART_WORD_LENGTH_6B = 0x1U, /**< 6-bits */ + UART_WORD_LENGTH_7B = 0x2U, /**< 7-bits */ + UART_WORD_LENGTH_8B = 0x3U, /**< 8-bits */ } uart_word_length_t; /** * @brief UART stop bits */ -typedef enum -{ - UART_STOP_BITS_1 = 0x0, /**< 1-bits */ - UART_STOP_BITS_2 = 0x1, /**< 2-bits */ - UART_STOP_BITS_0_5 = 0x0, /**< 0.5-bits, using smartcard mode */ - UART_STOP_BITS_1_5 = 0x1, /**< 1.5-bits, using smartcard mode */ +typedef enum { + UART_STOP_BITS_1 = 0x0U, /**< 1-bits */ + UART_STOP_BITS_2 = 0x1U, /**< 2-bits */ + UART_STOP_BITS_0_5 = 0x0U, /**< 0.5-bits, using smartcard mode */ + UART_STOP_BITS_1_5 = 0x1U, /**< 1.5-bits, using smartcard mode */ } uart_stop_bits_t; /** * @brief UART parity */ -typedef enum -{ - UART_PARITY_NONE = 0x0, /**< Not parity */ - UART_PARITY_ODD = 0x1, /**< Odd parity */ - UART_PARITY_EVEN = 0x3, /**< Even parity */ +typedef enum { + UART_PARITY_NONE = 0x0U, /**< Not parity */ + UART_PARITY_ODD = 0x1U, /**< Odd parity */ + UART_PARITY_EVEN = 0x3U, /**< Even parity */ } uart_parity_t; /** * @brief UART mode */ -typedef enum -{ - UART_MODE_UART = 0x0, /**< UART */ - UART_MODE_LIN = 0x1, /**< LIN */ - UART_MODE_IrDA = 0x2, /**< IrDA */ - UART_MODE_RS485 = 0x3, /**< RS485 */ - UART_MODE_HDSEL = 0x4, /**< Single-wire half-duplex */ +typedef enum { + UART_MODE_UART = 0x0U, /**< UART */ + UART_MODE_LIN = 0x1U, /**< LIN */ + UART_MODE_IrDA = 0x2U, /**< IrDA */ + UART_MODE_RS485 = 0x3U, /**< RS485 */ + UART_MODE_HDSEL = 0x4U, /**< Single-wire half-duplex */ } uart_mode_t; /** * @brief UART hardware flow control */ -typedef enum -{ - UART_HW_FLOW_CTL_DISABLE = 0x0, /**< Auto-flow-control disable */ - UART_HW_FLOW_CTL_ENABLE = 0x1, /**< Auto-flow-control enable */ +typedef enum { + UART_HW_FLOW_CTL_DISABLE = 0x0U, /**< Auto-flow-control disable */ + UART_HW_FLOW_CTL_ENABLE = 0x1U, /**< Auto-flow-control enable */ } uart_hw_flow_ctl_t; /** * @brief ALD UART state */ -typedef enum -{ - UART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - UART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - UART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - UART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - UART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ - UART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ - UART_STATE_TIMEOUT = 0x03, /**< Timeout state */ - UART_STATE_ERROR = 0x04, /**< Error */ +typedef enum { + UART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + UART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + UART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + UART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ + UART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ + UART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */ + UART_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + UART_STATE_ERROR = 0x04U, /**< Error */ } uart_state_t; /** * @brief UART error codes */ -typedef enum -{ - UART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ - UART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ - UART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ - UART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ - UART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ - UART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +typedef enum { + UART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ + UART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ + UART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ + UART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ + UART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ + UART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ } uart_error_t; /** * @brief UART init structure definition */ -typedef struct -{ - uint32_t baud; /**< Specifies the uart communication baud rate */ - uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ - uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ - uart_parity_t parity; /**< Specifies the parity mode */ - uart_mode_t mode; /**< Specifies uart mode */ - uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ +typedef struct { + uint32_t baud; /**< Specifies the uart communication baud rate */ + uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ + uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ + uart_parity_t parity; /**< Specifies the parity mode */ + uart_mode_t mode; /**< Specifies uart mode */ + uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ } uart_init_t; /** * @brief UART handle structure definition */ -typedef struct uart_handle_s -{ - UART_TypeDef *perh; /**< UART registers base address */ - uart_init_t init; /**< UART communication parameters */ - uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */ - uint16_t tx_size; /**< UART Tx Transfer size */ - uint16_t tx_count; /**< UART Tx Transfer Counter */ - uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */ - uint16_t rx_size; /**< UART Rx Transfer size */ - uint16_t rx_count; /**< UART Rx Transfer Counter */ +typedef struct uart_handle_s { + UART_TypeDef *perh; /**< UART registers base address */ + uart_init_t init; /**< UART communication parameters */ + uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */ + uint16_t tx_size; /**< UART Tx Transfer size */ + uint16_t tx_count; /**< UART Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */ + uint16_t rx_size; /**< UART Rx Transfer size */ + uint16_t rx_count; /**< UART Rx Transfer Counter */ #ifdef ALD_DMA - dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */ - dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */ + dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */ + dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */ #endif - lock_state_t lock; /**< Locking object */ - uart_state_t state; /**< UART communication state */ - uart_error_t err_code; /**< UART Error code */ + lock_state_t lock; /**< Locking object */ + uart_state_t state; /**< UART communication state */ + uart_error_t err_code; /**< UART Error code */ - void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */ + void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */ } uart_handle_t; /** * @brief UART RS485 configure structure definition */ -typedef struct -{ - type_func_t normal; /**< Normal mode */ - type_func_t dir; /**< Auto-direction mode */ - type_func_t invert; /**< Address detection invert */ - uint8_t addr; /**< Address for compare */ +typedef struct { + type_func_t normal; /**< Normal mode */ + type_func_t dir; /**< Auto-direction mode */ + type_func_t invert; /**< Address detection invert */ + uint8_t addr; /**< Address for compare */ } uart_rs485_config_t; /** * @brief LIN detection break length */ -typedef enum -{ - LIN_BREAK_LEN_10B = 0x0, /**< 10-bit break */ - LIN_BREAK_LEN_11B = 0x1, /**< 11-bit break */ +typedef enum { + LIN_BREAK_LEN_10B = 0x0U, /**< 10-bit break */ + LIN_BREAK_LEN_11B = 0x1U, /**< 11-bit break */ } uart_lin_break_len_t; /** * @brief UART TXFIFO size */ -typedef enum -{ - UART_TXFIFO_EMPTY = 0x0, /**< Empty */ - UART_TXFIFO_2BYTE = 0x1, /**< 2-Bytes */ - UART_TXFIFO_4BYTE = 0x2, /**< 4-Bytes */ - UART_TXFIFO_8BYTE = 0x3, /**< 8-Bytes */ +typedef enum { + UART_TXFIFO_EMPTY = 0x0U, /**< Empty */ + UART_TXFIFO_2BYTE = 0x1U, /**< 2-Bytes */ + UART_TXFIFO_4BYTE = 0x2U, /**< 4-Bytes */ + UART_TXFIFO_8BYTE = 0x3U, /**< 8-Bytes */ } uart_txfifo_t; /** * @brief UART RXFIFO size */ -typedef enum -{ - UART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */ - UART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */ - UART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */ - UART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */ +typedef enum { + UART_RXFIFO_1BYTE = 0x0U, /**< 1-Byte */ + UART_RXFIFO_4BYTE = 0x1U, /**< 4-Bytes */ + UART_RXFIFO_8BYTE = 0x2U, /**< 8-Bytes */ + UART_RXFIFO_14BYTE = 0x3U, /**< 14-Bytes */ } uart_rxfifo_t; /** * @brief UART auto-baud mode */ -typedef enum -{ - UART_ABRMOD_1_TO_0 = 0x0, /**< Detect bit0:1, bit1:0 */ - UART_ABRMOD_1 = 0x1, /**< Detect bit0:1 */ - UART_ABRMOD_0_TO_1 = 0x2, /**< Detect bit0:0, bit1:1 */ +typedef enum { + UART_ABRMOD_1_TO_0 = 0x0U, /**< Detect bit0:1, bit1:0 */ + UART_ABRMOD_1 = 0x1U, /**< Detect bit0:1 */ + UART_ABRMOD_0_TO_1 = 0x2U, /**< Detect bit0:0, bit1:1 */ } uart_auto_baud_mode_t; /** * @brief UART status types */ -typedef enum -{ - UART_STATUS_DR = (1U << 0), /**< Data ready */ - UART_STATUS_OE = (1U << 1), /**< Overrun error */ - UART_STATUS_PE = (1U << 2), /**< Parity error */ - UART_STATUS_FE = (1U << 3), /**< Framing error */ - UART_STATUS_BI = (1U << 4), /**< Break interrupt */ - UART_STATUS_TBEM = (1U << 5), /**< Transmit buffer empty */ - UART_STATUS_TEM = (1U << 6), /**< Transmitter empty */ - UART_STATUS_RFE = (1U << 7), /**< Reveiver FIFO data error */ - UART_STATUS_BUSY = (1U << 8), /**< UART busy */ - UART_STATUS_TFNF = (1U << 9), /**< Transmit FIFO not full */ - UART_STATUS_TFEM = (1U << 10), /**< Transmit FIFO not empty */ - UART_STATUS_RFNE = (1U << 11), /**< Receive FIFO not empty */ - UART_STATUS_RFF = (1U << 12), /**< Receive FIFO full */ - UART_STATUS_DCTS = (1U << 14), /**< Delta clear to send */ - UART_STATUS_CTS = (1U << 15), /**< Clear to send */ +typedef enum { + UART_STATUS_DR = (1U << 0), /**< Data ready */ + UART_STATUS_OE = (1U << 1), /**< Overrun error */ + UART_STATUS_PE = (1U << 2), /**< Parity error */ + UART_STATUS_FE = (1U << 3), /**< Framing error */ + UART_STATUS_BI = (1U << 4), /**< Break interrupt */ + UART_STATUS_TBEM = (1U << 5), /**< Transmit buffer empty */ + UART_STATUS_TEM = (1U << 6), /**< Transmitter empty */ + UART_STATUS_RFE = (1U << 7), /**< Reveiver FIFO data error */ + UART_STATUS_BUSY = (1U << 8), /**< UART busy */ + UART_STATUS_TFNF = (1U << 9), /**< Transmit FIFO not full */ + UART_STATUS_TFEM = (1U << 10), /**< Transmit FIFO not empty */ + UART_STATUS_RFNE = (1U << 11), /**< Receive FIFO not empty */ + UART_STATUS_RFF = (1U << 12), /**< Receive FIFO full */ + UART_STATUS_DCTS = (1U << 14), /**< Delta clear to send */ + UART_STATUS_CTS = (1U << 15), /**< Clear to send */ } uart_status_t; /** * @brief UART interrupt types */ -typedef enum -{ - UART_IT_RXRD = (1U << 0), /**< Receive data available */ - UART_IT_TXS = (1U << 1), /**< Tx empty status */ - UART_IT_RXS = (1U << 2), /**< Rx line status */ - UART_IT_MDS = (1U << 3), /**< Modem status */ - UART_IT_RTO = (1U << 4), /**< Receiver timeout */ - UART_IT_BZ = (1U << 5), /**< Busy status */ - UART_IT_ABE = (1U << 6), /**< Auto-baud rate detection end */ - UART_IT_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ - UART_IT_LINBK = (1U << 8), /**< Lin break detection */ - UART_IT_TC = (1U << 9), /**< Transmission complete */ - UART_IT_EOB = (1U << 10), /**< End of block */ - UART_IT_CM = (1U << 11), /**< Character match */ +typedef enum { + UART_IT_RXRD = (1U << 0), /**< Receive data available */ + UART_IT_TXS = (1U << 1), /**< Tx empty status */ + UART_IT_RXS = (1U << 2), /**< Rx line status */ + UART_IT_MDS = (1U << 3), /**< Modem status */ + UART_IT_RTO = (1U << 4), /**< Receiver timeout */ + UART_IT_BZ = (1U << 5), /**< Busy status */ + UART_IT_ABE = (1U << 6), /**< Auto-baud rate detection end */ + UART_IT_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ + UART_IT_LINBK = (1U << 8), /**< Lin break detection */ + UART_IT_TC = (1U << 9), /**< Transmission complete */ + UART_IT_EOB = (1U << 10), /**< End of block */ + UART_IT_CM = (1U << 11), /**< Character match */ } uart_it_t; /** * @brief UART flags types */ -typedef enum -{ - UART_IF_RXRD = (1U << 0), /**< Receive data available */ - UART_IF_TXS = (1U << 1), /**< Tx empty status */ - UART_IF_RXS = (1U << 2), /**< Rx line status */ - UART_IF_MDS = (1U << 3), /**< Modem status */ - UART_IF_RTO = (1U << 4), /**< Receiver timeout */ - UART_IF_BZ = (1U << 5), /**< Busy status */ - UART_IF_ABE = (1U << 6), /**< Auto-baud rate detection end */ - UART_IF_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ - UART_IF_LINBK = (1U << 8), /**< Lin break detection */ - UART_IF_TC = (1U << 9), /**< Transmission complete */ - UART_IF_EOB = (1U << 10), /**< End of block */ - UART_IF_CM = (1U << 11), /**< Character match */ +typedef enum { + UART_IF_RXRD = (1U << 0), /**< Receive data available */ + UART_IF_TXS = (1U << 1), /**< Tx empty status */ + UART_IF_RXS = (1U << 2), /**< Rx line status */ + UART_IF_MDS = (1U << 3), /**< Modem status */ + UART_IF_RTO = (1U << 4), /**< Receiver timeout */ + UART_IF_BZ = (1U << 5), /**< Busy status */ + UART_IF_ABE = (1U << 6), /**< Auto-baud rate detection end */ + UART_IF_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ + UART_IF_LINBK = (1U << 8), /**< Lin break detection */ + UART_IF_TC = (1U << 9), /**< Transmission complete */ + UART_IF_EOB = (1U << 10), /**< End of block */ + UART_IF_CM = (1U << 11), /**< Character match */ } uart_flag_t; /** * @} @@ -318,22 +301,22 @@ typedef enum ((x) == UART_WORD_LENGTH_7B) || \ ((x) == UART_WORD_LENGTH_8B)) #define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \ - ((x) == UART_STOP_BITS_2) || \ - ((x) == UART_STOP_BITS_0_5) || \ - ((x) == UART_STOP_BITS_1_5)) + ((x) == UART_STOP_BITS_2) || \ + ((x) == UART_STOP_BITS_0_5) || \ + ((x) == UART_STOP_BITS_1_5)) #define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \ - ((x) == UART_PARITY_ODD) || \ - ((x) == UART_PARITY_EVEN)) + ((x) == UART_PARITY_ODD) || \ + ((x) == UART_PARITY_EVEN)) #define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \ - ((x) == UART_MODE_LIN) || \ - ((x) == UART_MODE_IrDA) || \ - ((x) == UART_MODE_RS485) || \ - ((x) == UART_MODE_HDSEL)) + ((x) == UART_MODE_LIN) || \ + ((x) == UART_MODE_IrDA) || \ + ((x) == UART_MODE_RS485) || \ + ((x) == UART_MODE_HDSEL)) #define IS_UART_HARDWARE_FLOW_CONTROL(x) \ - (((x) == UART_HW_FLOW_CTL_DISABLE) || \ - ((x) == UART_HW_FLOW_CTL_ENABLE)) + (((x) == UART_HW_FLOW_CTL_DISABLE) || \ + ((x) == UART_HW_FLOW_CTL_ENABLE)) #define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \ - ((x) == LIN_BREAK_LEN_11B)) + ((x) == LIN_BREAK_LEN_11B)) #define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \ ((x) == UART_TXFIFO_2BYTE) || \ ((x) == UART_TXFIFO_4BYTE) || \ @@ -343,47 +326,47 @@ typedef enum ((x) == UART_RXFIFO_8BYTE) || \ ((x) == UART_RXFIFO_14BYTE)) #define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \ - ((x) == UART_ABRMOD_1) || \ - ((x) == UART_ABRMOD_0_TO_1)) + ((x) == UART_ABRMOD_1) || \ + ((x) == UART_ABRMOD_0_TO_1)) #define IS_UART_STATUS(x) (((x) == UART_STATUS_DR) || \ - ((x) == UART_STATUS_OE) || \ - ((x) == UART_STATUS_PE) || \ - ((x) == UART_STATUS_FE) || \ - ((x) == UART_STATUS_BI) || \ - ((x) == UART_STATUS_TBEM) || \ - ((x) == UART_STATUS_TEM) || \ - ((x) == UART_STATUS_RFE) || \ - ((x) == UART_STATUS_BUSY) || \ - ((x) == UART_STATUS_TFNF) || \ - ((x) == UART_STATUS_TFEM) || \ - ((x) == UART_STATUS_RFNE) || \ - ((x) == UART_STATUS_RFF) || \ - ((x) == UART_STATUS_DCTS) || \ - ((x) == UART_STATUS_CTS)) + ((x) == UART_STATUS_OE) || \ + ((x) == UART_STATUS_PE) || \ + ((x) == UART_STATUS_FE) || \ + ((x) == UART_STATUS_BI) || \ + ((x) == UART_STATUS_TBEM) || \ + ((x) == UART_STATUS_TEM) || \ + ((x) == UART_STATUS_RFE) || \ + ((x) == UART_STATUS_BUSY) || \ + ((x) == UART_STATUS_TFNF) || \ + ((x) == UART_STATUS_TFEM) || \ + ((x) == UART_STATUS_RFNE) || \ + ((x) == UART_STATUS_RFF) || \ + ((x) == UART_STATUS_DCTS) || \ + ((x) == UART_STATUS_CTS)) #define IS_UART_IT(x) (((x) == UART_IT_RXRD) || \ - ((x) == UART_IT_TXS) || \ - ((x) == UART_IT_RXS) || \ - ((x) == UART_IT_MDS) || \ - ((x) == UART_IT_RTO) || \ - ((x) == UART_IT_BZ) || \ - ((x) == UART_IT_ABE) || \ - ((x) == UART_IT_ABTO) || \ - ((x) == UART_IT_LINBK) || \ - ((x) == UART_IT_TC) || \ - ((x) == UART_IT_EOB) || \ - ((x) == UART_IT_CM)) + ((x) == UART_IT_TXS) || \ + ((x) == UART_IT_RXS) || \ + ((x) == UART_IT_MDS) || \ + ((x) == UART_IT_RTO) || \ + ((x) == UART_IT_BZ) || \ + ((x) == UART_IT_ABE) || \ + ((x) == UART_IT_ABTO) || \ + ((x) == UART_IT_LINBK) || \ + ((x) == UART_IT_TC) || \ + ((x) == UART_IT_EOB) || \ + ((x) == UART_IT_CM)) #define IS_UART_IF(x) (((x) == UART_IF_RXRD) || \ - ((x) == UART_IF_TXS) || \ - ((x) == UART_IF_RXS) || \ - ((x) == UART_IF_MDS) || \ - ((x) == UART_IF_RTO) || \ - ((x) == UART_IF_BZ) || \ - ((x) == UART_IF_ABE) || \ - ((x) == UART_IF_ABTO) || \ - ((x) == UART_IF_LINBK) || \ - ((x) == UART_IF_TC) || \ - ((x) == UART_IF_EOB) || \ - ((x) == UART_IF_CM)) + ((x) == UART_IF_TXS) || \ + ((x) == UART_IF_RXS) || \ + ((x) == UART_IF_MDS) || \ + ((x) == UART_IF_RTO) || \ + ((x) == UART_IF_BZ) || \ + ((x) == UART_IF_ABE) || \ + ((x) == UART_IF_ABTO) || \ + ((x) == UART_IF_LINBK) || \ + ((x) == UART_IF_TC) || \ + ((x) == UART_IF_EOB) || \ + ((x) == UART_IF_CM)) #define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21)) #define IS_UART_DATA(x) ((x) <= 0x1FF) @@ -434,8 +417,8 @@ void ald_uart_irq_handler(uart_handle_t *hperh); /* Peripheral Control functions */ void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state); void ald_uart_dma_req_config(uart_handle_t *hperh, type_func_t state); -void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); -void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); +void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config); +void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config); void ald_uart_lin_send_break(uart_handle_t *hperh); void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len); void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode); diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h index 62214b2a089d43a973487d3bb104619895f7ce4d..4f30e2c2a4e49d847a1f3378a051e57ed93dc51c 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h @@ -18,7 +18,7 @@ #define __ALD_USART_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -40,174 +40,159 @@ extern "C" { /** * @brief usart_word_length */ -typedef enum -{ - USART_WORD_LENGTH_8B = 0x0, /**< Word length is 8-bits */ - USART_WORD_LENGTH_9B = 0x1, /**< Word length is 9-bits */ +typedef enum { + USART_WORD_LENGTH_8B = 0x0U, /**< Word length is 8-bits */ + USART_WORD_LENGTH_9B = 0x1U, /**< Word length is 9-bits */ } usart_word_length_t; /** * @brief usart_stop_bits */ -typedef enum -{ - USART_STOP_BITS_1 = 0x0, /**< Stop bits is 1-bits */ - USART_STOP_BITS_0_5 = 0x1, /**< Stop bits is 0.5-bits */ - USART_STOP_BITS_2 = 0x2, /**< Stop bits is 2-bits */ - USART_STOP_BITS_1_5 = 0x3, /**< Stop bits is 1.5-bits */ +typedef enum { + USART_STOP_BITS_1 = 0x0U, /**< Stop bits is 1-bits */ + USART_STOP_BITS_0_5 = 0x1U, /**< Stop bits is 0.5-bits */ + USART_STOP_BITS_2 = 0x2U, /**< Stop bits is 2-bits */ + USART_STOP_BITS_1_5 = 0x3U, /**< Stop bits is 1.5-bits */ } usart_stop_bits_t; /** * @brief usart_parity */ -typedef enum -{ - USART_PARITY_NONE = 0x0, /**< Not parity */ - USART_PARITY_EVEN = 0x2, /**< Even parity */ - USART_PARITY_ODD = 0x3, /**< Odd parity */ +typedef enum { + USART_PARITY_NONE = 0x0U, /**< Not parity */ + USART_PARITY_EVEN = 0x2U, /**< Even parity */ + USART_PARITY_ODD = 0x3U, /**< Odd parity */ } usart_parity_t; /** * @brief usart_mode */ -typedef enum -{ - USART_MODE_RX = 0x1, /**< TX mode */ - USART_MODE_TX = 0x2, /**< RX mode */ - USART_MODE_TX_RX = 0x3, /**< TX & RX mode */ +typedef enum { + USART_MODE_RX = 0x1U, /**< TX mode */ + USART_MODE_TX = 0x2U, /**< RX mode */ + USART_MODE_TX_RX = 0x3U, /**< TX & RX mode */ } usart_mode_t; /** * @brief usart_hardware_flow_control */ -typedef enum -{ - USART_HW_FLOW_CTL_NONE = 0x0, /**< Not flow control */ - USART_HW_FLOW_CTL_RTS = 0x1, /**< RTS flow control */ - USART_HW_FLOW_CTL_CTS = 0x2, /**< CTS flow control */ - USART_HW_FLOW_CTL_RTS_CTS = 0x3, /**< RTS & CTS flow control */ +typedef enum { + USART_HW_FLOW_CTL_NONE = 0x0U, /**< Not flow control */ + USART_HW_FLOW_CTL_RTS = 0x1U, /**< RTS flow control */ + USART_HW_FLOW_CTL_CTS = 0x2U, /**< CTS flow control */ + USART_HW_FLOW_CTL_RTS_CTS = 0x3U, /**< RTS & CTS flow control */ } usart_hw_flow_ctl_t; /** * @brief usart_clock */ -typedef enum -{ - USART_CLOCK_DISABLE = 0x0, /**< Disable clock output */ - USART_CLOCK_ENABLE = 0x1, /**< Enable clock output */ +typedef enum { + USART_CLOCK_DISABLE = 0x0U, /**< Disable clock output */ + USART_CLOCK_ENABLE = 0x1U, /**< Enable clock output */ } usart_clock_t; /** * @brief usart_clock_polarity */ -typedef enum -{ - USART_CPOL_LOW = 0x0, /**< Clock polarity low */ - USART_CPOL_HIGH = 0x1, /**< Clock polarity high */ +typedef enum { + USART_CPOL_LOW = 0x0U, /**< Clock polarity low */ + USART_CPOL_HIGH = 0x1U, /**< Clock polarity high */ } usart_cpol_t; /** * @brief usart_clock_phase */ -typedef enum -{ - USART_CPHA_1EDGE = 0x0, /**< Clock phase first edge */ - USART_CPHA_2EDGE = 0x1, /**< Clock phase second edge */ +typedef enum { + USART_CPHA_1EDGE = 0x0U, /**< Clock phase first edge */ + USART_CPHA_2EDGE = 0x1U, /**< Clock phase second edge */ } usart_cpha_t; /** * @brief usart_last_bit */ -typedef enum -{ - USART_LAST_BIT_DISABLE = 0x0, /**< Disable last bit clock output */ - USART_LAST_BIT_ENABLE = 0x1, /**< Enable last bit clock output */ +typedef enum { + USART_LAST_BIT_DISABLE = 0x0U, /**< Disable last bit clock output */ + USART_LAST_BIT_ENABLE = 0x1U, /**< Enable last bit clock output */ } usart_last_bit_t; /** * @brief usart state structures definition */ -typedef enum -{ - USART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - USART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - USART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - USART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - USART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ - USART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ - USART_STATE_TIMEOUT = 0x03, /**< Timeout state */ - USART_STATE_ERROR = 0x04, /**< Error */ +typedef enum { + USART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + USART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + USART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + USART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ + USART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ + USART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */ + USART_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + USART_STATE_ERROR = 0x04U, /**< Error */ } usart_state_t; /** * @brief usart error codes */ -typedef enum -{ - USART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ - USART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ - USART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ - USART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ - USART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ - USART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +typedef enum { + USART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ + USART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ + USART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ + USART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ + USART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ + USART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ } usart_error_t; /** * @brief usart init structure definition */ -typedef struct -{ - uint32_t baud; /**< This member configures the Usart communication baud rate. */ - usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ - usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ - usart_parity_t parity; /**< Specifies the parity mode. +typedef struct { + uint32_t baud; /**< This member configures the Usart communication baud rate. */ + usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ + usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ + usart_parity_t parity; /**< Specifies the parity mode. @note When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits). */ - usart_mode_t mode; /**< Specifies wether the Receive or Transmit mode is enabled or disabled. */ - usart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled. */ - type_func_t over_sampling; /**< Specifies whether the Over sampling 8 is enabled or disabled. */ + usart_mode_t mode; /**< Specifies wether the Receive or Transmit mode is enabled or disabled. */ + usart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled. */ } usart_init_t; /** * @brief USART handle structure definition */ -typedef struct usart_handle_s -{ - USART_TypeDef *perh; /**< USART registers base address */ - usart_init_t init; /**< USART communication parameters */ - uint8_t *tx_buf; /**< Pointer to USART Tx transfer buffer */ - uint16_t tx_size; /**< USART Tx transfer size */ - uint16_t tx_count; /**< USART Tx transfer counter */ - uint8_t *rx_buf; /**< Pointer to USART Rx transfer buffer */ - uint16_t rx_size; /**< USART Rx Transfer size */ - uint16_t rx_count; /**< USART Rx Transfer Counter */ +typedef struct usart_handle_s { + USART_TypeDef *perh; /**< USART registers base address */ + usart_init_t init; /**< USART communication parameters */ + uint8_t *tx_buf; /**< Pointer to USART Tx transfer buffer */ + uint16_t tx_size; /**< USART Tx transfer size */ + uint16_t tx_count; /**< USART Tx transfer counter */ + uint8_t *rx_buf; /**< Pointer to USART Rx transfer buffer */ + uint16_t rx_size; /**< USART Rx Transfer size */ + uint16_t rx_count; /**< USART Rx Transfer Counter */ #ifdef ALD_DMA - dma_handle_t hdmatx; /**< USART Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< USART Rx DMA handle parameters */ + dma_handle_t hdmatx; /**< USART Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< USART Rx DMA handle parameters */ #endif - lock_state_t lock; /**< Locking object */ - usart_state_t state; /**< USART communication state */ - uint32_t err_code; /**< USART error code */ - - void (*tx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct usart_handle_s *arg); /**< Rx completed callback */ - void (*tx_rx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx & Rx completed callback */ - void (*error_cbk)(struct usart_handle_s *arg); /**< error callback */ + lock_state_t lock; /**< Locking object */ + usart_state_t state; /**< USART communication state */ + uint32_t err_code; /**< USART error code */ + + void (*tx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct usart_handle_s *arg); /**< Rx completed callback */ + void (*tx_rx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx & Rx completed callback */ + void (*error_cbk)(struct usart_handle_s *arg); /**< error callback */ } usart_handle_t; /** * @brief USART clock init structure definition */ -typedef struct -{ - usart_clock_t clk; /**< Pecifies whether the USART clock is enable or disable. */ - usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ - usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made. */ - usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted +typedef struct { + usart_clock_t clk; /**< Pecifies whether the USART clock is enable or disable. */ + usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ + usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made. */ + usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. */ } usart_clock_init_t; @@ -215,61 +200,56 @@ typedef struct /** * @brief usart_dma_request */ -typedef enum -{ - USART_DMA_REQ_TX = (1U << 7), /**< TX dma bit */ - USART_DMA_REQ_RX = (1U << 6), /**< RX dma bit */ +typedef enum { + USART_DMA_REQ_TX = (1U << 7), /**< TX dma bit */ + USART_DMA_REQ_RX = (1U << 6), /**< RX dma bit */ } usart_dma_req_t; /** * @brief usart_wakeup_methods */ -typedef enum -{ - USART_WAKEUP_IDLE = 0x0, /**< Wake up the machine when bus-line is idle */ - USART_WAKEUP_ADDR = 0x1, /**< Wake up the machine when match the address */ +typedef enum { + USART_WAKEUP_IDLE = 0x0U, /**< Wake up the machine when bus-line is idle */ + USART_WAKEUP_ADDR = 0x1U, /**< Wake up the machine when match the address */ } usart_wakeup_t; /** * @brief usart_IrDA_low_power */ -typedef enum -{ - USART_IrDA_MODE_NORMAL = 0x0, /**< Normal IrDA mode */ - USART_IrDA_MODE_LOW_POWER = 0x1, /**< Low-power IrDA mode */ +typedef enum { + USART_IrDA_MODE_NORMAL = 0x0U, /**< Normal IrDA mode */ + USART_IrDA_MODE_LOW_POWER = 0x1U, /**< Low-power IrDA mode */ } usart_IrDA_mode_t; /** * @brief USART interrupts definition */ -typedef enum -{ - USART_IT_PE = ((1U << 8) | (1U << 16)), /**< Parity error */ - USART_IT_TXE = ((1U << 7) | (1U << 16)), /**< Tx empty */ - USART_IT_TC = ((1U << 6) | (1U << 16)), /**< Tx complete */ - USART_IT_RXNE = ((1U << 5) | (1U << 16)), /**< Rx not empty */ - USART_IT_IDLE = ((1U << 4) | (1U << 16)), /**< Idle */ - USART_IT_CTS = ((1U << 10) | (1U << 18)), /**< CTS */ - USART_IT_ERR = ((1U << 0) | (1U << 18)), /**< Error */ - USART_IT_ORE = (1U << 3), /**< Overrun error */ - USART_IT_NE = (1U << 2), /**< Noise error */ - USART_IT_FE = (1U << 0), /**< Frame error */ +typedef enum { + USART_IT_PE = ((1U << 8) | (1U << 16)), /**< Parity error */ + USART_IT_TXE = ((1U << 7) | (1U << 16)), /**< Tx empty */ + USART_IT_TC = ((1U << 6) | (1U << 16)), /**< Tx complete */ + USART_IT_RXNE = ((1U << 5) | (1U << 16)), /**< Rx not empty */ + USART_IT_IDLE = ((1U << 4) | (1U << 16)), /**< Idle */ + USART_IT_CTS = ((1U << 10)| (1U << 18)), /**< CTS */ + USART_IT_ERR = ((1U << 0) | (1U << 18)), /**< Error */ + USART_IT_ORE = (1U << 3), /**< Overrun error */ + USART_IT_NE = (1U << 2), /**< Noise error */ + USART_IT_FE = (1U << 0), /**< Frame error */ } usart_it_t; /** * @brief USART flags */ -typedef enum -{ - USART_FLAG_CTS = (1U << 9), /**< CTS */ - USART_FLAG_TXE = (1U << 7), /**< Tx empty */ - USART_FLAG_TC = (1U << 6), /**< Tx complete */ - USART_FLAG_RXNE = (1U << 5), /**< Rx not empty */ - USART_FLAG_IDLE = (1U << 4), /**< Idle */ - USART_FLAG_ORE = (1U << 3), /**< Overrun error */ - USART_FLAG_NE = (1U << 2), /**< Noise error */ - USART_FLAG_FE = (1U << 1), /**< Frame error */ - USART_FLAG_PE = (1U << 0), /**< Parity error */ +typedef enum { + USART_FLAG_CTS = (1U << 9), /**< CTS */ + USART_FLAG_TXE = (1U << 7), /**< Tx empty */ + USART_FLAG_TC = (1U << 6), /**< Tx complete */ + USART_FLAG_RXNE = (1U << 5), /**< Rx not empty */ + USART_FLAG_IDLE = (1U << 4), /**< Idle */ + USART_FLAG_ORE = (1U << 3), /**< Overrun error */ + USART_FLAG_NE = (1U << 2), /**< Noise error */ + USART_FLAG_FE = (1U << 1), /**< Frame error */ + USART_FLAG_PE = (1U << 0), /**< Parity error */ } usart_flag_t; /** @@ -293,12 +273,12 @@ typedef enum * @{ */ #define USART_CLEAR_PEFLAG(handle) \ - do { \ - __IO uint32_t tmpreg; \ - tmpreg = (handle)->perh->STAT; \ - tmpreg = (handle)->perh->DATA; \ - UNUSED(tmpreg); \ - } while (0) +do { \ + __IO uint32_t tmpreg; \ + tmpreg = (handle)->perh->STAT; \ + tmpreg = (handle)->perh->DATA; \ + UNUSED(tmpreg); \ +} while (0) /** * @} */ @@ -339,7 +319,7 @@ typedef enum * @{ */ #define USART_HWCONTROL_CTS_ENABLE(handle) \ - (SET_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) + (SET_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) /** * @} */ @@ -348,7 +328,7 @@ typedef enum * @{ */ #define USART_HWCONTROL_CTS_DISABLE(handle) \ - (CLEAR_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) + (CLEAR_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) /** * @} */ @@ -357,7 +337,7 @@ typedef enum * @{ */ #define USART_HWCONTROL_RTS_ENABLE(handle) \ - (SET_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) + (SET_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) /** * @} */ @@ -366,7 +346,7 @@ typedef enum * @{ */ #define USART_HWCONTROL_RTS_DISABLE(handle) \ - (CLEAR_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) + (CLEAR_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) /** * @} */ @@ -383,9 +363,9 @@ typedef enum * @{ */ #define USART_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) -/** - * @} - */ + /** + * @} + */ /** * @} @@ -406,13 +386,13 @@ typedef enum ((x) == USART_PARITY_EVEN) || \ ((x) == USART_PARITY_ODD)) #define IS_USART_MODE(x) (((x) == USART_MODE_RX) || \ - ((x) == USART_MODE_TX) || \ - ((x) == USART_MODE_TX_RX)) + ((x) == USART_MODE_TX) || \ + ((x) == USART_MODE_TX_RX)) #define IS_USART_HARDWARE_FLOW_CONTROL(x)\ - (((x) == USART_HW_FLOW_CTL_NONE) || \ - ((x) == USART_HW_FLOW_CTL_RTS) || \ - ((x) == USART_HW_FLOW_CTL_CTS) || \ - ((x) == USART_HW_FLOW_CTL_RTS_CTS)) + (((x) == USART_HW_FLOW_CTL_NONE) || \ + ((x) == USART_HW_FLOW_CTL_RTS) || \ + ((x) == USART_HW_FLOW_CTL_CTS) || \ + ((x) == USART_HW_FLOW_CTL_RTS_CTS)) #define IS_USART_CLOCK(x) (((x) == USART_CLOCK_DISABLE) || \ ((x) == USART_CLOCK_ENABLE)) #define IS_USART_CPOL(x) (((x) == USART_CPOL_LOW) || ((x) == USART_CPOL_HIGH)) @@ -436,7 +416,7 @@ typedef enum ((x) == USART_IT_NE) || ((x) == USART_IT_FE) || \ ((x) == USART_IT_ERR)) #define IS_USART_CLEAR_IT(x) (((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ - ((x) == USART_IT_CTS)) + ((x) == USART_IT_CTS)) #define IS_USART_FLAG(x) (((x) == USART_FLAG_PE) || ((x) == USART_FLAG_TXE) || \ ((x) == USART_FLAG_TC) || ((x) == USART_FLAG_RXNE) || \ @@ -450,8 +430,8 @@ typedef enum #define IS_USART_ADDRESS(x) ((x) <= 0xF) #define IS_USART_DATA(x) ((x) <= 0x1FF) #define DUMMY_DATA 0xFFFF -#define USART_STATE_TX_MASK (1 << 4) -#define USART_STATE_RX_MASK (1 << 5) +#define USART_STATE_TX_MASK (1U << 4) +#define USART_STATE_RX_MASK (1U << 5) /** * @} @@ -509,7 +489,7 @@ ald_status_t ald_usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_b ald_status_t ald_usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, - uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); + uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); #endif /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h index b2b0e2203ab5cbb3b988f6e8926a3ce60798090f..619f777324f9b9134f60cde25c2d7d6868cd724a 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h @@ -38,12 +38,11 @@ extern "C" { /** * @brief Wwdt no dog window */ -typedef enum -{ - WWDT_WIN_25 = 0x0, /**< No dog window size: 25% */ - WWDT_WIN_50 = 0x1, /**< No dog window size: 50% */ - WWDT_WIN_75 = 0x2, /**< No dog window size: 75% */ - WWDT_WIN_00 = 0x3, /**< No dog window size: 0% */ +typedef enum { + WWDT_WIN_25 = 0x0U, /**< No dog window size: 25% */ + WWDT_WIN_50 = 0x1U, /**< No dog window size: 50% */ + WWDT_WIN_75 = 0x2U, /**< No dog window size: 75% */ + WWDT_WIN_00 = 0x3U, /**< No dog window size: 0% */ } wwdt_win_t; /** @@ -54,10 +53,10 @@ typedef enum * @defgroup WDT_Private_Macros WDT Private Macros * @{ */ -#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551);} -#define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFF);} -#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551);} -#define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFF);} +#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);} +#define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);} +#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);} +#define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);} /** * @} @@ -72,7 +71,7 @@ typedef enum (x == WWDT_WIN_75) || \ (x == WWDT_WIN_00)) #define IS_FUNC_STATE(x) (((x) == DISABLE) || \ - ((x) == ENABLE)) + ((x) == ENABLE)) /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h index 7bf1c1e543558d14b5db019e1cbc96bfef772173..54082f3f2192d488c395ba7a0329c17b7dd66375 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h @@ -34,41 +34,36 @@ extern "C" { #define __isr__ -typedef enum -{ - RESET = 0x0, - SET = 0x1, +typedef enum { + RESET = 0x0U, + SET = 0x1U, } flag_status_t, it_status_t; -typedef enum -{ - BIT_RESET = 0x0, - BIT_SET = 0x1, +typedef enum { + BIT_RESET = 0x0U, + BIT_SET = 0x1U, } bit_status_t; -typedef enum -{ - DISABLE = 0x0, - ENABLE = 0x1, +typedef enum { + DISABLE = 0x0U, + ENABLE = 0x1U, } type_func_t; #define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) -typedef enum -{ - FALSE = 0x0, - TRUE = 0x1, +typedef enum { + FALSE = 0x0U, + TRUE = 0x1U, } type_bool_t; -typedef enum -{ - UNLOCK = 0x0, - LOCK = 0x1, +typedef enum { + UNLOCK = 0x0U, + LOCK = 0x1U, } lock_state_t; #define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) #define BIT(x) ((1U << (x))) -#define BITS(s, e) ((0xffffffff << (s)) & (0xffffffff >> (31 - (e)))) +#define BITS(s, e) ((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e)))) #define SET_BIT(reg, bit) ((reg) |= (bit)) #define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) #define READ_BIT(reg, bit) ((reg) & (bit)) @@ -77,18 +72,18 @@ typedef enum #define WRITE_REG(reg, val) ((reg) = (val)) #define READ_REG(reg) ((reg)) #define MODIFY_REG(reg, clearmask, setmask) \ - WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask))) + WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask))) #define UNUSED(x) ((void)(x)) #ifdef USE_ASSERT #define assert_param(x) \ - do { \ - if (!(x)) { \ - __disable_irq(); \ - while (1) \ - ; \ - } \ - } while (0) +do { \ + if (!(x)) { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ +} while (0) #else #define assert_param(x) #endif @@ -101,23 +96,23 @@ typedef enum __STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val) { - uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2); - *((volatile uint32_t *)tmp) = (uint32_t)val; + uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; } __STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val) { - uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2); - *((volatile uint32_t *)tmp) = (uint32_t)val; + uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; } #if defined ( __GNUC__ ) -#ifndef __weak -#define __weak __attribute__((weak)) -#endif /* __weak */ -#ifndef __packed -#define __packed __attribute__((__packed__)) -#endif /* __packed */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ #endif /* __GNUC__ */ #ifdef __cplusplus diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h index b9041cb62a6ef1903032be1ba0edd4325fd1efa4..5ad1dc36a779c48a938bcd8553e53819ad3af829 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h @@ -18,7 +18,7 @@ #define __UTILS_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include @@ -46,23 +46,21 @@ extern uint32_t __systick_interval; /** * @brief ALD Status structures definition */ -typedef enum -{ - OK = 0x0, - ERROR = 0x1, - BUSY = 0x2, - TIMEOUT = 0x3 +typedef enum { + OK = 0x0U, /**< Status: OK */ + ERROR = 0x1U, /**< Status: ERROR */ + BUSY = 0x2U, /**< Status: BUSY */ + TIMEOUT = 0x3U, /**< Status: TIMEOUT */ } ald_status_t; /** * @brief SysTick interval definition */ -typedef enum -{ - SYSTICK_INTERVAL_1MS = 1000, /**< Interval is 1ms */ - SYSTICK_INTERVAL_10MS = 100, /**< Interval is 10ms */ - SYSTICK_INTERVAL_100MS = 10, /**< Interval is 100ms */ - SYSTICK_INTERVAL_1000MS = 1, /**< Interval is 1s */ +typedef enum { + SYSTICK_INTERVAL_1MS = 1000U, /**< Interval is 1ms */ + SYSTICK_INTERVAL_10MS = 100U, /**< Interval is 10ms */ + SYSTICK_INTERVAL_100MS = 10U, /**< Interval is 100ms */ + SYSTICK_INTERVAL_1000MS = 1U, /**< Interval is 1s */ } systick_interval_t; /** * @} @@ -71,25 +69,24 @@ typedef enum /** @defgroup ALD_Public_Macros Public Macros * @{ */ -#define ALD_MAX_DELAY 0xFFFFFFFF - +#define ALD_MAX_DELAY 0xFFFFFFFFU #define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET) #define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET) #define RESET_HANDLE_STATE(x) ((x)->state = 0) #define __LOCK(x) \ - do { \ - if ((x)->lock == LOCK) { \ - return BUSY; \ - } \ - else { \ - (x)->lock = LOCK; \ - } \ - } while (0) + do { \ + if ((x)->lock == LOCK) { \ + return BUSY; \ + } \ + else { \ + (x)->lock = LOCK; \ + } \ + } while (0) #define __UNLOCK(x) \ - do { \ - (x)->lock = UNLOCK; \ - } while (0) + do { \ + (x)->lock = UNLOCK; \ + } while (0) /** * @} @@ -98,6 +95,10 @@ typedef enum /** @defgroup ALD_Private_Macros Private Macros * @{ */ +#define MCU_UID0_ADDR 0x000403E0U +#define MCU_UID1_ADDR 0x000403E8U +#define MCU_UID2_ADDR 0x000403F0U +#define MCU_CHIPID_ADDR 0x000403F8U #define IS_PRIO(x) ((x) < 4) #define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \ ((x) == SYSTICK_INTERVAL_10MS) || \ @@ -140,7 +141,8 @@ ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, ui void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status); uint32_t ald_mcu_get_tick(void); uint32_t ald_mcu_get_cpu_id(void); - +void ald_mcu_get_uid(uint8_t *buf); +uint32_t ald_mcu_get_chipid(void); /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c index 3057d7d2463cd952b6bc0ea6331f4a7d3341b2ef..e480de1697bdb336f7987c49e96ca296abfcb784 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c @@ -44,86 +44,82 @@ */ ald_status_t ald_acmp_init(acmp_handle_t *hperh) { - uint32_t tmp = 0; + uint32_t tmp = 0; - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - if (hperh->init.vdd_level > 63) - return ERROR; + if (hperh->init.vdd_level > 63) + return ERROR; - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode)); - assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time)); - assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel)); - assert_param(IS_ACMP_WARM_FUNC_TYPE(hperh->init.warm_func)); - assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.pos_port)); - assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.neg_port)); - assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval)); - assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode)); + assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time)); + assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel)); + assert_param(IS_ACMP_WARM_FUNC_TYPE(hperh->init.warm_func)); + assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.pos_port)); + assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.neg_port)); + assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval)); + assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge)); - __LOCK(hperh); + __LOCK(hperh); - tmp = hperh->perh->CON; + tmp = hperh->perh->CON; - tmp |= ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) | - (hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS)); + tmp |= ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) | + (hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS)); - hperh->perh->CON = tmp; + hperh->perh->CON = tmp; - tmp = hperh->perh->INPUTSEL; + tmp = hperh->perh->INPUTSEL; - tmp |= ((hperh->init.pos_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.neg_port << ACMP_INPUTSEL_NSEL_POSS) | - (hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS)); + tmp |= ((hperh->init.pos_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.neg_port << ACMP_INPUTSEL_NSEL_POSS) | + (hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS)); - hperh->perh->INPUTSEL = tmp; + hperh->perh->INPUTSEL = tmp; - if (hperh->init.warm_func == ACMP_WARM_DISABLE) - CLEAR_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK); - else - SET_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK); + if (hperh->init.warm_func == ACMP_WARM_DISABLE) + CLEAR_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK); + else + SET_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK); - switch (hperh->init.edge) - { - case ACMP_EDGE_NONE: - CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; + switch (hperh->init.edge) { + case ACMP_EDGE_NONE: + CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; - case ACMP_EDGE_FALL: - SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; + case ACMP_EDGE_FALL: + SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; - case ACMP_EDGE_RISE: - CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; + case ACMP_EDGE_RISE: + CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; - case ACMP_EDGE_ALL: - SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; + case ACMP_EDGE_ALL: + SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; - default: - break; - } + default: + break; + } - SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK); - tmp = 0; + tmp = 0; + while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) { + if (tmp++ >= 600000) { + __UNLOCK(hperh); + return ERROR; + } + } - while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) - { - if (tmp++ >= 600000) - { - __UNLOCK(hperh); - return ERROR; - } - } - - __UNLOCK(hperh); - return OK; + __UNLOCK(hperh); + return OK; } /** * @} @@ -147,20 +143,20 @@ ald_status_t ald_acmp_init(acmp_handle_t *hperh) */ ald_status_t ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state) { - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_IT_TYPE(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); - __LOCK(hperh); + __LOCK(hperh); - if (state) - hperh->perh->IES |= it; - else - hperh->perh->IEC |= it; + if (state) + hperh->perh->IES |= it; + else + hperh->perh->IEC |= it; - __UNLOCK(hperh); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -175,13 +171,13 @@ ald_status_t ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_ */ it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it) { - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_IT_TYPE(it)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_IT_TYPE(it)); - if (hperh->perh->IEV & it) - return SET; - else - return RESET; + if (hperh->perh->IEV & it) + return SET; + else + return RESET; } /** @@ -196,16 +192,15 @@ it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it) */ it_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) { - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_FLAG_TYPE(flag)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_FLAG_TYPE(flag)); - if (hperh->perh->RIF & flag) - { - __UNLOCK(hperh); - return SET; - } + if (hperh->perh->RIF & flag) { + __UNLOCK(hperh); + return SET; + } - return RESET; + return RESET; } /** @brief Clear the specified ACMP it flags. @@ -217,14 +212,14 @@ it_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) */ ald_status_t ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) { - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_FLAG_TYPE(flag)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_FLAG_TYPE(flag)); - __LOCK(hperh); - hperh->perh->IFC |= flag; - __UNLOCK(hperh); + __LOCK(hperh); + hperh->perh->IFC |= flag; + __UNLOCK(hperh); - return OK; + return OK; } /** @brief Set the specified acmp it flags. @@ -236,14 +231,14 @@ ald_status_t ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) */ ald_status_t acmp_set_it_mask(acmp_handle_t *hperh, acmp_it_t it) { - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_IT_TYPE(it)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_IT_TYPE(it)); - __LOCK(hperh); - hperh->perh->IFM |= it; - __UNLOCK(hperh); + __LOCK(hperh); + hperh->perh->IFM |= it; + __UNLOCK(hperh); - return OK; + return OK; } /** @brief Check whether the specified ACMP flag is set or not. @@ -257,16 +252,15 @@ ald_status_t acmp_set_it_mask(acmp_handle_t *hperh, acmp_it_t it) */ flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status) { - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_STATUS_TYPE(status)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_STATUS_TYPE(status)); - if (hperh->perh->STAT & status) - { - __UNLOCK(hperh); - return SET; - } + if (hperh->perh->STAT & status) { + __UNLOCK(hperh); + return SET; + } - return RESET; + return RESET; } /** * @} @@ -285,23 +279,19 @@ flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status) */ void ald_acmp_irq_handler(acmp_handle_t *hperh) { - if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_WARMUP) == SET)) - { - if (hperh->acmp_warmup_cplt_cbk) - hperh->acmp_warmup_cplt_cbk(hperh); - - ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP); - } - - if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_EDGE) == SET)) - { - if (hperh->acmp_edge_cplt_cbk) - hperh->acmp_edge_cplt_cbk(hperh); - - ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE); - } - - return; + if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_WARMUP) == SET)) { + if (hperh->acmp_warmup_cplt_cbk) + hperh->acmp_warmup_cplt_cbk(hperh); + ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP); + } + + if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_EDGE) == SET)) { + if (hperh->acmp_edge_cplt_cbk) + hperh->acmp_edge_cplt_cbk(hperh); + ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE); + } + + return; } /** @@ -314,22 +304,22 @@ void ald_acmp_irq_handler(acmp_handle_t *hperh) */ ald_status_t ald_acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config) { - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - if (config == NULL) - return ERROR; + if (config == NULL) + return ERROR; - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_INVERT_TYPE(config->gpio_inv)); - assert_param(IS_ACMP_OUT_FUNC_TYPE(config->out_func)); + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_INVERT_TYPE(config->gpio_inv)); + assert_param(IS_ACMP_OUT_FUNC_TYPE(config->out_func)); - __LOCK(hperh); - hperh->perh->CON |= (config->gpio_inv << ACMP_CON_OUTINV_POS); - hperh->perh->PORT = config->out_func; - __UNLOCK(hperh); + __LOCK(hperh); + hperh->perh->CON |= (config->gpio_inv << ACMP_CON_OUTINV_POS); + hperh->perh->PORT = config->out_func; + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -340,9 +330,9 @@ ald_status_t ald_acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *con */ uint8_t ald_acmp_out_result(acmp_handle_t *hperh) { - assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_TYPE(hperh->perh)); - return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS); + return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS); } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c index 2019e5a948a337a2a9e99769f0f66514bff45faa..7f1f522c7af9d8b201c399258e283d8a6606bd91 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c @@ -47,8 +47,8 @@ * @{ */ #ifdef ALD_DMA - static void adc_dma_normal_conv_cplt(void *arg); - static void adc_dma_error(void *arg); +static void adc_dma_normal_conv_cplt(void *arg); +static void adc_dma_error(void *arg); #endif /** * @} @@ -73,114 +73,96 @@ */ ald_status_t ald_adc_init(adc_handle_t *hperh) { - ald_status_t tmp_status = OK; - - if (hperh == NULL) - return ERROR; - - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.data_align)); - assert_param(IS_ADC_SCAN_MODE_TYPE(hperh->init.scan_mode)); - assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.clk_div)); - assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.neg_ref)); - assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.pos_ref)); - assert_param(IS_ADC_CONV_RES_TYPE(hperh->init.conv_res)); - assert_param(IS_ADC_NCH_LEN_TYPE(hperh->init.nch_len)); - assert_param(IS_ADC_DISC_MODE_TYPE(hperh->init.disc_mode)); - assert_param(IS_ADC_DISC_NBR_TYPE(hperh->init.disc_nbr)); - assert_param(IS_FUNC_STATE(hperh->init.cont_mode)); - assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_sel)); - - if (hperh->state == ADC_STATE_RESET) - { - hperh->error_code = ADC_ERROR_NONE; - hperh->lock = UNLOCK; - } - - if ((hperh->init.pos_ref == ADC_POS_REF_VDD) && (hperh->init.neg_ref == ADC_NEG_REF_VSS)) - { - ADC_ENABLE(hperh); - - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.neg_ref << ADC_CCR_VRNSEL_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.pos_ref << ADC_CCR_VRPSEL_POSS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, 1 << ADC_CCR_VCMBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, 1 << ADC_CCR_IREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, 1 << ADC_CCR_VREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, 6 << ADC_CCR_CKDIV_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, ADC_DATAALIGN_RIGHT << ADC_CON1_ALIGN_POS); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, ADC_CONV_RES_12 << ADC_CON0_RSEL_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, DISABLE << ADC_CON1_CM_POS); - MODIFY_REG(hperh->perh->NCHS1, ADC_NCHS1_NS1_MSK, ADC_CHANNEL_18 << ADC_NCHS1_NS1_POSS); - - hperh->perh->SMPT2 = 0x30; - - /* Start adc normal convert */ - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - - /* Wait convert finish */ - while (!READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK)); - - hperh->vdd_value = (hperh->perh->NCHDR & 0xfff); - - /* Get calibration VDD value */ - hperh->vdd_value = 2000 * 4096 / hperh->vdd_value; - } - - ADC_DISABLE(hperh); - ald_adc_reset(hperh); - hperh->state = ADC_STATE_BUSY_INTERNAL; - MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.data_align << ADC_CON1_ALIGN_POS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont_mode << ADC_CON1_CM_POS); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan_mode << ADC_CON0_SCANEN_POS); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.conv_res << ADC_CON0_RSEL_POSS); - - /* Enable discontinuous mode only if continuous mode is enabled */ - if (hperh->init.disc_mode == ADC_NCH_DISC_EN) - { - hperh->init.scan_mode = ENABLE; - SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nbr << ADC_CON0_ETRGN_POSS); - } - else if (hperh->init.disc_mode == ADC_ICH_DISC_EN) - { - hperh->init.scan_mode = ENABLE; - SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nbr << ADC_CON0_ETRGN_POSS); - } - else - { - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); - } - - if ((hperh->init.scan_mode == ENABLE) || (hperh->init.disc_mode == ADC_NCH_DISC_EN)) - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_len << ADC_CHSL_NSL_POSS); - - MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan_mode << ADC_CON0_SCANEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS); - /* if the ADC CLK less than 1MHZ,PWRMOD should be Enable*/ - MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.clk_div << ADC_CCR_CKDIV_POSS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.neg_ref << ADC_CCR_VRNSEL_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.pos_ref << ADC_CCR_VRPSEL_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS); - - if (tmp_status == OK) - { - hperh->error_code = ADC_ERROR_NONE; - hperh->state |= ADC_STATE_READY; - hperh->state &= ~(ADC_STATE_ERROR | ADC_STATE_NM_BUSY - | ADC_STATE_IST_BUSY | ADC_STATE_BUSY_INTERNAL); - } - - ald_adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE); - return tmp_status; + if (hperh == NULL) + return ERROR; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.align)); + assert_param(IS_FUNC_STATE(hperh->init.scan)); + assert_param(IS_ADC_NCH_NR_TYPE(hperh->init.nch_nr)); + assert_param(IS_ADC_DISC_MODE_TYPE(hperh->init.disc)); + assert_param(IS_ADC_DISC_NR_TYPE(hperh->init.disc_nr)); + assert_param(IS_ADC_CONV_BIT_TYPE(hperh->init.data_bit)); + assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.div)); + assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_sel)); + assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.n_ref)); + assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.p_ref)); + + if (hperh->state == ADC_STATE_RESET ) { + hperh->error_code = ADC_ERROR_NONE; + hperh->lock = UNLOCK; + } + + if ((hperh->init.p_ref == ADC_POS_REF_VDD) && (hperh->init.n_ref == ADC_NEG_REF_VSS)) { + ADC_ENABLE(hperh); + + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, 1 << ADC_CCR_VCMBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, 1 << ADC_CCR_IREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, 1 << ADC_CCR_VREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, 6 << ADC_CCR_CKDIV_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, ADC_DATAALIGN_RIGHT << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, ADC_CONV_BIT_12 << ADC_CON0_RSEL_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, DISABLE << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->NCHS1, ADC_NCHS1_NS1_MSK, ADC_CHANNEL_18 << ADC_NCHS1_NS1_POSS); + hperh->perh->SMPT2 = 0x30; + + /* Start adc normal convert */ + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + /* Wait convert finish */ + while (!READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK)); + hperh->vdd_value = (hperh->perh->NCHDR & 0xfff); + /* Get calibration VDD value */ + hperh->vdd_value = 2000 * 4096 / hperh->vdd_value; + } + + ADC_DISABLE(hperh); + ald_adc_reset(hperh); + hperh->state = ADC_STATE_BUSY; + MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.align << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.data_bit << ADC_CON0_RSEL_POSS); + + /* Enable discontinuous mode only if continuous mode is disable */ + if (hperh->init.disc == ADC_NCH_DISC_EN) { + hperh->init.scan = ENABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS); + } + else if (hperh->init.disc == ADC_ICH_DISC_EN) { + hperh->init.scan = ENABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS); + } + else { + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + } + + if ((hperh->init.scan == ENABLE) || (hperh->init.disc == ADC_NCH_DISC_EN)) + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_nr << ADC_CHSL_NSL_POSS); + + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.scan << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS); + /* if the ADC clock less than 1MHz,PWRMOD should be disable*/ + MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.div << ADC_CCR_CKDIV_POSS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS); + ald_adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE); + ADC_ENABLE(hperh); + + hperh->init.cont = DISABLE; + hperh->error_code = ADC_ERROR_NONE; + hperh->state = ADC_STATE_READY; + return OK; } /** @@ -192,41 +174,31 @@ ald_status_t ald_adc_init(adc_handle_t *hperh) */ ald_status_t ald_adc_reset(adc_handle_t *hperh) { - if (hperh == NULL) - return ERROR; - - assert_param(IS_ADC_TYPE(hperh->perh)); - - ADC_DISABLE(hperh); - - ald_adc_clear_flag_status(hperh, ADC_FLAG_AWD); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); - ald_adc_clear_flag_status(hperh, ADC_FLAG_OVR); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); - - WRITE_REG(hperh->perh->CON0, 0x0); - WRITE_REG(hperh->perh->CON1, 0x0); - WRITE_REG(hperh->perh->CCR, 0x0); - WRITE_REG(hperh->perh->WDTH, 0xFFF); - WRITE_REG(hperh->perh->WDTL, 0x0); - WRITE_REG(hperh->perh->ICHOFF[0], 0x0); - WRITE_REG(hperh->perh->ICHOFF[1], 0x0); - WRITE_REG(hperh->perh->ICHOFF[2], 0x0); - WRITE_REG(hperh->perh->ICHOFF[3], 0x0); - WRITE_REG(hperh->perh->ICHS, 0x0); - WRITE_REG(hperh->perh->NCHS1, 0x0); - WRITE_REG(hperh->perh->NCHS2, 0x0); - WRITE_REG(hperh->perh->NCHS3, 0x0); - WRITE_REG(hperh->perh->NCHS4, 0x0); - WRITE_REG(hperh->perh->SMPT1, 0x0); - WRITE_REG(hperh->perh->SMPT2, 0x0); - WRITE_REG(hperh->perh->CHSL, 0x0); - - hperh->state = ADC_STATE_RESET; - hperh->error_code = ADC_ERROR_NONE; - return OK; + assert_param(IS_ADC_TYPE(hperh->perh)); + + ADC_DISABLE(hperh); + WRITE_REG(hperh->perh->CLR, 0x30F); + WRITE_REG(hperh->perh->CON0, 0x0); + WRITE_REG(hperh->perh->CON1, 0x0); + WRITE_REG(hperh->perh->CCR, 0x0); + WRITE_REG(hperh->perh->WDTH, 0xFFF); + WRITE_REG(hperh->perh->WDTL, 0x0); + WRITE_REG(hperh->perh->ICHOFF[0], 0x0); + WRITE_REG(hperh->perh->ICHOFF[1], 0x0); + WRITE_REG(hperh->perh->ICHOFF[2], 0x0); + WRITE_REG(hperh->perh->ICHOFF[3], 0x0); + WRITE_REG(hperh->perh->ICHS, 0x0); + WRITE_REG(hperh->perh->NCHS1, 0x0); + WRITE_REG(hperh->perh->NCHS2, 0x0); + WRITE_REG(hperh->perh->NCHS3, 0x0); + WRITE_REG(hperh->perh->NCHS4, 0x0); + WRITE_REG(hperh->perh->SMPT1, 0x0); + WRITE_REG(hperh->perh->SMPT2, 0x0); + WRITE_REG(hperh->perh->CHSL, 0x0); + + hperh->state = ADC_STATE_RESET; + hperh->error_code = ADC_ERROR_NONE; + return OK; } /** * @} @@ -245,21 +217,13 @@ ald_status_t ald_adc_reset(adc_handle_t *hperh) */ ald_status_t ald_adc_normal_start(adc_handle_t *hperh) { - if (hperh == NULL) - return ERROR; + assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_TYPE(hperh->perh)); + ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - __LOCK(hperh); - ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); - hperh->state |= ADC_STATE_NM_BUSY; - __UNLOCK(hperh); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - - return OK; + return OK; } /** @@ -274,16 +238,11 @@ ald_status_t ald_adc_normal_start(adc_handle_t *hperh) */ ald_status_t ald_adc_normal_stop(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); - - __LOCK(hperh); - - ADC_DISABLE(hperh); - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_NM_EOC); - hperh->state |= ADC_STATE_READY; + assert_param(IS_ADC_TYPE(hperh->perh)); - __UNLOCK(hperh); - return OK; + ADC_DISABLE(hperh); + hperh->state = ADC_STATE_READY; + return OK; } /** @@ -300,39 +259,22 @@ ald_status_t ald_adc_normal_stop(adc_handle_t *hperh) */ ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = 0; - - assert_param(IS_ADC_TYPE(hperh->perh)); - - tickstart = ald_get_tick(); - - while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) - { - if (timeout != ALD_MAX_DELAY) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->state |= ADC_STATE_TIMEOUT; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - - hperh->state |= ADC_STATE_NM_EOC; - - if ((hperh->init.cont_mode == DISABLE) && (hperh->init.scan_mode == DISABLE)) - { - hperh->state &= ~ADC_STATE_NM_BUSY; - - if ((hperh->state & ADC_STATE_IST_BUSY) == 0) - hperh->state |= ADC_STATE_READY; - } - - return OK; + uint32_t _tick; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + _tick = ald_get_tick(); + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) { + if (timeout != ALD_MAX_DELAY ) { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { + hperh->state = ADC_STATE_TIMEOUT; + return TIMEOUT; + } + } + } + + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCHS | ADC_FLAG_NCH); + return OK; } /** @@ -347,28 +289,24 @@ ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t ti */ ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout) { - uint32_t tickstart = 0; - - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_EVENT_TYPE(event_type)); - - tickstart = ald_get_tick(); - - while (ald_adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) - { - if (timeout != ALD_MAX_DELAY) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->state |= ADC_STATE_TIMEOUT; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - - hperh->state |= ADC_STATE_AWD; - return OK; + uint32_t _tick; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_EVENT_TYPE(event_type)); + + _tick = ald_get_tick(); + while (ald_adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) { + if (timeout != ALD_MAX_DELAY ) { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { + hperh->state = ADC_STATE_TIMEOUT; + return TIMEOUT; + } + } + } + + + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_WDG); + return OK; } /** @@ -382,27 +320,15 @@ ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_ */ ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); - - __LOCK(hperh); - ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); - hperh->state |= ADC_STATE_NM_BUSY; - hperh->error_code = ADC_ERROR_NONE; - - if (READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)) - { - hperh->state &= ~(ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_IST_BUSY; - } - - __UNLOCK(hperh); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - ald_adc_interrupt_config(hperh, ADC_IT_NCH, ENABLE); + assert_param(IS_ADC_TYPE(hperh->perh)); - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + SET_BIT(hperh->state, ADC_STATE_BUSY_N); + ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH); + ald_adc_interrupt_config(hperh, ADC_IT_NCH, ENABLE); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - return OK; + return OK; } /** @@ -415,16 +341,13 @@ ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh) */ ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_TYPE(hperh->perh)); - __LOCK(hperh); - ADC_DISABLE(hperh); - ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); - hperh->state |= ADC_STATE_READY; - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); + ADC_DISABLE(hperh); + ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); - __UNLOCK(hperh); - return OK; + return OK; } #ifdef ALD_DMA @@ -440,58 +363,36 @@ ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh) */ ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) { - if ((hperh == NULL) || (buf == NULL) || (size == 0) || (channel > 5)) - return ERROR; - - assert_param(IS_ADC_TYPE(hperh->perh)); - - __LOCK(hperh); - ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); - hperh->state |= ADC_STATE_NM_BUSY; - - if (READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)) - { - hperh->state &= ~(ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_IST_BUSY; - } - - if ((hperh->state & ADC_STATE_IST_BUSY) != 0) - { - hperh->state &= ~(ADC_STATE_ERROR); - hperh->error_code &= ~(ADC_ERROR_OVR | ADC_ERROR_DMA); - } - else - { - hperh->state &= ~(ADC_STATE_ERROR); - hperh->error_code = ADC_ERROR_NONE; - } - - __UNLOCK(hperh); - - if (hperh->hdma.perh == NULL) - hperh->hdma.perh = DMA0; - - hperh->hdma.cplt_cbk = adc_dma_normal_conv_cplt; - hperh->hdma.cplt_arg = hperh; - hperh->hdma.err_cbk = adc_dma_error; - hperh->hdma.err_arg = hperh; - - ald_dma_config_struct(&hperh->hdma.config); - hperh->hdma.config.src = (void *)&hperh->perh->NCHDR; - hperh->hdma.config.dst = (void *)buf; - hperh->hdma.config.size = size; - hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma.config.msel = DMA_MSEL_ADC0; - hperh->hdma.config.msigsel = DMA_MSIGSEL_ADC; - hperh->hdma.config.channel = channel; - ald_dma_config_basic(&hperh->hdma); - - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - - return OK; + if ((buf == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + SET_BIT(hperh->state, ADC_STATE_BUSY_N); + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_cbk = adc_dma_normal_conv_cplt; + hperh->hdma.cplt_arg = hperh; + hperh->hdma.err_cbk = adc_dma_error; + hperh->hdma.err_arg = hperh; + + ald_dma_config_struct(&hperh->hdma.config); + hperh->hdma.config.src = (void *)&hperh->perh->NCHDR; + hperh->hdma.config.dst = (void *)buf; + hperh->hdma.config.size = size; + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.msel = DMA_MSEL_ADC0; + hperh->hdma.config.msigsel = DMA_MSIGSEL_ADC; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&hperh->hdma); + + ADC_ENABLE(hperh); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + return OK; } /** @@ -500,20 +401,17 @@ ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t s * ADC peripheral. * @param hperh: Pointer to a adc_handle_t structure that contains * the configuration information for the specified ADC module. + * @param channel: The DMA channel. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_stop_dma(adc_handle_t *hperh) +ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel) { - assert_param(IS_ADC_TYPE(hperh->perh)); - __LOCK(hperh); + assert_param(IS_ADC_TYPE(hperh->perh)); - ADC_DISABLE(hperh); - ald_pis_destroy(&hperh->hpis); - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); - hperh->state |= ADC_STATE_READY; - - __UNLOCK(hperh); - return OK; + ADC_DISABLE(hperh); + ald_dma_channel_config(hperh->hdma.perh, channel, DISABLE); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); + return OK; } /** @@ -523,19 +421,19 @@ ald_status_t adc_stop_dma(adc_handle_t *hperh) */ static void adc_dma_timer_trigger_cplt(void *arg) { - adc_timer_config_t *hperh = (adc_timer_config_t *)arg; - - ADC_DISABLE(&hperh->lh_adc); - ald_timer_base_stop(&hperh->lh_timer); + adc_timer_config_t *hperh = (adc_timer_config_t *)arg; - __UNLOCK(hperh); + ald_timer_base_stop(&hperh->h_timer); + ADC_DISABLE(&hperh->h_adc); + ald_dma_channel_config(hperh->h_dma.perh, hperh->dma_ch, DISABLE); + CLEAR_BIT(hperh->h_adc.state, ADC_STATE_BUSY_N); - if (hperh->lh_adc.adc_reg_cplt_cbk != NULL) - hperh->lh_adc.adc_reg_cplt_cbk(&hperh->lh_adc); + if (hperh->h_adc.normal_cplt_cbk) + hperh->h_adc.normal_cplt_cbk(&hperh->h_adc); + return; } - /** * @brief Config Timer trigger adc function * @param config: Pointer to a adc_timer_config_t structure that @@ -544,98 +442,90 @@ static void adc_dma_timer_trigger_cplt(void *arg) */ ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) { - __LOCK(config); - - config->lh_pis.perh = PIS; - config->lh_pis.init.producer_clk = PIS_CLK_PCLK1; - config->lh_pis.init.producer_edge = PIS_EDGE_NONE; - config->lh_pis.init.consumer_clk = PIS_CLK_PCLK2; - -#if defined (ES32F065x) - - if (config->p_timer == AD16C4T0) - config->lh_pis.init.producer_src = PIS_TIMER0_UPDATA; - -#elif defined(ES32F033x) || defined (ES32F093x) - - if (config->p_timer == GP16C4T0) - config->lh_pis.init.producer_src = PIS_TIMER0_UPDATA; - -#endif - - else if (config->p_timer == BS16T0) - config->lh_pis.init.producer_src = PIS_TIMER1_UPDATA; - else if (config->p_timer == GP16C2T0) - config->lh_pis.init.producer_src = PIS_TIMER2_UPDATA; - else if (config->p_timer == GP16C2T1) - config->lh_pis.init.producer_src = PIS_TIMER3_UPDATA; - else - return ERROR; - - if (config->p_adc == ADC0) - config->lh_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL; - else if (config->p_adc == ADC1) - config->lh_pis.init.consumer_trig = PIS_CH0_ADC1_NORMAL; - else - return ERROR; - - ald_pis_create(&config->lh_pis); - - /* Initialize TIMER0 */ - config->lh_timer.perh = config->p_timer; - config->lh_timer.init.prescaler = 0; - config->lh_timer.init.mode = TIMER_CNT_MODE_UP; - config->lh_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time); - config->lh_timer.init.clk_div = TIMER_CLOCK_DIV1; - config->lh_timer.init.re_cnt = 0; - ald_timer_base_init(&config->lh_timer); - - config->lh_adc.perh = config->p_adc; - config->lh_adc.init.data_align = ADC_DATAALIGN_RIGHT; - config->lh_adc.init.scan_mode = DISABLE; - config->lh_adc.init.cont_mode = DISABLE; - config->lh_adc.init.nch_len = ADC_NCH_LEN_1; - config->lh_adc.init.disc_mode = ADC_ALL_DISABLE; - config->lh_adc.init.disc_nbr = ADC_DISC_NBR_1; - config->lh_adc.init.conv_res = ADC_CONV_RES_12; - config->lh_adc.init.clk_div = ADC_CKDIV_16; - config->lh_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE; - config->lh_adc.init.neg_ref = config->n_ref; - config->lh_adc.init.pos_ref = config->p_ref; - config->lh_adc.adc_reg_cplt_cbk = config->adc_cplt_cbk; - config->lh_adc.adc_inj_cplt_cbk = NULL; - config->lh_adc.adc_out_of_win_cbk = NULL; - config->lh_adc.adc_error_cbk = NULL; - config->lh_adc.adc_ovr_cbk = NULL; - ald_adc_init(&config->lh_adc); - - config->lnm_config.channel = config->adc_ch; - config->lnm_config.rank = ADC_NCH_RANK_1; - config->lnm_config.samp_time = ADC_SAMPLETIME_1; - ald_adc_normal_channel_config(&config->lh_adc, &config->lnm_config); - - config->lh_dma.cplt_cbk = adc_dma_timer_trigger_cplt; - config->lh_dma.cplt_arg = config; - config->lh_dma.err_cbk = adc_dma_error; - config->lh_dma.err_arg = &config->lh_adc; - - ald_dma_config_struct(&config->lh_dma.config); - config->lh_dma.perh = DMA0; - config->lh_dma.config.src = (void *)&config->lh_adc.perh->NCHDR; - config->lh_dma.config.dst = (void *)config->buf; - config->lh_dma.config.size = config->size; - config->lh_dma.config.data_width = DMA_DATA_SIZE_HALFWORD; - config->lh_dma.config.src_inc = DMA_DATA_INC_NONE; - config->lh_dma.config.dst_inc = DMA_DATA_INC_HALFWORD; - config->lh_dma.config.msel = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1; - config->lh_dma.config.msigsel = DMA_MSIGSEL_ADC; - config->lh_dma.config.channel = config->dma_ch; - ald_dma_config_basic(&config->lh_dma); - - ADC_ENABLE(&config->lh_adc); - ald_timer_base_start(&config->lh_timer); - - return OK; + SET_BIT(config->h_adc.state, ADC_STATE_BUSY_N); + + config->h_pis.perh = PIS; + config->h_pis.init.producer_clk = PIS_CLK_PCLK1; + config->h_pis.init.producer_edge = PIS_EDGE_NONE; + config->h_pis.init.consumer_clk = PIS_CLK_PCLK2; + + #if defined (ES32F065x) + if (config->p_timer == AD16C4T0) + config->h_pis.init.producer_src = PIS_TIMER0_UPDATA; + #elif defined(ES32F033x) || defined (ES32F093x) + if (config->p_timer == GP16C4T0) + config->h_pis.init.producer_src = PIS_TIMER0_UPDATA; + #endif + else if (config->p_timer == BS16T0) + config->h_pis.init.producer_src = PIS_TIMER1_UPDATA; + else if (config->p_timer == GP16C2T0) + config->h_pis.init.producer_src = PIS_TIMER2_UPDATA; + else if (config->p_timer == GP16C2T1) + config->h_pis.init.producer_src = PIS_TIMER3_UPDATA; + else + return ERROR; + + if (config->p_adc == ADC0) + config->h_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL; + else + return ERROR; + + ald_pis_create(&config->h_pis); + + /* Initialize TIMER0 */ + config->h_timer.perh = config->p_timer; + config->h_timer.init.prescaler = 0; + config->h_timer.init.mode = TIMER_CNT_MODE_UP; + config->h_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time); + config->h_timer.init.clk_div = TIMER_CLOCK_DIV1; + config->h_timer.init.re_cnt = 0; + ald_timer_base_init(&config->h_timer); + + config->h_adc.perh = config->p_adc; + config->h_adc.init.align = ADC_DATAALIGN_RIGHT; + config->h_adc.init.scan = DISABLE; + config->h_adc.init.cont = DISABLE; + config->h_adc.init.nch_nr = ADC_NCH_NR_1; + config->h_adc.init.disc = ADC_ALL_DISABLE; + config->h_adc.init.disc_nr = ADC_DISC_NR_1; + config->h_adc.init.data_bit = ADC_CONV_BIT_12; + config->h_adc.init.div = ADC_CKDIV_128; + config->h_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE; + config->h_adc.init.n_ref = config->n_ref; + config->h_adc.init.p_ref = config->p_ref; + config->h_adc.normal_cplt_cbk = config->cplt_cbk; + config->h_adc.insert_cplt_cbk = NULL; + config->h_adc.wdg_cbk = NULL; + config->h_adc.error_cbk = NULL; + config->h_adc.ovr_cbk = NULL; + ald_adc_init(&config->h_adc); + ADC_ENABLE(&config->h_adc); + + config->config.ch = config->adc_ch; + config->config.idx = ADC_NCH_IDX_1; + config->config.samp = ADC_SAMPLETIME_4; + ald_adc_normal_channel_config(&config->h_adc, &config->config); + + config->h_dma.cplt_cbk = adc_dma_timer_trigger_cplt; + config->h_dma.cplt_arg = config; + config->h_dma.err_cbk = adc_dma_error; + config->h_dma.err_arg = &config->h_adc; + + ald_dma_config_struct(&config->h_dma.config); + config->h_dma.perh = DMA0; + config->h_dma.config.src = (void *)&config->h_adc.perh->NCHDR; + config->h_dma.config.dst = (void *)config->buf; + config->h_dma.config.size = config->size; + config->h_dma.config.data_width = DMA_DATA_SIZE_HALFWORD; + config->h_dma.config.src_inc = DMA_DATA_INC_NONE; + config->h_dma.config.dst_inc = DMA_DATA_INC_HALFWORD; + config->h_dma.config.msel = DMA_MSEL_ADC0; + config->h_dma.config.msigsel = DMA_MSIGSEL_ADC; + config->h_dma.config.channel = config->dma_ch; + ald_dma_config_basic(&config->h_dma); + ald_timer_base_start(&config->h_timer); + + return OK; } #endif @@ -647,10 +537,9 @@ ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) */ uint32_t ald_adc_normal_get_value(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_TYPE(hperh->perh)); - hperh->state &= ~ADC_STATE_NM_EOC; - return hperh->perh->NCHDR; + return hperh->perh->NCHDR; } /** @@ -662,43 +551,45 @@ uint32_t ald_adc_normal_get_value(adc_handle_t *hperh) */ uint32_t ald_adc_get_vdd_value(adc_handle_t *hperh) { - uint32_t value = 0; - - if ((hperh->init.pos_ref != ADC_POS_REF_VDD) || (hperh->init.neg_ref != ADC_NEG_REF_VSS)) - return 0; - - __LOCK(hperh); - ADC_ENABLE(hperh); - - /* Set adc and measure 2V */ - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, DISABLE << ADC_CCR_VRBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFOEN_MSK, DISABLE << ADC_CCR_VREFOEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, ENABLE << ADC_CCR_PWRMODSEL_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, 6 << ADC_CCR_CKDIV_POSS); - MODIFY_REG(hperh->perh->CON0, ADC_CON1_ALIGN_MSK, ADC_DATAALIGN_RIGHT << ADC_CON1_ALIGN_POS); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, ADC_CONV_RES_12 << ADC_CON0_RSEL_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, DISABLE << ADC_CON1_CM_POS); - MODIFY_REG(hperh->perh->NCHS1, ADC_NCHS1_NS1_MSK, ADC_CHANNEL_18 << ADC_NCHS1_NS1_POSS); - - hperh->perh->SMPT2 = 0x30; - /* Start adc normal convert */ - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - - /* Wait convert finish */ - while (!READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK)); - - value = (hperh->perh->NCHDR & 0xfff); - /* Get calibration VDD value */ - value = 2000 * 4096 / value; - hperh->vdd_value = value; - - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); - __UNLOCK(hperh); - - return value; + uint32_t value, _tmp[5]; + + if ((hperh->init.p_ref != ADC_POS_REF_VDD) || (hperh->init.n_ref != ADC_NEG_REF_VSS)) + return 0; + + _tmp[0] = hperh->perh->CCR; + _tmp[1] = hperh->perh->CON0; + _tmp[2] = hperh->perh->CON1; + _tmp[3] = hperh->perh->NCHS1; + _tmp[4] = hperh->perh->SMPT2; + + hperh->perh->CON0 = 0x0; + hperh->perh->CON1 = 0x0; + hperh->perh->NCHS1 = 0x0; + + ADC_ENABLE(hperh); + hperh->perh->CCR = 0x8B06; + MODIFY_REG(hperh->perh->CON0, ADC_CON1_ALIGN_MSK, ADC_DATAALIGN_RIGHT << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, ADC_CONV_BIT_12 << ADC_CON0_RSEL_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, DISABLE << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->NCHS1, ADC_NCHS1_NS1_MSK, ADC_CHANNEL_18 << ADC_NCHS1_NS1_POSS); + hperh->perh->SMPT2 = 0x30; + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + while (!READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK)); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS); + value = (hperh->perh->NCHDR & 0xfff); + value = value == 0 ? 1 : value; + value = (2000 << 12) / value; + hperh->vdd_value = value; + + hperh->perh->CCR = _tmp[0]; + hperh->perh->CON0 = _tmp[1]; + hperh->perh->CON1 = _tmp[2]; + hperh->perh->NCHS1 = _tmp[3]; + hperh->perh->SMPT2 = _tmp[4]; + ADC_DISABLE(hperh); + + return value; } /** @@ -710,25 +601,15 @@ uint32_t ald_adc_get_vdd_value(adc_handle_t *hperh) */ ald_status_t ald_adc_insert_start(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); - - __LOCK(hperh); - ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_IST_BUSY; + assert_param(IS_ADC_TYPE(hperh->perh)); - if ((hperh->state & ADC_STATE_NM_BUSY) == 0) - hperh->error_code = ADC_ERROR_NONE; + ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICH); - __UNLOCK(hperh); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); - if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) - { - SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); - } - - return OK; + return OK; } /** @@ -745,26 +626,11 @@ ald_status_t ald_adc_insert_start(adc_handle_t *hperh) */ ald_status_t ald_adc_insert_stop(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); - - __LOCK(hperh); - - if (((hperh->state & ADC_STATE_NM_BUSY) == 0) - && (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))) - { - ADC_DISABLE(hperh); - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY | ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_READY; - } - else - { - hperh->state |= ADC_STATE_ERROR; - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); - return OK; + assert_param(IS_ADC_TYPE(hperh->perh)); + + ADC_DISABLE(hperh); + hperh->state = ADC_STATE_READY; + return OK; } /** @@ -776,39 +642,23 @@ ald_status_t ald_adc_insert_stop(adc_handle_t *hperh) */ ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart; - - assert_param(IS_ADC_TYPE(hperh->perh)); + uint32_t _tick; - tickstart = ald_get_tick(); + assert_param(IS_ADC_TYPE(hperh->perh)); - while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) - { - if (timeout != ALD_MAX_DELAY) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->state |= ADC_STATE_TIMEOUT; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } + _tick = ald_get_tick(); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) { + if (timeout != ALD_MAX_DELAY) { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { + hperh->state = ADC_STATE_TIMEOUT; + return TIMEOUT; + } + } + } - hperh->state |= ADC_STATE_IST_EOC; - - hperh->state &= ~(ADC_STATE_IST_BUSY); - - if ((hperh->state & ADC_STATE_NM_BUSY) == 0) - hperh->state |= ADC_STATE_READY; - - hperh->state &= ~(ADC_STATE_TIMEOUT); - __UNLOCK(hperh); - return OK; + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICHS | ADC_FLAG_ICH); + return OK; } /** @@ -821,24 +671,17 @@ ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t ti */ ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); - - __LOCK(hperh); - ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_IST_BUSY; + assert_param(IS_ADC_TYPE(hperh->perh)); - if ((hperh->state & ADC_STATE_NM_BUSY) == 0) - hperh->error_code = ADC_ERROR_NONE; + SET_BIT(hperh->state, ADC_STATE_BUSY_I); + ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICHS | ADC_FLAG_ICH); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, ENABLE); - __UNLOCK(hperh); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); - ald_adc_interrupt_config(hperh, ADC_IT_ICH, ENABLE); + if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); - if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) - SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); - - return OK; + return OK; } /** @@ -856,72 +699,27 @@ ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh) */ ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); - - __LOCK(hperh); - - if (((hperh->state & ADC_STATE_NM_BUSY) == 0) - && (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))) - { - ADC_DISABLE(hperh); - ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); - hperh->state |= ADC_STATE_READY; - } - else - { - ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); - hperh->state |= ADC_STATE_ERROR; - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); - return OK; + assert_param(IS_ADC_TYPE(hperh->perh)); + + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_I); + ADC_DISABLE(hperh); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); + return OK; } /** * @brief Get ADC insert group conversion result. * @param hperh: Pointer to a adc_handle_t structure that contains * the configuration information for the specified ADC module. - * @param ih_rank: the converted ADC insert rank. - * This parameter can be one of the following values: - * @arg ADC_INJ_RANK_1: insert Channel1 selected - * @arg ADC_INJ_RANK_2: insert Channel2 selected - * @arg ADC_INJ_RANK_3: insert Channel3 selected - * @arg ADC_INJ_RANK_4: insert Channel4 selected + * @param idx: Index of the insert channel. * @retval ADC group insert conversion data */ -uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank) +uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t idx) { - uint32_t tmp; - - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_ICH_RANK_TYPE(ih_rank)); + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_ICH_IDX_TYPE(idx)); - switch (ih_rank) - { - case ADC_ICH_RANK_1: - tmp = hperh->perh->ICHDR[0]; - break; - - case ADC_ICH_RANK_2: - tmp = hperh->perh->ICHDR[1]; - break; - - case ADC_ICH_RANK_3: - tmp = hperh->perh->ICHDR[2]; - break; - - case ADC_ICH_RANK_4: - tmp = hperh->perh->ICHDR[3]; - break; - - default: - break; - } - - return tmp; + return hperh->perh->ICHDR[idx - 1]; } /** @@ -932,70 +730,40 @@ uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank) */ void ald_adc_irq_handler(adc_handle_t *hperh) { - assert_param(IS_ADC_TYPE(hperh->perh)); - - if (ald_adc_get_it_status(hperh, ADC_IT_NCH) && ald_adc_get_flag_status(hperh, ADC_FLAG_NCH)) - { - if ((hperh->state & ADC_STATE_ERROR) == 0) - hperh->state |= ADC_STATE_NM_EOC; - - if (hperh->init.cont_mode == DISABLE) - { - ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); - hperh->state &= ~(ADC_STATE_NM_BUSY); - - if ((hperh->state & ADC_STATE_IST_BUSY) == 0) - hperh->state |= ADC_STATE_READY; - } - - if (hperh->adc_reg_cplt_cbk != NULL) - hperh->adc_reg_cplt_cbk(hperh); - - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - } - - if (ald_adc_get_it_status(hperh, ADC_IT_ICH) && ald_adc_get_flag_status(hperh, ADC_FLAG_ICH)) - { - if ((hperh->state & ADC_STATE_ERROR) == 0) - hperh->state |= ADC_STATE_IST_EOC; - - if ((!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) - && (hperh->init.cont_mode == DISABLE)) - { - ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); - hperh->state &= ~(ADC_STATE_IST_BUSY); - - if ((hperh->state & ADC_STATE_NM_BUSY) == 0) - hperh->state |= ADC_STATE_READY; - } - - if (hperh->adc_inj_cplt_cbk != NULL) - hperh->adc_inj_cplt_cbk(hperh); - - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); - } - - if (ald_adc_get_it_status(hperh, ADC_IT_AWD) && ald_adc_get_flag_status(hperh, ADC_FLAG_AWD)) - { - hperh->state |= ADC_STATE_AWD; - - if (hperh->adc_out_of_win_cbk != NULL) - hperh->adc_out_of_win_cbk(hperh); - - ald_adc_clear_flag_status(hperh, ADC_FLAG_AWD); - } - - if (ald_adc_get_it_status(hperh, ADC_IT_OVR) && ald_adc_get_flag_status(hperh, ADC_FLAG_OVR)) - { - ald_adc_clear_flag_status(hperh, ADC_FLAG_OVR); - hperh->error_code |= ADC_ERROR_OVR; - hperh->state |= ADC_STATE_ERROR; - - if (hperh->adc_ovr_cbk != NULL) - hperh->adc_ovr_cbk(hperh); - } + assert_param(IS_ADC_TYPE(hperh->perh)); + + if (ald_adc_get_it_status(hperh, ADC_IT_NCH) && ald_adc_get_flag_status(hperh, ADC_FLAG_NCH)) { + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); + + if (hperh->normal_cplt_cbk) + hperh->normal_cplt_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ADC_IT_ICH) && ald_adc_get_flag_status(hperh, ADC_FLAG_ICH)) { + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICH | ADC_FLAG_ICHS); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_I); + + if (hperh->insert_cplt_cbk) + hperh->insert_cplt_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ADC_IT_AWD) && ald_adc_get_flag_status(hperh, ADC_FLAG_AWD)) { + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_WDG); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_AWD); + + if (hperh->wdg_cbk) + hperh->wdg_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ADC_IT_OVR) && ald_adc_get_flag_status(hperh, ADC_FLAG_OVR)) { + WRITE_REG(hperh->perh->CLR, ADC_FLAG_OVR); + hperh->error_code |= ADC_ERROR_OVR; + hperh->state |= ADC_STATE_ERROR; + + if (hperh->ovr_cbk) + hperh->ovr_cbk(hperh); + } } /** @@ -1017,47 +785,39 @@ void ald_adc_irq_handler(adc_handle_t *hperh) */ ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config) { - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); - assert_param(IS_ADC_NCH_RANK_TYPE(config->rank)); - assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp_time)); - - __LOCK(hperh); - - if (config->rank <= ADC_NCH_RANK_4) - { - hperh->perh->NCHS1 &= ~(0x1f << ((config->rank - 1) << 3)); - hperh->perh->NCHS1 |= (config->channel << ((config->rank - 1) << 3)); - } - else if (config->rank <= ADC_NCH_RANK_8) - { - hperh->perh->NCHS2 &= ~(0x1f << ((config->rank - 5) << 3)); - hperh->perh->NCHS2 |= (config->channel << ((config->rank - 5) << 3)); - } - else if (config->rank <= ADC_NCH_RANK_12) - { - hperh->perh->NCHS3 &= ~(0x1f << ((config->rank - 9) << 3)); - hperh->perh->NCHS3 |= (config->channel << ((config->rank - 9) << 3)); - } - else - { - hperh->perh->NCHS4 &= ~(0x1f << ((config->rank - 13) << 3)); - hperh->perh->NCHS4 |= (config->channel << ((config->rank - 13) << 3)); - } - - if (config->channel <= 15) - { - hperh->perh->SMPT1 &= ~(0x03 << (config->channel << 1)); - hperh->perh->SMPT1 |= config->samp_time << (config->channel << 1); - } - else - { - hperh->perh->SMPT2 &= ~(0x03 << ((config->channel - 16) << 1)); - hperh->perh->SMPT2 |= config->samp_time << ((config->channel - 16) << 1); - } - - __UNLOCK(hperh); - return OK; + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + assert_param(IS_ADC_NCH_IDX_TYPE(config->idx)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp)); + + if (config->idx <= ADC_NCH_IDX_4 ) { + hperh->perh->NCHS1 &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); + hperh->perh->NCHS1 |= (config->ch << (uint32_t)((config->idx - 1) << 3)); + } + else if (config->idx <= ADC_NCH_IDX_8) { + hperh->perh->NCHS2 &= ~(0x1f << (uint32_t)((config->idx - 5) << 3)); + hperh->perh->NCHS2 |= (config->ch << (uint32_t)((config->idx - 5) << 3)); + } + else if (config->idx <= ADC_NCH_IDX_12) { + hperh->perh->NCHS3 &= ~(0x1f << (uint32_t)((config->idx - 9) << 3)); + hperh->perh->NCHS3 |= (config->ch << (uint32_t)((config->idx - 9) << 3)); + } + else { + hperh->perh->NCHS4 &= ~(0x1f << (uint32_t)((config->idx - 13) << 3)); + hperh->perh->NCHS4 |= (config->ch << (uint32_t)((config->idx - 13) << 3)); + } + + if (config->ch <= 15) { + hperh->perh->SMPT1 &= ~(0x03 << (uint32_t)(config->ch << 1)); + hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 1); + } + else { + hperh->perh->SMPT2 &= ~(0x03 << (uint32_t)((config->ch - 16) << 1)); + hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - 16) << 1); + } + + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_SCANEN_MSK); + return OK; } /** @@ -1070,121 +830,52 @@ ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t * */ ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config) { - uint8_t tmp1, tmp2; - ald_status_t tmp_status = OK; - - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); - assert_param(IS_ADC_ICH_RANK_TYPE(config->rank)); - assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp_time)); - assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset)); - assert_param(IS_ADC_NBR_OF_IST_TYPE(config->ich_len)); - assert_param(IS_FUNC_STATE(config->auto_inj)); - - __LOCK(hperh); - - if (hperh->init.scan_mode == DISABLE) - { - switch (config->rank) - { - case ADC_ICH_RANK_1: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS1_MSK, config->channel << ADC_ICHS_IS1_POSS); - break; - - case ADC_ICH_RANK_2: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS2_MSK, config->channel << ADC_ICHS_IS2_POSS); - break; - - case ADC_ICH_RANK_3: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS3_MSK, config->channel << ADC_ICHS_IS3_POSS); - break; - - case ADC_ICH_RANK_4: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS4_MSK, config->channel << ADC_ICHS_IS4_POSS); - break; - - default: - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_INTERNAL; - tmp_status = ERROR; - break; - } - } - else - { - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->ich_len << ADC_CHSL_ISL_POSS); - tmp1 = config->rank ; - tmp2 = config->ich_len; - - if (tmp1 <= tmp2) - { - hperh->perh->ICHS &= ~(0x1f << ((tmp1 - 1) << 3)); - hperh->perh->ICHS |= config->channel - << ((tmp1 - 1) << 3); - } - else - { - hperh->perh->ICHS &= ~(0x1f << ((tmp1 - 1) << 3)); - hperh->perh->ICHS |= config->channel - << ((tmp1 - 1) << 3); - } - } - - if (config->auto_inj == ENABLE) - { - SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); - } - - if (hperh->init.disc_mode == ADC_ICH_DISC_EN) - { - if (config->auto_inj == DISABLE) - { - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->ich_len << ADC_CHSL_ISL_POSS); - SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); - } - else - { - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_INTERNAL; - tmp_status = ERROR; - } - } - - if (config->channel <= 15) - { - hperh->perh->SMPT1 &= ~(0x03 << (config->channel << 1)); - hperh->perh->SMPT1 |= config->samp_time << (config->channel << 1); - } - else - { - hperh->perh->SMPT2 &= ~(0x03 << ((config->channel - 16) << 1)); - hperh->perh->SMPT2 |= config->samp_time << ((config->channel - 16) << 1); - } - - switch (config->rank) - { - case ADC_ICH_RANK_1: - hperh->perh->ICHOFF[0] = config->offset; - break; - - case ADC_ICH_RANK_2: - hperh->perh->ICHOFF[1] = config->offset; - break; - - case ADC_ICH_RANK_3: - hperh->perh->ICHOFF[2] = config->offset; - break; - - case ADC_ICH_RANK_4: - hperh->perh->ICHOFF[3] = config->offset; - break; - - default: - break; - } - - __UNLOCK(hperh); - return tmp_status; + ald_status_t status = OK; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + assert_param(IS_ADC_ICH_IDX_TYPE(config->idx)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp)); + assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset)); + assert_param(IS_ADC_ICH_NR_TYPE(config->nr)); + assert_param(IS_FUNC_STATE(config->auto_m)); + + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nr << ADC_CHSL_ISL_POSS); + hperh->perh->ICHS &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); + hperh->perh->ICHS |= config->ch << (uint32_t)((config->idx - 1) << 3); + + if (config->nr > 0) + SET_BIT(hperh->perh->CON0, ADC_CON0_SCANEN_MSK); + else + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_SCANEN_MSK); + + if (config->auto_m == ENABLE) + SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); + else + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); + + if (hperh->init.disc == ADC_ICH_DISC_EN) { + if (config->auto_m == DISABLE) { + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + } + else { + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_INTERNAL; + status = ERROR; + } + } + + if (config->ch <= 15) { + hperh->perh->SMPT1 &= ~(0x03U << ((uint32_t)config->ch << 1)); + hperh->perh->SMPT1 |= config->samp << ((uint32_t)config->ch << 1); + } + else { + hperh->perh->SMPT2 &= ~(0x03U << (((uint32_t)config->ch - 16) << 1)); + hperh->perh->SMPT2 |= config->samp << (((uint32_t)config->ch - 16) << 1); + } + + hperh->perh->ICHOFF[config->idx] = config->offset; + return status; } /** @@ -1196,38 +887,35 @@ ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t * */ ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config) { - - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->watchdog_mode)); - assert_param(IS_FUNC_STATE(config->it_mode)); - assert_param(IS_HTR_TYPE(config->high_threshold)); - assert_param(IS_LTR_TYPE(config->low_threshold)); - - __LOCK(hperh); - - if ((config->watchdog_mode == ADC_ANAWTD_SING_NM) - || (config->watchdog_mode == ADC_ANAWTD_SING_IST) - || (config->watchdog_mode == ADC_ANAWTD_SING_NMIST)) - assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); - - if (config->it_mode == DISABLE) - ald_adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE); - else - ald_adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE); - - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK); - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK); - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK); - hperh->perh->CON0 |= config->watchdog_mode; - - if (READ_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK)) - MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->channel << ADC_CON0_AWDCH_POSS); - - WRITE_REG(hperh->perh->WDTL, config->low_threshold); - WRITE_REG(hperh->perh->WDTH, config->high_threshold); - - __UNLOCK(hperh); - return OK; + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->mode)); + assert_param(IS_FUNC_STATE(config->interrupt)); + assert_param(IS_HTR_TYPE(config->high_thrd)); + assert_param(IS_LTR_TYPE(config->low_thrd)); + + if ((config->mode == ADC_ANAWTD_SING_NM) + || (config->mode == ADC_ANAWTD_SING_IST) + || (config->mode == ADC_ANAWTD_SING_NMIST)) + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + + if (config->interrupt == DISABLE) + ald_adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE); + else + ald_adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE); + + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK); + hperh->perh->CON0 |= config->mode; + + if (READ_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK)) + MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->ch << ADC_CON0_AWDCH_POSS); + + WRITE_REG(hperh->perh->WDTL, config->low_thrd); + WRITE_REG(hperh->perh->WDTH, config->high_thrd); + SET_BIT(hperh->state, ADC_STATE_BUSY_WDG); + + return OK; } /** @@ -1242,16 +930,16 @@ ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_ */ void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state) { - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_IT_TYPE(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - SET_BIT(hperh->perh->CON0, it); - else - CLEAR_BIT(hperh->perh->CON0, it); + if (state == ENABLE) + SET_BIT(hperh->perh->CON0, it); + else + CLEAR_BIT(hperh->perh->CON0, it); - return; + return; } /** @@ -1265,13 +953,13 @@ void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t stat */ it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it) { - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_IT_TYPE(it)); + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IT_TYPE(it)); - if (READ_BIT(hperh->perh->CON0, it)) - return SET; + if (READ_BIT(hperh->perh->CON0, it)) + return SET; - return RESET; + return RESET; } /** @brief Check whether the specified ADC flag is set or not. @@ -1284,13 +972,13 @@ it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it) */ flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag) { - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_FLAGS_TYPE(flag)); + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_FLAGS_TYPE(flag)); - if (READ_BIT(hperh->perh->STAT, flag)) - return SET; + if (READ_BIT(hperh->perh->STAT, flag)) + return SET; - return RESET; + return RESET; } /** @brief Clear the specified ADC pending flags. @@ -1301,11 +989,11 @@ flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag) */ void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag) { - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_FLAGS_TYPE(flag)); + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_FLAGS_TYPE(flag)); - WRITE_REG(hperh->perh->CLR, flag); - return; + WRITE_REG(hperh->perh->CLR, flag); + return; } /** * @} @@ -1324,7 +1012,7 @@ void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag) */ uint32_t ald_adc_get_state(adc_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** @@ -1335,7 +1023,7 @@ uint32_t ald_adc_get_state(adc_handle_t *hperh) */ uint32_t ald_adc_get_error(adc_handle_t *hperh) { - return hperh->error_code; + return hperh->error_code; } /** @@ -1358,10 +1046,10 @@ uint32_t ald_adc_get_error(adc_handle_t *hperh) */ static void adc_dma_normal_conv_cplt(void *arg) { - adc_handle_t *hperh = (adc_handle_t *)arg; + adc_handle_t *hperh = (adc_handle_t *)arg; - if (hperh->adc_reg_cplt_cbk != NULL) - hperh->adc_reg_cplt_cbk(hperh); + if (hperh->normal_cplt_cbk) + hperh->normal_cplt_cbk(hperh); } @@ -1372,12 +1060,12 @@ static void adc_dma_normal_conv_cplt(void *arg) */ static void adc_dma_error(void *arg) { - adc_handle_t *hperh = (adc_handle_t *)arg; - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_DMA; + adc_handle_t *hperh = (adc_handle_t *)arg; + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_DMA; - if (hperh->adc_error_cbk != NULL) - hperh->adc_error_cbk(hperh); + if (hperh->error_cbk) + hperh->error_cbk(hperh); } #endif /** diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c index 7035bc506719ee6d2087ea7f769ff69bc515c95b..a3852bdb2277845f25dc2d15c188bd8363702156 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c @@ -41,7 +41,7 @@ ============================================================================== [..] This section provides functions allowing to: (+) ald_bkpc_ldo_config() API can configure LDO in backup field. - (+) ald_bkpc_bor_config() API can configure BOR in backup field. + (+) ald_bkpc_standby_wakeup_config() API can configure STANDBY wakeup. @endverbatim * @{ @@ -55,40 +55,44 @@ */ void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state) { - assert_param(IS_BKPC_LDO_OUTPUT(output)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_BKPC_LDO_OUTPUT(output)); + assert_param(IS_FUNC_STATE(state)); - BKPC_UNLOCK(); - MODIFY_REG(BKPC->CR, BKPC_CR_MT_STDB_MSK, state << BKPC_CR_MT_STDB_POS); + BKPC_UNLOCK(); + MODIFY_REG(BKPC->CR, BKPC_CR_MT_STDB_MSK, state << BKPC_CR_MT_STDB_POS); - if (state) - MODIFY_REG(BKPC->CR, BKPC_CR_LDO_VSEL_MSK, output << BKPC_CR_LDO_VSEL_POSS); + if (state) + MODIFY_REG(BKPC->CR, BKPC_CR_LDO_VSEL_MSK, output << BKPC_CR_LDO_VSEL_POSS); - BKPC_LOCK(); - return; + BKPC_LOCK(); + return; } /** - * @brief Configure bor voltage in backup field - * @param vol: Voltage select. - * @param state: DISABLE/ENABLE. + * @brief Configure standby wakeup in backup field + * @param port: Wakeup port + * @param level: HIGH/LOW. * @retval None */ -void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state) +void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level) { - assert_param(IS_BKPC_BOR_VOL(vol)); - assert_param(IS_FUNC_STATE(state)); - - BKPC_UNLOCK(); - MODIFY_REG(BKPC->PCR, BKPC_PCR_BOREN_MSK, state << BKPC_PCR_BOREN_POS); - - if (state) - MODIFY_REG(BKPC->PCR, BKPC_PCR_BORS_MSK, vol << BKPC_PCR_BORS_POSS); - - BKPC_LOCK(); - return; - - + assert_param(IS_BKPC_WAKEUP_PORT(port)); + assert_param(IS_BKPC_WAKEUP_LEVEL(level)); + + if (port == PMU_STANDBY_PORT_SEL_NONE) { + BKPC_UNLOCK(); + CLEAR_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK); + BKPC_LOCK(); + return; + } + + BKPC_UNLOCK(); + SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK); + MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS); + MODIFY_REG(BKPC->CR, BKPC_CR_WKPOL_MSK, level << BKPC_CR_WKPOL_POS); + BKPC_LOCK(); + + return; } /** * @} @@ -117,13 +121,13 @@ void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state) */ void ald_bkpc_write_ram(uint8_t idx, uint32_t value) { - assert_param(IS_BKPC_RAM_IDX(idx)); + assert_param(IS_BKPC_RAM_IDX(idx)); - RTC_UNLOCK(); - WRITE_REG(RTC->BKPR[idx], value); - RTC_LOCK(); + RTC_UNLOCK(); + WRITE_REG(RTC->BKPR[idx], value); + RTC_LOCK(); - return; + return; } /** @@ -133,9 +137,9 @@ void ald_bkpc_write_ram(uint8_t idx, uint32_t value) */ uint32_t ald_bkpc_read_ram(uint8_t idx) { - assert_param(IS_BKPC_RAM_IDX(idx)); + assert_param(IS_BKPC_RAM_IDX(idx)); - return READ_REG(RTC->BKPR[idx]); + return READ_REG(RTC->BKPR[idx]); } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c index 26a67f249377d3d27d137bacd4a0af09dd0f10f2..ec2400453d960401cc3acbc2b0b8ffbb5734b7e6 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c @@ -45,16 +45,15 @@ /** * @brief Square root operation. - * @param data: The data; + * @param data: The radicand * @retval The value of square root. */ uint32_t ald_calc_sqrt(uint32_t data) { - WRITE_REG(CALC->RDCND, data); + WRITE_REG(CALC->RDCND, data); + while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK)); - while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK)); - - return READ_REG(CALC->SQRTRES); + return READ_REG(CALC->SQRTRES); } /** @@ -66,15 +65,15 @@ uint32_t ald_calc_sqrt(uint32_t data) */ uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder) { - CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); - SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); - WRITE_REG(CALC->DIVDR, dividend); - WRITE_REG(CALC->DIVSR, divisor); + CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); + SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); + WRITE_REG(CALC->DIVDR, dividend); + WRITE_REG(CALC->DIVSR, divisor); - while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); + while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); - *remainder = READ_REG(CALC->DIVRR); - return READ_REG(CALC->DIVQR); + *remainder = READ_REG(CALC->DIVRR); + return READ_REG(CALC->DIVQR); } /** @@ -86,15 +85,15 @@ uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder) */ int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder) { - SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); - SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); - WRITE_REG(CALC->DIVDR, dividend); - WRITE_REG(CALC->DIVSR, divisor); + SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); + SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); + WRITE_REG(CALC->DIVDR, dividend); + WRITE_REG(CALC->DIVSR, divisor); - while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); + while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); - *remainder = READ_REG(CALC->DIVRR); - return READ_REG(CALC->DIVQR); + *remainder = READ_REG(CALC->DIVRR); + return READ_REG(CALC->DIVQR); } /** @@ -103,10 +102,10 @@ int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder) */ flag_status_t ald_calc_get_dz_status(void) { - if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK)) - return SET; + if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK)) + return SET; - return RESET; + return RESET; } /** diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c index cc55f867c5e465bd8c115412c034661e073cde16..fb551abdf1417cef24465b7f6d710360ef2e5c68 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c @@ -9,7 +9,7 @@ * + Peripheral Control functions * + Peripheral State and Error functions * @version V1.0 - * @date 25 Apr 2017 + * @date 25 Apr 2019 * @author AE Team * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. @@ -84,7 +84,7 @@ */ static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num); static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err); -static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num); +static ald_status_t __can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num); /** * @} */ @@ -118,72 +118,68 @@ static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num); */ ald_status_t ald_can_init(can_handle_t *hperh) { - uint32_t tickstart = 0; - - assert_param(IS_CAN_ALL(hperh->perh)); - assert_param(IS_FUNC_STATE(hperh->init.ttcm)); - assert_param(IS_FUNC_STATE(hperh->init.abom)); - assert_param(IS_FUNC_STATE(hperh->init.awk)); - assert_param(IS_FUNC_STATE(hperh->init.abom)); - assert_param(IS_FUNC_STATE(hperh->init.rfom)); - assert_param(IS_FUNC_STATE(hperh->init.txmp)); - assert_param(IS_CAN_MODE(hperh->init.mode)); - assert_param(IS_CAN_SJW(hperh->init.sjw)); - assert_param(IS_CAN_BS1(hperh->init.seg1)); - assert_param(IS_CAN_BS2(hperh->init.seg2)); - assert_param(IS_CAN_PRESCALER(hperh->init.psc)); - - if (hperh->state == CAN_STATE_RESET) - hperh->lock = UNLOCK; - - hperh->state = CAN_STATE_BUSY; - tickstart = ald_get_tick(); - - CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); - SET_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); - - while (!READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) - { - if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) - { - hperh->state = CAN_STATE_TIMEOUT; - __UNLOCK(hperh); - - return TIMEOUT; - } - } - - MODIFY_REG(hperh->perh->CON, CAN_CON_TTCEN_MSK, hperh->init.ttcm << CAN_CON_TTCEN_POS); - MODIFY_REG(hperh->perh->CON, CAN_CON_ABOFFEN_MSK, hperh->init.abom << CAN_CON_ABOFFEN_POS); - MODIFY_REG(hperh->perh->CON, CAN_CON_AWKEN_MSK, hperh->init.awk << CAN_CON_AWKEN_POS); - MODIFY_REG(hperh->perh->CON, CAN_CON_ARTXDIS_MSK, hperh->init.artx << CAN_CON_ARTXDIS_POS); - MODIFY_REG(hperh->perh->CON, CAN_CON_RXFOPM_MSK, hperh->init.rfom << CAN_CON_RXFOPM_POS); - MODIFY_REG(hperh->perh->CON, CAN_CON_TXMP_MSK, hperh->init.txmp << CAN_CON_TXMP_POS); - MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_LOOP_MSK, (hperh->init.mode & 0x1) << CAN_BTIME_LOOP_POS); - MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SILENT_MSK, ((hperh->init.mode >> 1) & 0x1) << CAN_BTIME_SILENT_POS); - MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_RESJW_MSK, hperh->init.sjw << CAN_BTIME_RESJW_POSS); - MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SEG1_MSK, hperh->init.seg1 << CAN_BTIME_SEG1_POSS); - MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SEG2_MSK, hperh->init.seg2 << CAN_BTIME_SEG2_POSS); - MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_BPSC_MSK, (hperh->init.psc - 1) << CAN_BTIME_BPSC_POSS); - - CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); - tickstart = ald_get_tick(); - - while (READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) - { - if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) - { - hperh->state = CAN_STATE_TIMEOUT; - __UNLOCK(hperh); - - return TIMEOUT; - } - } - - hperh->err = CAN_ERROR_NONE; - hperh->state = CAN_STATE_READY; - - return OK; + uint32_t tickstart = 0; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_FUNC_STATE(hperh->init.ttcm)); + assert_param(IS_FUNC_STATE(hperh->init.abom)); + assert_param(IS_FUNC_STATE(hperh->init.awk)); + assert_param(IS_FUNC_STATE(hperh->init.abom)); + assert_param(IS_FUNC_STATE(hperh->init.rfom)); + assert_param(IS_FUNC_STATE(hperh->init.txmp)); + assert_param(IS_CAN_MODE(hperh->init.mode)); + assert_param(IS_CAN_SJW(hperh->init.sjw)); + assert_param(IS_CAN_BS1(hperh->init.seg1)); + assert_param(IS_CAN_BS2(hperh->init.seg2)); + assert_param(IS_CAN_PRESCALER(hperh->init.psc)); + + if (hperh->state == CAN_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = CAN_STATE_BUSY; + tickstart = ald_get_tick(); + + CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); + SET_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); + + while (!READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { + if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + + return TIMEOUT; + } + } + + MODIFY_REG(hperh->perh->CON, CAN_CON_TTCEN_MSK, hperh->init.ttcm << CAN_CON_TTCEN_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_ABOFFEN_MSK, hperh->init.abom << CAN_CON_ABOFFEN_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_AWKEN_MSK, hperh->init.awk << CAN_CON_AWKEN_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_ARTXDIS_MSK, hperh->init.artx << CAN_CON_ARTXDIS_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_RXFOPM_MSK, hperh->init.rfom << CAN_CON_RXFOPM_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_TXMP_MSK, hperh->init.txmp << CAN_CON_TXMP_POS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_LOOP_MSK, (hperh->init.mode & 0x1) << CAN_BTIME_LOOP_POS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SILENT_MSK, ((hperh->init.mode >> 1) & 0x1) << CAN_BTIME_SILENT_POS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_RESJW_MSK, hperh->init.sjw << CAN_BTIME_RESJW_POSS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SEG1_MSK, hperh->init.seg1 << CAN_BTIME_SEG1_POSS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SEG2_MSK, hperh->init.seg2 << CAN_BTIME_SEG2_POSS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_BPSC_MSK, (hperh->init.psc - 1) << CAN_BTIME_BPSC_POSS); + + CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); + tickstart = ald_get_tick(); + + while (READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { + if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + + return TIMEOUT; + } + } + + hperh->err = CAN_ERROR_NONE; + hperh->state = CAN_STATE_READY; + + return OK; } /** @@ -196,50 +192,46 @@ ald_status_t ald_can_init(can_handle_t *hperh) */ ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config) { - uint32_t pos; - - assert_param(IS_CAN_ALL(hperh->perh)); - assert_param(IS_CAN_FILTER_NUMBER(config->number)); - assert_param(IS_CAN_FILTER_MODE(config->mode)); - assert_param(IS_CAN_FILTER_SCALE(config->scale)); - assert_param(IS_CAN_FILTER_FIFO(config->fifo)); - assert_param(IS_FUNC_STATE(config->active)); - assert_param(IS_CAN_BANKNUMBER(config->bank_number)); - - pos = 1 << config->number; - - SET_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK); - CLEAR_BIT(hperh->perh->FLTGO, pos); - - if (config->scale == CAN_FILTER_SCALE_16) - { - CLEAR_BIT(hperh->perh->FLTWS, pos); - hperh->perh->Filter[config->number].FLT1 = - ((0xFFFF & config->mask_id_low) << 16) | - (0xFFFF & config->id_low); - - hperh->perh->Filter[config->number].FLT2 = - ((0xFFFF & config->mask_id_high) << 16) | - (0xFFFF & config->id_high); - } - - if (config->scale == CAN_FILTER_SCALE_32) - { - SET_BIT(hperh->perh->FLTWS, pos); - hperh->perh->Filter[config->number].FLT1 = - ((0xFFFF & config->id_high) << 16) | - (0xFFFF & config->id_low); - hperh->perh->Filter[config->number].FLT2 = - ((0xFFFF & config->mask_id_high) << 16) | - (0xFFFF & config->mask_id_low); - } - - MODIFY_REG(hperh->perh->FLTM, pos, config->mode << config->number); - MODIFY_REG(hperh->perh->FLTAS, pos, config->fifo << config->number); - MODIFY_REG(hperh->perh->FLTGO, pos, config->active << config->number); - CLEAR_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK); - - return OK; + uint32_t pos; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_FILTER_NUMBER(config->number)); + assert_param(IS_CAN_FILTER_MODE(config->mode)); + assert_param(IS_CAN_FILTER_SCALE(config->scale)); + assert_param(IS_CAN_FILTER_FIFO(config->fifo)); + assert_param(IS_FUNC_STATE(config->active)); + + pos = 1 << config->number; + SET_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK); + CLEAR_BIT(hperh->perh->FLTGO, pos); + + if (config->scale == CAN_FILTER_SCALE_16) { + CLEAR_BIT(hperh->perh->FLTWS, pos); + hperh->perh->Filter[config->number].FLT1 = + ((0xFFFF & config->mask_id_low) << 16) | + (0xFFFF & config->id_low); + + hperh->perh->Filter[config->number].FLT2 = + ((0xFFFF & config->mask_id_high) << 16) | + (0xFFFF & config->id_high); + } + + if (config->scale == CAN_FILTER_SCALE_32) { + SET_BIT(hperh->perh->FLTWS, pos); + hperh->perh->Filter[config->number].FLT1 = + ((0xFFFF & config->id_high) << 16) | + (0xFFFF & config->id_low); + hperh->perh->Filter[config->number].FLT2 = + ((0xFFFF & config->mask_id_high) << 16) | + (0xFFFF & config->mask_id_low); + } + + MODIFY_REG(hperh->perh->FLTM, pos, config->mode << config->number); + MODIFY_REG(hperh->perh->FLTAS, pos, config->fifo << config->number); + MODIFY_REG(hperh->perh->FLTGO, pos, config->active << config->number); + CLEAR_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK); + + return OK; } /** @@ -249,12 +241,12 @@ ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config) */ void ald_can_reset(can_handle_t *hperh) { - assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_ALL(hperh->perh)); - hperh->state = CAN_STATE_RESET; - __UNLOCK(hperh); + hperh->state = CAN_STATE_RESET; + __UNLOCK(hperh); - return; + return; } /** @@ -287,69 +279,63 @@ void ald_can_reset(can_handle_t *hperh) */ ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout) { - uint32_t tick; - can_tx_mailbox_t idx; - - assert_param(IS_CAN_ALL(hperh->perh)); - assert_param(IS_CAN_IDTYPE(msg->type)); - assert_param(IS_CAN_RTR(msg->rtr)); - assert_param(IS_CAN_DATA_LEN(msg->len)); - - __LOCK(hperh); - SET_BIT(hperh->state, CAN_STATE_TX_MASK); - - if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) - idx = CAN_TX_MAILBOX_0; - else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) - idx = CAN_TX_MAILBOX_1; - else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) - idx = CAN_TX_MAILBOX_2; - else - idx = CAN_TX_MAILBOX_NONE; - - if (idx == CAN_TX_MAILBOX_NONE) - { - hperh->state = CAN_STATE_ERROR; - __UNLOCK(hperh); - return ERROR; - } - - CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); - MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_IDE_MSK, msg->type << CAN_TXID0_IDE_POS); - MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_RTR_MSK, msg->rtr << CAN_TXID0_RTR_POS); - - if (msg->type == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(msg->std)); - MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, msg->std << CAN_TXID0_STDID_POSS); - CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK); - } - else - { - assert_param(IS_CAN_EXTID(msg->ext)); - MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS); - MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS); - } - - MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS); - WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24)); - WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24)); - SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); - tick = ald_get_tick(); - - while (!(ald_can_get_tx_status(hperh, idx))) - { - if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) - { - hperh->state = CAN_STATE_TIMEOUT; - __UNLOCK(hperh); - return TIMEOUT; - } - } - - CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK); - __UNLOCK(hperh); - return OK; + uint32_t tick; + can_tx_mailbox_t idx; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IDTYPE(msg->type)); + assert_param(IS_CAN_RTR(msg->rtr)); + assert_param(IS_CAN_DATA_LEN(msg->len)); + + __LOCK(hperh); + SET_BIT(hperh->state, CAN_STATE_TX_MASK); + + if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) + idx = CAN_TX_MAILBOX_0; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) + idx = CAN_TX_MAILBOX_1; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) + idx = CAN_TX_MAILBOX_2; + else + idx = CAN_TX_MAILBOX_NONE; + + if (idx == CAN_TX_MAILBOX_NONE) { + hperh->state = CAN_STATE_ERROR; + __UNLOCK(hperh); + return ERROR; + } + + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_IDE_MSK, msg->type << CAN_TXID0_IDE_POS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_RTR_MSK, msg->rtr << CAN_TXID0_RTR_POS); + + if (msg->type == CAN_ID_STD) { + assert_param(IS_CAN_STDID(msg->std)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, msg->std << CAN_TXID0_STDID_POSS); + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK); + } + else { + assert_param(IS_CAN_EXTID(msg->ext)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS); + } + MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24)); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24)); + SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + tick = ald_get_tick(); + + while (!(ald_can_get_tx_status(hperh, idx))) { + if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + + CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK); + __UNLOCK(hperh); + return OK; } /** @@ -360,60 +346,58 @@ ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeo */ ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg) { - uint8_t idx = CAN_TX_MAILBOX_NONE; - - assert_param(IS_CAN_ALL(hperh->perh)); - assert_param(IS_CAN_IDTYPE(msg->type)); - assert_param(IS_CAN_RTR(msg->rtr)); - assert_param(IS_CAN_DATA_LEN(msg->len)); - - if ((hperh->state != CAN_STATE_READY) && (hperh->state != CAN_STATE_BUSY_RX)) - return BUSY; - - if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) - idx = CAN_TX_MAILBOX_0; - else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) - idx = CAN_TX_MAILBOX_1; - else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) - idx = CAN_TX_MAILBOX_2; - else - idx = CAN_TX_MAILBOX_NONE; - - if (idx == CAN_TX_MAILBOX_NONE) - return BUSY; - - CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); - MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_IDE_MSK, msg->type << CAN_TXID0_IDE_POS); - MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_RTR_MSK, msg->rtr << CAN_TXID0_RTR_POS); - - if (msg->type == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(msg->std)); - MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, msg->std << CAN_TXID0_STDID_POSS); - CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK); - } - else - { - assert_param(IS_CAN_EXTID(msg->ext)); - MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS); - MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS); - } - - MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS); - WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24)); - WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24)); - - SET_BIT(hperh->state, CAN_STATE_TX_MASK); - - ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE); - ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE); - ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); - ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE); - ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); - ald_can_interrupt_config(hperh, CAN_IT_TXM, ENABLE); - - SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); - return OK; + uint8_t idx = CAN_TX_MAILBOX_NONE; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IDTYPE(msg->type)); + assert_param(IS_CAN_RTR(msg->rtr)); + assert_param(IS_CAN_DATA_LEN(msg->len)); + + if ((hperh->state & CAN_STATE_TX_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY)) + return BUSY; + + if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) + idx = CAN_TX_MAILBOX_0; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) + idx = CAN_TX_MAILBOX_1; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) + idx = CAN_TX_MAILBOX_2; + else + idx = CAN_TX_MAILBOX_NONE; + + if (idx == CAN_TX_MAILBOX_NONE) + return BUSY; + + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_IDE_MSK, msg->type << CAN_TXID0_IDE_POS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_RTR_MSK, msg->rtr << CAN_TXID0_RTR_POS); + + if (msg->type == CAN_ID_STD) { + assert_param(IS_CAN_STDID(msg->std)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, msg->std << CAN_TXID0_STDID_POSS); + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK); + } + else { + assert_param(IS_CAN_EXTID(msg->ext)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS); + } + + MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24)); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24)); + + SET_BIT(hperh->state, CAN_STATE_TX_MASK); + + ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_TXM, ENABLE); + + SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + return OK; } /** @@ -426,51 +410,50 @@ ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg) */ ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout) { - uint32_t tick, stid, exid; - - assert_param(IS_CAN_ALL(hperh->perh)); - assert_param(IS_CAN_FIFO(num)); - - __LOCK(hperh); - SET_BIT(hperh->state, CAN_STATE_RX_MASK); - tick = ald_get_tick(); - - while (CAN_RX_MSG_PENDING(hperh, num) == 0) - { - if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) - { - hperh->state = CAN_STATE_TIMEOUT; - __UNLOCK(hperh); - return TIMEOUT; - } - } - - stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS); - exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS); - msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS); - - if (msg->type == CAN_ID_STD) - msg->std = stid; - else - msg->ext = (stid << 18) | exid; - - msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS); - msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS); - msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS); - msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF; - msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF; - msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF; - msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF; - msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF; - msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF; - msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF; - msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF; - - can_rx_fifo_release(hperh, num); - CLEAR_BIT(hperh->state, CAN_STATE_RX_MASK); - __UNLOCK(hperh); - - return OK; + uint32_t tick, stid, exid; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_FIFO(num)); + assert_param(msg != NULL); + + __LOCK(hperh); + SET_BIT(hperh->state, num == CAN_RX_FIFO0 ? CAN_STATE_RX0_MASK : CAN_STATE_RX1_MASK); + tick = ald_get_tick(); + + while (CAN_RX_MSG_PENDING(hperh, num) == 0) { + if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + + stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS); + exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS); + msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS); + + if (msg->type == CAN_ID_STD) + msg->std = stid; + else + msg->ext = (stid << 18) | exid; + + msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS); + msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS); + msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS); + msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF; + msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF; + msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF; + msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF; + msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF; + msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF; + msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF; + msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF; + + can_rx_fifo_release(hperh, num); + CLEAR_BIT(hperh->state, num == CAN_RX_FIFO0 ? CAN_STATE_RX0_MASK : CAN_STATE_RX1_MASK); + __UNLOCK(hperh); + + return OK; } /** @@ -482,27 +465,37 @@ ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t * */ ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg) { - assert_param(IS_CAN_ALL(hperh->perh)); - assert_param(IS_CAN_FIFO(num)); - - if ((hperh->state != CAN_STATE_READY) && (hperh->state != CAN_STATE_BUSY_TX)) - return BUSY; - - SET_BIT(hperh->state, CAN_STATE_RX_MASK); - hperh->rx_msg = msg; - - ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE); - ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE); - ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); - ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE); - ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); - - if (num == CAN_RX_FIFO0) - ald_can_interrupt_config(hperh, CAN_IT_FP0, ENABLE); - else - ald_can_interrupt_config(hperh, CAN_IT_FP1, ENABLE); - - return OK; + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_FIFO(num)); + assert_param(msg != NULL); + + if (num == CAN_RX_FIFO0) { + if ((hperh->state & CAN_STATE_RX0_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY)) + return BUSY; + + SET_BIT(hperh->state, CAN_STATE_RX0_MASK); + hperh->rx0_msg = msg; + } + else { + if ((hperh->state & CAN_STATE_RX1_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY)) + return BUSY; + + SET_BIT(hperh->state, CAN_STATE_RX1_MASK); + hperh->rx1_msg = msg; + } + + ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); + + if (num == CAN_RX_FIFO0) + ald_can_interrupt_config(hperh, CAN_IT_FP0, ENABLE); + else + ald_can_interrupt_config(hperh, CAN_IT_FP1, ENABLE); + + return OK; } /** * @} @@ -538,31 +531,29 @@ ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_m */ ald_status_t ald_can_sleep(can_handle_t *hperh) { - uint32_t tick; + uint32_t tick; - assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_ALL(hperh->perh)); - __LOCK(hperh); - hperh->state = CAN_STATE_BUSY; + __LOCK(hperh); + hperh->state = CAN_STATE_BUSY; - CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); - SET_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); - tick = ald_get_tick(); + CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); + SET_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); + tick = ald_get_tick(); - while ((!(READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK))) || READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) - { - if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) - { - hperh->state = CAN_STATE_TIMEOUT; - __UNLOCK(hperh); - return TIMEOUT; - } - } + while ((!(READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK))) || READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { + if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } - hperh->state = CAN_STATE_READY; - __UNLOCK(hperh); + hperh->state = CAN_STATE_READY; + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -573,30 +564,28 @@ ald_status_t ald_can_sleep(can_handle_t *hperh) */ ald_status_t ald_can_wake_up(can_handle_t *hperh) { - uint32_t tick; + uint32_t tick; - assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_ALL(hperh->perh)); - __LOCK(hperh); - hperh->state = CAN_STATE_BUSY; + __LOCK(hperh); + hperh->state = CAN_STATE_BUSY; - CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); - tick = ald_get_tick(); + CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); + tick = ald_get_tick(); - while (READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK)) - { - if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) - { - hperh->state = CAN_STATE_TIMEOUT; - __UNLOCK(hperh); - return TIMEOUT; - } - } + while (READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK)) { + if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } - hperh->state = CAN_STATE_READY; - __UNLOCK(hperh); + hperh->state = CAN_STATE_READY; + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -604,115 +593,99 @@ ald_status_t ald_can_wake_up(can_handle_t *hperh) * @param hperh: pointer to a can_handle_t structure. * @retval None */ -void ald_can_irq_handler(can_handle_t *hperh) +void ald_can_irq_handler(can_handle_t* hperh) { - if (ald_can_get_it_status(hperh, CAN_IT_TXM)) - { - if ((ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_0)) - || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_1)) - || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_2))) - __can_send_by_it(hperh, 0); - - if (hperh->perh->TXSTAT & CAN_TXSTAT_M0TXERR_MSK) - { - SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M0REQC_MSK); - __can_send_by_it(hperh, 1); - } - - if (hperh->perh->TXSTAT & CAN_TXSTAT_M1TXERR_MSK) - { - SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M1REQC_MSK); - __can_send_by_it(hperh, 1); - } - - if (hperh->perh->TXSTAT & CAN_TXSTAT_M2TXERR_MSK) - { - SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M2REQC_MSK); - __can_send_by_it(hperh, 1); - } - } - - if ((ald_can_get_it_status(hperh, CAN_IT_FP0)) - && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO0) != 0)) - __can_recv_by_it(hperh, CAN_RX_FIFO0); - - if ((ald_can_get_it_status(hperh, CAN_IT_FP1)) - && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO1) != 0)) - __can_recv_by_it(hperh, CAN_RX_FIFO1); - - if ((ald_can_get_flag_status(hperh, CAN_FLAG_WARN)) - && (ald_can_get_it_status(hperh, CAN_IT_WARN)) - && (ald_can_get_it_status(hperh, CAN_IT_ERR))) - hperh->err |= CAN_ERROR_EWG; - - if ((ald_can_get_flag_status(hperh, CAN_FLAG_PERR)) - && (ald_can_get_it_status(hperh, CAN_IT_PERR)) - && (ald_can_get_it_status(hperh, CAN_IT_ERR))) - hperh->err |= CAN_ERROR_EPV; - - if ((ald_can_get_flag_status(hperh, CAN_FLAG_BOF)) - && (ald_can_get_it_status(hperh, CAN_IT_BOF)) - && (ald_can_get_it_status(hperh, CAN_IT_ERR))) - hperh->err |= CAN_ERROR_BOF; - - if (READ_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK) - && (ald_can_get_it_status(hperh, CAN_IT_PRERR)) - && (ald_can_get_it_status(hperh, CAN_IT_ERR))) - { - - switch (READ_BITS(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK, CAN_ERRSTAT_PRERRF_POSS)) - { - case (1): - hperh->err |= CAN_ERROR_STF; - break; - - case (2): - hperh->err |= CAN_ERROR_FOR; - break; - - case (3): - hperh->err |= CAN_ERROR_ACK; - break; - - case (4): - hperh->err |= CAN_ERROR_BR; - break; - - case (5): - hperh->err |= CAN_ERROR_BD; - break; - - case (6): - hperh->err |= CAN_ERROR_CRC; - break; - - default: - break; - } - - CLEAR_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK); - - if (READ_BIT(hperh->perh->IE, CAN_IE_TXMEIE_MSK)) - ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE); - - if (READ_BIT(hperh->perh->IE, CAN_IE_F0PIE_MSK)) - ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE); - - if (READ_BIT(hperh->perh->IE, CAN_IE_F1PIE_MSK)) - ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE); - } - - if ((ald_can_get_flag_status(hperh, CAN_FLAG_ERR)) && (hperh->err == CAN_ERROR_NONE)) - hperh->err = CAN_ERROR_UNK; - - if (hperh->err != CAN_ERROR_NONE) - { - SET_BIT(hperh->perh->IFC, CAN_IFC_ERRIFC_MSK); - hperh->state = CAN_STATE_READY; - - if (hperh->error_cbk != NULL) - hperh->error_cbk(hperh); - } + if (ald_can_get_it_status(hperh, CAN_IT_TXM)) { + if ((ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_0)) + || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_1)) + || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_2))) + __can_send_by_it(hperh, 0); + if (hperh->perh->TXSTAT & CAN_TXSTAT_M0TXERR_MSK) { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M0REQC_MSK); + __can_send_by_it(hperh, 1); + } + if (hperh->perh->TXSTAT & CAN_TXSTAT_M1TXERR_MSK) { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M1REQC_MSK); + __can_send_by_it(hperh, 1); + } + if (hperh->perh->TXSTAT & CAN_TXSTAT_M2TXERR_MSK) { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M2REQC_MSK); + __can_send_by_it(hperh, 1); + } + } + + if ((ald_can_get_it_status(hperh, CAN_IT_FP0)) + && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO0) != 0)) + __can_recv_by_it(hperh, CAN_RX_FIFO0); + + if ((ald_can_get_it_status(hperh, CAN_IT_FP1)) + && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO1) != 0)) + __can_recv_by_it(hperh, CAN_RX_FIFO1); + + if ((ald_can_get_flag_status(hperh, CAN_FLAG_WARN)) + && (ald_can_get_it_status(hperh, CAN_IT_WARN)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) + hperh->err |= CAN_ERROR_EWG; + + if ((ald_can_get_flag_status(hperh, CAN_FLAG_PERR)) + && (ald_can_get_it_status(hperh, CAN_IT_PERR)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) + hperh->err |= CAN_ERROR_EPV; + + if ((ald_can_get_flag_status(hperh, CAN_FLAG_BOF)) + && (ald_can_get_it_status(hperh, CAN_IT_BOF)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) + hperh->err |= CAN_ERROR_BOF; + + if (READ_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK) + && (ald_can_get_it_status(hperh, CAN_IT_PRERR)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) { + + switch (READ_BITS(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK, CAN_ERRSTAT_PRERRF_POSS)) { + case(1): + hperh->err |= CAN_ERROR_STF; + break; + case(2): + hperh->err |= CAN_ERROR_FOR; + break; + case(3): + hperh->err |= CAN_ERROR_ACK; + break; + case(4): + hperh->err |= CAN_ERROR_BR; + break; + case(5): + hperh->err |= CAN_ERROR_BD; + break; + case(6): + hperh->err |= CAN_ERROR_CRC; + break; + default: + break; + } + + CLEAR_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK); + + if (READ_BIT(hperh->perh->IE, CAN_IE_TXMEIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE); + + if (READ_BIT(hperh->perh->IE, CAN_IE_F0PIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE); + + if (READ_BIT(hperh->perh->IE, CAN_IE_F1PIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE); + } + + if ((ald_can_get_flag_status(hperh, CAN_FLAG_ERR)) && (hperh->err == CAN_ERROR_NONE)) + hperh->err = CAN_ERROR_UNK; + + if (hperh->err != CAN_ERROR_NONE) { + SET_BIT(hperh->perh->IFC, CAN_IFC_ERRIFC_MSK); + hperh->state = CAN_STATE_READY; + + if (hperh->error_cbk != NULL) + hperh->error_cbk(hperh); + } } /** @@ -723,52 +696,45 @@ void ald_can_irq_handler(can_handle_t *hperh) */ type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box) { - assert_param(IS_CAN_ALL(hperh->perh)); - assert_param(IS_CAN_TX_MAILBOX(box)); - - switch (box) - { - case CAN_TX_MAILBOX_0: - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0REQC_MSK)) - return FALSE; - - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0TXC_MSK)) - return FALSE; - - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) - return FALSE; - - return TRUE; - - case CAN_TX_MAILBOX_1: - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1REQC_MSK)) - return FALSE; - - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1TXC_MSK)) - return FALSE; - - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) - return FALSE; - - return TRUE; - - case CAN_TX_MAILBOX_2: - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2REQC_MSK)) - return FALSE; - - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2TXC_MSK)) - return FALSE; - - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) - return FALSE; - - return TRUE; - - default: - break; - } - - return FALSE; + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_TX_MAILBOX(box)); + + switch (box) { + case CAN_TX_MAILBOX_0: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0REQC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0TXC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) + return FALSE; + + return TRUE; + + case CAN_TX_MAILBOX_1: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1REQC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1TXC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) + return FALSE; + + return TRUE; + + case CAN_TX_MAILBOX_2: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2REQC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2TXC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) + return FALSE; + + return TRUE; + + default: + break; + } + + return FALSE; } /** @@ -779,28 +745,24 @@ type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box) */ void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box) { - assert_param(IS_CAN_ALL(hperh->perh)); - assert_param(IS_CAN_TX_MAILBOX(box)); - - switch (box) - { - case CAN_TX_MAILBOX_0: - SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0STPREQ_MSK); - break; - - case CAN_TX_MAILBOX_1: - SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1STPREQ_MSK); - break; - - case CAN_TX_MAILBOX_2: - SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2STPREQ_MSK); - break; - - default: - break; - } - - return; + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_TX_MAILBOX(box)); + + switch (box) { + case CAN_TX_MAILBOX_0: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0STPREQ_MSK); + break; + case CAN_TX_MAILBOX_1: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1STPREQ_MSK); + break; + case CAN_TX_MAILBOX_2: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2STPREQ_MSK); + break; + default: + break; + } + + return; } /** @@ -816,16 +778,16 @@ void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box) */ void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state) { - assert_param(IS_CAN_ALL(hperh->perh)); - assert_param(IS_CAN_IT(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IT(it)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - SET_BIT(hperh->perh->IE, it); - else - CLEAR_BIT(hperh->perh->IE, it); + if (state == ENABLE) + SET_BIT(hperh->perh->IE, it); + else + CLEAR_BIT(hperh->perh->IE, it); - return; + return; } /** @@ -839,13 +801,13 @@ void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t stat */ it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it) { - assert_param(IS_CAN_ALL(hperh->perh)); - assert_param(IS_CAN_IT(it)); + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IT(it)); - if (READ_BIT(hperh->perh->IE, it)) - return SET; + if (READ_BIT(hperh->perh->IE, it)) + return SET; - return RESET; + return RESET; } /** @@ -859,48 +821,42 @@ it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it) */ flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag) { - uint32_t idx = (flag >> 20) & 0x7; - uint32_t _flag = flag & 0xFF8FFFFF; - - assert_param(IS_CAN_GET_FLAG(flag)); - - switch (idx) - { - case 0: - if (READ_BIT(hperh->perh->STAT, _flag)) - return SET; - - break; - - case 1: - if (READ_BIT(hperh->perh->TXSTAT, _flag)) - return SET; - - break; - - case 2: - if (READ_BIT(hperh->perh->RXF0, _flag)) - return SET; - - break; - - case 3: - if (READ_BIT(hperh->perh->RXF1, _flag)) - return SET; - - break; - - case 4: - if (READ_BIT(hperh->perh->ERRSTAT, _flag)) - return SET; - - break; - - default: - break; - } - - return RESET; + uint32_t idx = (flag >> 20) & 0x7; + uint32_t _flag = flag & 0xFF8FFFFF; + + assert_param(IS_CAN_GET_FLAG(flag)); + + switch (idx) { + case 0: + if (READ_BIT(hperh->perh->STAT, _flag)) + return SET; + + break; + case 1: + if (READ_BIT(hperh->perh->TXSTAT, _flag)) + return SET; + + break; + case 2: + if (READ_BIT(hperh->perh->RXF0, _flag)) + return SET; + + break; + case 3: + if (READ_BIT(hperh->perh->RXF1, _flag)) + return SET; + + break; + case 4: + if (READ_BIT(hperh->perh->ERRSTAT, _flag)) + return SET; + + break; + default: + break; + } + + return RESET; } /** @brief Clear the specified CAN pending flag. @@ -910,34 +866,29 @@ flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag) */ void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag) { - uint32_t idx = (flag >> 20) & 0x7; - uint32_t _flag = flag & 0xFF8FFFFF; - - assert_param(IS_CAN_CLEAR_FLAG(flag)); - - switch (idx) - { - case 0: - WRITE_REG(hperh->perh->IFC, _flag); - break; - - case 1: - WRITE_REG(hperh->perh->TXSTATC, _flag); - break; - - case 2: - WRITE_REG(hperh->perh->RXF0C, _flag); - break; - - case 3: - WRITE_REG(hperh->perh->RXF1C, _flag); - break; - - default: - break; - } - - return; + uint32_t idx = ((uint32_t)flag >> 20) & 0x7; + uint32_t _flag = flag & 0xFF8FFFFF; + + assert_param(IS_CAN_CLEAR_FLAG(flag)); + + switch (idx) { + case 0: + WRITE_REG(hperh->perh->IFC, _flag); + break; + case 1: + WRITE_REG(hperh->perh->TXSTATC, _flag); + break; + case 2: + WRITE_REG(hperh->perh->RXF0C, _flag); + break; + case 3: + WRITE_REG(hperh->perh->RXF1C, _flag); + break; + default: + break; + } + + return; } /** * @} @@ -965,7 +916,7 @@ void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag) */ can_state_t ald_can_get_state(can_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** @@ -975,7 +926,7 @@ can_state_t ald_can_get_state(can_handle_t *hperh) */ can_error_t ald_can_get_error(can_handle_t *hperh) { - return hperh->err; + return hperh->err; } /** @@ -998,10 +949,10 @@ can_error_t ald_can_get_error(can_handle_t *hperh) */ static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num) { - if (num == CAN_RX_FIFO0) - SET_BIT(hperh->perh->RXF0, CAN_RXF0_FREE_MSK); - else - SET_BIT(hperh->perh->RXF1, CAN_RXF1_FREE_MSK); + if (num == CAN_RX_FIFO0) + SET_BIT(hperh->perh->RXF0, CAN_RXF0_FREE_MSK); + else + SET_BIT(hperh->perh->RXF1, CAN_RXF1_FREE_MSK); } @@ -1013,29 +964,63 @@ static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num) */ static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err) { - ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE); + + if (hperh->state == CAN_STATE_BUSY_TX) { + ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); + } - if (hperh->state == CAN_STATE_BUSY_TX) - { - ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE); - ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE); - ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); - ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE); - ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); - } + CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK); - CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK); + if ((err == 0) && (hperh->tx_cplt_cbk)) + hperh->tx_cplt_cbk(hperh); - if ((err == 0) && (hperh->tx_cplt_cbk)) - hperh->tx_cplt_cbk(hperh); + if ((err) && (hperh->error_cbk != NULL)) { + hperh->err = CAN_ERROR_UNK; + hperh->error_cbk(hperh); + } - if ((err) && (hperh->error_cbk != NULL)) - { - hperh->err = CAN_ERROR_UNK; - hperh->error_cbk(hperh); - } + return OK; +} - return OK; +/** + * @brief Check whether the data in the mailbox is contaminated. + * @param hperh: Pointer to a can_handle_t structure. + * @param num: Specify the FIFO number + * @retval status: + * - 0: Data is valid + * - 1: Data is invalid + */ +static int __can_rx_check(can_handle_t *hperh, can_rx_fifo_t num) +{ + int i; + + if (!(hperh->perh->RESERVED0[0] & 0x200000U)) + return 0; + + if (num == CAN_RX_FIFO0) { + for (i = 0; i < 3; ++i) { + if (hperh->perh->RXF0 & 0x3) + SET_BIT(hperh->perh->RXF0, CAN_RXF0_FREE_MSK); + else + break; + } + } + else { + for (i = 0; i < 3; ++i) { + if (hperh->perh->RXF1 & 0x3) + SET_BIT(hperh->perh->RXF1, CAN_RXF1_FREE_MSK); + else + break; + } + } + + hperh->perh->RESERVED0[0] |= 0x200000U; + return 1; } /** @@ -1044,57 +1029,60 @@ static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err) * @param num: Specify the FIFO number * @retval Status, see ald_status_t. */ -static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num) +static ald_status_t __can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num) { - uint32_t stid, exid; - - stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS); - exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS); - hperh->rx_msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS); - - if (hperh->rx_msg->type == CAN_ID_STD) - hperh->rx_msg->std = stid; - else - hperh->rx_msg->ext = (stid << 18) | exid; - - hperh->rx_msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS); - hperh->rx_msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS); - hperh->rx_msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS); - hperh->rx_msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF; - hperh->rx_msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF; - hperh->rx_msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF; - hperh->rx_msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF; - hperh->rx_msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF; - hperh->rx_msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF; - hperh->rx_msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF; - hperh->rx_msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF; - - if (num == CAN_RX_FIFO0) - { - can_rx_fifo_release(hperh, CAN_RX_FIFO0); - ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE); - } - else - { - can_rx_fifo_release(hperh, CAN_RX_FIFO1); - ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE); - } - - if (hperh->state == CAN_STATE_BUSY_RX) - { - ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE); - ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE); - ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); - ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE); - ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); - } - - CLEAR_BIT(hperh->state, CAN_STATE_RX_MASK); - - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - - return OK; + uint32_t stid, exid; + can_rx_msg_t *_msg; + + if (__can_rx_check(hperh, num)) + return ERROR; + + stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS); + exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS); + + _msg = num == CAN_RX_FIFO0 ? hperh->rx0_msg : hperh->rx1_msg; + _msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS); + + if (_msg->type == CAN_ID_STD) + _msg->std = stid; + else + _msg->ext = (stid << 18) | exid; + + _msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS); + _msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS); + _msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS); + _msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF; + _msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF; + _msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF; + _msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF; + _msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF; + _msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF; + _msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF; + _msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF; + + if (num == CAN_RX_FIFO0) { + can_rx_fifo_release(hperh, CAN_RX_FIFO0); + ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE); + CLEAR_BIT(hperh->state, CAN_STATE_RX0_MASK); + } + else { + can_rx_fifo_release(hperh, CAN_RX_FIFO1); + ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE); + CLEAR_BIT(hperh->state, CAN_STATE_RX1_MASK); + } + + if (hperh->state == CAN_STATE_READY) { + ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); + } + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh, num); + + return OK; } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c index f5a6016d23ce682b856404f17ac3b7f605913c55..e43b12c7d1a143c66e7cd4e0fcf79f1abe54c063 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c @@ -125,7 +125,7 @@ * @defgroup CMU_Private_Variables CMU Private Variables * @{ */ -uint32_t __system_clock = 24000000; +uint32_t __system_clock = 24000000U; /** * @} */ @@ -143,12 +143,12 @@ uint32_t __system_clock = 24000000; static void cmu_clock_update(uint32_t clock) { - __system_clock = clock; + __system_clock = clock; - if (clock > 1000000) - ald_tick_init(TICK_INT_PRIORITY); + if (clock > 1000000) + ald_tick_init(TICK_INT_PRIORITY); - return; + return; } /** @@ -157,69 +157,61 @@ static void cmu_clock_update(uint32_t clock) */ void ald_cmu_irq_handler(void) { - /* HOSC stop */ - if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) - { - SYSCFG_UNLOCK(); - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); - SYSCFG_LOCK(); - - if ((READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) - && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) - || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) - cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); - - ald_cmu_irq_cbk(CMU_HOSC_STOP); - } - - /* HOSC start */ - if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) - { - SYSCFG_UNLOCK(); - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK); - SYSCFG_LOCK(); - - if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) - && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))) - cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000); - - ald_cmu_irq_cbk(CMU_HOSC_START); - } - - /* LOSC stop */ - if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK)) - { - SYSCFG_UNLOCK(); - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); - SYSCFG_LOCK(); - ald_cmu_irq_cbk(CMU_LOSC_STOP); - } - - /* LOSC start */ - if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIE_MSK)) - { - SYSCFG_UNLOCK(); - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK); - SYSCFG_LOCK(); - ald_cmu_irq_cbk(CMU_LOSC_START); - } - - /* PLL1 lose */ - if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) - { - SYSCFG_UNLOCK(); - SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); - SYSCFG_LOCK(); - - if (READ_BIT(CMU->PULMCR, CMU_PULMCR_CLKS_MSK) - && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) - || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) - cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); - - ald_cmu_irq_cbk(CMU_PLL1_UNLOCK); - } - - return; + /* HOSC stop */ + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); + SYSCFG_LOCK(); + + if ((READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) + || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) + cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); + ald_cmu_irq_cbk(CMU_HOSC_STOP); + } + + /* HOSC start */ + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK); + SYSCFG_LOCK(); + + if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))) + cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000); + ald_cmu_irq_cbk(CMU_HOSC_START); + } + + /* LOSC stop */ + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); + SYSCFG_LOCK(); + ald_cmu_irq_cbk(CMU_LOSC_STOP); + } + + /* LOSC start */ + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK); + SYSCFG_LOCK(); + ald_cmu_irq_cbk(CMU_LOSC_START); + } + + /* PLL1 lose */ + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); + SYSCFG_LOCK(); + + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_CLKS_MSK) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) + || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) + cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); + ald_cmu_irq_cbk(CMU_PLL1_UNLOCK); + } + + return; } /** * @} @@ -254,30 +246,28 @@ void ald_cmu_irq_handler(void) */ ald_status_t ald_cmu_clock_config_default(void) { - uint32_t cnt = 4000, tmp; + uint32_t cnt = 4000, tmp; - SYSCFG_UNLOCK(); + SYSCFG_UNLOCK(); - /* Select HRC */ - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); + /* Select HRC */ + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) { + SYSCFG_LOCK(); + return ERROR; + } - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) - { - SYSCFG_LOCK(); - return ERROR; - } + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); /* Select 24Mhz */ - CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); /* Select 24Mhz */ + tmp = READ_REG(CMU->CLKENR); + /* Enable HRC/LRC/LOSC */ + SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK | CMU_CLKENR_LOSCEN_MSK); + WRITE_REG(CMU->CLKENR, tmp); - tmp = READ_REG(CMU->CLKENR); - /* Enable HRC/LRC/LOSC */ - SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK | CMU_CLKENR_LOSCEN_MSK); - WRITE_REG(CMU->CLKENR, tmp); - - SYSCFG_LOCK(); - return OK; + SYSCFG_LOCK(); + return OK; } /** @@ -294,161 +284,132 @@ ald_status_t ald_cmu_clock_config_default(void) */ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock) { - uint32_t cnt = 4000; - - assert_param(IS_CMU_CLOCK(clk)); - SYSCFG_UNLOCK(); - - switch (clk) - { - case CMU_CLOCK_HRC: - assert_param(clock == 24000000 || clock == 2000000); - - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); - - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) - { - SYSCFG_LOCK(); - return ERROR; - } - - if (clock == 24000000) - CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); - else - SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); - - SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); - - for (cnt = 4000; cnt; --cnt); - - cnt = 4000; - - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt)); - - cnt = 4000; - - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt)); - - cmu_clock_update(clock); - break; + uint32_t cnt = 4000; - case CMU_CLOCK_LRC: - /* Close SysTick interrupt in lower clock */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + assert_param(IS_CMU_CLOCK(clk)); + SYSCFG_UNLOCK(); - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); + switch (clk) { + case CMU_CLOCK_HRC: + assert_param(clock == 24000000 || clock == 2000000); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) - { - SYSCFG_LOCK(); - return ERROR; - } + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) { + SYSCFG_LOCK(); + return ERROR; + } - SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); + if (clock == 24000000) + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); + else + SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); - cnt = 4000; + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt)); + for (cnt = 4000; cnt; --cnt); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt)); - cnt = 4000; + cmu_clock_update(clock); + break; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); + case CMU_CLOCK_LRC: + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - cmu_clock_update(32768); - break; + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - case CMU_CLOCK_LOSC: - /* Close SysTick interrupt in lower clock */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) { + SYSCFG_LOCK(); + return ERROR; + } - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS); + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) - { - SYSCFG_LOCK(); - return ERROR; - } + cmu_clock_update(32768); + break; - SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); + case CMU_CLOCK_LOSC: + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - cnt = 4000; + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt)); + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) { + SYSCFG_LOCK(); + return ERROR; + } - cnt = 4000; + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt)); - cmu_clock_update(32768); - break; + cmu_clock_update(32768); + break; - case CMU_CLOCK_PLL1: - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS); + case CMU_CLOCK_PLL1: + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) { + SYSCFG_LOCK(); + return ERROR; + } - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) - { - SYSCFG_LOCK(); - return ERROR; - } + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); - SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); + for (cnt = 4000; cnt; --cnt); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); - for (cnt = 4000; cnt; --cnt); + cmu_clock_update(clock); + break; - cnt = 4000; + case CMU_CLOCK_HOSC: + assert_param(clock <= 24000000); - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt)); + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - cnt = 4000; + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) { + SYSCFG_LOCK(); + return ERROR; + } - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1); - cmu_clock_update(clock); - break; + for (cnt = 4000; cnt; --cnt); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); - case CMU_CLOCK_HOSC: - assert_param(clock <= 24000000); + cmu_clock_update(clock); + break; - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); + default: + break; + } - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) - { - SYSCFG_LOCK(); - return ERROR; - } - - SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); - MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1); - - for (cnt = 4000; cnt; --cnt); - - cnt = 4000; - - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); - - cnt = 4000; - - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); - - cmu_clock_update(clock); - break; - - default: - break; - } - - SYSCFG_LOCK(); - return OK; + SYSCFG_LOCK(); + return OK; } @@ -463,40 +424,35 @@ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock) */ void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) { - uint32_t cnt = 4000; - - assert_param(IS_CMU_PLL1_INPUT(input)); - assert_param(IS_CMU_PLL1_OUTPUT(output)); - - SYSCFG_UNLOCK(); - - if (input == CMU_PLL1_INPUT_HRC_6) - { - SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); - } - else if (input == CMU_PLL1_INPUT_PLL2) - { - SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); - CLEAR_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2RFS_MSK); - SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); - } - else - { - SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); - } - - MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1RFS_MSK, input << CMU_PLLCFG_PLL1RFS_POSS); - MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1OS_MSK, output << CMU_PLLCFG_PLL1OS_POS); - SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); - - while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL1LCKN_MSK)) && (--cnt)); - - cnt = 4000; - - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); - - SYSCFG_LOCK(); - return; + uint32_t cnt = 4000; + + assert_param(IS_CMU_PLL1_INPUT(input)); + assert_param(IS_CMU_PLL1_OUTPUT(output)); + + SYSCFG_UNLOCK(); + + if (input == CMU_PLL1_INPUT_HRC_6) { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); + } + else if (input == CMU_PLL1_INPUT_PLL2) { + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); + CLEAR_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2RFS_MSK); + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + } + else { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + } + + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1RFS_MSK, input << CMU_PLLCFG_PLL1RFS_POSS); + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1OS_MSK, output << CMU_PLLCFG_PLL1OS_POS); + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); + + while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL1LCKN_MSK)) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); + + SYSCFG_LOCK(); + return; } /** @@ -505,7 +461,7 @@ void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) */ uint32_t ald_cmu_get_clock(void) { - return __system_clock; + return __system_clock; } /** @@ -518,39 +474,36 @@ uint32_t ald_cmu_get_clock(void) */ int32_t ald_cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq) { - uint32_t cnt = 5000, tmp; + uint32_t cnt = 5000, tmp; - assert_param(IS_CMU_AUTO_CALIB_INPUT(input)); - assert_param(IS_CMU_AUTO_CALIB_OUTPUT(freq)); + assert_param(IS_CMU_AUTO_CALIB_INPUT(input)); + assert_param(IS_CMU_AUTO_CALIB_OUTPUT(freq)); - SYSCFG_UNLOCK(); + SYSCFG_UNLOCK(); - tmp = READ_REG(CMU->HRCACR); + tmp = READ_REG(CMU->HRCACR); - MODIFY_REG(tmp, CMU_HRCACR_AC_MSK, 1 << CMU_HRCACR_AC_POSS); - MODIFY_REG(tmp, CMU_HRCACR_RFSEL_MSK, input << CMU_HRCACR_RFSEL_POS); - MODIFY_REG(tmp, CMU_HRCACR_FREQ_MSK, freq << CMU_HRCACR_FREQ_POS); - SET_BIT(tmp, CMU_HRCACR_EN_MSK); - WRITE_REG(CMU->HRCACR, tmp); + MODIFY_REG(tmp, CMU_HRCACR_AC_MSK, 1 << CMU_HRCACR_AC_POSS); + MODIFY_REG(tmp, CMU_HRCACR_RFSEL_MSK, input << CMU_HRCACR_RFSEL_POS); + MODIFY_REG(tmp, CMU_HRCACR_FREQ_MSK, freq << CMU_HRCACR_FREQ_POS); + SET_BIT(tmp, CMU_HRCACR_EN_MSK); + WRITE_REG(CMU->HRCACR, tmp); - while (cnt--); + while (cnt--); + cnt = 30000; + while ((READ_BIT(CMU->HRCACR, CMU_HRCACR_BUSY_MSK)) && (--cnt)); - cnt = 30000; + if (READ_BITS(CMU->HRCACR, CMU_HRCACR_STA_MSK, CMU_HRCACR_STA_POSS) != 1) { + CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK); + SYSCFG_LOCK(); + return -1; + } - while ((READ_BIT(CMU->HRCACR, CMU_HRCACR_BUSY_MSK)) && (--cnt)); + SET_BIT(CMU->HRCACR, CMU_HRCACR_WRTRG_MSK); + CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK); + SYSCFG_LOCK(); - if (READ_BITS(CMU->HRCACR, CMU_HRCACR_STA_MSK, CMU_HRCACR_STA_POSS) != 1) - { - CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK); - SYSCFG_LOCK(); - return -1; - } - - SET_BIT(CMU->HRCACR, CMU_HRCACR_WRTRG_MSK); - CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK); - SYSCFG_LOCK(); - - return 0; + return 0; } /** * @} @@ -586,46 +539,43 @@ int32_t ald_cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_ou */ void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div) { - assert_param(IS_CMU_BUS(bus)); - assert_param(IS_CMU_DIV(div)); - - SYSCFG_UNLOCK(); - - switch (bus) - { - case CMU_HCLK_1: - MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS); - break; - - case CMU_SYS: - MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); - - if ((__system_clock >> div) <= 1000000) - { - /* Close SysTick interrupt in lower clock */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - } - else - { - ald_tick_init(TICK_INT_PRIORITY); - } - - break; - - case CMU_PCLK_1: - MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS); - break; - - case CMU_PCLK_2: - MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS); - break; - - default: - break; - } - - SYSCFG_LOCK(); - return; + assert_param(IS_CMU_BUS(bus)); + assert_param(IS_CMU_DIV(div)); + + SYSCFG_UNLOCK(); + + switch (bus) { + case CMU_HCLK_1: + MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS); + break; + + case CMU_SYS: + MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); + + if ((__system_clock >> div) <= 1000000) { + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + } + else { + ald_tick_init(TICK_INT_PRIORITY); + } + + break; + + case CMU_PCLK_1: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS); + break; + + case CMU_PCLK_2: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS); + break; + + default: + break; + } + + SYSCFG_LOCK(); + return; } /** @@ -634,10 +584,10 @@ void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div) */ uint32_t ald_cmu_get_hclk1_clock(void) { - uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); - uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, CMU_CFGR_HCLK1DIV_POSS); + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, CMU_CFGR_HCLK1DIV_POSS); - return (__system_clock >> sys_div) >> ahb_div; + return (__system_clock >> sys_div) >> ahb_div; } /** @@ -646,9 +596,9 @@ uint32_t ald_cmu_get_hclk1_clock(void) */ uint32_t ald_cmu_get_sys_clock(void) { - uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); - return __system_clock >> sys_div; + return __system_clock >> sys_div; } /** @@ -657,10 +607,10 @@ uint32_t ald_cmu_get_sys_clock(void) */ uint32_t ald_cmu_get_pclk1_clock(void) { - uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); - uint32_t apb1_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, CMU_CFGR_PCLK1DIV_POSS); + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t apb1_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, CMU_CFGR_PCLK1DIV_POSS); - return (__system_clock >> sys_div) >> apb1_div; + return (__system_clock >> sys_div) >> apb1_div; } /** @@ -669,10 +619,10 @@ uint32_t ald_cmu_get_pclk1_clock(void) */ uint32_t ald_cmu_get_pclk2_clock(void) { - uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); - uint32_t apb2_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, CMU_CFGR_PCLK2DIV_POSS); + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t apb2_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, CMU_CFGR_PCLK2DIV_POSS); - return (__system_clock >> sys_div) >> apb2_div; + return (__system_clock >> sys_div) >> apb2_div; } /** * @} @@ -703,31 +653,29 @@ uint32_t ald_cmu_get_pclk2_clock(void) */ void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) { - assert_param(IS_CMU_HOSC_RANGE(clock)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (status) - { - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); - MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clock << CMU_HOSMCR_FRQS_POSS); - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); - - ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); - } - else - { - CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); - CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); - - if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) - ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_CMU_HOSC_RANGE(clock)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); + MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clock << CMU_HOSMCR_FRQS_POSS); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); + } + else { + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); + + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; } /** @@ -737,28 +685,26 @@ void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) */ void ald_cmu_losc_safe_config(type_func_t status) { - assert_param(IS_FUNC_STATE(status)); - SYSCFG_UNLOCK(); - - if (status) - { - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); - - ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); - } - else - { - CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); - CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); - - if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) - ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_FUNC_STATE(status)); + SYSCFG_UNLOCK(); + + if (status) { + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); + } + else { + CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); + CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); + + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; } /** @@ -768,29 +714,46 @@ void ald_cmu_losc_safe_config(type_func_t status) */ void ald_cmu_pll_safe_config(type_func_t status) { - assert_param(IS_FUNC_STATE(status)); - SYSCFG_UNLOCK(); - - if (status) - { - SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); - MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS); - SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); - SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); - - ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); - } - else - { - CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); - CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); - - if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0) - ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_FUNC_STATE(status)); + SYSCFG_UNLOCK(); + + if (status) { + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); + MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS); + SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); + } + else { + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); + + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Get current clock source. + * @param type: Type of source: HOSC/LOSC/PLL. + * @retval Status: + * - 0: Current clock is HOSC, LOSC or PLL + * - 1: Current clock is HRC, LRC or HRC + */ +uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type) +{ + assert_param(IS_CMU_SAFE_CLOCK_TYPE(type)); + + if (type == CMU_SAFE_CLK_HOSC) + return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK, CMU_HOSMCR_CLKS_POS); + else if (type == CMU_SAFE_CLK_LOSC) + return READ_BITS(CMU->LOSMCR, CMU_LOSMCR_CLKS_MSK, CMU_LOSMCR_CLKS_POS); + else + return READ_BITS(CMU->PULMCR, CMU_PULMCR_CLKS_MSK, CMU_PULMCR_CLKS_POS); } /** @@ -800,12 +763,12 @@ void ald_cmu_pll_safe_config(type_func_t status) */ flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr) { - assert_param(IS_CMU_CLOCK_STATE(sr)); + assert_param(IS_CMU_CLOCK_STATE(sr)); - if (READ_BIT(CMU->CLKSR, sr)) - return SET; + if (READ_BIT(CMU->CLKSR, sr)) + return SET; - return RESET; + return RESET; } /** @@ -816,7 +779,7 @@ flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr) */ __weak void ald_cmu_irq_cbk(cmu_security_t se) { - return; + return; } /** * @} @@ -861,27 +824,25 @@ __weak void ald_cmu_irq_cbk(cmu_security_t se) * @retval None */ void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, - cmu_output_high_div_t div, type_func_t status) + cmu_output_high_div_t div, type_func_t status) { - assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel)); - assert_param(IS_CMU_OUTPUT_HIGH_DIV(div)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (status) - { - MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS); - MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, div << CMU_CLKOCR_HSCODIV_POSS); - SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); - } - else - { - CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel)); + assert_param(IS_CMU_OUTPUT_HIGH_DIV(div)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS); + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, div << CMU_CLKOCR_HSCODIV_POSS); + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); + } + else { + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); + } + + SYSCFG_LOCK(); + return; } /** @@ -897,23 +858,21 @@ void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, */ void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status) { - assert_param(IS_CMU_OUTPUT_LOW_SEL(sel)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (status) - { - MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS); - SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); - } - else - { - CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_CMU_OUTPUT_LOW_SEL(sel)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS); + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); + } + else { + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); + } + + SYSCFG_LOCK(); + return; } /** * @} @@ -947,24 +906,22 @@ void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t statu */ void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status) { - assert_param(IS_CMU_BUZZ_DIV(div)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (status) - { - MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS); - MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS); - SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); - } - else - { - CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_CMU_BUZZ_DIV(div)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS); + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS); + SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); + } + else { + CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); + } + + SYSCFG_LOCK(); + return; } /** @@ -986,13 +943,13 @@ void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status) */ void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock) { - assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); + assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); - SYSCFG_UNLOCK(); - MODIFY_REG(CMU->PERICR, CMU_PERICR_LPTIM0_MSK, clock << CMU_PERICR_LPTIM0_POSS); - SYSCFG_LOCK(); + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LPTIM0_MSK, clock << CMU_PERICR_LPTIM0_POSS); + SYSCFG_LOCK(); - return; + return; } /** @@ -1014,13 +971,13 @@ void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock) */ void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock) { - assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); + assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); - SYSCFG_UNLOCK(); - MODIFY_REG(CMU->PERICR, CMU_PERICR_LPUART0_MSK, clock << CMU_PERICR_LPUART0_POSS); - SYSCFG_LOCK(); + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LPUART0_MSK, clock << CMU_PERICR_LPUART0_POSS); + SYSCFG_LOCK(); - return; + return; } /** @@ -1036,13 +993,13 @@ void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock) */ void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock) { - assert_param(IS_CMU_LCD_CLOCK_SEL(clock)); + assert_param(IS_CMU_LCD_CLOCK_SEL(clock)); - SYSCFG_UNLOCK(); - MODIFY_REG(CMU->PERICR, CMU_PERICR_LCD_MSK, clock << CMU_PERICR_LCD_POSS); - SYSCFG_LOCK(); + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LCD_MSK, clock << CMU_PERICR_LCD_POSS); + SYSCFG_LOCK(); - return; + return; } /** @@ -1053,78 +1010,71 @@ void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock) */ void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status) { - uint32_t idx, pos; - - assert_param(IS_CMU_PERH(perh)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (perh == CMU_PERH_ALL) - { - if (status) - { - WRITE_REG(CMU->AHB1ENR, ~0); - WRITE_REG(CMU->APB1ENR, ~0); - WRITE_REG(CMU->APB2ENR, ~0); - } - else - { - WRITE_REG(CMU->AHB1ENR, 0); - WRITE_REG(CMU->APB1ENR, 0); - WRITE_REG(CMU->APB2ENR, 0); - } - - SYSCFG_LOCK(); - return; - } - - idx = (perh >> 27) & 0x3; - pos = perh & ~(0x3 << 27); - - if (status) - { - switch (idx) - { - case 0: - SET_BIT(CMU->AHB1ENR, pos); - break; - - case 1: - SET_BIT(CMU->APB1ENR, pos); - break; - - case 2: - SET_BIT(CMU->APB2ENR, pos); - break; - - default: - break; - } - } - else - { - switch (idx) - { - case 0: - CLEAR_BIT(CMU->AHB1ENR, pos); - break; - - case 1: - CLEAR_BIT(CMU->APB1ENR, pos); - break; - - case 2: - CLEAR_BIT(CMU->APB2ENR, pos); - break; - - default: - break; - } - } - - SYSCFG_LOCK(); - return; + uint32_t idx, pos; + + assert_param(IS_CMU_PERH(perh)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (perh == CMU_PERH_ALL) { + if (status) { + WRITE_REG(CMU->AHB1ENR, ~0); + WRITE_REG(CMU->APB1ENR, ~0); + WRITE_REG(CMU->APB2ENR, ~0); + } + else { + WRITE_REG(CMU->AHB1ENR, 0); + WRITE_REG(CMU->APB1ENR, 0); + WRITE_REG(CMU->APB2ENR, 0); + } + + SYSCFG_LOCK(); + return; + } + + idx = (perh >> 27) & 0x3; + pos = perh & ~(0x3 << 27); + + if (status) { + switch (idx) { + case 0: + SET_BIT(CMU->AHB1ENR, pos); + break; + + case 1: + SET_BIT(CMU->APB1ENR, pos); + break; + + case 2: + SET_BIT(CMU->APB2ENR, pos); + break; + + default: + break; + } + } + else { + switch (idx) { + case 0: + CLEAR_BIT(CMU->AHB1ENR, pos); + break; + + case 1: + CLEAR_BIT(CMU->APB1ENR, pos); + break; + + case 2: + CLEAR_BIT(CMU->APB2ENR, pos); + break; + + default: + break; + } + } + + SYSCFG_LOCK(); + return; } /** diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c index d49b39fe564f2522393158e2de1dbe9be88a49c3..bf6fde037c11c63e8fe3d8a6f92bb69239211e3e 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c @@ -31,8 +31,8 @@ */ void ald_crc_reset(crc_handle_t *hperh); #ifdef ALD_DMA - static void crc_dma_calculate_cplt(void *arg); - static void crc_dma_error(void *arg); +static void crc_dma_calculate_cplt(void *arg); +static void crc_dma_error(void *arg); #endif /** * @} @@ -57,38 +57,38 @@ void ald_crc_reset(crc_handle_t *hperh); */ ald_status_t ald_crc_init(crc_handle_t *hperh) { - uint32_t tmp = 0; + uint32_t tmp = 0; - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - assert_param(IS_CRC(hperh->perh)); - assert_param(IS_CRC_MODE(hperh->init.mode)); - assert_param(IS_FUNC_STATE(hperh->init.chs_rev)); - assert_param(IS_FUNC_STATE(hperh->init.data_inv)); - assert_param(IS_FUNC_STATE(hperh->init.data_rev)); - assert_param(IS_FUNC_STATE(hperh->init.chs_inv)); + assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC_MODE(hperh->init.mode)); + assert_param(IS_FUNC_STATE(hperh->init.chs_rev)); + assert_param(IS_FUNC_STATE(hperh->init.data_inv)); + assert_param(IS_FUNC_STATE(hperh->init.data_rev)); + assert_param(IS_FUNC_STATE(hperh->init.chs_inv)); - ald_crc_reset(hperh); - __LOCK(hperh); + ald_crc_reset(hperh); + __LOCK(hperh); - CRC_ENABLE(hperh); + CRC_ENABLE(hperh); - tmp = hperh->perh->CR; + tmp = hperh->perh->CR; - tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) | - (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) | - (CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) | - (0 << CRC_CR_BYTORD_POS)); + tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) | + (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) | + (CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) | + (0 << CRC_CR_BYTORD_POS)); - hperh->perh->CR = tmp; - hperh->perh->SEED = hperh->init.seed; - CRC_RESET(hperh); + hperh->perh->CR = tmp; + hperh->perh->SEED = hperh->init.seed; + CRC_RESET(hperh); - hperh->state = CRC_STATE_READY; + hperh->state = CRC_STATE_READY; - __UNLOCK(hperh); - return OK; + __UNLOCK(hperh); + return OK; } /** @@ -110,26 +110,26 @@ ald_status_t ald_crc_init(crc_handle_t *hperh) */ uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) { - uint32_t i; - uint32_t ret; + uint32_t i; + uint32_t ret; - assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC(hperh->perh)); - if (buf == NULL || size == 0) - return 0; + if (buf == NULL || size == 0) + return 0; - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; - for (i = 0; i < size; i++) - *((volatile uint8_t *) & (hperh->perh->DATA)) = buf[i]; + for (i = 0; i < size; i++) + *((volatile uint8_t *)&(hperh->perh->DATA)) = buf[i]; - ret = CRC->CHECKSUM; - hperh->state = CRC_STATE_READY; - __UNLOCK(hperh); + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); - return ret; + return ret; } /** @@ -142,26 +142,26 @@ uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) */ uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size) { - uint32_t i; - uint32_t ret; + uint32_t i; + uint32_t ret; - assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC(hperh->perh)); - if (buf == NULL || size == 0) - return 0; + if (buf == NULL || size == 0) + return 0; - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; - for (i = 0; i < size; i++) - *((volatile uint16_t *) & (hperh->perh->DATA)) = buf[i]; + for (i = 0; i < size; i++) + *((volatile uint16_t *)&(hperh->perh->DATA)) = buf[i]; - ret = CRC->CHECKSUM; - hperh->state = CRC_STATE_READY; - __UNLOCK(hperh); + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); - return ret; + return ret; } /** @@ -174,26 +174,26 @@ uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t */ uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size) { - uint32_t i; - uint32_t ret; + uint32_t i; + uint32_t ret; - assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC(hperh->perh)); - if (buf == NULL || size == 0) - return 0; + if (buf == NULL || size == 0) + return 0; - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; - for (i = 0; i < size; i++) - CRC->DATA = buf[i]; + for (i = 0; i < size; i++) + CRC->DATA = buf[i]; - ret = CRC->CHECKSUM; - hperh->state = CRC_STATE_READY; - __UNLOCK(hperh); + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); - return ret; + return ret; } /** @@ -218,44 +218,44 @@ uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t siz */ ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel) { - if (hperh->state != CRC_STATE_READY) - return BUSY; + if (hperh->state != CRC_STATE_READY) + return BUSY; - if (buf == NULL || size == 0) - return ERROR; + if (buf == NULL || size == 0) + return ERROR; - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; + hperh->state = CRC_STATE_BUSY; - hperh->cal_buf = buf; - hperh->cal_res = res; + hperh->cal_buf = buf; + hperh->cal_res = res; - if (hperh->hdma.perh == NULL) - hperh->hdma.perh = DMA0; + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; - hperh->hdma.cplt_arg = (void *)hperh; - hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; - hperh->hdma.err_arg = (void *)hperh; - hperh->hdma.err_cbk = &crc_dma_error; + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; - ald_dma_config_struct(&(hperh->hdma.config)); - hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdma.config.src = (void *)buf; - hperh->hdma.config.dst = (void *)&hperh->perh->DATA; - hperh->hdma.config.size = size; - hperh->hdma.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.msel = DMA_MSEL_CRC; - hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; - hperh->hdma.config.channel = channel; - ald_dma_config_basic(&(hperh->hdma)); + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); - __UNLOCK(hperh); - CRC_DMA_ENABLE(hperh); + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); - return OK; + return OK; } /** @@ -270,44 +270,44 @@ ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_ */ ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel) { - if (hperh->state != CRC_STATE_READY) - return BUSY; + if (hperh->state != CRC_STATE_READY) + return BUSY; - if (buf == NULL || size == 0) - return ERROR; + if (buf == NULL || size == 0) + return ERROR; - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; + hperh->state = CRC_STATE_BUSY; - hperh->cal_buf = (uint8_t *)buf; - hperh->cal_res = res; + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; - if (hperh->hdma.perh == NULL) - hperh->hdma.perh = DMA0; + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; - hperh->hdma.cplt_arg = (void *)hperh; - hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; - hperh->hdma.err_arg = (void *)hperh; - hperh->hdma.err_cbk = &crc_dma_error; + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; - ald_dma_config_struct(&(hperh->hdma.config)); - hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma.config.src = (void *)buf; - hperh->hdma.config.dst = (void *)&hperh->perh->DATA; - hperh->hdma.config.size = size; - hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.msel = DMA_MSEL_CRC; - hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; - hperh->hdma.config.channel = channel; - ald_dma_config_basic(&(hperh->hdma)); + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); - __UNLOCK(hperh); - CRC_DMA_ENABLE(hperh); + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); - return OK; + return OK; } /** @@ -322,44 +322,44 @@ ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *bu */ ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel) { - if (hperh->state != CRC_STATE_READY) - return BUSY; + if (hperh->state != CRC_STATE_READY) + return BUSY; - if (buf == NULL || size == 0) - return ERROR; + if (buf == NULL || size == 0) + return ERROR; - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; + hperh->state = CRC_STATE_BUSY; - hperh->cal_buf = (uint8_t *)buf; - hperh->cal_res = res; + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; - if (hperh->hdma.perh == NULL) - hperh->hdma.perh = DMA0; + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; - hperh->hdma.cplt_arg = (void *)hperh; - hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; - hperh->hdma.err_arg = (void *)hperh; - hperh->hdma.err_cbk = &crc_dma_error; + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; - ald_dma_config_struct(&(hperh->hdma.config)); - hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma.config.src = (void *)buf; - hperh->hdma.config.dst = (void *)&hperh->perh->DATA; - hperh->hdma.config.size = size; - hperh->hdma.config.src_inc = DMA_DATA_INC_WORD; - hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.msel = DMA_MSEL_CRC; - hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; - hperh->hdma.config.channel = channel; - ald_dma_config_basic(&(hperh->hdma)); + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); - __UNLOCK(hperh); - CRC_DMA_ENABLE(hperh); + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); - return OK; + return OK; } @@ -371,11 +371,11 @@ ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, u */ ald_status_t ald_crc_dma_pause(crc_handle_t *hperh) { - __LOCK(hperh); - CRC_DMA_DISABLE(hperh); - __UNLOCK(hperh); + __LOCK(hperh); + CRC_DMA_DISABLE(hperh); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -386,11 +386,11 @@ ald_status_t ald_crc_dma_pause(crc_handle_t *hperh) */ ald_status_t ald_crc_dma_resume(crc_handle_t *hperh) { - __LOCK(hperh); - CRC_DMA_ENABLE(hperh); - __UNLOCK(hperh); + __LOCK(hperh); + CRC_DMA_ENABLE(hperh); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -401,12 +401,12 @@ ald_status_t ald_crc_dma_resume(crc_handle_t *hperh) */ ald_status_t ald_crc_dma_stop(crc_handle_t *hperh) { - __LOCK(hperh); - CRC_DMA_DISABLE(hperh); - __UNLOCK(hperh); + __LOCK(hperh); + CRC_DMA_DISABLE(hperh); + __UNLOCK(hperh); - hperh->state = CRC_STATE_READY; - return OK; + hperh->state = CRC_STATE_READY; + return OK; } /** @@ -427,9 +427,9 @@ ald_status_t ald_crc_dma_stop(crc_handle_t *hperh) */ crc_state_t ald_crc_get_state(crc_handle_t *hperh) { - assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC(hperh->perh)); - return hperh->state; + return hperh->state; } /** * @} @@ -452,13 +452,13 @@ crc_state_t ald_crc_get_state(crc_handle_t *hperh) */ void ald_crc_reset(crc_handle_t *hperh) { - hperh->perh->DATA = 0x0; - hperh->perh->CR = 0x2; - hperh->perh->SEED = 0xFFFFFFFF; + hperh->perh->DATA = 0x0; + hperh->perh->CR = 0x2; + hperh->perh->SEED = 0xFFFFFFFF; - hperh->state = CRC_STATE_READY; - __UNLOCK(hperh); - return; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + return; } #ifdef ALD_DMA @@ -470,15 +470,15 @@ void ald_crc_reset(crc_handle_t *hperh) */ static void crc_dma_calculate_cplt(void *arg) { - crc_handle_t *hperh = (crc_handle_t *)arg; + crc_handle_t *hperh = (crc_handle_t *)arg; - *(hperh->cal_res) = CRC->CHECKSUM; - CRC_DMA_DISABLE(hperh); + *(hperh->cal_res) = CRC->CHECKSUM; + CRC_DMA_DISABLE(hperh); - hperh->state = CRC_STATE_READY; + hperh->state = CRC_STATE_READY; - if (hperh->cal_cplt_cbk) - hperh->cal_cplt_cbk(hperh); + if (hperh->cal_cplt_cbk) + hperh->cal_cplt_cbk(hperh); } /** @@ -489,15 +489,15 @@ static void crc_dma_calculate_cplt(void *arg) */ static void crc_dma_error(void *arg) { - crc_handle_t *hperh = (crc_handle_t *)arg; + crc_handle_t *hperh = (crc_handle_t *)arg; - CRC_CLEAR_ERROR_FLAG(hperh); - CRC_DMA_DISABLE(hperh); + CRC_CLEAR_ERROR_FLAG(hperh); + CRC_DMA_DISABLE(hperh); - hperh->state = CRC_STATE_READY; + hperh->state = CRC_STATE_READY; - if (hperh->err_cplt_cbk) - hperh->err_cplt_cbk(hperh); + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); } #endif /** diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c index 30d7f1e3ef8e6d1aed5f9e25f2ed997384684955..ff8f92d9d53fbfe537bc677a23b259573019294a 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c @@ -34,8 +34,8 @@ */ void crypt_reset(crypt_handle_t *hperh); #ifdef ALD_DMA - static void crypt_dma_crypt_cplt(void *arg); - static void crypt_dma_error(void *arg); +static void crypt_dma_crypt_cplt(void *arg); +static void crypt_dma_error(void *arg); #endif /** * @} @@ -60,29 +60,29 @@ void crypt_reset(crypt_handle_t *hperh); */ ald_status_t ald_crypt_init(crypt_handle_t *hperh) { - uint32_t tmp = 0; + uint32_t tmp = 0; - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - assert_param(IS_CRYPT(hperh->perh)); - assert_param(IS_CRYPT_MODE(hperh->init.mode)); + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_MODE(hperh->init.mode)); - __LOCK(hperh); - crypt_reset(hperh); + __LOCK(hperh); + crypt_reset(hperh); - if (hperh->state == CRYPT_STATE_RESET) - __UNLOCK(hperh); + if (hperh->state == CRYPT_STATE_RESET) + __UNLOCK(hperh); - tmp = hperh->perh->CON; - hperh->step = 4; - tmp |= ((1 << CRYPT_CON_FIFOODR_POS) | (hperh->init.mode << CRYPT_CON_MODE_POSS) | \ - (hperh->init.type << CRYPT_CON_TYPE_POSS) | (1 << CRYPT_CON_FIFOEN_POS)); - WRITE_REG(hperh->perh->CON, tmp); - hperh->state = CRYPT_STATE_READY; - __UNLOCK(hperh); + tmp = hperh->perh->CON; + hperh->step = 4; + tmp |= ((1 << CRYPT_CON_FIFOODR_POS) | (hperh->init.mode << CRYPT_CON_MODE_POSS) | \ + (hperh->init.type << CRYPT_CON_TYPE_POSS) | (1 << CRYPT_CON_FIFOEN_POS)); + WRITE_REG(hperh->perh->CON, tmp); + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -94,26 +94,25 @@ ald_status_t ald_crypt_init(crypt_handle_t *hperh) */ ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key) { - uint32_t *temp = key; - uint32_t i; + uint32_t *temp = key; + uint32_t i; - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; + if ((hperh == NULL) || (key == NULL)) + return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; - if ((hperh == NULL) || (key == NULL)) - return ERROR; + assert_param(IS_CRYPT(hperh->perh)); - assert_param(IS_CRYPT(hperh->perh)); + hperh->perh->KEY[3] = *temp++; + hperh->perh->KEY[2] = *temp++; + hperh->perh->KEY[1] = *temp++; + hperh->perh->KEY[0] = *temp; - hperh->perh->KEY[3] = *temp++; - hperh->perh->KEY[2] = *temp++; - hperh->perh->KEY[1] = *temp++; - hperh->perh->KEY[0] = *temp; + for (i = 0; i < 4; i++) + hperh->key[i] = *key++; - for (i = 0; i < 4; i++) - hperh->key[i] = *key++; - - return OK; + return OK; } /** @@ -125,22 +124,21 @@ ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key) */ ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t *key) { - uint32_t *temp = key; - - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; + uint32_t *temp = key; - if ((hperh == NULL) || (key == NULL)) - return ERROR; + if ((hperh == NULL) || (key == NULL)) + return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; - assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT(hperh->perh)); - *temp++ = hperh->perh->KEY[3]; - *temp++ = hperh->perh->KEY[2]; - *temp++ = hperh->perh->KEY[1]; - *temp = hperh->perh->KEY[0]; + *temp++ = hperh->perh->KEY[3]; + *temp++ = hperh->perh->KEY[2]; + *temp++ = hperh->perh->KEY[1]; + *temp = hperh->perh->KEY[0]; - return OK; + return OK; } /** @@ -152,27 +150,26 @@ ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t *key) */ ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv) { - uint32_t *temp = iv; - uint32_t i; + uint32_t *temp = iv; + uint32_t i; - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; + if ((hperh == NULL) || (iv == NULL)) + return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; - if ((hperh == NULL) || (iv == NULL)) - return ERROR; + assert_param(IS_CRYPT(hperh->perh)); - assert_param(IS_CRYPT(hperh->perh)); + hperh->perh->IV[3] = *temp++; + hperh->perh->IV[2] = *temp++; + hperh->perh->IV[1] = *temp++; + hperh->perh->IV[0] = *temp; - hperh->perh->IV[3] = *temp++; - hperh->perh->IV[2] = *temp++; - hperh->perh->IV[1] = *temp++; - hperh->perh->IV[0] = *temp; + for (i = 0; i < 4; i++) + hperh->iv[i] = *iv++; - for (i = 0; i < 4; i++) - hperh->iv[i] = *iv++; - - CRYPT_IVEN_ENABLE(hperh); - return OK; + CRYPT_IVEN_ENABLE(hperh); + return OK; } /** @@ -184,22 +181,21 @@ ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv) */ ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv) { - uint32_t *temp = iv; - - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; + uint32_t *temp = iv; - if ((hperh == NULL) || (iv == NULL)) - return ERROR; + if ((hperh == NULL) || (iv == NULL)) + return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; - assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT(hperh->perh)); - *temp++ = hperh->perh->IV[3]; - *temp++ = hperh->perh->IV[2]; - *temp++ = hperh->perh->IV[1]; - *temp = hperh->perh->IV[0]; + *temp++ = hperh->perh->IV[3]; + *temp++ = hperh->perh->IV[2]; + *temp++ = hperh->perh->IV[1]; + *temp = hperh->perh->IV[0]; - return OK; + return OK; } /** @@ -223,45 +219,42 @@ ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv) */ ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) { - uint32_t count = 0; - uint32_t i; - uint32_t *plain_buf = (uint32_t *)plain_text; - uint32_t *cipher_buf = (uint32_t *)cipher_text; + uint32_t count = 0; + uint32_t i; + uint32_t *plain_buf = (uint32_t *)plain_text; + uint32_t *cipher_buf = (uint32_t *)cipher_text; - if (hperh->state != CRYPT_STATE_READY) - return ERROR; + if (hperh->state != CRYPT_STATE_READY) + return ERROR; - if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) - return ERROR; + if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) + return ERROR; - assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT(hperh->perh)); - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); - count = size / (4 * hperh->step); + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + count = size / (4 * hperh->step); - while (count--) - { - for (i = 0; i < hperh->step; i++) - { - CRYPT_WRITE_FIFO(hperh, *plain_buf); - plain_buf++; - } + while (count--) { + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *plain_buf); + plain_buf++; + } - while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); + while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); - for (i = 0; i < hperh->step; i++) - { - *cipher_buf = CRYPT_READ_FIFO(hperh); - cipher_buf++; - } - } + for (i = 0; i < hperh->step; i++) { + *cipher_buf = CRYPT_READ_FIFO(hperh); + cipher_buf++; + } + } - hperh->state = CRYPT_STATE_READY; - __UNLOCK(hperh); + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -276,75 +269,71 @@ ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8 */ ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) { - uint32_t count = 0; - uint32_t i; - uint32_t *plain_buf = (uint32_t *)plain_text; - uint32_t *cipher_buf = (uint32_t *)cipher_text; - - if (hperh->init.mode == CRYPT_MODE_CTR) - { - return ald_crypt_encrypt(hperh, cipher_text, plain_text, size); - } - - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) - return ERROR; - - assert_param(IS_CRYPT(hperh->perh)); - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - CRYPT_SETDIR(hperh, CRYPT_DECRYPT); - count = size / (4 * hperh->step); - - while (count--) - { - for (i = 0; i < hperh->step; i++) - { - CRYPT_WRITE_FIFO(hperh, *cipher_buf); - cipher_buf++; - } - - while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); - - for (i = 0; i < hperh->step; i++) - { - *plain_buf = CRYPT_READ_FIFO(hperh); - plain_buf++; - } - } - - hperh->state = CRYPT_STATE_READY; - __UNLOCK(hperh); - - return OK; + uint32_t count = 0; + uint32_t i; + uint32_t *plain_buf = (uint32_t*)plain_text; + uint32_t *cipher_buf = (uint32_t*)cipher_text; + + if (hperh->init.mode == CRYPT_MODE_CTR) { + return ald_crypt_encrypt(hperh, cipher_text, plain_text, size); + } + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + count = size / (4 * hperh->step); + + while (count--) { + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *cipher_buf); + cipher_buf++; + } + + while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); + + for (i = 0; i < hperh->step; i++) { + *plain_buf = CRYPT_READ_FIFO(hperh); + plain_buf++; + } + } + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); + + return OK; } void gcm_mul(uint32_t *res, uint32_t *data, uint32_t *iv) { - CRYPT->CON = 0; - CRYPT->DATA[0] = data[3]; - CRYPT->DATA[1] = data[2]; - CRYPT->DATA[2] = data[1]; - CRYPT->DATA[3] = data[0]; - CRYPT->IV[0] = iv[3]; - CRYPT->IV[1] = iv[2]; - CRYPT->IV[2] = iv[1]; - CRYPT->IV[3] = iv[0]; - CRYPT->CON |= ((1 << CRYPT_CON_RESCLR_POS) | (3 << CRYPT_CON_MODE_POSS) | \ - (1 << CRYPT_CON_GO_POS)); - - while (READ_BIT(CRYPT->IF, CRYPT_IF_MULTHIF_MSK) == 0); - - res[3] = CRYPT->RES[0]; - res[2] = CRYPT->RES[1]; - res[1] = CRYPT->RES[2]; - res[0] = CRYPT->RES[3]; - - WRITE_REG(CRYPT->IFC, CRYPT_IFC_MULTHIFC_MSK); - return; + CRYPT->CON = 0; + CRYPT->DATA[0] = data[3]; + CRYPT->DATA[1] = data[2]; + CRYPT->DATA[2] = data[1]; + CRYPT->DATA[3] = data[0]; + CRYPT->IV[0] = iv[3]; + CRYPT->IV[1] = iv[2]; + CRYPT->IV[2] = iv[1]; + CRYPT->IV[3] = iv[0]; + CRYPT->CON |= ((1 << CRYPT_CON_RESCLR_POS) | (3 << CRYPT_CON_MODE_POSS) | \ + (1 << CRYPT_CON_GO_POS)); + + while (READ_BIT(CRYPT->IF, CRYPT_IF_MULTHIF_MSK) == 0); + + res[3] = CRYPT->RES[0]; + res[2] = CRYPT->RES[1]; + res[1] = CRYPT->RES[2]; + res[0] = CRYPT->RES[3]; + + WRITE_REG(CRYPT->IFC, CRYPT_IFC_MULTHIFC_MSK); + return; } /** @@ -360,114 +349,90 @@ void gcm_mul(uint32_t *res, uint32_t *data, uint32_t *iv) */ ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag) { - uint8_t GCM_HASH_in[0x60] = {0}; - uint8_t ecb[16] = {0}; - uint32_t x_temp[4]; - uint64_t u, v; - uint32_t len = 0; - uint32_t j, i, k; - uint32_t *tag_temp, *cipher_text_temp; - - /* calculate u and v */ - u = 128 * ((size % 16) ? (size / 16 + 1) : size / 16) - size * 8; - v = 128 * ((alen % 16) ? (alen / 16 + 1) : alen / 16) - alen * 8; - - /* get the input of GHASH algorithm,the input:A||0^v||C||0^u||[len(A)]_64||[len(C)]_64 */ - for (i = 0; i < alen; i++) - { - GCM_HASH_in [i] = * (aadata + i); - } - - len += alen; - - for (i = 0; i < v / 8; i++) - { - GCM_HASH_in[i + len] = 0; - } - - len += v / 8; - - for (i = 0; i < size; i++) - { - GCM_HASH_in[i + len] = * (cipher_text + i); - } - - len += size; - - for (i = 0; i < u / 8; i++) - { - GCM_HASH_in[i + len] = 0; - } - - len += u / 8; - - for (i = 0; i < 4; i++) - { - GCM_HASH_in[i + len] = 0; - } - - len += 4; - - for (i = 0; i < 4; i++) - { - GCM_HASH_in[i + len] = ((alen * 8) >> (8 * i)) & 0xFF; - } - - len += 4; - - for (i = 0; i < 4; i++) - { - GCM_HASH_in[i + len] = 0; - } - - len += 4; - - for (i = 0; i < 4; i++) - { - GCM_HASH_in[i + len] = ((size * 8) >> (8 * i)) & 0xFF; - } - - len += 4; - - CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS); - CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS); - - ald_crypt_encrypt(hperh, ecb, ecb, 16); - - k = len / 16; - - for (i = 0; i < 16; i++) - { - tag[i] = 0; - } - - cipher_text_temp = (uint32_t *)GCM_HASH_in; - tag_temp = (uint32_t *)tag; - - for (i = 0; i < k; i++) - { - for (j = 0; j < 4; j++) - { - x_temp[j] = (*cipher_text_temp) ^ tag_temp[j]; - ++cipher_text_temp; - } - - gcm_mul((uint32_t *)tag_temp, x_temp, (uint32_t *)ecb); - } - - /* calculate the authentication tag T, - * T = CIPH_K(J0)^S,J0=IV||0^31||1,CIPH_K is the algorithm of AES in ECB mode - */ - tag_temp = (uint32_t *)tag; - ald_crypt_init(hperh); - CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS); - CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS); - ald_crypt_write_key(hperh, hperh->key); - hperh->iv[3] = 1; - ald_crypt_write_ivr(hperh, hperh->iv); - ald_crypt_encrypt(hperh, tag, tag, 16); - - return OK; + uint8_t GCM_HASH_in[0x60] = {0}; + uint8_t ecb[16] = {0}; + uint32_t x_temp[4]; + uint64_t u, v; + uint32_t len = 0; + uint32_t j, i, k; + uint32_t *tag_temp, *cipher_text_temp; + + /* calculate u and v */ + u = 128 * ((size % 16) ? (size / 16 + 1) : size / 16) - size * 8; + v = 128 * ((alen % 16) ? (alen / 16 + 1): alen / 16) - alen * 8; + + /* get the input of GHASH algorithm,the input:A||0^v||C||0^u||[len(A)]_64||[len(C)]_64 */ + for (i = 0; i < alen; i++) { + GCM_HASH_in [i] = * (aadata + i); + } + len += alen; + for (i = 0; i < v / 8; i++) { + GCM_HASH_in[i + len] = 0; + } + len += v / 8; + for (i = 0; i < size; i++) { + GCM_HASH_in[i + len] = * (cipher_text + i); + } + len += size; + for (i = 0; i < u / 8; i++) { + GCM_HASH_in[i + len] = 0; + } + len += u / 8; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = 0; + } + len += 4; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = ((alen * 8) >> (8 * i)) & 0xFF; + } + len += 4; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = 0; + } + len += 4; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = ((size * 8) >> (8 * i)) & 0xFF; + } + len += 4; + + CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS); + CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS); + + ald_crypt_encrypt(hperh, ecb, ecb, 16); + + k = len / 16; + for (i = 0; i < 16; i++) { + tag[i] = 0; + } + + cipher_text_temp = (uint32_t *)GCM_HASH_in; + tag_temp = (uint32_t *)tag; + for (i = 0; i < k; i++) { + for (j = 0; j < 4; j++) { + x_temp[j] = (*cipher_text_temp) ^ tag_temp[j]; + ++cipher_text_temp; + } + + gcm_mul((uint32_t *)tag_temp, x_temp, (uint32_t *)ecb); + } + + /* calculate the authentication tag T, + * T = CIPH_K(J0)^S,J0=IV||0^31||1,CIPH_K is the algorithm of AES in ECB mode + */ + tag_temp = (uint32_t *)tag; + ald_crypt_init(hperh); + CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS); + CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS); + ald_crypt_write_key(hperh, hperh->key); + hperh->iv[3] = 1; + ald_crypt_write_ivr(hperh, hperh->iv); + ald_crypt_encrypt(hperh, tag, tag, 16); + + return OK; } /** @@ -480,36 +445,35 @@ ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, u * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) +ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t *cipher_text, uint32_t size) { - uint32_t i; - uint32_t *plain_buf = (uint32_t *)plain_text; - - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) - return ERROR; - - assert_param(IS_CRYPT(hperh->perh)); - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); - hperh->count = hperh->step; - hperh->plain_text = plain_text; - hperh->cipher_text = cipher_text; - hperh->size = size; - ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); - - for (i = 0; i < hperh->step; i++) - { - CRYPT_WRITE_FIFO(hperh, *plain_buf); - ++plain_buf; - } - - __UNLOCK(hperh); - return OK; + uint32_t i; + uint32_t *plain_buf = (uint32_t *)plain_text; + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + hperh->count = hperh->step; + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); + + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *plain_buf); + ++plain_buf; + } + + __UNLOCK(hperh); + return OK; } /** @@ -524,39 +488,37 @@ ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, */ ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) { - uint32_t i; - uint32_t *cipher_buf = (uint32_t *)cipher_text; - - if (hperh->init.mode == CRYPT_MODE_CTR) - { - return ald_crypt_decrypt_by_it(hperh, cipher_text, plain_text, size); - } - - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) - return ERROR; - - assert_param(IS_CRYPT(hperh->perh)); - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - CRYPT_SETDIR(hperh, CRYPT_DECRYPT); - hperh->count = hperh->step; - hperh->plain_text = plain_text; - hperh->cipher_text = cipher_text; - hperh->size = size; - ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); - - for (i = 0; i < hperh->step; i++) - { - CRYPT_WRITE_FIFO(hperh, *cipher_buf); - cipher_buf++; - } - - __UNLOCK(hperh); - return OK; + uint32_t i; + uint32_t *cipher_buf = (uint32_t*)cipher_text; + + if (hperh->init.mode == CRYPT_MODE_CTR) { + return ald_crypt_decrypt_by_it(hperh, cipher_text, plain_text, size); + } + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + hperh->count = hperh->step; + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); + + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *cipher_buf); + cipher_buf++; + } + + __UNLOCK(hperh); + return OK; } #ifdef ALD_DMA @@ -572,71 +534,70 @@ ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, - uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) +ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t * plain_text, + uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) { - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if (plain_text == NULL || cipher_text == NULL || size == 0) - return ERROR; - - assert_param(IS_CRYPT(hperh->perh)); - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - - hperh->plain_text = plain_text; - hperh->cipher_text = cipher_text; - hperh->size = size; - hperh->count = size; - - if (hperh->hdma_m2p.perh == NULL) - hperh->hdma_m2p.perh = DMA0; - - if (hperh->hdma_p2m.perh == NULL) - hperh->hdma_p2m.perh = DMA0; - - hperh->hdma_m2p.cplt_arg = NULL; - hperh->hdma_m2p.cplt_cbk = NULL; - hperh->hdma_m2p.err_arg = NULL; - hperh->hdma_m2p.err_cbk = NULL; - - hperh->hdma_p2m.cplt_arg = (void *)hperh; - hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; - hperh->hdma_p2m.err_arg = (void *)hperh; - hperh->hdma_p2m.err_cbk = &crypt_dma_error; - - CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); - - ald_dma_config_struct(&hperh->hdma_m2p.config); - hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma_m2p.config.src = (void *)hperh->plain_text; - hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; - hperh->hdma_m2p.config.size = size / 4; - hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; - hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; - hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; - hperh->hdma_m2p.config.channel = channel_m2p; - ald_dma_config_basic(&(hperh->hdma_m2p)); - - ald_dma_config_struct(&hperh->hdma_p2m.config); - hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; - hperh->hdma_p2m.config.dst = (void *)hperh->cipher_text; - hperh->hdma_p2m.config.size = size / 4; - hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; - hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; - hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; - hperh->hdma_p2m.config.channel = channel_p2m; - ald_dma_config_basic(&(hperh->hdma_p2m)); - - CRYPT_DMA_ENABLE(hperh); - __UNLOCK(hperh); - - return OK; + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if (plain_text == NULL || cipher_text == NULL || size == 0) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + hperh->count = size; + + if (hperh->hdma_m2p.perh == NULL) + hperh->hdma_m2p.perh = DMA0; + if (hperh->hdma_p2m.perh == NULL) + hperh->hdma_p2m.perh = DMA0; + + hperh->hdma_m2p.cplt_arg = NULL; + hperh->hdma_m2p.cplt_cbk = NULL; + hperh->hdma_m2p.err_arg = NULL; + hperh->hdma_m2p.err_cbk = NULL; + + hperh->hdma_p2m.cplt_arg = (void *)hperh; + hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; + hperh->hdma_p2m.err_arg = (void *)hperh; + hperh->hdma_p2m.err_cbk = &crypt_dma_error; + + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + + ald_dma_config_struct(&hperh->hdma_m2p.config); + hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_m2p.config.src = (void *)hperh->plain_text; + hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; + hperh->hdma_m2p.config.size = size / 4; + hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; + hperh->hdma_m2p.config.channel = channel_m2p; + ald_dma_config_basic(&(hperh->hdma_m2p)); + + ald_dma_config_struct(&hperh->hdma_p2m.config); + hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; + hperh->hdma_p2m.config.dst = (void *)hperh->cipher_text; + hperh->hdma_p2m.config.size = size / 4; + hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; + hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; + hperh->hdma_p2m.config.channel = channel_p2m; + ald_dma_config_basic(&(hperh->hdma_p2m)); + + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; } /** @@ -651,73 +612,71 @@ ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, - uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) +ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t * cipher_text, + uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) { - if (hperh->init.mode == CRYPT_MODE_CTR) - return ald_crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m); - - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if (plain_text == NULL || cipher_text == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - - hperh->plain_text = plain_text; - hperh->cipher_text = cipher_text; - hperh->size = size; - hperh->count = size; - - if (hperh->hdma_m2p.perh == NULL) - hperh->hdma_m2p.perh = DMA0; - - if (hperh->hdma_p2m.perh == NULL) - hperh->hdma_p2m.perh = DMA0; - - - hperh->hdma_m2p.cplt_arg = NULL; - hperh->hdma_m2p.cplt_cbk = NULL; - hperh->hdma_m2p.err_arg = NULL; - hperh->hdma_m2p.err_cbk = NULL; - - hperh->hdma_p2m.cplt_arg = (void *)hperh; - hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; - hperh->hdma_p2m.err_arg = (void *)hperh; - hperh->hdma_p2m.err_cbk = &crypt_dma_error; - - CRYPT_SETDIR(hperh, CRYPT_DECRYPT); - - ald_dma_config_struct(&hperh->hdma_m2p.config); - hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma_m2p.config.src = (void *)hperh->cipher_text; - hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; - hperh->hdma_m2p.config.size = size / 4; - hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; - hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; - hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; - hperh->hdma_m2p.config.channel = channel_m2p; - ald_dma_config_basic(&(hperh->hdma_m2p)); - - ald_dma_config_struct(&hperh->hdma_p2m.config); - hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; - hperh->hdma_p2m.config.dst = (void *)hperh->plain_text; - hperh->hdma_p2m.config.size = size / 4; - hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; - hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; - hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; - hperh->hdma_p2m.config.channel = channel_p2m; - ald_dma_config_basic(&(hperh->hdma_p2m)); - - CRYPT_DMA_ENABLE(hperh); - __UNLOCK(hperh); - - return OK; + if (hperh->init.mode == CRYPT_MODE_CTR) + return ald_crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m); + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + if (plain_text == NULL || cipher_text == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + hperh->count = size; + + if (hperh->hdma_m2p.perh == NULL) + hperh->hdma_m2p.perh = DMA0; + if (hperh->hdma_p2m.perh == NULL) + hperh->hdma_p2m.perh = DMA0; + + + hperh->hdma_m2p.cplt_arg = NULL; + hperh->hdma_m2p.cplt_cbk = NULL; + hperh->hdma_m2p.err_arg = NULL; + hperh->hdma_m2p.err_cbk = NULL; + + hperh->hdma_p2m.cplt_arg = (void *)hperh; + hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; + hperh->hdma_p2m.err_arg = (void *)hperh; + hperh->hdma_p2m.err_cbk = &crypt_dma_error; + + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + + ald_dma_config_struct(&hperh->hdma_m2p.config); + hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_m2p.config.src = (void *)hperh->cipher_text; + hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; + hperh->hdma_m2p.config.size = size / 4; + hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; + hperh->hdma_m2p.config.channel = channel_m2p; + ald_dma_config_basic(&(hperh->hdma_m2p)); + + ald_dma_config_struct(&hperh->hdma_p2m.config); + hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; + hperh->hdma_p2m.config.dst = (void *)hperh->plain_text; + hperh->hdma_p2m.config.size = size / 4; + hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; + hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; + hperh->hdma_p2m.config.channel = channel_p2m; + ald_dma_config_basic(&(hperh->hdma_p2m)); + + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; } /** @@ -737,11 +696,11 @@ ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_tex */ ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh) { - __LOCK(hperh); - CRYPT_DMA_DISABLE(hperh); - __UNLOCK(hperh); + __LOCK(hperh); + CRYPT_DMA_DISABLE(hperh); + __UNLOCK(hperh); - return OK; + return OK; } @@ -753,11 +712,11 @@ ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh) */ ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh) { - __LOCK(hperh); - CRYPT_DMA_ENABLE(hperh); - __UNLOCK(hperh); + __LOCK(hperh); + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -768,12 +727,12 @@ ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh) */ ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh) { - __LOCK(hperh); - CRYPT_DMA_DISABLE(hperh); - __UNLOCK(hperh); + __LOCK(hperh); + CRYPT_DMA_DISABLE(hperh); + __UNLOCK(hperh); - hperh->state = CRYPT_STATE_READY; - return OK; + hperh->state = CRYPT_STATE_READY; + return OK; } #endif @@ -785,46 +744,39 @@ ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh) */ void ald_crypt_irq_handler(crypt_handle_t *hperh) { - uint32_t i; - uint32_t *in_buf; - uint32_t *out_buf; - - if (READ_BIT(hperh->perh->CON, CRYPT_CON_ENCS_MSK)) - { - in_buf = (uint32_t *)hperh->plain_text + hperh->count; - out_buf = (uint32_t *)hperh->cipher_text + hperh->count - hperh->step; - } - else - { - in_buf = (uint32_t *)hperh->cipher_text + hperh->count; - out_buf = (uint32_t *)hperh->plain_text + hperh->count - hperh->step; - } - - if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) - { - ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF); - } - - for (i = 0; i < hperh->step; i++) - *out_buf++ = CRYPT_READ_FIFO(hperh); - - hperh->count += hperh->step; - - if (hperh->count > (hperh->size / 4)) - { - hperh->count = 0; - hperh->state = CRYPT_STATE_READY; - - if (hperh->crypt_cplt_cbk) - hperh->crypt_cplt_cbk(hperh); - } - else - { - for (i = 0; i < hperh->step; i++) - { - CRYPT_WRITE_FIFO(hperh, *in_buf++); - } - } + uint32_t i; + uint32_t *in_buf; + uint32_t *out_buf; + + if (READ_BIT(hperh->perh->CON, CRYPT_CON_ENCS_MSK)) { + in_buf = (uint32_t *)hperh->plain_text + hperh->count; + out_buf = (uint32_t *)hperh->cipher_text + hperh->count - hperh->step; + } + else { + in_buf = (uint32_t *)hperh->cipher_text + hperh->count; + out_buf = (uint32_t *)hperh->plain_text + hperh->count - hperh->step; + } + + if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) { + ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF); + } + + for (i = 0; i < hperh->step; i++) + *out_buf++ = CRYPT_READ_FIFO(hperh); + + hperh->count += hperh->step; + if (hperh->count > (hperh->size / 4)) { + hperh->count = 0; + hperh->state = CRYPT_STATE_READY; + + if (hperh->crypt_cplt_cbk) + hperh->crypt_cplt_cbk(hperh); + } + else { + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *in_buf++); + } + } } /** * @} @@ -849,15 +801,14 @@ void ald_crypt_irq_handler(crypt_handle_t *hperh) */ void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state) { - assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT(hperh->perh)); - if (it == CRYPT_IT_IT) - { - CLEAR_BIT(CRYPT->CON, CRYPT_CON_IE_MSK); - CRYPT->CON |= (state << CRYPT_CON_IE_POS); - } + if (it == CRYPT_IT_IT) { + CLEAR_BIT(CRYPT->CON, CRYPT_CON_IE_MSK); + CRYPT->CON |= (state << CRYPT_CON_IE_POS); + } - return; + return; } /** @brief Check whether the specified CRYPT flag is set or not. @@ -871,13 +822,13 @@ void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_ */ flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) { - assert_param(IS_CRYPT(hperh->perh)); - assert_param(IS_CRYPT_FLAG(flag)); + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_FLAG(flag)); - if (CRYPT->IF & flag) - return SET; + if (CRYPT->IF & flag) + return SET; - return RESET; + return RESET; } /** @brief Clear the specified CRYPT pending flags. @@ -891,11 +842,11 @@ flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag */ void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) { - assert_param(IS_CRYPT(hperh->perh)); - assert_param(IS_CRYPT_FLAG(flag)); + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_FLAG(flag)); - WRITE_REG(CRYPT->IFC, flag); - return; + WRITE_REG(CRYPT->IFC, flag); + return; } /** @@ -911,12 +862,12 @@ void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) */ it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it) { - assert_param(IS_CRYPT_IT(it)); + assert_param(IS_CRYPT_IT(it)); - if (READ_BIT(CRYPT->CON, CRYPT_CON_IE_MSK)) - return SET; + if (READ_BIT(CRYPT->CON, CRYPT_CON_IE_MSK)) + return SET; - return RESET; + return RESET; } @@ -937,10 +888,10 @@ it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it) */ crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh) { - assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT(hperh->perh)); - return hperh->state; + return hperh->state; } /** @@ -964,26 +915,26 @@ crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh) */ void crypt_reset(crypt_handle_t *hperh) { - hperh->perh->DATA[0] = 0x0; - hperh->perh->DATA[1] = 0x0; - hperh->perh->DATA[2] = 0x0; - hperh->perh->DATA[3] = 0x0; - hperh->perh->KEY[0] = 0x0; - hperh->perh->KEY[1] = 0x0; - hperh->perh->KEY[2] = 0x0; - hperh->perh->KEY[3] = 0x0; - hperh->perh->KEY[4] = 0x0; - hperh->perh->KEY[5] = 0x0; - hperh->perh->KEY[6] = 0x0; - hperh->perh->KEY[7] = 0x0; - hperh->perh->IV[0] = 0x0; - hperh->perh->IV[1] = 0x0; - hperh->perh->IV[2] = 0x0; - hperh->perh->IV[3] = 0x0; - hperh->perh->CON = 0x0; - - hperh->state = CRYPT_STATE_READY; - __UNLOCK(hperh); + hperh->perh->DATA[0] = 0x0; + hperh->perh->DATA[1] = 0x0; + hperh->perh->DATA[2] = 0x0; + hperh->perh->DATA[3] = 0x0; + hperh->perh->KEY[0] = 0x0; + hperh->perh->KEY[1] = 0x0; + hperh->perh->KEY[2] = 0x0; + hperh->perh->KEY[3] = 0x0; + hperh->perh->KEY[4] = 0x0; + hperh->perh->KEY[5] = 0x0; + hperh->perh->KEY[6] = 0x0; + hperh->perh->KEY[7] = 0x0; + hperh->perh->IV[0] = 0x0; + hperh->perh->IV[1] = 0x0; + hperh->perh->IV[2] = 0x0; + hperh->perh->IV[3] = 0x0; + hperh->perh->CON = 0x0; + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); } #ifdef ALD_DMA @@ -995,18 +946,18 @@ void crypt_reset(crypt_handle_t *hperh) */ static void crypt_dma_crypt_cplt(void *arg) { - crypt_handle_t *hperh = (crypt_handle_t *)arg; + crypt_handle_t *hperh = (crypt_handle_t *)arg; - CRYPT_DMA_DISABLE(hperh); - hperh->count = 0; - hperh->plain_text = NULL; - hperh->cipher_text = NULL; - hperh->size = 0; + CRYPT_DMA_DISABLE(hperh); + hperh->count = 0; + hperh->plain_text = NULL; + hperh->cipher_text = NULL; + hperh->size = 0; - hperh->state = CRYPT_STATE_READY; + hperh->state = CRYPT_STATE_READY; - if (hperh->crypt_cplt_cbk) - hperh->crypt_cplt_cbk(hperh); + if (hperh->crypt_cplt_cbk) + hperh->crypt_cplt_cbk(hperh); } /** @@ -1017,18 +968,18 @@ static void crypt_dma_crypt_cplt(void *arg) */ static void crypt_dma_error(void *arg) { - crypt_handle_t *hperh = (crypt_handle_t *)arg; - CRYPT_DMA_DISABLE(hperh); + crypt_handle_t *hperh = (crypt_handle_t *)arg; + CRYPT_DMA_DISABLE(hperh); - hperh->count = 0; - hperh->plain_text = NULL; - hperh->cipher_text = NULL; - hperh->size = 0; + hperh->count = 0; + hperh->plain_text = NULL; + hperh->cipher_text = NULL; + hperh->size = 0; - hperh->state = CRYPT_STATE_READY; + hperh->state = CRYPT_STATE_READY; - if (hperh->err_cplt_cbk) - hperh->err_cplt_cbk(hperh); + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); } #endif /** diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c index 5847fa627dd02189c59ee19a0fd597cd703c20f6..f3c125578de145f3f890eaacf04392e482439abf 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c @@ -73,7 +73,7 @@ /** @defgroup DMA_Private_Variables DMA Private Variables * @{ */ -dma_descriptor_t dma0_ctrl_base[28] __attribute__((aligned(512))); +dma_descriptor_t dma0_ctrl_base[28] __attribute__ ((aligned(512))); dma_call_back_t dma0_cbk[6]; /** * @} @@ -93,74 +93,74 @@ dma_call_back_t dma0_cbk[6]; */ static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config_t *p) { - dma_descriptor_t *descr; - - assert_param(IS_DMA(DMAx)); - assert_param(IS_CYCLECTRL_TYPE(mode)); - assert_param(p->src != NULL); - assert_param(p->dst != NULL); - assert_param(IS_DMA_DATA_SIZE(p->size)); - assert_param(IS_DMA_DATASIZE_TYPE(p->data_width)); - assert_param(IS_DMA_DATAINC_TYPE(p->src_inc)); - assert_param(IS_DMA_DATAINC_TYPE(p->dst_inc)); - assert_param(IS_DMA_ARBITERCONFIG_TYPE(p->R_power)); - assert_param(IS_FUNC_STATE(p->primary)); - assert_param(IS_FUNC_STATE(p->burst)); - assert_param(IS_FUNC_STATE(p->high_prio)); - assert_param(IS_FUNC_STATE(p->iterrupt)); - assert_param(IS_DMA_MSEL_TYPE(p->msel)); - assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel)); - assert_param(IS_DMA_CHANNEL(p->channel)); - - if (p->primary) - descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + p->channel; - else - descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + p->channel; - - if (p->src_inc == DMA_DATA_INC_NONE) - descr->src = p->src; - else - descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << p->data_width)); - - if (p->dst_inc == DMA_DATA_INC_NONE) - descr->dst = p->dst; - else - descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << p->data_width)); - - descr->ctrl.cycle_ctrl = mode; - descr->ctrl.next_useburst = 0; - descr->ctrl.n_minus_1 = p->size - 1; - descr->ctrl.R_power = p->R_power; - descr->ctrl.src_prot_ctrl = 0, - descr->ctrl.dst_prot_ctrl = 0, - descr->ctrl.src_size = p->data_width; - descr->ctrl.src_inc = p->src_inc; - descr->ctrl.dst_size = p->data_width; - descr->ctrl.dst_inc = p->dst_inc; - - if (p->primary) - WRITE_REG(DMAx->CHPRIALTCLR, (1 << p->channel)); - else - WRITE_REG(DMAx->CHPRIALTSET, (1 << p->channel)); - - if (p->burst) - WRITE_REG(DMAx->CHUSEBURSTSET, (1 << p->channel)); - else - WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << p->channel)); - - if (p->high_prio) - WRITE_REG(DMAx->CHPRSET, (1 << p->channel)); - else - WRITE_REG(DMAx->CHPRCLR, (1 << p->channel)); - - if (p->iterrupt) - SET_BIT(DMAx->IER, (1 << p->channel)); - else - CLEAR_BIT(DMAx->IER, (1 << p->channel)); - - MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSEL_MSK, p->msel << DMA_CH0_SELCON_MSEL_POSS); - MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSIGSEL_MSK, p->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); - return; + dma_descriptor_t *descr; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_CYCLECTRL_TYPE(mode)); + assert_param(p->src != NULL); + assert_param(p->dst != NULL); + assert_param(IS_DMA_DATA_SIZE(p->size)); + assert_param(IS_DMA_DATASIZE_TYPE(p->data_width)); + assert_param(IS_DMA_DATAINC_TYPE(p->src_inc)); + assert_param(IS_DMA_DATAINC_TYPE(p->dst_inc)); + assert_param(IS_DMA_ARBITERCONFIG_TYPE(p->R_power)); + assert_param(IS_FUNC_STATE(p->primary)); + assert_param(IS_FUNC_STATE(p->burst)); + assert_param(IS_FUNC_STATE(p->high_prio)); + assert_param(IS_FUNC_STATE(p->interrupt)); + assert_param(IS_DMA_MSEL_TYPE(p->msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel)); + assert_param(IS_DMA_CHANNEL(p->channel)); + + if (p->primary) + descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + p->channel; + else + descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + p->channel; + + if (p->src_inc == DMA_DATA_INC_NONE) + descr->src = p->src; + else + descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << (uint32_t)p->src_inc)); + + if (p->dst_inc == DMA_DATA_INC_NONE) + descr->dst = p->dst; + else + descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << (uint32_t)p->dst_inc)); + + descr->ctrl.cycle_ctrl = mode; + descr->ctrl.next_useburst = 0; + descr->ctrl.n_minus_1 = p->size - 1; + descr->ctrl.R_power = p->R_power; + descr->ctrl.src_prot_ctrl = 0, + descr->ctrl.dst_prot_ctrl = 0, + descr->ctrl.src_size = p->data_width; + descr->ctrl.src_inc = p->src_inc; + descr->ctrl.dst_size = p->data_width; + descr->ctrl.dst_inc = p->dst_inc; + + if (p->primary) + WRITE_REG(DMAx->CHPRIALTCLR, (1 << p->channel)); + else + WRITE_REG(DMAx->CHPRIALTSET, (1 << p->channel)); + + if (p->burst) + WRITE_REG(DMAx->CHUSEBURSTSET, (1 << p->channel)); + else + WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << p->channel)); + + if (p->high_prio) + WRITE_REG(DMAx->CHPRSET, (1 << p->channel)); + else + WRITE_REG(DMAx->CHPRCLR, (1 << p->channel)); + + if (p->interrupt) + SET_BIT(DMAx->IER, (1 << p->channel)); + else + CLEAR_BIT(DMAx->IER, (1 << p->channel)); + + MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSEL_MSK, p->msel << DMA_CH0_SELCON_MSEL_POSS); + MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSIGSEL_MSK, p->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); + return; } /** @@ -169,31 +169,27 @@ static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config */ void ald_dma_irq_handler(void) { - uint32_t i, reg = DMA0->IFLAG; - - for (i = 0; i < DMA_CH_COUNT; ++i) - { - if (READ_BIT(reg, (1 << i))) - { - if (dma0_cbk[i].cplt_cbk != NULL) - dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg); - - ald_dma_clear_flag_status(DMA0, i); - } - } - - if (READ_BIT(reg, (1U << DMA_ERR))) - { - ald_dma_clear_flag_status(DMA0, DMA_ERR); - - for (i = 0; i < DMA_CH_COUNT; ++i) - { - if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL)) - dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg); - } - } - - return; + uint32_t i, reg = DMA0->IFLAG; + + for (i = 0; i < DMA_CH_COUNT; ++i) { + if (READ_BIT(reg, (1 << i))) { + if (dma0_cbk[i].cplt_cbk != NULL) + dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg); + + ald_dma_clear_flag_status(DMA0, i); + } + } + + if (READ_BIT(reg, (1U << DMA_ERR))) { + ald_dma_clear_flag_status(DMA0, DMA_ERR); + + for (i = 0; i < DMA_CH_COUNT; ++i) { + if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL)) + dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg); + } + } + + return; } /** * @} @@ -230,6 +226,9 @@ void ald_dma_irq_handler(void) (+) ald_dma_config_struct(): Configure dma_config_t structure using default parameter. + (+) ald_dma_config_sg_alt_desc(): Configure dma_descriptor_t + structure using specified parameter. This function used + in scatter-gather mode(memory or peripheral). @endverbatim * @{ */ @@ -241,24 +240,24 @@ void ald_dma_irq_handler(void) */ void ald_dma_reset(DMA_TypeDef *DMAx) { - uint32_t i; + uint32_t i; - assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA(DMAx)); - WRITE_REG(DMAx->CFG, 0x0); - WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF); - WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF); - WRITE_REG(DMAx->CHENCLR, 0xFFF); - WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF); - WRITE_REG(DMAx->CHPRCLR, 0xFFF); - WRITE_REG(DMAx->ERRCLR, 0x1); - WRITE_REG(DMAx->IER, 0x0); - WRITE_REG(DMAx->ICFR, 0x80000FFF); + WRITE_REG(DMAx->CFG, 0x0); + WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF); + WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF); + WRITE_REG(DMAx->CHENCLR, 0xFFF); + WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF); + WRITE_REG(DMAx->CHPRCLR, 0xFFF); + WRITE_REG(DMAx->ERRCLR, 0x1); + WRITE_REG(DMAx->IER, 0x0); + WRITE_REG(DMAx->ICFR, 0x80000FFF); - for (i = 0; i < DMA_CH_COUNT; ++i) - WRITE_REG(DMAx->CH_SELCON[i], 0x0); + for (i = 0; i < DMA_CH_COUNT; ++i) + WRITE_REG(DMAx->CH_SELCON[i], 0x0); - return; + return; } /** @@ -269,20 +268,20 @@ void ald_dma_reset(DMA_TypeDef *DMAx) */ void ald_dma_init(DMA_TypeDef *DMAx) { - assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA(DMAx)); - memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base)); - memset(dma0_cbk, 0x0, sizeof(dma0_cbk)); + memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base)); + memset(dma0_cbk, 0x0, sizeof(dma0_cbk)); - ald_dma_reset(DMAx); - NVIC_SetPriority(DMA_IRQn, 2); - NVIC_EnableIRQ(DMA_IRQn); - SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK); + ald_dma_reset(DMAx); + NVIC_SetPriority(DMA_IRQn, 2); + NVIC_EnableIRQ(DMA_IRQn); + SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK); - WRITE_REG(DMAx->CTRLBASE, (uint32_t)&dma0_ctrl_base); - SET_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE_MSK); + WRITE_REG(DMAx->CTRLBASE, (uint32_t)&dma0_ctrl_base); + SET_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE_MSK); - return; + return; } /** @@ -293,16 +292,53 @@ void ald_dma_init(DMA_TypeDef *DMAx) */ void ald_dma_config_struct(dma_config_t *p) { - p->data_width = DMA_DATA_SIZE_BYTE; - p->src_inc = DMA_DATA_INC_BYTE; - p->dst_inc = DMA_DATA_INC_BYTE; - p->R_power = DMA_R_POWER_1; - p->primary = ENABLE; - p->burst = DISABLE; - p->high_prio = DISABLE; - p->iterrupt = ENABLE; - - return; + p->data_width = DMA_DATA_SIZE_BYTE; + p->src_inc = DMA_DATA_INC_BYTE; + p->dst_inc = DMA_DATA_INC_BYTE; + p->R_power = DMA_R_POWER_1; + p->primary = ENABLE; + p->burst = DISABLE; + p->high_prio = DISABLE; + p->interrupt = ENABLE; + + return; +} + +/** + * @brief Configure dma_descriptor_t structure using specified parameter. + * @note This function used in scatter-gather mode(memory or peripheral). + * @param desc: Address of the alternate descriptor. + * @param config: Pointer to the dma_config_t structure. + * @param memory: Memory or peripheral scatter-gather. + * @retval None + */ +void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory) +{ + if ((desc == NULL) || (config == NULL)) + return; + + if (config->src_inc == DMA_DATA_INC_NONE) + desc->src = config->src; + else + desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width)); + + if (config->dst_inc == DMA_DATA_INC_NONE) + desc->dst = config->dst; + else + desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width)); + + desc->ctrl.cycle_ctrl = memory ? DMA_CYCLE_CTRL_MEM_SG_ALTERNATE : DMA_CYCLE_CTRL_PER_SG_ALTERNATE; + desc->ctrl.next_useburst = memory ? 0 : 1; + desc->ctrl.n_minus_1 = config->size - 1; + desc->ctrl.R_power = config->R_power; + desc->ctrl.src_prot_ctrl = 0; + desc->ctrl.dst_prot_ctrl = 0; + desc->ctrl.src_size = config->data_width; + desc->ctrl.src_inc = config->src_inc; + desc->ctrl.dst_size = config->data_width; + desc->ctrl.dst_inc = config->dst_inc; + + return; } /** @@ -328,6 +364,7 @@ void ald_dma_config_struct(dma_config_t *p) (++) ald_dma_config_auto_easy(): Configure DMA channel according to the specified parameter. If you want use the dma easily, you can invoke this function. + (++) ald_dma_config_sg_mem(): Carry data used scatter-gather mode. (+) Carry data from peripheral to memory or from memory to peripheral, this mode APIs are: (++) ald_dma_config_basic(): Configure DMA channel according to @@ -336,6 +373,8 @@ void ald_dma_config_struct(dma_config_t *p) (++) ald_dma_config_basic_easy(): Configure DMA channel according to the specified parameter. If you want use the dma easily, you can invoke this function. + (++) ald_dma_ping_pong(): Carry data used ping-pong mode. + (++) ald_dma_config_sg_per(): Carry data used scatter-gather mode. @endverbatim * @{ @@ -351,17 +390,17 @@ void ald_dma_config_struct(dma_config_t *p) */ void ald_dma_config_auto(dma_handle_t *hperh) { - dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; - dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; - dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; - dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; - dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config); + dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; + dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; + dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; + dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; + dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config); - ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); - WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); - SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); - return; + return; } /** @@ -376,39 +415,35 @@ void ald_dma_config_auto(dma_handle_t *hperh) */ void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size) { - dma_descriptor_t *descr; - - if (hperh->config.primary) - descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; - else - descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; - - if (src) - { - if (hperh->config.src_inc == DMA_DATA_INC_NONE) - descr->src = src; - else - descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width)); - } - - if (dst) - { - if (hperh->config.dst_inc == DMA_DATA_INC_NONE) - descr->dst = dst; - else - descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width)); - } - - ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); - descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; - descr->ctrl.n_minus_1 = size - 1; - WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); - SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); - return; + dma_descriptor_t *descr; + + if (hperh->config.primary) + descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; + else + descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; + + if (src) { + if (hperh->config.src_inc == DMA_DATA_INC_NONE) + descr->src = src; + else + descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width)); + } + + if (dst) { + if (hperh->config.dst_inc == DMA_DATA_INC_NONE) + descr->dst = dst; + else + descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width)); + } + + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; + descr->ctrl.n_minus_1 = size - 1; + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); + return; } - - /** * @brief Configure DMA channel according to the specified parameter. * The DMA mode is automatic. This mode is used to carry data @@ -420,33 +455,32 @@ void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t si * @param size: The total number of DMA transfers that DMA cycle contains * @param channel: Channel index which will be used. * @param cbk: DMA complete callback function - * * @retval None */ void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, - uint16_t size, uint8_t channel, void (*cbk)(void *arg)) + uint16_t size, uint8_t channel, void (*cbk)(void *arg)) { - dma_handle_t hperh; + dma_handle_t hperh; - assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA(DMAx)); - ald_dma_config_struct(&hperh.config); - hperh.config.src = src; - hperh.config.dst = dst; - hperh.config.size = size; - hperh.config.msel = DMA_MSEL_NONE; - hperh.config.msigsel = DMA_MSIGSEL_NONE; - hperh.config.channel = channel; + ald_dma_config_struct(&hperh.config); + hperh.config.src = src; + hperh.config.dst = dst; + hperh.config.size = size; + hperh.config.msel = DMA_MSEL_NONE; + hperh.config.msigsel = DMA_MSIGSEL_NONE; + hperh.config.channel = channel; - hperh.perh = DMAx; - hperh.cplt_cbk = cbk; - hperh.cplt_arg = NULL; - hperh.err_cbk = NULL; + hperh.perh = DMAx; + hperh.cplt_cbk = cbk; + hperh.cplt_arg = NULL; + hperh.err_cbk = NULL; - ald_dma_clear_flag_status(DMAx, channel); - ald_dma_config_auto(&hperh); + ald_dma_clear_flag_status(DMAx, channel); + ald_dma_config_auto(&hperh); - return; + return; } /** @@ -460,16 +494,16 @@ void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, */ void ald_dma_config_basic(dma_handle_t *hperh) { - dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; - dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; - dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; - dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; + dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; + dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; + dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; + dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; - ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); - dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config); - WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config); + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); - return; + return; } /** @@ -484,35 +518,33 @@ void ald_dma_config_basic(dma_handle_t *hperh) */ void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size) { - dma_descriptor_t *descr; - - if (hperh->config.primary) - descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; - else - descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; - - if (src) - { - if (hperh->config.src_inc == DMA_DATA_INC_NONE) - descr->src = src; - else - descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width)); - } - - if (dst) - { - if (hperh->config.dst_inc == DMA_DATA_INC_NONE) - descr->dst = dst; - else - descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width)); - } - - ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); - descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; - descr->ctrl.n_minus_1 = size - 1; - WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); - - return; + dma_descriptor_t *descr; + + if (hperh->config.primary) + descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; + else + descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; + + if (src) { + if (hperh->config.src_inc == DMA_DATA_INC_NONE) + descr->src = src; + else + descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width)); + } + + if (dst) { + if (hperh->config.dst_inc == DMA_DATA_INC_NONE) + descr->dst = dst; + else + descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width)); + } + + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; + descr->ctrl.n_minus_1 = size - 1; + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + + return; } /** @@ -528,42 +560,248 @@ void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t s * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t * @param channel: Channel index which will be used * @param cbk: DMA complete callback function - * * @retval None - * - */ + */ void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, - dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) + dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) { - dma_handle_t hperh; + dma_handle_t hperh; + + assert_param(IS_DMA(DMAx)); + ald_dma_config_struct(&hperh.config); - assert_param(IS_DMA(DMAx)); - ald_dma_config_struct(&hperh.config); + if (((uint32_t)src) >= 0x40000000) + hperh.config.src_inc = DMA_DATA_INC_NONE; - if (((uint32_t)src) >= 0x40000000) - hperh.config.src_inc = DMA_DATA_INC_NONE; + if (((uint32_t)dst) >= 0x40000000) + hperh.config.dst_inc = DMA_DATA_INC_NONE; - if (((uint32_t)dst) >= 0x40000000) - hperh.config.dst_inc = DMA_DATA_INC_NONE; + hperh.config.src = src; + hperh.config.dst = dst; + hperh.config.size = size; + hperh.config.msel = msel; + hperh.config.msigsel = msigsel; + hperh.config.channel = channel; - hperh.config.src = src; - hperh.config.dst = dst; - hperh.config.size = size; - hperh.config.msel = msel; - hperh.config.msigsel = msigsel; - hperh.config.channel = channel; + hperh.perh = DMAx; + hperh.cplt_cbk = cbk; + hperh.cplt_arg = NULL; + hperh.err_cbk = NULL; - hperh.perh = DMAx; - hperh.cplt_cbk = cbk; - hperh.cplt_arg = NULL; - hperh.err_cbk = NULL; + ald_dma_clear_flag_status(DMAx, channel); + ald_dma_config_basic(&hperh); - ald_dma_clear_flag_status(DMAx, channel); - ald_dma_config_basic(&hperh); + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is ping-pong. + * @note The ping-pong mode does not support memory to memory. + * @param DMAx: Pointer to DMA peripheral. + * @param config: Pointer to the dma_config_t structure which contains + * the specified parameters. + * @param first: Whether it is the first transmission. 1-first, 0-not first. + * @param cbk: DMA complete callback function. + * @retval None + */ +void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config, + uint8_t first, void (*cbk)(void *arg)) +{ + dma_descriptor_t *desc; + + assert_param(IS_DMA(DMAx)); + assert_param(config->src != NULL); + assert_param(config->dst != NULL); + assert_param(IS_DMA_DATA_SIZE(config->size)); + assert_param(IS_DMA_DATASIZE_TYPE(config->data_width)); + assert_param(IS_DMA_DATAINC_TYPE(config->src_inc)); + assert_param(IS_DMA_DATAINC_TYPE(config->dst_inc)); + assert_param(IS_DMA_ARBITERCONFIG_TYPE(config->R_power)); + assert_param(IS_FUNC_STATE(config->primary)); + assert_param(IS_FUNC_STATE(config->burst)); + assert_param(IS_FUNC_STATE(config->high_prio)); + assert_param(IS_FUNC_STATE(config->interrupt)); + assert_param(IS_DMA_MSEL_TYPE(config->msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(config->msigsel)); + assert_param(IS_DMA_CHANNEL(config->channel)); + + dma0_cbk[config->channel].cplt_cbk = cbk; + dma0_cbk[config->channel].err_cbk = NULL; + dma0_cbk[config->channel].cplt_arg = NULL; + dma0_cbk[config->channel].err_arg = NULL; + + if (config->primary) + desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + config->channel; + else + desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + config->channel; + + if (config->src_inc == DMA_DATA_INC_NONE) + desc->src = config->src; + else + desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width)); + + if (config->dst_inc == DMA_DATA_INC_NONE) + desc->dst = config->dst; + else + desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width)); + + desc->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PINGPONG; + desc->ctrl.next_useburst = 0; + desc->ctrl.n_minus_1 = config->size - 1; + desc->ctrl.R_power = config->R_power; + desc->ctrl.src_prot_ctrl = 0, + desc->ctrl.dst_prot_ctrl = 0, + desc->ctrl.src_size = config->data_width; + desc->ctrl.src_inc = config->src_inc; + desc->ctrl.dst_size = config->data_width; + desc->ctrl.dst_inc = config->dst_inc; + + if (!first) + return; + + if (config->primary) + WRITE_REG(DMAx->CHPRIALTCLR, (1 << config->channel)); + else + WRITE_REG(DMAx->CHPRIALTSET, (1 << config->channel)); + + if (config->burst) + WRITE_REG(DMAx->CHUSEBURSTSET, (1 << config->channel)); + else + WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << config->channel)); + + if (config->high_prio) + WRITE_REG(DMAx->CHPRSET, (1 << config->channel)); + else + WRITE_REG(DMAx->CHPRCLR, (1 << config->channel)); + + if (config->interrupt) + SET_BIT(DMAx->IER, (1 << config->channel)); + else + CLEAR_BIT(DMAx->IER, (1 << config->channel)); + + MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSEL_MSK, config->msel << DMA_CH0_SELCON_MSEL_POSS); + MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSIGSEL_MSK, config->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); + + WRITE_REG(DMAx->ICFR, (1 << config->channel)); + WRITE_REG(DMAx->CHENSET, (1 << config->channel)); + + return; +} - return; +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is memory scatter-gather. + * @param DMAx: Pointer to DMA peripheral. + * @param desc: Pointer to first alternate descriptor. + * @param nr: Number of the alternate descriptor. + * @param channel: Channel index which will be used. + * @param cbk: DMA complete callback function. + * @retval None + */ +void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, + uint8_t channel, void (*cbk)(void *arg)) +{ + dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_CHANNEL(channel)); + + if ((desc == NULL) || (nr == 0)) + return; + + dma0_cbk[channel].cplt_cbk = cbk; + dma0_cbk[channel].err_cbk = NULL; + dma0_cbk[channel].cplt_arg = NULL; + dma0_cbk[channel].err_arg = NULL; + + tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD)); + tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD)); + tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_MEM_SG_PRIMARY; + tmp->ctrl.next_useburst = 0; + tmp->ctrl.n_minus_1 = (nr << 2) - 1; + tmp->ctrl.R_power = DMA_R_POWER_4; + tmp->ctrl.src_prot_ctrl = 0, + tmp->ctrl.dst_prot_ctrl = 0, + tmp->ctrl.src_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.src_inc = DMA_DATA_INC_WORD; + tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.dst_inc = DMA_DATA_INC_WORD; + + desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; + WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel)); + WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << channel)); + WRITE_REG(DMAx->CHPRCLR, (1 << channel)); + + WRITE_REG(DMAx->ICFR, (1 << channel)); + SET_BIT(DMAx->IER, (1 << channel)); + WRITE_REG(DMAx->CHENSET, (1 << channel)); + SET_BIT(DMAx->CHSWREQ, (1 << channel)); + + return; } +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is peripheral scatter-gather. + * @note The size of the first transmission must be 5. + * @param DMAx: Pointer to DMA peripheral. + * @param desc: Pointer to first alternate descriptor. + * @param nr: Number of the alternate descriptor. + * @param burst: 1-Enable burst, 0-Disable burst. + * @param msel: Input source to DMA channel @ref dma_msel_t + * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t + * @param channel: Channel index which will be used. + * @param cbk: DMA complete callback function. + * @retval None + */ +void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, + dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) +{ + dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_MSEL_TYPE(msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(msigsel)); + assert_param(IS_DMA_CHANNEL(channel)); + + if ((desc == NULL) || (nr == 0)) + return; + + dma0_cbk[channel].cplt_cbk = cbk; + dma0_cbk[channel].err_cbk = NULL; + dma0_cbk[channel].cplt_arg = NULL; + dma0_cbk[channel].err_arg = NULL; + + tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD)); + tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD)); + tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PER_SG_PRIMARY; + tmp->ctrl.next_useburst = 0; + tmp->ctrl.n_minus_1 = (nr << 2) - 1; + tmp->ctrl.R_power = DMA_R_POWER_4; + tmp->ctrl.src_prot_ctrl = 0, + tmp->ctrl.dst_prot_ctrl = 0, + tmp->ctrl.src_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.src_inc = DMA_DATA_INC_WORD; + tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.dst_inc = DMA_DATA_INC_WORD; + + desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; + WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel)); + burst ? (DMAx->CHUSEBURSTSET = (1 << channel)) : (DMAx->CHUSEBURSTCLR, (1 << channel)); + WRITE_REG(DMAx->CHPRCLR, (1 << channel)); + + MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSEL_MSK, msel << DMA_CH0_SELCON_MSEL_POSS); + MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSIGSEL_MSK, msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); + + WRITE_REG(DMAx->ICFR, (1 << channel)); + SET_BIT(DMAx->IER, (1 << channel)); + WRITE_REG(DMAx->CHENSET, (1 << channel)); + + return; +} /** * @} */ @@ -605,28 +843,26 @@ void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t */ void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) { - dma_descriptor_t *descr, *alt_descr; - - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_CHANNEL(channel)); - assert_param(IS_FUNC_STATE(state)); - - descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; - alt_descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; - - if (state) - { - WRITE_REG(DMAx->CHENSET, (1 << channel)); - } - else - { - memset(descr, 0x00, sizeof(dma_descriptor_t)); - memset(alt_descr, 0x00, sizeof(dma_descriptor_t)); - WRITE_REG(DMAx->CH_SELCON[channel], 0x0); - WRITE_REG(DMAx->CHENCLR, (1 << channel)); - } - - return; + dma_descriptor_t *descr, *alt_descr; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_FUNC_STATE(state)); + + descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + alt_descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + + if (state) { + WRITE_REG(DMAx->CHENSET, (1 << channel)); + } + else { + memset(descr, 0x00, sizeof(dma_descriptor_t)); + memset(alt_descr, 0x00, sizeof(dma_descriptor_t)); + WRITE_REG(DMAx->CH_SELCON[channel], 0x0); + WRITE_REG(DMAx->CHENCLR, (1 << channel)); + } + + return; } /** @@ -643,16 +879,16 @@ void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t stat */ void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) { - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_IT_TYPE(channel)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + assert_param(IS_FUNC_STATE(state)); - if (state) - SET_BIT(DMAx->IER, (1 << channel)); - else - CLEAR_BIT(DMAx->IER, (1 << channel)); + if (state) + SET_BIT(DMAx->IER, (1 << channel)); + else + CLEAR_BIT(DMAx->IER, (1 << channel)); - return; + return; } /** @@ -668,13 +904,13 @@ void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t st */ it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel) { - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_IT_TYPE(channel)); + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); - if (READ_BIT(DMAx->IER, (1 << channel))) - return SET; + if (READ_BIT(DMAx->IER, (1 << channel))) + return SET; - return RESET; + return RESET; } /** @@ -690,13 +926,13 @@ it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel) */ flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel) { - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_IT_TYPE(channel)); + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); - if (READ_BIT(DMAx->IFLAG, (1 << channel))) - return SET; + if (READ_BIT(DMAx->IFLAG, (1 << channel))) + return SET; - return RESET; + return RESET; } /** @@ -709,11 +945,42 @@ flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel) */ void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel) { - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_IT_TYPE(channel)); + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + WRITE_REG(DMAx->ICFR, (1 << channel)); + return; +} + +/** + * @brief Get the completion status of the descriptor + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index + * @retval Completion status: + * - DMA_DESCP_CPLT_PRI: Primary descriptor has been completed + * - DMA_DESCP_CPLT_ALT: Alternate descriptor has been completed + * - DMA_DESCP_CPLT_ALL: Both primary and alternate descriptors have been completed + */ +dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel) +{ + uint8_t pri, alt; + dma_descriptor_t *desc; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + pri = desc->ctrl.cycle_ctrl; + desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + alt = desc->ctrl.cycle_ctrl; + + if ((pri == 0) && (alt == 0)) + return DMA_DESCP_CPLT_ALL; - WRITE_REG(DMAx->ICFR, (1 << channel)); - return; + if (pri == 0) + return DMA_DESCP_CPLT_PRI; + else + return DMA_DESCP_CPLT_ALT; } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c index b7a3e128c93200e3a8dc5c710403900aefbe5be8..44d25a7f7638ec90b8cb4781c7388b66fd134245 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c @@ -27,9 +27,9 @@ #ifdef ALD_FLASH #if defined ( __ICCARM__ ) - #define __RAMFUNC __ramfunc +#define __RAMFUNC __ramfunc #else - #define __RAMFUNC +#define __RAMFUNC #endif /** @defgroup Flash_Private_Variables Flash Private Variables @@ -51,23 +51,22 @@ static op_cmd_type OP_CMD = OP_FLASH; */ __RAMFUNC static ald_status_t flash_unlock(void) { - uint16_t i; - uint16_t op_cmd = OP_CMD; + uint16_t i; + uint16_t op_cmd = OP_CMD; - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - return ERROR; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + return ERROR; - FLASH_REG_UNLOCK(); - FLASH_IAP_ENABLE(); - FLASH_REQ(); + FLASH_REG_UNLOCK(); + FLASH_IAP_ENABLE(); + FLASH_REQ(); - for (i = 0; i < 0xFFFF; i++) - { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)) - break; - } + for (i = 0; i < 0xFFFF; i++) { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)) + break; + } - return i == 0xFFFF ? ERROR : OK; + return i == 0xFFFF ? ERROR : OK; } /** @@ -76,19 +75,18 @@ __RAMFUNC static ald_status_t flash_unlock(void) */ __RAMFUNC static ald_status_t flash_lock(void) { - uint16_t i; - uint16_t op_cmd = OP_CMD; + uint16_t i; + uint16_t op_cmd = OP_CMD; - FLASH_REG_UNLOCK(); - WRITE_REG(MSC->FLASHCR, 0x0); + FLASH_REG_UNLOCK(); + WRITE_REG(MSC->FLASHCR, 0x0); - for (i = 0; i < 0xFFFF; i++) - { - if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))) - break; - } + for (i = 0; i < 0xFFFF; i++) { + if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))) + break; + } - return i == 0xFFFF ? ERROR : OK; + return i == 0xFFFF ? ERROR : OK; } /** @@ -98,50 +96,44 @@ __RAMFUNC static ald_status_t flash_lock(void) */ __RAMFUNC ald_status_t flash_page_erase(uint32_t addr) { - uint32_t i; - uint16_t op_cmd = OP_CMD; - - if (flash_unlock() != OK) - goto end; - - if (op_cmd == OP_FLASH) - { - CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); - } - else - { - SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); - } - - WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE); - - for (i = 0; i < 0xFFFF; i++) - { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - continue; - - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK)) - goto end; - - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK)) - goto end; - - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK)) - break; - } - - if (i == 0xFFFF) - goto end; - - if (flash_lock() == ERROR) - goto end; - - return OK; + uint32_t i; + uint16_t op_cmd = OP_CMD; + + if (flash_unlock() != OK) + goto end; + + if (op_cmd == OP_FLASH) { + CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); + } + else { + SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); + } + + WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE); + + for (i = 0; i < 0xFFFF; i++) { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + continue; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK)) + goto end; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK)) + goto end; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK)) + break; + } + + if (i == 0xFFFF) + goto end; + + if (flash_lock() == ERROR) + goto end; + + return OK; end: - flash_lock(); - return ERROR; + flash_lock(); + return ERROR; } /** @@ -154,58 +146,52 @@ end: */ __RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo) { - uint16_t i; - uint16_t prog_len; - uint32_t *p_data = data; - uint16_t op_cmd = OP_CMD; - - if (flash_unlock() != OK) - goto end; - - if (op_cmd == OP_FLASH) - CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - else - SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS); - MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS); - - for (prog_len = 0; prog_len < len; prog_len++) - { - if (fifo) - { - WRITE_REG(MSC->FLASHFIFO, p_data[0]); - WRITE_REG(MSC->FLASHFIFO, p_data[1]); - } - else - { - WRITE_REG(MSC->FLASHDL, p_data[0]); - WRITE_REG(MSC->FLASHDH, p_data[1]); - WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP); - } - - p_data += 2; - - for (i = 0; i < 0xFFFF; i++) - { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - continue; - - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK)) - break; - } - } - - if (i == 0xFFFF) - goto end; - - if (flash_lock() == ERROR) - goto end; - - return OK; + uint16_t i = 0; + uint16_t prog_len; + uint32_t *p_data = data; + uint16_t op_cmd = OP_CMD; + + if (flash_unlock() != OK) + goto end; + + if (op_cmd == OP_FLASH) + CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + else + SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS); + MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS); + + for (prog_len = 0; prog_len < len; prog_len++) { + if (fifo) { + WRITE_REG(MSC->FLASHFIFO, p_data[0]); + WRITE_REG(MSC->FLASHFIFO, p_data[1]); + } + else { + WRITE_REG(MSC->FLASHDL, p_data[0]); + WRITE_REG(MSC->FLASHDH, p_data[1]); + WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP); + } + + p_data += 2; + + for (i = 0; i < 0xFFFF; i++) { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + continue; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK)) + break; + } + } + if (i == 0xFFFF) + goto end; + + if (flash_lock() == ERROR) + goto end; + + return OK; end: - flash_lock(); - return ERROR; + flash_lock(); + return ERROR; } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c index 87595d3ce9af2c9d59bd519618a354a849c231a2..44e8fe7d9c7d6ae18a1d55a6486ef8ba9787bb73 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c @@ -84,30 +84,29 @@ static uint8_t write_buf[FLASH_PAGE_SIZE]; */ static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr) { - uint8_t *addr_to_read; - uint8_t value; - uint32_t index; + uint8_t* addr_to_read; + uint8_t value; + uint32_t index; - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(begin_addr)); - assert_param(IS_FLASH_ADDRESS(end_addr)); + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(begin_addr)); + assert_param(IS_FLASH_ADDRESS(end_addr)); - addr_to_read = (uint8_t *)begin_addr; - index = begin_addr; - value = 0xFF; + addr_to_read = (uint8_t *)begin_addr; + index = begin_addr; + value = 0xFF; - if (begin_addr > end_addr) - return FALSE; + if (begin_addr > end_addr) + return FALSE; - while (index++ <= end_addr) - { - value = *addr_to_read++; + while (index++ <= end_addr) { + value = *addr_to_read++; - if (value != 0xFF) - break; - } + if (value != 0xFF) + break; + } - return value == 0xFF ? FALSE : TRUE; + return value == 0xFF ? FALSE : TRUE; } /** * @} @@ -134,24 +133,23 @@ static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr) */ ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) { - uint32_t i; - uint32_t temp; + uint32_t i; + uint32_t temp; - assert_param(IS_4BYTES_ALIGN(ram_addr)); - assert_param(IS_FLASH_ADDRESS(addr)); - assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + assert_param(IS_4BYTES_ALIGN(ram_addr)); + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); - temp = (uint32_t)ram_addr; + temp = (uint32_t)ram_addr; - if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0)) - return ERROR; + if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0)) + return ERROR; - for (i = 0; i < len; i++) - { - ram_addr[i] = ((uint32_t *)addr)[i]; - } + for (i = 0; i < len; i++) { + ram_addr[i] = ((uint32_t *)addr)[i]; + } - return OK; + return OK; } /** @@ -164,92 +162,84 @@ ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) { - uint32_t index = 0; - uint32_t para = 0; - uint32_t index2 = 0; - uint32_t start_write_addr; - uint32_t end_write_addr; - uint32_t start_word_addr; - uint32_t end_word_addr; - uint16_t len_to_write; - uint32_t len_index; - type_bool_t need_erase_page; - - assert_param(IS_FLASH_ADDRESS(addr)); - assert_param(IS_FLASH_ADDRESS(addr + len - 1)); - - len_to_write = len; - - __disable_irq(); - - while (len_to_write > 0) - { - need_erase_page = FALSE; - - for (index = 0; index < FLASH_PAGE_SIZE; index++) - write_buf[index] = 0xFF; - - start_write_addr = addr + (len - len_to_write); - end_write_addr = addr + len - 1; - end_write_addr = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr) - ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr); - need_erase_page = page_have_writen(FLASH_WORD_ADDR(start_write_addr), - FLASH_WORDEND_ADDR(end_write_addr)); - - if (need_erase_page) - { - if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr), - FLASH_PAGE_SIZE >> 2)) - { - __enable_irq(); - return ERROR; - } - - if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) - { - __enable_irq(); - return ERROR; - } - - para = end_write_addr & (FLASH_PAGE_SIZE - 1); - index = start_write_addr & (FLASH_PAGE_SIZE - 1); - index2 = len - len_to_write; - - while (index <= para) - write_buf[index++] = buf[index2++]; - - index2 = 0; - index = FLASH_PAGE_ADDR(start_write_addr); - para = FLASH_PAGE_ADDR(start_write_addr) + FLASH_PAGE_SIZE; - len_index = FLASH_PAGE_SIZE; - } - else - { - para = end_write_addr & (FLASH_PAGE_SIZE - 1); - index = start_write_addr & (FLASH_PAGE_SIZE - 1); - index2 = len - len_to_write; - - while (index <= para) - write_buf[index++] = buf[index2++]; - - start_word_addr = FLASH_WORD_ADDR(start_write_addr); - end_word_addr = FLASH_WORDEND_ADDR(end_write_addr); - index2 = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr)); - index = start_word_addr; - len_index = end_word_addr - start_word_addr + 1; - } - - if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) - { - __enable_irq(); - return ERROR; - } - - len_to_write = len_to_write - (end_write_addr - start_write_addr + 1); - } - - __enable_irq(); - return OK; + uint32_t index = 0; + uint32_t para = 0; + uint32_t index2 = 0; + uint32_t start_write_addr; + uint32_t end_write_addr; + uint32_t start_word_addr; + uint32_t end_word_addr; + uint16_t len_to_write; + uint32_t len_index; + type_bool_t need_erase_page; + + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + len_to_write = len; + + __disable_irq(); + while (len_to_write > 0) { + need_erase_page = FALSE; + + for (index = 0; index < FLASH_PAGE_SIZE; index++) + write_buf[index] = 0xFF; + + start_write_addr = addr + (len - len_to_write); + end_write_addr = addr + len - 1; + end_write_addr = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr) + ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr); + need_erase_page = page_have_writen(FLASH_WORD_ADDR(start_write_addr), + FLASH_WORDEND_ADDR(end_write_addr)); + + if (need_erase_page) { + if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr), + FLASH_PAGE_SIZE >> 2)) { + __enable_irq(); + return ERROR; + } + + if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) { + __enable_irq(); + return ERROR; + } + + para = end_write_addr & (FLASH_PAGE_SIZE - 1); + index = start_write_addr & (FLASH_PAGE_SIZE - 1); + index2 = len - len_to_write; + + while (index <= para) + write_buf[index++] = buf[index2++]; + + index2 = 0; + index = FLASH_PAGE_ADDR(start_write_addr); + len_index = FLASH_PAGE_SIZE; + } + else { + para = end_write_addr & (FLASH_PAGE_SIZE - 1); + index = start_write_addr & (FLASH_PAGE_SIZE - 1); + index2 = len - len_to_write; + + while (index <= para) + write_buf[index++] = buf[index2++]; + + start_word_addr = FLASH_WORD_ADDR(start_write_addr); + end_word_addr = FLASH_WORDEND_ADDR(end_write_addr); + index2 = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr)); + index = start_word_addr; + len_index = end_word_addr - start_word_addr + 1; + } + + if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) { + __enable_irq(); + return ERROR; + } + + len_to_write = len_to_write - (end_write_addr - start_write_addr + 1); + } + + __enable_irq(); + return OK; } /** @@ -260,81 +250,69 @@ ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) */ ald_status_t ald_flash_erase(uint32_t addr, uint16_t len) { - int32_t index; - int32_t para; - int32_t start_erase_addr; - int32_t end_erase_addr; - uint16_t len_not_erase; - uint32_t len_index; - type_bool_t page_need_save; - - assert_param(IS_FLASH_ADDRESS(addr)); - assert_param(IS_FLASH_ADDRESS(addr + len - 1)); - - len_not_erase = len; - - __disable_irq(); - - while (len_not_erase > 0) - { - page_need_save = FALSE; - - start_erase_addr = addr + len - len_not_erase; - end_erase_addr = addr + len - 1; - end_erase_addr = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr)) - ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr); - - if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) - { - if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1))) - page_need_save = TRUE; - } - - if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) - { - if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr))) - page_need_save = TRUE; - } - - if (page_need_save) - { - if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr), - FLASH_PAGE_SIZE >> 2)) - { - __enable_irq(); - return ERROR; - } - } - - if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) - { - __enable_irq(); - return ERROR; - } - - if (page_need_save) - { - para = end_erase_addr & (FLASH_PAGE_SIZE - 1); - index = start_erase_addr & (FLASH_PAGE_SIZE - 1); - - while (index <= para) - write_buf[index++] = 0xFF; - - index = FLASH_PAGE_ADDR(start_erase_addr); - len_index = FLASH_PAGE_SIZE; - - if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) - { - __enable_irq(); - return ERROR; - } - } - - len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1); - } - - __enable_irq(); - return OK; + uint32_t index; + int32_t para; + int32_t start_erase_addr; + int32_t end_erase_addr; + uint16_t len_not_erase; + uint32_t len_index; + type_bool_t page_need_save; + + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + len_not_erase = len; + + __disable_irq(); + while (len_not_erase > 0) { + page_need_save = FALSE; + + start_erase_addr = addr + len - len_not_erase; + end_erase_addr = addr + len - 1; + end_erase_addr = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr)) + ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr); + + if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) { + if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1))) + page_need_save = TRUE; + } + if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) { + if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr))) + page_need_save = TRUE; + } + + if (page_need_save) { + if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr), + FLASH_PAGE_SIZE >> 2)) { + __enable_irq(); + return ERROR; + } + } + + if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) { + __enable_irq(); + return ERROR; + } + + if (page_need_save) { + para = end_erase_addr & (FLASH_PAGE_SIZE - 1); + index = start_erase_addr & (FLASH_PAGE_SIZE - 1); + + while (index <= para) + write_buf[index++] = 0xFF; + + index = FLASH_PAGE_ADDR(start_erase_addr); + len_index = FLASH_PAGE_SIZE; + if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) { + __enable_irq(); + return ERROR; + } + } + len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1); + } + + __enable_irq(); + return OK; } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c index 17b4464ac161953b72512091f191abb41915731f..08366e93502bc9ec126ced29cc7ecb4bd57f6e9e 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c @@ -168,77 +168,76 @@ */ void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) { - uint32_t i, pos, mask, tmp; - - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); - assert_param(IS_GPIO_MODE(init->mode)); - assert_param(IS_GPIO_ODOS(init->odos)); - assert_param(IS_GPIO_PUPD(init->pupd)); - assert_param(IS_GPIO_ODRV(init->odrv)); - assert_param(IS_GPIO_FLT(init->flt)); - assert_param(IS_GPIO_TYPE(init->type)); - assert_param(IS_GPIO_FUNC(init->func)); - - for (i = 0; i < 16; ++i) - { - if (((pin >> i) & 0x1) == 0) - continue; - - /* Get position and 2-bits mask */ - pos = i << 1; - mask = 0x3 << pos; - - /* Set PIN mode */ - tmp = READ_REG(GPIOx->MODE); - tmp &= ~mask; - tmp |= (init->mode << pos); - WRITE_REG(GPIOx->MODE, tmp); - - /* Set PIN open-drain or push-pull */ - tmp = READ_REG(GPIOx->ODOS); - tmp &= ~mask; - tmp |= (init->odos << pos); - WRITE_REG(GPIOx->ODOS, tmp); - - /* Set PIN push-up or/and push-down */ - tmp = READ_REG(GPIOx->PUPD); - tmp &= ~mask; - tmp |= (init->pupd << pos); - WRITE_REG(GPIOx->PUPD, tmp); - - /* Set PIN output driver */ - tmp = READ_REG(GPIOx->ODRV); - tmp &= ~mask; - tmp |= (init->odrv << pos); - WRITE_REG(GPIOx->ODRV, tmp); - - /* Get position and 1-bit mask */ - pos = i; - mask = 0x1 << pos; - - /* Set PIN filter enable or disable */ - tmp = READ_REG(GPIOx->FLT); - tmp &= ~mask; - tmp |= (init->flt << pos); - WRITE_REG(GPIOx->FLT, tmp); - - /* Set PIN type ttl or smit */ - tmp = READ_REG(GPIOx->TYPE); - tmp &= ~mask; - tmp |= (init->type << pos); - WRITE_REG(GPIOx->TYPE, tmp); - - /* Configure PIN function */ - pos = i < 8 ? (i << 2) : ((i - 8) << 2); - mask = 0xF << pos; - tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); - tmp &= ~mask; - tmp |= (init->func << pos); - i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); - } - - return; + uint32_t i, pos, mask, tmp; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_MODE(init->mode)); + assert_param(IS_GPIO_ODOS(init->odos)); + assert_param(IS_GPIO_PUPD(init->pupd)); + assert_param(IS_GPIO_ODRV(init->odrv)); + assert_param(IS_GPIO_FLT(init->flt)); + assert_param(IS_GPIO_TYPE(init->type)); + assert_param(IS_GPIO_FUNC(init->func)); + + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Set PIN mode */ + tmp = READ_REG(GPIOx->MODE); + tmp &= ~mask; + tmp |= (init->mode << pos); + WRITE_REG(GPIOx->MODE, tmp); + + /* Set PIN open-drain or push-pull */ + tmp = READ_REG(GPIOx->ODOS); + tmp &= ~mask; + tmp |= (init->odos << pos); + WRITE_REG(GPIOx->ODOS, tmp); + + /* Set PIN push-up or/and push-down */ + tmp = READ_REG(GPIOx->PUPD); + tmp &= ~mask; + tmp |= (init->pupd << pos); + WRITE_REG(GPIOx->PUPD, tmp); + + /* Set PIN output driver */ + tmp = READ_REG(GPIOx->ODRV); + tmp &= ~mask; + tmp |= (init->odrv << pos); + WRITE_REG(GPIOx->ODRV, tmp); + + /* Get position and 1-bit mask */ + pos = i; + mask = 0x1 << pos; + + /* Set PIN filter enable or disable */ + tmp = READ_REG(GPIOx->FLT); + tmp &= ~mask; + tmp |= (init->flt << pos); + WRITE_REG(GPIOx->FLT, tmp); + + /* Set PIN type ttl or smit */ + tmp = READ_REG(GPIOx->TYPE); + tmp &= ~mask; + tmp |= (init->type << pos); + WRITE_REG(GPIOx->TYPE, tmp); + + /* Configure PIN function */ + pos = i < 8 ? (i << 2) : ((i - 8) << 2); + mask = 0xF << pos; + tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); + tmp &= ~mask; + tmp |= (init->func << pos); + i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); + } + + return; } /** @@ -249,19 +248,19 @@ void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) */ void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) { - gpio_init_t init; - - /* Fill GPIO_init_t structure with default parameter */ - init.mode = GPIO_MODE_OUTPUT; - init.odos = GPIO_PUSH_PULL; - init.pupd = GPIO_PUSH_UP; - init.odrv = GPIO_OUT_DRIVE_NORMAL; - init.flt = GPIO_FILTER_DISABLE; - init.type = GPIO_TYPE_CMOS; - init.func = GPIO_FUNC_1; - - ald_gpio_init(GPIOx, pin, &init); - return; + gpio_init_t init; + + /* Fill GPIO_init_t structure with default parameter */ + init.mode = GPIO_MODE_OUTPUT; + init.odos = GPIO_PUSH_PULL; + init.pupd = GPIO_PUSH_UP; + init.odrv = GPIO_OUT_DRIVE_NORMAL; + init.flt = GPIO_FILTER_DISABLE; + init.type = GPIO_TYPE_CMOS; + init.func = GPIO_FUNC_1; + + ald_gpio_init(GPIOx, pin, &init); + return; } /** @@ -271,10 +270,10 @@ void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) */ void ald_gpio_func_default(GPIO_TypeDef *GPIOx) { - WRITE_REG(GPIOx->FUNC0, 0x00); - WRITE_REG(GPIOx->FUNC1, 0x00); + WRITE_REG(GPIOx->FUNC0, 0x00); + WRITE_REG(GPIOx->FUNC1, 0x00); - return; + return; } /** @@ -288,67 +287,62 @@ void ald_gpio_func_default(GPIO_TypeDef *GPIOx) */ void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) { - uint8_t i; - uint8_t port; - - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); - assert_param(IS_FUNC_STATE(init->filter)); - assert_param(IS_EXTI_FLTCKS_TYPE(init->cks)); - - /* Get GPIO port */ - if (GPIOx == GPIOA) - port = 0x0; - else if (GPIOx == GPIOB) - port = 0x1; - else if (GPIOx == GPIOC) - port = 2; - else if (GPIOx == GPIOD) - port = 3; - else if (GPIOx == GPIOE) - port = 4; - else if (GPIOx == GPIOF) - port = 5; - else if (GPIOx == GPIOG) - port = 6; - else if (GPIOx == GPIOH) - port = 7; - else - port = 0; - - /* Get Pin index */ - for (i = 0; i < 16; ++i) - { - if (((pin >> i) & 0x1) == 0x1) - break; - } - - /* Select external interrupt line */ - if (i <= 7) - { - EXTI->EXTIPSR0 &= ~(0x7 << (i * 4)); - EXTI->EXTIPSR0 |= (port << (i * 4)); - } - else - { - i -= 8; - EXTI->EXTIPSR1 &= ~(0x7 << (i * 4)); - EXTI->EXTIPSR1 |= (port << (i * 4)); - } - - /* Configure filter parameter */ - if (init->filter == ENABLE) - { - SET_BIT(EXTI->EXTIFLTCR, pin); - MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS); - MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS); - } - else - { - CLEAR_BIT(EXTI->EXTIFLTCR, pin); - } - - return; + uint8_t i; + uint8_t port; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_FUNC_STATE(init->filter)); + assert_param(IS_EXTI_FLTCKS_TYPE(init->cks)); + + /* Get GPIO port */ + if (GPIOx == GPIOA) + port = 0x0; + else if (GPIOx == GPIOB) + port = 0x1; + else if (GPIOx == GPIOC) + port = 2; + else if (GPIOx == GPIOD) + port = 3; + else if (GPIOx == GPIOE) + port = 4; + else if (GPIOx == GPIOF) + port = 5; + else if (GPIOx == GPIOG) + port = 6; + else if (GPIOx == GPIOH) + port = 7; + else + port = 0; + + /* Get Pin index */ + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0x1) + break; + } + + /* Select external interrupt line */ + if (i <= 7) { + EXTI->EXTIPSR0 &= ~(0x7U << (i * 4)); + EXTI->EXTIPSR0 |= (port << (i * 4)); + } + else { + i -= 8; + EXTI->EXTIPSR1 &= ~(0x7U << (i * 4)); + EXTI->EXTIPSR1 |= (port << (i * 4)); + } + + /* Configure filter parameter */ + if (init->filter == ENABLE) { + SET_BIT(EXTI->EXTIFLTCR, pin); + MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS); + MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS); + } + else { + CLEAR_BIT(EXTI->EXTIFLTCR, pin); + } + + return; } /** * @} @@ -373,19 +367,16 @@ void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. * @param pin: Specifies the pin to read. * @retval The input pin value - * - BIT_SET - * - BIT_RESET */ uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) { - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); - if (READ_BIT(GPIOx->DIN, pin)) - return BIT_SET; - - else - return BIT_RESET; + if (READ_BIT(GPIOx->DIN, pin)) + return 1; + else + return 0; } /** @@ -397,15 +388,15 @@ uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) */ void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) { - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); - if ((val & (0x01)) == 0x00) - CLEAR_BIT(GPIOx->DOUT, pin); - else - SET_BIT(GPIOx->DOUT, pin); + if ((val & (0x01)) == 0x00) + CLEAR_BIT(GPIOx->DOUT, pin); + else + SET_BIT(GPIOx->DOUT, pin); - return; + return; } /** @@ -416,11 +407,11 @@ void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) */ void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) { - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); - WRITE_REG(GPIOx->BIR, pin); - return; + WRITE_REG(GPIOx->BIR, pin); + return; } /** @@ -431,42 +422,39 @@ void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) */ void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) { - uint32_t i, pos, mask, tmp, value; - - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); - - for (i = 0; i < 16; ++i) - { - if (((pin >> i) & 0x1) == 0) - continue; - - /* Get position and 2-bits mask */ - pos = i << 1; - mask = 0x3 << pos; - - /* Get the new direction */ - tmp = READ_REG(GPIOx->MODE); - value = (tmp >> pos) & 0x3; - - if ((value == 2) || (value == 3)) - value = 1; - else if (value == 1) - { - value = 2; - } - else - { - continue; /* do nothing */ - } - - /* Set PIN mode */ - tmp &= ~mask; - tmp |= (value << pos); - WRITE_REG(GPIOx->MODE, tmp); - } - - return; + uint32_t i, pos, mask, tmp, value; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Get the new direction */ + tmp = READ_REG(GPIOx->MODE); + value = (tmp >> pos) & 0x3; + + if ((value == 2) || (value == 3)) + value = 1; + else if (value == 1) { + value = 2; + } + else { + continue; /* do nothing */ + } + + /* Set PIN mode */ + tmp &= ~mask; + tmp |= (value << pos); + WRITE_REG(GPIOx->MODE, tmp); + } + + return; } /** @@ -479,13 +467,13 @@ void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) */ void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) { - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); - MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, UNLOCK_KEY << GPIO_LOCK_KEY_POSS); - WRITE_REG(GPIOx->LOCK, pin); + MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, UNLOCK_KEY << GPIO_LOCK_KEY_POSS); + WRITE_REG(GPIOx->LOCK, pin); - return; + return; } /** @@ -495,9 +483,9 @@ void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) */ uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx) { - assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PORT(GPIOx)); - return READ_REG(GPIOx->DIN); + return READ_REG(GPIOx->DIN); } /** @@ -508,10 +496,10 @@ uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx) */ void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) { - assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PORT(GPIOx)); - WRITE_REG(GPIOx->DOUT, val); - return; + WRITE_REG(GPIOx->DOUT, val); + return; } @@ -545,57 +533,47 @@ void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) */ void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status) { - assert_param(IS_GPIO_PIN(pin)); - assert_param(IS_TRIGGER_STYLE(style)); - assert_param(IS_FUNC_STATE(status)); - - if (status == ENABLE) - { - if (style == EXTI_TRIGGER_RISING_EDGE) - { - SET_BIT(EXTI->EXTIRER, pin); - } - else if (style == EXTI_TRIGGER_TRAILING_EDGE) - { - SET_BIT(EXTI->EXTIFER, pin); - } - else if (style == EXTI_TRIGGER_BOTH_EDGE) - { - SET_BIT(EXTI->EXTIRER, pin); - SET_BIT(EXTI->EXTIFER, pin); - } - else - { - ; /* do nothing */ - } - - WRITE_REG(EXTI->EXTICFR, 0xffff); - SET_BIT(EXTI->EXTIEN, pin); - } - else - { - if (style == EXTI_TRIGGER_RISING_EDGE) - { - CLEAR_BIT(EXTI->EXTIRER, pin); - } - else if (style == EXTI_TRIGGER_TRAILING_EDGE) - { - CLEAR_BIT(EXTI->EXTIFER, pin); - } - else if (style == EXTI_TRIGGER_BOTH_EDGE) - { - CLEAR_BIT(EXTI->EXTIRER, pin); - CLEAR_BIT(EXTI->EXTIFER, pin); - } - else - { - ; /* do nothing */ - } - - CLEAR_BIT(EXTI->EXTIEN, pin); - } - - return; + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_TRIGGER_STYLE(style)); + assert_param(IS_FUNC_STATE(status)); + + if (status == ENABLE) { + if (style == EXTI_TRIGGER_RISING_EDGE) { + SET_BIT(EXTI->EXTIRER, pin); + } + else if (style == EXTI_TRIGGER_TRAILING_EDGE) { + SET_BIT(EXTI->EXTIFER, pin); + } + else if (style == EXTI_TRIGGER_BOTH_EDGE) { + SET_BIT(EXTI->EXTIRER, pin); + SET_BIT(EXTI->EXTIFER, pin); + } + else { + ; /* do nothing */ + } + + WRITE_REG(EXTI->EXTICFR, 0xffff); + SET_BIT(EXTI->EXTIEN, pin); + } + else { + if (style == EXTI_TRIGGER_RISING_EDGE) { + CLEAR_BIT(EXTI->EXTIRER, pin); + } + else if (style == EXTI_TRIGGER_TRAILING_EDGE) { + CLEAR_BIT(EXTI->EXTIFER, pin); + } + else if (style == EXTI_TRIGGER_BOTH_EDGE) { + CLEAR_BIT(EXTI->EXTIRER, pin); + CLEAR_BIT(EXTI->EXTIFER, pin); + } + else { + ; /* do nothing */ + } + + CLEAR_BIT(EXTI->EXTIEN, pin); + } + + return; } /** @@ -607,12 +585,12 @@ void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, ty */ flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin) { - assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_PIN(pin)); - if (READ_BIT(EXTI->EXTIFLAG, pin)) - return SET; + if (READ_BIT(EXTI->EXTIFLAG, pin)) + return SET; - return RESET; + return RESET; } /** @@ -622,10 +600,10 @@ flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin) */ void ald_gpio_exti_clear_flag_status(uint16_t pin) { - assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_PIN(pin)); - WRITE_REG(EXTI->EXTICFR, pin); - return; + WRITE_REG(EXTI->EXTICFR, pin); + return; } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c index 1e5f32cde1248511f4c36ffcf1eb78c308aaac10..82faa3150285ec98b154dcef97989cf4493cbefa 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c @@ -177,13 +177,13 @@ * @{ */ #ifdef ALD_DMA - static void i2c_dma_master_send_cplt(void *argv); - static void i2c_dma_master_recv_cplt(void *argv); - static void i2c_dma_slave_send_cplt(void *argv); - static void i2c_dma_slave_recv_cplt(void *argv); - static void i2c_dma_mem_send_cplt(void *argv); - static void i2c_dma_mem_recv_cplt(void *argv); - static void i2c_dma_error(void *argv); +static void i2c_dma_master_send_cplt(void *argv); +static void i2c_dma_master_recv_cplt(void *argv); +static void i2c_dma_slave_send_cplt(void *argv); +static void i2c_dma_slave_recv_cplt(void *argv); +static void i2c_dma_mem_send_cplt(void *argv); +static void i2c_dma_mem_recv_cplt(void *argv); +static void i2c_dma_error(void *argv); #endif static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); @@ -192,7 +192,7 @@ static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, ui static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout); static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, - flag_status_t status, uint32_t timeout); + flag_status_t status, uint32_t timeout); static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, uint32_t timeout); static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout); static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeout); @@ -256,47 +256,54 @@ static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk); */ ald_status_t ald_i2c_init(i2c_handle_t *hperh) { - uint32_t freqrange = 0; - uint32_t pclk1 = 0; - - if (hperh == NULL) - return ERROR; - - /* Check the parameters */ - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_CLOCK_SPEED(hperh->init.clk_speed)); - assert_param(IS_I2C_DUTY_CYCLE(hperh->init.duty)); - assert_param(IS_I2C_OWN_ADDRESS1(hperh->init.own_addr1)); - assert_param(IS_I2C_ADDRESSING_MODE(hperh->init.addr_mode)); - assert_param(IS_I2C_GENERAL_CALL(hperh->init.general_call)); - assert_param(IS_I2C_NO_STRETCH(hperh->init.no_stretch)); - - if (hperh->init.dual_addr == I2C_DUALADDR_ENABLE) - assert_param(IS_I2C_OWN_ADDRESS2(hperh->init.own_addr2)); - - if (hperh->state == I2C_STATE_RESET) - hperh->lock = UNLOCK; - - hperh->state = I2C_STATE_BUSY; - pclk1 = ald_cmu_get_pclk1_clock(); - I2C_DISABLE(hperh); - - freqrange = I2C_FREQ_RANGE(pclk1); - WRITE_REG(hperh->perh->CON2, freqrange); - WRITE_REG(hperh->perh->RT, I2C_RISE_TIME(freqrange, hperh->init.clk_speed)); - WRITE_REG(hperh->perh->CKCFG, i2c_configure_speed(hperh, pclk1)); - WRITE_REG(hperh->perh->CON1, hperh->init.general_call); - SET_BIT(hperh->perh->CON1, hperh->init.no_stretch); - WRITE_REG(hperh->perh->ADDR1, (hperh->init.addr_mode | hperh->init.own_addr1)); - WRITE_REG(hperh->perh->ADDR2, (hperh->init.dual_addr | hperh->init.own_addr2)); - - I2C_ENABLE(hperh); - - hperh->error_code = I2C_ERROR_NONE; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - return OK; + uint32_t freqrange = 0; + uint32_t pclk1 = 0; + + if (hperh == NULL) + return ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_CLOCK_SPEED(hperh->init.clk_speed)); + assert_param(IS_I2C_DUTY_CYCLE(hperh->init.duty)); + assert_param(IS_I2C_OWN_ADDRESS1(hperh->init.own_addr1)); + assert_param(IS_I2C_ADDRESSING_MODE(hperh->init.addr_mode)); + assert_param(IS_I2C_GENERAL_CALL(hperh->init.general_call)); + assert_param(IS_I2C_NO_STRETCH(hperh->init.no_stretch)); + + if (hperh->init.dual_addr == I2C_DUALADDR_ENABLE) + assert_param(IS_I2C_OWN_ADDRESS2(hperh->init.own_addr2)); + + if (hperh->state == I2C_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = I2C_STATE_BUSY; + pclk1 = ald_cmu_get_pclk1_clock(); + I2C_DISABLE(hperh); + + freqrange = I2C_FREQ_RANGE(pclk1); + WRITE_REG(hperh->perh->CON2, freqrange); + WRITE_REG(hperh->perh->RT, I2C_RISE_TIME(freqrange, hperh->init.clk_speed)); + WRITE_REG(hperh->perh->CKCFG, i2c_configure_speed(hperh, pclk1)); + WRITE_REG(hperh->perh->CON1, hperh->init.general_call); + SET_BIT(hperh->perh->CON1, hperh->init.no_stretch); + + if (hperh->init.addr_mode == I2C_ADDR_7BIT) { + WRITE_REG(hperh->perh->ADDR1, (0x7FFF & hperh->init.own_addr1)); + } + else { + WRITE_REG(hperh->perh->ADDR1, (0x8000 | hperh->init.own_addr1)); + } + + WRITE_REG(hperh->perh->ADDR2, (hperh->init.dual_addr | hperh->init.own_addr2)); + + I2C_ENABLE(hperh); + + hperh->error_code = I2C_ERROR_NONE; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + return OK; } /** @@ -307,21 +314,21 @@ ald_status_t ald_i2c_init(i2c_handle_t *hperh) */ ald_status_t ald_i2c_reset(i2c_handle_t *hperh) { - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_TYPE(hperh->perh)); - hperh->state = I2C_STATE_BUSY; - I2C_DISABLE(hperh); + hperh->state = I2C_STATE_BUSY; + I2C_DISABLE(hperh); - hperh->error_code = I2C_ERROR_NONE; - hperh->state = I2C_STATE_RESET; - hperh->mode = I2C_MODE_NONE; + hperh->error_code = I2C_ERROR_NONE; + hperh->state = I2C_STATE_RESET; + hperh->mode = I2C_MODE_NONE; - __UNLOCK(hperh); + __UNLOCK(hperh); - return OK; + return OK; } /** * @} @@ -399,86 +406,75 @@ ald_status_t ald_i2c_reset(i2c_handle_t *hperh) ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size, uint32_t timeout) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - - if (i2c_master_req_write(hperh, dev_addr, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - I2C_CLEAR_ADDRFLAG(hperh); - - while (size > 0) - { - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - hperh->perh->DATA = (*buf++); - --size; - - if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) - { - hperh->perh->DATA = (*buf++); - --size; - } - } - - if (i2c_wait_btf_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + + if (i2c_master_req_write(hperh, dev_addr, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + I2C_CLEAR_ADDRFLAG(hperh); + + while (size > 0) { + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->perh->DATA = (*buf++); + --size; + + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { + hperh->perh->DATA = (*buf++); + --size; + } + } + + if (i2c_wait_btf_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return OK; } @@ -493,154 +489,136 @@ ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint32_t timeout) + uint16_t size, uint32_t timeout) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - __LOCK(hperh); - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - - if (i2c_master_req_read(hperh, dev_addr, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (size == 1) - { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __enable_irq(); - } - else if (size == 2) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - __disable_irq(); - I2C_CLEAR_ADDRFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __enable_irq(); - } - else - { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - } - - while (size > 3) - { - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_TIMEOUT) - { - __UNLOCK(hperh); - return TIMEOUT; - } - else - { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - --size; - - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) - { - (*buf++) = hperh->perh->DATA; - --size; - } - } - - switch (size) - { - case 1: - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_TIMEOUT) - { - __UNLOCK(hperh); - return TIMEOUT; - } - else - { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - break; - - case 2: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - __disable_irq(); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; - - case 3: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - (*buf++) = hperh->perh->DATA; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - __enable_irq(); - return TIMEOUT; - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; - - default : - break; - } - - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + + if (i2c_master_req_read(hperh, dev_addr, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (size == 1) { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __enable_irq(); + } + else if (size == 2) { + SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + __disable_irq(); + I2C_CLEAR_ADDRFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __enable_irq(); + } + else { + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + } + + while (size > 3) { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_TIMEOUT) { + __UNLOCK(hperh); + return TIMEOUT; + } + else { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + --size; + + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) { + (*buf++) = hperh->perh->DATA; + --size; + } + } + + switch (size) { + case 1: + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_TIMEOUT) { + __UNLOCK(hperh); + return TIMEOUT; + } + else { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + break; + + case 2: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + __disable_irq(); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; + + case 3: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + (*buf++) = hperh->perh->DATA; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { + __UNLOCK(hperh); + __enable_irq(); + return TIMEOUT; + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; + + default : + break; + } + + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + return OK; } /** @@ -654,85 +632,76 @@ ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t */ ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - - if (hperh->init.addr_mode == I2C_ADDR_10BIT) - { - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - } - - while (size > 0) - { - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - hperh->perh->DATA = (*buf++); - --size; - - if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) - { - hperh->perh->DATA = (*buf++); - --size; - } - } - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + + if (hperh->init.addr_mode == I2C_ADDR_10BIT) { + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + } + + while (size > 0) { + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->perh->DATA = (*buf++); + --size; + + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { + hperh->perh->DATA = (*buf++); + --size; + } + } + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + return OK; } /** @@ -746,83 +715,73 @@ ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size */ ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - - while (size > 0) - { - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) - { - hperh->perh->CON1 &= ~I2C_CON1_ACKEN; - - if (hperh->error_code == I2C_ERROR_TIMEOUT) - { - __UNLOCK(hperh); - return TIMEOUT; - } - else - { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - --size; - - if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) - { - (*buf++) = hperh->perh->DATA; - --size; - } - } - - if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) - { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - __I2C_CLEAR_STOPFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + + while (size > 0) { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { + hperh->perh->CON1 &= (uint32_t)(~I2C_CON1_ACKEN); + + if (hperh->error_code == I2C_ERROR_TIMEOUT) { + __UNLOCK(hperh); + return TIMEOUT; + } + else { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + --size; + + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { + (*buf++) = hperh->perh->DATA; + --size; + } + } + + if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + __I2C_CLEAR_STOPFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + return OK; } /** @@ -836,52 +795,49 @@ ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size */ ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - I2C_CLEAR_ADDRFLAG(hperh); - - __UNLOCK(hperh); - - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + I2C_CLEAR_ADDRFLAG(hperh); + + __UNLOCK(hperh); + + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + return OK; } /** @@ -895,68 +851,62 @@ ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, u */ ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (hperh->xfer_count == 1) - { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - } - else if (hperh->xfer_count == 2) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - I2C_CLEAR_ADDRFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - } - else - { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - } - - __UNLOCK(hperh); - - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (hperh->xfer_count == 1) { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + } + else if (hperh->xfer_count == 2) { + SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + I2C_CLEAR_ADDRFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + } + else { + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + } + + __UNLOCK(hperh); + + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + return OK; } /** @@ -969,37 +919,37 @@ ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, u */ ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) { - if (hperh->state != I2C_STATE_READY) - return BUSY; + if (hperh->state != I2C_STATE_READY) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL) || (size == 0)) + return ERROR; - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; - assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_TYPE(hperh->perh)); - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __UNLOCK(hperh); + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __UNLOCK(hperh); - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - return OK; + return OK; } /** @@ -1012,37 +962,37 @@ ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_ */ ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) { - if (hperh->state != I2C_STATE_READY) - return BUSY; + if (hperh->state != I2C_STATE_READY) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL) || (size == 0)) + return ERROR; - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; - assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_TYPE(hperh->perh)); - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __UNLOCK(hperh); + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __UNLOCK(hperh); - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - return OK; + return OK; } #ifdef ALD_DMA @@ -1057,67 +1007,64 @@ ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_ * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint8_t channel) + uint16_t size, uint8_t channel) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = i2c_dma_master_send_cplt; - hperh->hdmatx.cplt_arg = hperh; - hperh->hdmatx.err_cbk = i2c_dma_error; - hperh->hdmatx.err_arg = hperh; - - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmatx); - - if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - I2C_CLEAR_ADDRFLAG(hperh); - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_master_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + I2C_CLEAR_ADDRFLAG(hperh); + __UNLOCK(hperh); + return OK; } /** @@ -1131,72 +1078,69 @@ ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint8_t channel) + uint16_t size, uint8_t channel) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = i2c_dma_master_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = i2c_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmarx); - - if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (size == 1) - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - else - SET_BIT(hperh->perh->CON2, I2C_CON2_LDMA); - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - I2C_CLEAR_ADDRFLAG(hperh); - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_master_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (size == 1) + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + else + SET_BIT(hperh->perh->CON2, I2C_CON2_LDMA); + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + I2C_CLEAR_ADDRFLAG(hperh); + __UNLOCK(hperh); + return OK; } /** @@ -1210,76 +1154,72 @@ ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, */ ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = i2c_dma_slave_send_cplt; - hperh->hdmatx.cplt_arg = hperh; - hperh->hdmatx.err_cbk = i2c_dma_error; - hperh->hdmatx.err_arg = hperh; - - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmatx); - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.addr_mode == I2C_ADDR_7BIT) - { - I2C_CLEAR_ADDRFLAG(hperh); - } - else - { - I2C_CLEAR_ADDRFLAG(hperh); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - } - - __UNLOCK(hperh); - - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_slave_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.addr_mode == I2C_ADDR_7BIT) { + I2C_CLEAR_ADDRFLAG(hperh); + } + else { + I2C_CLEAR_ADDRFLAG(hperh); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + } + + __UNLOCK(hperh); + + return OK; } /** @@ -1293,59 +1233,58 @@ ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16 */ ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = i2c_dma_slave_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = i2c_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmarx); - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_slave_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + __UNLOCK(hperh); + return OK; } #endif @@ -1362,89 +1301,78 @@ ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16 * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout) + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - - if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - while (size > 0) - { - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - hperh->perh->DATA = (*buf++); - --size; - - if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) - { - hperh->perh->DATA = (*buf++); - --size; - } - } - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - ald_delay_ms(10); - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + while (size > 0) { + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->perh->DATA = (*buf++); + --size; + + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { + hperh->perh->DATA = (*buf++); + --size; + } + } + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + ald_delay_ms(10); + __UNLOCK(hperh); + return OK; } /** @@ -1460,155 +1388,137 @@ ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint32_t timeout) + uint8_t *buf, uint16_t size, uint32_t timeout) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - - if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (size == 1) - { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __enable_irq(); - } - else if (size == 2) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - __disable_irq(); - I2C_CLEAR_ADDRFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __enable_irq(); - } - else - { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - } - - while (size > 3) - { - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_TIMEOUT) - { - __UNLOCK(hperh); - return TIMEOUT; - } - else - { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - --size; - - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) - { - (*buf++) = hperh->perh->DATA; - --size; - } - } - - switch (size) - { - case 1: - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_TIMEOUT) - { - __UNLOCK(hperh); - return TIMEOUT; - } - else - { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - break; - - case 2: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - __disable_irq(); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; - - case 3: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - (*buf++) = hperh->perh->DATA; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - __enable_irq(); - return TIMEOUT; - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; - - default: - break; - } - - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + + if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (size == 1) { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __enable_irq(); + } + else if (size == 2) { + SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + __disable_irq(); + I2C_CLEAR_ADDRFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __enable_irq(); + } + else { + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + } + + while (size > 3) { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_TIMEOUT) { + __UNLOCK(hperh); + return TIMEOUT; + } + else { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + --size; + + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) { + (*buf++) = hperh->perh->DATA; + --size; + } + } + + switch (size) { + case 1: + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_TIMEOUT) { + __UNLOCK(hperh); + return TIMEOUT; + } + else { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + break; + + case 2: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + __disable_irq(); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; + + case 3: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + (*buf++) = hperh->perh->DATA; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { + __UNLOCK(hperh); + __enable_irq(); + return TIMEOUT; + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; + + default: + break; + } + + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + return OK; } /** @@ -1623,54 +1533,51 @@ ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t m * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - __UNLOCK(hperh); - - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + __UNLOCK(hperh); + + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + + return OK; } /** @@ -1685,72 +1592,66 @@ ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uin * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (hperh->xfer_count == 1) - { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - } - else if (hperh->xfer_count == 2) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - I2C_CLEAR_ADDRFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - } - else - { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - } - - __UNLOCK(hperh); - - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (hperh->xfer_count == 1) { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + } + else if (hperh->xfer_count == 2) { + SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + I2C_CLEAR_ADDRFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + } + else { + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + } + + __UNLOCK(hperh); + + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + + return OK; } #ifdef ALD_DMA @@ -1767,67 +1668,64 @@ ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel) + uint8_t *buf, uint16_t size, uint8_t channel) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = i2c_dma_mem_send_cplt; - hperh->hdmatx.cplt_arg = hperh; - hperh->hdmatx.err_cbk = i2c_dma_error; - hperh->hdmatx.err_arg = hperh; - ald_dma_config_struct(&hperh->hdmatx.config); - - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmatx); - - if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_mem_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + ald_dma_config_struct(&hperh->hdmatx.config); + + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + __UNLOCK(hperh); + return OK; } /** @@ -1843,73 +1741,70 @@ ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, ui * @retval Status, see @ref ald_status_t. */ ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel) + uint8_t *buf, uint16_t size, uint8_t channel) { - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = i2c_dma_mem_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = i2c_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - ald_dma_config_struct(&hperh->hdmarx.config); - - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmarx); - - if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - __UNLOCK(hperh); - return ERROR; - } - else - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (size == 1) - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - else - SET_BIT(hperh->perh->CON2, I2C_CON2_LDMA); - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - I2C_CLEAR_ADDRFLAG(hperh); - __UNLOCK(hperh); - return OK; + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_mem_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + ald_dma_config_struct(&hperh->hdmarx.config); + + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (size == 1) + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + else + SET_BIT(hperh->perh->CON2, I2C_CON2_LDMA); + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + I2C_CLEAR_ADDRFLAG(hperh); + __UNLOCK(hperh); + return OK; } #endif @@ -1925,88 +1820,79 @@ ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uin */ ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout) { - uint32_t tickstart = 0; - uint32_t tmp1 = 0; - uint32_t tmp2 = 0; - uint32_t tmp3 = 0; - uint32_t I2C_Trials = 1; - - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY; - hperh->error_code = I2C_ERROR_NONE; - - do - { - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); - tickstart = ald_get_tick(); - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); - tmp2 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); - tmp3 = hperh->state; - - while ((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != I2C_STATE_TIMEOUT)) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - hperh->state = I2C_STATE_TIMEOUT; - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); - tmp2 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); - tmp3 = hperh->state; - } - - hperh->state = I2C_STATE_READY; - - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR) == SET) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - I2C_CLEAR_ADDRFLAG(hperh); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, - I2C_TIMEOUT_BUSY_FLAG) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return OK; - } - else - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, - I2C_TIMEOUT_BUSY_FLAG) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - while (I2C_Trials++ < trials); - - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return OK; + uint32_t tickstart = 0; + uint32_t tmp1 = 0; + uint32_t tmp2 = 0; + uint32_t tmp3 = 0; + uint32_t I2C_Trials = 1; + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY; + hperh->error_code = I2C_ERROR_NONE; + + do { + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); + tickstart = ald_get_tick(); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); + tmp2 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); + tmp3 = hperh->state; + + while ((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != I2C_STATE_TIMEOUT)) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) + hperh->state = I2C_STATE_TIMEOUT; + + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); + tmp2 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); + tmp3 = hperh->state; + } + hperh->state = I2C_STATE_READY; + + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR) == SET) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + I2C_CLEAR_ADDRFLAG(hperh); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, + I2C_TIMEOUT_BUSY_FLAG) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return OK; + } + else { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, + I2C_TIMEOUT_BUSY_FLAG) != OK) { + __UNLOCK(hperh); + return TIMEOUT; + } + } + } while (I2C_Trials++ < trials); + + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return OK; } /** * @} @@ -2040,16 +1926,16 @@ ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uin */ void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state) { - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_IT_TYPE(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - SET_BIT((hperh)->perh->CON2, (it)); - else - CLEAR_BIT((hperh)->perh->CON2, (it)); + if (state == ENABLE) + SET_BIT((hperh)->perh->CON2, (it)); + else + CLEAR_BIT((hperh)->perh->CON2, (it)); - return; + return; } /** @@ -2063,23 +1949,21 @@ void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func */ flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) { - flag_status_t state = RESET; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_FLAG(flag)); - - if ((flag & 0xFF0000) == 0) - { - if ((hperh->perh->STAT1 & flag) == flag) - state = SET; - } - else - { - if ((hperh->perh->STAT2 & (flag >> 16)) == (flag >> 16)) - state = SET; - } - - return state; + flag_status_t state = RESET; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_FLAG(flag)); + + if ((flag & 0xFF0000) == 0) { + if ((hperh->perh->STAT1 & flag) == flag) + state = SET; + } + else { + if ((hperh->perh->STAT2 & (flag >> 16)) == (flag >> 16)) + state = SET; + } + + return state; } /** @@ -2093,13 +1977,13 @@ flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) */ flag_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it) { - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_IT_TYPE(it)); + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT_TYPE(it)); - if ((hperh->perh->CON2 & it) == it) - return SET; - else - return RESET; + if ((hperh->perh->CON2 & it) == it) + return SET; + else + return RESET; } /** @@ -2111,15 +1995,15 @@ flag_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it) */ void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) { - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_FLAG(flag)); + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_FLAG(flag)); - if (flag > 65535) - return; + if (flag > 65535) + return; - hperh->perh->STAT1 = (hperh->perh->STAT1 & (~flag)); + hperh->perh->STAT1 = (hperh->perh->STAT1 & (uint32_t)(~flag)); - return; + return; } @@ -2131,7 +2015,7 @@ void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) */ i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** @@ -2142,7 +2026,7 @@ i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh) */ uint32_t ald_i2c_get_error(i2c_handle_t *hperh) { - return hperh->error_code; + return hperh->error_code; } /** * @} @@ -2160,86 +2044,40 @@ uint32_t ald_i2c_get_error(i2c_handle_t *hperh) */ void ald_i2c_ev_irq_handler(i2c_handle_t *hperh) { - uint32_t tmp1 = 0; - uint32_t tmp2 = 0; - uint32_t tmp3 = 0; - uint32_t tmp4 = 0; - - if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) - { - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_TRA) == SET) - { - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); - - if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) - i2c_master_send_txe(hperh); - else if ((tmp3 == SET) && (tmp4 == SET)) - i2c_master_send_btf(hperh); - } - - /* I2C in mode Receiver */ - else - { - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); - - if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) - i2c_master_recv_rxne(hperh); - else if ((tmp3 == SET) && (tmp4 == SET)) - i2c_master_recv_btf(hperh); - } - } - - /* Slave mode selected */ - else - { - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); - tmp2 = ald_i2c_get_it_status(hperh, (I2C_IT_EVT)); - tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF); - tmp4 = ald_i2c_get_flag_status(hperh, I2C_FLAG_TRA); - - if ((tmp1 == SET) && (tmp2 == SET)) - { - i2c_slave_addr(hperh); - } - else if ((tmp3 == SET) && (tmp2 == SET)) - { - i2c_slave_stopf(hperh); - } - - /* I2C in mode Transmitter */ - else if (tmp4 == SET) - { - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); - - if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) - i2c_slave_send_txe(hperh); - else if ((tmp3 == SET) && (tmp4 == SET)) - i2c_slave_send_btf(hperh); - } - - /* I2C in mode Receiver */ - else - { - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); - - if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) - i2c_slave_recv_rxne(hperh); - else if ((tmp3 == SET) && (tmp4 == SET)) - i2c_slave_recv_btf(hperh); - } - } + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR) == SET) + i2c_slave_addr(hperh); + + if ((ald_i2c_get_it_status(hperh, I2C_IT_BUF) == SET) && (ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE) == SET)) { + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) + i2c_master_send_txe(hperh); + else + i2c_slave_send_txe(hperh); + } + + if ((ald_i2c_get_it_status(hperh, I2C_IT_BUF) == SET) && (ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE) == SET)) { + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) + i2c_master_recv_rxne(hperh); + else + i2c_slave_recv_rxne(hperh); + } + + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) { + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_TRA) == SET) { + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) + i2c_master_send_btf(hperh); + else + i2c_slave_send_btf(hperh); + } + else { + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) + i2c_master_recv_btf(hperh); + else + i2c_slave_recv_btf(hperh); + } + } + + if ((hperh->mode == I2C_MODE_SLAVE) && (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == SET)) + i2c_slave_stopf(hperh); } /** @@ -2250,72 +2088,63 @@ void ald_i2c_ev_irq_handler(i2c_handle_t *hperh) */ void ald_i2c_er_irq_handler(i2c_handle_t *hperh) { - uint32_t tmp1 = 0; - uint32_t tmp2 = 0; - uint32_t tmp3 = 0; - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BERR); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); - - /* I2C Bus error interrupt occurred */ - if ((tmp1 == SET) && (tmp2 == SET)) - { - hperh->error_code |= I2C_ERROR_BERR; - ald_i2c_clear_flag_status(hperh, I2C_FLAG_BERR); - SET_BIT(hperh->perh->CON1, I2C_CON1_SRST); - } - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ARLO); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); - - /* I2C Arbitration Loss error interrupt occurred */ - if ((tmp1 == SET) && (tmp2 == SET)) - { - hperh->error_code |= I2C_ERROR_ARLO; - ald_i2c_clear_flag_status(hperh, I2C_FLAG_ARLO); - } - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); - - /* I2C Acknowledge failure error interrupt occurred */ - if ((tmp1 == SET) && (tmp2 == SET)) - { - tmp1 = hperh->mode; - tmp2 = hperh->xfer_count; - tmp3 = hperh->state; - - if ((tmp1 == I2C_MODE_SLAVE) && (tmp2 == 0) && \ - (tmp3 == I2C_STATE_BUSY_TX)) - { - i2c_slave_af(hperh); - } - else - { - hperh->error_code |= I2C_ERROR_AF; - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - } - } - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_OVR); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); - - /* I2C Over-Run/Under-Run interrupt occurred */ - if ((tmp1 == SET) && (tmp2 == SET)) - { - hperh->error_code |= I2C_ERROR_OVR; - ald_i2c_clear_flag_status(hperh, I2C_FLAG_OVR); - } - - if (hperh->error_code != I2C_ERROR_NONE) - { - hperh->state = I2C_STATE_READY; - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - if (hperh->error_callback) - hperh->error_callback(hperh); - } + uint32_t tmp1 = 0; + uint32_t tmp2 = 0; + uint32_t tmp3 = 0; + + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BERR); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); + + /* I2C Bus error interrupt occurred */ + if ((tmp1 == SET) && (tmp2 == SET)) { + hperh->error_code |= I2C_ERROR_BERR; + ald_i2c_clear_flag_status(hperh, I2C_FLAG_BERR); + SET_BIT(hperh->perh->CON1, I2C_CON1_SRST); + } + + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ARLO); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); + + /* I2C Arbitration Loss error interrupt occurred */ + if ((tmp1 == SET) && (tmp2 == SET)) { + hperh->error_code |= I2C_ERROR_ARLO; + ald_i2c_clear_flag_status(hperh, I2C_FLAG_ARLO); + } + + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); + + /* I2C Acknowledge failure error interrupt occurred */ + if ((tmp1 == SET) && (tmp2 == SET)) { + tmp1 = hperh->mode; + tmp2 = hperh->xfer_count; + tmp3 = hperh->state; + if ((tmp1 == I2C_MODE_SLAVE) && (tmp2 == 0) && \ + (tmp3 == I2C_STATE_BUSY_TX)) { + i2c_slave_af(hperh); + } + else { + hperh->error_code |= I2C_ERROR_AF; + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); + } + } + + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_OVR); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); + + /* I2C Over-Run/Under-Run interrupt occurred */ + if ((tmp1 == SET) && (tmp2 == SET)) { + hperh->error_code |= I2C_ERROR_OVR; + ald_i2c_clear_flag_status(hperh, I2C_FLAG_OVR); + } + + if (hperh->error_code != I2C_ERROR_NONE) { + hperh->state = I2C_STATE_READY; + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + if (hperh->error_callback) + hperh->error_callback(hperh); + } } /** * @} @@ -2337,17 +2166,15 @@ void ald_i2c_er_irq_handler(i2c_handle_t *hperh) */ static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh) { - if (hperh->xfer_count == 0) - { - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - } - else - { - hperh->perh->DATA = (*hperh->p_buff++); - hperh->xfer_count--; - } - - return OK; + if (hperh->xfer_count == 0) { + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + } + else { + hperh->perh->DATA = (*hperh->p_buff++); + hperh->xfer_count--; + } + + return OK; } /** @@ -2358,35 +2185,27 @@ static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh) */ static ald_status_t i2c_master_send_btf(i2c_handle_t *hperh) { - if (hperh->xfer_count != 0) - { - hperh->perh->DATA = (*hperh->p_buff++); - hperh->xfer_count--; - } - else - { - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - - if (hperh->mode == I2C_MODE_MEM) - { - hperh->state = I2C_STATE_READY; - - if (hperh->mem_tx_cplt_cbk) - hperh->mem_tx_cplt_cbk(hperh); - } - else - { - hperh->state = I2C_STATE_READY; - - if (hperh->master_tx_cplt_cbk) - hperh->master_tx_cplt_cbk(hperh); - } - } - - return OK; + if (hperh->xfer_count != 0) { + hperh->perh->DATA = (*hperh->p_buff++); + hperh->xfer_count--; + } + else { + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + if (hperh->mode == I2C_MODE_MEM) { + hperh->state = I2C_STATE_READY; + if (hperh->mem_tx_cplt_cbk) + hperh->mem_tx_cplt_cbk(hperh); + } + else { + hperh->state = I2C_STATE_READY; + if (hperh->master_tx_cplt_cbk) + hperh->master_tx_cplt_cbk(hperh); + } + } + return OK; } /** @@ -2397,44 +2216,35 @@ static ald_status_t i2c_master_send_btf(i2c_handle_t *hperh) */ static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh) { - uint32_t tmp = 0; - - tmp = hperh->xfer_count; - - if (tmp > 3) - { - (*hperh->p_buff++) = hperh->perh->DATA; - hperh->xfer_count--; - } - else if ((tmp == 2) || (tmp == 3)) - { - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - } - else - { - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - (*hperh->p_buff++) = hperh->perh->DATA; - hperh->xfer_count--; - - if (hperh->mode == I2C_MODE_MEM) - { - hperh->state = I2C_STATE_READY; - - if (hperh->mem_rx_cplt_cbk) - hperh->mem_rx_cplt_cbk(hperh); - } - else - { - hperh->state = I2C_STATE_READY; - - if (hperh->master_rx_cplt_cbk) - hperh->master_rx_cplt_cbk(hperh); - } - } - - return OK; + uint32_t tmp = 0; + + tmp = hperh->xfer_count; + if (tmp > 3) { + (*hperh->p_buff++) = hperh->perh->DATA; + hperh->xfer_count--; + } + else if ((tmp == 2) || (tmp == 3)) { + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + } + else { + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + (*hperh->p_buff++) = hperh->perh->DATA; + hperh->xfer_count--; + + if (hperh->mode == I2C_MODE_MEM) { + hperh->state = I2C_STATE_READY; + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } + else { + hperh->state = I2C_STATE_READY; + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } + } + return OK; } /** @@ -2445,45 +2255,37 @@ static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh) */ static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh) { - if (hperh->xfer_count == 3) - { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } - else if (hperh->xfer_count == 2) - { - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - - if (hperh->mode == I2C_MODE_MEM) - { - hperh->state = I2C_STATE_READY; - - if (hperh->mem_rx_cplt_cbk) - hperh->mem_rx_cplt_cbk(hperh); - } - else - { - hperh->state = I2C_STATE_READY; - - if (hperh->master_rx_cplt_cbk) - hperh->master_rx_cplt_cbk(hperh); - } - } - else - { - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } - - return OK; + if (hperh->xfer_count == 3) { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } + else if (hperh->xfer_count == 2) { + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + + if (hperh->mode == I2C_MODE_MEM) { + hperh->state = I2C_STATE_READY; + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } + else { + hperh->state = I2C_STATE_READY; + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } + } + else { + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } + return OK; } /** @@ -2494,13 +2296,11 @@ static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh) { - if (hperh->xfer_count != 0) - { - hperh->perh->DATA = (*hperh->p_buff++); - --hperh->xfer_count; - } - - return OK; + if (hperh->xfer_count != 0) { + hperh->perh->DATA = (*hperh->p_buff++); + --hperh->xfer_count; + } + return OK; } /** @@ -2511,13 +2311,11 @@ static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_send_btf(i2c_handle_t *hperh) { - if (hperh->xfer_count != 0) - { - hperh->perh->DATA = (*hperh->p_buff++); - --hperh->xfer_count; - } - - return OK; + if (hperh->xfer_count != 0) { + hperh->perh->DATA = (*hperh->p_buff++); + --hperh->xfer_count; + } + return OK; } /** @@ -2528,13 +2326,11 @@ static ald_status_t i2c_slave_send_btf(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh) { - if (hperh->xfer_count != 0) - { - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } - - return OK; + if (hperh->xfer_count != 0) { + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } + return OK; } /** @@ -2545,13 +2341,11 @@ static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_recv_btf(i2c_handle_t *hperh) { - if (hperh->xfer_count != 0) - { - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } - - return OK; + if (hperh->xfer_count != 0) { + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } + return OK; } /** @@ -2562,9 +2356,9 @@ static ald_status_t i2c_slave_recv_btf(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_addr(i2c_handle_t *hperh) { - I2C_CLEAR_ADDRFLAG(hperh); + I2C_CLEAR_ADDRFLAG(hperh); - return OK; + return OK; } /** @@ -2575,24 +2369,23 @@ static ald_status_t i2c_slave_addr(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh) { - if (hperh->xfer_count != 0) - { - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } + if (hperh->xfer_count != 0) { + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - __I2C_CLEAR_STOPFLAG(hperh); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + __I2C_CLEAR_STOPFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - hperh->state = I2C_STATE_READY; + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + hperh->state = I2C_STATE_READY; - if (hperh->slave_rx_cplt_cbk) - hperh->slave_rx_cplt_cbk(hperh); + if (hperh->slave_rx_cplt_cbk) + hperh->slave_rx_cplt_cbk(hperh); - return OK; + return OK; } /** @@ -2603,18 +2396,18 @@ static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_af(i2c_handle_t *hperh) { - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - hperh->state = I2C_STATE_READY; + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + hperh->state = I2C_STATE_READY; - if (hperh->slave_tx_cplt_cbk) - hperh->slave_tx_cplt_cbk(hperh); + if (hperh->slave_tx_cplt_cbk) + hperh->slave_tx_cplt_cbk(hperh); - return OK; + return OK; } /** @@ -2627,43 +2420,36 @@ static ald_status_t i2c_slave_af(i2c_handle_t *hperh) */ static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) { - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - if (hperh->init.addr_mode == I2C_ADDR_7BIT) - { - hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); - } - else - { - hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - return ERROR; - } - else - { - return TIMEOUT; - } - } - - hperh->perh->DATA = I2C_10BIT_ADDRESS(dev_addr); - } - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - return OK; + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + if (hperh->init.addr_mode == I2C_ADDR_7BIT) { + hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); + } + else { + hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + return ERROR; + } + else { + return TIMEOUT; + } + } + + hperh->perh->DATA = I2C_10BIT_ADDRESS(dev_addr); + } + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + return OK; } /** @@ -2676,57 +2462,51 @@ static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, */ static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - if (hperh->init.addr_mode == I2C_ADDR_7BIT) - { - hperh->perh->DATA = I2C_7BIT_ADD_READ(dev_addr); - } - else - { - hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - hperh->perh->DATA = I2C_10BIT_ADDRESS(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - hperh->perh->DATA = I2C_10BIT_HEADER_READ(dev_addr); - } - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - return OK; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + if (hperh->init.addr_mode == I2C_ADDR_7BIT) { + hperh->perh->DATA = I2C_7BIT_ADD_READ(dev_addr); + } + else { + hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr); + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + hperh->perh->DATA = I2C_10BIT_ADDRESS(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + hperh->perh->DATA = I2C_10BIT_HEADER_READ(dev_addr); + } + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + return OK; } /** @@ -2741,63 +2521,51 @@ static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, */ static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) { - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - { - return TIMEOUT; - } - - hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else - { - return TIMEOUT; - } - } - - if (add_size == I2C_MEMADD_SIZE_8BIT) - { - hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); - } - else - { - hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr); - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else - { - return TIMEOUT; - } - } - - hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); - } - - return OK; + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) { + return TIMEOUT; + } + + hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else { + return TIMEOUT; + } + } + + if (add_size == I2C_MEMADD_SIZE_8BIT) { + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); + } + else { + hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr); + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else { + return TIMEOUT; + } + } + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); + } + + return OK; } /** @@ -2812,90 +2580,76 @@ static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, ui */ static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else - { - return TIMEOUT; - } - } - - if (add_size == I2C_MEMADD_SIZE_8BIT) - { - hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); - } - else - { - hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr); - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else - { - return TIMEOUT; - } - } - - hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); - } - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else - { - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - hperh->perh->DATA = I2C_7BIT_ADD_READ(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - return OK; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else { + return TIMEOUT; + } + } + + if (add_size == I2C_MEMADD_SIZE_8BIT) { + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); + } + else { + hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else { + return TIMEOUT; + } + } + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); + } + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else { + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + hperh->perh->DATA = I2C_7BIT_ADD_READ(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + return OK; } #ifdef ALD_DMA @@ -2906,28 +2660,26 @@ static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uin */ static void i2c_dma_master_send_cplt(void *argv) { - i2c_handle_t *hperh = (i2c_handle_t *)argv; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != OK) - hperh->error_code |= I2C_ERROR_TIMEOUT; - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) - { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else - { - if (hperh->master_tx_cplt_cbk) - hperh->master_tx_cplt_cbk(hperh); - } + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != OK) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->master_tx_cplt_cbk) + hperh->master_tx_cplt_cbk(hperh); + } } /** @@ -2937,30 +2689,28 @@ static void i2c_dma_master_send_cplt(void *argv) */ static void i2c_dma_slave_send_cplt(void *argv) { - i2c_handle_t *hperh = (i2c_handle_t *)argv; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != OK) - hperh->error_code |= I2C_ERROR_TIMEOUT; - - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) - { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else - { - if (hperh->slave_tx_cplt_cbk) - hperh->slave_tx_cplt_cbk(hperh); - } + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != OK) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->slave_tx_cplt_cbk) + hperh->slave_tx_cplt_cbk(hperh); + } } /** @@ -2970,27 +2720,25 @@ static void i2c_dma_slave_send_cplt(void *argv) */ static void i2c_dma_master_recv_cplt(void *argv) { - i2c_handle_t *hperh = (i2c_handle_t *)argv; - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_LDMA); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) - { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else - { - if (hperh->master_rx_cplt_cbk) - hperh->master_rx_cplt_cbk(hperh); - } + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_LDMA); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } } /** @@ -3000,35 +2748,32 @@ static void i2c_dma_master_recv_cplt(void *argv) */ static void i2c_dma_slave_recv_cplt(void *argv) { - i2c_handle_t *hperh = (i2c_handle_t *)argv; - - if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) - { - if (hperh->error_code == I2C_ERROR_AF) - hperh->error_code |= I2C_ERROR_AF; - else - hperh->error_code |= I2C_ERROR_TIMEOUT; - } - - __I2C_CLEAR_STOPFLAG(hperh); - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) - { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else - { - if (hperh->slave_rx_cplt_cbk) - hperh->slave_rx_cplt_cbk(hperh); - } + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) + hperh->error_code |= I2C_ERROR_AF; + else + hperh->error_code |= I2C_ERROR_TIMEOUT; + } + + __I2C_CLEAR_STOPFLAG(hperh); + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->slave_rx_cplt_cbk) + hperh->slave_rx_cplt_cbk(hperh); + } } /** @@ -3038,28 +2783,26 @@ static void i2c_dma_slave_recv_cplt(void *argv) */ static void i2c_dma_mem_send_cplt(void *argv) { - i2c_handle_t *hperh = (i2c_handle_t *)argv; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != OK) - hperh->error_code |= I2C_ERROR_TIMEOUT; - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) - { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else - { - if (hperh->mem_tx_cplt_cbk) - hperh->mem_tx_cplt_cbk(hperh); - } + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != OK) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->mem_tx_cplt_cbk) + hperh->mem_tx_cplt_cbk(hperh); + } } /** @@ -3069,27 +2812,25 @@ static void i2c_dma_mem_send_cplt(void *argv) */ static void i2c_dma_mem_recv_cplt(void *argv) { - i2c_handle_t *hperh = (i2c_handle_t *)argv; - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_LDMA); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) - { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else - { - if (hperh->mem_rx_cplt_cbk) - hperh->mem_rx_cplt_cbk(hperh); - } + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_LDMA); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } } #endif @@ -3102,31 +2843,32 @@ static void i2c_dma_mem_recv_cplt(void *argv) */ static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk) { - uint32_t tmp1 = 0; - - if (hperh->init.clk_speed <= I2C_STANDARD_MODE_MAX_CLK) - { - tmp1 = (i2c_clk / (hperh->init.clk_speed << 1)); - - if ((tmp1 & I2C_CKCFG_CLKSET) < 4) - return 4; - else - return tmp1; - } - else - { - tmp1 = I2C_CKCFG_CLKMOD; - - if (hperh->init.duty == I2C_DUTYCYCLE_2) - tmp1 |= (i2c_clk / (hperh->init.clk_speed * 3)) | I2C_DUTYCYCLE_2; - else - tmp1 |= (i2c_clk / (hperh->init.clk_speed * 25)) | I2C_DUTYCYCLE_16_9; - - if ((tmp1 & I2C_CKCFG_CLKSET) < 1) - return 1; - else - return tmp1; - } + uint32_t tmp1 = 0; + + if (hperh->init.clk_speed <= I2C_STANDARD_MODE_MAX_CLK) { + tmp1 = (i2c_clk / (hperh->init.clk_speed << 1)); + if ((tmp1 & I2C_CKCFG_CLKSET) < 4 ) + return 4; + else + return tmp1; + } + else { + tmp1 = I2C_CKCFG_CLKMOD; + + if (hperh->init.duty == I2C_DUTYCYCLE_2) { + tmp1 |= (i2c_clk / (hperh->init.clk_speed * 3)) | I2C_DUTYCYCLE_2; + CLEAR_BIT(hperh->perh->CKCFG, I2C_CKCFG_CLKMOD_MSK); + } + else { + tmp1 |= (i2c_clk / (hperh->init.clk_speed * 25)) | I2C_DUTYCYCLE_16_9; + SET_BIT(hperh->perh->CKCFG, I2C_CKCFG_CLKMOD_MSK); + } + + if ((tmp1 & I2C_CKCFG_CLKSET) < 1 ) + return 1; + else + return tmp1; + } } #ifdef ALD_DMA @@ -3137,17 +2879,17 @@ static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk) */ static void i2c_dma_error(void *argv) { - i2c_handle_t *hperh = (i2c_handle_t *)argv; + i2c_handle_t* hperh = (i2c_handle_t*)argv; - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - hperh->error_code |= I2C_ERROR_DMA; + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + hperh->error_code |= I2C_ERROR_DMA; - if (hperh->error_callback) - hperh->error_callback(hperh); + if (hperh->error_callback) + hperh->error_callback(hperh); } #endif @@ -3162,36 +2904,29 @@ static void i2c_dma_error(void *argv) */ static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, flag_status_t status, uint32_t timeout) { - uint32_t tickstart = 0; - - tickstart = ald_get_tick(); - - if (status == RESET) - { - while (ald_i2c_get_flag_status(hperh, flag) == RESET) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - else - { - while (ald_i2c_get_flag_status(hperh, flag) != RESET) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - - return OK; + uint32_t tickstart = 0; + + tickstart = ald_get_tick(); + + if (status == RESET) { + while (ald_i2c_get_flag_status(hperh, flag) == RESET) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + else { + while (ald_i2c_get_flag_status(hperh, flag) != RESET) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + return OK; } /** @@ -3204,35 +2939,29 @@ static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t fla */ static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, uint32_t timeout) { - uint32_t tickstart = 0; - - tickstart = ald_get_tick(); - - while (ald_i2c_get_flag_status(hperh, flag) == RESET) - { - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) - { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - - hperh->error_code = I2C_ERROR_AF; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return ERROR; - } - - if (timeout != I2C_MAX_DELAY) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - - return OK; + uint32_t tickstart = 0; + + tickstart = ald_get_tick(); + while (ald_i2c_get_flag_status(hperh, flag) == RESET) { + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); + + hperh->error_code = I2C_ERROR_AF; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return ERROR; + } + + if (timeout != I2C_MAX_DELAY) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + return OK; } /** @@ -3244,26 +2973,22 @@ static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_fla */ static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = ald_get_tick(); - - while (ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE) == RESET) - { - if (i2c_is_ack_failed(hperh) != OK) - return ERROR; - - if (timeout != I2C_MAX_DELAY) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->error_code |= I2C_ERROR_TIMEOUT; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - - return OK; + uint32_t tickstart = ald_get_tick(); + + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE) == RESET) { + if (i2c_is_ack_failed(hperh) != OK) + return ERROR; + + if (timeout != I2C_MAX_DELAY) { + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + return OK; } /** @@ -3275,28 +3000,23 @@ static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeou */ static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = ald_get_tick(); - - while (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == RESET) - { - if (i2c_is_ack_failed(hperh) != OK) - { - return ERROR; - } - - if (timeout != I2C_MAX_DELAY) - { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->error_code |= I2C_ERROR_TIMEOUT; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - - return OK; + uint32_t tickstart = ald_get_tick(); + + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == RESET) { + if (i2c_is_ack_failed(hperh) != OK) { + return ERROR; + } + + if (timeout != I2C_MAX_DELAY) { + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + return OK; } /** @@ -3308,24 +3028,21 @@ static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeou */ static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = 0x00; - tickstart = ald_get_tick(); - - while (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == RESET) - { - if (i2c_is_ack_failed(hperh) != OK) - return ERROR; - - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->error_code |= I2C_ERROR_TIMEOUT; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - - return OK; + uint32_t tickstart = 0x00; + tickstart = ald_get_tick(); + + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == RESET) { + if (i2c_is_ack_failed(hperh) != OK) + return ERROR; + + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + return OK; } /** @@ -3337,30 +3054,26 @@ static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeo */ static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = 0x00; - tickstart = ald_get_tick(); - - while (ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE) == RESET) - { - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == SET) - { - ald_i2c_clear_flag_status(hperh, I2C_FLAG_STOPF); - hperh->error_code = I2C_ERROR_NONE; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return ERROR; - } - - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) - { - hperh->error_code |= I2C_ERROR_TIMEOUT; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - - return OK; + uint32_t tickstart = 0x00; + tickstart = ald_get_tick(); + + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE) == RESET) { + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_FLAG_STOPF); + hperh->error_code = I2C_ERROR_NONE; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return ERROR; + } + + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + return OK; } /** @@ -3371,17 +3084,16 @@ static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeo */ static ald_status_t i2c_is_ack_failed(i2c_handle_t *hperh) { - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) - { - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - hperh->error_code = I2C_ERROR_AF; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); + hperh->error_code = I2C_ERROR_AF; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); - return ERROR; - } + return ERROR; + } - return OK; + return OK; } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c index 81b933d6c78acd5a98fc6d6f5a7369c7540c3250..ccb9b5170b58270c550ad1fd5dfef208251db7b5 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c @@ -51,14 +51,14 @@ */ uint32_t ald_iap_erase_page(uint32_t addr) { - uint32_t status; - IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR); + uint32_t status; + IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR); - __disable_irq(); - status = (*iap_pe)(addr); - __enable_irq(); + __disable_irq(); + status = (*iap_pe)(addr); + __enable_irq(); - return !status; + return !status; } /** @@ -72,17 +72,17 @@ uint32_t ald_iap_erase_page(uint32_t addr) */ uint32_t ald_iap_program_word(uint32_t addr, uint32_t data) { - uint32_t status; - IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR); + uint32_t status; + IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR); - if (addr & 0x3) - return 1; + if (addr & 0x3) + return 1; - __disable_irq(); - status = (*iap_wp)(addr, data); - __enable_irq(); + __disable_irq(); + status = (*iap_wp)(addr, data); + __enable_irq(); - return !status; + return !status; } /** @@ -97,17 +97,17 @@ uint32_t ald_iap_program_word(uint32_t addr, uint32_t data) */ uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h) { - uint32_t status; - IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR); + uint32_t status; + IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR); - if (addr & 0x3) - return 1; + if (addr & 0x3) + return 1; - __disable_irq(); - status = (*iap_dwp)(addr, data_l, data_h); - __enable_irq(); + __disable_irq(); + status = (*iap_dwp)(addr, data_l, data_h); + __enable_irq(); - return !status; + return !status; } /** @@ -124,17 +124,17 @@ uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h) */ uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase) { - uint32_t status; - IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR); + uint32_t status; + IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR); - if ((addr & 0x3) || (len & 0x3)) - return 1; + if ((addr & 0x3) || (len & 0x3)) + return 1; - __disable_irq(); - status = (*iap_wsp)(addr, data, len, erase); - __enable_irq(); + __disable_irq(); + status = (*iap_wsp)(addr, data, len, erase); + __enable_irq(); - return !status; + return !status; } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c index 0966ea26a28a0794cb8a096e00b92e8ac9dd8cd7..d9067499ea7e2326421aabf3585fbd68920e821a 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c @@ -44,99 +44,86 @@ */ ald_status_t ald_pis_create(pis_handle_t *hperh) { - pis_divide_t temp; - uint8_t clock_menu = 0; - - if (hperh == NULL) - return ERROR; - - assert_param(IS_PIS_SRC(hperh->init.producer_src)); - assert_param(IS_PIS_TRIG(hperh->init.consumer_trig)); - assert_param(IS_PIS_CLOCK(hperh->init.producer_clk)); - assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk)); - assert_param(IS_PIS_EDGE(hperh->init.producer_edge)); - - __LOCK(hperh); - hperh->perh = PIS; - - /* get location of consumer in channel and position of con0/con1 - * accord to comsumer_trig information */ - temp.HalfWord = (hperh->init.consumer_trig); - hperh->consumer_ch = (pis_ch_t)(temp.ch); - hperh->consumer_con = (pis_con_t)(temp.con); - hperh->consumer_pos = (1 << temp.shift); - - /* union producer clock and consumer clock */ - clock_menu = (hperh->init.producer_clk << 4) | (hperh->init.consumer_clk); - - if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) - { - __UNLOCK(hperh); - return BUSY; - } - - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS); - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS); - - /* configure sync clock, judging by producer clock with consumer clock */ - switch (clock_menu) - { - case 0x00: - case 0x11: - case 0x22: - case 0x33: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS); - break; - - case 0x01: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS); - break; - - case 0x02: - case 0x12: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS); - break; - - case 0x21: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS); - break; - - case 0x30: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS); - break; - - case 0x31: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS); - break; - - case 0x32: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS); - - default: - break; - } - - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS); - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS); - hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch]; - - /* enable consumer bit, switch pin of consumer */ - switch (hperh->consumer_con) - { - case PIS_CON_0: - PIS->TAR_CON0 |= hperh->consumer_pos; - break; - - case PIS_CON_1: - PIS->TAR_CON1 |= hperh->consumer_pos; - break; - - default: - break; - } - - __UNLOCK(hperh); - return OK; + uint8_t clock_menu = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_PIS_SRC(hperh->init.producer_src)); + assert_param(IS_PIS_TRIG(hperh->init.consumer_trig)); + assert_param(IS_PIS_CLOCK(hperh->init.producer_clk)); + assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk)); + assert_param(IS_PIS_EDGE(hperh->init.producer_edge)); + + __LOCK(hperh); + hperh->perh = PIS; + + /* get location of consumer in channel and position of con0/con1 + * accord to comsumer_trig information */ + hperh->consumer_ch = (pis_ch_t)(hperh->init.consumer_trig & 0x0F); + hperh->consumer_con = (pis_con_t)(((uint32_t)hperh->init.consumer_trig >> 4) & 0x0F); + hperh->consumer_pos = (1U << (uint32_t)(((uint32_t)hperh->init.consumer_trig >> 8) & 0xFF)); + + /* union producer clock and consumer clock */ + clock_menu = (hperh->init.producer_clk << 4) | (hperh->init.consumer_clk); + + if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) { + __UNLOCK(hperh); + return BUSY; + } + + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS); + + /* configure sync clock, judging by producer clock with consumer clock */ + switch (clock_menu) { + case 0x00: + case 0x11: + case 0x22: + case 0x33: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x01: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x02: + case 0x12: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x21: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x30: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x31: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x32: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS); + break; + default: + break; + } + + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS); + hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch]; + + /* enable consumer bit, switch pin of consumer */ + switch (hperh->consumer_con) { + case PIS_CON_0: + PIS->TAR_CON0 |= hperh->consumer_pos; + break; + case PIS_CON_1: + PIS->TAR_CON1 |= hperh->consumer_pos; + break; + default: + break; + } + + __UNLOCK(hperh); + return OK; } /** @@ -148,34 +135,31 @@ ald_status_t ald_pis_create(pis_handle_t *hperh) */ ald_status_t ald_pis_destroy(pis_handle_t *hperh) { - assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS(hperh->perh)); - if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch]) - return ERROR; + if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch]) + return ERROR; - __LOCK(hperh); + __LOCK(hperh); - CLEAR_BIT(PIS->CH_OER, (1 << hperh->consumer_ch)); - WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0); + CLEAR_BIT(PIS->CH_OER, (1U << (uint32_t)hperh->consumer_ch)); + WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0); - switch (hperh->consumer_con) - { - case PIS_CON_0: - PIS->TAR_CON0 &= ~(hperh->consumer_pos); - break; + switch (hperh->consumer_con) { + case PIS_CON_0: + PIS->TAR_CON0 &= ~(hperh->consumer_pos); + break; + case PIS_CON_1: + PIS->TAR_CON1 &= ~(hperh->consumer_pos); + break; + default: + break; + } - case PIS_CON_1: - PIS->TAR_CON1 &= ~(hperh->consumer_pos); - break; + hperh->state = PIS_STATE_RESET; + __UNLOCK(hperh); - default: - break; - } - - hperh->state = PIS_STATE_RESET; - __UNLOCK(hperh); - - return OK; + return OK; } /** * @} @@ -200,13 +184,13 @@ ald_status_t ald_pis_destroy(pis_handle_t *hperh) */ ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch) { - assert_param(IS_PIS(hperh->perh)); - assert_param(IS_PIS_OUPUT_CH(ch)); - __LOCK(hperh); - SET_BIT(PIS->CH_OER, (1 << ch)); - __UNLOCK(hperh); + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_OUPUT_CH(ch)); + __LOCK(hperh); + SET_BIT(PIS->CH_OER, (1 << ch)); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -223,13 +207,13 @@ ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch) */ ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch) { - assert_param(IS_PIS(hperh->perh)); - assert_param(IS_PIS_OUPUT_CH(ch)); - __LOCK(hperh); - CLEAR_BIT(PIS->CH_OER, (1 << ch)); - __UNLOCK(hperh); + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_OUPUT_CH(ch)); + __LOCK(hperh); + CLEAR_BIT(PIS->CH_OER, (1 << ch)); + __UNLOCK(hperh); - return OK; + return OK; } /** * @} @@ -248,8 +232,8 @@ ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch) */ pis_state_t ald_pis_get_state(pis_handle_t *hperh) { - assert_param(IS_PIS(hperh->perh)); - return hperh->state; + assert_param(IS_PIS(hperh->perh)); + return hperh->state; } /** @@ -272,51 +256,50 @@ pis_state_t ald_pis_get_state(pis_handle_t *hperh) */ ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config) { - assert_param(IS_PIS(hperh->perh)); - assert_param(IS_PIS_MODU_TARGET(config->target)); - assert_param(IS_PIS_MODU_LEVEL(config->level)); - assert_param(IS_PIS_MODU_SRC(config->src)); - assert_param(IS_PIS_MODU_CHANNEL(config->channel)); - __LOCK(hperh); - - switch (config->target) - { - case PIS_UART0_TX: - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART1_TX: - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART2_TX: - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART3_TX: - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_LPUART0_TX: - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - default: - break; - } - - __UNLOCK(hperh); - return OK; + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_MODU_TARGET(config->target)); + assert_param(IS_PIS_MODU_LEVEL(config->level)); + assert_param(IS_PIS_MODU_SRC(config->src)); + assert_param(IS_PIS_MODU_CHANNEL(config->channel)); + __LOCK(hperh); + + switch (config->target) { + case PIS_UART0_TX: + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART1_TX: + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART2_TX: + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART3_TX: + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_LPUART0_TX: + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + default: + break; + } + + __UNLOCK(hperh); + return OK; } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c index 0c488304a17925b8c25566eb42dcc9fc240126eb..f8b4b94e27d0602e16463267407a77131d1c9ff9 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c @@ -15,7 +15,6 @@ */ #include "ald_pmu.h" -#include "ald_bkpc.h" /** @addtogroup ES32FXXX_ALD @@ -39,11 +38,11 @@ */ void ald_lvd_irq_handler(void) { - SYSCFG_UNLOCK(); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); - SYSCFG_LOCK(); + SYSCFG_UNLOCK(); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + SYSCFG_LOCK(); - return; + return; } /** * @} @@ -63,6 +62,7 @@ void ald_lvd_irq_handler(void) [..] This section provides functions allowing to: (+) Enter stop1 mode. (+) Enter stop2 mode. + (+) Enter standby mode. (+) Get wakeup status. (+) Clear wakeup status. @@ -76,16 +76,16 @@ void ald_lvd_irq_handler(void) */ void ald_pmu_stop1_enter(void) { - SYSCFG_UNLOCK(); - MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP1 << PMU_CR_LPM_POSS); - SYSCFG_LOCK(); + SYSCFG_UNLOCK(); + MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP1 << PMU_CR_LPM_POSS); + SYSCFG_LOCK(); - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - return; + return; } /** @@ -94,17 +94,40 @@ void ald_pmu_stop1_enter(void) */ void ald_pmu_stop2_enter(void) { - SYSCFG_UNLOCK(); - SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); - MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP2 << PMU_CR_LPM_POSS); - SYSCFG_LOCK(); + SYSCFG_UNLOCK(); + SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); + MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP2 << PMU_CR_LPM_POSS); + SYSCFG_LOCK(); - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - return; + return; +} + +/** + * @brief Enter standby mode + * @param port: The port whick wake up the standby mode. + * @param level: Wakeup level. + * @retval None + */ +void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level) +{ + ald_bkpc_standby_wakeup_config(port, level); + + SYSCFG_UNLOCK(); + SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); + MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STANDBY << PMU_CR_LPM_POSS); + SYSCFG_LOCK(); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + + return; } /** @@ -114,12 +137,12 @@ void ald_pmu_stop2_enter(void) */ flag_status_t ald_pmu_get_status(pmu_status_t sr) { - assert_param(IS_PMU_STATUS(sr)); + assert_param(IS_PMU_STATUS(sr)); - if (READ_BIT(PMU->SR, sr)) - return SET; + if (READ_BIT(PMU->SR, sr)) + return SET; - return RESET; + return RESET; } /** @@ -129,19 +152,17 @@ flag_status_t ald_pmu_get_status(pmu_status_t sr) */ void ald_pmu_clear_status(pmu_status_t sr) { - assert_param(IS_PMU_STATUS(sr)); - SYSCFG_UNLOCK(); + assert_param(IS_PMU_STATUS(sr)); + SYSCFG_UNLOCK(); - if (sr == PMU_SR_WUF) - SET_BIT(PMU->CR, PMU_CR_CWUF_MSK); - else - SET_BIT(PMU->CR, PMU_CR_CSTANDBYF_MSK); + if (sr == PMU_SR_WUF) + SET_BIT(PMU->CR, PMU_CR_CWUF_MSK); + else + SET_BIT(PMU->CR, PMU_CR_CSTANDBYF_MSK); - SYSCFG_LOCK(); - return; + SYSCFG_LOCK(); + return; } - - /** * @} */ @@ -170,36 +191,32 @@ void ald_pmu_clear_status(pmu_status_t sr) */ void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state) { - assert_param(IS_FUNC_STATE(state)); - SYSCFG_UNLOCK(); - - if (state) - { - assert_param(IS_PMU_LVD_VOL_SEL(sel)); - assert_param(IS_PMU_LVD_TRIGGER_MODE(mode)); - - MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS); - MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); - } - else - { - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); - CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); - CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_FUNC_STATE(state)); + SYSCFG_UNLOCK(); + + if (state) { + assert_param(IS_PMU_LVD_VOL_SEL(sel)); + assert_param(IS_PMU_LVD_TRIGGER_MODE(mode)); + + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS); + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + else { + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + + SYSCFG_LOCK(); + return; } /** * @} */ - - /** * @} */ @@ -207,7 +224,6 @@ void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, /** * @} */ - /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c index b896bcf104e7325a1d30f190a0669391a39c40dd..2b04f2719c57d009170a1d0ac5362d748ff52a7e 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c @@ -40,41 +40,42 @@ */ void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state) { - assert_param(IS_FUNC_STATE(state)); - - SYSCFG_UNLOCK(); - - if (state) - { - assert_param(IS_RMU_BORFLT(flt)); - assert_param(IS_RMU_BORVOL(vol)); - - MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS); - MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS); - SET_BIT(RMU->CR, RMU_CR_BOREN_MSK); - } - else - { - CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK); - } - - SYSCFG_LOCK(); - return; + assert_param(IS_FUNC_STATE(state)); + + SYSCFG_UNLOCK(); + + if (state) { + assert_param(IS_RMU_BORFLT(flt)); + assert_param(IS_RMU_BORVOL(vol)); + + MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS); + MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS); + SET_BIT(RMU->CR, RMU_CR_BOREN_MSK); + } + else { + CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK); + } + + SYSCFG_LOCK(); + return; } /** * @brief Get specified reset status * @param state: Speicifies the type of the reset, - * @retval The status: SET/RESET. + * @retval The status. */ -flag_status_t ald_rmu_get_reset_status(rmu_state_t state) +uint32_t ald_rmu_get_reset_status(rmu_state_t state) { - assert_param(IS_RMU_STATE(state)); + assert_param(IS_RMU_STATE(state)); + + if (state == RMU_RST_ALL) + return RMU->RSTSR; - if (READ_BIT(RMU->RSTSR, state)) - return SET; + if (READ_BIT(RMU->RSTSR, state)) + return SET; - return RESET; + return RESET; } /** @@ -84,13 +85,13 @@ flag_status_t ald_rmu_get_reset_status(rmu_state_t state) */ void ald_rmu_clear_reset_status(rmu_state_t state) { - assert_param(IS_RMU_STATE_CLEAR(state)); + assert_param(IS_RMU_STATE_CLEAR(state)); - SYSCFG_UNLOCK(); - WRITE_REG(RMU->CRSTSR, state); - SYSCFG_LOCK(); + SYSCFG_UNLOCK(); + WRITE_REG(RMU->CRSTSR, state); + SYSCFG_LOCK(); - return; + return; } /** * @brief Reset peripheral device @@ -99,38 +100,37 @@ void ald_rmu_clear_reset_status(rmu_state_t state) */ void ald_rmu_reset_periperal(rmu_peripheral_t perh) { - uint32_t idx, pos; + uint32_t idx, pos; - assert_param(IS_RMU_PERH(perh)); + assert_param(IS_RMU_PERH(perh)); - idx = (perh >> 27) & 0x7; - pos = perh & ~(0x7 << 27); - SYSCFG_UNLOCK(); + idx = ((uint32_t)perh >> 27) & 0x7; + pos = perh & ~(0x7 << 27); + SYSCFG_UNLOCK(); - switch (idx) - { - case 0: - WRITE_REG(RMU->AHB1RSTR, pos); - break; + switch (idx) { + case 0: + WRITE_REG(RMU->AHB1RSTR, pos); + break; - case 1: - WRITE_REG(RMU->AHB2RSTR, pos); - break; + case 1: + WRITE_REG(RMU->AHB2RSTR, pos); + break; - case 2: - WRITE_REG(RMU->APB1RSTR, pos); - break; + case 2: + WRITE_REG(RMU->APB1RSTR, pos); + break; - case 4: - WRITE_REG(RMU->APB2RSTR, pos); - break; + case 4: + WRITE_REG(RMU->APB2RSTR, pos); + break; - default: - break; - } + default: + break; + } - SYSCFG_LOCK(); - return; + SYSCFG_LOCK(); + return; } /** diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c index c8294d3ab7d4472daa7ab7e6949501d4757ed4a1..7391045a62dbc821736d01935c5657590924d6fb 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c @@ -142,7 +142,7 @@ */ static uint32_t bcd_to_dec(uint32_t bcd) { - return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10); + return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10); } /** @@ -152,7 +152,7 @@ static uint32_t bcd_to_dec(uint32_t bcd) */ static uint32_t dec_to_bcd(uint32_t dec) { - return (((dec / 10) << 4) | (dec % 10)); + return (((dec / 10) << 4) | (dec % 10)); } /** @@ -166,27 +166,22 @@ static uint32_t dec_to_bcd(uint32_t dec) * 1 - Consistency */ static int32_t rtc_consistency_check(rtc_time_t *t_last, - rtc_date_t *d_last, rtc_time_t *time, rtc_date_t *date) + rtc_date_t *d_last, rtc_time_t *time, rtc_date_t *date) { - if (t_last->second != time->second) - return 0; - - if (t_last->minute != time->minute) - return 0; - - if (t_last->hour != time->hour) - return 0; - - if (d_last->day != date->day) - return 0; - - if (d_last->month != date->month) - return 0; - - if (d_last->year != date->year) - return 0; - - return 1; + if (t_last->second != time->second) + return 0; + if (t_last->minute != time->minute) + return 0; + if (t_last->hour != time->hour) + return 0; + if (d_last->day != date->day) + return 0; + if (d_last->month != date->month) + return 0; + if (d_last->year != date->year) + return 0; + + return 1; } /** * @} @@ -224,16 +219,16 @@ static int32_t rtc_consistency_check(rtc_time_t *t_last, */ void ald_rtc_reset(void) { - RTC_UNLOCK(); + RTC_UNLOCK(); - WRITE_REG(RTC->CON, 0x0); - WRITE_REG(RTC->TAMPCON, 0x0); - WRITE_REG(RTC->WUMAT, 0x0); - WRITE_REG(RTC->IER, 0x0); - WRITE_REG(RTC->IFCR, ~0x0); + WRITE_REG(RTC->CON, 0x0); + WRITE_REG(RTC->TAMPCON, 0x0); + WRITE_REG(RTC->WUMAT, 0x0); + WRITE_REG(RTC->IER, 0x0); + WRITE_REG(RTC->IFCR, ~0x0); - RTC_LOCK(); - return; + RTC_LOCK(); + return; } /** @@ -244,22 +239,22 @@ void ald_rtc_reset(void) */ void ald_rtc_init(rtc_init_t *init) { - assert_param(IS_RTC_HOUR_FORMAT(init->hour_format)); - assert_param(IS_RTC_OUTPUT_SEL(init->output)); - assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); - - ald_rtc_reset(); - RTC_UNLOCK(); - - MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); - MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS); - MODIFY_REG(RTC->CON, RTC_CON_POL_MSK, init->output_polarity << RTC_CON_POL_POS); - MODIFY_REG(RTC->PSR, RTC_PSR_SPRS_MSK, init->synch_pre_div << RTC_PSR_SPRS_POSS); - MODIFY_REG(RTC->PSR, RTC_PSR_APRS_MSK, init->asynch_pre_div << RTC_PSR_APRS_POSS); - SET_BIT(RTC->CON, RTC_CON_GO_MSK); - - RTC_LOCK(); - return; + assert_param(IS_RTC_HOUR_FORMAT(init->hour_format)); + assert_param(IS_RTC_OUTPUT_SEL(init->output)); + assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); + + ald_rtc_reset(); + RTC_UNLOCK(); + + MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); + MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS); + MODIFY_REG(RTC->CON, RTC_CON_POL_MSK, init->output_polarity << RTC_CON_POL_POS); + MODIFY_REG(RTC->PSR, RTC_PSR_SPRS_MSK, init->synch_pre_div << RTC_PSR_SPRS_POSS); + MODIFY_REG(RTC->PSR, RTC_PSR_APRS_MSK, init->asynch_pre_div << RTC_PSR_APRS_POSS); + SET_BIT(RTC->CON, RTC_CON_GO_MSK); + + RTC_LOCK(); + return; } /** @@ -269,26 +264,23 @@ void ald_rtc_init(rtc_init_t *init) */ void ald_rtc_source_select(rtc_source_sel_t sel) { - assert_param(IS_RTC_SOURCE_SEL(sel)); - - BKPC_UNLOCK(); - MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, sel << BKPC_PCCR_RTCCS_POSS); - - if (sel == RTC_SOURCE_LOSC) - { - SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); - } - else if (sel == RTC_SOURCE_LRC) - { - SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); - } - else - { - ; /* do nothing */ - } - - BKPC_LOCK(); - return; + assert_param(IS_RTC_SOURCE_SEL(sel)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, sel << BKPC_PCCR_RTCCS_POSS); + + if (sel == RTC_SOURCE_LOSC) { + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); + } + else if (sel == RTC_SOURCE_LRC) { + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); + } + else { + ; /* do nothing */ + } + + BKPC_LOCK(); + return; } /** * @} @@ -319,45 +311,41 @@ void ald_rtc_source_select(rtc_source_sel_t sel) * @param format: Data format. * @retval ALD status. */ -ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format) +ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format) { - uint32_t tmp; - - assert_param(IS_RTC_FORMAT(format)); - - if (format == RTC_FORMAT_DEC) - { - assert_param(IS_RTC_SECOND(time->second)); - assert_param(IS_RTC_MINUTE(time->minute)); - assert_param(IS_RTC_HOUR(time->hour)); - - tmp = (dec_to_bcd(time->second)) | - (dec_to_bcd(time->minute) << 8) | - (dec_to_bcd(time->hour) << 16); - } - else - { - assert_param(IS_RTC_SECOND(bcd_to_dec(time->second))); - assert_param(IS_RTC_MINUTE(bcd_to_dec(time->minute))); - assert_param(IS_RTC_HOUR(bcd_to_dec(time->hour))); - - tmp = time->second | (time->minute << 8) | (time->hour << 16); - } - - RTC_UNLOCK(); - WRITE_REG(RTC->TIME, tmp); - WRITE_REG(RTC->SSEC, time->sub_sec); - RTC_LOCK(); - - tmp = ald_get_tick(); - - while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) - { - if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) - return TIMEOUT; - } - - return OK; + uint32_t tmp; + + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + assert_param(IS_RTC_SECOND(time->second)); + assert_param(IS_RTC_MINUTE(time->minute)); + assert_param(IS_RTC_HOUR(time->hour)); + + tmp = (dec_to_bcd(time->second)) | + (dec_to_bcd(time->minute) << 8) | + (dec_to_bcd(time->hour) << 16); + } + else { + assert_param(IS_RTC_SECOND(bcd_to_dec(time->second))); + assert_param(IS_RTC_MINUTE(bcd_to_dec(time->minute))); + assert_param(IS_RTC_HOUR(bcd_to_dec(time->hour))); + + tmp = time->second | (time->minute << 8) | (time->hour << 16); + } + + RTC_UNLOCK(); + WRITE_REG(RTC->TIME, tmp); + RTC_LOCK(); + + tmp = ald_get_tick(); + + while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) { + if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } + + return OK; } /** @@ -368,44 +356,41 @@ ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format) */ ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format) { - uint32_t tmp; - - assert_param(IS_RTC_FORMAT(format)); - - if (format == RTC_FORMAT_DEC) - { - assert_param(IS_RTC_DAY(date->day)); - assert_param(IS_RTC_MONTH(date->month)); - assert_param(IS_RTC_YEAR(date->year)); - - tmp = (dec_to_bcd(date->day)) | - (dec_to_bcd(date->month) << 8) | - (dec_to_bcd(date->year) << 16) | - (dec_to_bcd(date->week) << 24); - } - else - { - assert_param(IS_RTC_DAY(bcd_to_dec(date->day))); - assert_param(IS_RTC_MONTH(bcd_to_dec(date->month))); - assert_param(IS_RTC_YEAR(bcd_to_dec(date->year))); - - tmp = date->day | (date->month << 8) | - (date->year << 16) | (date->week << 24); - } - - RTC_UNLOCK(); - WRITE_REG(RTC->DATE, tmp); - RTC_LOCK(); - - tmp = ald_get_tick(); - - while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) - { - if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) - return TIMEOUT; - } - - return OK; + uint32_t tmp; + + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + assert_param(IS_RTC_DAY(date->day)); + assert_param(IS_RTC_MONTH(date->month)); + assert_param(IS_RTC_YEAR(date->year)); + + tmp = (dec_to_bcd(date->day)) | + (dec_to_bcd(date->month) << 8) | + (dec_to_bcd(date->year) << 16) | + (dec_to_bcd(date->week) << 24); + } + else { + assert_param(IS_RTC_DAY(bcd_to_dec(date->day))); + assert_param(IS_RTC_MONTH(bcd_to_dec(date->month))); + assert_param(IS_RTC_YEAR(bcd_to_dec(date->year))); + + tmp = date->day | (date->month << 8) | + (date->year << 16) | (date->week << 24); + } + + RTC_UNLOCK(); + WRITE_REG(RTC->DATE, tmp); + RTC_LOCK(); + + tmp = ald_get_tick(); + + while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) { + if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } + + return OK; } /** @@ -416,28 +401,26 @@ ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format) */ void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format) { - uint32_t tmp; - - assert_param(time != NULL); - assert_param(IS_RTC_FORMAT(format)); - - time->sub_sec = RTC->SSEC & 0xFFFF; - tmp = RTC->TIME; - - if (format == RTC_FORMAT_DEC) - { - time->second = bcd_to_dec(tmp & 0x7F); - time->minute = bcd_to_dec((tmp >> 8) & 0x7F); - time->hour = bcd_to_dec((tmp >> 16) & 0x7F); - } - else - { - time->second = tmp & 0x7F; - time->minute = (tmp >> 8) & 0x7F; - time->hour = (tmp >> 16) & 0x7F; - } - - return; + uint32_t tmp; + + assert_param(time != NULL); + assert_param(IS_RTC_FORMAT(format)); + + time->sub_sec = RTC->SSEC & 0xFFFF; + tmp = RTC->TIME; + + if (format == RTC_FORMAT_DEC) { + time->second = bcd_to_dec(tmp & 0x7F); + time->minute = bcd_to_dec((tmp >> 8) & 0x7F); + time->hour = bcd_to_dec((tmp >> 16) & 0x7F); + } + else { + time->second = tmp & 0x7F; + time->minute = (tmp >> 8) & 0x7F; + time->hour = (tmp >> 16) & 0x7F; + } + + return; } /** @@ -448,27 +431,25 @@ void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format) */ void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format) { - uint32_t tmp = RTC->DATE; - - assert_param(date != NULL); - assert_param(IS_RTC_FORMAT(format)); - - if (format == RTC_FORMAT_DEC) - { - date->day = bcd_to_dec(tmp & 0x3F); - date->month = bcd_to_dec((tmp >> 8) & 0x1F); - date->year = bcd_to_dec((tmp >> 16) & 0xFF); - date->week = bcd_to_dec((tmp >> 24) & 0x7); - } - else - { - date->day = tmp & 0x3F; - date->month = (tmp >> 8) & 0x1F; - date->year = (tmp >> 16) & 0xFF; - date->week = (tmp >> 24) & 0x7; - } - - return; + uint32_t tmp = RTC->DATE; + + assert_param(date != NULL); + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + date->day = bcd_to_dec(tmp & 0x3F); + date->month = bcd_to_dec((tmp >> 8) & 0x1F); + date->year = bcd_to_dec((tmp >> 16) & 0xFF); + date->week = bcd_to_dec((tmp >> 24) & 0x7); + } + else { + date->day = tmp & 0x3F; + date->month = (tmp >> 8) & 0x1F; + date->year = (tmp >> 16) & 0xFF; + date->week = (tmp >> 24) & 0x7; + } + + return; } /** @@ -482,22 +463,21 @@ void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format) */ int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format) { - int32_t nr = 3; - rtc_date_t d_last; - rtc_time_t t_last; - - while (nr--) - { - ald_rtc_get_time(&t_last, format); - ald_rtc_get_date(&d_last, format); - ald_rtc_get_time(time, format); - ald_rtc_get_date(date, format); - - if (rtc_consistency_check(&t_last, &d_last, time, date)) - return 0; - } - - return -1; + int32_t nr = 3; + rtc_date_t d_last; + rtc_time_t t_last; + + while (nr--) { + ald_rtc_get_time(&t_last, format); + ald_rtc_get_date(&d_last, format); + ald_rtc_get_time(time, format); + ald_rtc_get_date(date, format); + + if (rtc_consistency_check(&t_last, &d_last, time, date)) + return 0; + } + + return -1; } /** * @} @@ -528,82 +508,74 @@ int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t f */ void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format) { - unsigned int tmp, ss_tmp; - - assert_param(IS_RTC_ALARM(alarm->idx)); - assert_param(IS_RTC_ALARM_SEL(alarm->sel)); - assert_param(IS_RTC_ALARM_SS_MASK(alarm->ss_mask)); - assert_param(IS_RTC_FORMAT(format)); - - if (format == RTC_FORMAT_DEC) - { - assert_param(IS_RTC_SECOND(alarm->time.second)); - assert_param(IS_RTC_MINUTE(alarm->time.minute)); - assert_param(IS_RTC_HOUR(alarm->time.hour)); - - tmp = (dec_to_bcd(alarm->time.second)) | - (dec_to_bcd(alarm->time.minute) << 8) | - (dec_to_bcd(alarm->time.hour) << 16) | - alarm->mask; - - if (alarm->sel == RTC_SELECT_DAY) - { - assert_param(IS_RTC_DAY(alarm->day)); - - tmp |= (dec_to_bcd(alarm->day) << 24); - tmp &= 0x7FFFFFFF; /* Reset bit31 */ - } - else - { - tmp |= (1 << (alarm->week + 24)); - tmp |= 0x80000000; /* Set bit31 */ - } - } - else - { - assert_param(IS_RTC_SECOND(bcd_to_dec(alarm->time.second))); - assert_param(IS_RTC_MINUTE(bcd_to_dec(alarm->time.minute))); - assert_param(IS_RTC_HOUR(bcd_to_dec(alarm->time.hour))); - - tmp = alarm->time.second | - (alarm->time.minute << 8) | - (alarm->time.hour << 16) | - alarm->mask; - - if (alarm->sel == RTC_SELECT_DAY) - { - assert_param(IS_RTC_DAY(bcd_to_dec(alarm->day))); - - tmp |= (alarm->day << 24); - tmp &= 0x7FFFFFFF; /* Reset bit31 */ - } - else - { - tmp |= (1 << (alarm->week + 24)); - tmp |= 0x80000000; /* Set bit31 */ - } - } - - ss_tmp = (alarm->time.sub_sec & 0x7F) | - (alarm->ss_mask << 24); - - RTC_UNLOCK(); - - if (alarm->idx == RTC_ALARM_A) - { - WRITE_REG(RTC->ALMA, tmp); - WRITE_REG(RTC->ALMASSEC, ss_tmp); - SET_BIT(RTC->CON, RTC_CON_ALMAEN_MSK); - } - else - { - WRITE_REG(RTC->ALMB, tmp); - WRITE_REG(RTC->ALMBSSEC, ss_tmp); - SET_BIT(RTC->CON, RTC_CON_ALMBEN_MSK); - } - - RTC_LOCK(); - return; + unsigned int tmp, ss_tmp; + + assert_param(IS_RTC_ALARM(alarm->idx)); + assert_param(IS_RTC_ALARM_SEL(alarm->sel)); + assert_param(IS_RTC_ALARM_SS_MASK(alarm->ss_mask)); + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + assert_param(IS_RTC_SECOND(alarm->time.second)); + assert_param(IS_RTC_MINUTE(alarm->time.minute)); + assert_param(IS_RTC_HOUR(alarm->time.hour)); + + tmp = (dec_to_bcd(alarm->time.second)) | + (dec_to_bcd(alarm->time.minute) << 8) | + (dec_to_bcd(alarm->time.hour) << 16) | + alarm->mask; + + if (alarm->sel == RTC_SELECT_DAY) { + assert_param(IS_RTC_DAY(alarm->day)); + + tmp |= (dec_to_bcd(alarm->day) << 24); + tmp &= 0x7FFFFFFF; /* Reset bit31 */ + } + else { + tmp |= (1 << (alarm->week + 24)); + tmp |= 0x80000000; /* Set bit31 */ + } + } + else { + assert_param(IS_RTC_SECOND(bcd_to_dec(alarm->time.second))); + assert_param(IS_RTC_MINUTE(bcd_to_dec(alarm->time.minute))); + assert_param(IS_RTC_HOUR(bcd_to_dec(alarm->time.hour))); + + tmp = alarm->time.second | + (alarm->time.minute << 8) | + (alarm->time.hour << 16) | + alarm->mask; + + if (alarm->sel == RTC_SELECT_DAY) { + assert_param(IS_RTC_DAY(bcd_to_dec(alarm->day))); + + tmp |= (alarm->day << 24); + tmp &= 0x7FFFFFFF; /* Reset bit31 */ + } + else { + tmp |= (1 << (alarm->week + 24)); + tmp |= 0x80000000; /* Set bit31 */ + } + } + + ss_tmp = (alarm->time.sub_sec & 0x7F) | + (alarm->ss_mask << 24); + + RTC_UNLOCK(); + + if (alarm->idx == RTC_ALARM_A) { + WRITE_REG(RTC->ALMA, tmp); + WRITE_REG(RTC->ALMASSEC, ss_tmp); + SET_BIT(RTC->CON, RTC_CON_ALMAEN_MSK); + } + else { + WRITE_REG(RTC->ALMB, tmp); + WRITE_REG(RTC->ALMBSSEC, ss_tmp); + SET_BIT(RTC->CON, RTC_CON_ALMBEN_MSK); + } + + RTC_LOCK(); + return; } /** @@ -614,90 +586,76 @@ void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format) */ void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) { - uint8_t week; - uint32_t tmp, ss_tmp; - - assert_param(alarm != NULL); - assert_param(IS_RTC_FORMAT(format)); - - if (alarm->idx == RTC_ALARM_A) - { - tmp = RTC->ALMA; - ss_tmp = RTC->ALMASSEC; - } - else - { - tmp = RTC->ALMB; - ss_tmp = RTC->ALMBSSEC; - } - - if ((tmp >> 31) & 0x1) - { - alarm->sel = RTC_SELECT_WEEK; - week = ((tmp >> 24) & 0x7F); - - switch (week) - { - case 1: - alarm->week = 0; - break; - - case 2: - alarm->week = 1; - break; - - case 4: - alarm->week = 2; - break; - - case 8: - alarm->week = 3; - break; - - case 16: - alarm->week = 4; - break; - - case 32: - alarm->week = 5; - break; - - case 64: - alarm->week = 6; - break; - - default: - break; - } - } - else - { - alarm->sel = RTC_SELECT_DAY; - - if (format == RTC_FORMAT_DEC) - alarm->day = bcd_to_dec((tmp >> 24) & 0x3F); - else - alarm->day = (tmp >> 24) & 0x3F; - } - - if (format == RTC_FORMAT_DEC) - { - alarm->time.second = bcd_to_dec(tmp & 0x7F); - alarm->time.minute = bcd_to_dec((tmp >> 8) & 0x7F); - alarm->time.hour = bcd_to_dec((tmp >> 16) & 0x3F); - } - else - { - alarm->time.second = tmp & 0x7F; - alarm->time.minute = (tmp >> 8) & 0x7F; - alarm->time.hour = (tmp >> 16) & 0x3F; - } - - alarm->time.sub_sec = ss_tmp & 0x7FFF; - alarm->ss_mask = (rtc_sub_second_mask_t)((ss_tmp >> 24) & 0xF); - alarm->mask = tmp & ALARM_MASK_ALL; - - return; + uint8_t week; + uint32_t tmp, ss_tmp; + + assert_param(alarm != NULL); + assert_param(IS_RTC_FORMAT(format)); + + if (alarm->idx == RTC_ALARM_A) { + tmp = RTC->ALMA; + ss_tmp = RTC->ALMASSEC; + } + else { + tmp = RTC->ALMB; + ss_tmp = RTC->ALMBSSEC; + } + + if ((tmp >> 31) & 0x1) { + alarm->sel = RTC_SELECT_WEEK; + week = ((tmp >> 24) & 0x7F); + + switch (week) { + case 1: + alarm->week = 0; + break; + case 2: + alarm->week = 1; + break; + case 4: + alarm->week = 2; + break; + case 8: + alarm->week = 3; + break; + case 16: + alarm->week = 4; + break; + case 32: + alarm->week = 5; + break; + case 64: + alarm->week = 6; + break; + default: + break; + } + } + else { + alarm->sel = RTC_SELECT_DAY; + + if (format == RTC_FORMAT_DEC) + alarm->day = bcd_to_dec((tmp >> 24) & 0x3F); + else + alarm->day = (tmp >> 24) & 0x3F; + } + + if (format == RTC_FORMAT_DEC) { + alarm->time.second = bcd_to_dec(tmp & 0x7F); + alarm->time.minute = bcd_to_dec((tmp >> 8) & 0x7F); + alarm->time.hour = bcd_to_dec((tmp >> 16) & 0x3F); + } + else { + alarm->time.second = tmp & 0x7F; + alarm->time.minute = (tmp >> 8) & 0x7F; + alarm->time.hour = (tmp >> 16) & 0x3F; + } + + alarm->time.sub_sec = ss_tmp & 0x7FFF; + alarm->ss_mask = (rtc_sub_second_mask_t)((ss_tmp >> 24) & 0xF); + alarm->mask = tmp & ALARM_MASK_ALL; + + return; } /** * @} @@ -733,18 +691,18 @@ void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) */ void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style) { - assert_param(IS_RTC_TS_SIGNAL(sel)); - assert_param(IS_RTC_TS_STYLE(style)); + assert_param(IS_RTC_TS_SIGNAL(sel)); + assert_param(IS_RTC_TS_STYLE(style)); - RTC_UNLOCK(); + RTC_UNLOCK(); - CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); - MODIFY_REG(RTC->CON, RTC_CON_TSSEL_MSK, style << RTC_CON_TSSEL_POS); - MODIFY_REG(RTC->CON, RTC_CON_TSPIN_MSK, sel << RTC_CON_TSPIN_POS); - SET_BIT(RTC->CON, RTC_CON_TSEN_MSK); + CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); + MODIFY_REG(RTC->CON, RTC_CON_TSSEL_MSK, style << RTC_CON_TSSEL_POS); + MODIFY_REG(RTC->CON, RTC_CON_TSPIN_MSK, sel << RTC_CON_TSPIN_POS); + SET_BIT(RTC->CON, RTC_CON_TSEN_MSK); - RTC_LOCK(); - return; + RTC_LOCK(); + return; } /** @@ -753,11 +711,11 @@ void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t styl */ void ald_rtc_cancel_time_stamp(void) { - RTC_UNLOCK(); - CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); - RTC_LOCK(); + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); + RTC_LOCK(); - return; + return; } /** @@ -769,38 +727,36 @@ void ald_rtc_cancel_time_stamp(void) */ void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format) { - uint32_t tmp0, tmp1; - - assert_param(ts_time != NULL); - assert_param(ts_date != NULL); - assert_param(IS_RTC_FORMAT(format)); - - ts_time->sub_sec = RTC->TSSSEC & 0xFFFF; - tmp0 = RTC->TSTIME; - tmp1 = RTC->TSDATE; - - if (format == RTC_FORMAT_DEC) - { - ts_time->second = bcd_to_dec(tmp0 & 0x7F); - ts_time->minute = bcd_to_dec((tmp0 >> 8) & 0x7F); - ts_time->hour = bcd_to_dec((tmp0 >> 16) & 0x3F); - ts_date->day = bcd_to_dec(tmp1 & 0x3F); - ts_date->month = bcd_to_dec((tmp1 >> 8) & 0x1F); - ts_date->year = bcd_to_dec((tmp1 >> 16) & 0xFF); - ts_date->week = bcd_to_dec((tmp1 >> 24) & 0x7); - } - else - { - ts_time->second = tmp0 & 0x7F; - ts_time->minute = (tmp0 >> 8) & 0x7F; - ts_time->hour = (tmp0 >> 16) & 0x3F; - ts_date->day = tmp1 & 0x3F; - ts_date->month = (tmp1 >> 8) & 0x1F; - ts_date->year = (tmp1 >> 16) & 0xFF; - ts_date->week = (tmp1 >> 24) & 0x7; - } - - return; + uint32_t tmp0, tmp1; + + assert_param(ts_time != NULL); + assert_param(ts_date != NULL); + assert_param(IS_RTC_FORMAT(format)); + + ts_time->sub_sec = RTC->TSSSEC & 0xFFFF; + tmp0 = RTC->TSTIME; + tmp1 = RTC->TSDATE; + + if (format == RTC_FORMAT_DEC) { + ts_time->second = bcd_to_dec(tmp0 & 0x7F); + ts_time->minute = bcd_to_dec((tmp0 >> 8) & 0x7F); + ts_time->hour = bcd_to_dec((tmp0 >> 16) & 0x3F); + ts_date->day = bcd_to_dec(tmp1 & 0x3F); + ts_date->month = bcd_to_dec((tmp1 >> 8) & 0x1F); + ts_date->year = bcd_to_dec((tmp1 >> 16) & 0xFF); + ts_date->week = bcd_to_dec((tmp1 >> 24) & 0x7); + } + else { + ts_time->second = tmp0 & 0x7F; + ts_time->minute = (tmp0 >> 8) & 0x7F; + ts_time->hour = (tmp0 >> 16) & 0x3F; + ts_date->day = tmp1 & 0x3F; + ts_date->month = (tmp1 >> 8) & 0x1F; + ts_date->year = (tmp1 >> 16) & 0xFF; + ts_date->week = (tmp1 >> 24) & 0x7; + } + + return; } /** * @} @@ -829,30 +785,28 @@ void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format */ void ald_rtc_set_tamper(rtc_tamper_t *tamper) { - assert_param(IS_RTC_TAMPER(tamper->idx)); - assert_param(IS_RTC_TAMPER_TRIGGER(tamper->trig)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(tamper->freq)); - assert_param(IS_RTC_TAMPER_DURATION(tamper->dur)); - assert_param(IS_FUNC_STATE(tamper->ts)); - - RTC_UNLOCK(); - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPTS_MSK, tamper->ts << RTC_TAMPCON_TAMPTS_POS); - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPCKS_MSK, tamper->freq << RTC_TAMPCON_TAMPCKS_POSS); - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPFLT_MSK, tamper->dur << RTC_TAMPCON_TAMPFLT_POSS); - - if (tamper->idx == RTC_TAMPER_0) - { - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP1LV_MSK, tamper->trig << RTC_TAMPCON_TAMP1LV_POS); - SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); - } - else - { - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP2LV_MSK, tamper->trig << RTC_TAMPCON_TAMP2LV_POS); - SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK); - } - - RTC_LOCK(); - return; + assert_param(IS_RTC_TAMPER(tamper->idx)); + assert_param(IS_RTC_TAMPER_TRIGGER(tamper->trig)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(tamper->freq)); + assert_param(IS_RTC_TAMPER_DURATION(tamper->dur)); + assert_param(IS_FUNC_STATE(tamper->ts)); + + RTC_UNLOCK(); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPTS_MSK, tamper->ts << RTC_TAMPCON_TAMPTS_POS); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPCKS_MSK, tamper->freq << RTC_TAMPCON_TAMPCKS_POSS); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPFLT_MSK, tamper->dur << RTC_TAMPCON_TAMPFLT_POSS); + + if (tamper->idx == RTC_TAMPER_0) { + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP0LV_MSK, tamper->trig << RTC_TAMPCON_TAMP0LV_POS); + SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP0EN_MSK); + } + else { + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP1LV_MSK, tamper->trig << RTC_TAMPCON_TAMP1LV_POS); + SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); + } + + RTC_LOCK(); + return; } /** @@ -864,17 +818,17 @@ void ald_rtc_set_tamper(rtc_tamper_t *tamper) */ void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx) { - assert_param(IS_RTC_TAMPER(idx)); + assert_param(IS_RTC_TAMPER(idx)); - RTC_UNLOCK(); + RTC_UNLOCK(); - if (idx == RTC_TAMPER_0) - CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); - else - CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK); + if (idx == RTC_TAMPER_0) + CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP0EN_MSK); + else + CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); - RTC_LOCK(); - return; + RTC_LOCK(); + return; } /** * @} @@ -905,15 +859,15 @@ void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx) */ void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value) { - assert_param(IS_RTC_WAKEUP_CLOCK(clock)); + assert_param(IS_RTC_WAKEUP_CLOCK(clock)); - RTC_UNLOCK(); - MODIFY_REG(RTC->CON, RTC_CON_WUCKS_MSK, clock << RTC_CON_WUCKS_POSS); - WRITE_REG(RTC->WUMAT, value & 0xFFFF); - SET_BIT(RTC->CON, RTC_CON_WUTE_MSK); - RTC_LOCK(); + RTC_UNLOCK(); + MODIFY_REG(RTC->CON, RTC_CON_WUCKS_MSK, clock << RTC_CON_WUCKS_POSS); + WRITE_REG(RTC->WUMAT, value & 0xFFFF); + SET_BIT(RTC->CON, RTC_CON_WUTE_MSK); + RTC_LOCK(); - return; + return; } /** @@ -922,11 +876,11 @@ void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value) */ void ald_rtc_cancel_wakeup(void) { - RTC_UNLOCK(); - CLEAR_BIT(RTC->CON, RTC_CON_WUTE_MSK); - RTC_LOCK(); + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_WUTE_MSK); + RTC_LOCK(); - return; + return; } /** @@ -935,7 +889,7 @@ void ald_rtc_cancel_wakeup(void) */ uint16_t ald_rtc_get_wakeup_timer_value(void) { - return RTC->WUMAT & 0xFFFF; + return RTC->WUMAT & 0xFFFF; } /** * @} @@ -964,33 +918,28 @@ uint16_t ald_rtc_get_wakeup_timer_value(void) */ ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock) { - uint32_t cnt = 4000; - assert_param(IS_RTC_CLOCK_OUTPUT(clock)); - - SYSCFG_UNLOCK(); - - if (clock == RTC_CLOCK_OUTPUT_EXA_1) - { - SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); - - while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2LCKN_MSK)) && (--cnt)); - - cnt = 4000; - - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL2RDY_MSK))) && (--cnt)); - } - else - { - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); - } - - SYSCFG_LOCK(); - RTC_UNLOCK(); - MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, clock << RTC_CON_CKOS_POSS); - SET_BIT(RTC->CON, RTC_CON_CKOE_MSK); - RTC_LOCK(); - - return OK; + uint32_t cnt = 4000; + assert_param(IS_RTC_CLOCK_OUTPUT(clock)); + + SYSCFG_UNLOCK(); + + if (clock == RTC_CLOCK_OUTPUT_EXA_1) { + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2LCKN_MSK)) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL2RDY_MSK))) && (--cnt)); + } + else { + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + } + + SYSCFG_LOCK(); + RTC_UNLOCK(); + MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, clock << RTC_CON_CKOS_POSS); + SET_BIT(RTC->CON, RTC_CON_CKOE_MSK); + RTC_LOCK(); + + return OK; } /** @@ -999,11 +948,11 @@ ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock) */ void ald_rtc_cancel_clock_output(void) { - RTC_UNLOCK(); - CLEAR_BIT(RTC->CON, RTC_CON_CKOE_MSK); - RTC_LOCK(); + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_CKOE_MSK); + RTC_LOCK(); - return; + return; } /** * @} @@ -1042,18 +991,18 @@ void ald_rtc_cancel_clock_output(void) */ void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state) { - assert_param(IS_RTC_IT(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_RTC_IT(it)); + assert_param(IS_FUNC_STATE(state)); - RTC_UNLOCK(); + RTC_UNLOCK(); - if (state == ENABLE) - SET_BIT(RTC->IER, it); - else - CLEAR_BIT(RTC->IER, it); + if (state == ENABLE) + SET_BIT(RTC->IER, it); + else + CLEAR_BIT(RTC->IER, it); - RTC_LOCK(); - return; + RTC_LOCK(); + return; } /** @@ -1068,18 +1017,18 @@ void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state) */ void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state) { - assert_param(IS_RTC_ALARM(idx)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_RTC_ALARM(idx)); + assert_param(IS_FUNC_STATE(state)); - RTC_UNLOCK(); + RTC_UNLOCK(); - if (idx == RTC_ALARM_A) - MODIFY_REG(RTC->CON, RTC_CON_ALMAEN_MSK, state << RTC_CON_ALMAEN_POS); - else - MODIFY_REG(RTC->CON, RTC_CON_ALMBEN_MSK, state << RTC_CON_ALMBEN_POS); + if (idx == RTC_ALARM_A) + MODIFY_REG(RTC->CON, RTC_CON_ALMAEN_MSK, state << RTC_CON_ALMAEN_POS); + else + MODIFY_REG(RTC->CON, RTC_CON_ALMBEN_MSK, state << RTC_CON_ALMBEN_POS); - RTC_LOCK(); - return; + RTC_LOCK(); + return; } /** @@ -1090,25 +1039,24 @@ void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state) */ ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) { - uint32_t tick; + uint32_t tick; - assert_param(IS_FUNC_STATE(add_1s)); - assert_param(IS_SHIFT_SUB_SS(sub_ss)); + assert_param(IS_FUNC_STATE(add_1s)); + assert_param(IS_SHIFT_SUB_SS(sub_ss)); - RTC_UNLOCK(); - MODIFY_REG(RTC->SSECTR, RTC_SSECTR_TRIM_MSK, sub_ss << RTC_SSECTR_TRIM_POSS); - MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS); - RTC_LOCK(); + RTC_UNLOCK(); + MODIFY_REG(RTC->SSECTR, RTC_SSECTR_TRIM_MSK, sub_ss << RTC_SSECTR_TRIM_POSS); + MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS); + RTC_LOCK(); - tick = ald_get_tick(); + tick = ald_get_tick(); - while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK)) - { - if ((ald_get_tick() - tick) > RTC_TIMEOUT_VALUE) - return TIMEOUT; - } + while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK)) { + if ((ald_get_tick() - tick) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } - return OK; + return OK; } /** @@ -1118,26 +1066,26 @@ ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) */ void ald_rtc_set_cali(rtc_cali_t *config) { - assert_param(IS_RTC_CALI_FREQ(config->cali_freq)); - assert_param(IS_RTC_CALI_TC(config->tc)); - assert_param(IS_RTC_CALC_FREQ(config->calc_freq)); - assert_param(IS_RTC_CALI_CALC(config->calc)); - assert_param(IS_FUNC_STATE(config->acc)); - - RTC_UNLOCK(); - RTC_CALI_UNLOCK(); - - MODIFY_REG(RTC->CALCON, RTC_CALCON_CALP_MSK, config->cali_freq << RTC_CALCON_CALP_POSS); - MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, config->tc << RTC_CALCON_TCM_POSS); - MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, config->calc_freq << RTC_CALCON_TCP_POSS); - MODIFY_REG(RTC->CALCON, RTC_CALCON_ALG_MSK, config->calc << RTC_CALCON_ALG_POS); - MODIFY_REG(RTC->CALCON, RTC_CALCON_DCMACC_MSK, config->acc << RTC_CALCON_DCMACC_POS); - SET_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); - - RTC_CALI_LOCK(); - RTC_LOCK(); - - return; + assert_param(IS_RTC_CALI_FREQ(config->cali_freq)); + assert_param(IS_RTC_CALI_TC(config->tc)); + assert_param(IS_RTC_CALC_FREQ(config->calc_freq)); + assert_param(IS_RTC_CALI_CALC(config->calc)); + assert_param(IS_FUNC_STATE(config->acc)); + + RTC_UNLOCK(); + RTC_CALI_UNLOCK(); + + MODIFY_REG(RTC->CALCON, RTC_CALCON_CALP_MSK, config->cali_freq << RTC_CALCON_CALP_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, config->tc << RTC_CALCON_TCM_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, config->calc_freq << RTC_CALCON_TCP_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_ALG_MSK, config->calc << RTC_CALCON_ALG_POS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_DCMACC_MSK, config->acc << RTC_CALCON_DCMACC_POS); + SET_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); + + RTC_CALI_LOCK(); + RTC_LOCK(); + + return; } /** @@ -1146,11 +1094,11 @@ void ald_rtc_set_cali(rtc_cali_t *config) */ void ald_rtc_cancel_cali(void) { - RTC_CALI_UNLOCK(); - CLEAR_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); - RTC_CALI_LOCK(); + RTC_CALI_UNLOCK(); + CLEAR_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); + RTC_CALI_LOCK(); - return; + return; } /** @@ -1159,10 +1107,10 @@ void ald_rtc_cancel_cali(void) */ ald_status_t ald_rtc_get_cali_status(void) { - if (READ_BIT(RTC->CALCON, RTC_CALCON_ERR_MSK)) - return ERROR; - else - return OK; + if (READ_BIT(RTC->CALCON, RTC_CALCON_ERR_MSK)) + return ERROR; + else + return OK; } /** @@ -1172,11 +1120,11 @@ ald_status_t ald_rtc_get_cali_status(void) */ void ald_rtc_write_temp(uint16_t temp) { - RTC_CALI_UNLOCK(); - MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, temp << RTC_TEMPR_VAL_POSS); - RTC_CALI_LOCK(); + RTC_CALI_UNLOCK(); + MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, temp << RTC_TEMPR_VAL_POSS); + RTC_CALI_LOCK(); - return; + return; } /** @@ -1189,12 +1137,12 @@ void ald_rtc_write_temp(uint16_t temp) */ it_status_t ald_rtc_get_it_status(rtc_it_t it) { - assert_param(IS_RTC_IT(it)); + assert_param(IS_RTC_IT(it)); - if (READ_BIT(RTC->IER, it)) - return SET; + if (READ_BIT(RTC->IER, it)) + return SET; - return RESET; + return RESET; } /** @@ -1207,12 +1155,12 @@ it_status_t ald_rtc_get_it_status(rtc_it_t it) */ flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag) { - assert_param(IS_RTC_IF(flag)); + assert_param(IS_RTC_IF(flag)); - if (READ_BIT(RTC->IFR, flag)) - return SET; + if (READ_BIT(RTC->IFR, flag)) + return SET; - return RESET; + return RESET; } /** @brief Clear the specified RTC pending flag. @@ -1221,13 +1169,13 @@ flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag) */ void ald_rtc_clear_flag_status(rtc_flag_t flag) { - assert_param(IS_RTC_IF(flag)); + assert_param(IS_RTC_IF(flag)); - RTC_UNLOCK(); - WRITE_REG(RTC->IFCR, flag); - RTC_LOCK(); + RTC_UNLOCK(); + WRITE_REG(RTC->IFCR, flag); + RTC_LOCK(); - return; + return; } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c index e7d1f466223fe4b7e4cbd7414e8d89912ede3827..2b3552ab77779cc33c4eff58e7e2a56250066e93 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c @@ -122,9 +122,9 @@ static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hsmartcard); static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh); static void smartcard_set_config(smartcard_handle_t *hperh); #ifdef ALD_DMA - static void smartcard_dma_send_cplt(void *arg); - static void smartcard_dma_recv_cplt(void *arg); - static void smartcard_dma_error(void *arg); +static void smartcard_dma_send_cplt(void *arg); +static void smartcard_dma_recv_cplt(void *arg); +static void smartcard_dma_error(void *arg); #endif static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout); /** @@ -204,33 +204,33 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t */ ald_status_t ald_smartcard_init(smartcard_handle_t *hperh) { - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); - assert_param(IS_USART_PARITY(hperh->init.parity)); - assert_param(IS_USART(hperh->perh)); - assert_param(IS_FUNC_STATE(hperh->init.nack)); - assert_param(IS_SMARTCARD_PRESCALER(hperh->init.prescaler)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_USART_PARITY(hperh->init.parity)); + assert_param(IS_USART(hperh->perh)); + assert_param(IS_FUNC_STATE(hperh->init.nack)); + assert_param(IS_SMARTCARD_PRESCALER(hperh->init.prescaler)); - if (hperh->state == SMARTCARD_STATE_RESET) - hperh->lock = UNLOCK; + if (hperh->state == SMARTCARD_STATE_RESET) + hperh->lock = UNLOCK; - hperh->state = SMARTCARD_STATE_BUSY; - SMARTCARD_DISABLE(hperh); + hperh->state = SMARTCARD_STATE_BUSY; + SMARTCARD_DISABLE(hperh); - MODIFY_REG(hperh->perh->GP, USART_GP_PSC_MSK, hperh->init.prescaler << USART_GP_PSC_POSS); - MODIFY_REG(hperh->perh->GP, USART_GP_GTVAL_MSK, hperh->init.guard_time << USART_GP_GTVAL_POSS); - smartcard_set_config(hperh); + MODIFY_REG(hperh->perh->GP, USART_GP_PSC_MSK, hperh->init.prescaler << USART_GP_PSC_POSS); + MODIFY_REG(hperh->perh->GP, USART_GP_GTVAL_MSK, hperh->init.guard_time << USART_GP_GTVAL_POSS); + smartcard_set_config(hperh); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - SMARTCARD_ENABLE(hperh); - MODIFY_REG(hperh->perh->CON2, USART_CON2_NACK_MSK, hperh->init.nack << USART_CON2_NACK_POS); - SET_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + SMARTCARD_ENABLE(hperh); + MODIFY_REG(hperh->perh->CON2, USART_CON2_NACK_MSK, hperh->init.nack << USART_CON2_NACK_POS); + SET_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - hperh->err_code = SMARTCARD_ERROR_NONE; - hperh->state = SMARTCARD_STATE_READY; - return OK; + hperh->err_code = SMARTCARD_ERROR_NONE; + hperh->state = SMARTCARD_STATE_READY; + return OK; } /** @@ -241,22 +241,22 @@ ald_status_t ald_smartcard_init(smartcard_handle_t *hperh) */ ald_status_t ald_smartcard_reset(smartcard_handle_t *hperh) { - assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART(hperh->perh)); - hperh->state = SMARTCARD_STATE_BUSY; - SMARTCARD_DISABLE(hperh); + hperh->state = SMARTCARD_STATE_BUSY; + SMARTCARD_DISABLE(hperh); - WRITE_REG(hperh->perh->CON0, 0x0); - WRITE_REG(hperh->perh->CON1, 0x0); - WRITE_REG(hperh->perh->CON2, 0x0); - WRITE_REG(hperh->perh->BAUDCON, 0x0); - WRITE_REG(hperh->perh->GP, 0x0); + WRITE_REG(hperh->perh->CON0, 0x0); + WRITE_REG(hperh->perh->CON1, 0x0); + WRITE_REG(hperh->perh->CON2, 0x0); + WRITE_REG(hperh->perh->BAUDCON, 0x0); + WRITE_REG(hperh->perh->GP, 0x0); - hperh->err_code = SMARTCARD_ERROR_NONE; - hperh->state = SMARTCARD_STATE_RESET; - __UNLOCK(hperh); + hperh->err_code = SMARTCARD_ERROR_NONE; + hperh->state = SMARTCARD_STATE_RESET; + __UNLOCK(hperh); - return OK; + return OK; } /** * @} @@ -322,42 +322,38 @@ ald_status_t ald_smartcard_reset(smartcard_handle_t *hperh) */ ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - hperh->err_code = SMARTCARD_ERROR_NONE; - SET_BIT(hperh->state, USART_STATE_TX_MASK); - - hperh->tx_size = size; - hperh->tx_count = size; - - while (hperh->tx_count-- > 0) - { - if (smartcard_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) - { - hperh->state = SMARTCARD_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - WRITE_REG(hperh->perh->DATA, *buf++); - } - - if (smartcard_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) - { - hperh->state = SMARTCARD_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); - __UNLOCK(hperh); - - return OK; + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = SMARTCARD_ERROR_NONE; + SET_BIT(hperh->state, USART_STATE_TX_MASK); + + hperh->tx_size = size; + hperh->tx_count = size; + + while (hperh->tx_count-- > 0) { + if (smartcard_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { + hperh->state = SMARTCARD_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + WRITE_REG(hperh->perh->DATA, *buf++); + } + + if (smartcard_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) { + hperh->state = SMARTCARD_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); + __UNLOCK(hperh); + + return OK; } /** @@ -371,35 +367,32 @@ ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_ */ ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) - return BUSY; + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; - if ((buf == NULL) || (size == 0)) - return ERROR; + __LOCK(hperh); + hperh->err_code = SMARTCARD_ERROR_NONE; + SET_BIT(hperh->state, USART_STATE_RX_MASK); - __LOCK(hperh); - hperh->err_code = SMARTCARD_ERROR_NONE; - SET_BIT(hperh->state, USART_STATE_RX_MASK); + hperh->rx_size = size; + hperh->rx_count = size; - hperh->rx_size = size; - hperh->rx_count = size; + while (hperh->rx_count-- > 0) { + if (smartcard_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { + hperh->state = SMARTCARD_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } - while (hperh->rx_count-- > 0) - { - if (smartcard_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) - { - hperh->state = SMARTCARD_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } + *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } - *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } + __UNLOCK(hperh); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - __UNLOCK(hperh); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - - return OK; + return OK; } /** @@ -412,25 +405,24 @@ ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_ */ ald_status_t ald_smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) { - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_TX_MASK); + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_TX_MASK); - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = SMARTCARD_ERROR_NONE; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = SMARTCARD_ERROR_NONE; - __UNLOCK(hperh); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, ENABLE); + __UNLOCK(hperh); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, ENABLE); - return OK; + return OK; } /** @@ -443,26 +435,25 @@ ald_status_t ald_smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, u */ ald_status_t ald_smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) { - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = SMARTCARD_ERROR_NONE; + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = SMARTCARD_ERROR_NONE; - __UNLOCK(hperh); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, ENABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); + __UNLOCK(hperh); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); - return OK; + return OK; } #ifdef ALD_DMA @@ -477,44 +468,43 @@ ald_status_t ald_smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, u */ ald_status_t ald_smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_TX_MASK); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = SMARTCARD_ERROR_NONE; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = smartcard_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = smartcard_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmatx); - - ald_usart_clear_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); - __UNLOCK(hperh); - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, ENABLE); - - return OK; + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_TX_MASK); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = SMARTCARD_ERROR_NONE; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = smartcard_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = smartcard_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + ald_usart_clear_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); + __UNLOCK(hperh); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, ENABLE); + + return OK; } /** @@ -529,43 +519,42 @@ ald_status_t ald_smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, */ ald_status_t ald_smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = SMARTCARD_ERROR_NONE; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = smartcard_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = smartcard_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmarx); - - __UNLOCK(hperh); - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, ENABLE); - - return OK; + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = SMARTCARD_ERROR_NONE; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = smartcard_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = smartcard_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + __UNLOCK(hperh); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, ENABLE); + + return OK; } #endif @@ -577,65 +566,57 @@ ald_status_t ald_smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, */ void ald_smartcard_irq_handler(smartcard_handle_t *hperh) { - uint32_t flag; - uint32_t source; - - /* Handle parity error */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_PE); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_PE); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= SMARTCARD_ERROR_PE; - - /* Handle frame error */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_FE); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_ERR); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= SMARTCARD_ERROR_FE; - - /* Handle noise error */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_NE); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= SMARTCARD_ERROR_NE; - - /* Handle overrun error */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_ORE); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= SMARTCARD_ERROR_ORE; - - /* Handle receive */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_RXNE); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_RXNE); - - if ((flag != RESET) && (source != RESET)) - __smartcard_recv_by_it(hperh); - - /* Handle transmit */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TXE); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TXE); - - if ((flag != RESET) && (source != RESET)) - __smartcard_send_by_it(hperh); - - /* Handle transmit complete */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TC); - - if ((flag != RESET) && (source != RESET)) - __smartcard_end_send_by_it(hperh); - - /* Handle error */ - if (hperh->err_code != SMARTCARD_ERROR_NONE) - { - USART_CLEAR_PEFLAG(hperh); - hperh->state = SMARTCARD_STATE_READY; - - if (hperh->error_cbk) - hperh->error_cbk(hperh); - } + uint32_t flag; + uint32_t source; + + /* Handle parity error */ + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_PE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_PE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= SMARTCARD_ERROR_PE; + + /* Handle frame error */ + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_FE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_ERR); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= SMARTCARD_ERROR_FE; + + /* Handle noise error */ + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_NE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= SMARTCARD_ERROR_NE; + + /* Handle overrun error */ + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_ORE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= SMARTCARD_ERROR_ORE; + + /* Handle receive */ + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_RXNE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) + __smartcard_recv_by_it(hperh); + + /* Handle transmit */ + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TXE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) + __smartcard_send_by_it(hperh); + + /* Handle transmit complete */ + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TC); + if ((flag != RESET) && (source != RESET)) + __smartcard_end_send_by_it(hperh); + + /* Handle error */ + if (hperh->err_code != SMARTCARD_ERROR_NONE) { + USART_CLEAR_PEFLAG(hperh); + hperh->state = SMARTCARD_STATE_READY; + + if (hperh->error_cbk) + hperh->error_cbk(hperh); + } } /** * @} @@ -668,7 +649,7 @@ void ald_smartcard_irq_handler(smartcard_handle_t *hperh) */ smartcard_state_t ald_smartcard_get_state(smartcard_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** @@ -679,7 +660,7 @@ smartcard_state_t ald_smartcard_get_state(smartcard_handle_t *hperh) */ uint32_t ald_smartcard_get_error(smartcard_handle_t *hperh) { - return hperh->err_code; + return hperh->err_code; } /** @@ -704,13 +685,13 @@ uint32_t ald_smartcard_get_error(smartcard_handle_t *hperh) */ static void smartcard_dma_send_cplt(void *arg) { - smartcard_handle_t *hperh = (smartcard_handle_t *)arg; + smartcard_handle_t* hperh = ( smartcard_handle_t *)arg; - hperh->tx_count = 0; - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); + hperh->tx_count = 0; + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); - return; + return; } /** @@ -721,16 +702,16 @@ static void smartcard_dma_send_cplt(void *arg) */ static void smartcard_dma_recv_cplt(void *arg) { - smartcard_handle_t *hperh = (smartcard_handle_t *)arg; + smartcard_handle_t* hperh = ( smartcard_handle_t* )arg; - hperh->rx_count = 0; - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + hperh->rx_count = 0; + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); - return; + return; } /** @@ -741,20 +722,20 @@ static void smartcard_dma_recv_cplt(void *arg) */ static void smartcard_dma_error(void *arg) { - smartcard_handle_t *hperh = (smartcard_handle_t *)arg; + smartcard_handle_t* hperh = ( smartcard_handle_t* )arg; - hperh->rx_count = 0; - hperh->tx_count = 0; - hperh->err_code = SMARTCARD_ERROR_DMA; - hperh->state = SMARTCARD_STATE_READY; + hperh->rx_count = 0; + hperh->tx_count = 0; + hperh->err_code = SMARTCARD_ERROR_DMA; + hperh->state = SMARTCARD_STATE_READY; - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); - if (hperh->error_cbk) - hperh->error_cbk(hperh); + if (hperh->error_cbk) + hperh->error_cbk(hperh); - return; + return; } #endif @@ -769,27 +750,25 @@ static void smartcard_dma_error(void *arg) */ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout) { - uint32_t tick; + uint32_t tick; - if (timeout == 0) - return OK; + if (timeout == 0) + return OK; - tick = ald_get_tick(); + tick = ald_get_tick(); - while ((ald_usart_get_flag_status((usart_handle_t *)hperh, flag)) != status) - { - if (((ald_get_tick()) - tick) > timeout) - { - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + while ((ald_usart_get_flag_status((usart_handle_t *)hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) { + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); - return TIMEOUT; - } - } + return TIMEOUT; + } + } - return OK; + return OK; } /** @@ -802,18 +781,17 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t */ static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh) { - if ((hperh->state != SMARTCARD_STATE_BUSY_TX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX)) - return BUSY; + if ((hperh->state != SMARTCARD_STATE_BUSY_TX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX)) + return BUSY; - WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); + WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); - if (--hperh->tx_count == 0) - { - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); - } + if (--hperh->tx_count == 0) { + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); + } - return OK; + return OK; } @@ -825,16 +803,16 @@ static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh) */ static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hperh) { - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); - if (hperh->state == SMARTCARD_STATE_READY) - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + if (hperh->state == SMARTCARD_STATE_READY) + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); - if (hperh->tx_cplt_cbk) - hperh->tx_cplt_cbk(hperh); + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); - return OK; + return OK; } @@ -846,23 +824,22 @@ static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hperh) */ static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh) { - if ((hperh->state != SMARTCARD_STATE_BUSY_RX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX)) - return BUSY; + if ((hperh->state != SMARTCARD_STATE_BUSY_RX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX)) + return BUSY; - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - if (--hperh->rx_count == 0) - { - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + if (--hperh->rx_count == 0) { + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - } + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } - return OK; + return OK; } /** @@ -873,68 +850,65 @@ static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh) */ static void smartcard_set_config(smartcard_handle_t *hperh) { - uint32_t tmp; - uint32_t integer; - uint32_t fractional; - - /* Check the parameters */ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_BAUDRATE(hperh->init.baud)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); - assert_param(IS_USART_PARITY(hperh->init.parity)); - assert_param(IS_USART_MODE(hperh->init.mode)); - - MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS); - tmp = READ_REG(hperh->perh->CON0); - MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS); - - if (hperh->init.parity == USART_PARITY_NONE) - CLEAR_BIT(tmp, USART_CON0_PEN_MSK); - else - SET_BIT(tmp, USART_CON0_PEN_MSK); - - if (hperh->init.parity == USART_PARITY_ODD) - SET_BIT(tmp, USART_CON0_PSEL_MSK); - else - CLEAR_BIT(tmp, USART_CON0_PSEL_MSK); - - WRITE_REG(hperh->perh->CON0, tmp); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RTSEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_CTSEN_MSK); - MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS); - MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS); - tmp = READ_REG(hperh->perh->CON1); - SET_BIT(tmp, USART_CON1_SCKEN_MSK); - MODIFY_REG(tmp, USART_CON1_SCKPOL_MSK, hperh->init.polarity << USART_CON1_SCKPOL_POS); - MODIFY_REG(tmp, USART_CON1_SCKPHA_MSK, hperh->init.phase << USART_CON1_SCKPHA_POS); - MODIFY_REG(tmp, USART_CON1_LBCP_MSK, hperh->init.last_bit << USART_CON1_LBCP_POS); - - /* Determine the integer part */ - if (READ_BIT(hperh->perh->CON0, (1 << 15))) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); - } - else - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); - } - - tmp = (integer / 100) << 4; - - /* Determine the fractional part */ - fractional = integer - (100 * (tmp >> 4)); - - /* Implement the fractional part in the register */ - if (READ_BIT(hperh->perh->CON0, (1 << 15))) - tmp |= ((((fractional * 8) + 50) / 100)) & ((uint8_t)0x07); - else - tmp |= ((((fractional * 16) + 50) / 100)) & ((uint8_t)0x0F); - - WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp); - return; + uint32_t tmp; + uint32_t integer; + uint32_t fractional; + + /* Check the parameters */ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_BAUDRATE(hperh->init.baud)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_USART_PARITY(hperh->init.parity)); + assert_param(IS_USART_MODE(hperh->init.mode)); + + MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS); + tmp = READ_REG(hperh->perh->CON0); + MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS); + + if (hperh->init.parity == USART_PARITY_NONE) + CLEAR_BIT(tmp, USART_CON0_PEN_MSK); + else + SET_BIT(tmp, USART_CON0_PEN_MSK); + + if (hperh->init.parity == USART_PARITY_ODD) + SET_BIT(tmp, USART_CON0_PSEL_MSK); + else + CLEAR_BIT(tmp, USART_CON0_PSEL_MSK); + + WRITE_REG(hperh->perh->CON0, tmp); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RTSEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_CTSEN_MSK); + MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS); + MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS); + tmp = READ_REG(hperh->perh->CON1); + SET_BIT(tmp, USART_CON1_SCKEN_MSK); + MODIFY_REG(tmp, USART_CON1_SCKPOL_MSK, hperh->init.polarity << USART_CON1_SCKPOL_POS); + MODIFY_REG(tmp, USART_CON1_SCKPHA_MSK, hperh->init.phase << USART_CON1_SCKPHA_POS); + MODIFY_REG(tmp, USART_CON1_LBCP_MSK, hperh->init.last_bit << USART_CON1_LBCP_POS); + + /* Determine the integer part */ + if (READ_BIT(hperh->perh->CON0, (1 << 15))) { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); + } + else { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); + } + tmp = (integer / 100) << 4; + + /* Determine the fractional part */ + fractional = integer - (100 * (tmp >> 4)); + + /* Implement the fractional part in the register */ + if (READ_BIT(hperh->perh->CON0, (1 << 15))) + tmp |= ((((fractional * 8) + 50) / 100)) & ((uint8_t)0x07); + else + tmp |= ((((fractional * 16) + 50) / 100)) & ((uint8_t)0x0F); + + WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp); + return; } /** diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c index 9ab99c71a543b0a0d5c353ce8e1850b5d80c29d2..f756f6785df8d12fcb748e9b624d22e96cbc0287 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c @@ -78,10 +78,10 @@ static void __spi_send_by_it(spi_handle_t *hperh); static void __spi_recv_by_it(spi_handle_t *hperh); static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); #ifdef ALD_DMA - static void spi_dma_send_cplt(void *arg); - static void spi_dma_recv_cplt(void *arg); - static void spi_dma_send_recv_cplt(void *arg); - static void spi_dma_error(void *arg); +static void spi_dma_send_cplt(void *arg); +static void spi_dma_recv_cplt(void *arg); +static void spi_dma_send_recv_cplt(void *arg); +static void spi_dma_error(void *arg); #endif /** * @} @@ -131,14 +131,14 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); */ void ald_spi_reset(spi_handle_t *hperh) { - hperh->perh->CON1 = 0x0; - hperh->perh->CON2 = 0x0; - hperh->perh->CRCPOLY = 0x00000007; + hperh->perh->CON1 = 0x0; + hperh->perh->CON2 = 0x0; + hperh->perh->CRCPOLY = 0x00000007; - SPI_RESET_HANDLE_STATE(hperh); - __UNLOCK(hperh); + SPI_RESET_HANDLE_STATE(hperh); + __UNLOCK(hperh); - return; + return; } /** @@ -150,62 +150,59 @@ void ald_spi_reset(spi_handle_t *hperh) */ ald_status_t ald_spi_init(spi_handle_t *hperh) { - uint32_t tmp = 0; - - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_MODE(hperh->init.mode)); - assert_param(IS_SPI_DIRECTION(hperh->init.dir)); - assert_param(IS_SPI_BAUD(hperh->init.baud)); - assert_param(IS_FUNC_STATE(hperh->init.first_bit)); - assert_param(IS_FUNC_STATE(hperh->init.ss_en)); - assert_param(IS_FUNC_STATE(hperh->init.crc_calc)); - assert_param(IS_SPI_DATASIZE(hperh->init.data_size)); - assert_param(IS_SPI_CPHA(hperh->init.phase)); - assert_param(IS_SPI_CPOL(hperh->init.polarity)); - - if (hperh == NULL) - return ERROR; - - ald_spi_reset(hperh); - - tmp = hperh->perh->CON1; - - if (hperh->init.mode == SPI_MODE_MASTER) - tmp |= 1 << SPI_CON1_SSOUT_POS; - - tmp |= ((hperh->init.phase << SPI_CON1_CPHA_POS) | (hperh->init.polarity << SPI_CON1_CPOL_POS) | - (hperh->init.baud << SPI_CON1_BAUD_POSS) | (hperh->init.data_size << SPI_CON1_FLEN_POS) | - (hperh->init.mode << SPI_CON1_MSTREN_POS) | (hperh->init.ss_en << SPI_CON1_SSEN_POS) | - (hperh->init.first_bit << SPI_CON1_LSBFST_POS)); - - hperh->perh->CON1 = tmp; - - if (hperh->init.dir == SPI_DIRECTION_2LINES) - { - CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); - CLEAR_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); - } - else if (hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) - { - CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); - SET_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); - } - else - { - SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); - } - - /* configure CRC */ - hperh->perh->CON1 |= (hperh->init.crc_calc << SPI_CON1_CRCEN_POS); - hperh->perh->CRCPOLY = hperh->init.crc_poly; - - hperh->err_code = SPI_ERROR_NONE; - hperh->state = SPI_STATE_READY; - - if (hperh->init.dir == SPI_DIRECTION_2LINES) - SPI_ENABLE(hperh); - - return OK; + uint32_t tmp = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_MODE(hperh->init.mode)); + assert_param(IS_SPI_DIRECTION(hperh->init.dir)); + assert_param(IS_SPI_BAUD(hperh->init.baud)); + assert_param(IS_SPI_FIRSTBIT(hperh->init.first_bit)); + assert_param(IS_FUNC_STATE(hperh->init.ss_en)); + assert_param(IS_FUNC_STATE(hperh->init.crc_calc)); + assert_param(IS_SPI_DATASIZE(hperh->init.data_size)); + assert_param(IS_SPI_CPHA(hperh->init.phase)); + assert_param(IS_SPI_CPOL(hperh->init.polarity)); + + ald_spi_reset(hperh); + + tmp = hperh->perh->CON1; + + if (hperh->init.mode == SPI_MODE_MASTER) + tmp |= 1 << SPI_CON1_SSOUT_POS; + + tmp |= ((hperh->init.phase << SPI_CON1_CPHA_POS) | (hperh->init.polarity << SPI_CON1_CPOL_POS) | + (hperh->init.baud << SPI_CON1_BAUD_POSS) | (hperh->init.data_size << SPI_CON1_FLEN_POS) | + (hperh->init.mode << SPI_CON1_MSTREN_POS) | (hperh->init.ss_en << SPI_CON1_SSEN_POS) | + (hperh->init.first_bit << SPI_CON1_LSBFST_POS)); + + hperh->perh->CON1 = tmp; + + if (hperh->init.dir == SPI_DIRECTION_2LINES) { + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); + } + else if (hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) { + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + SET_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); + } + else { + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + } + + /* configure CRC */ + hperh->perh->CON1 |= (hperh->init.crc_calc << SPI_CON1_CRCEN_POS); + hperh->perh->CRCPOLY = hperh->init.crc_poly; + + hperh->err_code = SPI_ERROR_NONE; + hperh->state = SPI_STATE_READY; + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + SPI_ENABLE(hperh); + + return OK; } /** * @} @@ -253,20 +250,16 @@ ald_status_t ald_spi_init(spi_handle_t *hperh) */ int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data) { - uint16_t cnt = 2000, temp; + uint16_t cnt = 2000, temp; - hperh->perh->DATA = data; + hperh->perh->DATA = data; + while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); + cnt = 2000; + while ((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0 && (--cnt)); + temp = hperh->perh->DATA; + UNUSED(temp); - while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); - - cnt = 2000; - - while ((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0 && (--cnt)); - - temp = hperh->perh->DATA; - UNUSED(temp); - - return cnt == 0 ? -1 : 0; + return cnt == 0 ? -1 : 0; } /** @@ -279,13 +272,12 @@ int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data) */ int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data) { - uint16_t cnt = 2000; + uint16_t cnt = 2000; - hperh->perh->DATA = data; + hperh->perh->DATA = data; + while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); - while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); - - return cnt == 0 ? -1 : 0; + return cnt == 0 ? -1 : 0; } /** @@ -295,20 +287,16 @@ int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data) */ uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh) { - uint16_t cnt = 2000; - - if (hperh->init.mode == SPI_MODE_MASTER) - { - hperh->perh->DATA = 0xFF; - - while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); - } - - cnt = 2000; + uint16_t cnt = 2000; - while (((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0) && (--cnt)); + if (hperh->init.mode == SPI_MODE_MASTER) { + hperh->perh->DATA = 0xFF; + while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); + } - return (uint8_t)hperh->perh->DATA; + cnt = 2000; + while (((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0) && (--cnt)); + return (uint8_t)hperh->perh->DATA; } /** @@ -321,98 +309,87 @@ uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh) */ ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - - hperh->state = SPI_STATE_BUSY_TX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = NULL; - hperh->rx_size = 0; - hperh->rx_count = 0; - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if (hperh->init.dir == SPI_DIRECTION_1LINE) - SPI_1LINE_TX(hperh); - - if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) - SPI_ENABLE(hperh); - - if ((hperh->init.mode == SPI_MODE_SLAVER) || (hperh->tx_count == 1)) - { - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; - } - else - { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; - } - } - - while (hperh->tx_count > 0) - { - if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; - } - else - { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; - } - } - - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - - if ((spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) - || (spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.dir == SPI_DIRECTION_2LINES) - ald_spi_clear_flag_status(hperh, SPI_IF_OVE); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - - return OK; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + + hperh->state = SPI_STATE_BUSY_TX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + if (hperh->init.dir == SPI_DIRECTION_1LINE) + SPI_1LINE_TX(hperh); + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + SPI_ENABLE(hperh); + + if ((hperh->init.mode == SPI_MODE_SLAVER) || (hperh->tx_count == 1)) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + } + + while (hperh->tx_count > 0) { + if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + } + + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + + if ((spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) + || (spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return OK; } /** @@ -425,124 +402,111 @@ ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint */ ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - uint16_t temp; - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_RX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) - SPI_1LINE_RX(hperh); - - if ((hperh->init.mode == SPI_MODE_MASTER) && (hperh->init.dir == SPI_DIRECTION_2LINES)) - { - __UNLOCK(hperh); - hperh->state = SPI_STATE_READY; - return ald_spi_send_recv(hperh, buf, buf, size, timeout); - } - - if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) - SPI_ENABLE(hperh); - - while (hperh->rx_count > 1) - { - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else - { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; - --hperh->rx_count; - } - } - - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else - { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; - --hperh->rx_count; - } - - if (hperh->init.crc_calc) - { - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - temp = hperh->perh->DATA; - UNUSED(temp); - } - - if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) - { - hperh->err_code |= SPI_ERROR_CRC; - SPI_CRC_RESET(hperh); - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return ERROR; - } - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - - return OK; + uint16_t temp; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) + SPI_1LINE_RX(hperh); + + if ((hperh->init.mode == SPI_MODE_MASTER) && (hperh->init.dir == SPI_DIRECTION_2LINES)) { + __UNLOCK(hperh); + hperh->state = SPI_STATE_READY; + return ald_spi_send_recv(hperh, buf, buf, size, timeout); + } + + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); + + while (hperh->rx_count > 1) { + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + --hperh->rx_count; + } + + if (hperh->init.crc_calc) { + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= SPI_ERROR_CRC; + SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return ERROR; + } + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return OK; } /** @@ -556,199 +520,175 @@ ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint */ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) { - uint16_t temp; - - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - - if (hperh->init.dir != SPI_DIRECTION_2LINES) - return ERROR; - - if (tx_buf == NULL || rx_buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_TX_RX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->rx_count = size; - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if ((hperh->init.mode == SPI_MODE_SLAVER) || ((hperh->init.mode == SPI_MODE_SLAVER) && (hperh->tx_size == 1))) - { - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; - } - else - { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; - } - } - - if (hperh->tx_buf == 0) - { - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - - if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else - { - (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; - hperh->rx_buf += 2; - --hperh->rx_count; - } - } - - while (hperh->tx_count > 0) - { - if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; - } - else - { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; - } - - if ((hperh->tx_count == 0) && (hperh->init.crc_calc)) - SPI_CRCNEXT_ENABLE(hperh); - - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else - { - (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; - - hperh->rx_buf += 2; - --hperh->rx_count; - } - } - - if (hperh->init.mode == SPI_MODE_SLAVER) - { - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else - { - (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; - - hperh->rx_buf += 2; - --hperh->rx_count; - } - } - - if (hperh->init.crc_calc) - { - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - temp = hperh->perh->DATA; - UNUSED(temp); - } - - if ((spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) - { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) - { - hperh->err_code |= SPI_ERROR_CRC; - SPI_CRC_RESET(hperh); - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - - return ERROR; - } - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - - return OK; + uint16_t temp; + + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (hperh->init.dir != SPI_DIRECTION_2LINES) + return ERROR; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if ((hperh->init.mode == SPI_MODE_SLAVER) || ((hperh->init.mode == SPI_MODE_SLAVER) && (hperh->tx_size == 1))) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + } + + if (hperh->tx_count == 0) { + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + + if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + while (hperh->tx_count > 0) { + if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + + if ((hperh->tx_count == 0) && (hperh->init.crc_calc)) + SPI_CRCNEXT_ENABLE(hperh); + + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; + + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + if (hperh->init.mode == SPI_MODE_SLAVER) { + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; + + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + if (hperh->init.crc_calc) { + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if ((spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= SPI_ERROR_CRC; + SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return ERROR; + } + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return OK; } /** @@ -760,46 +700,43 @@ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx */ ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) { - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_TX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = NULL; - hperh->rx_size = 0; - hperh->rx_count = 0; - __UNLOCK(hperh); - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if (hperh->init.dir == SPI_DIRECTION_1LINE) - SPI_1LINE_TX(hperh); - - if (hperh->init.dir == SPI_DIRECTION_2LINES) - { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); - } - else - { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); - } - - if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) - SPI_ENABLE(hperh); - - return OK; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + __UNLOCK(hperh); + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->init.dir == SPI_DIRECTION_1LINE) + SPI_1LINE_TX(hperh); + + if (hperh->init.dir == SPI_DIRECTION_2LINES) { + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + } + else { + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); + } + + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + SPI_ENABLE(hperh); + + return OK; } /** @@ -811,42 +748,40 @@ ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size */ ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) { - assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI(hperh->perh)); - if (hperh->state != SPI_STATE_READY) - return BUSY; + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) + return ERROR; /* Please call ald_spi_send_recv_by_it() */ - if (buf == NULL || size == 0) - return ERROR; + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; - if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) - return ERROR; /* Please call ald_spi_send_recv_by_it() */ + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + __UNLOCK(hperh); - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_RX; - hperh->err_code = SPI_ERROR_NONE; + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) + SPI_1LINE_RX(hperh); - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; - __UNLOCK(hperh); + if (hperh->init.crc_calc == ENABLE) + SPI_CRC_RESET(hperh); - if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) - SPI_1LINE_RX(hperh); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); - if (hperh->init.crc_calc == ENABLE) - SPI_CRC_RESET(hperh); + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); - - if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) - SPI_ENABLE(hperh); - - return OK; + return OK; } /** @@ -860,34 +795,33 @@ ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size */ ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) { - assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI(hperh->perh)); - if (hperh->state != SPI_STATE_READY) - return BUSY; + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; - if (tx_buf == NULL || rx_buf == NULL || size == 0) - return ERROR; + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX_RX; + hperh->err_code = SPI_ERROR_NONE; - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_TX_RX; - hperh->err_code = SPI_ERROR_NONE; + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + __UNLOCK(hperh); - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->rx_count = size; - __UNLOCK(hperh); + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); - - return OK; + return OK; } #ifdef ALD_DMA @@ -901,59 +835,57 @@ ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8 */ ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_TX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = NULL; - hperh->rx_size = 0; - hperh->rx_count = 0; - - if (hperh->init.dir == SPI_DIRECTION_1LINE) - SPI_1LINE_TX(hperh); - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.cplt_cbk = spi_dma_send_cplt; - hperh->hdmatx.err_arg = (void *)hperh; - hperh->hdmatx.err_cbk = spi_dma_error; - - /* Configure SPI DMA transmit */ - ald_dma_config_struct(&(hperh->hdmatx.config)); - hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&(hperh->hdmatx)); - - __UNLOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); - - if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) - SPI_ENABLE(hperh); - - return OK; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + if (hperh->init.dir == SPI_DIRECTION_1LINE) + SPI_1LINE_TX(hperh); + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.cplt_cbk = spi_dma_send_cplt; + hperh->hdmatx.err_arg = (void *)hperh; + hperh->hdmatx.err_cbk = spi_dma_error; + + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&(hperh->hdmatx)); + + __UNLOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + SPI_ENABLE(hperh); + + return OK; } /** @@ -966,65 +898,61 @@ ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t siz */ ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_RX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; - - if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) - SPI_1LINE_RX(hperh); - - if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) - { - __UNLOCK(hperh); - return ERROR; /* Please use ald_spi_send_recv_by_dma() */ - } - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.cplt_cbk = spi_dma_recv_cplt; - hperh->hdmarx.err_arg = (void *)hperh; - hperh->hdmarx.err_cbk = spi_dma_error; - - /* Configure DMA Receive */ - ald_dma_config_struct(&(hperh->hdmarx.config)); - hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; - hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&(hperh->hdmarx)); - - __UNLOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); - - if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) - SPI_ENABLE(hperh); - - return OK; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) + SPI_1LINE_RX(hperh); + if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) { + __UNLOCK(hperh); + return ERROR; /* Please use ald_spi_send_recv_by_dma() */ + } + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.cplt_cbk = spi_dma_recv_cplt; + hperh->hdmarx.err_arg = (void *)hperh; + hperh->hdmarx.err_cbk = spi_dma_error; + + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; + hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&(hperh->hdmarx)); + + __UNLOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); + + return OK; } /** @@ -1039,74 +967,72 @@ ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t siz */ ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) { - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY && hperh->state != SPI_STATE_BUSY_RX) - return BUSY; - - if (tx_buf == NULL || rx_buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_RX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->rx_count = size; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmatx.cplt_arg = NULL; - hperh->hdmatx.cplt_cbk = NULL; - hperh->hdmatx.err_arg = (void *)hperh; - hperh->hdmatx.err_cbk = spi_dma_error; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.cplt_cbk = spi_dma_send_recv_cplt; - hperh->hdmarx.err_arg = (void *)hperh; - hperh->hdmarx.err_cbk = spi_dma_error; - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - /* Configure SPI DMA transmit */ - ald_dma_config_struct(&(hperh->hdmatx.config)); - hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; - hperh->hdmatx.config.src = (void *)tx_buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; - hperh->hdmatx.config.channel = tx_channel; - ald_dma_config_basic(&(hperh->hdmatx)); - - /* Configure DMA Receive */ - ald_dma_config_struct(&(hperh->hdmarx.config)); - hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)rx_buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; - hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; - hperh->hdmarx.config.channel = rx_channel; - ald_dma_config_basic(&(hperh->hdmarx)); - - __UNLOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); - - return OK; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY && hperh->state != SPI_STATE_BUSY_RX) + return BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmatx.cplt_arg = NULL; + hperh->hdmatx.cplt_cbk = NULL; + hperh->hdmatx.err_arg = (void *)hperh; + hperh->hdmatx.err_cbk = spi_dma_error; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.cplt_cbk = spi_dma_send_recv_cplt; + hperh->hdmarx.err_arg = (void *)hperh; + hperh->hdmarx.err_cbk = spi_dma_error; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)tx_buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = tx_channel; + ald_dma_config_basic(&(hperh->hdmatx)); + + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)rx_buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; + hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.channel = rx_channel; + ald_dma_config_basic(&(hperh->hdmarx)); + + __UNLOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + + return OK; } /** @@ -1116,14 +1042,14 @@ ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint */ ald_status_t ald_spi_dma_pause(spi_handle_t *hperh) { - assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI(hperh->perh)); - __LOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - __UNLOCK(hperh); + __LOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -1133,14 +1059,14 @@ ald_status_t ald_spi_dma_pause(spi_handle_t *hperh) */ ald_status_t ald_spi_dma_resume(spi_handle_t *hperh) { - assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI(hperh->perh)); - __LOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); - __UNLOCK(hperh); + __LOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -1150,15 +1076,15 @@ ald_status_t ald_spi_dma_resume(spi_handle_t *hperh) */ ald_status_t ald_spi_dma_stop(spi_handle_t *hperh) { - assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI(hperh->perh)); - __LOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - __UNLOCK(hperh); + __LOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); - hperh->state = SPI_STATE_READY; - return OK; + hperh->state = SPI_STATE_READY; + return OK; } #endif /** @@ -1193,66 +1119,65 @@ ald_status_t ald_spi_dma_stop(spi_handle_t *hperh) */ void ald_spi_irq_handler(spi_handle_t *hperh) { - if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX)) - { - if ((ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) - __spi_recv_by_it(hperh); - - if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) - __spi_send_by_it(hperh); - } - - else if (hperh->state == SPI_STATE_BUSY_TX_RX) - { - if (hperh->tx_size == hperh->tx_count) - { - if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) - __spi_send_recv_by_it(hperh, SPI_SR_TXBE); - } - else - { - if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET) - && (ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) - __spi_send_recv_by_it(hperh, SPI_SR_TXBE_RXBNE); - } - } - - if ((ald_spi_get_it_status(hperh, SPI_IT_ERR) != RESET)) - { - if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) - { - hperh->err_code |= SPI_ERROR_CRC; - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - } - - if (ald_spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) - { - hperh->err_code |= SPI_ERROR_MODF; - ald_spi_clear_flag_status(hperh, SPI_IF_MODF); - } - - if (ald_spi_get_flag_status(hperh, SPI_IF_OVE) != RESET) - { - if (hperh->state != SPI_STATE_BUSY_TX) - { - hperh->err_code |= SPI_ERROR_OVE; - ald_spi_clear_flag_status(hperh, SPI_IF_OVE); - } - } - - if (hperh->err_code != SPI_ERROR_NONE) - { - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); - hperh->state = SPI_STATE_READY; - - if (hperh->err_cbk) - hperh->err_cbk(hperh); - } - } - - return; + if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX)) { + if ((ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) + __spi_recv_by_it(hperh); + + if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) + __spi_send_by_it(hperh); + } + + else if (hperh->state == SPI_STATE_BUSY_TX_RX) { + if (hperh->tx_size == hperh->tx_count) { + if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_TXBE); + } + else { + if (hperh->init.mode == SPI_MODE_MASTER) { + if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET) + && (ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_TXBE_RXBNE); + } + else { + if ((ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_RXBNE); + + if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_TXBE); + } + + + } + } + + if ((ald_spi_get_it_status(hperh, SPI_IT_ERR) != RESET)) { + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) { + hperh->err_code |= SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + if (ald_spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) { + hperh->err_code |= SPI_ERROR_MODF; + ald_spi_clear_flag_status(hperh, SPI_IF_MODF); + } + if (ald_spi_get_flag_status(hperh, SPI_IF_OVE) != RESET) { + if ((hperh->state != SPI_STATE_BUSY_TX) && (hperh->state != SPI_STATE_READY)) { + hperh->err_code |= SPI_ERROR_OVE; + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); + } + } + + if (hperh->err_code != SPI_ERROR_NONE) { + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + } + + return; } /** @@ -1267,16 +1192,16 @@ void ald_spi_irq_handler(spi_handle_t *hperh) */ void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state) { - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_IT(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IT(it)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - hperh->perh->CON2 |= (uint32_t)it; - else - hperh->perh->CON2 &= ~((uint32_t)it); + if (state == ENABLE) + hperh->perh->CON2 |= (uint32_t)it; + else + hperh->perh->CON2 &= ~((uint32_t)it); - return; + return; } /** @@ -1288,15 +1213,15 @@ void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t stat */ void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) { - uint32_t tmp = 0; - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_BAUD(speed)); - - tmp = hperh->perh->CON1; - tmp &= ~(0x7 << SPI_CON1_BAUD_POSS); - tmp |= (speed << SPI_CON1_BAUD_POSS); - hperh->perh->CON1 = tmp; - return; + uint32_t tmp = 0; + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_BAUD(speed)); + + tmp = hperh->perh->CON1; + tmp &= ~(0x7U << SPI_CON1_BAUD_POSS); + tmp |= (speed << SPI_CON1_BAUD_POSS); + hperh->perh->CON1 = tmp; + return; } /** @@ -1311,26 +1236,24 @@ void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) */ void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state) { - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_DMA_REQ(req)); - assert_param(IS_FUNC_STATE(state)); - - if (state == ENABLE) - { - if (req == SPI_DMA_REQ_TX) - SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); - else - SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); - } - else - { - if (req == SPI_DMA_REQ_TX) - CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); - else - CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); - } - - return; + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) { + if (req == SPI_DMA_REQ_TX) + SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + else { + if (req == SPI_DMA_REQ_TX) + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + + return; } /** @brief Check whether the specified SPI state flag is set or not. @@ -1343,13 +1266,13 @@ void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t */ flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status) { - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_STATUS(status)); + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_STATUS(status)); - if (hperh->perh->STAT & status) - return SET; + if (hperh->perh->STAT & status) + return SET; - return RESET; + return RESET; } /** @@ -1363,13 +1286,13 @@ flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status) */ it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it) { - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_IT(it)); + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IT(it)); - if (hperh->perh->CON2 & it) - return SET; + if (hperh->perh->CON2 & it) + return SET; - return RESET; + return RESET; } /** @brief Check whether the specified SPI flag is set or not. @@ -1382,13 +1305,13 @@ it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it) */ flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag) { - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_IF(flag)); + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IF(flag)); - if (hperh->perh->STAT & flag) - return SET; + if (hperh->perh->STAT & flag) + return SET; - return RESET; + return RESET; } /** @brief Clear the specified SPI pending flags. @@ -1399,34 +1322,29 @@ flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag) */ void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) { - uint32_t temp; - - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_IF(flag)); - - if (flag == SPI_IF_CRCERR) - { - SET_BIT(hperh->perh->STAT, SPI_STAT_CRCERR_MSK); - return; - } - - if (flag == SPI_IF_OVE) - { - temp = hperh->perh->DATA; - temp = hperh->perh->STAT; - UNUSED(temp); - return; - } - - if (flag == SPI_IF_MODF) - { - temp = hperh->perh->STAT; - UNUSED(temp); - hperh->perh->CON1 = hperh->perh->CON1; - return; - } - - return; + uint32_t temp; + + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IF(flag)); + + if (flag == SPI_IF_CRCERR) { + SET_BIT(hperh->perh->STAT, SPI_STAT_CRCERR_MSK); + return; + } + if (flag == SPI_IF_OVE) { + temp = hperh->perh->DATA; + temp = hperh->perh->STAT; + UNUSED(temp); + return; + } + if (flag == SPI_IF_MODF) { + temp = hperh->perh->STAT; + UNUSED(temp); + hperh->perh->CON1 = hperh->perh->CON1; + return; + } + + return; } /** @@ -1439,22 +1357,20 @@ void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) */ static ald_status_t spi_wait_flag(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout) { - uint32_t tick = ald_get_tick(); - - assert_param(timeout > 0); - - while ((ald_spi_get_flag_status(hperh, flag)) != status) - { - if (((ald_get_tick()) - tick) > timeout) - { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); - return TIMEOUT; - } - } - - return OK; + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + while ((ald_spi_get_flag_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) { + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + return TIMEOUT; + } + } + + return OK; } /** @@ -1467,18 +1383,18 @@ static ald_status_t spi_wait_flag(spi_handle_t *hperh, spi_flag_t flag, flag_sta */ static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout) { - assert_param(timeout > 0); + assert_param(timeout > 0); - while (((ald_spi_get_flag_status(hperh, flag)) != status) && (--timeout)); + while (((ald_spi_get_flag_status(hperh, flag)) != status) && (--timeout)); - if (timeout) - return OK; + if (timeout) + return OK; - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); - return TIMEOUT; + return TIMEOUT; } /** @@ -1508,8 +1424,8 @@ static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag */ spi_state_t ald_spi_get_state(spi_handle_t *hperh) { - assert_param(IS_SPI(hperh->perh)); - return hperh->state; + assert_param(IS_SPI(hperh->perh)); + return hperh->state; } /** @@ -1519,8 +1435,8 @@ spi_state_t ald_spi_get_state(spi_handle_t *hperh) */ uint32_t ald_spi_get_error(spi_handle_t *hperh) { - assert_param(IS_SPI(hperh->perh)); - return hperh->err_code; + assert_param(IS_SPI(hperh->perh)); + return hperh->err_code; } /** * @} @@ -1542,48 +1458,43 @@ uint32_t ald_spi_get_error(spi_handle_t *hperh) */ static void __spi_send_by_it(spi_handle_t *hperh) { - if (hperh->tx_count == 0) - { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - hperh->state = SPI_STATE_READY; - - if (hperh->init.dir == SPI_DIRECTION_2LINES) - ald_spi_clear_flag_status(hperh, SPI_IF_OVE); - - if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) - { - if (hperh->err_cbk) - hperh->err_cbk(hperh); - - return; - } - - if (hperh->tx_cplt_cbk) - hperh->tx_cplt_cbk(hperh); - - return; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - } - else - { - hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; - hperh->tx_buf += 2; - } - - --hperh->tx_count; - - if (hperh->tx_count == 0) - { - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - } - - return; + if (hperh->tx_count == 0) { + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); + + if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else { + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + --hperh->tx_count; + + if (hperh->tx_count == 0) { + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + } + + return; } /** @@ -1593,51 +1504,45 @@ static void __spi_send_by_it(spi_handle_t *hperh) */ static void __spi_recv_by_it(spi_handle_t *hperh) { - uint16_t temp; - - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - } - else - { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; - } - - --hperh->rx_count; - - if ((hperh->rx_count == 1) && (hperh->init.crc_calc)) - SPI_CRCNEXT_ENABLE(hperh); - - if (hperh->rx_count == 0) - { - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - hperh->state = SPI_STATE_READY; - - if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) - { - hperh->err_code |= SPI_ERROR_CRC; - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - - if (hperh->err_cbk) - hperh->err_cbk(hperh); - - return; - } - - if (hperh->init.crc_calc) - { - temp = hperh->perh->DATA; - UNUSED(temp); - } - - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - } - - return; + uint16_t temp; + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + --hperh->rx_count; + + if ((hperh->rx_count == 1) && (hperh->init.crc_calc)) + SPI_CRCNEXT_ENABLE(hperh); + + if (hperh->rx_count == 0) { + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + hperh->state = SPI_STATE_READY; + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->init.crc_calc) { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return; } /** @@ -1648,99 +1553,82 @@ static void __spi_recv_by_it(spi_handle_t *hperh) */ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) { - assert_param(IS_SPI_SR_STATUS(status)); - - if (hperh->rx_count != 0) - { - if ((status == SPI_SR_RXBNE) || (status == SPI_SR_TXBE_RXBNE)) - { - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - } - else - { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; - } - - --hperh->rx_count; - } - } - - if (hperh->tx_count != 0) - { - if ((status == SPI_SR_TXBE) || (status == SPI_SR_TXBE_RXBNE)) - { - if (hperh->tx_count == 1) - { - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - } - else - { - hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; - hperh->tx_buf += 2; - } - - --hperh->tx_count; - - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - } - else - { - if (hperh->init.data_size == SPI_DATA_SIZE_8) - { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - } - else - { - hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; - hperh->tx_buf += 2; - } - - if (--hperh->tx_count == 0) - { - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - } - } - } - } - - if (hperh->rx_count == 0) - { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); - hperh->state = SPI_STATE_READY; - - if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) - { - hperh->err_code |= SPI_ERROR_CRC; - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - - if (hperh->err_cbk) - hperh->err_cbk(hperh); - - return; - } - - if (hperh->tx_rx_cplt_cbk) - hperh->tx_rx_cplt_cbk(hperh); - } - - return; + assert_param(IS_SPI_SR_STATUS(status)); + + if (hperh->rx_count != 0) { + if ((status == SPI_SR_RXBNE) || (status == SPI_SR_TXBE_RXBNE)) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + + --hperh->rx_count; + } + } + + if (hperh->tx_count != 0) { + if ((status == SPI_SR_TXBE) || (status == SPI_SR_TXBE_RXBNE)) { + if (hperh->tx_count == 1) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else { + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + + --hperh->tx_count; + + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + } + else { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else { + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + + if (--hperh->tx_count == 0) { + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + } + } + } + } + + if (hperh->rx_count == 0) { + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + hperh->state = SPI_STATE_READY; + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->tx_rx_cplt_cbk) + hperh->tx_rx_cplt_cbk(hperh); + } + + return; } - #ifdef ALD_DMA /** * @brief DMA SPI transmit process complete callback. @@ -1749,33 +1637,31 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) */ static void spi_dma_send_cplt(void *arg) { - uint16_t delay; - spi_handle_t *hperh = (spi_handle_t *)arg; + uint16_t delay; + spi_handle_t *hperh = (spi_handle_t *)arg; - hperh->tx_count = 0; - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - hperh->state = SPI_STATE_READY; + hperh->tx_count = 0; + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + hperh->state = SPI_STATE_READY; - if (hperh->init.dir == SPI_DIRECTION_2LINES) - ald_spi_clear_flag_status(hperh, SPI_IF_OVE); + if (hperh->init.dir == SPI_DIRECTION_2LINES) + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); - if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) - hperh->err_code |= SPI_ERROR_FLAG; + if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; - for (delay = 0; delay < 3000; delay++); + for (delay = 0; delay < 3000; delay++); - if (hperh->err_code == SPI_ERROR_NONE) - { - if (hperh->tx_cplt_cbk) - hperh->tx_cplt_cbk(hperh); - } - else - { - if (hperh->err_cbk) - hperh->err_cbk(hperh); - } + if (hperh->err_code == SPI_ERROR_NONE) { + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } - return; + return; } /** @@ -1785,42 +1671,38 @@ static void spi_dma_send_cplt(void *arg) */ static void spi_dma_recv_cplt(void *arg) { - uint32_t tmp; - spi_handle_t *hperh = (spi_handle_t *)arg; - - hperh->rx_count = 0; - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - hperh->state = SPI_STATE_READY; - - if (hperh->init.crc_calc) - { - if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK) - hperh->err_code |= SPI_ERROR_FLAG; - - tmp = hperh->perh->DATA; - UNUSED(tmp); - - if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) - { - SET_BIT(hperh->err_code, SPI_ERROR_CRC); - SPI_CRC_RESET(hperh); - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - } - } - - if (hperh->err_code == SPI_ERROR_NONE) - { - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - } - else - { - if (hperh->err_cbk) - hperh->err_cbk(hperh); - } - - return; + uint32_t tmp; + spi_handle_t *hperh = (spi_handle_t *)arg; + + hperh->rx_count = 0; + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->init.crc_calc) { + if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + tmp = hperh->perh->DATA; + UNUSED(tmp); + + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) { + SET_BIT(hperh->err_code, SPI_ERROR_CRC); + SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + } + + if (hperh->err_code == SPI_ERROR_NONE) { + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; } /** @@ -1830,48 +1712,44 @@ static void spi_dma_recv_cplt(void *arg) */ static void spi_dma_send_recv_cplt(void *arg) { - uint32_t tmp; - uint16_t delay; - spi_handle_t *hperh = (spi_handle_t *)arg; - - if (hperh->init.crc_calc) - { - if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK) - hperh->err_code |= SPI_ERROR_FLAG; - - tmp = hperh->perh->DATA; - UNUSED(tmp); - - if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) - { - SET_BIT(hperh->err_code, SPI_ERROR_CRC); - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - } - } - - if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) - hperh->err_code |= SPI_ERROR_FLAG; - - for (delay = 0; delay < 3000; delay++); - - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - hperh->tx_count = 0; - hperh->rx_count = 0; - hperh->state = SPI_STATE_READY; - - if (hperh->err_code == SPI_ERROR_NONE) - { - if (hperh->tx_rx_cplt_cbk) - hperh->tx_rx_cplt_cbk(hperh); - } - else - { - if (hperh->err_cbk) - hperh->err_cbk(hperh); - } - - return; + uint32_t tmp; + uint16_t delay; + spi_handle_t *hperh = (spi_handle_t *)arg; + + if (hperh->init.crc_calc) { + if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + tmp = hperh->perh->DATA; + UNUSED(tmp); + + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) { + SET_BIT(hperh->err_code, SPI_ERROR_CRC); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + } + + if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + for (delay = 0; delay < 3000; delay++); + + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + hperh->tx_count = 0; + hperh->rx_count = 0; + hperh->state = SPI_STATE_READY; + + if (hperh->err_code == SPI_ERROR_NONE) { + if (hperh->tx_rx_cplt_cbk) + hperh->tx_rx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; } /** @@ -1882,20 +1760,20 @@ static void spi_dma_send_recv_cplt(void *arg) */ static void spi_dma_error(void *arg) { - spi_handle_t *hperh = (spi_handle_t *)arg; + spi_handle_t *hperh = (spi_handle_t *)arg; - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - SET_BIT(hperh->err_code, SPI_ERROR_DMA); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + SET_BIT(hperh->err_code, SPI_ERROR_DMA); - hperh->tx_count = 0; - hperh->rx_count = 0; - hperh->state = SPI_STATE_READY; + hperh->tx_count = 0; + hperh->rx_count = 0; + hperh->state = SPI_STATE_READY; - if (hperh->err_cbk) - hperh->err_cbk(hperh); + if (hperh->err_cbk) + hperh->err_cbk(hperh); - return; + return; } #endif /* ALD_DMA */ /** diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c index 677bbdcf86eabab4b48eed0542015e6234580949..dc0a2853686fccd2e5b88e1370955774e14bc139 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c @@ -38,26 +38,26 @@ static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_conf static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); -static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state); -static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state); +static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state); +static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state); static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter); + timer_ic_select_t sel, uint32_t filter); static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter); static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter); + timer_ic_select_t sel, uint32_t filter); static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter); static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter); + timer_ic_select_t sel, uint32_t filter); static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter); -static void timer_etr_set_config(TIMER_TypeDef *TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter); + timer_ic_select_t sel, uint32_t filter); +static void timer_etr_set_config(TIMER_TypeDef* TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter); static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config); #ifdef ALD_DMA - static void timer_dma_oc_cplt(void *arg); - static void timer_dma_capture_cplt(void *arg); - static void timer_dma_period_elapse_cplt(void *arg); - static void timer_dma_error(void *arg); - static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config); +static void timer_dma_oc_cplt(void *arg); +static void timer_dma_capture_cplt(void *arg); +static void timer_dma_period_elapse_cplt(void *arg); +static void timer_dma_error(void *arg); +static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config); #endif /** * @} @@ -96,21 +96,21 @@ static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t * */ ald_status_t ald_timer_base_init(timer_handle_t *hperh) { - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); - assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); - if (hperh->state == TIMER_STATE_RESET) - hperh->lock = UNLOCK; + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; - hperh->state = TIMER_STATE_BUSY; - timer_base_set_config(hperh->perh, &hperh->init); - hperh->state = TIMER_STATE_READY; + hperh->state = TIMER_STATE_BUSY; + timer_base_set_config(hperh->perh, &hperh->init); + hperh->state = TIMER_STATE_READY; - return OK; + return OK; } /** @@ -120,14 +120,14 @@ ald_status_t ald_timer_base_init(timer_handle_t *hperh) */ void ald_timer_base_reset(timer_handle_t *hperh) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - hperh->state = TIMER_STATE_BUSY; - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_RESET; - __UNLOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_RESET; + __UNLOCK(hperh); - return; + return; } /** @@ -137,13 +137,15 @@ void ald_timer_base_reset(timer_handle_t *hperh) */ void ald_timer_base_start(timer_handle_t *hperh) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - hperh->state = TIMER_STATE_BUSY; - TIMER_ENABLE(hperh); - hperh->state = TIMER_STATE_READY; + hperh->state = TIMER_STATE_BUSY; + SET_BIT(hperh->perh->SGE, TIMER_SGE_SGU_MSK); + SET_BIT(hperh->perh->ICR, TIMER_ICR_UEIC_MSK); + TIMER_ENABLE(hperh); + hperh->state = TIMER_STATE_READY; - return; + return; } /** @@ -153,13 +155,13 @@ void ald_timer_base_start(timer_handle_t *hperh) */ void ald_timer_base_stop(timer_handle_t *hperh) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - hperh->state = TIMER_STATE_BUSY; - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; + hperh->state = TIMER_STATE_BUSY; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; - return; + return; } /** @@ -169,12 +171,12 @@ void ald_timer_base_stop(timer_handle_t *hperh) */ void ald_timer_base_start_by_it(timer_handle_t *hperh) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE); - TIMER_ENABLE(hperh); + ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE); + TIMER_ENABLE(hperh); - return; + return; } /** @@ -184,64 +186,61 @@ void ald_timer_base_start_by_it(timer_handle_t *hperh) */ void ald_timer_base_stop_by_it(timer_handle_t *hperh) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE); - TIMER_DISABLE(hperh); + ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE); + TIMER_DISABLE(hperh); - return; + return; } #ifdef ALD_DMA /** * @brief Starts the TIMER Base generation in DMA mode. * @param hperh: TIMER handle - * @param hdma: Pointer to dma_handle_t. * @param buf: The source Buffer address. * @param len: The length of buffer to be transferred from memory to TIMER peripheral * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } - if ((hperh->state == TIMER_STATE_READY)) - { - if (((uint32_t)buf == 0) || (len == 0)) - return ERROR; - } + hperh->state = TIMER_STATE_BUSY; - hperh->state = TIMER_STATE_BUSY; + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; - if (hdma->perh == NULL) - hdma->perh = DMA0; + hperh->hdma1.cplt_cbk = timer_dma_period_elapse_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; - hdma->cplt_cbk = timer_dma_period_elapse_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.dst = (void *)&hperh->perh->AR; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_UPDATE; + hperh->hdma1.config.channel = dma_ch; - ald_dma_config_struct(&hdma->config); - hdma->config.src = (void *)buf; - hdma->config.dst = (void *)&hperh->perh->AR; - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_HALFWORD; - hdma->config.dst_inc = DMA_DATA_INC_NONE; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_UPDATE; - hdma->config.channel = dma_ch; + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE); + TIMER_ENABLE(hperh); - timer_dma_msel(hperh->perh, &hdma->config); - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE); - TIMER_ENABLE(hperh); - - return OK; + return OK; } /** @@ -251,13 +250,13 @@ ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hd */ void ald_timer_base_stop_by_dma(timer_handle_t *hperh) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE); - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; + ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE); + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; - return; + return; } #endif /** @@ -292,7 +291,7 @@ void ald_timer_base_stop_by_dma(timer_handle_t *hperh) */ ald_status_t ald_timer_oc_init(timer_handle_t *hperh) { - return ald_timer_base_init(hperh); + return ald_timer_base_init(hperh); } /** @@ -308,15 +307,15 @@ ald_status_t ald_timer_oc_init(timer_handle_t *hperh) */ void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - return; + TIMER_ENABLE(hperh); + return; } /** @@ -332,16 +331,16 @@ void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; } /** @@ -357,37 +356,36 @@ void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; - case TIMER_CHANNEL_4: - ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); - break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); + break; - default: - break; - } + default: + break; + } - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - return; + TIMER_ENABLE(hperh); + return; } /** @@ -403,38 +401,37 @@ void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; - case TIMER_CHANNEL_4: - ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); - break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); + break; - default: - break; - } + default: + break; + } - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; } @@ -451,92 +448,88 @@ void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The source Buffer address. * @param len: The length of buffer to be transferred from memory to TIMER peripheral * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) + uint16_t *buf, uint32_t len, uint8_t dma_ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - if ((hperh->state == TIMER_STATE_READY)) - { - if (((uint32_t)buf == 0) || (len == 0)) - return ERROR; - } + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } - hperh->state = TIMER_STATE_BUSY; + hperh->state = TIMER_STATE_BUSY; - if (hdma->perh == NULL) - hdma->perh = DMA0; + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; - hdma->cplt_cbk = timer_dma_oc_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; + hperh->hdma1.cplt_cbk = timer_dma_oc_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; - ald_dma_config_struct(&hdma->config); - hdma->config.src = (void *)buf; - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_HALFWORD; - hdma->config.dst_inc = DMA_DATA_INC_NONE; - hdma->config.channel = dma_ch; + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.channel = dma_ch; - timer_dma_msel(hperh->perh, &hdma->config); + timer_dma_msel(hperh->perh, &hperh->hdma1.config); - switch (ch) - { - case TIMER_CHANNEL_1: - hdma->config.dst = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; + switch (ch) { + case TIMER_CHANNEL_1: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; - case TIMER_CHANNEL_2: - hdma->config.dst = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; + case TIMER_CHANNEL_2: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; - case TIMER_CHANNEL_3: - hdma->config.dst = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; + case TIMER_CHANNEL_3: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; - case TIMER_CHANNEL_4: - hdma->config.dst = (void *)&hperh->perh->CCVAL4; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_4; - break; + case TIMER_CHANNEL_4: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL4; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + break; - default: - break; - } + default: + break; + } - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - return OK; + TIMER_ENABLE(hperh); + return OK; } /** @@ -552,38 +545,37 @@ ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch */ void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; - case TIMER_CHANNEL_2: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; - case TIMER_CHANNEL_3: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; - case TIMER_CHANNEL_4: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); - break; + case TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); + break; - default: - break; - } + default: + break; + } - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; } #endif /** @@ -618,7 +610,7 @@ void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) */ ald_status_t ald_timer_pwm_init(timer_handle_t *hperh) { - return ald_timer_base_init(hperh); + return ald_timer_base_init(hperh); } /** @@ -634,8 +626,8 @@ ald_status_t ald_timer_pwm_init(timer_handle_t *hperh) */ void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_oc_start(hperh, ch); - return; + ald_timer_oc_start(hperh, ch); + return; } /** @@ -651,8 +643,8 @@ void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_oc_stop(hperh, ch); - return; + ald_timer_oc_stop(hperh, ch); + return; } /** @@ -668,8 +660,8 @@ void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_oc_start_by_it(hperh, ch); - return; + ald_timer_oc_start_by_it(hperh, ch); + return; } /** @@ -685,8 +677,8 @@ void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_oc_stop_by_it(hperh, ch); - return; + ald_timer_oc_stop_by_it(hperh, ch); + return; } #ifdef ALD_DMA @@ -699,16 +691,15 @@ void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The source Buffer address. * @param len: The length of buffer to be transferred from memory to TIMER peripheral * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) + uint16_t *buf, uint32_t len, uint8_t dma_ch) { - return ald_timer_oc_start_by_dma(hperh, ch, hdma, buf, len, dma_ch); + return ald_timer_oc_start_by_dma(hperh, ch, buf, len, dma_ch); } /** @@ -724,8 +715,8 @@ ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t c */ void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_oc_stop_by_dma(hperh, ch); - return; + ald_timer_oc_stop_by_dma(hperh, ch); + return; } #endif /** @@ -736,10 +727,14 @@ void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) { - uint32_t _arr = ald_cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1; + uint32_t _arr; + + if (freq == 0) + return; - WRITE_REG(hperh->perh->AR, _arr); - hperh->init.period = _arr; + _arr = ald_cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1; + WRITE_REG(hperh->perh->AR, _arr); + hperh->init.period = _arr; } /** @@ -756,20 +751,19 @@ void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) */ void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty) { - uint32_t tmp = (hperh->init.period + 1) * duty / 100 - 1; + uint32_t tmp = (hperh->init.period + 1) * duty / 100 - 1; - if (ch == TIMER_CHANNEL_1) - WRITE_REG(hperh->perh->CCVAL1, tmp); - else if (ch == TIMER_CHANNEL_2) - WRITE_REG(hperh->perh->CCVAL2, tmp); - else if (ch == TIMER_CHANNEL_3) - WRITE_REG(hperh->perh->CCVAL3, tmp); - else if (ch == TIMER_CHANNEL_4) - WRITE_REG(hperh->perh->CCVAL4, tmp); - else - { - ;/* do nothing */ - } + if (ch == TIMER_CHANNEL_1) + WRITE_REG(hperh->perh->CCVAL1, tmp); + else if (ch == TIMER_CHANNEL_2) + WRITE_REG(hperh->perh->CCVAL2, tmp); + else if (ch == TIMER_CHANNEL_3) + WRITE_REG(hperh->perh->CCVAL3, tmp); + else if (ch == TIMER_CHANNEL_4) + WRITE_REG(hperh->perh->CCVAL4, tmp); + else { + ;/* do nothing */ + } } /** @@ -783,42 +777,38 @@ void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t */ void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch)); - - CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); - - switch (ch) - { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); - break; - - default: - break; - } - - SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); - SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2EN_MSK); - - return; + assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch)); + + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2EN_MSK); + + return; } /** * @} @@ -852,7 +842,7 @@ void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch) */ ald_status_t ald_timer_ic_init(timer_handle_t *hperh) { - return ald_timer_base_init(hperh); + return ald_timer_base_init(hperh); } /** @@ -868,11 +858,11 @@ ald_status_t ald_timer_ic_init(timer_handle_t *hperh) */ void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_ENABLE(hperh); - return; + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return; } /** @@ -888,11 +878,11 @@ void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_DISABLE(hperh); - return; + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + return; } /** @@ -908,33 +898,28 @@ void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); + break; + default: + break; + } - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; - - case TIMER_CHANNEL_4: - ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); - break; - - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_ENABLE(hperh); - return; + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return; } /** @@ -950,33 +935,28 @@ void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; - - case TIMER_CHANNEL_4: - ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); - break; - - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_DISABLE(hperh); - return; + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + return; } #ifdef ALD_DMA @@ -989,87 +969,83 @@ void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The destination Buffer address. * @param len: The length of buffer to be transferred TIMER peripheral to memory * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; - - if ((hperh->state == TIMER_STATE_READY)) - { - if (((uint32_t)buf == 0) || (len == 0)) - return ERROR; - } - - hperh->state = TIMER_STATE_BUSY; - - if (hdma->perh == NULL) - hdma->perh = DMA0; - - hdma->cplt_cbk = timer_dma_capture_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; - - ald_dma_config_struct(&hdma->config); - hdma->config.dst = (void *)buf; - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_NONE; - hdma->config.dst_inc = DMA_DATA_INC_HALFWORD; - hdma->config.channel = dma_ch; - - timer_dma_msel(hperh->perh, &hdma->config); - - switch (ch) - { - case TIMER_CHANNEL_1: - hdma->config.src = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; - - case TIMER_CHANNEL_2: - hdma->config.src = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; - - case TIMER_CHANNEL_3: - hdma->config.src = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; - - case TIMER_CHANNEL_4: - hdma->config.src = (void *)&hperh->perh->CCVAL4; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_4; - break; - - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_ENABLE(hperh); - return OK; + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } + + hperh->state = TIMER_STATE_BUSY; + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; + + hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.dst = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.channel = dma_ch; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + switch (ch) { + case TIMER_CHANNEL_1: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + case TIMER_CHANNEL_4: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL4; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return OK; } /** @@ -1085,34 +1061,29 @@ ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch */ void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - - case TIMER_CHANNEL_3: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; - - case TIMER_CHANNEL_4: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); - break; - - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + case TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; } #endif /** @@ -1151,23 +1122,23 @@ void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) */ ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode) { - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); - assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); - assert_param(IS_TIMER_OP_MODE(mode)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_OP_MODE(mode)); - if (hperh->state == TIMER_STATE_RESET) - hperh->lock = UNLOCK; + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; - hperh->state = TIMER_STATE_BUSY; - timer_base_set_config(hperh->perh, &hperh->init); - MODIFY_REG(hperh->perh->CON1, TIMER_CON1_SPMEN_MSK, mode << TIMER_CON1_SPMEN_POS); - hperh->state = TIMER_STATE_READY; + hperh->state = TIMER_STATE_BUSY; + timer_base_set_config(hperh->perh, &hperh->init); + MODIFY_REG(hperh->perh->CON1, TIMER_CON1_SPMEN_MSK, mode << TIMER_CON1_SPMEN_POS); + hperh->state = TIMER_STATE_READY; - return OK; + return OK; } /** @@ -1181,19 +1152,19 @@ ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mod */ void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch) { - /* Enable the Capture compare and the Input Capture channels - * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) - * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and - * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output - * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together - */ - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + /* Enable the Capture compare and the Input Capture channels + * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) + * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and + * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output + * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together + */ + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); - return; + return; } /** @@ -1207,14 +1178,14 @@ void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t */ void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch) { - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); - return; + TIMER_DISABLE(hperh); + return; } /** @@ -1228,21 +1199,21 @@ void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t c */ void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) { - /* Enable the Capture compare and the Input Capture channels - * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) - * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and - * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output - * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together - */ - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + /* Enable the Capture compare and the Input Capture channels + * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) + * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and + * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output + * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together + */ + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); - return; + return; } /** @@ -1256,16 +1227,16 @@ void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_chan */ void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) { - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); - return; + TIMER_DISABLE(hperh); + return; } /** * @} @@ -1299,41 +1270,41 @@ void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_chann */ ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config) { - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_ENCODER_MODE(config->mode)); - assert_param(IS_TIMER_IC_POLARITY(config->ic1_polarity)); - assert_param(IS_TIMER_IC_POLARITY(config->ic2_polarity)); - assert_param(IS_TIMER_IC_SELECT(config->ic1_sel)); - assert_param(IS_TIMER_IC_SELECT(config->ic2_sel)); - assert_param(IS_TIMER_IC_PSC(config->ic1_psc)); - assert_param(IS_TIMER_IC_PSC(config->ic2_psc)); - assert_param(IS_TIMER_IC_FILTER(config->ic1_filter)); - assert_param(IS_TIMER_IC_FILTER(config->ic2_filter)); + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_ENCODER_MODE(config->mode)); + assert_param(IS_TIMER_IC_POLARITY(config->ic1_polarity)); + assert_param(IS_TIMER_IC_POLARITY(config->ic2_polarity)); + assert_param(IS_TIMER_IC_SELECT(config->ic1_sel)); + assert_param(IS_TIMER_IC_SELECT(config->ic2_sel)); + assert_param(IS_TIMER_IC_PSC(config->ic1_psc)); + assert_param(IS_TIMER_IC_PSC(config->ic2_psc)); + assert_param(IS_TIMER_IC_FILTER(config->ic1_filter)); + assert_param(IS_TIMER_IC_FILTER(config->ic2_filter)); - if (hperh->state == TIMER_STATE_RESET) - hperh->lock = UNLOCK; + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; - hperh->state = TIMER_STATE_BUSY; - CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); - timer_base_set_config(hperh->perh, &hperh->init); + hperh->state = TIMER_STATE_BUSY; + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + timer_base_set_config(hperh->perh, &hperh->init); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, config->ic1_sel << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, config->ic2_sel << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->ic1_psc << TIMER_CHMR1_IC1PRES_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->ic2_psc << TIMER_CHMR1_IC2PRES_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->ic1_filter << TIMER_CHMR1_I1FLT_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I2FLT_MSK, config->ic2_filter << TIMER_CHMR1_I2FLT_POSS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, (config->ic1_polarity & 0x1) << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((config->ic1_polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, (config->ic2_polarity & 0x1) << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((config->ic2_polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, config->ic1_sel << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, config->ic2_sel << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->ic1_psc << TIMER_CHMR1_IC1PRES_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->ic2_psc << TIMER_CHMR1_IC2PRES_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->ic1_filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I2FLT_MSK, config->ic2_filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, (config->ic1_polarity & 0x1) << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((config->ic1_polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, (config->ic2_polarity & 0x1) << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((config->ic2_polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); - hperh->state = TIMER_STATE_READY; - return OK; + hperh->state = TIMER_STATE_READY; + return OK; } /** @@ -1348,26 +1319,23 @@ ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t */ void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - switch (ch) - { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - break; - - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - break; + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - break; - } + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + break; + } - TIMER_ENABLE(hperh); - return; + TIMER_ENABLE(hperh); + return; } /** @@ -1382,26 +1350,23 @@ void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - switch (ch) - { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + break; + } - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - break; - - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - break; - } - - TIMER_DISABLE(hperh); - return; + TIMER_DISABLE(hperh); + return; } /** @@ -1416,30 +1381,27 @@ void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - switch (ch) - { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; - - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - } + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + } - TIMER_ENABLE(hperh); - return; + TIMER_ENABLE(hperh); + return; } /** @@ -1454,31 +1416,28 @@ void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - switch (ch) - { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - } - - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + } + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; } #ifdef ALD_DMA @@ -1490,8 +1449,6 @@ void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected - * @param hdma1: Pointer to dma_handle_t. - * @param hdma2: Pointer to dma_handle_t. * @param buf1: The destination Buffer address. Reading data from CCR1. * @param buf2: The destination Buffer address. Reading data from CCR2. * @param len: The length of buffer to be transferred TIMER peripheral to memory @@ -1500,92 +1457,88 @@ void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @retval Status, see @ref ald_status_t. */ ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, - uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2) -{ - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; - - if ((hperh->state == TIMER_STATE_READY)) - { - if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0)) - return ERROR; - } - - if (hdma1->perh == NULL) - hdma1->perh = DMA0; - - if (hdma2->perh == NULL) - hdma2->perh = DMA0; - - hperh->state = TIMER_STATE_BUSY; - hdma1->cplt_cbk = timer_dma_capture_cplt; - hdma1->cplt_arg = (void *)hperh; - hdma1->err_cbk = timer_dma_error; - hdma1->err_arg = (void *)hperh; - - ald_dma_config_struct(&hdma1->config); - hdma1->config.size = len; - hdma1->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma1->config.src_inc = DMA_DATA_INC_NONE; - hdma1->config.dst_inc = DMA_DATA_INC_HALFWORD; - - timer_dma_msel(hperh->perh, &hdma1->config); - - switch (ch) - { - case TIMER_CHANNEL_1: - hdma1->config.src = (void *)&hperh->perh->CCVAL1; - hdma1->config.dst = (void *)buf1; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hdma1->config.channel = dma_ch1; - ald_dma_config_basic(hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - TIMER_ENABLE(hperh); - break; - - case TIMER_CHANNEL_2: - hdma1->config.src = (void *)&hperh->perh->CCVAL2; - hdma1->config.dst = (void *)buf2; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - hdma1->config.channel = dma_ch2; - ald_dma_config_basic(hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - TIMER_ENABLE(hperh); - break; - - default: - hdma2->cplt_cbk = timer_dma_capture_cplt; - hdma2->cplt_arg = (void *)hperh; - hdma2->err_cbk = timer_dma_error; - hdma2->err_arg = (void *)hperh; - memcpy(&hdma2->config, &hdma1->config, sizeof(dma_config_t)); - - hdma1->config.src = (void *)&hperh->perh->CCVAL1; - hdma1->config.dst = (void *)buf1; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hdma1->config.channel = dma_ch1; - ald_dma_config_basic(hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - - hdma2->config.src = (void *)&hperh->perh->CCVAL2; - hdma2->config.dst = (void *)buf2; - hdma2->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - hdma2->config.channel = dma_ch2; - ald_dma_config_basic(hdma2); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - TIMER_ENABLE(hperh); - break; - } - - return OK; + uint16_t *buf1, uint16_t *buf2, uint32_t len, + uint8_t dma_ch1, uint8_t dma_ch2) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0)) + return ERROR; + } + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; + if (hperh->hdma2.perh == NULL) + hperh->hdma2.perh = DMA0; + + hperh->state = TIMER_STATE_BUSY; + hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + switch (ch) { + case TIMER_CHANNEL_1: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + break; + + case TIMER_CHANNEL_2: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.dst = (void *)buf2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hperh->hdma1.config.channel = dma_ch2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + TIMER_ENABLE(hperh); + break; + + default: + hperh->hdma2.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma2.cplt_arg = (void *)hperh; + hperh->hdma2.err_cbk = timer_dma_error; + hperh->hdma2.err_arg = (void *)hperh; + memcpy(&hperh->hdma2.config, &hperh->hdma1.config, sizeof(dma_config_t)); + + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + + hperh->hdma2.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma2.config.dst = (void *)buf2; + hperh->hdma2.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hperh->hdma2.config.channel = dma_ch2; + ald_dma_config_basic(&hperh->hdma2); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + TIMER_ENABLE(hperh); + break; + } + + return OK; } /** @@ -1600,31 +1553,28 @@ ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel */ void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - switch (ch) - { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - } - - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + } + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; } #endif /** @@ -1659,38 +1609,38 @@ void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) */ ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config) { - timer_oc_init_t oc; + timer_oc_init_t oc; - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); - assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); - assert_param(IS_TIMER_IC_POLARITY(config->polarity)); - assert_param(IS_TIMER_IC_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); - if (hperh->state == TIMER_STATE_RESET) - hperh->lock = UNLOCK; + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; - hperh->state = TIMER_STATE_READY; - timer_base_set_config(hperh->perh, &hperh->init); - timer_ti1_set_config(hperh->perh, config->polarity, TIMER_IC_SEL_TRC, config->filter); + hperh->state = TIMER_STATE_READY; + timer_base_set_config(hperh->perh, &hperh->init); + timer_ti1_set_config(hperh->perh, config->polarity, TIMER_IC_SEL_TRC, config->filter); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); - SET_BIT(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + SET_BIT(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); - oc.oc_mode = TIMER_OC_MODE_PWM2; - oc.pulse = config->delay; - oc.oc_polarity = TIMER_OC_POLARITY_HIGH; - oc.ocn_polarity = TIMER_OCN_POLARITY_HIGH; - oc.oc_fast_en = DISABLE; - oc.oc_idle = TIMER_OC_IDLE_RESET; - oc.ocn_idle = TIMER_OCN_IDLE_RESET; - timer_oc2_set_config(hperh->perh, &oc); + oc.oc_mode = TIMER_OC_MODE_PWM2; + oc.pulse = config->delay; + oc.oc_polarity = TIMER_OC_POLARITY_HIGH; + oc.ocn_polarity = TIMER_OCN_POLARITY_HIGH; + oc.oc_fast_en = DISABLE; + oc.oc_idle = TIMER_OC_IDLE_RESET; + oc.ocn_idle = TIMER_OCN_IDLE_RESET; + timer_oc2_set_config(hperh->perh, &oc); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_TRGO_OC2REF << TIMER_SMCON_SMODS_POSS); - return OK; + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_TRGO_OC2REF << TIMER_SMCON_SMODS_POSS); + return OK; } /** * @brief Starts the TIMER hall sensor interface. @@ -1699,12 +1649,12 @@ ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_senso */ void ald_timer_hall_sensor_start(timer_handle_t *hperh) { - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - TIMER_ENABLE(hperh); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); - return; + return; } /** @@ -1714,12 +1664,12 @@ void ald_timer_hall_sensor_start(timer_handle_t *hperh) */ void ald_timer_hall_sensor_stop(timer_handle_t *hperh) { - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - TIMER_DISABLE(hperh); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + TIMER_DISABLE(hperh); - return; + return; } /** @@ -1729,13 +1679,13 @@ void ald_timer_hall_sensor_stop(timer_handle_t *hperh) */ void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh) { - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - TIMER_ENABLE(hperh); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); - return; + return; } /** @@ -1745,66 +1695,63 @@ void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh) */ void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh) { - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - TIMER_DISABLE(hperh); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + TIMER_DISABLE(hperh); - return; + return; } #ifdef ALD_DMA /** * @brief Starts the TIMER hall sensor interface in DMA mode. * @param hperh: TIMER handle - * @param hdma: Pointer to dma_handle_t. * @param buf: The destination Buffer address. Reading data from CCR1. * @param len: The length of buffer to be transferred TIMER peripheral to memory * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch) { - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - if ((hperh->state == TIMER_STATE_READY)) - { - if (((uint32_t)buf == 0) || (len == 0)) - return ERROR; - } + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0) || (len == 0)) + return ERROR; + } - if (hdma->perh == NULL) - hdma->perh = DMA0; + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; - hperh->state = TIMER_STATE_BUSY; - hdma->cplt_cbk = timer_dma_capture_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; + hperh->state = TIMER_STATE_BUSY; + hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; - ald_dma_config_struct(&hdma->config); - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_NONE; - hdma->config.dst_inc = DMA_DATA_INC_HALFWORD; + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; - timer_dma_msel(hperh->perh, &hdma->config); + timer_dma_msel(hperh->perh, &hperh->hdma1.config); - hdma->config.src = (void *)&hperh->perh->CCVAL1; - hdma->config.dst = (void *)buf; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hdma->config.channel = dma_ch; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - TIMER_ENABLE(hperh); + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); - return OK; + return OK; } /** * @brief Stops the TIMER hall sensor interface in DMA mode. @@ -1813,13 +1760,13 @@ ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handl */ void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) { - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - TIMER_DISABLE(hperh); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + TIMER_DISABLE(hperh); - return; + return; } #endif /** @@ -1858,13 +1805,13 @@ void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) */ void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); + timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); - return; + return; } /** @@ -1879,13 +1826,13 @@ void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); - return; + return; } /** @@ -1901,32 +1848,30 @@ void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + default: + break; + } - default: - break; - } + ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE); + timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); - ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE); - timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - - return; + return; } /** @@ -1942,38 +1887,35 @@ void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; - default: - break; - } + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + default: + break; + } - if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NEN_MSK))) - && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NEN_MSK))) - && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NEN_MSK)))) - { - ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE); - } + if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NEN_MSK))) + && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NEN_MSK))) + && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NEN_MSK)))) { + ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE); + } - timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); - return; + return; } #ifdef ALD_DMA @@ -1986,80 +1928,76 @@ void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The destination Buffer address. Reading data from CCRx. * @param len: The length of buffer to be transferred TIMER peripheral to memory * @param dma_ch: Channel of DMA. * @retval None */ -ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) { - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } - if ((hperh->state == TIMER_STATE_READY)) - { - if (((uint32_t)buf == 0) || (len == 0)) - return ERROR; - } + hperh->state = TIMER_STATE_BUSY; - hperh->state = TIMER_STATE_BUSY; + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; - if (hdma->perh == NULL) - hdma->perh = DMA0; + hperh->hdma1.cplt_cbk = timer_dma_oc_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; - hdma->cplt_cbk = timer_dma_oc_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.channel = dma_ch; + hperh->hdma1.config.msel = DMA_MSEL_TIMER0; - ald_dma_config_struct(&hdma->config); - hdma->config.src = (void *)buf; - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_HALFWORD; - hdma->config.dst_inc = DMA_DATA_INC_NONE; - hdma->config.channel = dma_ch; - hdma->config.msel = DMA_MSEL_TIMER0; + switch (ch) { + case TIMER_CHANNEL_1: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; - switch (ch) - { - case TIMER_CHANNEL_1: - hdma->config.dst = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; + case TIMER_CHANNEL_2: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; - case TIMER_CHANNEL_2: - hdma->config.dst = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; + case TIMER_CHANNEL_3: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; - case TIMER_CHANNEL_3: - hdma->config.dst = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - ald_dma_config_basic(hdma); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; + default: + break; + } - default: - break; - } + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - - return OK; + return OK; } /** @@ -2075,31 +2013,29 @@ ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdm */ void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - - switch (ch) - { - case TIMER_CHANNEL_1: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - case TIMER_CHANNEL_2: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; - case TIMER_CHANNEL_3: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; - default: - break; - } + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + default: + break; + } - timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); - return; + return; } #endif /** @@ -2138,7 +2074,7 @@ void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_start(hperh, ch); + ald_timer_ocn_start(hperh, ch); } /** @@ -2153,7 +2089,7 @@ void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_stop(hperh, ch); + ald_timer_ocn_stop(hperh, ch); } /** @@ -2169,7 +2105,7 @@ void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_start_by_it(hperh, ch); + ald_timer_ocn_start_by_it(hperh, ch); } /** @@ -2185,7 +2121,7 @@ void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_stop_by_it(hperh, ch); + ald_timer_ocn_stop_by_it(hperh, ch); } #ifdef ALD_DMA @@ -2198,16 +2134,15 @@ void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The destination Buffer address. Reading data from CCRx. * @param len: The length of buffer to be transferred TIMER peripheral to memory * @param dma_ch: Channel of DMA. * @retval None */ -ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) { - return ald_timer_ocn_start_by_dma(hperh, hdma, ch, buf, len, dma_ch); + return ald_timer_ocn_start_by_dma(hperh, ch, buf, len, dma_ch); } /** @@ -2223,7 +2158,7 @@ ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hd */ void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_stop_by_dma(hperh, ch); + ald_timer_ocn_stop_by_dma(hperh, ch); } #endif /** @@ -2259,7 +2194,7 @@ void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_start(hperh, ch); + ald_timer_ocn_start(hperh, ch); } /** @@ -2273,7 +2208,7 @@ void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_stop(hperh, ch); + ald_timer_ocn_stop(hperh, ch); } /** @@ -2288,7 +2223,7 @@ void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_start_by_it(hperh, ch); + ald_timer_ocn_start_by_it(hperh, ch); } /** @@ -2303,7 +2238,7 @@ void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch */ void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - ald_timer_ocn_stop_by_it(hperh, ch); + ald_timer_ocn_stop_by_it(hperh, ch); } /** * @} @@ -2345,40 +2280,39 @@ void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch) +ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch) { - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - assert_param(IS_TIMER_OC_MODE(config->oc_mode)); - assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_OC_MODE(config->oc_mode)); + assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; - switch (ch) - { - case TIMER_CHANNEL_1: - timer_oc1_set_config(hperh->perh, config); - break; + switch (ch) { + case TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, config); + break; - case TIMER_CHANNEL_2: - timer_oc2_set_config(hperh->perh, config); - break; + case TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, config); + break; - case TIMER_CHANNEL_3: - timer_oc3_set_config(hperh->perh, config); - break; + case TIMER_CHANNEL_3: + timer_oc3_set_config(hperh->perh, config); + break; - case TIMER_CHANNEL_4: - timer_oc4_set_config(hperh->perh, config); - break; + case TIMER_CHANNEL_4: + timer_oc4_set_config(hperh->perh, config); + break; - default: - break; - } + default: + break; + } - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -2394,46 +2328,45 @@ ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch) +ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_IC_POLARITY(config->polarity)); - assert_param(IS_TIMER_IC_SELECT(config->sel)); - assert_param(IS_TIMER_IC_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_SELECT(config->sel)); + assert_param(IS_TIMER_IC_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; - switch (ch) - { - case TIMER_CHANNEL_1: - timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); - break; + switch (ch) { + case TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + break; - case TIMER_CHANNEL_2: - timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS); - break; + case TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS); + break; - case TIMER_CHANNEL_3: - timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS); - break; + case TIMER_CHANNEL_3: + timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS); + break; - case TIMER_CHANNEL_4: - timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS); - break; + case TIMER_CHANNEL_4: + timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS); + break; - default: - break; - } + default: + break; + } - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -2452,70 +2385,65 @@ ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t * @retval Status, see @ref ald_status_t. */ ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, - timer_channel_t ch_out, timer_channel_t ch_in) -{ - timer_oc_init_t tmp; - - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_OC_MODE(config->mode)); - assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); - assert_param(IS_TIMER_OCN_POLARITY(config->ocn_polarity)); - assert_param(IS_TIMER_OCIDLE_STATE(config->oc_idle)); - assert_param(IS_TIMER_OCNIDLE_STATE(config->ocn_idle)); - assert_param(IS_TIMER_IC_POLARITY(config->polarity)); - assert_param(IS_TIMER_IC_SELECT(config->sel)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); - - if (ch_out == ch_in) - return ERROR; - - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; - - tmp.oc_mode = config->mode; - tmp.pulse = config->pulse; - tmp.oc_polarity = config->oc_polarity; - tmp.ocn_polarity = config->ocn_polarity; - tmp.oc_idle = config->oc_idle; - tmp.ocn_idle = config->ocn_idle; - - switch (ch_out) - { - case TIMER_CHANNEL_1: - timer_oc1_set_config(hperh->perh, &tmp); - break; - - case TIMER_CHANNEL_2: - timer_oc2_set_config(hperh->perh, &tmp); - break; - - default: - break; - } - - switch (ch_in) - { - case TIMER_CHANNEL_1: - timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); - CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_CHANNEL_2: - timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); - CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); - break; - - default: - break; - } - - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; + timer_channel_t ch_out, timer_channel_t ch_in) +{ + timer_oc_init_t tmp; + + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_OC_MODE(config->mode)); + assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); + assert_param(IS_TIMER_OCN_POLARITY(config->ocn_polarity)); + assert_param(IS_TIMER_OCIDLE_STATE(config->oc_idle)); + assert_param(IS_TIMER_OCNIDLE_STATE(config->ocn_idle)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_SELECT(config->sel)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (ch_out == ch_in) + return ERROR; + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + tmp.oc_mode = config->mode; + tmp.pulse = config->pulse; + tmp.oc_polarity = config->oc_polarity; + tmp.ocn_polarity = config->ocn_polarity; + tmp.oc_idle = config->oc_idle; + tmp.ocn_idle = config->ocn_idle; + + switch (ch_out) { + case TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, &tmp); + break; + case TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, &tmp); + break; + default: + break; + } + + switch (ch_in) { + case TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -2533,48 +2461,45 @@ ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one */ ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_FUNC_STATE(config->state)); - assert_param(IS_TIMER_CLEAR_INPUT_SOURCE(config->source)); - assert_param(IS_TIMER_CLEAR_INPUT_POLARITY(config->polarity)); - assert_param(IS_TIMER_ETR_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->state)); + assert_param(IS_TIMER_CLEAR_INPUT_SOURCE(config->source)); + assert_param(IS_TIMER_CLEAR_INPUT_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); - if (config->source == TIMER_INPUT_NONE) - { - timer_etr_set_config(hperh->perh, TIMER_ETR_PSC_DIV1, TIMER_CLK_POLARITY_NO_INV, 0); - } - else - { - timer_etr_set_config(hperh->perh, config->psc, - (timer_clock_polarity_t)config->polarity, config->filter); - } + if (config->source == TIMER_INPUT_NONE) { + timer_etr_set_config(hperh->perh, TIMER_ETR_PSC_DIV1, TIMER_CLK_POLARITY_NO_INV, 0); + } + else { + timer_etr_set_config(hperh->perh, config->psc, + (timer_clock_polarity_t)config->polarity, config->filter); + } - switch (ch) - { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS); - break; + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS); + break; - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS); - break; + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS); + break; - case TIMER_CHANNEL_3: - assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS); - break; + case TIMER_CHANNEL_3: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS); + break; - case TIMER_CHANNEL_4: - assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS); - break; + case TIMER_CHANNEL_4: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS); + break; - default: - break; - } + default: + break; + } - return OK; + return OK; } /** @@ -2586,78 +2511,76 @@ ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_in */ ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_CLOCK_SOURCE(config->source)); - assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); - assert_param(IS_TIMER_ETR_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); - - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; - WRITE_REG(hperh->perh->SMCON, 0x0); - - switch (config->source) - { - case TIMER_SRC_INTER: - CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); - break; - - case TIMER_SRC_ETRMODE1: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ETRMODE2: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK); - break; - - case TIMER_SRC_TI1: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_TI2: - timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_TI1ED: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR0: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR1: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR2: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR3: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - default: - break; - } - - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_CLOCK_SOURCE(config->source)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + WRITE_REG(hperh->perh->SMCON, 0x0); + + switch (config->source) { + case TIMER_SRC_INTER: + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + break; + + case TIMER_SRC_ETRMODE1: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ETRMODE2: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK); + break; + + case TIMER_SRC_TI1: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_TI2: + timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_TI1ED: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR0: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR1: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR2: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR3: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -2674,10 +2597,10 @@ ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_co */ ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); - MODIFY_REG(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK, ti1_select << TIMER_CON2_I1FSEL_POS); - return OK; + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK, ti1_select << TIMER_CON2_I1FSEL_POS); + return OK; } /** @@ -2691,23 +2614,23 @@ ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_sele */ ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_SLAVE_MODE(config->mode)); - assert_param(IS_TIMER_TS(config->input)); - assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); - assert_param(IS_TIMER_ETR_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_SLAVE_MODE(config->mode)); + assert_param(IS_TIMER_TS(config->input)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; - timer_slave_set_config(hperh, config); - ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); + timer_slave_set_config(hperh, config); + ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -2721,23 +2644,23 @@ ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_conf */ ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_SLAVE_MODE(config->mode)); - assert_param(IS_TIMER_TS(config->input)); - assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); - assert_param(IS_TIMER_ETR_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_SLAVE_MODE(config->mode)); + assert_param(IS_TIMER_TS(config->input)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; - timer_slave_set_config(hperh, config); - ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); + timer_slave_set_config(hperh, config); + ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; } /** @@ -2748,16 +2671,16 @@ ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slav */ ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_EVENT_SOURCE(event)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_EVENT_SOURCE(event)); - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; - WRITE_REG(hperh->perh->SGE, event); - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + WRITE_REG(hperh->perh->SGE, event); + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -2773,36 +2696,32 @@ ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_ */ uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) { - uint32_t tmp; + uint32_t tmp; - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; - switch (ch) - { - case TIMER_CHANNEL_1: - tmp = hperh->perh->CCVAL1; - break; + switch (ch) { + case TIMER_CHANNEL_1: + tmp = hperh->perh->CCVAL1; + break; + case TIMER_CHANNEL_2: + tmp = hperh->perh->CCVAL2; + break; + case TIMER_CHANNEL_3: + tmp = hperh->perh->CCVAL3; + break; + case TIMER_CHANNEL_4: + tmp = hperh->perh->CCVAL4; + break; + default: + tmp = hperh->perh->CCVAL1; + break; + } - case TIMER_CHANNEL_2: - tmp = hperh->perh->CCVAL2; - break; - - case TIMER_CHANNEL_3: - tmp = hperh->perh->CCVAL3; - break; - - case TIMER_CHANNEL_4: - tmp = hperh->perh->CCVAL4; - break; - - default: - break; - } - - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return tmp; + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return tmp; } /** @@ -2819,33 +2738,28 @@ uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch) { - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_OC_MODE(mode)); - assert_param(IS_TIMER_CHANNELS(ch)); - - switch (ch) - { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS); - break; + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_OC_MODE(mode)); + assert_param(IS_TIMER_CHANNELS(ch)); - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS); - break; + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS); + break; + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS); + break; + case TIMER_CHANNEL_3: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS); + break; + case TIMER_CHANNEL_4: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS); + break; + default: + break; + } - case TIMER_CHANNEL_3: - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS); - break; - - case TIMER_CHANNEL_4: - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS); - break; - - default: - break; - } - - return; + return; } /** @@ -2853,46 +2767,46 @@ void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, time * @param hperh: TIMER handel * @param config: Parameters of the channel. * @retval None - */ + */ void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config) { - uint32_t cm1, cm2, cce; + uint32_t cm1, cm2, cce; - assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); - assert_param(IS_FUNC_STATE(config->ch[0].en)); - assert_param(IS_FUNC_STATE(config->ch[0].n_en)); - assert_param(IS_TIMER_OC_MODE(config->ch[0].mode)); - assert_param(IS_FUNC_STATE(config->ch[1].en)); - assert_param(IS_FUNC_STATE(config->ch[1].n_en)); - assert_param(IS_TIMER_OC_MODE(config->ch[1].mode)); - assert_param(IS_FUNC_STATE(config->ch[2].en)); - assert_param(IS_FUNC_STATE(config->ch[2].n_en)); - assert_param(IS_TIMER_OC_MODE(config->ch[2].mode)); + assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->ch[0].en)); + assert_param(IS_FUNC_STATE(config->ch[0].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[0].mode)); + assert_param(IS_FUNC_STATE(config->ch[1].en)); + assert_param(IS_FUNC_STATE(config->ch[1].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[1].mode)); + assert_param(IS_FUNC_STATE(config->ch[2].en)); + assert_param(IS_FUNC_STATE(config->ch[2].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[2].mode)); - TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); - cm1 = hperh->perh->CHMR1; - cm2 = hperh->perh->CHMR2; - cce = hperh->perh->CCEP; + cm1 = hperh->perh->CHMR1; + cm2 = hperh->perh->CHMR2; + cce = hperh->perh->CCEP; - MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4)); - MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12)); - MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4)); - MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0)); - MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2)); - MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4)); - MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6)); - MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8)); - MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10)); + MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4)); + MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12)); + MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4)); + MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0)); + MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2)); + MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4)); + MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6)); + MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8)); + MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10)); - WRITE_REG(hperh->perh->CHMR1, cm1); - WRITE_REG(hperh->perh->CHMR2, cm2); - WRITE_REG(hperh->perh->CCEP, cce); + WRITE_REG(hperh->perh->CHMR1, cm1); + WRITE_REG(hperh->perh->CHMR2, cm2); + WRITE_REG(hperh->perh->CCEP, cce); - TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - return; + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); + return; } /** @@ -2910,18 +2824,18 @@ void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config * @arg ENABLE: Commutation event source is TRGI * @arg DISABLE: Commutation event source is set by software using the COMG bit * @retval None - */ + */ void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) { - assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_TS(ts)); - assert_param(IS_FUNC_STATE(trgi)); + assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_TS(ts)); + assert_param(IS_FUNC_STATE(trgi)); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ts << TIMER_SMCON_TSSEL_POSS); - SET_BIT(hperh->perh->CON2, TIMER_CON2_CCPCEN_MSK); - MODIFY_REG(hperh->perh->CON2, TIMER_CON2_CCUSEL_MSK, trgi << TIMER_CON2_CCUSEL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ts << TIMER_SMCON_TSSEL_POSS); + SET_BIT(hperh->perh->CON2, TIMER_CON2_CCPCEN_MSK); + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_CCUSEL_MSK, trgi << TIMER_CON2_CCUSEL_POS); - return; + return; } /** @@ -2942,8 +2856,8 @@ void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_ */ void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) { - ald_timer_com_event_config(hperh, ts, trgi); - ald_timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE); + ald_timer_com_event_config(hperh, ts, trgi); + ald_timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE); } /** @@ -2951,32 +2865,32 @@ void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_fu * @param hperh: TIMER handle * @param config: Pointer to the timer_break_dead_timere_t structure. * @retval None - */ + */ void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config) { - uint32_t tmp; + uint32_t tmp; - assert_param(IS_TIMER_BREAK_INSTANCE(hperh->perh)); - assert_param(IS_FUNC_STATE(config->off_run)); - assert_param(IS_FUNC_STATE(config->off_idle)); - assert_param(IS_TIMER_CLOCK_LEVEL(config->lock_level)); - assert_param(IS_TIMER_DEAD_TIMERE(config->dead_time)); - assert_param(IS_FUNC_STATE(config->break_state)); - assert_param(IS_TIMER_BREAK_POLARITY(config->polarity)); - assert_param(IS_FUNC_STATE(config->auto_out)); + assert_param(IS_TIMER_BREAK_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->off_run)); + assert_param(IS_FUNC_STATE(config->off_idle)); + assert_param(IS_TIMER_CLOCK_LEVEL(config->lock_level)); + assert_param(IS_TIMER_DEAD_TIMERE(config->dead_time)); + assert_param(IS_FUNC_STATE(config->break_state)); + assert_param(IS_TIMER_BREAK_POLARITY(config->polarity)); + assert_param(IS_FUNC_STATE(config->auto_out)); - tmp = READ_REG(hperh->perh->BDCFG); - MODIFY_REG(tmp, TIMER_BDCFG_OFFSSR_MSK, config->off_run << TIMER_BDCFG_OFFSSR_POS); - MODIFY_REG(tmp, TIMER_BDCFG_OFFSSI_MSK, config->off_idle << TIMER_BDCFG_OFFSSI_POS); - MODIFY_REG(tmp, TIMER_BDCFG_LOCKLVL_MSK, config->lock_level << TIMER_BDCFG_LOCKLVL_POSS); - MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS); - MODIFY_REG(tmp, TIMER_BDCFG_BRKEN_MSK, config->break_state << TIMER_BDCFG_BRKEN_POS); - MODIFY_REG(tmp, TIMER_BDCFG_BRKP_MSK, config->polarity << TIMER_BDCFG_BRKP_POS); - MODIFY_REG(tmp, TIMER_BDCFG_AOEN_MSK, config->auto_out << TIMER_BDCFG_AOEN_POS); - WRITE_REG(hperh->perh->BDCFG, tmp); + tmp = READ_REG(hperh->perh->BDCFG); + MODIFY_REG(tmp, TIMER_BDCFG_OFFSSR_MSK, config->off_run << TIMER_BDCFG_OFFSSR_POS); + MODIFY_REG(tmp, TIMER_BDCFG_OFFSSI_MSK, config->off_idle << TIMER_BDCFG_OFFSSI_POS); + MODIFY_REG(tmp, TIMER_BDCFG_LOCKLVL_MSK, config->lock_level << TIMER_BDCFG_LOCKLVL_POSS); + MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS); + MODIFY_REG(tmp, TIMER_BDCFG_BRKEN_MSK, config->break_state << TIMER_BDCFG_BRKEN_POS); + MODIFY_REG(tmp, TIMER_BDCFG_BRKP_MSK, config->polarity << TIMER_BDCFG_BRKP_POS); + MODIFY_REG(tmp, TIMER_BDCFG_AOEN_MSK, config->auto_out << TIMER_BDCFG_AOEN_POS); + WRITE_REG(hperh->perh->BDCFG, tmp); - hperh->state = TIMER_STATE_READY; - return; + hperh->state = TIMER_STATE_READY; + return; } /** @@ -2984,19 +2898,19 @@ void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_ti * @param hperh: TIMER handle * @param config: Pointer to the timer_master_config_t structure. * @retval None - */ + */ void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel)); - assert_param(IS_FUNC_STATE(config->master_en)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel)); + assert_param(IS_FUNC_STATE(config->master_en)); - hperh->state = TIMER_STATE_BUSY; - MODIFY_REG(hperh->perh->CON2, TIMER_CON2_TRGOSEL_MSK, config->sel << TIMER_CON2_TRGOSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_MSCFG_MSK, config->master_en << TIMER_SMCON_MSCFG_POS); - hperh->state = TIMER_STATE_READY; + hperh->state = TIMER_STATE_BUSY; + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_TRGOSEL_MSK, config->sel << TIMER_CON2_TRGOSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_MSCFG_MSK, config->master_en << TIMER_SMCON_MSCFG_POS); + hperh->state = TIMER_STATE_READY; - return; + return; } /** @@ -3006,141 +2920,118 @@ void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t * */ void ald_timer_irq_handler(timer_handle_t *hperh) { - uint32_t reg = hperh->perh->IFM; - - /* Capture or compare 1 event */ - if (READ_BIT(reg, TIMER_FLAG_CC1)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC1); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK)) - { - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); - } - else /* Output compare event */ - { - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); - - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); - } - - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - } - - /* Capture or compare 2 event */ - if (READ_BIT(reg, TIMER_FLAG_CC2)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC2); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - - /* Input capture event */ - if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK)) - { - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); - } - else /* Output compare event */ - { - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); - - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); - } - - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - } - - /* Capture or compare 3 event */ - if (READ_BIT(reg, TIMER_FLAG_CC3)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC3); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - - /* Input capture event */ - if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC3SSEL_MSK)) - { - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); - } - else /* Output compare event */ - { - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); - - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); - } - - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - } - - /* Capture or compare 4 event */ - if (READ_BIT(reg, TIMER_FLAG_CC4)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC4); - hperh->ch = TIMER_ACTIVE_CHANNEL_4; - - /* Input capture event */ - if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC4SSEL_MSK)) - { - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); - } - else /* Output compare event */ - { - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); - - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); - } - - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - } - - /* TIMER Update event */ - if (READ_BIT(reg, TIMER_FLAG_UPDATE)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE); - - if (hperh->period_elapse_cbk) - hperh->period_elapse_cbk(hperh); - } - - /* TIMER Break input event */ - if (READ_BIT(reg, TIMER_FLAG_BREAK)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_BREAK); - - if (hperh->break_cbk) - hperh->break_cbk(hperh); - } - - /* TIMER Trigger detection event */ - if (READ_BIT(reg, TIMER_FLAG_TRIGGER)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER); - - if (hperh->trigger_cbk) - hperh->trigger_cbk(hperh); - } - - /* TIMER commutation event */ - if (READ_BIT(reg, TIMER_FLAG_COM)) - { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_COM); - - if (hperh->com_cbk) - hperh->com_cbk(hperh); - } - - return; + uint32_t reg = hperh->perh->IFM; + + /* Capture or compare 1 event */ + if (READ_BIT(reg, TIMER_FLAG_CC1)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC1); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 2 event */ + if (READ_BIT(reg, TIMER_FLAG_CC2)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC2); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 3 event */ + if (READ_BIT(reg, TIMER_FLAG_CC3)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC3); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC3SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 4 event */ + if (READ_BIT(reg, TIMER_FLAG_CC4)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC4); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC4SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + + /* TIMER Update event */ + if (READ_BIT(reg, TIMER_FLAG_UPDATE)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE); + + if (hperh->period_elapse_cbk) + hperh->period_elapse_cbk(hperh); + } + + /* TIMER Break input event */ + if (READ_BIT(reg, TIMER_FLAG_BREAK)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_BREAK); + + if (hperh->break_cbk) + hperh->break_cbk(hperh); + } + + /* TIMER Trigger detection event */ + if (READ_BIT(reg, TIMER_FLAG_TRIGGER)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER); + + if (hperh->trigger_cbk) + hperh->trigger_cbk(hperh); + } + + /* TIMER commutation event */ + if (READ_BIT(reg, TIMER_FLAG_COM)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_COM); + + if (hperh->com_cbk) + hperh->com_cbk(hperh); + } + + return; } /** @@ -3152,16 +3043,16 @@ void ald_timer_irq_handler(timer_handle_t *hperh) */ void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_DMA_REQ(req)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - SET_BIT(hperh->perh->DIER, req); - else - CLEAR_BIT(hperh->perh->DIER, req); + if (state == ENABLE) + SET_BIT(hperh->perh->DIER, req); + else + SET_BIT(hperh->perh->DIDR, req); - return; + return; } /** @@ -3177,16 +3068,16 @@ void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_f */ void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_IT(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IT(it)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - SET_BIT(hperh->perh->DIER, it); - else - CLEAR_BIT(hperh->perh->DIER, it); + if (state == ENABLE) + SET_BIT(hperh->perh->DIER, it); + else + SET_BIT(hperh->perh->DIDR, it); - return; + return; } /** @@ -3200,13 +3091,13 @@ void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_ */ it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_IT(it)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IT(it)); - if (hperh->perh->DIVS & it) - return SET; + if (hperh->perh->DIVS & it) + return SET; - return RESET; + return RESET; } /** @@ -3220,13 +3111,13 @@ it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it) */ flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_FLAG(flag)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_FLAG(flag)); - if (hperh->perh->RIF & flag) - return SET; + if (hperh->perh->RIF & flag) + return SET; - return RESET; + return RESET; } /** @@ -3238,11 +3129,11 @@ flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag */ void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag) { - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_FLAG(flag)); + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_FLAG(flag)); - hperh->perh->ICR = flag; - return; + hperh->perh->ICR = flag; + return; } /** * @} @@ -3270,7 +3161,7 @@ void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag) */ timer_state_t ald_timer_get_state(timer_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** * @} @@ -3291,16 +3182,16 @@ timer_state_t ald_timer_get_state(timer_handle_t *hperh) */ void timer_dma_oc_cplt(void *arg) { - timer_handle_t *hperh = (timer_handle_t *)arg; + timer_handle_t *hperh = (timer_handle_t *)arg; - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - return; + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + return; } /** @@ -3310,13 +3201,13 @@ void timer_dma_oc_cplt(void *arg) */ void timer_dma_capture_cplt(void *arg) { - timer_handle_t *hperh = (timer_handle_t *)arg; + timer_handle_t *hperh = (timer_handle_t *)arg; - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - return; + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + return; } /** @@ -3326,13 +3217,13 @@ void timer_dma_capture_cplt(void *arg) */ void timer_dma_period_elapse_cplt(void *arg) { - timer_handle_t *hperh = (timer_handle_t *)arg; + timer_handle_t *hperh = (timer_handle_t *)arg; - if (hperh->period_elapse_cbk) - hperh->period_elapse_cbk(hperh); + if (hperh->period_elapse_cbk) + hperh->period_elapse_cbk(hperh); - hperh->state = TIMER_STATE_READY; - return; + hperh->state = TIMER_STATE_READY; + return; } /** @@ -3342,14 +3233,13 @@ void timer_dma_period_elapse_cplt(void *arg) */ void timer_dma_error(void *arg) { - timer_handle_t *hperh = (timer_handle_t *)arg; + timer_handle_t *hperh = (timer_handle_t *)arg; - hperh->state = TIMER_STATE_READY; + hperh->state = TIMER_STATE_READY; + if (hperh->error_cbk) + hperh->error_cbk(hperh); - if (hperh->error_cbk) - hperh->error_cbk(hperh); - - return; + return; } #endif @@ -3361,29 +3251,27 @@ void timer_dma_error(void *arg) */ static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init) { - assert_param(IS_TIMER_COUNTER_MODE(init->mode)); - assert_param(IS_TIMER_CLOCK_DIVISION(init->clk_div)); + assert_param(IS_TIMER_COUNTER_MODE(init->mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(init->clk_div)); - if (init->mode == TIMER_CNT_MODE_UP || init->mode == TIMER_CNT_MODE_DOWN) - { - CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CMSEL_MSK); - MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, init->mode << TIMER_CON1_DIRSEL_POS); - } - else - { - MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, (init->mode - 1) << TIMER_CON1_CMSEL_POSS); - } + if (init->mode == TIMER_CNT_MODE_UP || init->mode == TIMER_CNT_MODE_DOWN) { + CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CMSEL_MSK); + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, init->mode << TIMER_CON1_DIRSEL_POS); + } + else { + MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, (init->mode - 1) << TIMER_CON1_CMSEL_POSS); + } - if (IS_TIMER_CLOCK_DIVISION_INSTANCE(TIMERx)) - MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, init->clk_div << TIMER_CON1_DFCKSEL_POSS); + if (IS_TIMER_CLOCK_DIVISION_INSTANCE(TIMERx)) + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, init->clk_div << TIMER_CON1_DFCKSEL_POSS); - WRITE_REG(TIMERx->AR, init->period); - WRITE_REG(TIMERx->PRES, init->prescaler); + WRITE_REG(TIMERx->AR, init->period); + WRITE_REG(TIMERx->PRES, init->prescaler); - if (IS_TIMER_REPETITION_COUNTER_INSTANCE(TIMERx)) - WRITE_REG(TIMERx->REPAR, init->re_cnt); + if (IS_TIMER_REPETITION_COUNTER_INSTANCE(TIMERx)) + WRITE_REG(TIMERx->REPAR, init->re_cnt); - return; + return; } /** @@ -3394,29 +3282,27 @@ static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init */ static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); - CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK); - CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH1OMOD_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC1POL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH1OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC1POL_POS); - if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_1)) - { - assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC1NPOL_POS); - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK); - } + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_1)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC1NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK); + } - if (IS_TIMER_BREAK_INSTANCE(TIMERx)) - { - assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); - assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1_MSK, oc_config->oc_idle << TIMER_CON2_OISS1_POS); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS1N_POS); - } + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1_MSK, oc_config->oc_idle << TIMER_CON2_OISS1_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS1N_POS); + } - WRITE_REG(TIMERx->CCVAL1, oc_config->pulse); + WRITE_REG(TIMERx->CCVAL1, oc_config->pulse); } /** @@ -3427,29 +3313,27 @@ static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_conf */ static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); - CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK); - CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH2OMOD_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC2POL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH2OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC2POL_POS); - if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_2)) - { - assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC2NPOL_POS); - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK); - } + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_2)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC2NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK); + } - if (IS_TIMER_BREAK_INSTANCE(TIMERx)) - { - assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); - assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2_MSK, oc_config->oc_idle << TIMER_CON2_OISS2_POS); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS2N_POS); - } + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2_MSK, oc_config->oc_idle << TIMER_CON2_OISS2_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS2N_POS); + } - WRITE_REG(TIMERx->CCVAL2, oc_config->pulse); + WRITE_REG(TIMERx->CCVAL2, oc_config->pulse); } /** @@ -3460,29 +3344,27 @@ static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_conf */ static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); - CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK); - CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH3OMOD_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC3POL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH3OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC3POL_POS); - if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_3)) - { - assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC3NPOL_POS); - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK); - } + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_3)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC3NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK); + } - if (IS_TIMER_BREAK_INSTANCE(TIMERx)) - { - assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); - assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3_MSK, oc_config->oc_idle << TIMER_CON2_OISS3_POS); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS3N_POS); - } + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3_MSK, oc_config->oc_idle << TIMER_CON2_OISS3_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS3N_POS); + } - WRITE_REG(TIMERx->CCVAL3, oc_config->pulse); + WRITE_REG(TIMERx->CCVAL3, oc_config->pulse); } /** @@ -3493,19 +3375,18 @@ static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_conf */ static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); - CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK); - CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH4OMOD_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC4POL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH4OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC4POL_POS); - if (IS_TIMER_BREAK_INSTANCE(TIMERx)) - { - assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS4_MSK, oc_config->oc_idle << TIMER_CON2_OISS4_POS); - } + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS4_MSK, oc_config->oc_idle << TIMER_CON2_OISS4_POS); + } - WRITE_REG(TIMERx->CCVAL4, oc_config->pulse); + WRITE_REG(TIMERx->CCVAL4, oc_config->pulse); } /** @@ -3520,32 +3401,31 @@ static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_conf * @param state: specifies the TIMER Channel CCxE bit new state. * @retval None */ -static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state) +static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state) { - assert_param(IS_TIMER_CC2_INSTANCE(TIMERx)); - assert_param(IS_TIMER_CHANNELS(ch)); + assert_param(IS_TIMER_CC2_INSTANCE(TIMERx)); + assert_param(IS_TIMER_CHANNELS(ch)); - switch (ch) - { - case TIMER_CHANNEL_1: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS); - break; + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS); + break; - case TIMER_CHANNEL_2: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS); - break; + case TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS); + break; - case TIMER_CHANNEL_3: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS); - break; + case TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS); + break; - case TIMER_CHANNEL_4: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS); - break; + case TIMER_CHANNEL_4: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS); + break; - default: - break; - } + default: + break; + } } /** * @brief Enables or disables the TIMER Capture Compare Channel xN. @@ -3558,25 +3438,24 @@ static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, typ * @param state: specifies the TIMER Channel CCxNE bit new state. * @retval None */ -static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state) +static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state) { - switch (ch) - { - case TIMER_CHANNEL_1: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS); - break; + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS); + break; - case TIMER_CHANNEL_2: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS); - break; + case TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS); + break; - case TIMER_CHANNEL_3: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS); - break; + case TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS); + break; - default: - break; - } + default: + break; + } } @@ -3590,14 +3469,14 @@ static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, ty * @retval None */ static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter) + timer_ic_select_t sel, uint32_t filter) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); - return; + return; } /** @@ -3610,11 +3489,11 @@ static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola */ static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) { - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); - return; + return; } /** @@ -3627,15 +3506,15 @@ static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_ * @retval None */ static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter) + timer_ic_select_t sel, uint32_t filter) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); - return; + return; } /** @@ -3648,9 +3527,9 @@ static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola */ static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) { - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); - return; + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); + return; } /** @@ -3663,14 +3542,14 @@ static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_ * @retval None */ static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter) + timer_ic_select_t sel, uint32_t filter) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, polarity << TIMER_CCEP_CC3POL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, polarity << TIMER_CCEP_CC3POL_POS); - return; + return; } /** @@ -3683,13 +3562,13 @@ static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola * @retval None */ static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter) + timer_ic_select_t sel, uint32_t filter) { - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, polarity << TIMER_CCEP_CC4POL_POS); - return; + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, polarity << TIMER_CCEP_CC4POL_POS); + return; } /** @@ -3701,13 +3580,13 @@ static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola * This parameter must be a value between 0x00 and 0x0F * @retval None */ -static void timer_etr_set_config(TIMER_TypeDef *TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter) +static void timer_etr_set_config(TIMER_TypeDef* TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter) { - MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETFLT_MSK, filter << TIMER_SMCON_ETFLT_POSS); - MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, psc << TIMER_SMCON_ETPSEL_POSS); - CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK); - MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, polarity << TIMER_SMCON_ETPOL_POS); - return; + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETFLT_MSK, filter << TIMER_SMCON_ETFLT_POSS); + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, psc << TIMER_SMCON_ETPSEL_POSS); + CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK); + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, polarity << TIMER_SMCON_ETPOL_POS); + return; } /** @@ -3719,31 +3598,30 @@ static void timer_etr_set_config(TIMER_TypeDef *TIMERx, timer_etr_psc_t psc, tim */ static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config) { - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, config->input << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, config->input << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); - switch (config->input) - { - case TIMER_TS_ETRF: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - break; + switch (config->input) { + case TIMER_TS_ETRF: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + break; - case TIMER_TS_TI1F_ED: - CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS); - break; + case TIMER_TS_TI1F_ED: + CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS); + break; - case TIMER_TS_TI1FP1: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - break; + case TIMER_TS_TI1FP1: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + break; - case TIMER_TS_TI2FP2: - timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - break; + case TIMER_TS_TI2FP2: + timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + break; - default: - break; - } + default: + break; + } } #ifdef ALD_DMA @@ -3757,41 +3635,30 @@ static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t * */ static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config) { -#if defined (ES32F065x) - - if (hperh == AD16C4T0) - config->msel = DMA_MSEL_TIMER0; - - if (hperh == GP16C4T0) - config->msel = DMA_MSEL_TIMER6; - -#elif defined (ES32F033x) || defined (ES32F093x) - - if (hperh == GP16C4T0) - config->msel = DMA_MSEL_TIMER0; - - if (hperh == GP16C4T1) - config->msel = DMA_MSEL_TIMER6; - -#endif - - if (hperh == GP16C2T0) - config->msel = DMA_MSEL_TIMER2; - - if (hperh == GP16C2T1) - config->msel = DMA_MSEL_TIMER3; - - if (hperh == BS16T0) - config->msel = DMA_MSEL_TIMER1; - - if (hperh == BS16T1) - config->msel = DMA_MSEL_TIMER4; - - if (hperh == BS16T2) - config->msel = DMA_MSEL_TIMER5; - - if (hperh == BS16T3) - config->msel = DMA_MSEL_TIMER7; + #if defined (ES32F065x) + if (hperh == AD16C4T0) + config->msel = DMA_MSEL_TIMER0; + if (hperh == GP16C4T0) + config->msel = DMA_MSEL_TIMER6; + #elif defined (ES32F033x) || defined (ES32F093x) + if (hperh == GP16C4T0) + config->msel = DMA_MSEL_TIMER0; + if (hperh == GP16C4T1) + config->msel = DMA_MSEL_TIMER6; + #endif + + if (hperh == GP16C2T0) + config->msel = DMA_MSEL_TIMER2; + if (hperh == GP16C2T1) + config->msel = DMA_MSEL_TIMER3; + if (hperh == BS16T0) + config->msel = DMA_MSEL_TIMER1; + if (hperh == BS16T1) + config->msel = DMA_MSEL_TIMER4; + if (hperh == BS16T2) + config->msel = DMA_MSEL_TIMER5; + if (hperh == BS16T3) + config->msel = DMA_MSEL_TIMER7; } #endif diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c index 85539e815a0131bfe4fc4ace236de042e51dbc2b..8e4d13a4d0711aa3b03250562b5579d73f73a6bf 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c @@ -33,7 +33,7 @@ void trng_reset(trng_handle_t *hperh); /** * @} - */ + */ /** @defgroup TRNG_Public_Functions TRNG Public Functions * @{ @@ -68,40 +68,42 @@ void trng_reset(trng_handle_t *hperh); */ ald_status_t ald_trng_init(trng_handle_t *hperh) { - uint32_t tmp = 0; + uint32_t tmp = 0; - if (hperh == NULL) - return ERROR; + if (hperh == NULL) + return ERROR; - assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width)); - assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type)); - assert_param(IS_TRNG_ADJC(hperh->init.adjc)); + assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width)); + assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type)); + assert_param(IS_TRNG_ADJC(hperh->init.adjc)); + assert_param(IS_FUNC_STATE(hperh->init.posten)); + assert_param(IS_TRNG_T_START(hperh->init.t_start)); - __LOCK(hperh); - trng_reset(hperh); + __LOCK(hperh); + trng_reset(hperh); - if (hperh->state == TRNG_STATE_RESET) - __UNLOCK(hperh); + if (hperh->state == TRNG_STATE_RESET) + __UNLOCK(hperh); - tmp = TRNG->CR; + tmp = TRNG->CR; - if (hperh->init.adjc == 0) - tmp = (0 << TRNG_CR_ADJM_POS); - else - tmp = (1 << TRNG_CR_ADJM_POS); + if (hperh->init.adjc == 0) + tmp = (0 << TRNG_CR_ADJM_POS); + else + tmp = (1 << TRNG_CR_ADJM_POS); - tmp |= ((1 << TRNG_CR_TRNGSEL_POS) | (hperh->init.data_width << TRNG_CR_DSEL_POSS) | - (hperh->init.seed_type << TRNG_CR_SDSEL_POSS) | (hperh->init.adjc << TRNG_CR_ADJC_POSS) | - (hperh->init.posten << TRNG_CR_POSTEN_MSK)); + tmp |= ((1 << TRNG_CR_TRNGSEL_POS) | (hperh->init.data_width << TRNG_CR_DSEL_POSS) | + (hperh->init.seed_type << TRNG_CR_SDSEL_POSS) | (hperh->init.adjc << TRNG_CR_ADJC_POSS) | + (hperh->init.posten << TRNG_CR_POSTEN_MSK)); - TRNG->CR = tmp; + TRNG->CR = tmp; - WRITE_REG(TRNG->SEED, hperh->init.seed); - MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (hperh->init.t_start) << TRNG_CFGR_TSTART_POSS); + WRITE_REG(TRNG->SEED, hperh->init.seed); + MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (hperh->init.t_start) << TRNG_CFGR_TSTART_POSS); - hperh->state = TRNG_STATE_READY; - __UNLOCK(hperh); - return OK; + hperh->state = TRNG_STATE_READY; + __UNLOCK(hperh); + return OK; } /** * @} @@ -134,9 +136,9 @@ ald_status_t ald_trng_init(trng_handle_t *hperh) */ uint32_t ald_trng_get_result(trng_handle_t *hperh) { - hperh->state = TRNG_STATE_READY; - hperh->data = hperh->perh->DR; - return (uint32_t)hperh->perh->DR; + hperh->state = TRNG_STATE_READY; + hperh->data = hperh->perh->DR; + return (uint32_t)hperh->perh->DR; } /** @@ -153,15 +155,15 @@ uint32_t ald_trng_get_result(trng_handle_t *hperh) */ void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state) { - assert_param(IS_TRNG_IT(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_TRNG_IT(it)); + assert_param(IS_FUNC_STATE(state)); - if (state) - SET_BIT(hperh->perh->IER, it); - else - CLEAR_BIT(hperh->perh->IER, it); + if (state) + SET_BIT(hperh->perh->IER, it); + else + CLEAR_BIT(hperh->perh->IER, it); - return; + return; } /** @@ -176,12 +178,12 @@ void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t s */ flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status) { - assert_param(IS_TRNG_STATUS(status)); + assert_param(IS_TRNG_STATUS(status)); - if (READ_BIT(hperh->perh->SR, status)) - return SET; + if (READ_BIT(hperh->perh->SR, status)) + return SET; - return RESET; + return RESET; } /** @@ -196,12 +198,12 @@ flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status) */ it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it) { - assert_param(IS_TRNG_IT(it)); + assert_param(IS_TRNG_IT(it)); - if (READ_BIT(hperh->perh->IER, it)) - return SET; + if (READ_BIT(hperh->perh->IER, it)) + return SET; - return RESET; + return RESET; } /** @@ -216,12 +218,12 @@ it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it) */ flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag) { - assert_param(IS_TRNG_FLAG(flag)); + assert_param(IS_TRNG_FLAG(flag)); - if (READ_BIT(hperh->perh->IFR, flag)) - return SET; + if (READ_BIT(hperh->perh->IFR, flag)) + return SET; - return RESET; + return RESET; } /** @@ -234,10 +236,10 @@ flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag) */ void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag) { - assert_param(IS_TRNG_FLAG(flag)); - WRITE_REG(hperh->perh->IFCR, flag); + assert_param(IS_TRNG_FLAG(flag)); + WRITE_REG(hperh->perh->IFCR, flag); - return; + return; } /** @@ -248,15 +250,15 @@ void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag) */ void trng_reset(trng_handle_t *hperh) { - TRNG->CR = 0; - TRNG->SEED = 0; - TRNG->CFGR = 0x1FF0707; - TRNG->IER = 0; - TRNG->IFCR = 0xFFFFFFFF; - - hperh->state = TRNG_STATE_READY; - __UNLOCK(hperh); - return; + TRNG->CR = 0; + TRNG->SEED = 0; + TRNG->CFGR = 0x1FF0707; + TRNG->IER = 0; + TRNG->IFCR = 0xFFFFFFFF; + + hperh->state = TRNG_STATE_READY; + __UNLOCK(hperh); + return; } /** @@ -267,35 +269,28 @@ void trng_reset(trng_handle_t *hperh) */ void ald_trng_irq_handler(trng_handle_t *hperh) { - if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET) - { - hperh->state = TRNG_STATE_ERROR; - ald_trng_clear_flag_status(hperh, TRNG_IF_SERR); - - if (hperh->err_cplt_cbk) - hperh->err_cplt_cbk(hperh); - - return; - } - - if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET) - { - hperh->data = hperh->perh->DR; - hperh->state = TRNG_STATE_READY; - ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD); - - if (hperh->trng_cplt_cbk) - hperh->trng_cplt_cbk(hperh); - } - - if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET) - { - hperh->state = TRNG_STATE_BUSY; - ald_trng_clear_flag_status(hperh, TRNG_IF_START); - - if (hperh->init_cplt_cbk) - hperh->init_cplt_cbk(hperh); - } + if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET) { + hperh->state = TRNG_STATE_ERROR; + ald_trng_clear_flag_status(hperh, TRNG_IF_SERR); + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); + return; + } + + if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET) { + hperh->data = hperh->perh->DR; + hperh->state = TRNG_STATE_READY; + ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD); + if (hperh->trng_cplt_cbk) + hperh->trng_cplt_cbk(hperh); + } + + if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET) { + hperh->state = TRNG_STATE_BUSY; + ald_trng_clear_flag_status(hperh, TRNG_IF_START); + if (hperh->init_cplt_cbk) + hperh->init_cplt_cbk(hperh); + } } /** diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c index b31d5084cb5e0a7b114a0553bfdadcb7667c9de5..5fcd8311f1eaa82fdb8429232ace60736b199867 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c @@ -61,26 +61,39 @@ tsense_cbk __tsense_cbk; /** * @brief Initializes the TSENSE according to the specified - * parameters in the tsense_init_t. - * @param init: Pointer to a tsense_init_t structure that contains - * the configuration information. * @retval None */ -void ald_tsense_init(tsense_init_t *init) +void ald_tsense_init(void) { - assert_param(IS_TSENSE_UPDATE_CYCLE(init->cycle)); - assert_param(IS_TSENSE_OUTPUT_MODE(init->mode)); - - TSENSE_UNLOCK(); - TSENSE->CR = 0; - - MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, init->cycle << TSENSE_CR_TSU_POSS); - MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, init->mode << TSENSE_CR_TOM_POSS); - MODIFY_REG(TSENSE->CR, TSENSE_CR_CTN_MSK, init->ctn << TSENSE_CR_CTN_POS); - MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, init->psc << TSENSE_PSR_PRS_POSS); - TSENSE_LOCK(); - - return; + uint16_t tempt, temptinv; + uint32_t tscic, tscicinv; + + TSENSE_UNLOCK(); + TSENSE->CR = 0; + + MODIFY_REG(TSENSE->CR, TSENSE_CR_CTN_MSK, 0x1 << TSENSE_CR_CTN_POS); + MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, 0x4 << TSENSE_CR_TSU_POSS); + MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, 0x3 << TSENSE_CR_TOM_POSS); + MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, 0x1 << TSENSE_PSR_PRS_POSS); + + TSENSE->HTGR = 0x88F18; + TSENSE->LTGR = 0x85C39; + tempt = *(volatile uint16_t *)0x40348; + temptinv = *(volatile uint16_t *)0x4034A; + tscic = *(volatile uint32_t *)0x40350; + tscicinv = *(volatile uint32_t *)0x40358; + + if ((tempt == (uint16_t)(~temptinv)) && (tscic == (~tscicinv))) { + TSENSE->TBDR = tempt; + TSENSE->TCALBDR = (tscic & 0x1FFFFFF) >> 6; + } + else { + TSENSE->TBDR = 0x1E00; + TSENSE->TCALBDR = 0x1FE70; + } + + TSENSE_LOCK(); + return; } /** @@ -90,26 +103,23 @@ void ald_tsense_init(tsense_init_t *init) */ void ald_tsense_source_select(tsense_source_sel_t sel) { - assert_param(IS_TSENSE_SOURCE_SEL(sel)); - - BKPC_UNLOCK(); - MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS); - - if (sel == TSENSE_SOURCE_LOSC) - { - SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); - } - else if (sel == TSENSE_SOURCE_LRC) - { - SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); - } - else - { - ; /* do nothing */ - } - - BKPC_LOCK(); - return; + assert_param(IS_TSENSE_SOURCE_SEL(sel)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS); + + if (sel == TSENSE_SOURCE_LOSC) { + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); + } + else if (sel == TSENSE_SOURCE_LRC) { + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); + } + else { + ; /* do nothing */ + } + + BKPC_LOCK(); + return; } /** * @} @@ -140,27 +150,40 @@ void ald_tsense_source_select(tsense_source_sel_t sel) */ ald_status_t ald_tsense_get_value(uint16_t *tsense) { - uint32_t tmp = 0; + uint32_t tmp = 0; + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + + while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000)); - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); - TSENSE_LOCK(); + if (tmp >= 1000000) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + return TIMEOUT; + } - while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000)); + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + TSENSE_LOCK(); - if (tmp >= 1000000) - return TIMEOUT; + if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + return ERROR; + } - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - TSENSE_LOCK(); + *tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS); - if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) - return ERROR; + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); - *tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS); - return OK; + return OK; } /** @@ -170,15 +193,15 @@ ald_status_t ald_tsense_get_value(uint16_t *tsense) */ void ald_tsense_get_value_by_it(tsense_cbk cbk) { - __tsense_cbk = cbk; + __tsense_cbk = cbk; - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - SET_BIT(TSENSE->IE, TSENSE_IE_TSENSE_MSK); - SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); - TSENSE_LOCK(); + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + SET_BIT(TSENSE->IE, TSENSE_IE_TSENSE_MSK); + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); - return; + return; } /** @@ -187,25 +210,32 @@ void ald_tsense_get_value_by_it(tsense_cbk cbk) */ void ald_tsense_irq_handler(void) { - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - TSENSE_LOCK(); - - if (__tsense_cbk == NULL) - return; - - if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) - { - __tsense_cbk(0, ERROR); - return; - } - - __tsense_cbk(READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS), OK); - - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - TSENSE_LOCK(); - return; + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + TSENSE_LOCK(); + + if (__tsense_cbk == NULL) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + return; + } + + if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + __tsense_cbk(0, ERROR); + return; + } + + __tsense_cbk(READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS), OK); + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + return; } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c index ee0751ad8d07847a8406b11a7f8f0036fae5036a..59c2489bfafe22362491dfe96f17cd62aabc9880 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c @@ -112,14 +112,14 @@ */ static void uart_dma_send_cplt(void *arg) { - uart_handle_t *hperh = (uart_handle_t *)arg; + uart_handle_t *hperh = (uart_handle_t *)arg; - if (hperh->state == UART_STATE_BUSY_TX) - ald_uart_dma_req_config(hperh, DISABLE); + if (hperh->state == UART_STATE_BUSY_TX) + ald_uart_dma_req_config(hperh, DISABLE); - hperh->tx_count = 0; - ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); - return; + hperh->tx_count = 0; + ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + return; } /** @@ -129,18 +129,18 @@ static void uart_dma_send_cplt(void *arg) */ static void uart_dma_recv_cplt(void *arg) { - uart_handle_t *hperh = (uart_handle_t *)arg; + uart_handle_t *hperh = (uart_handle_t *)arg; - if (hperh->state == UART_STATE_BUSY_RX) - ald_uart_dma_req_config(hperh, DISABLE); + if (hperh->state == UART_STATE_BUSY_RX) + ald_uart_dma_req_config(hperh, DISABLE); - hperh->rx_count = 0; - CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + hperh->rx_count = 0; + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); - return; + return; } /** @@ -150,18 +150,18 @@ static void uart_dma_recv_cplt(void *arg) */ static void uart_dma_error(void *arg) { - uart_handle_t *hperh = (uart_handle_t *)arg; + uart_handle_t *hperh = (uart_handle_t *)arg; - hperh->rx_count = 0; - hperh->tx_count = 0; - hperh->state = UART_STATE_READY; - hperh->err_code |= UART_ERROR_DMA; - ald_uart_dma_req_config(hperh, DISABLE); + hperh->rx_count = 0; + hperh->tx_count = 0; + hperh->state = UART_STATE_READY; + hperh->err_code |= UART_ERROR_DMA; + ald_uart_dma_req_config(hperh, DISABLE); - if (hperh->error_cbk) - hperh->error_cbk(hperh); + if (hperh->error_cbk) + hperh->error_cbk(hperh); - return; + return; } #endif @@ -175,21 +175,20 @@ static void uart_dma_error(void *arg) */ static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout) { - uint32_t tick; + uint32_t tick; - if (timeout == 0) - return ERROR; + if (timeout == 0) + return ERROR; - tick = ald_get_tick(); + tick = ald_get_tick(); - /* Waiting for flag */ - while ((ald_uart_get_status(hperh, flag)) != status) - { - if (((ald_get_tick()) - tick) > timeout) - return TIMEOUT; - } + /* Waiting for flag */ + while ((ald_uart_get_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } - return OK; + return OK; } /** @@ -199,19 +198,18 @@ static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, fla */ static ald_status_t __uart_send_by_it(uart_handle_t *hperh) { - if ((hperh->state & UART_STATE_TX_MASK) == 0x0) - return BUSY; + if ((hperh->state & UART_STATE_TX_MASK) == 0x0) + return BUSY; - WRITE_REG(hperh->perh->TBR, (uint8_t)(*hperh->tx_buf++ & 0x00FF)); + WRITE_REG(hperh->perh->TBR, (uint8_t)(*hperh->tx_buf++ & 0x00FF)); - if (--hperh->tx_count == 0) - { - ald_uart_clear_flag_status(hperh, UART_IF_TC); - ald_uart_interrupt_config(hperh, UART_IT_TXS, DISABLE); - ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); - } + if (--hperh->tx_count == 0) { + ald_uart_clear_flag_status(hperh, UART_IF_TC); + ald_uart_interrupt_config(hperh, UART_IT_TXS, DISABLE); + ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + } - return OK; + return OK; } /** @@ -221,16 +219,15 @@ static ald_status_t __uart_send_by_it(uart_handle_t *hperh) */ static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh) { - if (!(READ_BIT(hperh->perh->SR, UART_SR_TEM_MSK))) - return OK; + if (!(READ_BIT(hperh->perh->SR, UART_SR_TEM_MSK))) + return OK; - ald_uart_interrupt_config(hperh, UART_IT_TC, DISABLE); - CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + ald_uart_interrupt_config(hperh, UART_IT_TC, DISABLE); + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); - if (hperh->tx_cplt_cbk) - hperh->tx_cplt_cbk(hperh); - - return OK; + return OK; } /** @@ -240,21 +237,25 @@ static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh) */ static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) { - if ((hperh->state & UART_STATE_RX_MASK) == 0x0) - return BUSY; + if ((hperh->state & UART_STATE_RX_MASK) == 0x0) + return BUSY; - *hperh->rx_buf++ = (uint8_t)(hperh->perh->RBR & 0xFF); + while(READ_BIT(hperh->perh->SR, UART_SR_DR_MSK) != RESET) { + *hperh->rx_buf++ = (uint8_t)(hperh->perh->RBR & 0xFF); + + if (--hperh->rx_count == 0) + break; + } - if (--hperh->rx_count == 0) - { - ald_uart_interrupt_config(hperh, UART_IT_RXRD, DISABLE); - CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + if (--hperh->rx_count == 0) { + ald_uart_interrupt_config(hperh, UART_IT_RXRD, DISABLE); + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - } + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } - return OK; + return OK; } /** * @} @@ -299,21 +300,21 @@ static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) */ void ald_uart_reset(uart_handle_t *hperh) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - WRITE_REG(hperh->perh->BRR, 0x0); - WRITE_REG(hperh->perh->LCR, 0x0); - WRITE_REG(hperh->perh->MCR, 0x0); - WRITE_REG(hperh->perh->CR, 0x0); - WRITE_REG(hperh->perh->RTOR, 0x0); - WRITE_REG(hperh->perh->FCR, 0x0); - WRITE_REG(hperh->perh->IDR, 0xFFF); + WRITE_REG(hperh->perh->BRR, 0x0); + WRITE_REG(hperh->perh->LCR, 0x0); + WRITE_REG(hperh->perh->MCR, 0x0); + WRITE_REG(hperh->perh->CR, 0x0); + WRITE_REG(hperh->perh->RTOR, 0x0); + WRITE_REG(hperh->perh->FCR, 0x0); + WRITE_REG(hperh->perh->IDR, 0xFFF); - hperh->err_code = UART_ERROR_NONE; - hperh->state = UART_STATE_RESET; + hperh->err_code = UART_ERROR_NONE; + hperh->state = UART_STATE_RESET; - __UNLOCK(hperh); - return; + __UNLOCK(hperh); + return; } /** @@ -325,55 +326,54 @@ void ald_uart_reset(uart_handle_t *hperh) */ void ald_uart_init(uart_handle_t *hperh) { - uint32_t tmp; - - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_BAUDRATE(hperh->init.baud)); - assert_param(IS_UART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_UART_STOPBITS(hperh->init.stop_bits)); - assert_param(IS_UART_PARITY(hperh->init.parity)); - assert_param(IS_UART_MODE(hperh->init.mode)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); - - ald_uart_reset(hperh); - - tmp = READ_REG(hperh->perh->LCR); - MODIFY_REG(tmp, UART_LCR_DLS_MSK, hperh->init.word_length << UART_LCR_DLS_POSS); - MODIFY_REG(tmp, UART_LCR_STOP_MSK, hperh->init.stop_bits << UART_LCR_STOP_POS); - MODIFY_REG(tmp, UART_LCR_PEN_MSK, (hperh->init.parity == UART_PARITY_NONE ? 0 : 1) << UART_LCR_PEN_POS); - MODIFY_REG(tmp, UART_LCR_PS_MSK, (hperh->init.parity == UART_PARITY_EVEN ? 1 : 0) << UART_LCR_PS_POS); - WRITE_REG(hperh->perh->LCR, tmp); - MODIFY_REG(hperh->perh->MCR, UART_MCR_AFCEN_MSK, hperh->init.fctl << UART_MCR_AFCEN_POS); - SET_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); - WRITE_REG(hperh->perh->BRR, ald_cmu_get_pclk1_clock() / hperh->init.baud); - CLEAR_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); - SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); - SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); - SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK); - MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, 0 << UART_FCR_RXTL_POSS); - MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, 0 << UART_FCR_TXTL_POSS); - SET_BIT(hperh->perh->LCR, UART_LCR_RXEN_MSK); - - if (hperh->init.mode == UART_MODE_LIN) - SET_BIT(hperh->perh->MCR, UART_MCR_LINEN_MSK); - else if (hperh->init.mode == UART_MODE_IrDA) - SET_BIT(hperh->perh->MCR, UART_MCR_IREN_MSK); - else if (hperh->init.mode == UART_MODE_RS485) - SET_BIT(hperh->perh->MCR, UART_MCR_AADEN_MSK); - else if (hperh->init.mode == UART_MODE_HDSEL) - SET_BIT(hperh->perh->MCR, UART_MCR_HDSEL_MSK); - else - ;/* do nothing */ - - if (hperh->init.fctl) - SET_BIT(hperh->perh->MCR, UART_MCR_RTSCTRL_MSK); - - if (hperh->init.mode == UART_MODE_IrDA) - SET_BIT(hperh->perh->LCR, UART_LCR_RXINV_MSK); - - hperh->state = UART_STATE_READY; - hperh->err_code = UART_ERROR_NONE; - return; + uint32_t tmp; + + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_BAUDRATE(hperh->init.baud)); + assert_param(IS_UART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_UART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_UART_PARITY(hperh->init.parity)); + assert_param(IS_UART_MODE(hperh->init.mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); + + ald_uart_reset(hperh); + + tmp = READ_REG(hperh->perh->LCR); + MODIFY_REG(tmp, UART_LCR_DLS_MSK, hperh->init.word_length << UART_LCR_DLS_POSS); + MODIFY_REG(tmp, UART_LCR_STOP_MSK, hperh->init.stop_bits << UART_LCR_STOP_POS); + MODIFY_REG(tmp, UART_LCR_PEN_MSK, (hperh->init.parity == UART_PARITY_NONE ? 0 : 1) << UART_LCR_PEN_POS); + MODIFY_REG(tmp, UART_LCR_PS_MSK, (hperh->init.parity == UART_PARITY_EVEN ? 1 : 0) << UART_LCR_PS_POS); + WRITE_REG(hperh->perh->LCR, tmp); + MODIFY_REG(hperh->perh->MCR, UART_MCR_AFCEN_MSK, hperh->init.fctl << UART_MCR_AFCEN_POS); + SET_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); + WRITE_REG(hperh->perh->BRR, ald_cmu_get_pclk1_clock() / hperh->init.baud); + CLEAR_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); + SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); + SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); + SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK); + MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, 0 << UART_FCR_RXTL_POSS); + MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, 0 << UART_FCR_TXTL_POSS); + SET_BIT(hperh->perh->LCR, UART_LCR_RXEN_MSK); + + if (hperh->init.mode == UART_MODE_LIN) + SET_BIT(hperh->perh->MCR, UART_MCR_LINEN_MSK); + else if (hperh->init.mode == UART_MODE_IrDA) + SET_BIT(hperh->perh->MCR, UART_MCR_IREN_MSK); + else if (hperh->init.mode == UART_MODE_RS485) + SET_BIT(hperh->perh->MCR, UART_MCR_AADEN_MSK); + else if (hperh->init.mode == UART_MODE_HDSEL) + SET_BIT(hperh->perh->MCR, UART_MCR_HDSEL_MSK); + else + ;/* do nothing */ + + if (hperh->init.fctl) + SET_BIT(hperh->perh->MCR, UART_MCR_RTSCTRL_MSK); + if (hperh->init.mode == UART_MODE_IrDA) + SET_BIT(hperh->perh->LCR, UART_LCR_RXINV_MSK); + + hperh->state = UART_STATE_READY; + hperh->err_code = UART_ERROR_NONE; + return; } /** @@ -386,17 +386,17 @@ void ald_uart_init(uart_handle_t *hperh) */ void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_FUNC_STATE(config->normal)); - assert_param(IS_FUNC_STATE(config->dir)); - assert_param(IS_FUNC_STATE(config->invert)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_FUNC_STATE(config->normal)); + assert_param(IS_FUNC_STATE(config->dir)); + assert_param(IS_FUNC_STATE(config->invert)); - MODIFY_REG(hperh->perh->MCR, UART_MCR_AADNOR_MSK, config->normal << UART_MCR_AADNOR_POS); - MODIFY_REG(hperh->perh->MCR, UART_MCR_AADDIR_MSK, config->dir << UART_MCR_AADDIR_POS); - MODIFY_REG(hperh->perh->MCR, UART_MCR_AADINV_MSK, config->invert << UART_MCR_AADINV_POS); - MODIFY_REG(hperh->perh->CR, UART_CR_ADDR_MSK, config->addr << UART_CR_ADDR_POSS); + MODIFY_REG(hperh->perh->MCR, UART_MCR_AADNOR_MSK, config->normal << UART_MCR_AADNOR_POS); + MODIFY_REG(hperh->perh->MCR, UART_MCR_AADDIR_MSK, config->dir << UART_MCR_AADDIR_POS); + MODIFY_REG(hperh->perh->MCR, UART_MCR_AADINV_MSK, config->invert << UART_MCR_AADINV_POS); + MODIFY_REG(hperh->perh->CR, UART_CR_ADDR_MSK, config->addr << UART_CR_ADDR_POSS); - return; + return; } /** * @} @@ -460,44 +460,41 @@ void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) */ ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) - return BUSY; + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL) || (size == 0)) + return ERROR; - __LOCK(hperh); - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_TX_MASK); + __LOCK(hperh); + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); - hperh->tx_size = size; - hperh->tx_count = size; + hperh->tx_size = size; + hperh->tx_count = size; - while (hperh->tx_count-- > 0) - { - if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = UART_STATE_READY; - return TIMEOUT; - } + while (hperh->tx_count-- > 0) { + if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } - WRITE_REG(hperh->perh->TBR, (*buf++ & 0xFF)); - } + WRITE_REG(hperh->perh->TBR, (*buf++ & 0xFF)); + } - if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = UART_STATE_READY; - return TIMEOUT; - } + if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } - CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); - __UNLOCK(hperh); + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + __UNLOCK(hperh); - return OK; + return OK; } /** @@ -510,38 +507,61 @@ ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, ui */ ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - assert_param(IS_UART_ALL(hperh->perh)); - - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_RX_MASK); - - hperh->rx_size = size; - hperh->rx_count = size; - - while (hperh->rx_count-- > 0) - { - if (uart_wait_flag(hperh, UART_STATUS_DR, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = UART_STATE_READY; - return TIMEOUT; - } - - *buf++ = (uint8_t)(hperh->perh->RBR & 0xFF); - } - - CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); - __UNLOCK(hperh); - - return OK; + uint32_t stat = 0; + uint32_t err = 0; + + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + hperh->rx_size = size; + hperh->rx_count = size; + + err = (UART_ERROR_PE | UART_STATUS_FE | UART_STATUS_OE); + + while (hperh->rx_count-- > 0) { + if (uart_wait_flag(hperh, UART_STATUS_DR, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + stat = hperh->perh->SR; + + if ((stat & err) == RESET) { + *buf++ = (uint8_t)(hperh->perh->RBR & 0xFF); + } else { + /* Handle parity error */ + if ((READ_BIT(stat, UART_STATUS_PE)) != RESET) + hperh->err_code |= UART_ERROR_PE; + + /* Handle frame error */ + if ((READ_BIT(stat, UART_STATUS_FE)) != RESET) + hperh->err_code |= UART_ERROR_FE; + + /* Handle overflow error */ + if ((READ_BIT(stat, UART_STATUS_OE)) != RESET) + hperh->err_code |= UART_ERROR_ORE; + + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + __UNLOCK(hperh); + + return ERROR; + } + } + + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + __UNLOCK(hperh); + + return OK; } /** @@ -553,38 +573,36 @@ ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, ui */ ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) { - assert_param(IS_UART_ALL(hperh->perh)); - - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_TX_MASK); - __UNLOCK(hperh); - - if (((ald_uart_get_status(hperh, UART_STATUS_TBEM)) == SET) - && ((ald_uart_get_flag_status(hperh, UART_IF_TXS)) == RESET)) - { - WRITE_REG(hperh->perh->TBR, (*hperh->tx_buf++ & 0xFF)); - --hperh->tx_count; - } - - if (hperh->tx_count == 0) - { - ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); - return OK; - } - - ald_uart_interrupt_config(hperh, UART_IT_TXS, ENABLE); - return OK; + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + __UNLOCK(hperh); + + if (((ald_uart_get_status(hperh, UART_STATUS_TBEM)) == SET) + && ((ald_uart_get_flag_status(hperh, UART_IF_TXS)) == RESET)) { + WRITE_REG(hperh->perh->TBR, (*hperh->tx_buf++ & 0xFF)); + --hperh->tx_count; + } + + if (hperh->tx_count == 0) { + ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + return OK; + } + + ald_uart_interrupt_config(hperh, UART_IT_TXS, ENABLE); + return OK; } /** @@ -596,24 +614,24 @@ ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t si */ ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) - return BUSY; + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL ) || (size == 0)) + return ERROR; - __LOCK(hperh); - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_RX_MASK); - __UNLOCK(hperh); + __LOCK(hperh); + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + __UNLOCK(hperh); - ald_uart_interrupt_config(hperh, UART_IT_RXRD, ENABLE); - return OK; + ald_uart_interrupt_config(hperh, UART_IT_RXRD, ENABLE); + return OK; } #ifdef ALD_DMA /** @@ -626,64 +644,63 @@ ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t si */ ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - assert_param(IS_UART_ALL(hperh->perh)); - - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_TX_MASK); - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = uart_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = uart_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->TBR; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART_TXEMPTY; - hperh->hdmatx.config.burst = ENABLE; - hperh->hdmatx.config.channel = channel; - - if (hperh->init.mode == UART_MODE_RS485) - { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - if (hperh->perh == UART0) - hperh->hdmatx.config.msel = DMA_MSEL_UART0; - else if (hperh->perh == UART1) - hperh->hdmatx.config.msel = DMA_MSEL_UART1; - else if (hperh->perh == UART2) - hperh->hdmatx.config.msel = DMA_MSEL_UART2; - else if (hperh->perh == UART3) - hperh->hdmatx.config.msel = DMA_MSEL_UART3; - else - ; /* do nothing */ - - ald_dma_config_basic(&hperh->hdmatx); - - __UNLOCK(hperh); - ald_uart_clear_flag_status(hperh, UART_IF_TC); - ald_uart_dma_req_config(hperh, ENABLE); - - return OK; + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = uart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = uart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TBR; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART_TXEMPTY; + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.channel = channel; + + if (hperh->init.mode == UART_MODE_RS485) { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + if (hperh->perh == UART0) + hperh->hdmatx.config.msel = DMA_MSEL_UART0; + else if (hperh->perh == UART1) + hperh->hdmatx.config.msel = DMA_MSEL_UART1; + else if (hperh->perh == UART2) + hperh->hdmatx.config.msel = DMA_MSEL_UART2; + else if (hperh->perh == UART3) + hperh->hdmatx.config.msel = DMA_MSEL_UART3; + else + ; /* do nothing */ + + ald_dma_config_basic(&hperh->hdmatx); + + __UNLOCK(hperh); + ald_uart_clear_flag_status(hperh, UART_IF_TC); + ald_uart_dma_req_config(hperh, ENABLE); + + return OK; } /** @@ -696,61 +713,60 @@ ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t s */ ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - assert_param(IS_UART_ALL(hperh->perh)); - - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_RX_MASK); - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = uart_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = uart_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->RBR; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART_RNR; - hperh->hdmarx.config.burst = ENABLE; - hperh->hdmarx.config.channel = channel; - - if (hperh->init.mode == UART_MODE_RS485) - { - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - if (hperh->perh == UART0) - hperh->hdmarx.config.msel = DMA_MSEL_UART0; - else if (hperh->perh == UART1) - hperh->hdmarx.config.msel = DMA_MSEL_UART1; - else if (hperh->perh == UART2) - hperh->hdmarx.config.msel = DMA_MSEL_UART2; - else if (hperh->perh == UART3) - hperh->hdmarx.config.msel = DMA_MSEL_UART3; - else - ; - - ald_dma_config_basic(&hperh->hdmarx); - __UNLOCK(hperh); - ald_uart_dma_req_config(hperh, ENABLE); - - return OK; + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = uart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = uart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RBR; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART_RNR; + hperh->hdmarx.config.burst = ENABLE; + hperh->hdmarx.config.channel = channel; + + if (hperh->init.mode == UART_MODE_RS485) { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + if (hperh->perh == UART0) + hperh->hdmarx.config.msel = DMA_MSEL_UART0; + else if (hperh->perh == UART1) + hperh->hdmarx.config.msel = DMA_MSEL_UART1; + else if (hperh->perh == UART2) + hperh->hdmarx.config.msel = DMA_MSEL_UART2; + else if (hperh->perh == UART3) + hperh->hdmarx.config.msel = DMA_MSEL_UART3; + else + ; + + ald_dma_config_basic(&hperh->hdmarx); + __UNLOCK(hperh); + ald_uart_dma_req_config(hperh, ENABLE); + + return OK; } /** @@ -760,10 +776,10 @@ ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t s */ ald_status_t ald_uart_dma_pause(uart_handle_t *hperh) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - ald_uart_dma_req_config(hperh, DISABLE); - return OK; + ald_uart_dma_req_config(hperh, DISABLE); + return OK; } /** @@ -773,10 +789,10 @@ ald_status_t ald_uart_dma_pause(uart_handle_t *hperh) */ ald_status_t ald_uart_dma_resume(uart_handle_t *hperh) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - ald_uart_dma_req_config(hperh, ENABLE); - return OK; + ald_uart_dma_req_config(hperh, ENABLE); + return OK; } /** @@ -786,11 +802,11 @@ ald_status_t ald_uart_dma_resume(uart_handle_t *hperh) */ ald_status_t ald_uart_dma_stop(uart_handle_t *hperh) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - ald_uart_dma_req_config(hperh, DISABLE); - hperh->state = UART_STATE_READY; - return OK; + ald_uart_dma_req_config(hperh, DISABLE); + hperh->state = UART_STATE_READY; + return OK; } #endif @@ -801,49 +817,51 @@ ald_status_t ald_uart_dma_stop(uart_handle_t *hperh) */ void ald_uart_irq_handler(uart_handle_t *hperh) { - assert_param(IS_UART_ALL(hperh->perh)); - - /* Handle parity error */ - if ((ald_uart_get_status(hperh, UART_STATUS_PE)) != RESET) - hperh->err_code |= UART_ERROR_PE; - - /* Handle frame error */ - if ((ald_uart_get_status(hperh, UART_STATUS_FE)) != RESET) - hperh->err_code |= UART_ERROR_FE; - - /* Handle overflow error */ - if ((ald_uart_get_status(hperh, UART_STATUS_OE)) != RESET) - hperh->err_code |= UART_ERROR_ORE; - - /* Receive */ - if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RXRD)) != RESET) - { - ald_uart_clear_flag_status(hperh, UART_IF_RXRD); - __uart_recv_by_it(hperh); - } - - /* Transmit */ - if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TXS)) != RESET) - { - ald_uart_clear_flag_status(hperh, UART_IF_TXS); - __uart_send_by_it(hperh); - } - - /* End Transmit */ - if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TC)) != RESET) - { - ald_uart_clear_flag_status(hperh, UART_IF_TC); - __uart_end_send_by_it(hperh); - } - - /* Handle error state */ - if (hperh->err_code != UART_ERROR_NONE) - { - hperh->state = UART_STATE_READY; - - if (hperh->error_cbk) - hperh->error_cbk(hperh); - } + uint32_t stat = 0; + + assert_param(IS_UART_ALL(hperh->perh)); + + stat = hperh->perh->SR; + + /* Handle parity error */ + if ((READ_BIT(stat, UART_STATUS_PE)) != RESET) + hperh->err_code |= UART_ERROR_PE; + + /* Handle frame error */ + if ((READ_BIT(stat, UART_STATUS_FE)) != RESET) + hperh->err_code |= UART_ERROR_FE; + + /* Handle overflow error */ + if ((READ_BIT(stat, UART_STATUS_OE)) != RESET) { + hperh->err_code |= UART_ERROR_ORE; + UART_FIFO_RX_RESET(hperh); + } + + /* Receive */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RXRD)) != RESET) { + __uart_recv_by_it(hperh); + ald_uart_clear_flag_status(hperh, UART_IF_RXRD); + } + + /* Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TXS)) != RESET) { + __uart_send_by_it(hperh); + ald_uart_clear_flag_status(hperh, UART_IF_TXS); + } + + /* End Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TC)) != RESET) { + __uart_end_send_by_it(hperh); + ald_uart_clear_flag_status(hperh, UART_IF_TC); + } + + /* Handle error state */ + if (hperh->err_code != UART_ERROR_NONE) { + hperh->state = UART_STATE_READY; + + if (hperh->error_cbk) + hperh->error_cbk(hperh); + } } /** * @} @@ -888,16 +906,16 @@ void ald_uart_irq_handler(uart_handle_t *hperh) */ void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IT(it)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IT(it)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - WRITE_REG(hperh->perh->IER, it); - else - WRITE_REG(hperh->perh->IDR, it); + if (state == ENABLE) + WRITE_REG(hperh->perh->IER, it); + else + WRITE_REG(hperh->perh->IDR, it); - return; + return; } /** @@ -911,55 +929,51 @@ void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t s */ void ald_uart_dma_req_config(uart_handle_t *hperh, type_func_t state) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_FUNC_STATE(state)); - if (state == ENABLE) - SET_BIT(hperh->perh->MCR, UART_MCR_DMAEN_MSK); - else - CLEAR_BIT(hperh->perh->MCR, UART_MCR_DMAEN_MSK); + if (state == ENABLE) + SET_BIT(hperh->perh->MCR, UART_MCR_DMAEN_MSK); + else + CLEAR_BIT(hperh->perh->MCR, UART_MCR_DMAEN_MSK); - return; + return; } /** * @brief Configure transmit fifo parameters. * @param hperh: Pointer to a uart_handle_t structure. * @param config: Transmit fifo trigger level. - * @param level: Transmit fifo level. * @retval None */ -void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) +void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_TXFIFO_TYPE(config)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_TXFIFO_TYPE(config)); - SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK); - MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, config << UART_FCR_TXTL_POSS); - MODIFY_REG(hperh->perh->FCR, UART_FCR_TXFL_MSK, level << UART_FCR_TXFL_POSS); - SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); + SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK); + MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, config << UART_FCR_TXTL_POSS); + SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); - return; + return; } /** * @brief Configure receive fifo parameters. * @param hperh: Pointer to a uart_handle_t structure. * @param config: Receive fifo trigger level. - * @param level: Receive fifo level. * @retval None */ -void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) +void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_RXFIFO_TYPE(config)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_RXFIFO_TYPE(config)); - SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); - MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, config << UART_FCR_RXTL_POSS); - MODIFY_REG(hperh->perh->FCR, UART_FCR_RXFL_MSK, level << UART_FCR_RXFL_POSS); - SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); + SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); + MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, config << UART_FCR_RXTL_POSS); + SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); - return; + return; } /** @@ -969,10 +983,10 @@ void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t */ void ald_uart_lin_send_break(uart_handle_t *hperh) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - SET_BIT(hperh->perh->MCR, UART_MCR_BKREQ_MSK); - return; + SET_BIT(hperh->perh->MCR, UART_MCR_BKREQ_MSK); + return; } /** @@ -985,11 +999,11 @@ void ald_uart_lin_send_break(uart_handle_t *hperh) */ void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_LIN_BREAK_LEN(len)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_LIN_BREAK_LEN(len)); - MODIFY_REG(hperh->perh->MCR, UART_MCR_LINBDL_MSK, len << UART_MCR_LINBDL_POS); - return; + MODIFY_REG(hperh->perh->MCR, UART_MCR_LINBDL_MSK, len << UART_MCR_LINBDL_POS); + return; } /** @@ -1003,11 +1017,11 @@ void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_l */ void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_AUTO_BAUD_MODE(mode)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_AUTO_BAUD_MODE(mode)); - MODIFY_REG(hperh->perh->MCR, UART_MCR_ABRMOD_MSK, mode << UART_MCR_ABRMOD_POSS); - return; + MODIFY_REG(hperh->perh->MCR, UART_MCR_ABRMOD_MSK, mode << UART_MCR_ABRMOD_POSS); + return; } /** @@ -1020,30 +1034,28 @@ void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode) */ ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout) { - assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_ALL(hperh->perh)); - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) - return BUSY; + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; - SET_BIT(hperh->state, UART_STATE_TX_MASK); + SET_BIT(hperh->state, UART_STATE_TX_MASK); - if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) - { - hperh->state = UART_STATE_READY; - return TIMEOUT; - } + if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } - WRITE_REG(hperh->perh->TBR, (addr | 0x100)); + WRITE_REG(hperh->perh->TBR, (addr | 0x100)); - if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) - { - hperh->state = UART_STATE_READY; - return TIMEOUT; - } + if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } - CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); - return OK; + return OK; } /** @@ -1057,13 +1069,13 @@ ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint3 */ it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IT(it)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IT(it)); - if (READ_BIT(hperh->perh->IVS, it)) - return SET; + if (READ_BIT(hperh->perh->IVS, it)) + return SET; - return RESET; + return RESET; } /** @@ -1077,13 +1089,13 @@ it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it) */ flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_STATUS(status)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_STATUS(status)); - if (READ_BIT(hperh->perh->SR, status)) - return SET; + if (READ_BIT(hperh->perh->SR, status)) + return SET; - return RESET; + return RESET; } @@ -1098,13 +1110,13 @@ flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status) */ flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IF(flag)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); - if (READ_BIT(hperh->perh->RIF, flag)) - return SET; + if (READ_BIT(hperh->perh->RIF, flag)) + return SET; - return RESET; + return RESET; } /** @@ -1118,13 +1130,13 @@ flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag) */ flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IF(flag)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); - if (READ_BIT(hperh->perh->IFM, flag)) - return SET; + if (READ_BIT(hperh->perh->IFM, flag)) + return SET; - return RESET; + return RESET; } /** @@ -1136,11 +1148,11 @@ flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t fl */ void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) { - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IF(flag)); + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); - WRITE_REG(hperh->perh->ICR, flag); - return; + WRITE_REG(hperh->perh->ICR, flag); + return; } /** * @} @@ -1171,7 +1183,7 @@ void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) */ uart_state_t ald_uart_get_state(uart_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** @@ -1181,7 +1193,7 @@ uart_state_t ald_uart_get_state(uart_handle_t *hperh) */ uint32_t ald_uart_get_error(uart_handle_t *hperh) { - return hperh->err_code; + return hperh->err_code; } /** diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c index 18672dd07e84908f68354d78175bd40443cc26e1..1e9ed5c50147b929c9c3fb21f03428f3ec91bb67 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c @@ -173,7 +173,7 @@ uint8_t __frame_mode = 0; /** @addtogroup USART_Private_Functions USART Private Functions * @{ */ -static void usart_set_config(usart_handle_t *hperh); +static void usart_set_config (usart_handle_t *hperh); static ald_status_t __usart_send_by_it(usart_handle_t *hperh); static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh); static ald_status_t __usart_recv_by_it(usart_handle_t *hperh); @@ -181,9 +181,9 @@ static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh); static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh); static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh); #ifdef ALD_DMA - static void usart_dma_send_cplt(void *arg); - static void usart_dma_recv_cplt(void *arg); - static void usart_dma_error(void *arg); +static void usart_dma_send_cplt(void *arg); +static void usart_dma_recv_cplt(void *arg); +static void usart_dma_error(void *arg); #endif static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout); /** @@ -247,20 +247,20 @@ static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, fl */ void ald_usart_reset(usart_handle_t *hperh) { - assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART(hperh->perh)); - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); - WRITE_REG(hperh->perh->CON0, 0x0); - WRITE_REG(hperh->perh->CON1, 0x0); - WRITE_REG(hperh->perh->CON2, 0x0); + WRITE_REG(hperh->perh->CON0, 0x0); + WRITE_REG(hperh->perh->CON1, 0x0); + WRITE_REG(hperh->perh->CON2, 0x0); - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_RESET; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_RESET; - __UNLOCK(hperh); - return; + __UNLOCK(hperh); + return; } /** @@ -272,30 +272,29 @@ void ald_usart_reset(usart_handle_t *hperh) */ ald_status_t ald_usart_init(usart_handle_t *hperh) { - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - - ald_usart_reset(hperh); - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); - usart_set_config(hperh); - - /* In asynchronous mode, the following bits must be kept cleared: - * - LINEN and CLKEN bits in the USART_CR2 register, - * - SCEN, HDSEL and IREN bits in the USART_CR3 register. - */ - CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_READY; - USART_ENABLE(hperh); - - return OK; + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + + ald_usart_reset(hperh); + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); + usart_set_config(hperh); + + /* In asynchronous mode, the following bits must be kept cleared: + * - LINEN and CLKEN bits in the USART_CR2 register, + * - SCEN, HDSEL and IREN bits in the USART_CR3 register. + */ + CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_READY; + USART_ENABLE(hperh); + + return OK; } /** @@ -307,28 +306,27 @@ ald_status_t ald_usart_init(usart_handle_t *hperh) */ ald_status_t ald_usart_half_duplex_init(usart_handle_t *hperh) { - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - - ald_usart_reset(hperh); - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); - usart_set_config(hperh); - - /* In half-duplex mode, the following bits must be kept cleared: - * - LINEN and CLKEN bits in the USART_CR2 register, - * - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - SET_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_READY; - USART_ENABLE(hperh); - - return OK; + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + + ald_usart_reset(hperh); + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); + usart_set_config(hperh); + + /* In half-duplex mode, the following bits must be kept cleared: + * - LINEN and CLKEN bits in the USART_CR2 register, + * - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + SET_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_READY; + USART_ENABLE(hperh); + + return OK; } /** @@ -345,32 +343,31 @@ ald_status_t ald_usart_half_duplex_init(usart_handle_t *hperh) */ ald_status_t ald_usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup) { - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_WAKEUP(wakeup)); - assert_param(IS_USART_ADDRESS(addr)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - - ald_usart_reset(hperh); - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); - usart_set_config(hperh); - - /* In Multi-Processor mode, the following bits must be kept cleared: - * - LINEN and CLKEN bits in the USART_CR2 register, - * - SCEN, HDSEL and IREN bits in the USART_CR3 register */ - CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - MODIFY_REG(hperh->perh->CON1, USART_CON1_ADDR_MSK, addr << USART_CON1_ADDR_POSS); - MODIFY_REG(hperh->perh->CON0, USART_CON0_WKMOD_MSK, wakeup << USART_CON0_WKMOD_POS); - - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_READY; - USART_ENABLE(hperh); - - return OK; + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_WAKEUP(wakeup)); + assert_param(IS_USART_ADDRESS(addr)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + + ald_usart_reset(hperh); + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); + usart_set_config(hperh); + + /* In Multi-Processor mode, the following bits must be kept cleared: + * - LINEN and CLKEN bits in the USART_CR2 register, + * - SCEN, HDSEL and IREN bits in the USART_CR3 register */ + CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + MODIFY_REG(hperh->perh->CON1, USART_CON1_ADDR_MSK, addr << USART_CON1_ADDR_POSS); + MODIFY_REG(hperh->perh->CON0, USART_CON0_WKMOD_MSK, wakeup << USART_CON0_WKMOD_POS); + + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_READY; + USART_ENABLE(hperh); + + return OK; } /** @@ -383,31 +380,30 @@ ald_status_t ald_usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, */ ald_status_t ald_usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init) { - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - - ald_usart_reset(hperh); - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); - usart_set_config(hperh); - - /* In Multi-Processor mode, the following bits must be kept cleared: - * - LINEN and CLKEN bits in the USART_CR2 register, - * - SCEN, HDSEL and IREN bits in the USART_CR3 register */ - CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKEN_MSK, init->clk << USART_CON1_SCKEN_POS); - MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKPOL_MSK, init->polarity << USART_CON1_SCKPOL_POS); - MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKPHA_MSK, init->phase << USART_CON1_SCKPHA_POS); - MODIFY_REG(hperh->perh->CON1, USART_CON1_LBCP_MSK, init->last_bit << USART_CON1_LBCP_POS); - - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_READY; - USART_ENABLE(hperh); - - return OK; + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + + ald_usart_reset(hperh); + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); + usart_set_config(hperh); + + /* In Multi-Processor mode, the following bits must be kept cleared: + * - LINEN and CLKEN bits in the USART_CR2 register, + * - SCEN, HDSEL and IREN bits in the USART_CR3 register */ + CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKEN_MSK, init->clk << USART_CON1_SCKEN_POS); + MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKPOL_MSK, init->polarity << USART_CON1_SCKPOL_POS); + MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKPHA_MSK, init->phase << USART_CON1_SCKPHA_POS); + MODIFY_REG(hperh->perh->CON1, USART_CON1_LBCP_MSK, init->last_bit << USART_CON1_LBCP_POS); + + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_READY; + USART_ENABLE(hperh); + + return OK; } /** @@ -485,57 +481,50 @@ ald_status_t ald_usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *ini */ ald_status_t ald_usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - hperh->err_code = USART_ERROR_NONE; - SET_BIT(hperh->state, USART_STATE_TX_MASK); - - hperh->tx_size = size; - hperh->tx_count = size; - - while (hperh->tx_count-- > 0) - { - if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - if (hperh->init.parity == USART_PARITY_NONE) - { - WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & (uint16_t)0x01FF)); - buf += 2; - } - else - { - WRITE_REG(hperh->perh->DATA, *buf++); - } - } - else - { - WRITE_REG(hperh->perh->DATA, *buf++); - } - } - - if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); - __UNLOCK(hperh); - - return OK; + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = USART_ERROR_NONE; + SET_BIT(hperh->state, USART_STATE_TX_MASK); + + hperh->tx_size = size; + hperh->tx_count = size; + + while (hperh->tx_count-- > 0) { + if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + if (hperh->init.parity == USART_PARITY_NONE) { + WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & (uint16_t)0x01FF)); + buf += 2; + } + else { + WRITE_REG(hperh->perh->DATA, *buf++); + } + } + else { + WRITE_REG(hperh->perh->DATA, *buf++); + } + } + + if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); + __UNLOCK(hperh); + + return OK; } /** @@ -549,54 +538,48 @@ ald_status_t ald_usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, */ ald_status_t ald_usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - hperh->err_code = USART_ERROR_NONE; - SET_BIT(hperh->state, USART_STATE_RX_MASK); - - hperh->rx_size = size; - hperh->rx_count = size; - - while (hperh->rx_count-- > 0) - { - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - if (hperh->init.parity == USART_PARITY_NONE) - { - *(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - buf += 2; - } - else - { - *buf = (uint8_t)(hperh->perh->DATA & 0xFF); - buf += 1; - } - } - else - { - if (hperh->init.parity == USART_PARITY_NONE) - *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - } - - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - __UNLOCK(hperh); - - return OK; + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = USART_ERROR_NONE; + SET_BIT(hperh->state, USART_STATE_RX_MASK); + + hperh->rx_size = size; + hperh->rx_count = size; + + while (hperh->rx_count-- > 0) { + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + if (hperh->init.parity == USART_PARITY_NONE) { + *(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + buf += 2; + } + else { + *buf = (uint8_t)(hperh->perh->DATA & 0xFF); + buf += 1; + } + } + else { + if (hperh->init.parity == USART_PARITY_NONE) + *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + } + + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + __UNLOCK(hperh); + + return OK; } /** @@ -609,24 +592,24 @@ ald_status_t ald_usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, */ ald_status_t ald_usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) - return BUSY; + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL ) || (size == 0)) + return ERROR; - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_TX_MASK); + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_TX_MASK); - hperh->tx_buf = buf; - hperh->rx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + __UNLOCK(hperh); + ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); - return OK; + return OK; } /** @@ -639,26 +622,26 @@ ald_status_t ald_usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t */ ald_status_t ald_usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) - return BUSY; + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL ) || (size == 0)) + return ERROR; - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = USART_ERROR_NONE; + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = USART_ERROR_NONE; - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + __UNLOCK(hperh); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - return OK; + return OK; } /** @@ -671,27 +654,27 @@ ald_status_t ald_usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t */ ald_status_t ald_usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) - return BUSY; + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL ) || (size == 0)) + return ERROR; - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = USART_ERROR_NONE; + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = USART_ERROR_NONE; - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - __frame_mode = 1; + __UNLOCK(hperh); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + __frame_mode = 1; - return OK; + return OK; } #ifdef ALD_DMA @@ -706,54 +689,53 @@ ald_status_t ald_usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uin */ ald_status_t ald_usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_TX_MASK); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - /* Configure callback function */ - hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = usart_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - - /* Configure USART DMA transmit */ - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) - { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmatx); - - __UNLOCK(hperh); - ald_usart_clear_flag_status(hperh, USART_FLAG_TC); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - - return OK; + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_TX_MASK); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + /* Configure callback function */ + hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = usart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + /* Configure USART DMA transmit */ + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmatx); + + __UNLOCK(hperh); + ald_usart_clear_flag_status(hperh, USART_FLAG_TC); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + + return OK; } /** @@ -769,52 +751,51 @@ ald_status_t ald_usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t */ ald_status_t ald_usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->err_code = USART_ERROR_NONE; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - /* Configure callback function */ - hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = usart_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - /* Configure DMA Receive */ - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; - hperh->hdmarx.config.channel = channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) - { - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmarx); - - __UNLOCK(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - - return OK; + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->err_code = USART_ERROR_NONE; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + /* Configure callback function */ + hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = usart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + /* Configure DMA Receive */ + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; + hperh->hdmarx.config.channel = channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmarx); + + __UNLOCK(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + + return OK; } #endif /** @@ -890,50 +871,45 @@ ald_status_t ald_usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t */ ald_status_t ald_usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX; - - while (hperh->tx_count-- > 0) - { - if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) - { - WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & 0x1FF)); - buf += 2; - } - else - { - WRITE_REG(hperh->perh->DATA, *buf++); - } - } - - if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - - return OK; + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX; + + while (hperh->tx_count-- > 0) { + if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) { + WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & 0x1FF)); + buf += 2; + } + else { + WRITE_REG(hperh->perh->DATA, *buf++); + } + } + + if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + hperh->state = USART_STATE_READY; + __UNLOCK(hperh); + + return OK; } /** @@ -947,71 +923,63 @@ ald_status_t ald_usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t s */ ald_status_t ald_usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_RX; - - while (hperh->rx_count-- > 0) - { - if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF)); - - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.parity == USART_PARITY_NONE) - { - *(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - buf += 2; - } - else - { - *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - } - else - { - WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0xFF)); - - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.parity == USART_PARITY_NONE) - *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - } - - hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - - return OK; + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_RX; + + while (hperh->rx_count-- > 0) { + if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF)); + + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.parity == USART_PARITY_NONE) { + *(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + buf += 2; + } + else { + *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + } + else { + WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0xFF)); + + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.parity == USART_PARITY_NONE) + *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + } + + hperh->state = USART_STATE_READY; + __UNLOCK(hperh); + + return OK; } /** @@ -1026,83 +994,73 @@ ald_status_t ald_usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t s */ ald_status_t ald_usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) { - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_RX; - - while (hperh->tx_count-- > 0) - { - --hperh->rx_count; - - if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - if (hperh->init.parity == USART_PARITY_NONE) - { - WRITE_REG(hperh->perh->DATA, (*(uint16_t *)tx_buf & 0x1FF)); - tx_buf += 2; - } - else - { - WRITE_REG(hperh->perh->DATA, *tx_buf++); - } - - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.parity == USART_PARITY_NONE) - { - *(uint16_t *)rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - rx_buf += 2; - } - else - { - *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - } - else - { - WRITE_REG(hperh->perh->DATA, *tx_buf++); - - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) - { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.parity == USART_PARITY_NONE) - *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - } - - hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - - return OK; + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_RX; + + while (hperh->tx_count-- > 0) { + --hperh->rx_count; + + if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + if (hperh->init.parity == USART_PARITY_NONE) { + WRITE_REG(hperh->perh->DATA, (*(uint16_t *)tx_buf & 0x1FF)); + tx_buf += 2; + } + else { + WRITE_REG(hperh->perh->DATA, *tx_buf++); + } + + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.parity == USART_PARITY_NONE) { + *(uint16_t *)rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + rx_buf += 2; + } + else { + *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + } + else { + WRITE_REG(hperh->perh->DATA, *tx_buf++); + + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.parity == USART_PARITY_NONE) + *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + } + + hperh->state = USART_STATE_READY; + __UNLOCK(hperh); + + return OK; } /** @@ -1116,33 +1074,33 @@ ald_status_t ald_usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, ui */ ald_status_t ald_usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { - if (hperh->state != USART_STATE_READY) - return BUSY; + if (hperh->state != USART_STATE_READY) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL) || (size == 0)) + return ERROR; - __LOCK(hperh); + __LOCK(hperh); - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX; - /* The USART Error Interrupts: (Frame error, Noise error, Overrun error) - * are not managed by the USART transmit process to avoid the overrun interrupt - * when the USART mode is configured for transmit and receive "USART_MODE_TX_RX" - * to benefit for the frame error and noise interrupts the USART mode should be - * configured only for transmit "USART_MODE_TX" - * The __ALD_USART_ENABLE_IT(hperh, USART_IT_ERR) can be used to enable the Frame error, - * Noise error interrupt - */ + /* The USART Error Interrupts: (Frame error, Noise error, Overrun error) + * are not managed by the USART transmit process to avoid the overrun interrupt + * when the USART mode is configured for transmit and receive "USART_MODE_TX_RX" + * to benefit for the frame error and noise interrupts the USART mode should be + * configured only for transmit "USART_MODE_TX" + * The __ALD_USART_ENABLE_IT(hperh, USART_IT_ERR) can be used to enable the Frame error, + * Noise error interrupt + */ - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + __UNLOCK(hperh); + ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); - return OK; + return OK; } /** @@ -1155,27 +1113,27 @@ ald_status_t ald_usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint */ ald_status_t ald_usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { - if (hperh->state != USART_STATE_READY) - return BUSY; + if (hperh->state != USART_STATE_READY) + return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; + if ((buf == NULL) || (size == 0)) + return ERROR; - __LOCK(hperh); + __LOCK(hperh); - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_RX; + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_RX; - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + __UNLOCK(hperh); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & (uint16_t)0x01FF)); - return OK; + WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & (uint16_t)0x01FF)); + return OK; } /** @@ -1189,30 +1147,30 @@ ald_status_t ald_usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint */ ald_status_t ald_usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) { - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX_RX; - - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); - - return OK; + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX_RX; + + __UNLOCK(hperh); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + + return OK; } #ifdef ALD_DMA @@ -1227,54 +1185,53 @@ ald_status_t ald_usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_b */ ald_status_t ald_usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - /* Configure callback function */ - hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = usart_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - - /* Configure DMA transmit */ - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) - { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmatx); - - __UNLOCK(hperh); - ald_usart_clear_flag_status(hperh, USART_FLAG_TC); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - - return OK; + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + /* Configure callback function */ + hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = usart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + /* Configure DMA transmit */ + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmatx); + + __UNLOCK(hperh); + ald_usart_clear_flag_status(hperh, USART_FLAG_TC); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + + return OK; } /** @@ -1291,82 +1248,79 @@ ald_status_t ald_usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uin */ ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) { - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_RX; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - /* Configure DMA callback function */ - hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = usart_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - /* Configure DMA receive*/ - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; - hperh->hdmarx.config.channel = rx_channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) - { - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmarx); - - /* Enable the USART transmit DMA channel: the transmit channel is used in order - * to generate in the non-blocking mode the clock to the slave device, - * this mode isn't a simplex receive mode but a full-duplex receive one - */ - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = tx_channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) - { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmatx); - - USART_CLEAR_OREFLAG(hperh); - __UNLOCK(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - - return OK; + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_RX; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + /* Configure DMA callback function */ + hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = usart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + /* Configure DMA receive*/ + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; + hperh->hdmarx.config.channel = rx_channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmarx); + + /* Enable the USART transmit DMA channel: the transmit channel is used in order + * to generate in the non-blocking mode the clock to the slave device, + * this mode isn't a simplex receive mode but a full-duplex receive one + */ + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = tx_channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmatx); + + USART_CLEAR_OREFLAG(hperh); + __UNLOCK(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + + return OK; } /** @@ -1382,86 +1336,83 @@ ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uin * @retval Status, see @ref ald_status_t. */ ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, - uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) + uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) { - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX_RX; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - /* Configure DMA callback function */ - hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = usart_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - hperh->hdmarx.err_cbk = usart_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - /* Configure DMA receive */ - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)rx_buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; - hperh->hdmarx.config.channel = rx_channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) - { - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmarx); - - /* Configure DMA transmit*/ - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)tx_buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = tx_channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) - { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmatx); - - ald_usart_clear_flag_status(hperh, USART_FLAG_TC); - USART_CLEAR_OREFLAG(hperh); - __UNLOCK(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - - return OK; + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX_RX; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + /* Configure DMA callback function */ + hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = usart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + hperh->hdmarx.err_cbk = usart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + /* Configure DMA receive */ + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)rx_buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; + hperh->hdmarx.config.channel = rx_channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmarx); + + /* Configure DMA transmit*/ + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)tx_buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = tx_channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + ald_dma_config_basic(&hperh->hdmatx); + + ald_usart_clear_flag_status(hperh, USART_FLAG_TC); + USART_CLEAR_OREFLAG(hperh); + __UNLOCK(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + + return OK; } #endif /** @@ -1481,29 +1432,25 @@ ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_ */ ald_status_t ald_usart_dma_pause(usart_handle_t *hperh) { - __LOCK(hperh); - - if (hperh->state == USART_STATE_BUSY_TX) - { - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - } - else if (hperh->state == USART_STATE_BUSY_RX) - { - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - } - else if (hperh->state == USART_STATE_BUSY_TX_RX) - { - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - } - else - { - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); - return OK; + __LOCK(hperh); + + if (hperh->state == USART_STATE_BUSY_TX) { + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + } + else if (hperh->state == USART_STATE_BUSY_RX) { + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + } + else if (hperh->state == USART_STATE_BUSY_TX_RX) { + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + } + else { + __UNLOCK(hperh); + return ERROR; + } + + __UNLOCK(hperh); + return OK; } /** @@ -1514,31 +1461,27 @@ ald_status_t ald_usart_dma_pause(usart_handle_t *hperh) */ ald_status_t ald_usart_dma_resume(usart_handle_t *hperh) { - __LOCK(hperh); - - if (hperh->state == USART_STATE_BUSY_TX) - { - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - } - else if (hperh->state == USART_STATE_BUSY_RX) - { - USART_CLEAR_OREFLAG(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - } - else if (hperh->state == USART_STATE_BUSY_TX_RX) - { - USART_CLEAR_OREFLAG(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - } - else - { - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); - return OK; + __LOCK(hperh); + + if (hperh->state == USART_STATE_BUSY_TX) { + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + } + else if (hperh->state == USART_STATE_BUSY_RX) { + USART_CLEAR_OREFLAG(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + } + else if (hperh->state == USART_STATE_BUSY_TX_RX) { + USART_CLEAR_OREFLAG(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + } + else { + __UNLOCK(hperh); + return ERROR; + } + + __UNLOCK(hperh); + return OK; } /** @@ -1549,11 +1492,11 @@ ald_status_t ald_usart_dma_resume(usart_handle_t *hperh) */ ald_status_t ald_usart_dma_stop(usart_handle_t *hperh) { - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - hperh->state = USART_STATE_READY; - return OK; + hperh->state = USART_STATE_READY; + return OK; } #endif /** @@ -1564,102 +1507,87 @@ ald_status_t ald_usart_dma_stop(usart_handle_t *hperh) */ void ald_usart_irq_handler(usart_handle_t *hperh) { - uint32_t flag; - uint32_t source; - - /* Handle parity error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_PE); - source = ald_usart_get_it_status(hperh, USART_IT_PE); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= USART_ERROR_PE; - - /* Handle frame error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_FE); - source = ald_usart_get_it_status(hperh, USART_IT_ERR); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= USART_ERROR_FE; - - /* Handle noise error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_NE); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= USART_ERROR_NE; - - /* Handle overrun error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_ORE); - - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= USART_ERROR_ORE; - - /* Handle idle error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_IDLE); - source = ald_usart_get_it_status(hperh, USART_IT_IDLE); - - if ((flag != RESET) && (source != RESET)) - __usart_recv_frame_cplt(hperh); - - /* Handle asynchronous */ - if (READ_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK) == 0) - { - /* Receiver */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE); - source = ald_usart_get_it_status(hperh, USART_IT_RXNE); - - if ((flag != RESET) && (source != RESET)) - __usart_recv_by_it(hperh); - - /* Transmitter */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE); - source = ald_usart_get_it_status(hperh, USART_IT_TXE); - - if ((flag != RESET) && (source != RESET)) - __usart_send_by_it(hperh); - } - else /* Handle synchronous */ - { - /* Receiver */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE); - source = ald_usart_get_it_status(hperh, USART_IT_RXNE); - - if ((flag != RESET) && (source != RESET)) - { - if (hperh->state == USART_STATE_BUSY_RX) - __usart_recv_by_it_sync(hperh); - else - __usart_send_recv_by_it_sync(hperh); - } - - /* Transmitter */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE); - source = ald_usart_get_it_status(hperh, USART_IT_TXE); - - if ((flag != RESET) && (source != RESET)) - { - if (hperh->state == USART_STATE_BUSY_TX) - __usart_send_by_it(hperh); - else - __usart_send_recv_by_it_sync(hperh); - } - } - - /* Handle transmitter end */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_TC); - source = ald_usart_get_it_status(hperh, USART_IT_TC); - - if ((flag != RESET) && (source != RESET)) - __usart_end_send_by_it(hperh); - - /* Handle error */ - if (hperh->err_code != USART_ERROR_NONE) - { - USART_CLEAR_PEFLAG(hperh); - hperh->state = USART_STATE_READY; - - if (hperh->error_cbk != NULL) - hperh->error_cbk(hperh); - } + uint32_t flag; + uint32_t source; + + /* Handle parity error */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_PE); + source = ald_usart_get_it_status(hperh, USART_IT_PE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= USART_ERROR_PE; + + /* Handle frame error */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_FE); + source = ald_usart_get_it_status(hperh, USART_IT_ERR); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= USART_ERROR_FE; + + /* Handle noise error */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_NE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= USART_ERROR_NE; + + /* Handle overrun error */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_ORE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= USART_ERROR_ORE; + + /* Handle idle error */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_IDLE); + source = ald_usart_get_it_status(hperh, USART_IT_IDLE); + if ((flag != RESET) && (source != RESET)) + __usart_recv_frame_cplt(hperh); + + /* Handle asynchronous */ + if (READ_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK) == 0) { + /* Receiver */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE); + source = ald_usart_get_it_status(hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) + __usart_recv_by_it(hperh); + + /* Transmitter */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE); + source = ald_usart_get_it_status(hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) + __usart_send_by_it(hperh); + } + else { /* Handle synchronous */ + /* Receiver */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE); + source = ald_usart_get_it_status(hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) { + if (hperh->state == USART_STATE_BUSY_RX) + __usart_recv_by_it_sync(hperh); + else + __usart_send_recv_by_it_sync(hperh); + } + + /* Transmitter */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE); + source = ald_usart_get_it_status(hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) { + if (hperh->state == USART_STATE_BUSY_TX) + __usart_send_by_it(hperh); + else + __usart_send_recv_by_it_sync(hperh); + } + } + + /* Handle transmitter end */ + flag = ald_usart_get_flag_status(hperh, USART_FLAG_TC); + source = ald_usart_get_it_status(hperh, USART_IT_TC); + if ((flag != RESET) && (source != RESET)) + __usart_end_send_by_it(hperh); + + /* Handle error */ + if (hperh->err_code != USART_ERROR_NONE) { + USART_CLEAR_PEFLAG(hperh); + hperh->state = USART_STATE_READY; + + if (hperh->error_cbk != NULL) + hperh->error_cbk(hperh); + } } /** @@ -1701,16 +1629,16 @@ void ald_usart_irq_handler(usart_handle_t *hperh) */ ald_status_t ald_usart_multi_processor_enter_mute_mode(usart_handle_t *hperh) { - assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART(hperh->perh)); - __LOCK(hperh); + __LOCK(hperh); - hperh->state = USART_STATE_BUSY; - SET_BIT(hperh->perh->CON0, USART_CON0_RXWK_MSK); - hperh->state = USART_STATE_READY; + hperh->state = USART_STATE_BUSY; + SET_BIT(hperh->perh->CON0, USART_CON0_RXWK_MSK); + hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - return OK; + __UNLOCK(hperh); + return OK; } /** @@ -1721,16 +1649,16 @@ ald_status_t ald_usart_multi_processor_enter_mute_mode(usart_handle_t *hperh) */ ald_status_t ald_usart_multi_processor_exit_mute_mode(usart_handle_t *hperh) { - assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART(hperh->perh)); - __LOCK(hperh); + __LOCK(hperh); - hperh->state = USART_STATE_BUSY; - CLEAR_BIT(hperh->perh->CON0, USART_CON0_RXWK_MSK); - hperh->state = USART_STATE_READY; + hperh->state = USART_STATE_BUSY; + CLEAR_BIT(hperh->perh->CON0, USART_CON0_RXWK_MSK); + hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - return OK; + __UNLOCK(hperh); + return OK; } /** @@ -1741,15 +1669,15 @@ ald_status_t ald_usart_multi_processor_exit_mute_mode(usart_handle_t *hperh) */ ald_status_t ald_usart_half_duplex_enable_send(usart_handle_t *hperh) { - __LOCK(hperh); + __LOCK(hperh); - hperh->state = USART_STATE_BUSY; - SET_BIT(hperh->perh->CON0, USART_CON0_RXEN_MSK); - SET_BIT(hperh->perh->CON0, USART_CON0_TXEN_MSK); - hperh->state = USART_STATE_READY; + hperh->state = USART_STATE_BUSY; + SET_BIT(hperh->perh->CON0, USART_CON0_RXEN_MSK); + SET_BIT(hperh->perh->CON0, USART_CON0_TXEN_MSK); + hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - return OK; + __UNLOCK(hperh); + return OK; } /** @@ -1760,15 +1688,15 @@ ald_status_t ald_usart_half_duplex_enable_send(usart_handle_t *hperh) */ ald_status_t ald_usart_half_duplex_enable_recv(usart_handle_t *hperh) { - __LOCK(hperh); + __LOCK(hperh); - hperh->state = USART_STATE_BUSY; - SET_BIT(hperh->perh->CON0, USART_CON0_RXEN_MSK); - SET_BIT(hperh->perh->CON0, USART_CON0_TXEN_MSK); - hperh->state = USART_STATE_READY; + hperh->state = USART_STATE_BUSY; + SET_BIT(hperh->perh->CON0, USART_CON0_RXEN_MSK); + SET_BIT(hperh->perh->CON0, USART_CON0_TXEN_MSK); + hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - return OK; + __UNLOCK(hperh); + return OK; } /** @@ -1785,16 +1713,16 @@ ald_status_t ald_usart_half_duplex_enable_recv(usart_handle_t *hperh) */ void ald_usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state) { - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_DMAREQ(req)); - assert_param(IS_FUNC_STATE(state)); + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_DMAREQ(req)); + assert_param(IS_FUNC_STATE(state)); - if (state != DISABLE) - SET_BIT(hperh->perh->CON2, req); - else - CLEAR_BIT(hperh->perh->CON2, req); + if (state != DISABLE) + SET_BIT(hperh->perh->CON2, req); + else + CLEAR_BIT(hperh->perh->CON2, req); - return; + return; } /** @@ -1818,39 +1746,37 @@ void ald_usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_f */ void ald_usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state) { - uint8_t idx; - - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_CONFIG_IT(it)); - assert_param(IS_FUNC_STATE(state)); - - idx = (it >> 16) & 0x7; - it &= 0xFFFF; - - if (state) - { - if (idx == 1) - SET_BIT(hperh->perh->CON0, it); - else if (idx == 2) - SET_BIT(hperh->perh->CON1, it); - else if (idx == 4) - SET_BIT(hperh->perh->CON2, it); - else - ; - } - else - { - if (idx == 1) - CLEAR_BIT(hperh->perh->CON0, it); - else if (idx == 2) - CLEAR_BIT(hperh->perh->CON1, it); - else if (idx == 4) - CLEAR_BIT(hperh->perh->CON2, it); - else - ; - } - - return; + uint8_t idx; + + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_CONFIG_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + idx = (it >> 16) & 0x7; + it &= 0xFFFF; + + if (state) { + if (idx == 1) + SET_BIT(hperh->perh->CON0, it); + else if (idx == 2) + SET_BIT(hperh->perh->CON1, it); + else if (idx == 4) + SET_BIT(hperh->perh->CON2, it); + else + ; + } + else { + if (idx == 1) + CLEAR_BIT(hperh->perh->CON0, it); + else if (idx == 2) + CLEAR_BIT(hperh->perh->CON1, it); + else if (idx == 4) + CLEAR_BIT(hperh->perh->CON2, it); + else + ; + } + + return; } /** @brief Check whether the specified USART flag is set or not. @@ -1864,15 +1790,15 @@ void ald_usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_ */ flag_status_t ald_usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag) { - flag_status_t status = RESET; + flag_status_t status = RESET; - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_FLAG(flag)); + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_FLAG(flag)); - if (READ_BIT(hperh->perh->STAT, flag)) - status = SET; + if (READ_BIT(hperh->perh->STAT, flag)) + status = SET; - return status; + return status; } /** @brief Clear the specified USART pending flags. @@ -1894,10 +1820,10 @@ flag_status_t ald_usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag */ void ald_usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag) { - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_CLEAR_FLAG(flag)); + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_CLEAR_FLAG(flag)); - CLEAR_BIT(hperh->perh->STAT, flag); + CLEAR_BIT(hperh->perh->STAT, flag); } /** @@ -1922,42 +1848,37 @@ void ald_usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag) */ it_status_t ald_usart_get_it_status(usart_handle_t *hperh, usart_it_t it) { - uint8_t idx; - it_status_t status = RESET; - - /* Check the parameters */ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_GET_IT(it)); - - idx = (it >> 16) & 0x7; - it &= 0xFFFF; - - if (idx == 0) - { - if (READ_BIT(hperh->perh->STAT, it)) - status = SET; - } - else if (idx == 1) - { - if (READ_BIT(hperh->perh->CON0, it)) - status = SET; - } - else if (idx == 2) - { - if (READ_BIT(hperh->perh->CON1, it)) - status = SET; - } - else if (idx == 4) - { - if (READ_BIT(hperh->perh->CON2, it)) - status = SET; - } - else - { - /* do nothing */ - } - - return status; + uint8_t idx; + it_status_t status = RESET; + + /* Check the parameters */ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_GET_IT(it)); + + idx = (it >> 16) & 0x7; + it &= 0xFFFF; + + if (idx == 0) { + if (READ_BIT(hperh->perh->STAT, it)) + status = SET; + } + else if (idx == 1) { + if (READ_BIT(hperh->perh->CON0, it)) + status = SET; + } + else if (idx == 2) { + if (READ_BIT(hperh->perh->CON1, it)) + status = SET; + } + else if (idx == 4) { + if (READ_BIT(hperh->perh->CON2, it)) + status = SET; + } + else { + /* do nothing */ + } + + return status; } /** @@ -1990,7 +1911,7 @@ it_status_t ald_usart_get_it_status(usart_handle_t *hperh, usart_it_t it) */ usart_state_t ald_usart_get_state(usart_handle_t *hperh) { - return hperh->state; + return hperh->state; } /** @@ -2001,7 +1922,7 @@ usart_state_t ald_usart_get_state(usart_handle_t *hperh) */ uint32_t ald_usart_get_error(usart_handle_t *hperh) { - return hperh->err_code; + return hperh->err_code; } /** @@ -2025,11 +1946,11 @@ uint32_t ald_usart_get_error(usart_handle_t *hperh) */ static void usart_dma_send_cplt(void *arg) { - usart_handle_t *hperh = (usart_handle_t *)arg; + usart_handle_t *hperh = (usart_handle_t *)arg; - hperh->tx_count = 0; - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE); + hperh->tx_count = 0; + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE); } /** @@ -2040,14 +1961,14 @@ static void usart_dma_send_cplt(void *arg) */ static void usart_dma_recv_cplt(void *arg) { - usart_handle_t *hperh = (usart_handle_t *)arg; + usart_handle_t *hperh = (usart_handle_t *)arg; - hperh->rx_count = 0; - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + hperh->rx_count = 0; + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - if (hperh->rx_cplt_cbk != NULL) - hperh->rx_cplt_cbk(hperh); + if (hperh->rx_cplt_cbk != NULL) + hperh->rx_cplt_cbk(hperh); } /** @@ -2058,18 +1979,18 @@ static void usart_dma_recv_cplt(void *arg) */ static void usart_dma_error(void *arg) { - usart_handle_t *hperh = (usart_handle_t *)arg; + usart_handle_t *hperh = (usart_handle_t *)arg; - hperh->rx_count = 0; - hperh->tx_count = 0; - hperh->state = USART_STATE_READY; - hperh->err_code |= USART_ERROR_DMA; + hperh->rx_count = 0; + hperh->tx_count = 0; + hperh->state = USART_STATE_READY; + hperh->err_code |= USART_ERROR_DMA; - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - if (hperh->error_cbk != NULL) - hperh->error_cbk(hperh); + if (hperh->error_cbk != NULL) + hperh->error_cbk(hperh); } #endif /** @@ -2083,27 +2004,25 @@ static void usart_dma_error(void *arg) */ static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout) { - uint32_t tick; + uint32_t tick; - if (timeout == 0) - return OK; + if (timeout == 0) + return OK; - tick = ald_get_tick(); + tick = ald_get_tick(); - while ((ald_usart_get_flag_status(hperh, flag)) != status) - { - if (((ald_get_tick()) - tick) > timeout) - { - ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + while ((ald_usart_get_flag_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) { + ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - return TIMEOUT; - } - } + return TIMEOUT; + } + } - return OK; + return OK; } /** @@ -2114,26 +2033,23 @@ static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, fl */ static ald_status_t __usart_send_by_it(usart_handle_t *hperh) { - if ((hperh->state != USART_STATE_BUSY_TX) && (hperh->state != USART_STATE_BUSY_TX_RX)) - return BUSY; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) - { - WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & (uint16_t)0x01FF)); - hperh->tx_buf += 2; - } - else - { - WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); - } - - if (--hperh->tx_count == 0) - { - ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE); - } - - return OK; + if ((hperh->state != USART_STATE_BUSY_TX) && (hperh->state != USART_STATE_BUSY_TX_RX)) + return BUSY; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) { + WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & (uint16_t)0x01FF)); + hperh->tx_buf += 2; + } + else { + WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); + } + + if (--hperh->tx_count == 0) { + ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE); + } + + return OK; } @@ -2145,13 +2061,13 @@ static ald_status_t __usart_send_by_it(usart_handle_t *hperh) */ static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh) { - ald_usart_interrupt_config(hperh, USART_IT_TC, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); + ald_usart_interrupt_config(hperh, USART_IT_TC, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); - if (hperh->tx_cplt_cbk != NULL) - hperh->tx_cplt_cbk(hperh); + if (hperh->tx_cplt_cbk != NULL) + hperh->tx_cplt_cbk(hperh); - return OK; + return OK; } /** @@ -2162,49 +2078,43 @@ static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh) */ static ald_status_t __usart_recv_by_it(usart_handle_t *hperh) { - if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX)) - return BUSY; - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - if (hperh->init.parity == USART_PARITY_NONE) - { - *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & (uint16_t)0x01FF); - hperh->rx_buf += 2; - } - else - { - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - } - else - { - if (hperh->init.parity == USART_PARITY_NONE) - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - - if (__frame_mode && ((ald_usart_get_it_status(hperh, USART_IT_IDLE)) == RESET)) - ald_usart_interrupt_config(hperh, USART_IT_IDLE, ENABLE); - - if (--hperh->rx_count == 0) - { - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - __frame_mode = 0; - - if (hperh->state == USART_STATE_READY) - { - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - } - - if (hperh->rx_cplt_cbk != NULL) - hperh->rx_cplt_cbk(hperh); - } - - return OK; + if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX)) + return BUSY; + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + if (hperh->init.parity == USART_PARITY_NONE) { + *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & (uint16_t)0x01FF); + hperh->rx_buf += 2; + } + else { + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + } + else { + if (hperh->init.parity == USART_PARITY_NONE) + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + + if (__frame_mode && ((ald_usart_get_it_status(hperh, USART_IT_IDLE)) == RESET)) + ald_usart_interrupt_config(hperh, USART_IT_IDLE, ENABLE); + + if (--hperh->rx_count == 0) { + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + __frame_mode = 0; + + if (hperh->state == USART_STATE_READY) { + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + } + + if (hperh->rx_cplt_cbk != NULL) + hperh->rx_cplt_cbk(hperh); + } + + return OK; } /** @@ -2215,26 +2125,25 @@ static ald_status_t __usart_recv_by_it(usart_handle_t *hperh) */ static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh) { - if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX)) - return BUSY; + if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX)) + return BUSY; - ald_usart_interrupt_config(hperh, USART_IT_IDLE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + ald_usart_interrupt_config(hperh, USART_IT_IDLE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - __frame_mode = 0; - hperh->rx_size -= hperh->rx_count; + __frame_mode = 0; + hperh->rx_size -= hperh->rx_count; - if (hperh->state == USART_STATE_READY) - { - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - } + if (hperh->state == USART_STATE_READY) { + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + } - if (hperh->rx_cplt_cbk != NULL) - hperh->rx_cplt_cbk(hperh); + if (hperh->rx_cplt_cbk != NULL) + hperh->rx_cplt_cbk(hperh); - return OK; + return OK; } @@ -2247,48 +2156,43 @@ static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh) */ static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh) { - if (hperh->state != USART_STATE_BUSY_RX) - return BUSY; - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - - if (hperh->init.parity == USART_PARITY_NONE) - { - *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - hperh->rx_buf += 2; - } - else - { - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - - if (--hperh->rx_count != 0x00) - WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF)); - } - else - { - if (hperh->init.parity == USART_PARITY_NONE) - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - - if (--hperh->rx_count != 0x00) - hperh->perh->DATA = (DUMMY_DATA & 0xFF); - } - - if (hperh->rx_count == 0) - { - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - hperh->state = USART_STATE_READY; - - if (hperh->rx_cplt_cbk != NULL) - hperh->rx_cplt_cbk(hperh); - } - - return OK; + if (hperh->state != USART_STATE_BUSY_RX) + return BUSY; + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + + if (hperh->init.parity == USART_PARITY_NONE) { + *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + hperh->rx_buf += 2; + } + else { + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + + if (--hperh->rx_count != 0x00) + WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF)); + } + else { + if (hperh->init.parity == USART_PARITY_NONE) + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + + if (--hperh->rx_count != 0x00) + hperh->perh->DATA = (DUMMY_DATA & 0xFF); + } + + if (hperh->rx_count == 0) { + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + hperh->state = USART_STATE_READY; + + if (hperh->rx_cplt_cbk != NULL) + hperh->rx_cplt_cbk(hperh); + } + + return OK; } /** @@ -2299,76 +2203,63 @@ static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh) */ static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh) { - if (hperh->state != USART_STATE_BUSY_TX_RX) - return BUSY; - - if (hperh->tx_count != 0) - { - if (ald_usart_get_flag_status(hperh, USART_FLAG_TXE) != RESET) - { - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - if (hperh->init.parity == USART_PARITY_NONE) - { - WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & 0x1FF)); - hperh->tx_buf += 2; - } - else - { - WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); - } - } - else - { - WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); - } - - if (--hperh->tx_count == 0) - ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); - } - } - - if (hperh->rx_count != 0) - { - if (ald_usart_get_flag_status(hperh, USART_FLAG_RXNE) != RESET) - { - if (hperh->init.word_length == USART_WORD_LENGTH_9B) - { - if (hperh->init.parity == USART_PARITY_NONE) - { - *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - hperh->rx_buf += 2; - } - else - { - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - } - else - { - if (hperh->init.parity == USART_PARITY_NONE) - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - - --hperh->rx_count; - } - } - - if (hperh->rx_count == 0) - { - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - - hperh->state = USART_STATE_READY; - - if (hperh->tx_rx_cplt_cbk != NULL) - hperh->tx_rx_cplt_cbk(hperh); - } - - return OK; + if (hperh->state != USART_STATE_BUSY_TX_RX) + return BUSY; + + if (hperh->tx_count != 0) { + if (ald_usart_get_flag_status(hperh, USART_FLAG_TXE) != RESET) { + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + if (hperh->init.parity == USART_PARITY_NONE) { + WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & 0x1FF)); + hperh->tx_buf += 2; + } + else { + WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); + } + } + else { + WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); + } + + if (--hperh->tx_count == 0) + ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + } + } + + if (hperh->rx_count != 0) { + if (ald_usart_get_flag_status(hperh, USART_FLAG_RXNE) != RESET) { + if (hperh->init.word_length == USART_WORD_LENGTH_9B) { + if (hperh->init.parity == USART_PARITY_NONE) { + *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + hperh->rx_buf += 2; + } + else { + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + } + else { + if (hperh->init.parity == USART_PARITY_NONE) + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + + --hperh->rx_count; + } + } + + if (hperh->rx_count == 0) { + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + + hperh->state = USART_STATE_READY; + + if (hperh->tx_rx_cplt_cbk != NULL) + hperh->tx_rx_cplt_cbk(hperh); + } + + return OK; } /** @@ -2377,79 +2268,59 @@ static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval None */ -static void usart_set_config(usart_handle_t *hperh) +static void usart_set_config (usart_handle_t *hperh) { - uint32_t tmp; - uint32_t integer; - uint32_t fractional; - - /* Check the parameters */ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_BAUDRATE(hperh->init.baud)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); - assert_param(IS_USART_PARITY(hperh->init.parity)); - assert_param(IS_USART_MODE(hperh->init.mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); - - MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS); - tmp = READ_REG(hperh->perh->CON0); - MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS); - - if (hperh->init.parity == USART_PARITY_NONE) - CLEAR_BIT(tmp, USART_CON0_PEN_MSK); - else - SET_BIT(tmp, USART_CON0_PEN_MSK); - - if (hperh->init.parity == USART_PARITY_ODD) - SET_BIT(tmp, USART_CON0_PSEL_MSK); - else - CLEAR_BIT(tmp, USART_CON0_PSEL_MSK); - - WRITE_REG(hperh->perh->CON0, tmp); - MODIFY_REG(hperh->perh->CON2, USART_CON2_RTSEN_MSK, (hperh->init.fctl & 0x1) << USART_CON2_RTSEN_POS); - MODIFY_REG(hperh->perh->CON2, USART_CON2_CTSEN_MSK, ((hperh->init.fctl >> 1) & 0x1) << USART_CON2_CTSEN_POS); - MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS); - MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS); - - if (hperh->init.over_sampling) - SET_BIT(hperh->perh->CON0, (1 << 15)); - - /* Determine the integer part */ - if (READ_BIT(hperh->perh->CON0, (1 << 15))) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); - } - else - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); - } - - tmp = (integer / 100) << 4; - - /* Determine the fractional part */ - fractional = integer - (100 * (tmp >> 4)); - - /* Implement the fractional part in the register */ - if (READ_BIT(hperh->perh->CON0, (1 << 15))) - tmp |= ((((fractional * 8) + 50) / 100) & ((uint8_t)0x07)); - else - tmp |= ((((fractional * 16) + 50) / 100) & ((uint8_t)0x0F)); - - WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp); - return; + uint32_t tmp; + uint32_t integer; + uint32_t fractional; + + /* Check the parameters */ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_BAUDRATE(hperh->init.baud)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_USART_PARITY(hperh->init.parity)); + assert_param(IS_USART_MODE(hperh->init.mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); + + MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS); + tmp = READ_REG(hperh->perh->CON0); + MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS); + + if (hperh->init.parity == USART_PARITY_NONE) + CLEAR_BIT(tmp, USART_CON0_PEN_MSK); + else + SET_BIT(tmp, USART_CON0_PEN_MSK); + + if (hperh->init.parity == USART_PARITY_ODD) + SET_BIT(tmp, USART_CON0_PSEL_MSK); + else + CLEAR_BIT(tmp, USART_CON0_PSEL_MSK); + + WRITE_REG(hperh->perh->CON0, tmp); + MODIFY_REG(hperh->perh->CON2, USART_CON2_RTSEN_MSK, (hperh->init.fctl & 0x1) << USART_CON2_RTSEN_POS); + MODIFY_REG(hperh->perh->CON2, USART_CON2_CTSEN_MSK, ((hperh->init.fctl >> 1) & 0x1) << USART_CON2_CTSEN_POS); + MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS); + MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS); + + /* Determine the integer part */ + integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); + tmp = (integer / 100) << 4; + + /* Determine the fractional part */ + fractional = integer - (100 * (tmp >> 4)); + tmp |= ((((fractional * 16) + 50) / 100) & ((uint8_t)0x0F)); + WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp); + + return; } /** * @} */ - #endif /* ALD_USART */ /** * @} */ - /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c index acf092a2788b3ff79ca0e9ede781eeb8985f1077..d19a0397abb031fdf8ba01842863540051966999 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c @@ -46,18 +46,18 @@ */ void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt) { - assert_param(IS_WWDT_WIN_TYPE(win)); - assert_param(IS_FUNC_STATE(interrupt)); - - WWDT_UNLOCK(); - WRITE_REG(WWDT->LOAD, load); - MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS); - SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK); - SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK); - MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS); - WWDT_LOCK(); - - return; + assert_param(IS_WWDT_WIN_TYPE(win)); + assert_param(IS_FUNC_STATE(interrupt)); + + WWDT_UNLOCK(); + WRITE_REG(WWDT->LOAD, load); + MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS); + SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK); + SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK); + MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS); + WWDT_LOCK(); + + return; } /** @@ -66,11 +66,11 @@ void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt) */ void ald_wwdt_start(void) { - WWDT_UNLOCK(); - SET_BIT(WWDT->CON, WWDT_CON_EN_MSK); - WWDT_LOCK(); + WWDT_UNLOCK(); + SET_BIT(WWDT->CON, WWDT_CON_EN_MSK); + WWDT_LOCK(); - return; + return; } /** @@ -79,7 +79,7 @@ void ald_wwdt_start(void) */ uint32_t ald_wwdt_get_value(void) { - return WWDT->VALUE; + return WWDT->VALUE; } /** @@ -88,10 +88,10 @@ uint32_t ald_wwdt_get_value(void) */ it_status_t ald_wwdt_get_flag_status(void) { - if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK)) - return SET; + if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK)) + return SET; - return RESET; + return RESET; } /** @@ -100,8 +100,8 @@ it_status_t ald_wwdt_get_flag_status(void) */ void ald_wwdt_clear_flag_status(void) { - WRITE_REG(WWDT->INTCLR, 1); - return; + WRITE_REG(WWDT->INTCLR, 1); + return; } /** @@ -110,11 +110,11 @@ void ald_wwdt_clear_flag_status(void) */ void ald_wwdt_feed_dog(void) { - WWDT_UNLOCK(); - WRITE_REG(WWDT->INTCLR, 0x1); - WWDT_LOCK(); + WWDT_UNLOCK(); + WRITE_REG(WWDT->INTCLR, 0x1); + WWDT_LOCK(); - return; + return; } /** * @} @@ -132,16 +132,16 @@ void ald_wwdt_feed_dog(void) */ void ald_iwdt_init(uint32_t load, type_func_t interrupt) { - assert_param(IS_FUNC_STATE(interrupt)); + assert_param(IS_FUNC_STATE(interrupt)); - IWDT_UNLOCK(); - WRITE_REG(IWDT->LOAD, load); - SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK); - SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK); - MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS); - IWDT_LOCK(); + IWDT_UNLOCK(); + WRITE_REG(IWDT->LOAD, load); + SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK); + SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK); + MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS); + IWDT_LOCK(); - return; + return; } /** @@ -150,11 +150,11 @@ void ald_iwdt_init(uint32_t load, type_func_t interrupt) */ void ald_iwdt_start(void) { - IWDT_UNLOCK(); - SET_BIT(IWDT->CON, IWDT_CON_EN_MSK); - IWDT_LOCK(); + IWDT_UNLOCK(); + SET_BIT(IWDT->CON, IWDT_CON_EN_MSK); + IWDT_LOCK(); - return; + return; } /** @@ -163,7 +163,7 @@ void ald_iwdt_start(void) */ uint32_t ald_iwdt_get_value(void) { - return IWDT->VALUE; + return IWDT->VALUE; } /** @@ -172,10 +172,10 @@ uint32_t ald_iwdt_get_value(void) */ it_status_t ald_iwdt_get_flag_status(void) { - if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK)) - return SET; + if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK)) + return SET; - return RESET; + return RESET; } /** @@ -184,8 +184,8 @@ it_status_t ald_iwdt_get_flag_status(void) */ void ald_iwdt_clear_flag_status(void) { - WRITE_REG(IWDT->INTCLR, 1); - return; + WRITE_REG(IWDT->INTCLR, 1); + return; } /** @@ -194,11 +194,11 @@ void ald_iwdt_clear_flag_status(void) */ void ald_iwdt_feed_dog(void) { - IWDT_UNLOCK(); - WRITE_REG(IWDT->INTCLR, 1); - IWDT_LOCK(); + IWDT_UNLOCK(); + WRITE_REG(IWDT->INTCLR, 1); + IWDT_LOCK(); - return; + return; } /** * @} diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c index 596bc38fbf686078a559693810e977ca37da7955..e406c53afc91cc9edf514b0fcd85761325f24f7f 100644 --- a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c @@ -14,6 +14,7 @@ ********************************************************************************* */ +#include #include "utils.h" #include "ald_dma.h" #include "ald_cmu.h" @@ -42,9 +43,9 @@ #define __ALD_VERSION_SUB2 (0x00) /**< [15:8] sub2 version */ #define __ALD_VERSION_RC (0x00) /**< [7:0] release candidate */ #define __ALD_VERSION ((__ALD_VERSION_MAIN << 24) | \ - (__ALD_VERSION_SUB1 << 16) | \ - (__ALD_VERSION_SUB2 << 8 ) | \ - (__ALD_VERSION_RC)) + (__ALD_VERSION_SUB1 << 16) | \ + (__ALD_VERSION_SUB2 << 8 ) | \ + (__ALD_VERSION_RC)) /** * @} */ @@ -110,12 +111,12 @@ uint32_t __systick_interval = SYSTICK_INTERVAL_1MS; */ void ald_cmu_init(void) { - ald_cmu_clock_config_default(); - ald_tick_init(TICK_INT_PRIORITY); + ald_cmu_clock_config_default(); + ald_tick_init(TICK_INT_PRIORITY); #ifdef ALD_DMA - ald_dma_init(DMA0); + ald_dma_init(DMA0); #endif - return; + return; } /** @@ -134,13 +135,13 @@ void ald_cmu_init(void) */ __weak void ald_tick_init(uint32_t prio) { - /* Configure the SysTick IRQ */ - SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS); + /* Configure the SysTick IRQ */ + SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS); - if (prio != 3) - NVIC_SetPriority(SysTick_IRQn, prio); + if (prio != 3) + NVIC_SetPriority(SysTick_IRQn, prio); - return; + return; } /** @@ -154,15 +155,15 @@ __weak void ald_tick_init(uint32_t prio) */ void ald_systick_interval_select(systick_interval_t value) { - assert_param(IS_SYSTICK_INTERVAL(value)); + assert_param(IS_SYSTICK_INTERVAL(value)); - SysTick_Config(ald_cmu_get_sys_clock() / value); - __systick_interval = value; + SysTick_Config(ald_cmu_get_sys_clock() / value); + __systick_interval = value; - if (TICK_INT_PRIORITY != 3) - NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY); + if (TICK_INT_PRIORITY != 3) + NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY); - return; + return; } /** * @} @@ -185,6 +186,9 @@ void ald_systick_interval_select(systick_interval_t value) (+) Configure the interrupt (+) Provide system tick value (+) Get CPU ID + (+) Get UID + (+) Get CHIPID + @endverbatim * @{ */ @@ -200,7 +204,7 @@ void ald_systick_interval_select(systick_interval_t value) */ __weak void ald_inc_tick_weak(void) { - ++lib_tick; + ++lib_tick; } /** @@ -211,8 +215,8 @@ __weak void ald_inc_tick_weak(void) */ __weak void ald_systick_irq_cbk(void) { - /* do nothing */ - return; + /* do nothing */ + return; } /** @@ -221,10 +225,10 @@ __weak void ald_systick_irq_cbk(void) */ __isr__ void ald_inc_tick(void) { - ald_inc_tick_weak(); - ald_systick_irq_cbk(); + ald_inc_tick_weak(); + ald_systick_irq_cbk(); - return; + return; } /** @@ -235,7 +239,7 @@ __isr__ void ald_inc_tick(void) */ __weak uint32_t ald_get_tick(void) { - return lib_tick; + return lib_tick; } /** @@ -251,36 +255,35 @@ __weak uint32_t ald_get_tick(void) */ __weak void ald_delay_ms(__IO uint32_t delay) { - uint32_t tick, __delay; + uint32_t tick, __delay; - switch (__systick_interval) - { - case SYSTICK_INTERVAL_1MS: - __delay = delay; - break; + switch (__systick_interval) { + case SYSTICK_INTERVAL_1MS: + __delay = delay; + break; - case SYSTICK_INTERVAL_10MS: - __delay = delay / 10; - break; + case SYSTICK_INTERVAL_10MS: + __delay = delay / 10; + break; - case SYSTICK_INTERVAL_100MS: - __delay = delay / 100; - break; + case SYSTICK_INTERVAL_100MS: + __delay = delay / 100; + break; - case SYSTICK_INTERVAL_1000MS: - __delay = delay / 1000; - break; + case SYSTICK_INTERVAL_1000MS: + __delay = delay / 1000; + break; - default: - __delay = delay; - break; - } + default: + __delay = delay; + break; + } - tick = ald_get_tick(); - __delay = __delay == 0 ? 1 : __delay; + tick = ald_get_tick(); + __delay = __delay == 0 ? 1 : __delay; - while ((ald_get_tick() - tick) < __delay) - ; + while ((ald_get_tick() - tick) < __delay) + ; } /** @@ -295,7 +298,7 @@ __weak void ald_delay_ms(__IO uint32_t delay) */ __weak void ald_suspend_tick(void) { - CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } /** @@ -310,7 +313,7 @@ __weak void ald_suspend_tick(void) */ __weak void ald_resume_tick(void) { - SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } /** @@ -319,7 +322,7 @@ __weak void ald_resume_tick(void) */ uint32_t ald_get_ald_version(void) { - return __ALD_VERSION; + return __ALD_VERSION; } /** @@ -332,28 +335,24 @@ uint32_t ald_get_ald_version(void) */ ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout) { - uint32_t tick = ald_get_tick(); - - assert_param(timeout > 0); - - if (status == SET) - { - while (!(IS_BIT_SET(*reg, bit))) - { - if (((ald_get_tick()) - tick) > timeout) - return TIMEOUT; - } - } - else - { - while ((IS_BIT_SET(*reg, bit))) - { - if (((ald_get_tick()) - tick) > timeout) - return TIMEOUT; - } - } - - return OK; + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + if (status == SET) { + while (!(IS_BIT_SET(*reg, bit))) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + else { + while ((IS_BIT_SET(*reg, bit))) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + + return OK; } /** @@ -367,20 +366,18 @@ ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, ui */ void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) { - assert_param(IS_FUNC_STATE(status)); - assert_param(IS_PRIO(prio)); - - if (status == ENABLE) - { - NVIC_SetPriority(irq, prio); - NVIC_EnableIRQ(irq); - } - else - { - NVIC_DisableIRQ(irq); - } - - return; + assert_param(IS_FUNC_STATE(status)); + assert_param(IS_PRIO(prio)); + + if (status == ENABLE) { + NVIC_SetPriority(irq, prio); + NVIC_EnableIRQ(irq); + } + else { + NVIC_DisableIRQ(irq); + } + + return; } /** @@ -389,10 +386,10 @@ void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) */ uint32_t ald_mcu_get_tick(void) { - uint32_t load = SysTick->LOAD; - uint32_t val = SysTick->VAL; + uint32_t load = SysTick->LOAD; + uint32_t val = SysTick->VAL; - return (load - val); + return (load - val); } /** @@ -401,9 +398,31 @@ uint32_t ald_mcu_get_tick(void) */ uint32_t ald_mcu_get_cpu_id(void) { - return SCB->CPUID; + return SCB->CPUID; +} + +/** + * @brief Get the UID. + * @param buf: Pointer to UID, len: 12Bytes(96-bits) + * @retval None + */ +void ald_mcu_get_uid(uint8_t *buf) +{ + memcpy(&buf[0], (void *)MCU_UID0_ADDR, 4); + memcpy(&buf[4], (void *)MCU_UID1_ADDR, 4); + memcpy(&buf[8], (void *)MCU_UID2_ADDR, 4); + + return; } +/** + * @brief Get the CHIPID + * @retval CHPID + */ +uint32_t ald_mcu_get_chipid(void) +{ + return (uint32_t)*(uint32_t *)MCU_CHIPID_ADDR; +} /** * @} */ diff --git a/bsp/essemi/es32f0654/project.uvoptx b/bsp/essemi/es32f0654/project.uvoptx index 8c76d8ba7614b2891571eb854387be1d0b784a76..518e8945f923eb3b9306f9ecd38257458024a46b 100644 --- a/bsp/essemi/es32f0654/project.uvoptx +++ b/bsp/essemi/es32f0654/project.uvoptx @@ -73,7 +73,7 @@ 0 - 0 + 1 0 1 @@ -179,4 +179,948 @@ + + Applications + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + cpu + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + cpuport.c + 0 + 0 + + + 2 + 6 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + context_rvds.S + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\can\can.c + can.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\hwtimer\hwtimer.c + hwtimer.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\i2c\i2c_core.c + i2c_core.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\i2c\i2c_dev.c + i2c_dev.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\i2c\i2c-bit-ops.c + i2c-bit-ops.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\adc.c + adc.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\rt_drv_pwm.c + rt_drv_pwm.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\pm\pm.c + pm.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\rtc\rtc.c + rtc.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\spi\spi_core.c + spi_core.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\spi\spi_dev.c + spi_dev.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 4 + 27 + 1 + 0 + 0 + 0 + drivers\board.c + board.c + 0 + 0 + + + 4 + 28 + 1 + 0 + 0 + 0 + drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 4 + 29 + 1 + 0 + 0 + 0 + drivers\drv_uart.c + drv_uart.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 5 + 32 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 6 + 33 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\src\device.c + device.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 6 + 44 + 1 + 0 + 0 + 0 + ..\..\..\src\signal.c + signal.c + 0 + 0 + + + 6 + 45 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 6 + 46 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 7 + 47 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_acmp.c + ald_acmp.c + 0 + 0 + + + 7 + 48 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_adc.c + ald_adc.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_bkpc.c + ald_bkpc.c + 0 + 0 + + + 7 + 50 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_calc.c + ald_calc.c + 0 + 0 + + + 7 + 51 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_can.c + ald_can.c + 0 + 0 + + + 7 + 52 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_cmu.c + ald_cmu.c + 0 + 0 + + + 7 + 53 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crc.c + ald_crc.c + 0 + 0 + + + 7 + 54 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crypt.c + ald_crypt.c + 0 + 0 + + + 7 + 55 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_dma.c + ald_dma.c + 0 + 0 + + + 7 + 56 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash.c + ald_flash.c + 0 + 0 + + + 7 + 57 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + ald_flash_ext.c + 0 + 0 + + + 7 + 58 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_gpio.c + ald_gpio.c + 0 + 0 + + + 7 + 59 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_i2c.c + ald_i2c.c + 0 + 0 + + + 7 + 60 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_iap.c + ald_iap.c + 0 + 0 + + + 7 + 61 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pis.c + ald_pis.c + 0 + 0 + + + 7 + 62 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pmu.c + ald_pmu.c + 0 + 0 + + + 7 + 63 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rmu.c + ald_rmu.c + 0 + 0 + + + 7 + 64 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rtc.c + ald_rtc.c + 0 + 0 + + + 7 + 65 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_smartcard.c + ald_smartcard.c + 0 + 0 + + + 7 + 66 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_spi.c + ald_spi.c + 0 + 0 + + + 7 + 67 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c + ald_timer.c + 0 + 0 + + + 7 + 68 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c + ald_trng.c + 0 + 0 + + + 7 + 69 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_tsense.c + ald_tsense.c + 0 + 0 + + + 7 + 70 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_uart.c + ald_uart.c + 0 + 0 + + + 7 + 71 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_usart.c + ald_usart.c + 0 + 0 + + + 7 + 72 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_wdt.c + ald_wdt.c + 0 + 0 + + + 7 + 73 + 1 + 0 + 0 + 0 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\utils.c + utils.c + 0 + 0 + + + 7 + 74 + 2 + 0 + 0 + 0 + libraries\CMSIS\Device\EastSoft\ES32F065x\Startup\keil\startup_es32f065x.s + startup_es32f065x.s + 0 + 0 + + + diff --git a/bsp/essemi/es32f0654/project.uvprojx b/bsp/essemi/es32f0654/project.uvprojx index 724ef242af1bedcc7be2d89e261205f5ba19420a..70c93b4c8e48a8b1a31c4fff939b4df497d5a86c 100644 --- a/bsp/essemi/es32f0654/project.uvprojx +++ b/bsp/essemi/es32f0654/project.uvprojx @@ -1,42 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread 0x4 ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC 0 ES32F0654LT Eastsoft - Eastsoft.ES32_DFP.1.0.2 + Eastsoft.ES32_DFP.7.2350 http://www.essemi.com IRAM(0x20000000,0x00008000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0es32f0xx -FS00 -FL040000 -FP0($$Device:ES32F0654LT$Flash\es32f0xx.FLM)) 0 $$Device:ES32F0654LT$Device\Include\es32f0xx.h - - - - - - - - - + + + + + + + + + $$Device:ES32F0654LT$SVD\es32f0xx.svd 0 0 - - - - - + + + + + 0 0 @@ -58,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -68,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -79,14 +83,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -100,8 +104,8 @@ 0 0 3 - - + + 1 @@ -135,10 +139,10 @@ 1 BIN\UL2CM3.DLL "" () - - - - + + + + 0 @@ -171,7 +175,7 @@ 0 0 "Cortex-M0" - + 0 0 0 @@ -180,6 +184,7 @@ 0 0 0 + 0 0 0 8 @@ -303,7 +308,7 @@ 0x0 - + 1 @@ -320,6 +325,7 @@ 0 0 1 + 0 0 1 1 @@ -329,10 +335,10 @@ 0 0 - + ES32F065x - - .;..\..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\ES32F065x\Include;libraries\CMSIS\Include;libraries\ES32F065x_ALD_StdPeriph_Driver\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common + + applications;.;drivers;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;libraries\CMSIS\Device\EastSoft\ES32F065x\Include;libraries\CMSIS\Include;libraries\ES32F065x_ALD_StdPeriph_Driver\Include @@ -347,10 +353,10 @@ 0 0 - - - - + + + + @@ -362,17 +368,271 @@ 0 0x08000000 0x20000000 - - - - - - - + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + cpu + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + can.c + 1 + ..\..\..\components\drivers\can\can.c + + + hwtimer.c + 1 + ..\..\..\components\drivers\hwtimer\hwtimer.c + + + i2c_core.c + 1 + ..\..\..\components\drivers\i2c\i2c_core.c + + + i2c_dev.c + 1 + ..\..\..\components\drivers\i2c\i2c_dev.c + + + i2c-bit-ops.c + 1 + ..\..\..\components\drivers\i2c\i2c-bit-ops.c + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + adc.c + 1 + ..\..\..\components\drivers\misc\adc.c + + + rt_drv_pwm.c + 1 + ..\..\..\components\drivers\misc\rt_drv_pwm.c + + + pm.c + 1 + ..\..\..\components\drivers\pm\pm.c + + + rtc.c + 1 + ..\..\..\components\drivers\rtc\rtc.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + spi_core.c + 1 + ..\..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\..\components\drivers\spi\spi_dev.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + Kernel @@ -381,92 +641,66 @@ 1 ..\..\..\src\clock.c - - components.c 1 ..\..\..\src\components.c - - device.c 1 ..\..\..\src\device.c - - idle.c 1 ..\..\..\src\idle.c - - ipc.c 1 ..\..\..\src\ipc.c - - irq.c 1 ..\..\..\src\irq.c - - kservice.c 1 ..\..\..\src\kservice.c - - mem.c 1 ..\..\..\src\mem.c - - mempool.c 1 ..\..\..\src\mempool.c - - object.c 1 ..\..\..\src\object.c - - scheduler.c 1 ..\..\..\src\scheduler.c - - signal.c 1 ..\..\..\src\signal.c - - thread.c 1 ..\..\..\src\thread.c - - timer.c 1 @@ -474,40 +708,6 @@ - - Applications - - - main.c - 1 - applications\main.c - - - - - Drivers - - - board.c - 1 - drivers\board.c - - - - - drv_gpio.c - 1 - drivers\drv_gpio.c - - - - - drv_uart.c - 1 - drivers\drv_uart.c - - - Libraries @@ -516,190 +716,136 @@ 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_acmp.c - - ald_adc.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_adc.c - - ald_bkpc.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_bkpc.c - - ald_calc.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_calc.c - - ald_can.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_can.c - - ald_cmu.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_cmu.c - - ald_crc.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crc.c - - ald_crypt.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crypt.c - - ald_dma.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_dma.c - - ald_flash.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash.c - - ald_flash_ext.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c - - ald_gpio.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_gpio.c - - ald_i2c.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_i2c.c - - ald_iap.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_iap.c - - ald_pis.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pis.c - - ald_pmu.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pmu.c - - ald_rmu.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rmu.c - - ald_rtc.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rtc.c - - ald_smartcard.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_smartcard.c - - ald_spi.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_spi.c - - ald_timer.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c - - ald_trng.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c - - ald_tsense.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_tsense.c - - ald_uart.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_uart.c - - ald_usart.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_usart.c - - ald_wdt.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_wdt.c - - utils.c 1 libraries\ES32F065x_ALD_StdPeriph_Driver\Source\utils.c - - startup_es32f065x.s 2 @@ -707,140 +853,14 @@ - - cpu - - - backtrace.c - 1 - ..\..\..\libcpu\arm\common\backtrace.c - - - - - div0.c - 1 - ..\..\..\libcpu\arm\common\div0.c - - - - - showmem.c - 1 - ..\..\..\libcpu\arm\common\showmem.c - - - - - cpuport.c - 1 - ..\..\..\libcpu\arm\cortex-m0\cpuport.c - - - - - context_rvds.S - 2 - ..\..\..\libcpu\arm\cortex-m0\context_rvds.S - - - - - DeviceDrivers - - - pin.c - 1 - ..\..\..\components\drivers\misc\pin.c - - - - - serial.c - 1 - ..\..\..\components\drivers\serial\serial.c - - - - - completion.c - 1 - ..\..\..\components\drivers\src\completion.c - - - - - dataqueue.c - 1 - ..\..\..\components\drivers\src\dataqueue.c - - - - - pipe.c - 1 - ..\..\..\components\drivers\src\pipe.c - - - - - ringblk_buf.c - 1 - ..\..\..\components\drivers\src\ringblk_buf.c - - - - - ringbuffer.c - 1 - ..\..\..\components\drivers\src\ringbuffer.c - - - - - waitqueue.c - 1 - ..\..\..\components\drivers\src\waitqueue.c - - - - - workqueue.c - 1 - ..\..\..\components\drivers\src\workqueue.c - - - - - finsh - - - shell.c - 1 - ..\..\..\components\finsh\shell.c - - - - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - - - - - msh.c - 1 - ..\..\..\components\finsh\msh.c - - - + - - - + + + + diff --git a/bsp/essemi/es32f0654/rtconfig.h b/bsp/essemi/es32f0654/rtconfig.h index ab25a2d01bb306cf3e2e58e9be2d2783045171c4..3a173aaa59e533f863e09fbbddb0c6e01ac6d4f8 100644 --- a/bsp/essemi/es32f0654/rtconfig.h +++ b/bsp/essemi/es32f0654/rtconfig.h @@ -7,7 +7,7 @@ /* RT-Thread Kernel */ #define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 100 @@ -39,7 +39,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart2" -#define RT_VER_NUM 0x40002 +#define RT_VER_NUM 0x40003 /* RT-Thread Components */ @@ -76,7 +76,16 @@ #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_CAN +#define RT_USING_HWTIMER +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS #define RT_USING_PIN +#define RT_USING_ADC +#define RT_USING_PWM +#define RT_USING_PM +#define RT_USING_RTC +#define RT_USING_SPI /* Using USB */ @@ -161,6 +170,9 @@ /* I2C Drivers */ +/* CAN Drivers */ + + /* PWM Drivers */ @@ -181,5 +193,7 @@ /* Offboard Peripheral Drivers */ +/* Peripheral Drivers test example */ + #endif diff --git a/bsp/essemi/es32f369x/.config b/bsp/essemi/es32f369x/.config index 1c88a0f6c488ea17c5b82a5aab02238eaadf6a35..af456dc7654e408f692b65d125dae54d3429cf80 100644 --- a/bsp/essemi/es32f369x/.config +++ b/bsp/essemi/es32f369x/.config @@ -114,19 +114,31 @@ CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set +CONFIG_RT_USING_CAN=y +# CONFIG_RT_CAN_USING_HDR is not set +CONFIG_RT_USING_HWTIMER=y # CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_PWM is not set +CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_PWM=y # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_RTC is not set +CONFIG_RT_USING_PM=y +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -265,6 +277,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_AGILE_JSMN is not set # CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set # # security packages @@ -290,6 +304,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -338,6 +353,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MININI is not set # CONFIG_PKG_USING_QBOOT is not set # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -390,6 +406,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_AGILE_CONSOLE is not set # CONFIG_PKG_USING_LD3320 is not set # CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -424,11 +442,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set # CONFIG_PKG_USING_THREES is not set # CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set CONFIG_SOC_ES32F3696LT=y # @@ -490,6 +511,11 @@ CONFIG_BSP_USING_UART0=y # CONFIG_BSP_USING_PWM0 is not set # CONFIG_BSP_USING_PWM1 is not set +# +# PM Drivers +# +# CONFIG_BSP_USING_PM is not set + # # Onboard Peripheral Drivers # @@ -497,3 +523,18 @@ CONFIG_BSP_USING_UART0=y # # Offboard Peripheral Drivers # + +# +# Peripheral Drivers test example +# +# CONFIG_BSP_USING_EXAMPLE_ADC_VOL is not set +# CONFIG_BSP_USING_EXAMPLE_HWTIMER is not set +# CONFIG_BSP_USING_EXAMPLE_I2C is not set +# CONFIG_BSP_USING_EXAMPLE_LED_BLINK is not set +# CONFIG_BSP_USING_EXAMPLE_PIN_BEEP is not set +# CONFIG_BSP_USING_EXAMPLE_PWM_LED is not set +# CONFIG_BSP_USING_EXAMPLE_RTC is not set +# CONFIG_BSP_USING_EXAMPLE_SPI is not set +# CONFIG_BSP_USING_EXAMPLE_UART is not set +# CONFIG_BSP_USING_EXAMPLE_CAN is not set +# CONFIG_BSP_USING_EXAMPLE_PM is not set diff --git a/bsp/essemi/es32f369x/README.md b/bsp/essemi/es32f369x/README.md index 100fc9aa602a389aaf474579c6e20148145fbb12..7edc8bd23f16decd45ed3f5600093ecdaa69bf5f 100644 --- a/bsp/essemi/es32f369x/README.md +++ b/bsp/essemi/es32f369x/README.md @@ -86,6 +86,22 @@ msh> 2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + a）如果需要使用内核用例，先配置rt-thread内核，如图： + + ![kernel_config](figures/k_conf.jpg) + + 然后配置内核用例，如图： + + ![kernel_samples](figures/k_ex.jpg) + + b）如果需要使用驱动用例：先使能驱动，如图： + + ![driver_config](figures/d_conf.jpg) + + 然后配置驱动用例，如图： + + ![driver_sample](figures/d_ex.jpg) + 3. 输入`pkgs --update`命令更新软件包。 4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 @@ -94,7 +110,7 @@ msh> ## 4. 联系人信息 -- [wangyongquan](https://github.com/wangyq2018) +- [liuhongyan](https://gitee.com/liuhongyan98) ## 5. 参考 diff --git a/bsp/essemi/es32f369x/drivers/Kconfig b/bsp/essemi/es32f369x/drivers/Kconfig index a47aa307413a91266163a9fdf5c27db814de26ea..4b42e7e07482f04f4906cc64de34b5e9eab99dc6 100644 --- a/bsp/essemi/es32f369x/drivers/Kconfig +++ b/bsp/essemi/es32f369x/drivers/Kconfig @@ -123,6 +123,13 @@ menu "Hardware Drivers Config" default n endmenu + menu "PM Drivers" + config BSP_USING_PM + bool "Using PM" + select RT_USING_PM + default n + endmenu + endmenu menu "Onboard Peripheral Drivers" @@ -133,4 +140,53 @@ menu "Hardware Drivers Config" endmenu + + menu "Peripheral Drivers test example" + + config BSP_USING_EXAMPLE_ADC_VOL + bool "BSP_USING_EXAMPLE_ADC_VOL" + default n + + config BSP_USING_EXAMPLE_HWTIMER + bool "BSP_USING_EXAMPLE_HWTIMER" + default n + + config BSP_USING_EXAMPLE_I2C + bool "BSP_USING_EXAMPLE_I2C" + default n + + config BSP_USING_EXAMPLE_LED_BLINK + bool "BSP_USING_EXAMPLE_LED_BLINK" + default y + + config BSP_USING_EXAMPLE_PIN_BEEP + bool "BSP_USING_EXAMPLE_PIN_BEEP" + default y + + config BSP_USING_EXAMPLE_PWM_LED + bool "BSP_USING_EXAMPLE_PWM_LED" + default n + + config BSP_USING_EXAMPLE_RTC + bool "BSP_USING_EXAMPLE_RTC" + default n + + config BSP_USING_EXAMPLE_SPI + bool "BSP_USING_EXAMPLE_SPI" + default n + + config BSP_USING_EXAMPLE_UART + bool "BSP_USING_EXAMPLE_UART" + default y + + config BSP_USING_EXAMPLE_CAN + bool "BSP_USING_EXAMPLE_CAN" + default n + + config BSP_USING_EXAMPLE_PM + bool "BSP_USING_EXAMPLE_PM" + default n + + endmenu + endmenu diff --git a/bsp/essemi/es32f369x/drivers/SConscript b/bsp/essemi/es32f369x/drivers/SConscript index b8a39e8fac32ad1b7e3759205d0d03b24536cfe5..735ebb37be2f41a7701f9ea2a5d3f4a010bb8f6c 100644 --- a/bsp/essemi/es32f369x/drivers/SConscript +++ b/bsp/essemi/es32f369x/drivers/SConscript @@ -2,6 +2,8 @@ from building import * cwd = GetCurrentDir() +objs = [] + # add the general drivers. src = Split(''' board.c @@ -44,7 +46,52 @@ if GetDepend('BSP_USING_HWTIMER0') or GetDepend('BSP_USING_HWTIMER1'): if GetDepend('BSP_USING_PWM0') or GetDepend('BSP_USING_PWM1'): src += ['drv_pwm.c'] +# add pm driver code +if GetDepend(['BSP_USING_PM']): + src += ['drv_pm.c'] + CPPPATH = [cwd] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) +objs = objs + group + +src = [] +cwd = GetCurrentDir() +include_path = [cwd] + +if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'): + src += ['bsp_driver_example/adc_vol_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_HWTIMER'): + src += ['bsp_driver_example/hwtimer_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_I2C'): + src += ['bsp_driver_example/i2c_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'): + src += ['bsp_driver_example/led_blink_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_PIN_BEEP'): + src += ['bsp_driver_example/pin_beep_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_PWM_LED'): + src += ['bsp_driver_example/pwm_led_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_RTC'): + src += ['bsp_driver_example/rtc_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_UART'): + src += ['bsp_driver_example/uart_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_SPI'): + src += ['bsp_driver_example/spi_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_CAN'): + src += ['bsp_driver_example/can_sample.c'] + +if GetDepend('BSP_USING_EXAMPLE_PM'): + src += ['bsp_driver_example/pm_sample.c'] + +group = DefineGroup('bsp-drivers-test-samples', src, depend = [''], CPPPATH = include_path) -Return('group') +objs = objs + group +Return('objs') diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/.gitignore b/bsp/essemi/es32f369x/drivers/bsp_driver_example/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..c6127b38c1aa25968a88db3940604d41529e4cf5 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/.gitignore @@ -0,0 +1,52 @@ +# Prerequisites +*.d + +# Object files +*.o +*.ko +*.obj +*.elf + +# Linker output +*.ilk +*.map +*.exp + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex + +# Debug files +*.dSYM/ +*.su +*.idb +*.pdb + +# Kernel Module Compile Results +*.mod* +*.cmd +.tmp_versions/ +modules.order +Module.symvers +Mkfile.old +dkms.conf diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/README.md b/bsp/essemi/es32f369x/drivers/bsp_driver_example/README.md new file mode 100644 index 0000000000000000000000000000000000000000..80f12e1949235d15811415581686d64f623599f0 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/README.md @@ -0,0 +1,47 @@ +# 外设驱动测试用例 + +## 1、介绍 + +这个软件包包含一些外设设备操作的例程。 + +### 1.1 例程说明 + +| 文件 | 说明 | +| ---------------- | ------------------------------- | +| adc_vol_sample.c | 使用 ADC 设备转换电压数据 | +| can_sample.c | 通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。 | +| hwtimer_sample.c | 使用 硬件定时器定时 | +| i2c_sample.c | 使用 i2c 设备进行读写 | +| pm.c | 反复进入不同程度的睡眠。 | +| led_blink_sample.c | 使用 pin 设备控制 LED 闪烁 | +| pin_beep_sample.c | 使用 pin 设备控制蜂鸣器 | +| pwm_led_sample.c | 使用 pwm 设备控制 LED 的亮度 | +| rtc_sample.c | 使用 rtc 设备设置年月日时分秒信息 | +| spi_sample.c | 使用 spi 设备进行读写 | +| uart_sample.c | 使用 serial 设备中断接收及轮询发送模式收发数据 | + +### 1.2 依赖 + +依赖设备管理模块提供的设备驱动。 + +## 2、如何打开 外设驱动测试用例 + +使用 外设驱动测试用例 需要在 RT-Thread 的menuconfig中选择它，具体路径如下： + +``` +Hardware Driver Config ---> + Peripheral Driver test example---> +``` + +## 3、使用 外设驱动测试用例 + +在打开 Peripheral Driver test example 后，当进行 BSP 编译时，选择的软件包相关源代码会被加入到 BSP 工程中进行编译。 + +## 4、注意事项 + +暂无。 + +## 5、联系方式 & 感谢 + +* 维护：[misonyo](https://github.com/misonyo) +* 主页：https://github.com/RT-Thread-packages/peripheral-sample diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..f9444982d4ff19c21a19b99a8f42d8c68e4b891e --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-29 misonyo first implementation. + */ +/* + * 程序清单： ADC 设备使用例程 + * 例程导出了 adc_sample 命令到控制终端 + * 命令调用格式：adc_sample + * 程序功能：通过 ADC 设备采样电压值并转换为数值。 + * 示例代码参考电压为3.3V,转换位数为12位。 +*/ + +#include +#include + +#define ADC_DEV_NAME "adc0" /* ADC 设备名称 */ +#define ADC_DEV_CHANNEL 5 /* ADC 通道 5 PA1*/ +#define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/ +#define CONVERT_BITS (1 << 12) /* 转换位数为12位 */ + +static int adc_vol_sample(int argc, char *argv[]) +{ + rt_adc_device_t adc_dev; + rt_uint32_t value, vol; + rt_err_t ret = RT_EOK; + + /* 查找设备 */ + adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME); + if (adc_dev == RT_NULL) + { + rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME); + return RT_ERROR; + } + + /* 使能设备 */ + ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL); + + /* 读取采样值 */ + value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL); + rt_kprintf("the value is :%d \n", value); + + /* 转换为对应电压值 */ + vol = value * REFER_VOLTAGE / CONVERT_BITS; + rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); + + /* 关闭通道 */ + ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL); + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..bfbd50095e0217ee8b434423de44c816c9c8e120 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-06-25 misonyo first implementation. + */ +/* + * 程序清单：这是一个 CAN 设备使用例程 + * 例程导出了 can_sample 命令到控制终端 + * 命令调用格式：can_sample can + * 命令解释：命令第二个参数是要使用的 CAN 设备名称，为空则使用默认的 CAN 设备 + * 程序功能：通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。 +*/ + +#include +#include "rtdevice.h" + +#define CAN_DEV_NAME "can" /* CAN 设备名称 */ + +static struct rt_semaphore rx_sem; /* 用于接收消息的信号量 */ +static rt_device_t can_dev; /* CAN 设备句柄 */ + +/* 接收数据回调函数 */ +static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size) +{ + /* CAN 接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */ + rt_sem_release(&rx_sem); + + return RT_EOK; +} + +static void can_rx_thread(void *parameter) +{ + int i; + struct rt_can_msg rxmsg = {0}; + + /* 设置接收回调函数 */ + rt_device_set_rx_indicate(can_dev, can_rx_call); + +#ifdef RT_CAN_USING_HDR + + rt_err_t res; + + struct rt_can_filter_item items[5] = + { + RT_CAN_FILTER_ITEM_INIT(0x100, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x100~0x1ff，hdr为-1，设置默认过滤表 */ + RT_CAN_FILTER_ITEM_INIT(0x300, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x300~0x3ff，hdr为-1 */ + RT_CAN_FILTER_ITEM_INIT(0x211, 0, 0, 0, 0x7ff, RT_NULL, RT_NULL), /* std,match ID:0x211，hdr为-1 */ + RT_CAN_FILTER_STD_INIT(0x486, RT_NULL, RT_NULL), /* std,match ID:0x486，hdr为-1 */ + {0x555, 0, 0, 0, 0x7ff, 7,} /* std,match ID:0x555，hdr为7，指定设置7号过滤表 */ + }; + struct rt_can_filter_config cfg = {5, 1, items}; /* 一共有5个过滤表 */ + /* 设置硬件过滤表 */ + res = rt_device_control(can_dev, RT_CAN_CMD_SET_FILTER, &cfg); + RT_ASSERT(res == RT_EOK); +#endif + + while (1) + { + /* hdr值为-1，表示直接从uselist链表读取数据 */ + rxmsg.hdr = -1; + /* 阻塞等待接收信号量 */ + rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + /* 从CAN读取一帧数据 */ + rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg)); + /* 打印数据ID及内容 */ + rt_kprintf("ID:%x ", rxmsg.id); + for (i = 0; i < 8; i++) + { + rt_kprintf("%2x ", rxmsg.data[i]); + } + + rt_kprintf("\n"); + } +} + +int can_sample(int argc, char *argv[]) +{ + struct rt_can_msg msg = {0}; + rt_err_t res; + rt_size_t size; + rt_thread_t thread; + char can_name[RT_NAME_MAX]; + + if (argc == 2) + { + rt_strncpy(can_name, argv[1], RT_NAME_MAX); + } + else + { + rt_strncpy(can_name, CAN_DEV_NAME, RT_NAME_MAX); + } + + can_dev = rt_device_find(can_name); + if (!can_dev) + { + rt_kprintf("find %s failed!\n", can_name); + return RT_ERROR; + } + + /* 初始化CAN接收信号量 */ + rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); + + /* 以中断接收及发送方式打开CAN设备 */ + res = rt_device_open(can_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX); + RT_ASSERT(res == RT_EOK); + + thread = rt_thread_create("can_rx", can_rx_thread, RT_NULL, 1024, 25, 10); + if (thread != RT_NULL) + { + rt_thread_startup(thread); + } + else + { + rt_kprintf("create can_rx thread failed!\n"); + } + + msg.id = 0x78; /* ID为0x78 */ + msg.ide = RT_CAN_STDID; /* 标准格式 */ + msg.rtr = RT_CAN_DTR; /* 数据帧 */ + msg.len = 8; /* 数据长度为8 */ + /* 待发送的8字节数据 */ + msg.data[0] = 0x00; + msg.data[1] = 0x11; + msg.data[2] = 0x22; + msg.data[3] = 0x33; + msg.data[4] = 0x44; + msg.data[5] = 0x55; + msg.data[6] = 0x66; + msg.data[7] = 0x77; + /* 发送一帧CAN数据 */ + size = rt_device_write(can_dev, 0, &msg, sizeof(msg)); + if (size == 0) + { + rt_kprintf("can dev write data failed!\n"); + } + + return res; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(can_sample, can device sample); diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..e2e39664f3a5f7cd1c09f4a1e6dcf6d30e050e57 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-30 misonyo first implementation. + */ +/* + * 程序清单：这是一个 hwtimer 设备使用例程 + * 例程导出了 hwtimer_sample 命令到控制终端 + * 命令调用格式：hwtimer_sample + * 程序功能：硬件定时器超时回调函数周期性的打印当前tick值，2次tick值之差换算为时间等同于定时时间值。 +*/ + +#include +#include + +#define HWTIMER_DEV_NAME "timer0" /* 定时器名称 */ + +/* 定时器超时回调函数 */ +static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) +{ + rt_kprintf("tick is :%d !\n", rt_tick_get()); + + return 0; +} + +static int hwtimer_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + rt_hwtimerval_t timeout_s; /* 定时器超时值 */ + rt_device_t hw_dev = RT_NULL; /* 定时器设备句柄 */ + rt_hwtimer_mode_t mode; /* 定时器模式 */ + + /* 查找定时器设备 */ + hw_dev = rt_device_find(HWTIMER_DEV_NAME); + if (hw_dev == RT_NULL) + { + rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + return RT_ERROR; + } + + /* 以读写方式打开设备 */ + ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); + if (ret != RT_EOK) + { + rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + return ret; + } + + /* 设置超时回调函数 */ + rt_device_set_rx_indicate(hw_dev, timeout_cb); + + /* 设置模式为周期性定时器 */ + mode = HWTIMER_MODE_PERIOD; + ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + if (ret != RT_EOK) + { + rt_kprintf("set mode failed! ret is :%d\n", ret); + return ret; + } + + /* 设置定时器超时值为5s并启动定时器 */ + timeout_s.sec = 5; /* 秒 */ + timeout_s.usec = 0; /* 微秒 */ + + if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s)) + { + rt_kprintf("set timeout value failed\n"); + return RT_ERROR; + } + + /* 延时3500ms */ + rt_thread_mdelay(3500); + + /* 读取定时器当前值 */ + rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); + rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..4fd42baf4198ea00f91da17a2b7a38477696a023 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy first implementation. + */ +/* + * 程序清单：这是一个 I2C 设备使用例程 + * 例程导出了 i2c_io_sample 命令到控制终端 + * 命令调用格式：i2c_io_sample + * 命令解释：使用默认的I2C总线设备i2c0 + * 程序功能：通过 I2C 设备接收数据并打印，然后将接收的字符加1输出。 +*/ + +#include +#include + +#define I2C_BUS_NAME "i2c0" /* I2C总线设备名称 */ +#define SLAVE_ADDR 0x2D /* 从机地址 */ +#define STR_LEN 16 /* 接收发送的数据长度 */ + +static void i2c_io_sample(int argc, char *argv[]) +{ + + struct rt_i2c_bus_device *i2c_bus = RT_NULL; /* I2C总线设备句柄 */ + struct rt_i2c_msg temp_msg; /* I2C消息 */ + rt_uint8_t buffer[STR_LEN] = { 0U }; + rt_uint32_t i,num_msg; + rt_size_t s_stat; + + i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(I2C_BUS_NAME); /* 通过名字获取I2C总线设备的句柄 */ + + if( i2c_bus == RT_NULL) + { + rt_kprintf("can't find i2c device :%s !\n",I2C_BUS_NAME); + + return; + } + + /*初始化消息*/ + temp_msg.addr = SLAVE_ADDR; /* 从机地址 */ + temp_msg.len = STR_LEN; /* 传输的数据长度 */ + temp_msg.buf = buffer; /* 读写缓存器 */ + + num_msg = 1; /* 传输一条消息 */ + + temp_msg.flags = RT_I2C_RD; /* I2C读 */ + s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输消息 */ + + rt_thread_mdelay(400); + + if( s_stat == num_msg ) + { + rt_kprintf("receive successful. \n receive messege : %s \n:",buffer); + + for( i = 0 ; i < STR_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + } + else + { + rt_kprintf("device s% recieve fail \n buffer : s%\n",I2C_BUS_NAME,buffer); + return; + } + + for( i = 0 ; i < STR_LEN ; i++) + buffer[i]++; + + temp_msg.flags = RT_I2C_WR; /* I2C写 */ + s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输一条 */ + + rt_thread_mdelay(400); + + if( s_stat == num_msg ) + { + rt_kprintf(" send successful \n messege : %s \n:",buffer); + + for( i = 0 ; i < STR_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + } + else + { + rt_kprintf("device s% send fail \n",I2C_BUS_NAME); + return; + } + + return; + +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(i2c_io_sample, i2c io sample); diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/led_blink_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/led_blink_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..f1c9901ad05ed7fd866ba88c77b2fe025873648f --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/led_blink_sample.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-09-25 misonyo first edition. + */ +/* + * 程序清单：这是一个通过PIN脚控制LED亮灭的使用例程 + * 例程导出了 led_sample 命令到控制终端 + * 命令调用格式：led_sample 41 + * 命令解释：命令第二个参数是要使用的PIN脚编号，为空则使用例程默认的引脚编号。 + * 程序功能：程序创建一个led线程，线程每隔1000ms改变PIN脚状态，达到控制led灯 + * 亮灭的效果。 +*/ + +#include +#include +#include + +/* PIN脚编号，查看驱动文件drv_gpio.c确定 */ +#define LED_PIN_NUM 19 /*PF1*/ +static int pin_num; + +static void led_entry(void *parameter) +{ + int count = 0; + /* 设置PIN脚模式为输出 */ + rt_pin_mode(pin_num, PIN_MODE_OUTPUT); + + while (1) + { + count++; + rt_kprintf("thread run count : %d\r\n", count); + /* 拉低PIN脚 */ + rt_pin_write(pin_num, PIN_LOW); + rt_kprintf("led on!\r\n"); + /* 延时1000ms */ + rt_thread_mdelay(1000); + + /* 拉高PIN脚 */ + rt_pin_write(pin_num, PIN_HIGH); + rt_kprintf("led off!\r\n"); + rt_thread_mdelay(1000); + } +} + +static int led_sample(int argc, char *argv[]) +{ + rt_thread_t tid; + rt_err_t ret = RT_EOK; + + /* 判断命令行参数是否给定了PIN脚编号 */ + if (argc == 2) + { + pin_num = atoi(argv[1]); + } + else + { + pin_num = LED_PIN_NUM; + } + + tid = rt_thread_create("led", + led_entry, + RT_NULL, + 512, + RT_THREAD_PRIORITY_MAX / 3, + 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + ret = RT_ERROR; + } + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(led_sample, led sample); diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pin_beep_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pin_beep_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..58a7bf189150368d8267d3533ddcc01e8700f37c --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pin_beep_sample.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-15 misonyo first implementation. + */ +/* + * 程序清单：这是一个 PIN 设备使用例程 + * 例程导出了 pin_beep_sample 命令到控制终端 + * 命令调用格式：pin_beep_sample + * 程序功能：通过按键控制蜂鸣器对应引脚的电平状态控制蜂鸣器 +*/ + +#include +#include + +/* 引脚编号，通过查看驱动文件drv_gpio.c确定 */ +#ifndef BEEP_PIN_NUM + #define BEEP_PIN_NUM 19 /* PF1 */ +#endif +#ifndef KEY0_PIN_NUM + #define KEY0_PIN_NUM 52 /* PC11 */ +#endif +#ifndef KEY1_PIN_NUM + #define KEY1_PIN_NUM 53 /* PC12 */ +#endif + +void beep_on(void *args) +{ + rt_kprintf("turn on beep!\n"); + + rt_pin_write(BEEP_PIN_NUM, PIN_HIGH); +} + +void beep_off(void *args) +{ + rt_kprintf("turn off beep!\n"); + + rt_pin_write(BEEP_PIN_NUM, PIN_LOW); +} + +static void pin_beep_sample(void) +{ + /* 蜂鸣器引脚为输出模式 */ + rt_pin_mode(BEEP_PIN_NUM, PIN_MODE_OUTPUT); + /* 默认低电平 */ + rt_pin_write(BEEP_PIN_NUM, PIN_LOW); + + /* 按键0引脚为输入模式 */ + rt_pin_mode(KEY0_PIN_NUM, PIN_MODE_INPUT_PULLUP); + /* 绑定中断，下降沿模式，回调函数名为beep_on */ + rt_pin_attach_irq(KEY0_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_on, RT_NULL); + /* 使能中断 */ + rt_pin_irq_enable(KEY0_PIN_NUM, PIN_IRQ_ENABLE); + + /* 按键1引脚为输入模式 */ + rt_pin_mode(KEY1_PIN_NUM, PIN_MODE_INPUT_PULLUP); + /* 绑定中断，下降沿模式，回调函数名为beep_off */ + rt_pin_attach_irq(KEY1_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_off, RT_NULL); + /* 使能中断 */ + rt_pin_irq_enable(KEY1_PIN_NUM, PIN_IRQ_ENABLE); +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(pin_beep_sample, pin beep sample); diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..b8868761086855fc80078ee67c4ca5e6f3cb17cb --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy first implementation. + */ +/* + * 程序清单：这是一个 pm睡眠唤醒的使用例程 + * 例程导出了 pm_sample 命令到控制终端 + * 命令调用格式：pm_sample + * 命令解释：进入不同的睡眠模式，然后用按键唤醒 + * 程序功能：通过串口输出字符串，告知进入睡眠和唤醒睡眠的情况。 +*/ + +#include +#include +#include "drv_pm.h" + +#define PM_NAME "pm" /* 设备名称 */ +#define WAKE_UP_PIN 51 /* 唤醒源 */ +#define SLEEP_TIMES 12 /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */ + + +struct pm_callback_t +{ + volatile int in_fun_times; /*进入函数的次数*/ + volatile char flag; /*标志*/ + volatile int mode; /*需要打印的模式*/ +}; + +volatile struct pm_callback_t g_pm_data; + +uint32_t save_load_mem[1024] __attribute__ ((aligned(4))); /*备份的空间*/ + +/*进入睡眠前，睡眠唤醒后，都会进入。*/ +/*函数打印睡眠相关的信息*/ +void sleep_in_out_callback(rt_uint8_t event, rt_uint8_t mode, void *data) +{ + /*没有标志，不处理*/ + if(!(g_pm_data.flag)) + { + return; + } + + /*标志不正常，清空标志*/ + if((g_pm_data.flag) > 2) + { + (g_pm_data.flag) = 0; + return; + } + + /*模式不匹配*/ + if(g_pm_data.mode != mode ) + { + return; + } + + /*进入的事件*/ + switch(event) + { + /*进入睡眠前*/ + case RT_PM_ENTER_SLEEP: g_pm_data.flag = 1; + rt_kprintf("\n\r##%d : ENTER ",g_pm_data.in_fun_times); + save_register(UART0,sizeof(UART_TypeDef),save_load_mem); /*备份寄存器的值*/ + g_pm_data.in_fun_times++; /*进入睡眠次数+1*/ + break; + /*睡眠唤醒后*/ + case RT_PM_EXIT_SLEEP: g_pm_data.flag = 0; /*睡眠唤醒后*/ + load_register(UART0,sizeof(UART_TypeDef),save_load_mem); /*还原寄存器的值*/ + rt_kprintf("\n\rEXIT\n\r"); + rt_pm_release(mode); /*释放休眠模式*/ + return; + + default: break; + + }; + + /*当前的睡眠模式*/ + switch(mode) + { + case PM_SLEEP_MODE_NONE: rt_kprintf("PM_SLEEP_MODE_NONE\n\r"); + break; + case PM_SLEEP_MODE_IDLE: rt_kprintf("PM_SLEEP_MODE_IDLE\n\r"); + break; + case PM_SLEEP_MODE_LIGHT: rt_kprintf("PM_SLEEP_MODE_LIGHT\n\r"); + break; + case PM_SLEEP_MODE_DEEP: rt_kprintf("PM_SLEEP_MODE_DEEP\n\r"); + break; + case PM_SLEEP_MODE_STANDBY: rt_kprintf("PM_SLEEP_MODE_STANDBY\n\r"); + break; + case PM_SLEEP_MODE_SHUTDOWN: rt_kprintf("PM_SLEEP_MODE_SHUTDOWN\n\r"); + break; + case PM_SLEEP_MODE_MAX: rt_kprintf("PM_SLEEP_MODE_MAX\n\r"); + break; + default: break; + } + +} + +/* pm测试函数 */ +static void pm_test(void *parameter) +{ + int in_mode[7],i = 0; + + g_pm_data.in_fun_times = 0; + g_pm_data.flag = 0; + + in_mode[0] = PM_SLEEP_MODE_NONE; + in_mode[1] = PM_SLEEP_MODE_IDLE; + in_mode[2] = PM_SLEEP_MODE_LIGHT; + in_mode[3] = PM_SLEEP_MODE_DEEP; + in_mode[4] = PM_SLEEP_MODE_STANDBY; + in_mode[5] = PM_SLEEP_MODE_SHUTDOWN; + in_mode[6] = PM_SLEEP_MODE_MAX; + + /*设置回调函数和私有数据*/ + rt_pm_notify_set(sleep_in_out_callback,RT_NULL); + + while(i < SLEEP_TIMES) + { + + g_pm_data.mode = in_mode[i%6]; + + /*无休眠模式，不赋予标志*/ + if(g_pm_data.mode != PM_SLEEP_MODE_NONE) + { + g_pm_data.flag = 2; + + } + + /*请求选择的休眠模式*/ + rt_pm_request(in_mode[i%6]); + + rt_thread_mdelay(500); + + /*无休眠模式，不需要额外的等待*/ + while(( g_pm_data.flag != 0 )&&(g_pm_data.mode != PM_SLEEP_MODE_NONE)) + { + rt_thread_mdelay(500); + } + + /*释放选择的休眠模式*/ + rt_pm_release(in_mode[i%6]); + + i++; + + } + /*清除回调函数和私有数据*/ + rt_pm_notify_set(RT_NULL,RT_NULL); + rt_kprintf("thread pm_test close\n\r"); + +} + +/*按键唤醒的回调函数*/ +void wake_by_pin(void *args) +{ + +} + +static int pm_sample(int argc, char *argv[]) +{ + rt_thread_t thread; + + /* 按键引脚为输入模式 */ + rt_pin_mode(WAKE_UP_PIN, PIN_MODE_INPUT_PULLUP); + + /* 绑定中断，下降沿模式，回调函数名为wake_by_pin */ + rt_pin_attach_irq(WAKE_UP_PIN, PIN_IRQ_MODE_RISING, wake_by_pin, RT_NULL); + /* 使能中断 */ + rt_pin_irq_enable(WAKE_UP_PIN, PIN_IRQ_ENABLE); + + thread = rt_thread_create("pm_test", pm_test, RT_NULL, 1024, 25, 10); + + if (thread != RT_NULL) + { + rt_thread_startup(thread); + } + else + { + rt_kprintf("create pm_test thread failed!\n\r"); + } + + return RT_EOK; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(pm_sample, pm sample); diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..df82c1b41cd0a5f5b66b2a11869541570529af65 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-25 misonyo first implementation. + */ +/* + * 程序清单：这是一个 PWM 设备使用例程 + * 例程导出了 pwm_led_sample 命令到控制终端 + * 命令调用格式：pwm_led_sample + * 程序功能：通过 PWM 设备控制 LED 灯的亮度，可以看到LED不停的由暗变到亮，然后又从亮变到暗。 +*/ + +#include +#include + +#define LED_PIN_NUM 19 /* PF1 LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ +#define PWM_DEV_NAME "pwm1" /* PWM设备名称 */ +#define PWM_DEV_CHANNEL 2 /* PA1 PWM通道 */ + +struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */ + +static int pwm_led_sample(int argc, char *argv[]) +{ + rt_uint32_t period, pulse, dir; + + period = 500000; /* 周期为0.5ms，单位为纳秒ns */ + dir = 1; /* PWM脉冲宽度值的增减方向 */ + pulse = 0; /* PWM脉冲宽度值，单位为纳秒ns */ + + /* 查找设备 */ + pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME); + if (pwm_dev == RT_NULL) + { + rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME); + return RT_ERROR; + } + + /* 设置PWM周期和脉冲宽度默认值 */ + rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); + /* 使能设备 */ + rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL); + + while (1) + { + rt_thread_mdelay(50); + if (dir) + { + pulse += 5000; /* 从0值开始每次增加5000ns */ + } + else + { + pulse -= 5000; /* 从最大值开始每次减少5000ns */ + } + if (pulse >= period) + { + dir = 0; + } + if (0 == pulse) + { + dir = 1; + } + + /* 设置PWM周期和脉冲宽度 */ + rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); + } +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(pwm_led_sample, pwm sample); diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..711a3a0ebb497521114bbd24dd99933dbbd786a2 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-30 misonyo first implementation. + */ +/* + * 程序清单：这是一个 RTC 设备使用例程 + * 例程导出了 rtc_sample 命令到控制终端 + * 命令调用格式：rtc_sample + * 程序功能：设置RTC设备的日期和时间，延时一段时间后获取当前时间并打印显示。 +*/ + +#include +#include + +static int rtc_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + time_t now; + + /* 设置日期 */ + ret = set_date(2018, 12, 3); + if (ret != RT_EOK) + { + rt_kprintf("set RTC date failed\n"); + return ret; + } + + /* 设置时间 */ + ret = set_time(11, 15, 50); + if (ret != RT_EOK) + { + rt_kprintf("set RTC time failed\n"); + return ret; + } + + /* 延时3秒 */ + rt_thread_mdelay(3000); + + /* 获取时间 */ + now = time(RT_NULL); + rt_kprintf("%s\n", ctime(&now)); + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(rtc_sample, rtc sample); diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..994888cdb0d8a52bebf6bcd89f29df291db6dbe1 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy first implementation. + */ +/* + * 程序清单：这是一个 SPI 设备使用例程 + * 例程导出了 spi_io_sample 命令到控制终端 + * 命令调用格式：spi_io_sample + * 程序功能：通过SPI设备先读取数据，然后每个字符加1后输出。 +*/ + +#include +#include + +#define SPI_DEVICE_NAME "spi00" +#define BUF_LEN 16 + +static void spi_io_sample(int argc, char *argv[]) +{ + struct rt_spi_device * spi_dev; /* spi设备的句柄 */ + struct rt_spi_configuration spi_config; + rt_uint8_t i,buffer[BUF_LEN] = { 0U }; + rt_err_t s_stat; + rt_err_t result; + + /* 查找 spi设备 获取spi设备句柄 */ + spi_dev = (struct rt_spi_device *)rt_device_find(SPI_DEVICE_NAME); + + if (spi_dev == RT_NULL) + { + rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_DEVICE_NAME); + return; + } + + + /* 清空配置结构体 */ + rt_memset(&spi_config,0,sizeof(struct rt_spi_configuration)); + + spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ + spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ + spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ + spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ + spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ + spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ + + spi_config.data_width = 8; /* 数据长度：8 */ + + spi_config.max_hz = 2000000; /* 最快时钟频率 */ + + /* 配置SPI设备 */ + s_stat = rt_spi_configure(spi_dev,&spi_config); + + if(s_stat != RT_EOK) + { + rt_kprintf(" spi config fail !\n "); + return; + } + + + /* 获取总线 ，防止总线被多个线程同时使用 */ + result = rt_spi_take_bus(spi_dev); + + if (result != RT_EOK) + { + rt_kprintf(" %s take spi bus failed! \n", SPI_DEVICE_NAME); + return; + } + + /* 选中片选 */ + result = rt_spi_take(spi_dev); + + if (result != RT_EOK) + { + rt_kprintf(" %s take spi cs failed! \n", SPI_DEVICE_NAME); + return; + } + + + /*接收一次数据*/ + result = rt_spi_recv(spi_dev,buffer,BUF_LEN); + + if(result != BUF_LEN) + { + rt_kprintf("receive fail. \n buffer is : %s \n:",buffer); + + for( i = 0 ; i < BUF_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + + return; + } + + rt_kprintf("receive successful. \n buffer is : %s \n:",buffer); + + for( i = 0 ; i < BUF_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + + /* 将接收到的数据加1 */ + for( i = 0 ; i < BUF_LEN ; i++) + buffer[i]++; + + /*发送数据*/ + result = rt_spi_send(spi_dev,buffer,BUF_LEN); + + if(result != BUF_LEN) + { + rt_kprintf("send fail. \n buffer is : %s \n:",buffer); + + for( i = 0 ; i < BUF_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + + return; + } + + rt_kprintf("send successful. \n buffer is : %s \n:",buffer); + + for( i = 0 ; i < BUF_LEN ; i++) + rt_kprintf(" %x",(unsigned int)buffer[i]); + + rt_kprintf("\n"); + + /* 释放片选 */ + result = rt_spi_release(spi_dev); + + if (result != RT_EOK) + { + rt_kprintf(" %s release spi cs failed! \n", SPI_DEVICE_NAME); + return; + } + + /* 释放总线 */ + result = rt_spi_release_bus(spi_dev); + + if (result != RT_EOK) + { + rt_kprintf(" %s release spi bus failed! \n", SPI_DEVICE_NAME); + return; + } + +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(spi_io_sample, spi sample); diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/uart_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/uart_sample.c new file mode 100644 index 0000000000000000000000000000000000000000..e059df32bb23908edf252cef4efeaa316d6a840b --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/uart_sample.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-15 misonyo first implementation. + */ +/* + * 程序清单：这是一个 串口 设备使用例程 + * 例程导出了 uart_sample 命令到控制终端 + * 命令调用格式：uart_sample uart2 + * 命令解释：命令第二个参数是要使用的串口设备名称，为空则使用默认的串口设备 + * 程序功能：通过串口输出字符串"hello RT-Thread!"，然后错位输出输入的字符 +*/ + +#include + +#define SAMPLE_UART_NAME "uart0" /* 串口设备名称 */ + +/* 用于接收消息的信号量 */ +static struct rt_semaphore rx_sem; +static rt_device_t serial; + +/* 接收数据回调函数 */ +static rt_err_t uart_input(rt_device_t dev, rt_size_t size) +{ + /* 串口接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */ + rt_sem_release(&rx_sem); + + return RT_EOK; +} + +static void serial_thread_entry(void *parameter) +{ + char ch; + + while (1) + { + /* 从串口读取一个字节的数据，没有读取到则等待接收信号量 */ + while (rt_device_read(serial, -1, &ch, 1) != 1) + { + /* 阻塞等待接收信号量，等到信号量后再次读取数据 */ + rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + } + /* 读取到的数据通过串口错位输出 */ + ch = ch + 1; + rt_device_write(serial, 0, &ch, 1); + } +} + +static int uart_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + char uart_name[RT_NAME_MAX]; + char str[] = "hello RT-Thread!\r\n"; + + if (argc == 2) + { + rt_strncpy(uart_name, argv[1], RT_NAME_MAX); + } + else + { + rt_strncpy(uart_name, SAMPLE_UART_NAME, RT_NAME_MAX); + } + + /* 查找串口设备 */ + serial = rt_device_find(uart_name); + if (!serial) + { + rt_kprintf("find %s failed!\n", uart_name); + return RT_ERROR; + } + + /* 初始化信号量 */ + rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); + /* 以中断接收及轮询发送方式打开串口设备 */ + rt_device_open(serial, RT_DEVICE_FLAG_INT_RX); + /* 设置接收回调函数 */ + rt_device_set_rx_indicate(serial, uart_input); + /* 发送字符串 */ + rt_device_write(serial, 0, str, (sizeof(str) - 1)); + + /* 创建 serial 线程 */ + rt_thread_t thread = rt_thread_create("serial", serial_thread_entry, RT_NULL, 1024, 25, 10); + /* 创建成功则启动线程 */ + if (thread != RT_NULL) + { + rt_thread_startup(thread); + } + else + { + ret = RT_ERROR; + } + + return ret; +} +/* 导出到 msh 命令列表中 */ +MSH_CMD_EXPORT(uart_sample, uart device sample); diff --git a/bsp/essemi/es32f369x/drivers/drv_adc.c b/bsp/essemi/es32f369x/drivers/drv_adc.c index 6476aebd095d6e3927214c2daaf4e9e39c7dd9cc..79afc06123e4abe79463c40bc5f11d8d99cce45b 100644 --- a/bsp/essemi/es32f369x/drivers/drv_adc.c +++ b/bsp/essemi/es32f369x/drivers/drv_adc.c @@ -147,9 +147,9 @@ static rt_err_t es32f3_get_adc_value(struct rt_adc_device *device, rt_uint32_t c RT_ASSERT(value != RT_NULL); /* config adc channel */ - nm_config.channel = es32f3_adc_get_channel(channel); - nm_config.rank = ADC_NCH_RANK_1; - nm_config.samp_time = ADC_SAMPLETIME_4; + nm_config.ch = es32f3_adc_get_channel(channel); + nm_config.idx = ADC_NCH_IDX_1; + nm_config.samp = ADC_SAMPLETIME_4; ald_adc_normal_channel_config(_hadc, &nm_config); ald_adc_normal_start(_hadc); @@ -173,16 +173,16 @@ int rt_hw_adc_init(void) /* adc function initialization */ _h_adc0.perh = ADC0; - _h_adc0.init.data_align = ADC_DATAALIGN_RIGHT; - _h_adc0.init.scan_mode = DISABLE; - _h_adc0.init.cont_mode = DISABLE; - _h_adc0.init.disc_mode = ADC_ALL_DISABLE; - _h_adc0.init.disc_nbr = ADC_DISC_NBR_1; - _h_adc0.init.conv_res = ADC_CONV_RES_10; - _h_adc0.init.clk_div = ADC_CKDIV_128; + _h_adc0.init.align = ADC_DATAALIGN_RIGHT; + _h_adc0.init.scan = DISABLE; + _h_adc0.init.cont = DISABLE; + _h_adc0.init.disc = ADC_ALL_DISABLE; + _h_adc0.init.disc_nr = ADC_DISC_NR_1; + _h_adc0.init.data_bit = ADC_CONV_BIT_12; + _h_adc0.init.div = ADC_CKDIV_128; _h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL; - _h_adc0.init.neg_ref = ADC_NEG_REF_VSS; - _h_adc0.init.pos_ref = ADC_POS_REF_VDD; + _h_adc0.init.n_ref = ADC_NEG_REF_VSS; + _h_adc0.init.p_ref = ADC_POS_REF_VDD; ald_adc_init(&_h_adc0); rt_hw_adc_register(&_device_adc0, "adc0", &es32f3_adc_ops, &_h_adc0); diff --git a/bsp/essemi/es32f369x/drivers/drv_can.c b/bsp/essemi/es32f369x/drivers/drv_can.c index 6a887b719be321a97a36f28a37858fa4e30270bc..04f4f161d76dc775e887e798fc39055bf66d03c3 100644 --- a/bsp/essemi/es32f369x/drivers/drv_can.c +++ b/bsp/essemi/es32f369x/drivers/drv_can.c @@ -252,7 +252,7 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t RT_ASSERT(IS_CAN_DATA_LEN(pmsg->len)); if ((state == CAN_STATE_READY) || - (state == CAN_STATE_BUSY_RX)) + (state == CAN_STATE_BUSY_RX0)) { /*check select mailbox is empty */ switch (1 << box_num) @@ -611,7 +611,6 @@ int rt_hw_can_init(void) filter.mode = CAN_FILTER_MODE_MASK; filter.scale = CAN_FILTER_SCALE_32; filter.active = ENABLE; - filter.bank_number = 14; can.FilterConfig = filter; can.device.config = config; diff --git a/bsp/essemi/es32f369x/drivers/drv_i2c.c b/bsp/essemi/es32f369x/drivers/drv_i2c.c index 3ab68bae9e2d1154a32daccd5dd30ee5119bf62c..207890a6d407d01df127771d6b73a266af006784 100644 --- a/bsp/essemi/es32f369x/drivers/drv_i2c.c +++ b/bsp/essemi/es32f369x/drivers/drv_i2c.c @@ -37,7 +37,7 @@ static void _i2c_init(void) /* Initialize I2C Pin */ gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; + gpio_instruct.odos = GPIO_OPEN_DRAIN; gpio_instruct.pupd = GPIO_PUSH_UP; gpio_instruct.podrv = GPIO_OUT_DRIVE_1; gpio_instruct.nodrv = GPIO_OUT_DRIVE_0_1; diff --git a/bsp/essemi/es32f369x/drivers/drv_pm.c b/bsp/essemi/es32f369x/drivers/drv_pm.c new file mode 100644 index 0000000000000000000000000000000000000000..ffe46ff6f31ed7ddd60e06661891951ede0793d8 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_pm.c @@ -0,0 +1,273 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-15 liuhy the first version + */ + +#include "drv_pm.h" + +#ifdef RT_USING_PM + +//uint32_t save_mem[1024] __attribute__ ((aligned(4))); + +void save_register(void *p_head,uint32_t size,void *p_save) +{ + memcpy(p_save,p_head,size); +} + +void load_register(void *p_head,uint32_t size,void *p_load) +{ + uint32_t tmp; + memcpy(p_head,p_load,size); + + if((p_head == UART0) || (p_head == UART1) || (p_head == UART2) || + (p_head == UART3) || (p_head == UART4) || (p_head == UART5) ) + { + tmp = ((UART_TypeDef*)p_load)->IVS; + ((UART_TypeDef*)p_head)->IER = tmp; + } +} + +static void uart_console_reconfig(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config); +} + +static void delay(void) +{ + long i; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + i = 0; + do{ + i++; + } + while (i < 4000000); + + rt_hw_interrupt_enable(level); +} + +/** + * This function will put ES32F369x into sleep mode. + * + * @param pm pointer to power manage structure + */ + +struct pm_callback_t +{ + volatile int in_fun_times; /*进入函数的次数*/ + volatile char flag; /*标志*/ + volatile int mode; /*需要打印的模式*/ +}; + +extern volatile struct pm_callback_t g_pm_data; + +static void sleep(struct rt_pm *pm, uint8_t mode) +{ + + switch (mode) + { + case PM_SLEEP_MODE_NONE: + break; + + case PM_SLEEP_MODE_IDLE: + break; + + case PM_SLEEP_MODE_LIGHT: + /* Enter SLEEP Mode, Main regulator is ON */ + ald_pmu_stop1_enter(); + delay(); + + break; + + case PM_SLEEP_MODE_DEEP: + /* Enter STOP 2 mode */ + ald_pmu_stop2_enter(); + delay(); + break; + + case PM_SLEEP_MODE_STANDBY: + /* Enter STANDBY mode */ + ald_pmu_stop2_enter(); + delay(); + break; + + case PM_SLEEP_MODE_SHUTDOWN: + /* Enter SHUTDOWNN mode */ + ald_pmu_stop2_enter(); + delay(); + break; + + default: + RT_ASSERT(0); + break; + } + +} + +static uint8_t run_speed[PM_RUN_MODE_MAX][2] = +{ + {48, 0}, + {48, 1}, + {24, 2}, + {2, 3}, +}; + +static void run(struct rt_pm *pm, uint8_t mode) +{ + static uint8_t last_mode; + static char *run_str[] = PM_RUN_MODE_NAMES; + extern uint32_t __system_clock; + + if (mode == last_mode) + return; + last_mode = mode; + + ald_cmu_clock_config_default(); + __system_clock = 24000000; + switch (mode) + { + case PM_RUN_MODE_HIGH_SPEED: + case PM_RUN_MODE_NORMAL_SPEED: + /* hosc 12MHz, from hosc/3 pll to 48MHz */ + ald_cmu_pll1_config(CMU_PLL1_INPUT_HRC_6, CMU_PLL1_OUTPUT_48M); + /* MCLK 48MHz */ + ald_cmu_clock_config(CMU_CLOCK_PLL1, 48000000); + break; + case PM_RUN_MODE_MEDIUM_SPEED: + break; + case PM_RUN_MODE_LOW_SPEED: + ald_cmu_clock_config(CMU_CLOCK_HRC, 2000000); + break; + default: + break; + } + + /* 4. 更新外设时钟 */ + uart_console_reconfig(); + /* Re-Configure the Systick time */ + SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND); + + rt_kprintf("switch to %s mode, frequency = %d MHz\n", run_str[mode], run_speed[mode][0]); +} + +/** + * This function caculate the PM tick from OS tick + * + * @param tick OS tick + * + * @return the PM tick + */ +static rt_tick_t es32f3_pm_tick_from_os_tick(rt_tick_t tick) +{ + rt_uint32_t freq = 1; + + return (freq * tick / RT_TICK_PER_SECOND); +} + +/** + * This function caculate the OS tick from PM tick + * + * @param tick PM tick + * + * @return the OS tick + */ +static rt_tick_t es32f3_os_tick_from_pm_tick(rt_uint32_t tick) +{ + static rt_uint32_t os_tick_remain = 0; + rt_uint32_t ret, freq; + + freq = 1; + ret = (tick * RT_TICK_PER_SECOND + os_tick_remain) / freq; + + os_tick_remain += (tick * RT_TICK_PER_SECOND); + os_tick_remain %= freq; + + return ret; +} + +/** + * This function start the timer of pm + * + * @param pm Pointer to power manage structure + * @param timeout How many OS Ticks that MCU can sleep + */ +static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout) +{ + RT_ASSERT(pm != RT_NULL); + RT_ASSERT(timeout > 0); + + if (timeout != RT_TICK_MAX) + { + /* Convert OS Tick to pmtimer timeout value */ + timeout = es32f3_pm_tick_from_os_tick(timeout); + /* MAX 0xFFFF */ + if (timeout > 0xFFFF) + { + timeout = 0xFFFF; + } + } +} + +/** + * This function stop the timer of pm + * + * @param pm Pointer to power manage structure + */ +static void pm_timer_stop(struct rt_pm *pm) +{ + RT_ASSERT(pm != RT_NULL); +} + +/** + * This function calculate how many OS Ticks that MCU have suspended + * + * @param pm Pointer to power manage structure + * + * @return OS Ticks + */ +static rt_tick_t pm_timer_get_tick(struct rt_pm *pm) +{ + rt_uint32_t timer_tick; + + RT_ASSERT(pm != RT_NULL); + + timer_tick = 1; + + return es32f3_os_tick_from_pm_tick(timer_tick); +} + +/** + * This function initialize the power manager + */ +int drv_pm_hw_init(void) +{ + static const struct rt_pm_ops _ops = + { + sleep, + run, + pm_timer_start, + pm_timer_stop, + pm_timer_get_tick + }; + + rt_uint8_t timer_mask = 0; + + /* initialize timer mask */ + timer_mask = 1UL << PM_SLEEP_MODE_DEEP; + + /* initialize system pm module */ + rt_system_pm_init(&_ops, timer_mask, RT_NULL); + + return 0; +} +INIT_BOARD_EXPORT(drv_pm_hw_init); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_pm.h b/bsp/essemi/es32f369x/drivers/drv_pm.h new file mode 100644 index 0000000000000000000000000000000000000000..56de29eef5090b3d58ac26d74772c0c53bc694c6 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_pm.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-01 wangyq the first version + */ + +#ifndef DRV_PM_H__ +#define DRV_PM_H__ + +#include +#include +#include +#include +#include +#include "shell.h" + +int rt_hw_pm_init(void); + +extern void save_register(void *p_head,uint32_t size,void *p_save); + +extern void load_register(void *p_head,uint32_t size,void *p_load); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_spi.c b/bsp/essemi/es32f369x/drivers/drv_spi.c index 3bd56e18dea20f1a70188651f27bbc66718edec5..9bf7e4e4b58eb3627591c0039fb2f9b5db32fff9 100644 --- a/bsp/essemi/es32f369x/drivers/drv_spi.c +++ b/bsp/essemi/es32f369x/drivers/drv_spi.c @@ -29,6 +29,9 @@ rt_err_t spi_configure(struct rt_spi_device *device, spi_handle_t *hspi; hspi = (spi_handle_t *)device->bus->parent.user_data; + hspi->init.ss_en = DISABLE; + hspi->init.crc_calc = DISABLE; + /* config spi mode */ if (cfg->mode & RT_SPI_SLAVE) { @@ -63,6 +66,15 @@ rt_err_t spi_configure(struct rt_spi_device *device, { hspi->init.phase = SPI_CPHA_FIRST; } + if (cfg->mode & RT_SPI_MSB) + { + hspi->init.first_bit = SPI_FIRSTBIT_MSB; + } + else + { + hspi->init.first_bit = SPI_FIRSTBIT_LSB; + } + if (cfg->mode & RT_SPI_CPOL) { hspi->init.polarity = SPI_CPOL_HIGH; @@ -133,8 +145,7 @@ rt_err_t spi_configure(struct rt_spi_device *device, { hspi->init.baud = SPI_BAUD_256; } - hspi->init.ss_en = DISABLE; - hspi->init.crc_calc = DISABLE; + ald_spi_init(hspi); return RT_EOK; } @@ -148,11 +159,12 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * RT_ASSERT(device != RT_NULL); RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(device->bus->parent.user_data != RT_NULL); - RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL); - + hspi = (spi_handle_t *)device->bus->parent.user_data; cs = device->parent.user_data; + if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL) + { /* send & receive */ if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL)) { @@ -203,6 +215,20 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * } } + } + else + { + if (message->cs_take) + { + rt_pin_write(cs->pin, 0); + } + + if (message->cs_release) + { + rt_pin_write(cs->pin, 1); + } + return RT_EOK; + } return message->length; } @@ -252,6 +278,7 @@ int rt_hw_spi_init(void) _spi0.perh = SPI0; spi_bus = &_spi_bus0; spi = &_spi0; + rt_device_t spi_bus_dev0; /* SPI0 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; @@ -275,12 +302,24 @@ int rt_hw_spi_init(void) { return result; } + + rt_device_register(spi_bus_dev0, "spi00", RT_DEVICE_FLAG_RDWR); + + /* SPI0_NSS = PA15 = PIN 50 */ + result = es32f3_spi_device_attach(50, "spi0", "spi00"); + + if (result != RT_EOK) + { + return result; + } + #endif #ifdef BSP_USING_SPI1 _spi1.perh = SPI1; spi_bus = &_spi_bus1; spi = &_spi1; + rt_device_t spi_bus_dev0; /* SPI1 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; @@ -304,12 +343,24 @@ int rt_hw_spi_init(void) { return result; } + + rt_device_register(spi_bus_dev0, "spi10", RT_DEVICE_FLAG_RDWR); + + /* SPI1_NSS = PC00 = PIN 8 */ + result = es32f3_spi_device_attach(8, "spi1", "spi10"); + + if (result != RT_EOK) + { + return result; + } + #endif #ifdef BSP_USING_SPI2 _spi1.perh = SPI2; spi_bus = &_spi_bus2; spi = &_spi2; + rt_device_t spi_bus_dev0; /* SPI2 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; @@ -333,6 +384,17 @@ int rt_hw_spi_init(void) { return result; } + + rt_device_register(spi_bus_dev0, "spi20", RT_DEVICE_FLAG_RDWR); + + /* SPI2_NSS = PC04 = PIN 24 */ + result = es32f3_spi_device_attach(39, "spi2", "spi20"); + + if (result != RT_EOK) + { + return result; + } + #endif return result; } diff --git a/bsp/essemi/es32f369x/drivers/drv_uart.c b/bsp/essemi/es32f369x/drivers/drv_uart.c index 50d25474a0a3626a59e77b15f329f4b67ae1713a..b6a8b7a453b4e50f902c9818515f4870848bb24c 100644 --- a/bsp/essemi/es32f369x/drivers/drv_uart.c +++ b/bsp/essemi/es32f369x/drivers/drv_uart.c @@ -109,8 +109,8 @@ static rt_err_t es32f3x_configure(struct rt_serial_device *serial, struct serial ald_cmu_perh_clock_config(CMU_PERH_UART5, ENABLE); #endif /* uart5 gpio init */ - ald_uart_tx_fifo_config(&uart->huart, UART_TXFIFO_EMPTY, 1); - ald_uart_rx_fifo_config(&uart->huart, UART_RXFIFO_1BYTE, 1); + ald_uart_tx_fifo_config(&uart->huart, UART_TXFIFO_EMPTY); + ald_uart_rx_fifo_config(&uart->huart, UART_RXFIFO_1BYTE); uart->huart.init.mode = UART_MODE_UART; uart->huart.init.baud = cfg->baud_rate; diff --git a/bsp/essemi/es32f369x/figures/d_conf.jpg b/bsp/essemi/es32f369x/figures/d_conf.jpg new file mode 100644 index 0000000000000000000000000000000000000000..b6b206ea69341c910a63c45596bd1f55ea04c7a8 Binary files /dev/null and b/bsp/essemi/es32f369x/figures/d_conf.jpg differ diff --git a/bsp/essemi/es32f369x/figures/d_ex.jpg b/bsp/essemi/es32f369x/figures/d_ex.jpg new file mode 100644 index 0000000000000000000000000000000000000000..dc8854cd2d998d2560c02d99047753221f2d3bcc Binary files /dev/null and b/bsp/essemi/es32f369x/figures/d_ex.jpg differ diff --git a/bsp/essemi/es32f369x/figures/k_conf.jpg b/bsp/essemi/es32f369x/figures/k_conf.jpg new file mode 100644 index 0000000000000000000000000000000000000000..d900bd825105f3147d9f38919ca1e239cf55149c Binary files /dev/null and b/bsp/essemi/es32f369x/figures/k_conf.jpg differ diff --git a/bsp/essemi/es32f369x/figures/k_ex.jpg b/bsp/essemi/es32f369x/figures/k_ex.jpg new file mode 100644 index 0000000000000000000000000000000000000000..a4b1d3874d47f06a80cc6328322eaba41d62571a Binary files /dev/null and b/bsp/essemi/es32f369x/figures/k_ex.jpg differ diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h index dcb4caf65c36cd860f93d736d0a63591e18dfc39..2e29a0d5837ef618c39ce8c6f01e0e15da36a99b 100644 --- a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h @@ -2498,18 +2498,18 @@ typedef struct #define RTC_TAMPCON_TAMPTS_POS 16U #define RTC_TAMPCON_TAMPTS_MSK BIT(RTC_TAMPCON_TAMPTS_POS) -#define RTC_TAMPCON_TAMP2LV_POS 9U -#define RTC_TAMPCON_TAMP2LV_MSK BIT(RTC_TAMPCON_TAMP2LV_POS) - -#define RTC_TAMPCON_TAMP2EN_POS 8U -#define RTC_TAMPCON_TAMP2EN_MSK BIT(RTC_TAMPCON_TAMP2EN_POS) - -#define RTC_TAMPCON_TAMP1LV_POS 1U +#define RTC_TAMPCON_TAMP1LV_POS 9U #define RTC_TAMPCON_TAMP1LV_MSK BIT(RTC_TAMPCON_TAMP1LV_POS) -#define RTC_TAMPCON_TAMP1EN_POS 0U +#define RTC_TAMPCON_TAMP1EN_POS 8U #define RTC_TAMPCON_TAMP1EN_MSK BIT(RTC_TAMPCON_TAMP1EN_POS) +#define RTC_TAMPCON_TAMP0LV_POS 1U +#define RTC_TAMPCON_TAMP0LV_MSK BIT(RTC_TAMPCON_TAMP0LV_POS) + +#define RTC_TAMPCON_TAMP0EN_POS 0U +#define RTC_TAMPCON_TAMP0EN_MSK BIT(RTC_TAMPCON_TAMP0EN_POS) + /****************** Bit definition for RTC_TIME register ************************/ #define RTC_TIME_PM_POS 22U @@ -2802,12 +2802,12 @@ typedef struct #define RTC_IER_RSC_POS 16U #define RTC_IER_RSC_MSK BIT(RTC_IER_RSC_POS) -#define RTC_IER_TAMP2_POS 13U -#define RTC_IER_TAMP2_MSK BIT(RTC_IER_TAMP2_POS) - -#define RTC_IER_TAMP1_POS 12U +#define RTC_IER_TAMP1_POS 13U #define RTC_IER_TAMP1_MSK BIT(RTC_IER_TAMP1_POS) +#define RTC_IER_TAMP0_POS 12U +#define RTC_IER_TAMP0_MSK BIT(RTC_IER_TAMP0_POS) + #define RTC_IER_TSOV_POS 11U #define RTC_IER_TSOV_MSK BIT(RTC_IER_TSOV_POS) @@ -2855,12 +2855,12 @@ typedef struct #define RTC_IFR_RSCF_POS 16U #define RTC_IFR_RSCF_MSK BIT(RTC_IFR_RSCF_POS) -#define RTC_IFR_TAMP2F_POS 13U -#define RTC_IFR_TAMP2F_MSK BIT(RTC_IFR_TAMP2F_POS) - -#define RTC_IFR_TAMP1F_POS 12U +#define RTC_IFR_TAMP1F_POS 13U #define RTC_IFR_TAMP1F_MSK BIT(RTC_IFR_TAMP1F_POS) +#define RTC_IFR_TAMP0F_POS 12U +#define RTC_IFR_TAMP0F_MSK BIT(RTC_IFR_TAMP0F_POS) + #define RTC_IFR_TSOVF_POS 11U #define RTC_IFR_TSOVF_MSK BIT(RTC_IFR_TSOVF_POS) @@ -2908,17 +2908,17 @@ typedef struct #define RTC_IFCR_RSCFC_POS 16U #define RTC_IFCR_RSCFC_MSK BIT(RTC_IFCR_RSCFC_POS) -#define RTC_IFCR_TAMP2FC_POS 13U -#define RTC_IFCR_TAMP2FC_MSK BIT(RTC_IFCR_TAMP2FC_POS) - -#define RTC_IFCR_TAMP1FC_POS 12U +#define RTC_IFCR_TAMP1FC_POS 13U #define RTC_IFCR_TAMP1FC_MSK BIT(RTC_IFCR_TAMP1FC_POS) +#define RTC_IFCR_TAMP0FC_POS 12U +#define RTC_IFCR_TAMP0FC_MSK BIT(RTC_IFCR_TAMP0FC_POS) + #define RTC_IFCR_TSOVFC_POS 11U #define RTC_IFCR_TSOVFC_MSK BIT(RTC_IFCR_TSOVFC_POS) -#define RTC_IFCR_TSSTC_POS 10U -#define RTC_IFCR_TSSTC_MSK BIT(RTC_IFCR_TSSTC_POS) +#define RTC_IFCR_TSFC_POS 10U +#define RTC_IFCR_TSFC_MSK BIT(RTC_IFCR_TSFC_POS) #define RTC_IFCR_ALMBFC_POS 9U #define RTC_IFCR_ALMBFC_MSK BIT(RTC_IFCR_ALMBFC_POS) @@ -2961,12 +2961,12 @@ typedef struct #define RTC_ISR_RSCF_POS 16U #define RTC_ISR_RSCF_MSK BIT(RTC_ISR_RSCF_POS) -#define RTC_ISR_TAMP2F_POS 13U -#define RTC_ISR_TAMP2F_MSK BIT(RTC_ISR_TAMP2F_POS) - -#define RTC_ISR_TAMP1F_POS 12U +#define RTC_ISR_TAMP1F_POS 13U #define RTC_ISR_TAMP1F_MSK BIT(RTC_ISR_TAMP1F_POS) +#define RTC_ISR_TAMP0F_POS 12U +#define RTC_ISR_TAMP0F_MSK BIT(RTC_ISR_TAMP0F_POS) + #define RTC_ISR_TSOVF_POS 11U #define RTC_ISR_TSOVF_MSK BIT(RTC_ISR_TSOVF_POS) @@ -9030,14 +9030,11 @@ typedef struct #define QSPI_BASE (APB1_BASE + 0xD400) /* APB2 peripherals Base Address */ -#define LPTIM0_BASE (APB2_BASE + 0x0000) -#define LPUART0_BASE (APB2_BASE + 0x1000) #define ADC0_BASE (APB2_BASE + 0x2000) #define ADC1_BASE (APB2_BASE + 0x2400) #define ACMP0_BASE (APB2_BASE + 0x3000) #define ACMP1_BASE (APB2_BASE + 0x3400) #define ACMP2_BASE (APB2_BASE + 0x3800) -#define OPAMP_BASE (APB2_BASE + 0x4000) #define DAC0_BASE (APB2_BASE + 0x5000) #define WWDT_BASE (APB2_BASE + 0x6000) #define IWDT_BASE (APB2_BASE + 0x6400) @@ -9068,7 +9065,6 @@ typedef struct #define TRNG_BASE (AHB_BASE + 0x5C00) #define PIS_BASE (AHB_BASE + 0x6000) #define USB0_BASE (AHB_BASE + 0x6400) -#define ECC_BASE (AHB_BASE + 0x6800) /* EBI Base Address */ #define EBI_BANK1 (EBI_BASE) @@ -9111,18 +9107,14 @@ typedef struct #define QSPI ((QSPI_TypeDef *)QSPI_BASE) /* APB2 peripherals */ -#define LPTIM0 ((LPTIM_TypeDef *)LPTIM0_BASE) -#define LPUART0 ((LPUART_TypeDef *)LPUART0_BASE) #define ADC0 ((ADC_TypeDef *)ADC0_BASE) #define ADC1 ((ADC_TypeDef *)ADC1_BASE) #define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) #define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) #define ACMP2 ((ACMP_TypeDef *)ACMP2_BASE) -#define OPAMP ((OPAMP_TypeDef *)OPAMP_BASE) #define DAC0 ((DAC_TypeDef *)DAC0_BASE) #define WWDT ((WWDT_TypeDef *)WWDT_BASE) #define IWDT ((IWDT_TypeDef *)IWDT_BASE) -#define LCD ((LCD_TypeDef *)LCD_BASE) #define BKPC ((BKPC_TypeDef *)BKPC_BASE) #define RTC ((RTC_TypeDef *)RTC_BASE) #define TSENSE ((TSENSE_TypeDef *)TSENSE_BASE) @@ -9149,7 +9141,6 @@ typedef struct #define TRNG ((TRNG_TypeDef *)TRNG_BASE) #define PIS ((PIS_TypeDef *)PIS_BASE) #define USB0 ((USB_TypeDef *)USB0_BASE) -#define ECC ((ECC_TypeDef *)ECC_BASE) /* EBI peripherals */ #define EBI_Bank1 ((EBI_Bank1_TypeDef *)EBI_BANK1_R_BASE) diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/EASTSOFT_ES32F36xx_ALD.chm b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/EASTSOFT_ES32F36xx_ALD.chm index 2e2e54d9f7400d51fabd7152af218e5d81371e2c..bbe11349a6d676e4899aaa474559de323ec68518 100644 Binary files a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/EASTSOFT_ES32F36xx_ALD.chm and b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/EASTSOFT_ES32F36xx_ALD.chm differ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h index ab1140e97b5e5d2f75907ce20a646adaed8075a9..7fbb68e65510734c53bf1a390eee352c31d24500 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h @@ -63,95 +63,95 @@ typedef enum { * @brief ACMP positive input */ typedef enum { - ACMP_POS_CH0 = 0x0, /**< Channel 0 as positive input */ - ACMP_POS_CH1 = 0x1, /**< Channel 1 as positive input */ - ACMP_POS_CH2 = 0x2, /**< Channel 2 as positive input */ - ACMP_POS_CH3 = 0x3, /**< Channel 3 as positive input */ - ACMP_POS_CH4 = 0x4, /**< Channel 4 as positive input */ - ACMP_POS_CH5 = 0x5, /**< Channel 5 as positive input */ - ACMP_POS_CH6 = 0x6, /**< Channel 6 as positive input */ - ACMP_POS_CH7 = 0x7, /**< Channel 7 as positive input */ + ACMP_POS_CH0 = 0x0U, /**< Channel 0 as positive input */ + ACMP_POS_CH1 = 0x1U, /**< Channel 1 as positive input */ + ACMP_POS_CH2 = 0x2U, /**< Channel 2 as positive input */ + ACMP_POS_CH3 = 0x3U, /**< Channel 3 as positive input */ + ACMP_POS_CH4 = 0x4U, /**< Channel 4 as positive input */ + ACMP_POS_CH5 = 0x5U, /**< Channel 5 as positive input */ + ACMP_POS_CH6 = 0x6U, /**< Channel 6 as positive input */ + ACMP_POS_CH7 = 0x7U, /**< Channel 7 as positive input */ } acmp_pos_input_t; /** * @brief ACMP negative input */ typedef enum { - ACMP_NEG_CH0 = 0x0, /**< Channel 0 as negative input */ - ACMP_NEG_CH1 = 0x1, /**< Channel 1 as negative input */ - ACMP_NEG_CH2 = 0x2, /**< Channel 2 as negative input */ - ACMP_NEG_CH3 = 0x3, /**< Channel 3 as negative input */ - ACMP_NEG_CH4 = 0x4, /**< Channel 4 as negative input */ - ACMP_NEG_CH5 = 0x5, /**< Channel 5 as negative input */ - ACMP_NEG_CH6 = 0x6, /**< Channel 6 as negative input */ - ACMP_NEG_CH7 = 0x7, /**< Channel 7 as negative input */ - ACMP_NEG_1V25 = 0x8, /**< 1.25v as negative input */ - ACMP_NEG_2V5 = 0x9, /**< 2.5v as negative input */ - ACMP_NEG_VDD = 0xA, /**< VDD as negative input */ + ACMP_NEG_CH0 = 0x0U, /**< Channel 0 as negative input */ + ACMP_NEG_CH1 = 0x1U, /**< Channel 1 as negative input */ + ACMP_NEG_CH2 = 0x2U, /**< Channel 2 as negative input */ + ACMP_NEG_CH3 = 0x3U, /**< Channel 3 as negative input */ + ACMP_NEG_CH4 = 0x4U, /**< Channel 4 as negative input */ + ACMP_NEG_CH5 = 0x5U, /**< Channel 5 as negative input */ + ACMP_NEG_CH6 = 0x6U, /**< Channel 6 as negative input */ + ACMP_NEG_CH7 = 0x7U, /**< Channel 7 as negative input */ + ACMP_NEG_1V25 = 0x8U, /**< 1.25v as negative input */ + ACMP_NEG_2V5 = 0x9U, /**< 2.5v as negative input */ + ACMP_NEG_VDD = 0xAU, /**< VDD as negative input */ } acmp_neg_input_t; /** * @brief ACMP mode */ typedef enum { - ACMP_ULTRA_LOW_POWER = 0x0, /**< Ultra low power mode */ - ACMP_LOW_POWER = 0x1, /**< Low power mode */ - ACMP_MIDDLE_POWER = 0x2, /**< Middle power mode */ - ACMP_HIGH_POWER = 0x3, /**< High power mode */ + ACMP_ULTRA_LOW_POWER = 0x0U, /**< Ultra low power mode */ + ACMP_LOW_POWER = 0x1U, /**< Low power mode */ + ACMP_MIDDLE_POWER = 0x2U, /**< Middle power mode */ + ACMP_HIGH_POWER = 0x3U, /**< High power mode */ } acmp_mode_t; /** * @brief ACMP warm-up time */ typedef enum { - ACMP_4_PCLK = 0x0, /**< 4 hfperclk cycles */ - ACMP_8_PCLK = 0x1, /**< 4 hfperclk cycles */ - ACMP_16_PCLK = 0x2, /**< 4 hfperclk cycles */ - ACMP_32_PCLK = 0x3, /**< 4 hfperclk cycles */ - ACMP_64_PCLK = 0x4, /**< 4 hfperclk cycles */ - ACMP_128_PCLK = 0x5, /**< 4 hfperclk cycles */ - ACMP_256_PCLK = 0x6, /**< 4 hfperclk cycles */ - ACMP_512_PCLK = 0x7, /**< 4 hfperclk cycles */ + ACMP_4_PCLK = 0x0U, /**< 4 hfperclk cycles */ + ACMP_8_PCLK = 0x1U, /**< 4 hfperclk cycles */ + ACMP_16_PCLK = 0x2U, /**< 4 hfperclk cycles */ + ACMP_32_PCLK = 0x3U, /**< 4 hfperclk cycles */ + ACMP_64_PCLK = 0x4U, /**< 4 hfperclk cycles */ + ACMP_128_PCLK = 0x5U, /**< 4 hfperclk cycles */ + ACMP_256_PCLK = 0x6U, /**< 4 hfperclk cycles */ + ACMP_512_PCLK = 0x7U, /**< 4 hfperclk cycles */ } acmp_warm_time_t; /** * @brief ACMP hysteresis level */ typedef enum { - ACMP_HYST_0 = 0x0, /**< No hysteresis */ - ACMP_HYST_15 = 0x1, /**< 15mV hysteresis */ - ACMP_HYST_22 = 0x2, /**< 22mV hysteresis */ - ACMP_HYST_29 = 0x3, /**< 29mV hysteresis */ - ACMP_HYST_36 = 0x4, /**< 36mV hysteresis */ - ACMP_HYST_43 = 0x5, /**< 43mV hysteresis */ - ACMP_HYST_50 = 0x6, /**< 50mV hysteresis */ - ACMP_HYST_57 = 0x7, /**< 57mV hysteresis */ + ACMP_HYST_0 = 0x0U, /**< No hysteresis */ + ACMP_HYST_15 = 0x1U, /**< 15mV hysteresis */ + ACMP_HYST_22 = 0x2U, /**< 22mV hysteresis */ + ACMP_HYST_29 = 0x3U, /**< 29mV hysteresis */ + ACMP_HYST_36 = 0x4U, /**< 36mV hysteresis */ + ACMP_HYST_43 = 0x5U, /**< 43mV hysteresis */ + ACMP_HYST_50 = 0x6U, /**< 50mV hysteresis */ + ACMP_HYST_57 = 0x7U, /**< 57mV hysteresis */ } acmp_hystsel_t; /** * @brief ACMP inactive state */ typedef enum { - ACMP_INACTVAL_LOW = 0x0, /**< The inactive value is 0 */ - ACMP_INACTVAL_HIGH = 0x1, /**< The inactive value is 1 */ + ACMP_INACTVAL_LOW = 0x0U, /**< The inactive value is 0 */ + ACMP_INACTVAL_HIGH = 0x1U, /**< The inactive value is 1 */ } acmp_inactval_t; /** * @brief which edges set up interrupt */ typedef enum { - ACMP_EDGE_NONE = 0x0, /**< Disable EDGE interrupt */ - ACMP_EDGE_FALL = 0x1, /**< Falling edges set EDGE interrupt */ - ACMP_EDGE_RISE = 0x2, /**< rise edges set EDGE interrupt */ - ACMP_EDGE_ALL = 0x3, /**< Falling edges and rise edges set EDGE interrupt */ + ACMP_EDGE_NONE = 0x0U, /**< Disable EDGE interrupt */ + ACMP_EDGE_FALL = 0x1U, /**< Falling edges set EDGE interrupt */ + ACMP_EDGE_RISE = 0x2U, /**< rise edges set EDGE interrupt */ + ACMP_EDGE_ALL = 0x3U, /**< Falling edges and rise edges set EDGE interrupt */ } acmp_edge_t; /** * @brief ACMP output function */ typedef enum { - ACMP_OUT_DISABLE = 0x0, /**< Disable acmp output */ - ACMP_OUT_ENABLE = 0x1, /**< Enable acmp output */ + ACMP_OUT_DISABLE = 0x0U, /**< Disable acmp output */ + ACMP_OUT_ENABLE = 0x1U, /**< Enable acmp output */ } acmp_out_func_t; /** diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h index cfadf6af80e988c592b65a707d97ee378d89ea51..2638e139fd6d4ee2931f1103dad8365e900300f1 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h @@ -41,123 +41,121 @@ * @brief ADC State structures definition */ typedef enum { - ADC_STATE_RESET = 0x0, /**< ADC not yet initialized or disabled */ - ADC_STATE_READY = 0x1, /**< ADC peripheral ready for use */ - ADC_STATE_BUSY_INTERNAL = 0x2, /**< ADC is busy to internal process */ - ADC_STATE_TIMEOUT = 0x4, /**< TimeOut occurrence */ - ADC_STATE_ERROR = 0x10, /**< Internal error occurrence */ - ADC_STATE_NM_BUSY = 0x100, /**< Conversion on group normal is ongoing or can occur */ - ADC_STATE_NM_EOC = 0x200, /**< Conversion data available on group normal */ - ADC_STATE_IST_BUSY = 0x1000, /**< Conversion on group insert is ongoing or can occur */ - ADC_STATE_IST_EOC = 0x2000, /**< Conversion data available on group insert */ - ADC_STATE_AWD = 0x10000, /**< Out-of-window occurrence of analog watchdog */ + ADC_STATE_RESET = 0x0U, /**< ADC not yet initialized or disabled */ + ADC_STATE_READY = 0x1U, /**< ADC peripheral ready for use */ + ADC_STATE_BUSY = 0x2U, /**< ADC is busy to internal process */ + ADC_STATE_TIMEOUT = 0x4U, /**< TimeOut occurrence */ + ADC_STATE_ERROR = 0x8U, /**< Internal error occurrence */ + ADC_STATE_BUSY_N = 0x10U, /**< Normal channel busy */ + ADC_STATE_BUSY_I = 0x20U, /**< Insert channel busy */ + ADC_STATE_BUSY_WDG = 0x40U, /**< Insert channel busy */ } adc_state_t; /** *@brief ADC Error Code */ typedef enum { - ADC_ERROR_NONE = 0x0, /**< No error */ - ADC_ERROR_INTERNAL = 0x1, /**< ADC IP internal error*/ - ADC_ERROR_OVR = 0x2, /**< Overrun error */ - ADC_ERROR_DMA = 0x4, /**< DMA transfer error */ + ADC_ERROR_NONE = 0x0U, /**< No error */ + ADC_ERROR_INTERNAL = 0x1U, /**< ADC IP internal error*/ + ADC_ERROR_OVR = 0x2U, /**< Overrun error */ + ADC_ERROR_DMA = 0x4U, /**< DMA transfer error */ } adc_error_t; /** *@brief ADC data alignment */ typedef enum { - ADC_DATAALIGN_RIGHT = 0x0, /**< ADC data alignment right */ - ADC_DATAALIGN_LEFT = 0x1, /**< ADC data alignment left */ + ADC_DATAALIGN_RIGHT = 0x0U, /**< ADC data alignment right */ + ADC_DATAALIGN_LEFT = 0x1U, /**< ADC data alignment left */ } adc_align_t; /** *@brief ADC config hannal trigger the EOC IT mode */ typedef enum { - ADC_NCHESEL_MODE_ALL = 0x0, /**< ADC set RCHE after convert sequence finish */ - ADC_NCHESEL_MODE_ONE = 0x1, /**< ADC set RCHE after one convert finish */ + ADC_NCHESEL_MODE_ALL = 0x0U, /**< ADC set RCHE after convert sequence finish */ + ADC_NCHESEL_MODE_ONE = 0x1U, /**< ADC set RCHE after one convert finish */ } adc_nchesel_t; /** *@brief ADC channels */ typedef enum { - ADC_CHANNEL_0 = 0x0, /**< ADC channel 0 */ - ADC_CHANNEL_1 = 0x1, /**< ADC channel 1 */ - ADC_CHANNEL_2 = 0x2, /**< ADC channel 2 */ - ADC_CHANNEL_3 = 0x3, /**< ADC channel 3 */ - ADC_CHANNEL_4 = 0x4, /**< ADC channel 4 */ - ADC_CHANNEL_5 = 0x5, /**< ADC channel 5 */ - ADC_CHANNEL_6 = 0x6, /**< ADC channel 6 */ - ADC_CHANNEL_7 = 0x7, /**< ADC channel 7 */ - ADC_CHANNEL_8 = 0x8, /**< ADC channel 8 */ - ADC_CHANNEL_9 = 0x9, /**< ADC channel 9 */ - ADC_CHANNEL_10 = 0xA, /**< ADC channel 10 */ - ADC_CHANNEL_11 = 0xB, /**< ADC channel 11 */ - ADC_CHANNEL_12 = 0xC, /**< ADC channel 12 */ - ADC_CHANNEL_13 = 0xD, /**< ADC channel 13 */ - ADC_CHANNEL_14 = 0xE, /**< ADC channel 14 */ - ADC_CHANNEL_15 = 0xF, /**< ADC channel 15 */ - ADC_CHANNEL_16 = 0x10, /**< ADC channel 16 */ - ADC_CHANNEL_17 = 0x11, /**< ADC channel 17 */ - ADC_CHANNEL_18 = 0x12, /**< ADC channel 18 */ + ADC_CHANNEL_0 = 0x0U, /**< ADC channel 0 */ + ADC_CHANNEL_1 = 0x1U, /**< ADC channel 1 */ + ADC_CHANNEL_2 = 0x2U, /**< ADC channel 2 */ + ADC_CHANNEL_3 = 0x3U, /**< ADC channel 3 */ + ADC_CHANNEL_4 = 0x4U, /**< ADC channel 4 */ + ADC_CHANNEL_5 = 0x5U, /**< ADC channel 5 */ + ADC_CHANNEL_6 = 0x6U, /**< ADC channel 6 */ + ADC_CHANNEL_7 = 0x7U, /**< ADC channel 7 */ + ADC_CHANNEL_8 = 0x8U, /**< ADC channel 8 */ + ADC_CHANNEL_9 = 0x9U, /**< ADC channel 9 */ + ADC_CHANNEL_10 = 0xAU, /**< ADC channel 10 */ + ADC_CHANNEL_11 = 0xBU, /**< ADC channel 11 */ + ADC_CHANNEL_12 = 0xCU, /**< ADC channel 12 */ + ADC_CHANNEL_13 = 0xDU, /**< ADC channel 13 */ + ADC_CHANNEL_14 = 0xEU, /**< ADC channel 14 */ + ADC_CHANNEL_15 = 0xFU, /**< ADC channel 15 */ + ADC_CHANNEL_16 = 0x10U, /**< ADC channel 16 */ + ADC_CHANNEL_17 = 0x11U, /**< ADC channel 17 */ + ADC_CHANNEL_18 = 0x12U, /**< ADC channel 18 */ } adc_channel_t; /** *@brief ADC sampling times */ typedef enum { - ADC_SAMPLETIME_1 = 0x0, /**< ADC sampling times 1 clk */ - ADC_SAMPLETIME_2 = 0x1, /**< ADC sampling times 2 clk */ - ADC_SAMPLETIME_4 = 0x2, /**< ADC sampling times 4 clk */ - ADC_SAMPLETIME_15 = 0x3, /**< ADC sampling times 15 clk */ + ADC_SAMPLETIME_1 = 0x0U, /**< ADC sampling times 1 clk */ + ADC_SAMPLETIME_2 = 0x1U, /**< ADC sampling times 2 clk */ + ADC_SAMPLETIME_4 = 0x2U, /**< ADC sampling times 4 clk */ + ADC_SAMPLETIME_15 = 0x3U, /**< ADC sampling times 15 clk */ } adc_samp_t; /** - *@brief ADC rank into normal group + *@brief ADC index channel in normal group */ typedef enum { - ADC_NCH_RANK_1 = 0x1, /**< ADC normal channel rank 1 */ - ADC_NCH_RANK_2 = 0x2, /**< ADC normal channel rank 2 */ - ADC_NCH_RANK_3 = 0x3, /**< ADC normal channel rank 3 */ - ADC_NCH_RANK_4 = 0x4, /**< ADC normal channel rank 4 */ - ADC_NCH_RANK_5 = 0x5, /**< ADC normal channel rank 5 */ - ADC_NCH_RANK_6 = 0x6, /**< ADC normal channel rank 6 */ - ADC_NCH_RANK_7 = 0x7, /**< ADC normal channel rank 7 */ - ADC_NCH_RANK_8 = 0x8, /**< ADC normal channel rank 8 */ - ADC_NCH_RANK_9 = 0x9, /**< ADC normal channel rank 9 */ - ADC_NCH_RANK_10 = 0xA, /**< ADC normal channel rank 10 */ - ADC_NCH_RANK_11 = 0xB, /**< ADC normal channel rank 11 */ - ADC_NCH_RANK_12 = 0xC, /**< ADC normal channel rank 12 */ - ADC_NCH_RANK_13 = 0xD, /**< ADC normal channel rank 13 */ - ADC_NCH_RANK_14 = 0xE, /**< ADC normal channel rank 14 */ - ADC_NCH_RANK_15 = 0xF, /**< ADC normal channel rank 15 */ - ADC_NCH_RANK_16 = 0x10, /**< ADC normal channel rank 16 */ -} adc_nch_rank_t; - -/** - * @brief ADC rank into insert group + ADC_NCH_IDX_1 = 0x1U, /**< ADC normal channel index 1 */ + ADC_NCH_IDX_2 = 0x2U, /**< ADC normal channel index 2 */ + ADC_NCH_IDX_3 = 0x3U, /**< ADC normal channel index 3 */ + ADC_NCH_IDX_4 = 0x4U, /**< ADC normal channel index 4 */ + ADC_NCH_IDX_5 = 0x5U, /**< ADC normal channel index 5 */ + ADC_NCH_IDX_6 = 0x6U, /**< ADC normal channel index 6 */ + ADC_NCH_IDX_7 = 0x7U, /**< ADC normal channel index 7 */ + ADC_NCH_IDX_8 = 0x8U, /**< ADC normal channel index 8 */ + ADC_NCH_IDX_9 = 0x9U, /**< ADC normal channel index 9 */ + ADC_NCH_IDX_10 = 0xAU, /**< ADC normal channel index 10 */ + ADC_NCH_IDX_11 = 0xBU, /**< ADC normal channel index 11 */ + ADC_NCH_IDX_12 = 0xCU, /**< ADC normal channel index 12 */ + ADC_NCH_IDX_13 = 0xDU, /**< ADC normal channel index 13 */ + ADC_NCH_IDX_14 = 0xEU, /**< ADC normal channel index 14 */ + ADC_NCH_IDX_15 = 0xFU, /**< ADC normal channel index 15 */ + ADC_NCH_IDX_16 = 0x10U, /**< ADC normal channel index 16 */ +} adc_nch_idx_t; + +/** + * @brief ADC index channel in insert group */ typedef enum { - ADC_ICH_RANK_1 = 0x1, /**< ADC insert channel rank 1 */ - ADC_ICH_RANK_2 = 0x2, /**< ADC insert channel rank 2 */ - ADC_ICH_RANK_3 = 0x3, /**< ADC insert channel rank 3 */ - ADC_ICH_RANK_4 = 0x4, /**< ADC insert channel rank 4 */ -} adc_ich_rank_t; + ADC_ICH_IDX_1 = 0x1U, /**< ADC insert channel index 1 */ + ADC_ICH_IDX_2 = 0x2U, /**< ADC insert channel index 2 */ + ADC_ICH_IDX_3 = 0x3U, /**< ADC insert channel index 3 */ + ADC_ICH_IDX_4 = 0x4U, /**< ADC insert channel index 4 */ +} adc_ich_idx_t; /** * @brief ADC analog watchdog mode */ typedef enum { - ADC_ANAWTD_NONE = 0x0, /**< No watch dog */ - ADC_ANAWTD_SING_NM = 0x800200, /**< One normal channel watch dog */ - ADC_ANAWTD_SING_IST = 0x400200, /**< One inset channel Injec watch dog */ - ADC_ANAWTD_SING_NMIST = 0xC00200, /**< One normal and inset channel watch dog */ - ADC_ANAWTD_ALL_NM = 0x800000, /**< All normal channel watch dog */ - ADC_ANAWTD_ALL_IST = 0x400000, /**< All inset channel watch dog */ - ADC_ANAWTD_ALL_NMIST = 0xC00000, /**< All normal and inset channel watch dog */ -} adc_ana_wtd_t; + ADC_ANAWTD_NONE = 0x0U, /**< No watch dog */ + ADC_ANAWTD_SING_NM = 0x800200U, /**< One normal channel watch dog */ + ADC_ANAWTD_SING_IST = 0x400200U, /**< One insert channel Injec watch dog */ + ADC_ANAWTD_SING_NMIST = 0xC00200U, /**< One normal and insert channel watch dog */ + ADC_ANAWTD_ALL_NM = 0x800000U, /**< All normal channel watch dog */ + ADC_ANAWTD_ALL_IST = 0x400000U, /**< All insert channel watch dog */ + ADC_ANAWTD_ALL_NMIST = 0xC00000U, /**< All normal and insert channel watch dog */ +} adc_ana_wdg_t; /** * @brief ADC Event type @@ -170,9 +168,9 @@ typedef enum { * @brief ADC interrupts definition */ typedef enum { - ADC_IT_NCH = (1U << 5), /**< ADC it normal */ + ADC_IT_NCH = (1U << 5), /**< ADC it normal */ ADC_IT_AWD = (1U << 6), /**< ADC it awd */ - ADC_IT_ICH = (1U << 7), /**< ADC it insert */ + ADC_IT_ICH = (1U << 7), /**< ADC it insert */ ADC_IT_OVR = (1U << 26), /**< ADC it overring */ } adc_it_t; @@ -182,118 +180,118 @@ typedef enum { typedef enum { ADC_FLAG_AWD = (1U << 0), /**perh->CON1, ADC_CON1_ADCEN_MSK)) -#define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) -#define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) -#define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) -#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) -#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) -#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) -#define ADC_NETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, (mode) << ADC_CON1_NETS_POSS)) -#define ADC_IETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, (mode) << ADC_CON1_IETS_POSS)) -#define ADC_NETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, 0 << ADC_CON1_NETS_POSS)) -#define ADC_IETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, 0 << ADC_CON1_IETS_POSS)) +#define ADC_ENABLE(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) +#define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) +#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) +#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_NETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, (mode) << ADC_CON1_NETS_POSS)) +#define ADC_IETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, (mode) << ADC_CON1_IETS_POSS)) +#define ADC_NETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, 0 << ADC_CON1_NETS_POSS)) +#define ADC_IETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, 0 << ADC_CON1_IETS_POSS)) +#define ADC_SPEED_HIGH_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK)) +#define ADC_SPEED_HIGH_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK)) +#define ADC_CALIBRATE_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK)) +#define ADC_CALIBRATE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK)) /** * @} */ @@ -418,15 +422,13 @@ typedef struct { /** @defgroup ADC_Private_Macros ADC Private Macros * @{ */ -#define IS_ADC_ICH_RANK_TYPE(x) ((x) <= ADC_ICH_RANK_4) -#define IS_ADC_NCH_RANK_TYPE(x) ((x) <= ADC_NCH_RANK_16) +#define IS_ADC_ICH_IDX_TYPE(x) ((x) <= ADC_ICH_IDX_4) +#define IS_ADC_NCH_IDX_TYPE(x) ((x) <= ADC_NCH_IDX_16) #define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ADC_SAMPLETIME_1) || \ ((x) == ADC_SAMPLETIME_2) || \ ((x) == ADC_SAMPLETIME_4) || \ ((x) == ADC_SAMPLETIME_15)) #define IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_18) -#define IS_ADC_SCAN_MODE_TYPE(x) (((x) == DISABLE) || \ - ((x) == ENABLE)) #define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ADC_DATAALIGN_RIGHT) || \ ((x) == ADC_DATAALIGN_LEFT)) #define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ADC_ANAWTD_NONE) || \ @@ -457,16 +459,16 @@ typedef struct { #define IS_ADC_NEG_REF_VOLTAGE_TYPE(x) (((x) == ADC_NEG_REF_VSS ) || \ ((x) == ADC_NEG_REF_VREFN )) #define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ADC_POS_REF_VDD) || \ - ((x) == ADC_POS_REF_2_V) || \ + ((x) == ADC_POS_REF_2V) || \ ((x) == ADC_POS_REF_VREEFP) || \ ((x) == ADC_POS_REF_VREEFP_BUF)) -#define IS_ADC_NCH_LEN_TYPE(x) ((x) <= ADC_NCH_LEN_16) -#define IS_ADC_NBR_OF_IST_TYPE(x) ((x) <= ADC_ICH_LEN_4) -#define IS_ADC_DISC_NBR_TYPE(x) ((x) <= ADC_DISC_NBR_8) -#define IS_ADC_CONV_RES_TYPE(x) (((x) == ADC_CONV_RES_12) || \ - ((x) == ADC_CONV_RES_6) || \ - ((x) == ADC_CONV_RES_8) || \ - ((x) == ADC_CONV_RES_10)) +#define IS_ADC_NCH_NR_TYPE(x) ((x) <= ADC_NCH_NR_16) +#define IS_ADC_ICH_NR_TYPE(x) ((x) <= ADC_ICH_NR_4) +#define IS_ADC_DISC_NR_TYPE(x) ((x) <= ADC_DISC_NR_8) +#define IS_ADC_CONV_BIT_TYPE(x) (((x) == ADC_CONV_BIT_12) || \ + ((x) == ADC_CONV_BIT_6) || \ + ((x) == ADC_CONV_BIT_8) || \ + ((x) == ADC_CONV_BIT_10)) #define IS_ADC_TYPE(x) (((x) == ADC0) || \ ((x) == ADC1)) #define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ADC_NCHESEL_MODE_ALL) || \ @@ -503,8 +505,9 @@ ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh); ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh); #ifdef ALD_DMA ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh); +ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel); ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config); +ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config); #endif uint32_t ald_adc_normal_get_value(adc_handle_t *hperh); ald_status_t ald_adc_insert_start(adc_handle_t *hperh); @@ -512,7 +515,7 @@ ald_status_t ald_adc_insert_stop(adc_handle_t *hperh); ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh); ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh); -uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank); +uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t ih_rank); void ald_adc_irq_handler(adc_handle_t *hperh); /** * @} diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h index 700385cdbc2eb7e4212488756bdcf3999b5db3c5..ce23ba73e9f8b1ca26a44806199a942859af4be4 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h @@ -35,8 +35,8 @@ extern "C" { /** @defgroup BKPC_Public_Macros BKPC Public Macros * @{ */ -#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0)) -#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55)) +#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0U)) +#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55U)) #define BKPC_LRC_ENABLE() \ do { \ BKPC_UNLOCK(); \ @@ -99,32 +99,33 @@ do { \ * @brief BKPC preipheral clock select. */ typedef enum { - BKPC_PREH_CLK_LOSM = 0x0, /**< LOSM */ - BKPC_PREH_CLK_LRC = 0x1, /**< LRC */ - BKPC_PREH_CLK_HRC_1M = 0x2, /**< HRC down to 1MHz */ - BKPC_PREH_CLK_HOSC_1M = 0x3, /**< HOSC down to 1MHz */ + BKPC_PREH_CLK_LOSM = 0x0U, /**< LOSM */ + BKPC_PREH_CLK_LRC = 0x1U, /**< LRC */ + BKPC_PREH_CLK_HRC_1M = 0x2U, /**< HRC down to 1MHz */ + BKPC_PREH_CLK_HOSC_1M = 0x3U, /**< HOSC down to 1MHz */ } bkpc_preh_clk_t; /** * @brief Standby wakeup port select */ typedef enum { - PMU_STANDBY_PORT_SEL_PA0 = 0x0, /**< PA0 */ - PMU_STANDBY_PORT_SEL_PA1 = 0x1, /**< PA1 */ - PMU_STANDBY_PORT_SEL_PA2 = 0x2, /**< PA2 */ - PMU_STANDBY_PORT_SEL_PA3 = 0x3, /**< PA3 */ - PMU_STANDBY_PORT_SEL_PA4 = 0x4, /**< PA4 */ - PMU_STANDBY_PORT_SEL_PA5 = 0x5, /**< PA5 */ - PMU_STANDBY_PORT_SEL_PA6 = 0x6, /**< PA6 */ - PMU_STANDBY_PORT_SEL_PA7 = 0x7, /**< PA7 */ + PMU_STANDBY_PORT_SEL_PA0 = 0x0U, /**< Wakeup by PA0 */ + PMU_STANDBY_PORT_SEL_PA1 = 0x1U, /**< Wakeup by PA1 */ + PMU_STANDBY_PORT_SEL_PA2 = 0x2U, /**< Wakeup by PA2 */ + PMU_STANDBY_PORT_SEL_PA3 = 0x3U, /**< Wakeup by PA3 */ + PMU_STANDBY_PORT_SEL_PA4 = 0x4U, /**< Wakeup by PA4 */ + PMU_STANDBY_PORT_SEL_PA5 = 0x5U, /**< Wakeup by PA5 */ + PMU_STANDBY_PORT_SEL_PA6 = 0x6U, /**< Wakeup by PA6 */ + PMU_STANDBY_PORT_SEL_PA7 = 0x7U, /**< Wakeup by PA7 */ + PMU_STANDBY_PORT_SEL_NONE = 0xFU, /**< Wakeup by other source */ } bkpc_wakeup_port_t; /** * @brief Standby wakeup level */ typedef enum { - PMU_STANDBY_LEVEL_HIGH = 0x0, /**< PA0 */ - PMU_STANDBY_LEVEL_LOW = 0x1, /**< PA1 */ + PMU_STANDBY_LEVEL_HIGH = 0x0U, /**< High level */ + PMU_STANDBY_LEVEL_LOW = 0x1U, /**< Low level */ } bkpc_wakeup_level_t; /** @@ -142,7 +143,8 @@ typedef enum { ((x) == PMU_STANDBY_PORT_SEL_PA4) || \ ((x) == PMU_STANDBY_PORT_SEL_PA5) || \ ((x) == PMU_STANDBY_PORT_SEL_PA6) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA7)) + ((x) == PMU_STANDBY_PORT_SEL_PA7) || \ + ((x) == PMU_STANDBY_PORT_SEL_NONE)) #define IS_BKPC_WAKEUP_LEVEL(x) (((x) == PMU_STANDBY_LEVEL_HIGH) || \ ((x) == PMU_STANDBY_LEVEL_LOW)) #define IS_BKPC_PREH_CLOCK(x) (((x) == BKPC_PREH_CLK_LOSM) || \ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h index 9375b835a8201e4d807409549c5a1e8cf371de92..bd861b2d04983f71954055d120d8ebe572b952de 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h @@ -36,17 +36,12 @@ extern "C" { * @{ */ extern uint32_t ald_calc_sqrt(uint32_t data); -extern uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder); -extern int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder); -extern flag_status_t ald_calc_get_dz_status(void); /** * @} */ - /** * @} */ - /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h index 9999ccd675b0d0bdb9ccdd93c75ae6c9945bb03e..196094eaaa2f26a761d5c5fc4edd50ff04240070 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h @@ -37,145 +37,149 @@ extern "C" { * @brief ALD State structures definition */ typedef enum { - CAN_STATE_RESET = 0x00, /**< CAN not yet initialized or disabled */ - CAN_STATE_READY = 0x01, /**< CAN initialized and ready for use */ - CAN_STATE_BUSY = 0x02, /**< CAN process is ongoing */ - CAN_STATE_BUSY_TX = 0x11, /**< CAN process is ongoing */ - CAN_STATE_BUSY_RX = 0x21, /**< CAN process is ongoing */ - CAN_STATE_BUSY_TX_RX = 0x31, /**< CAN process is ongoing */ - CAN_STATE_TIMEOUT = 0x03, /**< CAN in Timeout state */ - CAN_STATE_ERROR = 0x04, /**< CAN error state */ + CAN_STATE_RESET = 0x00U, /**< CAN not yet initialized or disabled */ + CAN_STATE_READY = 0x01U, /**< CAN initialized and ready for use */ + CAN_STATE_BUSY = 0x02U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX = 0x11U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_RX0 = 0x21U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_RX1 = 0x41U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX_RX0 = 0x31U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX_RX1 = 0x51U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_RX0_RX1 = 0x61U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX_RX0_RX1 = 0x71U, /**< CAN process is ongoing */ + CAN_STATE_TIMEOUT = 0x04U, /**< CAN in Timeout state */ + CAN_STATE_ERROR = 0x08U, /**< CAN error state */ } can_state_t; /** * @brief CAN Error Code */ typedef enum { - CAN_ERROR_NONE = 0x00, /**< No error */ - CAN_ERROR_EWG = 0x01, /**< EWG error */ - CAN_ERROR_EPV = 0x02, /**< EPV error */ - CAN_ERROR_BOF = 0x04, /**< BOF error */ - CAN_ERROR_STF = 0x08, /**< Stuff error */ - CAN_ERROR_FOR = 0x10, /**< Form error */ - CAN_ERROR_ACK = 0x20, /**< Acknowledgment error */ - CAN_ERROR_BR = 0x40, /**< Bit recessive */ - CAN_ERROR_BD = 0x80, /**< LEC dominant */ - CAN_ERROR_CRC = 0x100, /**< LEC transfer error */ - CAN_ERROR_UNK = 0x200, /**< Unknown error */ + CAN_ERROR_NONE = 0x00U, /**< No error */ + CAN_ERROR_EWG = 0x01U, /**< EWG error */ + CAN_ERROR_EPV = 0x02U, /**< EPV error */ + CAN_ERROR_BOF = 0x04U, /**< BOF error */ + CAN_ERROR_STF = 0x08U, /**< Stuff error */ + CAN_ERROR_FOR = 0x10U, /**< Form error */ + CAN_ERROR_ACK = 0x20U, /**< Acknowledgment error */ + CAN_ERROR_BR = 0x40U, /**< Bit recessive */ + CAN_ERROR_BD = 0x80U, /**< LEC dominant */ + CAN_ERROR_CRC = 0x100U, /**< LEC transfer error */ + CAN_ERROR_UNK = 0x200U, /**< Unknown error */ } can_error_t; /** * @brief CAN Operating Mode */ typedef enum { - CAN_MODE_NORMAL = 0x00, /**< Normal mode */ - CAN_MODE_LOOPBACK = 0x01, /**< Loopback mode */ - CAN_MODE_SILENT = 0x02, /**< Silent mode */ - CAN_MODE_SILENT_LOOPBACK = 0x03, /**< Loopback combined with silent mode */ + CAN_MODE_NORMAL = 0x00U, /**< Normal mode */ + CAN_MODE_LOOPBACK = 0x01U, /**< Loopback mode */ + CAN_MODE_SILENT = 0x02U, /**< Silent mode */ + CAN_MODE_SILENT_LOOPBACK = 0x03U, /**< Loopback combined with silent mode */ } can_operate_mode_t; /** * @brief CAN Synchronization Jump Width */ typedef enum { - CAN_SJW_1 = 0x0, /**< 1 time quantum */ - CAN_SJW_2 = 0x1, /**< 2 time quantum */ - CAN_SJW_3 = 0x2, /**< 3 time quantum */ - CAN_SJW_4 = 0x3, /**< 4 time quantum */ + CAN_SJW_1 = 0x0U, /**< 1 time quantum */ + CAN_SJW_2 = 0x1U, /**< 2 time quantum */ + CAN_SJW_3 = 0x2U, /**< 3 time quantum */ + CAN_SJW_4 = 0x3U, /**< 4 time quantum */ } can_sjw_t; /** * @brief CAN Time Quantum in Bit Segment 1 */ typedef enum { - CAN_SEG1_1 = 0x0, /**< 1 time quantum */ - CAN_SEG1_2 = 0x1, /**< 2 time quantum */ - CAN_SEG1_3 = 0x2, /**< 3 time quantum */ - CAN_SEG1_4 = 0x3, /**< 4 time quantum */ - CAN_SEG1_5 = 0x4, /**< 5 time quantum */ - CAN_SEG1_6 = 0x5, /**< 6 time quantum */ - CAN_SEG1_7 = 0x6, /**< 7 time quantum */ - CAN_SEG1_8 = 0x7, /**< 8 time quantum */ - CAN_SEG1_9 = 0x8, /**< 9 time quantum */ - CAN_SEG1_10 = 0x9, /**< 10 time quantum */ - CAN_SEG1_11 = 0xA, /**< 11 time quantum */ - CAN_SEG1_12 = 0xB, /**< 12 time quantum */ - CAN_SEG1_13 = 0xC, /**< 13 time quantum */ - CAN_SEG1_14 = 0xD, /**< 14 time quantum */ - CAN_SEG1_15 = 0xE, /**< 15 time quantum */ - CAN_SEG1_16 = 0xF, /**< 16 time quantum */ + CAN_SEG1_1 = 0x0U, /**< 1 time quantum */ + CAN_SEG1_2 = 0x1U, /**< 2 time quantum */ + CAN_SEG1_3 = 0x2U, /**< 3 time quantum */ + CAN_SEG1_4 = 0x3U, /**< 4 time quantum */ + CAN_SEG1_5 = 0x4U, /**< 5 time quantum */ + CAN_SEG1_6 = 0x5U, /**< 6 time quantum */ + CAN_SEG1_7 = 0x6U, /**< 7 time quantum */ + CAN_SEG1_8 = 0x7U, /**< 8 time quantum */ + CAN_SEG1_9 = 0x8U, /**< 9 time quantum */ + CAN_SEG1_10 = 0x9U, /**< 10 time quantum */ + CAN_SEG1_11 = 0xAU, /**< 11 time quantum */ + CAN_SEG1_12 = 0xBU, /**< 12 time quantum */ + CAN_SEG1_13 = 0xCU, /**< 13 time quantum */ + CAN_SEG1_14 = 0xDU, /**< 14 time quantum */ + CAN_SEG1_15 = 0xEU, /**< 15 time quantum */ + CAN_SEG1_16 = 0xFU, /**< 16 time quantum */ } can_seg1_t; /** * @brief CAN Time Quantum in Bit Segment 2 */ typedef enum { - CAN_SEG2_1 = 0x0, /**< 1 time quantum */ - CAN_SEG2_2 = 0x1, /**< 2 time quantum */ - CAN_SEG2_3 = 0x2, /**< 3 time quantum */ - CAN_SEG2_4 = 0x3, /**< 4 time quantum */ - CAN_SEG2_5 = 0x4, /**< 5 time quantum */ - CAN_SEG2_6 = 0x5, /**< 6 time quantum */ - CAN_SEG2_7 = 0x6, /**< 7 time quantum */ - CAN_SEG2_8 = 0x7, /**< 8 time quantum */ + CAN_SEG2_1 = 0x0U, /**< 1 time quantum */ + CAN_SEG2_2 = 0x1U, /**< 2 time quantum */ + CAN_SEG2_3 = 0x2U, /**< 3 time quantum */ + CAN_SEG2_4 = 0x3U, /**< 4 time quantum */ + CAN_SEG2_5 = 0x4U, /**< 5 time quantum */ + CAN_SEG2_6 = 0x5U, /**< 6 time quantum */ + CAN_SEG2_7 = 0x6U, /**< 7 time quantum */ + CAN_SEG2_8 = 0x7U, /**< 8 time quantum */ } can_seg2_t; /** * @brief CAN Filter Mode */ typedef enum { - CAN_FILTER_MODE_MASK = 0x0, /**< Identifier mask mode */ - CAN_FILTER_MODE_LIST = 0x1, /**< Identifier list mode */ + CAN_FILTER_MODE_MASK = 0x0U, /**< Identifier mask mode */ + CAN_FILTER_MODE_LIST = 0x1U, /**< Identifier list mode */ } can_filter_mode_t; /** * @brief CAN Filter Scale */ typedef enum { - CAN_FILTER_SCALE_16 = 0x0, /**< Two 16-bit filters */ - CAN_FILTER_SCALE_32 = 0x1, /**< One 32-bit filter */ + CAN_FILTER_SCALE_16 = 0x0U, /**< Two 16-bit filters */ + CAN_FILTER_SCALE_32 = 0x1U, /**< One 32-bit filter */ } can_filter_scale_t; /** * @brief CAN Filter fifo */ typedef enum { - CAN_FILTER_FIFO0 = 0x0, /**< FIFO 0 assignment for filter */ - CAN_FILTER_FIFO1 = 0x1, /**< FIFO 1 assignment for filter */ + CAN_FILTER_FIFO0 = 0x0U, /**< FIFO 0 assignment for filter */ + CAN_FILTER_FIFO1 = 0x1U, /**< FIFO 1 assignment for filter */ } can_filter_fifo_t; /** * @brief CAN Identifier Type */ typedef enum { - CAN_ID_STD = 0x0, /**< Standard Id */ - CAN_ID_EXT = 0x1, /**< Extended Id */ + CAN_ID_STD = 0x0U, /**< Standard Id */ + CAN_ID_EXT = 0x1U, /**< Extended Id */ } can_id_type_t; /** * @brief CAN Remote Transmission Request */ typedef enum { - CAN_RTR_DATA = 0x0, /**< Data frame */ - CAN_RTR_REMOTE = 0x1, /**< Remote frame */ + CAN_RTR_DATA = 0x0U, /**< Data frame */ + CAN_RTR_REMOTE = 0x1U, /**< Remote frame */ } can_remote_req_t; /** * @brief CAN Transmit Constants */ typedef enum { - CAN_TX_MAILBOX_0 = 0x0, /**< TX mailbox index 0 */ - CAN_TX_MAILBOX_1 = 0x1, /**< TX mailbox index 1 */ - CAN_TX_MAILBOX_2 = 0x2, /**< TX mailbox index 2 */ - CAN_TX_MAILBOX_NONE = 0x3, /**< MailBox can't be used */ + CAN_TX_MAILBOX_0 = 0x0U, /**< TX mailbox index 0 */ + CAN_TX_MAILBOX_1 = 0x1U, /**< TX mailbox index 1 */ + CAN_TX_MAILBOX_2 = 0x2U, /**< TX mailbox index 2 */ + CAN_TX_MAILBOX_NONE = 0x3U, /**< MailBox can't be used */ } can_tx_mailbox_t; /** * @brief CAN Receive fifo Number */ typedef enum { - CAN_RX_FIFO0 = 0x0, /**< CAN fifo 0 used to receive */ - CAN_RX_FIFO1 = 0x1, /**< CAN fifo 1 used to receive */ + CAN_RX_FIFO0 = 0x0U, /**< CAN fifo 0 used to receive */ + CAN_RX_FIFO1 = 0x1U, /**< CAN fifo 1 used to receive */ } can_rx_fifo_t; /** @@ -237,7 +241,6 @@ typedef struct { can_filter_mode_t mode; /**< Specifies the filter mode to be initialized. */ can_filter_scale_t scale; /**< Specifies the filter scale. */ type_func_t active; /**< Enable or disable the filter. */ - uint32_t bank_number; /**< Select the start slave bank filter. */ } can_filter_t; /** @@ -290,14 +293,15 @@ typedef struct { typedef struct can_handle_s { CAN_TypeDef *perh; /**< Register base address */ can_init_t init; /**< CAN required parameters */ - can_rx_msg_t *rx_msg; /**< Pointer to receive message */ + can_rx_msg_t *rx0_msg; /**< Pointer to receive message from FIFO0 */ + can_rx_msg_t *rx1_msg; /**< Pointer to receive message from FIFO1 */ lock_state_t lock; /**< CAN locking object */ can_state_t state; /**< CAN communication state */ can_error_t err; /**< CAN Error code */ - void (*tx_cplt_cbk)(struct can_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct can_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct can_handle_s *arg); /**< error callback */ + void (*tx_cplt_cbk)(struct can_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct can_handle_s *arg, can_rx_fifo_t num); /**< Rx completed callback */ + void (*error_cbk)(struct can_handle_s *arg); /**< error callback */ } can_handle_t; /** * @} @@ -310,8 +314,8 @@ typedef struct can_handle_s { #define CAN_RX_MSG_PENDING(x, y) (((y) == CAN_RX_FIFO0) ? \ (READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK))) #define CAN_DBG_FREEZE(x, y) (MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS)) -#define CAN_TX_STAMP_ENABLE(x) (SET_BIT(hperh->perh->TxMailBox[(x)].TXFCON, CAN_TXFCON0_TXGT_MSK)) -#define CAN_TX_STAMP_DISABLE(x) (CLEAR_BIT(hperh->perh->TxMailBox[(x)].TXFCON, CAN_TXFCON0_TXGT_MSK)) +#define CAN_TX_STAMP_ENABLE(x, y) (SET_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK)) +#define CAN_TX_STAMP_DISABLE(x, y) (CLEAR_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK)) /** * @} */ @@ -341,7 +345,6 @@ typedef struct can_handle_s { ((x) == CAN_ID_EXT)) #define IS_CAN_RTR(x) (((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE)) #define IS_CAN_FIFO(x) (((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1)) -#define IS_CAN_BANKNUMBER(x) ((x) <= 28) #define IS_CAN_TX_MAILBOX(x) ((x) <= CAN_TX_MAILBOX_NONE) #define IS_CAN_STDID(x) ((x) <= ((uint32_t)0x7FF)) #define IS_CAN_EXTID(x) ((x) <= ((uint32_t)0x1FFFFFFF)) @@ -391,9 +394,11 @@ typedef struct can_handle_s { ((x) == CAN_IT_ERR) || \ ((x) == CAN_IT_WK) || \ ((x) == CAN_IT_SLP)) -#define CAN_TIMEOUT_VALUE 100 +#define CAN_TIMEOUT_VALUE 100 #define CAN_STATE_TX_MASK (1U << 4) -#define CAN_STATE_RX_MASK (1U << 5) +#define CAN_STATE_RX0_MASK (1U << 5) +#define CAN_STATE_RX1_MASK (1U << 6) + /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h index 3096ee23f46aa445745c2c84bc1c75204ddab327..400551ae4519ce3e46e8940594a3274d0f045fce 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h @@ -170,22 +170,22 @@ do { \ * @brief CMU state structure definition */ typedef enum { - CMU_CLOCK_HRC = 0x1, /**< HRC */ - CMU_CLOCK_LRC = 0x2, /**< LRC */ - CMU_CLOCK_LOSC = 0x3, /**< LOSC */ - CMU_CLOCK_PLL1 = 0x4, /**< PLL1 */ - CMU_CLOCK_HOSC = 0x5, /**< HOSC */ + CMU_CLOCK_HRC = 0x1U, /**< HRC */ + CMU_CLOCK_LRC = 0x2U, /**< LRC */ + CMU_CLOCK_LOSC = 0x3U, /**< LOSC */ + CMU_CLOCK_PLL1 = 0x4U, /**< PLL1 */ + CMU_CLOCK_HOSC = 0x5U, /**< HOSC */ } cmu_clock_t; /** * @brief PLL1 output clock */ typedef enum { - CMU_PLL1_OUTPUT_36M = 0x0, /**< x9 (36MHz) */ - CMU_PLL1_OUTPUT_48M = 0x1, /**< x12 (48MHz) */ + CMU_PLL1_OUTPUT_36M = 0x0U, /**< x9 (36MHz) */ + CMU_PLL1_OUTPUT_48M = 0x1U, /**< x12 (48MHz) */ #if defined(ES32F36xx) || defined(ES32F39xx) - CMU_PLL1_OUTPUT_72M = 0x2, /**< x18 (72MHz) */ - CMU_PLL1_OUTPUT_96M = 0x3, /**< x24 (96MHz) */ + CMU_PLL1_OUTPUT_72M = 0x2U, /**< x18 (72MHz) */ + CMU_PLL1_OUTPUT_96M = 0x3U, /**< x24 (96MHz) */ #endif } cmu_pll1_output_t; @@ -193,200 +193,217 @@ typedef enum { * @brief PLL1 referance clock */ typedef enum { - CMU_PLL1_INPUT_HRC_6 = 0x0, /**< HRC / 6 */ - CMU_PLL1_INPUT_PLL2 = 0x1, /**< PLL2 */ - CMU_PLL1_INPUT_HOSC = 0x2, /**< HOSC / 1 */ - CMU_PLL1_INPUT_HOSC_2 = 0x3, /**< HOSC / 2 */ - CMU_PLL1_INPUT_HOSC_3 = 0x4, /**< HOSC / 3 */ - CMU_PLL1_INPUT_HOSC_4 = 0x5, /**< HOSC / 4 */ - CMU_PLL1_INPUT_HOSC_5 = 0x6, /**< HOSC / 5 */ - CMU_PLL1_INPUT_HOSC_6 = 0x7, /**< HOSC / 6 */ + CMU_PLL1_INPUT_HRC_6 = 0x0U, /**< HRC / 6 */ + CMU_PLL1_INPUT_PLL2 = 0x1U, /**< PLL2 */ + CMU_PLL1_INPUT_HOSC = 0x2U, /**< HOSC / 1 */ + CMU_PLL1_INPUT_HOSC_2 = 0x3U, /**< HOSC / 2 */ + CMU_PLL1_INPUT_HOSC_3 = 0x4U, /**< HOSC / 3 */ + CMU_PLL1_INPUT_HOSC_4 = 0x5U, /**< HOSC / 4 */ + CMU_PLL1_INPUT_HOSC_5 = 0x6U, /**< HOSC / 5 */ + CMU_PLL1_INPUT_HOSC_6 = 0x7U, /**< HOSC / 6 */ } cmu_pll1_input_t; /** * @brief HOSC range */ typedef enum { - CMU_HOSC_2M = 0x0, /**< 0~2MHz */ - CMU_HOSC_4M = 0x1, /**< 2~4MHz */ - CMU_HOSC_8M = 0x2, /**< 4~8MHz */ - CMU_HOSC_16M = 0x3, /**< 8~16MHz */ - CMU_HOSC_24M = 0x4, /**< 16~24MHz */ + CMU_HOSC_2M = 0x0U, /**< 0~2MHz */ + CMU_HOSC_4M = 0x1U, /**< 2~4MHz */ + CMU_HOSC_8M = 0x2U, /**< 4~8MHz */ + CMU_HOSC_16M = 0x3U, /**< 8~16MHz */ + CMU_HOSC_24M = 0x4U, /**< 16~24MHz */ } cmu_hosc_range_t; /** - * @brief Auto-calibrate input + * @brief Safe clock source type */ typedef enum { - CMU_AUTO_CALIB_INPUT_LOSE = 0x0, /**< LOSC */ - CMU_AUTO_CALIB_INPUT_HOSE = 0x1, /**< HOSC */ -} cmu_auto_calib_input_t; - -/** - * @brief Auto-calibrate output - */ -typedef enum { - CMU_AUTO_CALIB_OUTPUT_24M = 0x0, /**< 2MHz */ - CMU_AUTO_CALIB_OUTPUT_2M = 0x1, /**< 2MHz */ -} cmu_auto_calib_output_t; + CMU_SAFE_CLK_HOSC = 0x0U, /**< HOSC */ + CMU_SAFE_CLK_LOSC = 0x1U, /**< LOSC */ + CMU_SAFE_CLK_PLL = 0x2U, /**< PLL */ +} cmu_clock_safe_type_t; /** * @brief Frequency division select bit */ typedef enum { - CMU_DIV_1 = 0x0, /**< Division by 1 */ - CMU_DIV_2 = 0x1, /**< Division by 2 */ - CMU_DIV_4 = 0x2, /**< Division by 4 */ - CMU_DIV_8 = 0x3, /**< Division by 8 */ - CMU_DIV_16 = 0x4, /**< Division by 16 */ - CMU_DIV_32 = 0x5, /**< Division by 32 */ - CMU_DIV_64 = 0x6, /**< Division by 64 */ - CMU_DIV_128 = 0x7, /**< Division by 128 */ - CMU_DIV_256 = 0x8, /**< Division by 256 */ - CMU_DIV_512 = 0x9, /**< Division by 512 */ - CMU_DIV_1024 = 0xA, /**< Division by 1024 */ - CMU_DIV_2048 = 0xB, /**< Division by 2048 */ - CMU_DIV_4096 = 0xC, /**< Division by 4096 */ + CMU_DIV_1 = 0x0U, /**< Division by 1 */ + CMU_DIV_2 = 0x1U, /**< Division by 2 */ + CMU_DIV_4 = 0x2U, /**< Division by 4 */ + CMU_DIV_8 = 0x3U, /**< Division by 8 */ + CMU_DIV_16 = 0x4U, /**< Division by 16 */ + CMU_DIV_32 = 0x5U, /**< Division by 32 */ + CMU_DIV_64 = 0x6U, /**< Division by 64 */ + CMU_DIV_128 = 0x7U, /**< Division by 128 */ + CMU_DIV_256 = 0x8U, /**< Division by 256 */ + CMU_DIV_512 = 0x9U, /**< Division by 512 */ + CMU_DIV_1024 = 0xAU, /**< Division by 1024 */ + CMU_DIV_2048 = 0xBU, /**< Division by 2048 */ + CMU_DIV_4096 = 0xCU, /**< Division by 4096 */ } cmu_div_t; /** * @brief Bus type */ typedef enum { - CMU_HCLK_1 = 0x0, /**< AHB1 bus */ - CMU_HCLK_2 = 0x1, /**< AHB2 bus */ - CMU_SYS = 0x2, /**< SYS bus */ - CMU_PCLK_1 = 0x3, /**< APB1 bus */ - CMU_PCLK_2 = 0x4, /**< APB2 bus */ + CMU_HCLK_1 = 0x0U, /**< AHB1 bus */ + CMU_HCLK_2 = 0x1U, /**< AHB2 bus */ + CMU_SYS = 0x2U, /**< SYS bus */ + CMU_PCLK_1 = 0x3U, /**< APB1 bus */ + CMU_PCLK_2 = 0x4U, /**< APB2 bus */ } cmu_bus_t; /** * @brief Output high clock select */ typedef enum { - CMU_OUTPUT_HIGH_SEL_HOSC = 0x0, /**< Select HOSC */ - CMU_OUTPUT_HIGH_SEL_LOSC = 0x1, /**< Select LOSC */ - CMU_OUTPUT_HIGH_SEL_HRC = 0x2, /**< Select HRC */ - CMU_OUTPUT_HIGH_SEL_LRC = 0x3, /**< Select LRC */ - CMU_OUTPUT_HIGH_SEL_HOSM = 0x4, /**< Select HOSM */ - CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5, /**< Select PLL1 */ - CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6, /**< Select PLL2 */ - CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7, /**< Select SYSCLK */ + CMU_OUTPUT_HIGH_SEL_HOSC = 0x0U, /**< Select HOSC */ + CMU_OUTPUT_HIGH_SEL_LOSC = 0x1U, /**< Select LOSC */ + CMU_OUTPUT_HIGH_SEL_HRC = 0x2U, /**< Select HRC */ + CMU_OUTPUT_HIGH_SEL_LRC = 0x3U, /**< Select LRC */ + CMU_OUTPUT_HIGH_SEL_HOSM = 0x4U, /**< Select HOSM */ + CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5U, /**< Select PLL1 */ + CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6U, /**< Select PLL2 */ + CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7U, /**< Select SYSCLK */ } cmu_output_high_sel_t; /** * @brief Output frequency division */ typedef enum { - CMU_OUTPUT_DIV_1 = 0x0, /**< Division by 1 */ - CMU_OUTPUT_DIV_2 = 0x1, /**< Division by 2 */ - CMU_OUTPUT_DIV_4 = 0x2, /**< Division by 4 */ - CMU_OUTPUT_DIV_8 = 0x3, /**< Division by 8 */ - CMU_OUTPUT_DIV_16 = 0x4, /**< Division by 16 */ - CMU_OUTPUT_DIV_32 = 0x5, /**< Division by 32 */ - CMU_OUTPUT_DIV_64 = 0x6, /**< Division by 64 */ - CMU_OUTPUT_DIV_128 = 0x7, /**< Division by 128 */ + CMU_OUTPUT_DIV_1 = 0x0U, /**< Division by 1 */ + CMU_OUTPUT_DIV_2 = 0x1U, /**< Division by 2 */ + CMU_OUTPUT_DIV_4 = 0x2U, /**< Division by 4 */ + CMU_OUTPUT_DIV_8 = 0x3U, /**< Division by 8 */ + CMU_OUTPUT_DIV_16 = 0x4U, /**< Division by 16 */ + CMU_OUTPUT_DIV_32 = 0x5U, /**< Division by 32 */ + CMU_OUTPUT_DIV_64 = 0x6U, /**< Division by 64 */ + CMU_OUTPUT_DIV_128 = 0x7U, /**< Division by 128 */ } cmu_output_high_div_t; /** * @brief Output low clock select */ typedef enum { - CMU_OUTPUT_LOW_SEL_LOSC = 0x0, /**< Select LOSC */ - CMU_OUTPUT_LOW_SEL_LRC = 0x1, /**< Select LRC */ - CMU_OUTPUT_LOW_SEL_LOSM = 0x2, /**< Select LOSM */ - CMU_OUTPUT_LOW_SEL_BUZZ = 0x3, /**< Select BUZZ */ - CMU_OUTPUT_LOW_SEL_ULRC = 0x4, /**< Select ULRC */ + CMU_OUTPUT_LOW_SEL_LOSC = 0x0U, /**< Select LOSC */ + CMU_OUTPUT_LOW_SEL_LRC = 0x1U, /**< Select LRC */ + CMU_OUTPUT_LOW_SEL_LOSM = 0x2U, /**< Select LOSM */ + CMU_OUTPUT_LOW_SEL_BUZZ = 0x3U, /**< Select BUZZ */ + CMU_OUTPUT_LOW_SEL_ULRC = 0x4U, /**< Select ULRC */ } cmu_output_low_sel_t; /** * @brief BUZZ frequency division */ typedef enum { - CMU_BUZZ_DIV_2 = 0x0, /**< Division by 2 */ - CMU_BUZZ_DIV_4 = 0x1, /**< Division by 4 */ - CMU_BUZZ_DIV_8 = 0x2, /**< Division by 8 */ - CMU_BUZZ_DIV_16 = 0x3, /**< Division by 16 */ - CMU_BUZZ_DIV_32 = 0x4, /**< Division by 32 */ - CMU_BUZZ_DIV_64 = 0x5, /**< Division by 64 */ - CMU_BUZZ_DIV_128 = 0x6, /**< Division by 128 */ - CMU_BUZZ_DIV_256 = 0x7, /**< Division by 256 */ + CMU_BUZZ_DIV_2 = 0x0U, /**< Division by 2 */ + CMU_BUZZ_DIV_4 = 0x1U, /**< Division by 4 */ + CMU_BUZZ_DIV_8 = 0x2U, /**< Division by 8 */ + CMU_BUZZ_DIV_16 = 0x3U, /**< Division by 16 */ + CMU_BUZZ_DIV_32 = 0x4U, /**< Division by 32 */ + CMU_BUZZ_DIV_64 = 0x5U, /**< Division by 64 */ + CMU_BUZZ_DIV_128 = 0x6U, /**< Division by 128 */ + CMU_BUZZ_DIV_256 = 0x7U, /**< Division by 256 */ } cmu_buzz_div_t; /** * @brief Low power peripheral clock select */ typedef enum { - CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0, /**< Select PCLK2 */ - CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1, /**< Select PLL1 */ - CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2, /**< Select PLL2 */ - CMU_LP_PERH_CLOCK_SEL_HRC = 0x3, /**< Select HRC */ - CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4, /**< Select HOSC */ - CMU_LP_PERH_CLOCK_SEL_LRC = 0x5, /**< Select LRC */ - CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6, /**< Select LOSC */ - CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7, /**< Select ULRC */ - CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8, /**< Select HRC down to 1MHz */ - CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9, /**< Select HOSC down to 1MHz */ - CMU_LP_PERH_CLOCK_SEL_LOSM = 0xA, /**< Select LOSM */ - CMU_LP_PERH_CLOCK_SEL_HOSM = 0xB, /**< Select HOSM */ + CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0U, /**< Select PCLK2 */ + CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1U, /**< Select PLL1 */ + CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2U, /**< Select PLL2 */ + CMU_LP_PERH_CLOCK_SEL_HRC = 0x3U, /**< Select HRC */ + CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4U, /**< Select HOSC */ + CMU_LP_PERH_CLOCK_SEL_LRC = 0x5U, /**< Select LRC */ + CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6U, /**< Select LOSC */ + CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7U, /**< Select ULRC */ + CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8U, /**< Select HRC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9U, /**< Select HOSC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_LOSM = 0xAU, /**< Select LOSM */ + CMU_LP_PERH_CLOCK_SEL_HOSM = 0xBU, /**< Select HOSM */ } cmu_lp_perh_clock_sel_t; /** * @brief LCD clock select */ typedef enum { - CMU_LCD_SEL_LOSM = 0x0, /**< Select LOSM */ - CMU_LCD_SEL_LOSC = 0x1, /**< Select LOSC */ - CMU_LCD_SEL_LRC = 0x2, /**< Select LRC */ - CMU_LCD_SEL_ULRC = 0x3, /**< Select ULRC */ - CMU_LCD_SEL_HRC_1M = 0x4, /**< Select HRC down to 1MHz */ - CMU_LCD_SEL_HOSC_1M = 0x5, /**< Select HOSC down to 1MHz */ + CMU_LCD_SEL_LOSM = 0x0U, /**< Select LOSM */ + CMU_LCD_SEL_LOSC = 0x1U, /**< Select LOSC */ + CMU_LCD_SEL_LRC = 0x2U, /**< Select LRC */ + CMU_LCD_SEL_ULRC = 0x3U, /**< Select ULRC */ + CMU_LCD_SEL_HRC_1M = 0x4U, /**< Select HRC down to 1MHz */ + CMU_LCD_SEL_HOSC_1M = 0x5U, /**< Select HOSC down to 1MHz */ } cmu_lcd_clock_sel_t; /** * @brief QSPI clock select */ typedef enum { - CMU_QSPI_CLOCK_SEL_PCLK1 = 0x0, /**< Select PCLK1 */ - CMU_QSPI_CLOCK_SEL_HCLK2 = 0x1, /**< Select HCLK2 */ - CMU_QSPI_CLOCK_SEL_HRC = 0x2, /**< Select HRC */ - CMU_QSPI_CLOCK_SEL_HOSC = 0x3, /**< Select HOSC */ - CMU_QSPI_CLOCK_SEL_PLL1 = 0x4, /**< Select PLL1 */ - CMU_QSPI_CLOCK_SEL_HOSM = 0x5, /**< Select HOSC security management */ + CMU_QSPI_CLOCK_SEL_PCLK1 = 0x0U, /**< Select PCLK1 */ + CMU_QSPI_CLOCK_SEL_HCLK2 = 0x1U, /**< Select HCLK2 */ + CMU_QSPI_CLOCK_SEL_HRC = 0x2U, /**< Select HRC */ + CMU_QSPI_CLOCK_SEL_HOSC = 0x3U, /**< Select HOSC */ + CMU_QSPI_CLOCK_SEL_PLL1 = 0x4U, /**< Select PLL1 */ + CMU_QSPI_CLOCK_SEL_HOSM = 0x5U, /**< Select HOSC security management */ } cmu_qspi_clock_sel_t; /** * @brief USB clock select */ typedef enum { - CMU_USB_CLOCK_SEL_HOSC = 0x0, /**< Select HOSC */ - CMU_USB_CLOCK_SEL_HRC = 0x1, /**< Select HRC */ - CMU_USB_CLOCK_SEL_PCLK1 = 0x2, /**< Select PCLK1 */ - CMU_USB_CLOCK_SEL_PLL1 = 0x3, /**< Select PLL1 */ - CMU_USB_CLOCK_SEL_HOSM = 0x4, /**< Select HOSC security management */ + CMU_USB_CLOCK_SEL_HOSC = 0x0U, /**< Select HOSC */ + CMU_USB_CLOCK_SEL_HRC = 0x1U, /**< Select HRC */ + CMU_USB_CLOCK_SEL_PCLK1 = 0x2U, /**< Select PCLK1 */ + CMU_USB_CLOCK_SEL_PLL1 = 0x3U, /**< Select PLL1 */ + CMU_USB_CLOCK_SEL_HOSM = 0x4U, /**< Select HOSC security management */ } cmu_usb_clock_sel_t; /** * @brief USB clock division */ typedef enum { - CMU_USB_DIV_1 = 0x0, /**< Division by 1 */ - CMU_USB_DIV_2 = 0x1, /**< Division by 2 */ - CMU_USB_DIV_4 = 0x2, /**< Division by 4 */ - CMU_USB_DIV_8 = 0x3, /**< Division by 8 */ - CMU_USB_DIV_16 = 0x4, /**< Division by 16 */ - CMU_USB_DIV_32 = 0x5, /**< Division by 32 */ - CMU_USB_DIV_64 = 0x6, /**< Division by 64 */ - CMU_USB_DIV_128 = 0x7, /**< Division by 128 */ - CMU_USB_DIV_256 = 0x8, /**< Division by 256 */ - CMU_USB_DIV_512 = 0x9, /**< Division by 512 */ - CMU_USB_DIV_1024 = 0xA, /**< Division by 1024 */ - CMU_USB_DIV_2048 = 0xB, /**< Division by 2048 */ - CMU_USB_DIV_4096 = 0xC, /**< Division by 4096 */ + CMU_USB_DIV_1 = 0x0U, /**< Division by 1 */ + CMU_USB_DIV_2 = 0x1U, /**< Division by 2 */ + CMU_USB_DIV_4 = 0x2U, /**< Division by 4 */ + CMU_USB_DIV_8 = 0x3U, /**< Division by 8 */ + CMU_USB_DIV_16 = 0x4U, /**< Division by 16 */ + CMU_USB_DIV_32 = 0x5U, /**< Division by 32 */ + CMU_USB_DIV_64 = 0x6U, /**< Division by 64 */ + CMU_USB_DIV_128 = 0x7U, /**< Division by 128 */ + CMU_USB_DIV_256 = 0x8U, /**< Division by 256 */ + CMU_USB_DIV_512 = 0x9U, /**< Division by 512 */ + CMU_USB_DIV_1024 = 0xAU, /**< Division by 1024 */ + CMU_USB_DIV_2048 = 0xBU, /**< Division by 2048 */ + CMU_USB_DIV_4096 = 0xCU, /**< Division by 4096 */ } cmu_usb_div_t; /** * @brief Peripheral clock enable/disable + * @verbatim + In this module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F36xx series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> AD16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + TIMER4 ----> BS16T0 + TIMER5 ----> BS16T1 + TIMER6 ----> GP16C4T0 + TIMER7 ----> GP16C4T1 + + 2. For ES32F393x/ES32F336x/ES32F392x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> GP16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + TIMER4 ----> BS16T0 + TIMER5 ----> BS16T1 + TIMER6 ----> GP16C4T2 + TIMER7 ----> GP16C4T3 + @endverbatim */ typedef enum { CMU_PERH_GPIO = (1U << 0), /**< GPIO */ @@ -400,14 +417,14 @@ typedef enum { CMU_PERH_DMA = (1U << 8), /**< DMA */ CMU_PERH_USB = (1U << 10), /**< USB */ CMU_PERH_ECC = (1U << 11), /**< ECC */ - CMU_PERH_TIM0 = (1U << 0) | (1U << 27), /**< TIM0 */ - CMU_PERH_TIM1 = (1U << 1) | (1U << 27), /**< TIM1 */ - CMU_PERH_TIM2 = (1U << 2) | (1U << 27), /**< TIM2 */ - CMU_PERH_TIM3 = (1U << 3) | (1U << 27), /**< TIM3 */ - CMU_PERH_TIM4 = (1U << 4) | (1U << 27), /**< TIM4 */ - CMU_PERH_TIM5 = (1U << 5) | (1U << 27), /**< TIM5 */ - CMU_PERH_TIM6 = (1U << 6) | (1U << 27), /**< TIM6 */ - CMU_PERH_TIM7 = (1U << 7) | (1U << 27), /**< TIM7 */ + CMU_PERH_TIMER0 = (1U << 0) | (1U << 27), /**< TIMER0 */ + CMU_PERH_TIMER1 = (1U << 1) | (1U << 27), /**< TIMER1 */ + CMU_PERH_TIMER2 = (1U << 2) | (1U << 27), /**< TIMER2 */ + CMU_PERH_TIMER3 = (1U << 3) | (1U << 27), /**< TIMER3 */ + CMU_PERH_TIMER4 = (1U << 4) | (1U << 27), /**< TIMER4 */ + CMU_PERH_TIMER5 = (1U << 5) | (1U << 27), /**< TIMER5 */ + CMU_PERH_TIMER6 = (1U << 6) | (1U << 27), /**< TIMER6 */ + CMU_PERH_TIMER7 = (1U << 7) | (1U << 27), /**< TIMER7 */ CMU_PERH_UART0 = (1U << 8) | (1U << 27), /**< UART0 */ CMU_PERH_UART1 = (1U << 9) | (1U << 27), /**< UART1 */ CMU_PERH_UART2 = (1U << 10) | (1U << 27), /**< UART2 */ @@ -429,27 +446,26 @@ typedef enum { CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), /**< ACMP1 */ CMU_PERH_OPAMP = (1U << 8) | (1U << 28), /**< OPAMP */ CMU_PERH_DAC0 = (1U << 9) | (1U << 28), /**< DAC0 */ - CMU_PERH_ACMP2 = (1U << 11) | (1U << 28), /**< ACMP2 */ + CMU_PERH_ACMP2 = (1U << 11) | (1U << 28), /**< ACMP2 */ CMU_PERH_WWDT = (1U << 12) | (1U << 28), /**< WWDT */ CMU_PERH_LCD = (1U << 13) | (1U << 28), /**< LCD */ CMU_PERH_IWDT = (1U << 14) | (1U << 28), /**< IWDT */ CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */ CMU_PERH_TSENSE = (1U << 16) | (1U << 28), /**< TSENSE */ CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */ - CMU_PERH_BKRPAM = (1U << 18) | (1U << 28), /**< BKPRAM */ CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */ - CMU_PERH_ALL = (0x7FFFFFFF), /**< ALL */ + CMU_PERH_ALL = (0x7FFFFFFFU), /**< ALL */ } cmu_perh_t; /** * @brief CMU interrupt type */ typedef enum { - CMU_LOSC_STOP = 0x0, /**< LOSC STOP INTERRUPT */ - CMU_HOSC_STOP = 0x1, /**< HOSC STOP INTERRUPT */ - CMU_PLL1_UNLOCK = 0x2, /**< PLL1 UNLOCK INTERRUPT */ - CMU_LOSC_START = 0x3, /**< LOSC START INTERRUPT */ - CMU_HOSC_START = 0x4, /**< HOSC START INTERRUPT */ + CMU_LOSC_STOP = 0x0U, /**< LOSC STOP INTERRUPT */ + CMU_HOSC_STOP = 0x1U, /**< HOSC STOP INTERRUPT */ + CMU_PLL1_UNLOCK = 0x2U, /**< PLL1 UNLOCK INTERRUPT */ + CMU_LOSC_START = 0x3U, /**< LOSC START INTERRUPT */ + CMU_HOSC_START = 0x4U, /**< HOSC START INTERRUPT */ } cmu_security_t; /** @@ -475,13 +491,13 @@ typedef enum { * @brief Stop1 clock select type */ typedef enum { - CMU_STOP1_CLOCK_LRC = 0x0, /**< LRC */ - CMU_STOP1_CLOCK_HRC_24M = 0x1, /**< HRC 24MHz */ - CMU_STOP1_CLOCK_HRC_2M = 0x2, /**< HRC 2MHz */ - CMU_STOP1_CLOCK_HRC_1M = 0x3, /**< HRC divides to 1MHz */ - CMU_STOP1_CLOCK_HOSC = 0x4, /**< HOSC */ - CMU_STOP1_CLOCK_HOSC_1M = 0x5, /**< HOSC divides to 1MHz */ - CMU_STOP1_CLOCK_HOSCM = 0x6, /**< HOSC security management */ + CMU_STOP1_CLOCK_LRC = 0x0U, /**< LRC */ + CMU_STOP1_CLOCK_HRC_24M = 0x1U, /**< HRC 24MHz */ + CMU_STOP1_CLOCK_HRC_2M = 0x2U, /**< HRC 2MHz */ + CMU_STOP1_CLOCK_HRC_1M = 0x3U, /**< HRC divides to 1MHz */ + CMU_STOP1_CLOCK_HOSC = 0x4U, /**< HOSC */ + CMU_STOP1_CLOCK_HOSC_1M = 0x5U, /**< HOSC divides to 1MHz */ + CMU_STOP1_CLOCK_HOSCM = 0x6U, /**< HOSC security management */ } cmu_stop1_clock_t; /** @@ -497,10 +513,16 @@ typedef enum { ((x) == CMU_CLOCK_LOSC) || \ ((x) == CMU_CLOCK_PLL1) || \ ((x) == CMU_CLOCK_HOSC)) +#if defined(ES32F36xx) || defined(ES32F39xx) #define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_36M) || \ ((x) == CMU_PLL1_OUTPUT_48M) || \ ((x) == CMU_PLL1_OUTPUT_72M) || \ ((x) == CMU_PLL1_OUTPUT_96M)) +#endif +#ifdef ES32F336x +#define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_36M) || \ + ((x) == CMU_PLL1_OUTPUT_48M)) +#endif #define IS_CMU_PLL1_INPUT(x) (((x) == CMU_PLL1_INPUT_HRC_6) || \ ((x) == CMU_PLL1_INPUT_PLL2) || \ ((x) == CMU_PLL1_INPUT_HOSC) || \ @@ -553,10 +575,9 @@ typedef enum { ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \ ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \ ((x) == CMU_OUTPUT_LOW_SEL_ULRC)) -#define IS_CMU_AUTO_CALIB_INPUT(x) (((x) == CMU_AUTO_CALIB_INPUT_LOSE) || \ - ((x) == CMU_AUTO_CALIB_INPUT_HOSE)) -#define IS_CMU_AUTO_CALIB_OUTPUT(x) (((x) == CMU_AUTO_CALIB_OUTPUT_24M) || \ - ((x) == CMU_AUTO_CALIB_OUTPUT_2M)) +#define IS_CMU_SAFE_CLOCK_TYPE(x) (((x) == CMU_SAFE_CLK_HOSC) || \ + ((x) == CMU_SAFE_CLK_LOSC) || \ + ((x) == CMU_SAFE_CLK_PLL)) #define IS_CMU_BUZZ_DIV(x) (((x) == CMU_BUZZ_DIV_2) || \ ((x) == CMU_BUZZ_DIV_4) || \ ((x) == CMU_BUZZ_DIV_8) || \ @@ -618,14 +639,14 @@ typedef enum { ((x) == CMU_PERH_DMA) || \ ((x) == CMU_PERH_USB) || \ ((x) == CMU_PERH_ECC) || \ - ((x) == CMU_PERH_TIM0) || \ - ((x) == CMU_PERH_TIM1) || \ - ((x) == CMU_PERH_TIM2) || \ - ((x) == CMU_PERH_TIM3) || \ - ((x) == CMU_PERH_TIM4) || \ - ((x) == CMU_PERH_TIM5) || \ - ((x) == CMU_PERH_TIM6) || \ - ((x) == CMU_PERH_TIM7) || \ + ((x) == CMU_PERH_TIMER0) || \ + ((x) == CMU_PERH_TIMER1) || \ + ((x) == CMU_PERH_TIMER2) || \ + ((x) == CMU_PERH_TIMER3) || \ + ((x) == CMU_PERH_TIMER4) || \ + ((x) == CMU_PERH_TIMER5) || \ + ((x) == CMU_PERH_TIMER6) || \ + ((x) == CMU_PERH_TIMER7) || \ ((x) == CMU_PERH_UART0) || \ ((x) == CMU_PERH_UART1) || \ ((x) == CMU_PERH_UART2) || \ @@ -654,7 +675,6 @@ typedef enum { ((x) == CMU_PERH_RTC) || \ ((x) == CMU_PERH_TSENSE) || \ ((x) == CMU_PERH_BKPC) || \ - ((x) == CMU_PERH_BKRPAM ) || \ ((x) == CMU_PERH_DBGC) || \ ((x) == CMU_PERH_ALL)) #define IS_CMU_CLOCK_STATE(x) (((x) == CMU_CLOCK_STATE_HOSCACT) || \ @@ -702,6 +722,7 @@ uint32_t ald_cmu_get_clock(void); /* BUS division control */ void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div); uint32_t ald_cmu_get_hclk1_clock(void); +uint32_t ald_cmu_get_hclk2_clock(void); uint32_t ald_cmu_get_sys_clock(void); uint32_t ald_cmu_get_pclk1_clock(void); uint32_t ald_cmu_get_pclk2_clock(void); @@ -716,6 +737,7 @@ uint32_t ald_cmu_get_pclk2_clock(void); void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status); void ald_cmu_losc_safe_config(type_func_t status); void ald_cmu_pll_safe_config(type_func_t status); +uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type); flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr); void ald_cmu_irq_handler(void); void ald_cmu_irq_cbk(cmu_security_t se); diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h index f38e08f598eb7c56687450036e9decaa88c40573..dcd6761acb7cd6f9e76a91af3f9ca98dcb048cf5 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h @@ -40,38 +40,38 @@ * @brief CRC mode */ typedef enum { - CRC_MODE_CCITT = 0, /**< Ccitt */ - CRC_MODE_8 = 1, /**< Crc8 */ - CRC_MODE_16 = 2, /**< Crc16 */ - CRC_MODE_32 = 3, /**< Crc32 */ + CRC_MODE_CCITT = 0U, /**< Ccitt */ + CRC_MODE_8 = 1U, /**< Crc8 */ + CRC_MODE_16 = 2U, /**< Crc16 */ + CRC_MODE_32 = 3U, /**< Crc32 */ } crc_mode_t; /** * @brief CRC input length */ typedef enum { - CRC_LEN_AUTO = 0, /**< Auto */ - CRC_DATASIZE_8 = 1, /**< Byte */ - CRC_DATASIZE_16 = 2, /**< Half word */ - CRC_DATASIZE_32 = 3, /**< Word */ + CRC_LEN_AUTO = 0U, /**< Auto */ + CRC_DATASIZE_8 = 1U, /**< Byte */ + CRC_DATASIZE_16 = 2U, /**< Half word */ + CRC_DATASIZE_32 = 3U, /**< Word */ } crc_datasize_t; /** * @brief CRC whether write error or no */ typedef enum { - CRC_WERR_NO = 0, /**< No error */ - CRC_WERR_ERR = 1, /**< Error */ + CRC_WERR_NO = 0U, /**< No error */ + CRC_WERR_ERR = 1U, /**< Error */ } crc_werr_t; /** * @brief CRC state structures definition */ typedef enum { - CRC_STATE_RESET = 0x0, /**< Peripheral is not initialized */ - CRC_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - CRC_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - CRC_STATE_ERROR = 0x4, /**< Error */ + CRC_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ + CRC_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + CRC_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + CRC_STATE_ERROR = 0x4U, /**< Error */ } crc_state_t; /** diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h index 9ba0fc438509d469330a653c0329abeecca668bf..f72cb06fc7307a28f4b5ed2cae20c8a2d7097f1e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h @@ -40,119 +40,119 @@ * @brief CRYPT encrypt or decrypt select */ typedef enum { - CRYPT_DECRYPT = 0, /**< Decrypt */ - CRYPT_ENCRYPT = 1, /**< Encrypt */ + CRYPT_DECRYPT = 0U, /**< Decrypt */ + CRYPT_ENCRYPT = 1U, /**< Encrypt */ } crypt_encs_t; /** * @brief CRYPT aes key select */ typedef enum { - CRYPT_BITS_128 = 0, /**< 128bit key for aes */ - CRYPT_BITS_192 = 1, /**< 192bit key for aes */ - CRYPT_BITS_256 = 2, /**< 256bit key for aes */ + CRYPT_BITS_128 = 0U, /**< 128bit key for aes */ + CRYPT_BITS_192 = 1U, /**< 192bit key for aes */ + CRYPT_BITS_256 = 2U, /**< 256bit key for aes */ } crypt_aesks_t; /** * @brief CRYPT mode select */ typedef enum { - CRYPT_MODE_ECB = 0, /**< ECB */ - CRYPT_MODE_CBC = 1, /**< CBC */ - CRYPT_MODE_CTR = 2, /**< CTR */ + CRYPT_MODE_ECB = 0U, /**< ECB */ + CRYPT_MODE_CBC = 1U, /**< CBC */ + CRYPT_MODE_CTR = 2U, /**< CTR */ } crypt_mode_t; /** * @brief CRYPT data type */ typedef enum { - CRYPT_DATA_CHANGE_NO = 0, /**< No exchange */ - CRYPT_DATA_CHANGE_16 = 1, /**< 16bit exchange */ - CRYPT_DATA_CHANGE_8 = 2, /**< 8bit exchange */ - CRYPT_DATA_CHANGE_1 = 3, /**< 1bit exchange */ + CRYPT_DATA_CHANGE_NO = 0U, /**< No exchange */ + CRYPT_DATA_CHANGE_16 = 1U, /**< 16bit exchange */ + CRYPT_DATA_CHANGE_8 = 2U, /**< 8bit exchange */ + CRYPT_DATA_CHANGE_1 = 3U, /**< 1bit exchange */ } crypt_datatype_t; /** * @brief CRYPT des key select */ typedef enum { - CRYPT_KEYS_2 = 0, /**< 2 key for des */ - CRYPT_KEYS_3 = 1, /**< 3 key for des */ - CRYPT_KEYS_1 = 2, /**< 1 key for des */ + CRYPT_KEYS_2 = 0U, /**< 2 key for des */ + CRYPT_KEYS_3 = 1U, /**< 3 key for des */ + CRYPT_KEYS_1 = 2U, /**< 1 key for des */ } crypt_desks_t; /** * @brief CRYPT crypt select */ typedef enum { - CRYPT_CRYSEL_AES = 0, /**< AES */ - CRYPT_CRYSEL_DES = 1, /**< DES */ + CRYPT_CRYSEL_AES = 0U, /**< AES */ + CRYPT_CRYSEL_DES = 1U, /**< DES */ } crypt_crysel_t; /** * @brief CRYPT interrupt */ typedef enum { - CRYPT_IT_IT = 0x80, /**< Interrupt */ + CRYPT_IT_IT = 0x80U, /**< Interrupt */ } crypt_it_t; /** * @brief CRYPT interrupt flag */ typedef enum { - CRYPT_FLAG_AESIF = 0x1, /**< Aes flag */ - CRYPT_FLAG_DESIF = 0x2, /**< Des flag */ - CRYPT_FLAG_DONE = 0x100, /**< Complete flag */ + CRYPT_FLAG_AESIF = 0x1U, /**< Aes flag */ + CRYPT_FLAG_DESIF = 0x2U, /**< Des flag */ + CRYPT_FLAG_DONE = 0x100U, /**< Complete flag */ } crypt_flag_t; /** * @brief CRYPT key select */ typedef enum { - CRYPT_AES_BITS_128 = 0x4, /**< 128bit key of aes */ - CRYPT_AES_BITS_192 = 0x6, /**< 192bit key of aes */ - CRYPT_AES_BITS_256 = 0x8, /**< 192bit key of ase */ - CRYPT_DES_KEYS_1 = 0x12, /**< 1 key of des */ - CRYPT_DES_KEYS_2 = 0x14, /**< 2 key of des */ - CRYPT_DES_KEYS_3 = 0x16, /**< 3 key of des */ + CRYPT_AES_BITS_128 = 0x4U, /**< 128bit key of aes */ + CRYPT_AES_BITS_192 = 0x6U, /**< 192bit key of aes */ + CRYPT_AES_BITS_256 = 0x8U, /**< 192bit key of ase */ + CRYPT_DES_KEYS_1 = 0x12U, /**< 1 key of des */ + CRYPT_DES_KEYS_2 = 0x14U, /**< 2 key of des */ + CRYPT_DES_KEYS_3 = 0x16U, /**< 3 key of des */ } crypt_ks_t; /** * @brief CRYPT state structures definition */ typedef enum { - CRYPT_STATE_RESET = 0x0, /**< Peripheral is not initialized */ - CRYPT_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - CRYPT_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - CRYPT_STATE_ERROR = 0x4, /**< Error */ + CRYPT_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ + CRYPT_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + CRYPT_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + CRYPT_STATE_ERROR = 0x4U, /**< Error */ } crypt_state_t; /** * @brief CRYPT key length */ typedef enum { - KEY_2_LEN = 2, /**< Key's lenth is 2 */ - KEY_4_LEN = 4, /**< Key's lenth is 4 */ - KEY_6_LEN = 6, /**< Key's lenth is 6 */ - KEY_8_LEN = 8, /**< Key's lenth is 8 */ + KEY_2_LEN = 2U, /**< Key's lenth is 2 */ + KEY_4_LEN = 4U, /**< Key's lenth is 4 */ + KEY_6_LEN = 6U, /**< Key's lenth is 6 */ + KEY_8_LEN = 8U, /**< Key's lenth is 8 */ } crypt_key_len_t; /** * @brief CRYPT iv length */ typedef enum { - IV_2_LEN = 2, /**< iv's lenth is 2 */ - IV_4_LEN = 4, /**< iv's lenth is 4 */ + IV_2_LEN = 2U, /**< iv's lenth is 2 */ + IV_4_LEN = 4U, /**< iv's lenth is 4 */ } crypt_ivr_len_t; /** * @brief CRYPT data type */ typedef enum { - DATA_32_BIT = 0, /**< 32 bit data,don't swap */ - DATA_16_BIT = 1, /**< 16 bit data,swap */ - DATA_8_BIT = 2, /**< 8 bit data,swap */ - DATA_1_BIT = 3, /**< 1 bit data, swap */ + DATA_32_BIT = 0U, /**< 32 bit data,don't swap */ + DATA_16_BIT = 1U, /**< 16 bit data,swap */ + DATA_8_BIT = 2U, /**< 8 bit data,swap */ + DATA_1_BIT = 3U, /**< 1 bit data, swap */ } crypt_data_t; /** @@ -199,7 +199,7 @@ typedef struct crypt_handle_s { */ #define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK)) #define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) -#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) +#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) #define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) #define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) #define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h index a70273076e55d00b93da4b3dfabaccc165e27bf9..d0869058261e122716ba204d07d58cb04e77db10 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h @@ -36,103 +36,103 @@ * @{ */ /** - * @brief ADC channel + * @brief DAC channel */ typedef enum { - DAC_CHANNEL_0 = 1, /**< ADC channel 0 */ - DAC_CHANNEL_1 = 2, /**< ADC channel 1 */ - DAC_CHANNEL_COMB = 3, /**< ADC channel 0 and 1 */ + DAC_CHANNEL_0 = 1U, /**< DAC channel 0 */ + DAC_CHANNEL_1 = 2U, /**< DAC channel 1 */ + DAC_CHANNEL_COMB = 3U, /**< DAC channel 0 and 1 */ } dac_channel_t; /** - * @brief Dac convert mode + * @brief DAC convert mode */ typedef enum { - DAC_CONV_MODE_CONTINUOUS = 0, /**< ADC set in continuous mode */ - DAC_CONV_MODE_SAMPLEHOLD = 1, /**< ADC set in sample/hold mode */ - DAC_CONV_MODE_SAMPLEOFF = 2, /**< ADC set in sample/shut off mode */ + DAC_CONV_MODE_CONTINUOUS = 0U, /**< DAC set in continuous mode */ + DAC_CONV_MODE_SAMPLEHOLD = 1U, /**< DAC set in sample/hold mode */ + DAC_CONV_MODE_SAMPLEOFF = 2U, /**< DAC set in sample/shut off mode */ } dac_conv_mode_t; /** - * @brief ADC out mode + * @brief DAC out mode */ typedef enum { - DAC_OUTPUT_DISABLE = 0, /**< ADC output disable */ - DAC_OUTPUT_PIN = 1, /**< ADC output to pin enable */ - DAC_OUTPUT_ADC = 2, /**< ADC output to adc and acmp enable */ - DAC_OUTPUT_PIN_ADC = 3, /**< ADC output to pin, adc and acmp enable */ + DAC_OUTPUT_DISABLE = 0U, /**< DAC output disable */ + DAC_OUTPUT_PIN = 1U, /**< DAC output to pin enable */ + DAC_OUTPUT_ADC = 2U, /**< DAC output to adc and acmp enable */ + DAC_OUTPUT_PIN_ADC = 3U, /**< DAC output to pin, adc and acmp enable */ } dac_out_mode_t; /** - * @brief ADC prs input channel + * @brief DAC pis input channel */ typedef enum { - DAC_PIS_CH_0 = 0, /**< PIS channel 0 triggers ADC channel conversion */ - DAC_PIS_CH_1 = 1, /**< PIS channel 1 triggers ADC channel conversion */ - DAC_PIS_CH_2 = 2, /**< PIS channel 2 triggers ADC channel conversion */ - DAC_PIS_CH_3 = 3, /**< PIS channel 3 triggers ADC channel conversion */ - DAC_PIS_CH_4 = 4, /**< PIS channel 4 triggers ADC channel conversion */ - DAC_PIS_CH_5 = 5, /**< PIS channel 5 triggers ADC channel conversion */ - DAC_PIS_CH_6 = 6, /**< PIS channel 6 triggers ADC channel conversion */ - DAC_PIS_CH_7 = 7, /**< PIS channel 7 triggers ADC channel conversion */ - DAC_PIS_CH_8 = 8, /**< PIS channel 8 triggers ADC channel conversion */ - DAC_PIS_CH_9 = 9, /**< PIS channel 9 triggers ADC channel conversion */ - DAC_PIS_CH_10 = 10, /**< PIS channel 10 triggers ADC channel conversion */ - DAC_PIS_CH_11 = 11, /**< PIS channel 11 triggers ADC channel conversion */ + DAC_PIS_CH_0 = 0U, /**< PIS channel 0 triggers DAC channel conversion */ + DAC_PIS_CH_1 = 1U, /**< PIS channel 1 triggers DAC channel conversion */ + DAC_PIS_CH_2 = 2U, /**< PIS channel 2 triggers DAC channel conversion */ + DAC_PIS_CH_3 = 3U, /**< PIS channel 3 triggers DAC channel conversion */ + DAC_PIS_CH_4 = 4U, /**< PIS channel 4 triggers DAC channel conversion */ + DAC_PIS_CH_5 = 5U, /**< PIS channel 5 triggers DAC channel conversion */ + DAC_PIS_CH_6 = 6U, /**< PIS channel 6 triggers DAC channel conversion */ + DAC_PIS_CH_7 = 7U, /**< PIS channel 7 triggers DAC channel conversion */ + DAC_PIS_CH_8 = 8U, /**< PIS channel 8 triggers DAC channel conversion */ + DAC_PIS_CH_9 = 9U, /**< PIS channel 9 triggers DAC channel conversion */ + DAC_PIS_CH_10 = 10U, /**< PIS channel 10 triggers DAC channel conversion */ + DAC_PIS_CH_11 = 11U, /**< PIS channel 11 triggers DAC channel conversion */ } dac_pissel_t; /** - * @brief ADC negative reference voltage definition + * @brief DAC negative reference voltage definition */ typedef enum { - DAC_NEG_REF_VSS = 0x0, /**< DAC negative regerence voltage vss */ - DAC_NEG_REF_VREFN = 0x1, /**< DAC negative regerence voltage vrefn */ + DAC_NEG_REF_VSS = 0x0U, /**< DAC negative regerence voltage vss */ + DAC_NEG_REF_VREFN = 0x1U, /**< DAC negative regerence voltage vrefn */ } dac_neg_ref_t; /** - * @brief ADC positive reference voltage definition + * @brief DAC positive reference voltage definition */ typedef enum { - DAC_POS_REF_VDD = 0x0, /**< DAC posotove reference is VDD */ - DAC_POS_REF_2V = 0x1, /**< DAC posotove reference is internal 2V */ - DAC_POS_REF_VREEFP = 0x2, /**< DAC posotove reference is VREEFP */ - DAC_POS_REF_VREEFP_BUF = 0x3, /**< DAC posotove reference is VREEFP BUFFER */ + DAC_POS_REF_VDD = 0x0U, /**< DAC posotove reference is VDD */ + DAC_POS_REF_2V = 0x1U, /**< DAC posotove reference is internal 2V */ + DAC_POS_REF_VREEFP = 0x2U, /**< DAC posotove reference is VREEFP */ + DAC_POS_REF_VREEFP_BUF = 0x3U, /**< DAC posotove reference is VREEFP BUFFER */ } dac_pos_ref_t; /** * @brief Refresh interval select */ typedef enum { - DAC_REFRESH_8 = 0, /**< Channel refreshed every 8 cycles */ - DAC_REFRESH_16 = 1, /**< Channel refreshed every 16 cycles */ - DAC_REFRESH_32 = 2, /**< Channel refreshed every 32 cycles */ - DAC_REFRESH_64 = 3, /**< Channel refreshed every 64 cycles */ + DAC_REFRESH_8 = 0U, /**< Channel refreshed every 8 cycles */ + DAC_REFRESH_16 = 1U, /**< Channel refreshed every 16 cycles */ + DAC_REFRESH_32 = 2U, /**< Channel refreshed every 32 cycles */ + DAC_REFRESH_64 = 3U, /**< Channel refreshed every 64 cycles */ } dac_refresh_t; /** - * @brief Dac prescale + * @brief DAC prescale */ typedef enum { - DAC_PRES_DIV_1 = 0, /**< No division */ - DAC_PRES_DIV_2 = 1, /**< 2 clock division */ - DAC_PRES_DIV_4 = 2, /**< 4 clock division */ - DAC_PRES_DIV_8 = 3, /**< 8 clock division */ - DAC_PRES_DIV_16 = 4, /**< 16 clock division */ - DAC_PRES_DIV_32 = 5, /**< 32 clock division */ - DAC_PRES_DIV_64 = 6, /**< 64 clock division */ - DAC_PRES_DIV_128 = 7, /**< 128 clock division */ + DAC_PRES_DIV_1 = 0U, /**< No division */ + DAC_PRES_DIV_2 = 1U, /**< 2 clock division */ + DAC_PRES_DIV_4 = 2U, /**< 4 clock division */ + DAC_PRES_DIV_8 = 3U, /**< 8 clock division */ + DAC_PRES_DIV_16 = 4U, /**< 16 clock division */ + DAC_PRES_DIV_32 = 5U, /**< 32 clock division */ + DAC_PRES_DIV_64 = 6U, /**< 64 clock division */ + DAC_PRES_DIV_128 = 7U, /**< 128 clock division */ } dac_prescale_div_t; /** - * @brief Dac output trigger select + * @brief DAC output trigger select */ typedef enum { - DAC_TRIGGER_BY_DATA = 0, /**< Channel is triggered by CHxDATA or COMBDATA write */ - DAC_TRIGGER_BY_PIS = 1, /**< Channel is triggered by PIS input */ + DAC_TRIGGER_BY_DATA = 0U, /**< Channel is triggered by CHxDATA or COMBDATA write */ + DAC_TRIGGER_BY_PIS = 1U, /**< Channel is triggered by PIS input */ } dac_trigger_t; /** - * @brief Dac interrupt type + * @brief DAC interrupt type */ typedef enum { DAC_IT_CH0 = (1U << 0), /**< Channel 0 conversion complete interrupt */ @@ -142,7 +142,7 @@ typedef enum { } dac_it_t; /** - * @brief Dac interrupt flag type + * @brief DAC interrupt flag type */ typedef enum { DAC_FLAG_CH0 = (1U << 0), /**< Channel 0 conversion complete interrupt flag */ @@ -152,7 +152,7 @@ typedef enum { } dac_flag_t; /** - * @brief Dac state flag + * @brief DAC state flag */ typedef enum { DAC_CH0_BSY = (1U << 0), /**< Channel_0 is BUSY */ @@ -160,7 +160,7 @@ typedef enum { } dac_status_t; /** - * @brief Dac init structure definition + * @brief DAC init structure definition */ typedef struct { dac_conv_mode_t conv_mode; /**< Conversion mode */ @@ -176,21 +176,21 @@ typedef struct { } dac_init_t; /** - * @brief Dac channel initialize structure definition + * @brief DAC channel initialize structure definition */ typedef struct { - type_func_t enable; /**< Dac channel output enable/disable */ + type_func_t enable; /**< DAC channel output enable/disable */ dac_trigger_t trigger; /**< Select channel conversion trigger */ type_func_t refresh_en; /**< Set automatic refresh of channel function */ dac_pissel_t pis_ch; /**< Select channel pis input channel */ } dac_channel_config_t; /** - * @brief Dac handle Structure definition + * @brief DAC handle Structure definition */ typedef struct dac_handle_s { DAC_TypeDef *perh; /**< Register base address */ - dac_init_t init; /**< Dac initialize parameters */ + dac_init_t init; /**< DAC initialize parameters */ lock_state_t lock; /**< Locking object */ void (*cbk)(struct dac_handle_s *arg, uint32_t event); /**< DAC event callback */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h index c1230e694ecc5fd6cc507957b0f2c95be8269a91..4d72f6cb2b046c38b6cad4abf9d2d3b3393c9a88 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h @@ -42,31 +42,31 @@ * @brief Debug mode select */ typedef enum { - DEBC_MODE_SLEEP = (1u << 0), /**< Sleep mode */ - DEBC_MODE_STOP1 = (1u << 1), /**< STOP1 mode */ - DEBC_MODE_STOP2 = (1u << 2), /**< STOP2 mode */ - DEBC_MODE_STANDBY = (1u << 3), /**< Standby mode */ + DEBC_MODE_SLEEP = (1U << 0), /**< Sleep mode */ + DEBC_MODE_STOP1 = (1U << 1), /**< STOP1 mode */ + DEBC_MODE_STOP2 = (1U << 2), /**< STOP2 mode */ + DEBC_MODE_STANDBY = (1U << 3), /**< Standby mode */ } dbgc_mode_t; /** * @brief Debug peripheral select */ typedef enum { - DEBC_PERH_TIMER0 = (1u << 0), /**< AD16C4T0 */ - DEBC_PERH_TIMER1 = (1u << 1), /**< BS16T0 */ - DEBC_PERH_TIMER2 = (1u << 2), /**< GP16C2T0 */ - DEBC_PERH_TIMER3 = (1u << 3), /**< GP16C2T1 */ - DEBC_PERH_TIMER4 = (1u << 4), /**< BS16T1 */ - DEBC_PERH_TIMER5 = (1u << 5), /**< BS16T2 */ - DEBC_PERH_TIMER6 = (1u << 6), /**< GP16C4T0 */ - DEBC_PERH_TIMER7 = (1u << 7), /**< BS16T3 */ - DEBC_PERH_I2C0 = (1u << 8), /**< I2C0 SMBUS */ - DEBC_PERH_I2C1 = (1u << 9), /**< I2C1 SMBUS */ - DEBC_PERH_CAN = (1u << 12), /**< CAN */ - DEBC_PERH_LPTIM0 = (1u << 0) | (1u << 16), /**< LPTIM0 */ - DEBC_PERH_IWDT = (1u << 8) | (1u << 16), /**< IWDT */ - DEBC_PERH_WWDT = (1u << 9) | (1u << 16), /**< WWDT */ - DEBC_PERH_RTC = (1u << 10) | (1u << 16), /**< RTC */ + DEBC_PERH_TIMER0 = (1U << 0), /**< AD16C4T0 */ + DEBC_PERH_TIMER1 = (1U << 1), /**< BS16T0 */ + DEBC_PERH_TIMER2 = (1U << 2), /**< GP16C2T0 */ + DEBC_PERH_TIMER3 = (1U << 3), /**< GP16C2T1 */ + DEBC_PERH_TIMER4 = (1U << 4), /**< BS16T1 */ + DEBC_PERH_TIMER5 = (1U << 5), /**< BS16T2 */ + DEBC_PERH_TIMER6 = (1U << 6), /**< GP16C4T0 */ + DEBC_PERH_TIMER7 = (1U << 7), /**< BS16T3 */ + DEBC_PERH_I2C0 = (1U << 8), /**< I2C0 SMBUS */ + DEBC_PERH_I2C1 = (1U << 9), /**< I2C1 SMBUS */ + DEBC_PERH_CAN = (1U << 12), /**< CAN */ + DEBC_PERH_LPTIM0 = (1U << 0) | (1U << 16), /**< LPTIM0 */ + DEBC_PERH_IWDT = (1U << 8) | (1U << 16), /**< IWDT */ + DEBC_PERH_WWDT = (1U << 9) | (1U << 16), /**< WWDT */ + DEBC_PERH_RTC = (1U << 10) | (1U << 16), /**< RTC */ } dbgc_perh_t; /** * @} diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h index 736e5b68be37178fe62beb4376949f9e5c1b1b5f..efd366889c4d33ff5af3b07be35126211e3c2302 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h @@ -36,8 +36,8 @@ * @defgroup DMA_Public_Macros DMA Public Macros * @{ */ -#define DMA_CH_COUNT 12 -#define DMA_ERR 31 +#define DMA_CH_COUNT 12U +#define DMA_ERR 31U /** * @} */ @@ -49,132 +49,136 @@ /** * @brief Input source to DMA channel - * @note - * ES32F36xx - * AD16C4T0 TIMER0 - * AD16C4T1 TIMER1 - * GP32C4T0 TIMER2 - * GP32C4T1 TIMER3 - * BS16T0 TIMER4 - * BS16T1 TIMER5 - * GP16C4T0 TIMER6 - * GP16C4T1 TIMER7 - * - * ES32F393x/ES32F336x/ES32F392x - * GP16C4T0 TIMER0 - * GP16C4T1 TIMER1 - * GP32C4T0 TIMER2 - * GP32C4T1 TIMER3 - * BS16T0 TIMER4 - * BS16T1 TIMER5 - * GP16C4T2 TIMER6 - * GP16C4T3 TIMER7 + * @verbatim + In this module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F36xx series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> AD16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + TIMER4 ----> BS16T0 + TIMER5 ----> BS16T1 + TIMER6 ----> GP16C4T0 + TIMER7 ----> GP16C4T1 + + 2. For ES32F393x/ES32F336x/ES32F392x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> GP16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + TIMER4 ----> BS16T0 + TIMER5 ----> BS16T1 + TIMER6 ----> GP16C4T2 + TIMER7 ----> GP16C4T3 + @endverbatim */ typedef enum { - DMA_MSEL_NONE = 0x0, /**< NONE */ - DMA_MSEL_GPIO = 0x1, /**< GPIO */ - DMA_MSEL_CRYPT = 0x2, /**< CRYPT */ - DMA_MSEL_DAC0 = 0x4, /**< DAC0 */ - DMA_MSEL_ADC0 = 0x6, /**< ADC0 */ - DMA_MSEL_CRC = 0x7, /**< CRC */ - DMA_MSEL_UART0 = 0x8, /**< UART0 */ - DMA_MSEL_UART1 = 0x9, /**< UART1 */ - DMA_MSEL_UART2 = 0xA, /**< UART2 */ - DMA_MSEL_UART3 = 0xB, /**< UART3 */ - DMA_MSEL_UART4 = 0xC, /**< UART4 */ - DMA_MSEL_UART5 = 0xD, /**< UART5 */ - DMA_MSEL_SPI0 = 0xE, /**< SPI0 */ - DMA_MSEL_SPI1 = 0xF, /**< SPI1 */ - DMA_MSEL_I2C0 = 0x10, /**< I2C0 */ - DMA_MSEL_I2C1 = 0x11, /**< I2C1 */ - DMA_MSEL_TIMER0 = 0x12, /**< TIMER0 */ - DMA_MSEL_TIMER1 = 0x13, /**< TIMER1 */ - DMA_MSEL_TIMER2 = 0x14, /**< TIMER2 */ - DMA_MSEL_TIMER3 = 0x15, /**< TIMER3 */ - DMA_MSEL_LPUART0 = 0x18, /**< LPUART0 */ - DMA_MSEL_SPI2 = 0x1A, /**< SPI2 */ - DMA_MSEL_TIMER4 = 0x1B, /**< TIMER4 */ - DMA_MSEL_TIMER5 = 0x1C, /**< TIMER5 */ - DMA_MSEL_TIMER6 = 0x1D, /**< TIMER6 */ - DMA_MSEL_TIMER7 = 0x1E, /**< TIMER7 */ - DMA_MSEL_ADC1 = 0x1F, /**< ADC1 */ - DMA_MSEL_PIS = 0x20, /**< PIS */ - DMA_MSEL_TRNG = 0x21, /**< TRNG */ - DMA_MSEL_QSPI = 0x22, /**< QSPI */ - DMA_MSEL_USB = 0x23, /**< USB */ + DMA_MSEL_NONE = 0x0U, /**< NONE */ + DMA_MSEL_GPIO = 0x1U, /**< GPIO */ + DMA_MSEL_CRYPT = 0x2U, /**< CRYPT */ + DMA_MSEL_DAC0 = 0x4U, /**< DAC0 */ + DMA_MSEL_ADC0 = 0x6U, /**< ADC0 */ + DMA_MSEL_CRC = 0x7U, /**< CRC */ + DMA_MSEL_UART0 = 0x8U, /**< UART0 */ + DMA_MSEL_UART1 = 0x9U, /**< UART1 */ + DMA_MSEL_UART2 = 0xAU, /**< UART2 */ + DMA_MSEL_UART3 = 0xBU, /**< UART3 */ + DMA_MSEL_UART4 = 0xCU, /**< UART4 */ + DMA_MSEL_UART5 = 0xDU, /**< UART5 */ + DMA_MSEL_SPI0 = 0xEU, /**< SPI0 */ + DMA_MSEL_SPI1 = 0xFU, /**< SPI1 */ + DMA_MSEL_I2C0 = 0x10U, /**< I2C0 */ + DMA_MSEL_I2C1 = 0x11U, /**< I2C1 */ + DMA_MSEL_TIMER0 = 0x12U, /**< TIMER0 */ + DMA_MSEL_TIMER1 = 0x13U, /**< TIMER1 */ + DMA_MSEL_TIMER2 = 0x14U, /**< TIMER2 */ + DMA_MSEL_TIMER3 = 0x15U, /**< TIMER3 */ + DMA_MSEL_LPUART0 = 0x18U, /**< LPUART0 */ + DMA_MSEL_SPI2 = 0x1AU, /**< SPI2 */ + DMA_MSEL_TIMER4 = 0x1BU, /**< TIMER4 */ + DMA_MSEL_TIMER5 = 0x1CU, /**< TIMER5 */ + DMA_MSEL_TIMER6 = 0x1DU, /**< TIMER6 */ + DMA_MSEL_TIMER7 = 0x1EU, /**< TIMER7 */ + DMA_MSEL_ADC1 = 0x1FU, /**< ADC1 */ + DMA_MSEL_PIS = 0x20U, /**< PIS */ + DMA_MSEL_TRNG = 0x21U, /**< TRNG */ + DMA_MSEL_QSPI = 0x22U, /**< QSPI */ + DMA_MSEL_USB = 0x23U, /**< USB */ } dma_msel_t; /** * @brief Input signal to DMA channel */ typedef enum { - DMA_MSIGSEL_NONE = 0x0, /**< NONE */ - DMA_MSIGSEL_EXTI_0 = 0x0, /**< External interrupt 0 */ - DMA_MSIGSEL_EXTI_1 = 0x1, /**< External interrupt 1 */ - DMA_MSIGSEL_EXTI_2 = 0x2, /**< External interrupt 2 */ - DMA_MSIGSEL_EXTI_3 = 0x3, /**< External interrupt 3 */ - DMA_MSIGSEL_EXTI_4 = 0x4, /**< External interrupt 4 */ - DMA_MSIGSEL_EXTI_5 = 0x5, /**< External interrupt 5 */ - DMA_MSIGSEL_EXTI_6 = 0x6, /**< External interrupt 6 */ - DMA_MSIGSEL_EXTI_7 = 0x7, /**< External interrupt 7 */ - DMA_MSIGSEL_EXTI_8 = 0x8, /**< External interrupt 8 */ - DMA_MSIGSEL_EXTI_9 = 0x9, /**< External interrupt 9 */ - DMA_MSIGSEL_EXTI_10 = 0xA, /**< External interrupt 10 */ - DMA_MSIGSEL_EXTI_11 = 0xB, /**< External interrupt 11 */ - DMA_MSIGSEL_EXTI_12 = 0xC, /**< External interrupt 12 */ - DMA_MSIGSEL_EXTI_13 = 0xD, /**< External interrupt 13 */ - DMA_MSIGSEL_EXTI_14 = 0xE, /**< External interrupt 14 */ - DMA_MSIGSEL_EXTI_15 = 0xF, /**< External interrupt 15 */ - DMA_MSIGSEL_CRYPT_WRITE = 0x0, /**< CRYPT write mode */ - DMA_MSIGSEL_CRYPT_READ = 0x1, /**< CRYPT read mode */ - DMA_MSIGSEL_DAC0_CH0 = 0x0, /**< DAC0 channel 0 complete */ - DMA_MSIGSEL_DAC0_CH1 = 0x1, /**< DAC0 channel 1 complete */ - DMA_MSIGSEL_ADC = 0x0, /**< ADC mode */ - DMA_MSIGSEL_UART_TXEMPTY = 0x0, /**< UART0/UART1/UART2/UART3 transmit */ - DMA_MSIGSEL_UART_RNR = 0x1, /**< UART0/UART1/UART2/UART3 receive */ - DMA_MSIGSEL_UART45_RNR = 0x0, /**< UART4/UART5 reveive */ - DMA_MSIGSEL_UART45_TXEMPTY = 0x1, /**< UART4/UART5 transmit */ - DMA_MSIGSEL_SPI_RNR = 0x0, /**< SPI receive */ - DMA_MSIGSEL_SPI_TXEMPTY = 0x1, /**< SPI transmit */ - DMA_MSIGSEL_I2C_RNR = 0x0, /**< I2C receive */ - DMA_MSIGSEL_I2C_TXEMPTY = 0x1, /**< I2C transmit */ - DMA_MSIGSEL_TIMER_CH1 = 0x0, /**< TIM channal 1 */ - DMA_MSIGSEL_TIMER_CH2 = 0x1, /**< TIM channal 2 */ - DMA_MSIGSEL_TIMER_CH3 = 0x2, /**< TIM channal 3 */ - DMA_MSIGSEL_TIMER_CH4 = 0x3, /**< TIM channal 4 */ - DMA_MSIGSEL_TIMER_TRI = 0x4, /**< TIM trigger */ - DMA_MSIGSEL_TIMER_COMP = 0x5, /**< TIM compare */ - DMA_MSIGSEL_TIMER_UPDATE = 0x6, /**< TIM update */ - DMA_MSIGSEL_LPUART_RNR = 0x0, /**< LPUART receive */ - DMA_MSIGSEL_LPUART_TXEMPTY = 0x1, /**< LPUART transmit */ - DMA_MSIGSEL_PIS_CH0 = 0x0, /**< PIS channal 0 */ - DMA_MSIGSEL_PIS_CH1 = 0x1, /**< PIS channal 1 */ - DMA_MSIGSEL_PIS_CH2 = 0x2, /**< PIS channal 2 */ - DMA_MSIGSEL_PIS_CH3 = 0x3, /**< PIS channal 3 */ - DMA_MSIGSEL_PIS_CH4 = 0x4, /**< PIS channal 4 */ - DMA_MSIGSEL_PIS_CH5 = 0x5, /**< PIS channal 5 */ - DMA_MSIGSEL_PIS_CH6 = 0x6, /**< PIS channal 6 */ - DMA_MSIGSEL_PIS_CH7 = 0x7, /**< PIS channal 7 */ - DMA_MSIGSEL_PIS_CH8 = 0x8, /**< PIS channal 8 */ - DMA_MSIGSEL_PIS_CH9 = 0x9, /**< PIS channal 9 */ - DMA_MSIGSEL_PIS_CH10 = 0xA, /**< PIS channal 10 */ - DMA_MSIGSEL_PIS_CH11 = 0xB, /**< PIS channal 11 */ - DMA_MSIGSEL_PIS_CH12 = 0xC, /**< PIS channal 12 */ - DMA_MSIGSEL_PIS_CH13 = 0xD, /**< PIS channal 13 */ - DMA_MSIGSEL_PIS_CH14 = 0xE, /**< PIS channal 14 */ - DMA_MSIGSEL_PIS_CH15 = 0xF, /**< PIS channal 15 */ - DMA_MSIGSEL_QSPI_WRITE = 0x0, /**< QSPI Write */ - DMA_MSIGSEL_QSPI_READ = 0x1, /**< QSPI Read */ - DMA_MSIGSEL_EP_TX1 = 0x0, /**< USB TX Endport 0 */ - DMA_MSIGSEL_EP_TX2 = 0x1, /**< USB TX Endport 1 */ - DMA_MSIGSEL_EP_TX3 = 0x2, /**< USB TX Endport 2 */ - DMA_MSIGSEL_EP_TX4 = 0x3, /**< USB TX Endport 3 */ - DMA_MSIGSEL_EP_TX5 = 0x4, /**< USB TX Endport 4 */ - DMA_MSIGSEL_EP_RX1 = 0x8, /**< USB RX Endport 0 */ - DMA_MSIGSEL_EP_RX2 = 0x9, /**< USB RX Endport 1 */ - DMA_MSIGSEL_EP_RX3 = 0xA, /**< USB RX Endport 2 */ - DMA_MSIGSEL_EP_RX4 = 0xB, /**< USB RX Endport 3 */ - DMA_MSIGSEL_EP_RX5 = 0xC, /**< USB RX Endport 4 */ + DMA_MSIGSEL_NONE = 0x0U, /**< NONE */ + DMA_MSIGSEL_EXTI_0 = 0x0U, /**< External interrupt 0 */ + DMA_MSIGSEL_EXTI_1 = 0x1U, /**< External interrupt 1 */ + DMA_MSIGSEL_EXTI_2 = 0x2U, /**< External interrupt 2 */ + DMA_MSIGSEL_EXTI_3 = 0x3U, /**< External interrupt 3 */ + DMA_MSIGSEL_EXTI_4 = 0x4U, /**< External interrupt 4 */ + DMA_MSIGSEL_EXTI_5 = 0x5U, /**< External interrupt 5 */ + DMA_MSIGSEL_EXTI_6 = 0x6U, /**< External interrupt 6 */ + DMA_MSIGSEL_EXTI_7 = 0x7U, /**< External interrupt 7 */ + DMA_MSIGSEL_EXTI_8 = 0x8U, /**< External interrupt 8 */ + DMA_MSIGSEL_EXTI_9 = 0x9U, /**< External interrupt 9 */ + DMA_MSIGSEL_EXTI_10 = 0xAU, /**< External interrupt 10 */ + DMA_MSIGSEL_EXTI_11 = 0xBU, /**< External interrupt 11 */ + DMA_MSIGSEL_EXTI_12 = 0xCU, /**< External interrupt 12 */ + DMA_MSIGSEL_EXTI_13 = 0xDU, /**< External interrupt 13 */ + DMA_MSIGSEL_EXTI_14 = 0xEU, /**< External interrupt 14 */ + DMA_MSIGSEL_EXTI_15 = 0xFU, /**< External interrupt 15 */ + DMA_MSIGSEL_CRYPT_WRITE = 0x0U, /**< CRYPT write mode */ + DMA_MSIGSEL_CRYPT_READ = 0x1U, /**< CRYPT read mode */ + DMA_MSIGSEL_DAC0_CH0 = 0x0U, /**< DAC0 channel 0 complete */ + DMA_MSIGSEL_DAC0_CH1 = 0x1U, /**< DAC0 channel 1 complete */ + DMA_MSIGSEL_ADC = 0x0U, /**< ADC mode */ + DMA_MSIGSEL_UART_TXEMPTY = 0x0U, /**< UART0/UART1/UART2/UART3 transmit */ + DMA_MSIGSEL_UART_RNR = 0x1U, /**< UART0/UART1/UART2/UART3 receive */ + DMA_MSIGSEL_UART45_RNR = 0x0U, /**< UART4/UART5 reveive */ + DMA_MSIGSEL_UART45_TXEMPTY = 0x1U, /**< UART4/UART5 transmit */ + DMA_MSIGSEL_SPI_RNR = 0x0U, /**< SPI receive */ + DMA_MSIGSEL_SPI_TXEMPTY = 0x1U, /**< SPI transmit */ + DMA_MSIGSEL_I2C_RNR = 0x0U, /**< I2C receive */ + DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, /**< I2C transmit */ + DMA_MSIGSEL_TIMER_CH1 = 0x0U, /**< TIM channal 1 */ + DMA_MSIGSEL_TIMER_CH2 = 0x1U, /**< TIM channal 2 */ + DMA_MSIGSEL_TIMER_CH3 = 0x2U, /**< TIM channal 3 */ + DMA_MSIGSEL_TIMER_CH4 = 0x3U, /**< TIM channal 4 */ + DMA_MSIGSEL_TIMER_TRI = 0x4U, /**< TIM trigger */ + DMA_MSIGSEL_TIMER_COMP = 0x5U, /**< TIM compare */ + DMA_MSIGSEL_TIMER_UPDATE = 0x6U, /**< TIM update */ + DMA_MSIGSEL_LPUART_RNR = 0x0U, /**< LPUART receive */ + DMA_MSIGSEL_LPUART_TXEMPTY = 0x1U, /**< LPUART transmit */ + DMA_MSIGSEL_PIS_CH0 = 0x0U, /**< PIS channal 0 */ + DMA_MSIGSEL_PIS_CH1 = 0x1U, /**< PIS channal 1 */ + DMA_MSIGSEL_PIS_CH2 = 0x2U, /**< PIS channal 2 */ + DMA_MSIGSEL_PIS_CH3 = 0x3U, /**< PIS channal 3 */ + DMA_MSIGSEL_PIS_CH4 = 0x4U, /**< PIS channal 4 */ + DMA_MSIGSEL_PIS_CH5 = 0x5U, /**< PIS channal 5 */ + DMA_MSIGSEL_PIS_CH6 = 0x6U, /**< PIS channal 6 */ + DMA_MSIGSEL_PIS_CH7 = 0x7U, /**< PIS channal 7 */ + DMA_MSIGSEL_PIS_CH8 = 0x8U, /**< PIS channal 8 */ + DMA_MSIGSEL_PIS_CH9 = 0x9U, /**< PIS channal 9 */ + DMA_MSIGSEL_PIS_CH10 = 0xAU, /**< PIS channal 10 */ + DMA_MSIGSEL_PIS_CH11 = 0xBU, /**< PIS channal 11 */ + DMA_MSIGSEL_PIS_CH12 = 0xCU, /**< PIS channal 12 */ + DMA_MSIGSEL_PIS_CH13 = 0xDU, /**< PIS channal 13 */ + DMA_MSIGSEL_PIS_CH14 = 0xEU, /**< PIS channal 14 */ + DMA_MSIGSEL_PIS_CH15 = 0xFU, /**< PIS channal 15 */ + DMA_MSIGSEL_QSPI_WRITE = 0x0U, /**< QSPI Write */ + DMA_MSIGSEL_QSPI_READ = 0x1U, /**< QSPI Read */ + DMA_MSIGSEL_EP_TX1 = 0x0U, /**< USB TX Endport 0 */ + DMA_MSIGSEL_EP_TX2 = 0x1U, /**< USB TX Endport 1 */ + DMA_MSIGSEL_EP_TX3 = 0x2U, /**< USB TX Endport 2 */ + DMA_MSIGSEL_EP_TX4 = 0x3U, /**< USB TX Endport 3 */ + DMA_MSIGSEL_EP_TX5 = 0x4U, /**< USB TX Endport 4 */ + DMA_MSIGSEL_EP_RX1 = 0x8U, /**< USB RX Endport 0 */ + DMA_MSIGSEL_EP_RX2 = 0x9U, /**< USB RX Endport 1 */ + DMA_MSIGSEL_EP_RX3 = 0xAU, /**< USB RX Endport 2 */ + DMA_MSIGSEL_EP_RX4 = 0xBU, /**< USB RX Endport 3 */ + DMA_MSIGSEL_EP_RX5 = 0xCU, /**< USB RX Endport 4 */ } dma_msigsel_t; /** @@ -210,31 +214,33 @@ typedef struct { * @brief data increment */ typedef enum { - DMA_DATA_INC_BYTE = 0x0, /**< Address increment by byte */ - DMA_DATA_INC_HALFWORD = 0x1, /**< Address increment by halfword */ - DMA_DATA_INC_WORD = 0x2, /**< Address increment by word */ - DMA_DATA_INC_NONE = 0x3, /**< No increment */ + DMA_DATA_INC_BYTE = 0x0U, /**< Address increment by byte */ + DMA_DATA_INC_HALFWORD = 0x1U, /**< Address increment by halfword */ + DMA_DATA_INC_WORD = 0x2U, /**< Address increment by word */ + DMA_DATA_INC_NONE = 0x3U, /**< No increment */ } dma_data_inc_t; /** * @brief Data size */ typedef enum { - DMA_DATA_SIZE_BYTE = 0x0, /**< Byte */ - DMA_DATA_SIZE_HALFWORD = 0x1, /**< Halfword */ - DMA_DATA_SIZE_WORD = 0x2, /**< Word */ + DMA_DATA_SIZE_BYTE = 0x0U, /**< Byte */ + DMA_DATA_SIZE_HALFWORD = 0x1U, /**< Halfword */ + DMA_DATA_SIZE_WORD = 0x2U, /**< Word */ } dma_data_size_t; /** * @brief The operating mode of the DMA cycle */ typedef enum { - DMA_CYCLE_CTRL_NONE = 0x0, /**< Stop */ - DMA_CYCLE_CTRL_BASIC = 0x1, /**< Basic */ - DMA_CYCLE_CTRL_AUTO = 0x2, /**< Auto-request */ - DMA_CYCLE_CTRL_PINGPONG = 0x3, /**< Ping-pong */ - DMA_CYCLE_CTRL_MEM_SCATTER_GATHER = 0x4, /**< Memory scatter/gather */ - DMA_CYCLE_CTRL_PER_SCATTER_GATHER = 0x6, /**< Peripheral scatter/gather */ + DMA_CYCLE_CTRL_NONE = 0x0U, /**< Stop */ + DMA_CYCLE_CTRL_BASIC = 0x1U, /**< Basic */ + DMA_CYCLE_CTRL_AUTO = 0x2U, /**< Auto-request */ + DMA_CYCLE_CTRL_PINGPONG = 0x3U, /**< Ping-pong */ + DMA_CYCLE_CTRL_MEM_SG_PRIMARY = 0x4U, /**< Memory scatter-gather using the primary structure */ + DMA_CYCLE_CTRL_MEM_SG_ALTERNATE = 0x5U, /**< Memory scatter-gather using the alternate structure */ + DMA_CYCLE_CTRL_PER_SG_PRIMARY = 0x6U, /**< Peripheral scatter-gather using the primary structure */ + DMA_CYCLE_CTRL_PER_SG_ALTERNATE = 0x7U, /**< Peripheral scatter-gather using the alternate structure */ } dma_cycle_ctrl_t; /** @@ -242,17 +248,17 @@ typedef enum { * before the controller re-arbitrates */ typedef enum { - DMA_R_POWER_1 = 0x0, /**< Arbitrates after each DMA transfer */ - DMA_R_POWER_2 = 0x1, /**< Arbitrates after 2 DMA transfer */ - DMA_R_POWER_4 = 0x2, /**< Arbitrates after 4 DMA transfer */ - DMA_R_POWER_8 = 0x3, /**< Arbitrates after 8 DMA transfer */ - DMA_R_POWER_16 = 0x4, /**< Arbitrates after 16 DMA transfer */ - DMA_R_POWER_32 = 0x5, /**< Arbitrates after 32 DMA transfer */ - DMA_R_POWER_64 = 0x6, /**< Arbitrates after 64 DMA transfer */ - DMA_R_POWER_128 = 0x7, /**< Arbitrates after 128 DMA transfer */ - DMA_R_POWER_256 = 0x8, /**< Arbitrates after 256 DMA transfer */ - DMA_R_POWER_512 = 0x9, /**< Arbitrates after 512 DMA transfer */ - DMA_R_POWER_1024 = 0xA, /**< Arbitrates after 1024 DMA transfer */ + DMA_R_POWER_1 = 0x0U, /**< Arbitrates after each DMA transfer */ + DMA_R_POWER_2 = 0x1U, /**< Arbitrates after 2 DMA transfer */ + DMA_R_POWER_4 = 0x2U, /**< Arbitrates after 4 DMA transfer */ + DMA_R_POWER_8 = 0x3U, /**< Arbitrates after 8 DMA transfer */ + DMA_R_POWER_16 = 0x4U, /**< Arbitrates after 16 DMA transfer */ + DMA_R_POWER_32 = 0x5U, /**< Arbitrates after 32 DMA transfer */ + DMA_R_POWER_64 = 0x6U, /**< Arbitrates after 64 DMA transfer */ + DMA_R_POWER_128 = 0x7U, /**< Arbitrates after 128 DMA transfer */ + DMA_R_POWER_256 = 0x8U, /**< Arbitrates after 256 DMA transfer */ + DMA_R_POWER_512 = 0x9U, /**< Arbitrates after 512 DMA transfer */ + DMA_R_POWER_1024 = 0xAU, /**< Arbitrates after 1024 DMA transfer */ } dma_arbiter_config_t; /** @@ -277,9 +283,9 @@ typedef struct { dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */ dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ type_func_t primary; /**< Use primary descriptor or alternate descriptor */ - type_func_t burst; /**< Uses the alternate data structure when complete a DMA cycle */ + type_func_t burst; /**< Enable/Disable the useburst setting for this channel */ type_func_t high_prio; /**< High priority or default priority */ - type_func_t iterrupt; /**< Enable/disable interrupt */ + type_func_t interrupt; /**< Enable/disable interrupt */ dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */ dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */ uint8_t channel; /**< Channel index */ @@ -296,6 +302,15 @@ typedef struct { void *cplt_arg; /**< The parameter of cplt_cbk() */ void *err_arg; /**< The parameter of err_cbk() */ } dma_handle_t; + +/** + * @brief Descriptor complete state + */ +typedef enum { + DMA_DESCP_CPLT_PRI = 0x0U, /**< Primary descriptor has been completed */ + DMA_DESCP_CPLT_ALT = 0x1U, /**< Alternate descriptor has been completed */ + DMA_DESCP_CPLT_ALL = 0x2U, /**< Both primary and alternate descriptors have been completed */ +} dma_descrp_cplt_t; /** * @} */ @@ -313,12 +328,14 @@ typedef struct { #define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \ ((x) == DMA_DATA_SIZE_HALFWORD) || \ ((x) == DMA_DATA_SIZE_WORD)) -#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ - ((x) == DMA_CYCLE_CTRL_BASIC) || \ - ((x) == DMA_CYCLE_CTRL_AUTO) || \ - ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ - ((x) == DMA_CYCLE_CTRL_MEM_SCATTER_GATHER) || \ - ((x) == DMA_CYCLE_CTRL_PER_SCATTER_GATHER)) +#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ + ((x) == DMA_CYCLE_CTRL_BASIC) || \ + ((x) == DMA_CYCLE_CTRL_AUTO) || \ + ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ + ((x) == DMA_CYCLE_CTRL_MEM_SG_PRIMARY) || \ + ((x) == DMA_CYCLE_CTRL_MEM_SG_ALTERNATE) || \ + ((x) == DMA_CYCLE_CTRL_PER_SG_PRIMARY) || \ + ((x) == DMA_CYCLE_CTRL_PER_SG_ALTERNATE)) #define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \ ((x) == DMA_R_POWER_2) || \ ((x) == DMA_R_POWER_4) || \ @@ -350,6 +367,7 @@ typedef struct { extern void ald_dma_reset(DMA_TypeDef *DMAx); extern void ald_dma_init(DMA_TypeDef *DMAx); extern void ald_dma_config_struct(dma_config_t *p); +extern void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory); /** * @} */ @@ -367,6 +385,12 @@ extern void ald_dma_config_basic(dma_handle_t *hperh); extern void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size); extern void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); +extern void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config, + uint8_t first, void (*cbk)(void *arg)); +extern void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, + uint32_t nr, uint8_t channel, void (*cbk)(void *arg)); +extern void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, + dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); /** * @} */ @@ -380,7 +404,8 @@ extern void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_fu extern it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel); extern flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel); extern void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel); -void ald_dma_irq_handler(void); +extern dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel); +extern void ald_dma_irq_handler(void); /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h index 11e8035923f16fe5e31f001c113285a200b8731a..a4c0f372d67c342a72afbddb7c74ec96836e3e1f 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h @@ -97,10 +97,10 @@ * @brief EBI Access Mode */ typedef enum { - EBI_ACCESS_MODE_A = 0x0, /**< EBI access mode A */ - EBI_ACCESS_MODE_B = (0x1U << 28), /**< EBI access mode B */ - EBI_ACCESS_MODE_C = (0x2U << 28), /**< EBI access mode C */ - EBI_ACCESS_MODE_D = (0x3U << 28), /**< EBI access mode D */ + EBI_ACCESS_MODE_A = 0x0U, /**< EBI access mode A */ + EBI_ACCESS_MODE_B = (0x1U << 28), /**< EBI access mode B */ + EBI_ACCESS_MODE_C = (0x2U << 28), /**< EBI access mode C */ + EBI_ACCESS_MODE_D = (0x3U << 28), /**< EBI access mode D */ } ebi_access_mode_t; /** @@ -120,36 +120,36 @@ typedef struct { * @brief EBI_Wait_feature EBI Wait feature */ typedef enum { - EBI_NAND_WAIT_FEATURE_DISABLE = 0x0, /**< NAND wait feature disable */ - EBI_NAND_WAIT_FEATURE_ENABLE = (0x1U << 1), /**< NAND wait feature enable */ + EBI_NAND_WAIT_FEATURE_DISABLE = 0x0U, /**< NAND wait feature disable */ + EBI_NAND_WAIT_FEATURE_ENABLE = (0x1U << 1), /**< NAND wait feature enable */ } ebi_nand_wait_feature_t; /** * @brief EBI NAND Data Width */ typedef enum { - EBI_NAND_MEM_BUS_WIDTH_8 = 0x0, /**< NAND mem bus width 8-bits */ - EBI_NAND_MEM_BUS_WIDTH_16 = (0x3U << 4), /**< NAND mem bus width 16-bits */ + EBI_NAND_MEM_BUS_WIDTH_8 = 0x0U, /**< NAND mem bus width 8-bits */ + EBI_NAND_MEM_BUS_WIDTH_16 = (0x3U << 4), /**< NAND mem bus width 16-bits */ } ebi_nand_mem_bus_width_t; /** * @brief EBI NAND ECC STATE */ typedef enum { - EBI_NAND_ECC_DISABLE = 0, /**< NAND ecc disable */ - EBI_NAND_ECC_ENABLE = (0x1U << 6), /**< NAND ecc enable */ + EBI_NAND_ECC_DISABLE = 0U, /**< NAND ecc disable */ + EBI_NAND_ECC_ENABLE = (0x1U << 6), /**< NAND ecc enable */ } ebi_nand_ecc_t; /** * @brief EBI ECC Page Size */ typedef enum { - EBI_NAND_ECC_PAGE_SIZE_256BYTE = 0, /**< NAND ecc page size 256 bytes */ - EBI_NAND_ECC_PAGE_SIZE_512BYTE = (0x1U << 17), /**< NAND ecc page size 512 bytes */ - EBI_NAND_ECC_PAGE_SIZE_1024BYTE = (0x2U << 17), /**< NAND ecc page size 1024 bytes */ - EBI_NAND_ECC_PAGE_SIZE_2048BYTE = (0x3U << 17), /**< NAND ecc page size 2048 bytes */ - EBI_NAND_ECC_PAGE_SIZE_4096BYTE = (0x4U << 17), /**< NAND ecc page size 4096 bytes */ - EBI_NAND_ECC_PAGE_SIZE_8192BYTE = (0x5U << 17), /**< NAND ecc page size 8192 bytes */ + EBI_NAND_ECC_PAGE_SIZE_256BYTE = 0U, /**< NAND ecc page size 256 bytes */ + EBI_NAND_ECC_PAGE_SIZE_512BYTE = (0x1U << 17), /**< NAND ecc page size 512 bytes */ + EBI_NAND_ECC_PAGE_SIZE_1024BYTE = (0x2U << 17), /**< NAND ecc page size 1024 bytes */ + EBI_NAND_ECC_PAGE_SIZE_2048BYTE = (0x3U << 17), /**< NAND ecc page size 2048 bytes */ + EBI_NAND_ECC_PAGE_SIZE_4096BYTE = (0x4U << 17), /**< NAND ecc page size 4096 bytes */ + EBI_NAND_ECC_PAGE_SIZE_8192BYTE = (0x5U << 17), /**< NAND ecc page size 8192 bytes */ } ebi_md_ecc_page_size_t; /** @@ -179,191 +179,191 @@ typedef struct { * @brief EBI Data Address Bus Multiplexing */ typedef enum { - EBI_DATA_ADDRESS_MUX_DISABLE = 0x0, /**< Data address mux disable */ - EBI_DATA_ADDRESS_MUX_ENABLE = (0x1U << 1), /**< Data address mux enable */ + EBI_DATA_ADDRESS_MUX_DISABLE = 0x0U, /**< Data address mux disable */ + EBI_DATA_ADDRESS_MUX_ENABLE = (0x1U << 1), /**< Data address mux enable */ } ebi_data_address_mux_t; /** * @brief EBI NOR/SRAM Bank */ typedef enum { - EBI_NORSRAM_BANK1 = 0x0, /**< Norsram bank 1 */ - EBI_NORSRAM_BANK2 = 0x2, /**< Norsram bank 2 */ - EBI_NORSRAM_BANK3 = 0x4, /**< Norsram bank 3 */ - EBI_NORSRAM_BANK4 = 0x6, /**< Norsram bank 4 */ + EBI_NORSRAM_BANK1 = 0x0U, /**< Norsram bank 1 */ + EBI_NORSRAM_BANK2 = 0x2U, /**< Norsram bank 2 */ + EBI_NORSRAM_BANK3 = 0x4U, /**< Norsram bank 3 */ + EBI_NORSRAM_BANK4 = 0x6U, /**< Norsram bank 4 */ } ebi_norsram_bank_t; /** * @brief EBI Memory Type */ typedef enum { - EBI_MEMORY_TYPE_SRAM = 0x0, /**< Memory tyepe SRAM */ - EBI_MEMORY_TYPE_PSRAM = (0x1U << 2), /**< Memory tyepe PSRAM */ - EBI_MEMORY_TYPE_NOR = (0x2U << 2), /**< Memory tyepe NOR */ + EBI_MEMORY_TYPE_SRAM = 0x0U, /**< Memory tyepe SRAM */ + EBI_MEMORY_TYPE_PSRAM = (0x1U << 2), /**< Memory tyepe PSRAM */ + EBI_MEMORY_TYPE_NOR = (0x2U << 2), /**< Memory tyepe NOR */ } ebi_memory_type_t; /** * @brief EBI NOR/SRAM Data Width */ typedef enum { - EBI_NORSRAM_MEM_BUS_WIDTH_8 = 0x0, /**< Norsram Memory width 8-bits */ - EBI_NORSRAM_MEM_BUS_WIDTH_16 = (0x1U << 4), /**< Norsram Memory width 16-bits */ - EBI_NORSRAM_MEM_BUS_WIDTH_32 = (0x2U << 4), /**< Norsram Memory width 32-bits */ + EBI_NORSRAM_MEM_BUS_WIDTH_8 = 0x0U, /**< Norsram Memory width 8-bits */ + EBI_NORSRAM_MEM_BUS_WIDTH_16 = (0x1U << 4), /**< Norsram Memory width 16-bits */ + EBI_NORSRAM_MEM_BUS_WIDTH_32 = (0x2U << 4), /**< Norsram Memory width 32-bits */ } ebi_norsram_mem_bus_width_t; /** * @brief EBI NOR/SRAM Flash Access */ typedef enum { - EBI_NORSRAM_FLASH_ACCESS_DISABLE = 0x0, /**< Norsram flash access disable */ - EBI_NORSRAM_FLASH_ACCESS_ENABLE = (0x1U << 6), /**< Norsram flash access enable */ + EBI_NORSRAM_FLASH_ACCESS_DISABLE = 0x0U, /**< Norsram flash access disable */ + EBI_NORSRAM_FLASH_ACCESS_ENABLE = (0x1U << 6), /**< Norsram flash access enable */ } ebi_norsram_flash_access_t; /** * @brief EBI Burst Access Mode */ typedef enum { - EBI_BURST_ACCESS_MODE_DISABLE = 0x0, /**< Burst access disable */ - EBI_BURST_ACCESS_MODE_ENABLE = (0x1U << 8), /**< Burst access enable */ + EBI_BURST_ACCESS_MODE_DISABLE = 0x0U, /**< Burst access disable */ + EBI_BURST_ACCESS_MODE_ENABLE = (0x1U << 8), /**< Burst access enable */ } ebi_burst_access_mode_t; /** * @brief EBI Wait Signal Polarity */ typedef enum { - EBI_WAIT_SIGNAL_POLARITY_LOW = 0x0, /**< Wait signal polarity low */ - EBI_WAIT_SIGNAL_POLARITY_HIGH = (0x1U << 9), /**< Wait signal polarity high */ + EBI_WAIT_SIGNAL_POLARITY_LOW = 0x0U, /**< Wait signal polarity low */ + EBI_WAIT_SIGNAL_POLARITY_HIGH = (0x1U << 9), /**< Wait signal polarity high */ } ebi_wait_signal_polarity_t; /** * @brief EBI Wrap Mode */ typedef enum { - EBI_WRAP_MODE_DISABLE = 0x0, /**< Wrap mode disable */ - EBI_WRAP_MODE_ENABLE = (0x1U << 10), /**< Wrap mode enable */ + EBI_WRAP_MODE_DISABLE = 0x0U, /**< Wrap mode disable */ + EBI_WRAP_MODE_ENABLE = (0x1U << 10), /**< Wrap mode enable */ } ebi_wrap_mode_t; /** * @brief EBI Wait Timing */ typedef enum { - EBI_WAIT_TIMING_BEFORE_WS = 0x0, /**< Wait timing before ws */ - EBI_WAIT_TIMING_DURING_WS = (0x1U << 11), /**< Wait timing during ws */ + EBI_WAIT_TIMING_BEFORE_WS = 0x0U, /**< Wait timing before ws */ + EBI_WAIT_TIMING_DURING_WS = (0x1U << 11), /**< Wait timing during ws */ } ebi_wait_timing_t; /** * @brief EBI Write Operation State */ typedef enum { - EBI_WRITE_OPERATION_DISABLE = 0x0, /**< Write operation disable */ - EBI_WRITE_OPERATION_ENABLE = (0x1U << 12), /**< Write operation enable */ + EBI_WRITE_OPERATION_DISABLE = 0x0U, /**< Write operation disable */ + EBI_WRITE_OPERATION_ENABLE = (0x1U << 12), /**< Write operation enable */ } ebi_write_operation_t; /** * @brief EBI Wait Signal */ typedef enum { - EBI_WAIT_SIGNAL_DISABLE = 0x0, /**< Wait signal disable */ - EBI_WAIT_SIGNAL_ENABLE = (0x1U << 13), /**< Wait signal enable */ + EBI_WAIT_SIGNAL_DISABLE = 0x0U, /**< Wait signal disable */ + EBI_WAIT_SIGNAL_ENABLE = (0x1U << 13), /**< Wait signal enable */ } ebi_wait_signal_t; /** * @brief EBI Extended Mode */ typedef enum { - EBI_EXTENDED_MODE_DISABLE = 0x0, /**< EBI extended mode disable */ - EBI_EXTENDED_MODE_ENABLE = (0x1U << 14), /**< EBI extended mode enable */ + EBI_EXTENDED_MODE_DISABLE = 0x0U, /**< EBI extended mode disable */ + EBI_EXTENDED_MODE_ENABLE = (0x1U << 14), /**< EBI extended mode enable */ } ebi_extended_mode_t; /** * @brief EBI Asynchronous Wait */ typedef enum { - EBI_ASYNCHRONOUS_WAIT_DISABLE = 0x0, /**< Asynchronous wait disable */ - EBI_ASYNCHRONOUS_WAIT_ENABLE = (0x1U << 15), /**< Asynchronous wait enable */ + EBI_ASYNCHRONOUS_WAIT_DISABLE = 0x0U, /**< Asynchronous wait disable */ + EBI_ASYNCHRONOUS_WAIT_ENABLE = (0x1U << 15), /**< Asynchronous wait enable */ } ebi_asynchronous_wait_t; /** * @brief EBI Write Burst */ typedef enum { - EBI_WRITE_BURST_DISABLE = 0x0, /**< Write burst disable */ - EBI_WRITE_BURST_ENABLE = (0x1U << 19), /**< Write burst enable */ + EBI_WRITE_BURST_DISABLE = 0x0U, /**< Write burst disable */ + EBI_WRITE_BURST_ENABLE = (0x1U << 19), /**< Write burst enable */ } ebi_write_burst_t; /** * @brief EBI PCR Memory Type */ typedef enum { - EBI_PCTRLR_MEMORY_TYPE_None = 0x0, /**< PCR memory type none */ - EBI_PCTRLR_MEMORY_TYPE_NAND = (0x1U << 3), /**< PCR memory type nand */ + EBI_PCTRLR_MEMORY_TYPE_None = 0x0U, /**< PCR memory type none */ + EBI_PCTRLR_MEMORY_TYPE_NAND = (0x1U << 3), /**< PCR memory type nand */ } ebi_pctrlr_memory_type_t; /** * @brief EBI Interrupt definition */ typedef enum { - EBI_IT_RISING_EDGE = (1U << 3), /**< Rising edge trigger interrupt */ - EBI_IT_LEVEL = (1U << 4), /**< Level trigger interrupt */ - EBI_IT_FALLING_EDGE = (1U << 5), /**< Falling edge trigger interrupt */ + EBI_IT_RISING_EDGE = (1U << 3), /**< Rising edge trigger interrupt */ + EBI_IT_LEVEL = (1U << 4), /**< Level trigger interrupt */ + EBI_IT_FALLING_EDGE = (1U << 5), /**< Falling edge trigger interrupt */ } ebi_it_t; /** * @brief EBI Flag definition */ typedef enum { - EBI_FLAG_RISING_EDGE = (1U << 0), /**< Rising edge flag */ - EBI_FLAG_LEVEL = (1U << 1), /**< Level flag */ - EBI_FLAG_FALLING_EDGE = (1U << 2), /**< Falling edge flag */ - EBI_FLAG_FEMPT = (1U << 6), /**< Rising edge trigger interrupt */ + EBI_FLAG_RISING_EDGE = (1U << 0), /**< Rising edge flag */ + EBI_FLAG_LEVEL = (1U << 1), /**< Level flag */ + EBI_FLAG_FALLING_EDGE = (1U << 2), /**< Falling edge flag */ + EBI_FLAG_FEMPT = (1U << 6), /**< Rising edge trigger interrupt */ } ebi_flag_t; /** * @brief EBI LCD_Horizontal Synch Polarity definition */ typedef enum { - EBI_LCD_HSYNCPOL_LOW = 0x0, /**< Horizontal synch polarity low */ - EBI_LCD_HSYNCPOL_HIGH = (0x1U << 29), /**< Horizontal synch polarity high */ + EBI_LCD_HSYNCPOL_LOW = 0x0U, /**< Horizontal synch polarity low */ + EBI_LCD_HSYNCPOL_HIGH = (0x1U << 29), /**< Horizontal synch polarity high */ } ebi_lcd_hsyncpol_t; /** * @brief EBI LCD Vertical Synch Polarity definition */ typedef enum { - EBI_LCD_VSYNCPOL_LOW = 0x0, /**< Vertical synch polarity low */ - EBI_LCD_VSYNCPOL_HIGH = (0x1U << 28), /**< Vertical synch polarity high */ + EBI_LCD_VSYNCPOL_LOW = 0x0U, /**< Vertical synch polarity low */ + EBI_LCD_VSYNCPOL_HIGH = (0x1U << 28), /**< Vertical synch polarity high */ } ebi_lcd_vsyncpol_t; /** * @brief EBI LCD Data Enable Polarity definition */ typedef enum { - EBI_LCD_DENPOL_LOW = 0x0, /**< LCD data enable polarity low */ - EBI_LCD_DENPOL_HIGH = (0x1U << 27), /**< LCD data enable polarity high */ + EBI_LCD_DENPOL_LOW = 0x0U, /**< LCD data enable polarity low */ + EBI_LCD_DENPOL_HIGH = (0x1U << 27), /**< LCD data enable polarity high */ } ebi_lcd_denpol_t; /** * @brief EBI LCD Enable definition */ typedef enum { - EBI_LCD_LCDEN_DISABLE = 0x0, /**< LCD disable */ - EBI_LCD_LCDEN_ENABLE = (0x1U << 26), /**< LCD data enable polarity low */ + EBI_LCD_LCDEN_DISABLE = 0x0U, /**< LCD disable */ + EBI_LCD_LCDEN_ENABLE = (0x1U << 26), /**< LCD data enable polarity low */ } ebi_lcd_lcden_t; /** * @brief EBI LCD Init Enable definition */ typedef enum { - EBI_LCD_LCDINT_DISABLE = 0x0, /**< LCD init disable */ - EBI_LCD_LCDINT_ENABLE = (0x1 << 25), /**< LCD init enable */ + EBI_LCD_LCDINT_DISABLE = 0x0U, /**< LCD init disable */ + EBI_LCD_LCDINT_ENABLE = (0x1 << 25), /**< LCD init enable */ } ebi_lcd_lcdint_t; /** * @brief EBI LCD Data Clock definition */ typedef enum { - EBI_LCD_DCLKPOL_FALLING = 0x0, /**< LCD data clock falling edge */ - EBI_LCD_DCLKPOL_RISING = (0x1U << 24), /**< LCD data clock rising edge */ + EBI_LCD_DCLKPOL_FALLING = 0x0U, /**< LCD data clock falling edge */ + EBI_LCD_DCLKPOL_RISING = (0x1U << 24), /**< LCD data clock rising edge */ } ebi_lcd_dclkpol_t; /** diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h index 13c8940a2ef09c7b4e38d09f59b803b3e7881d6e..3a1dfac1133263979c88b4701e62a51f50e5dc1a 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h @@ -79,19 +79,19 @@ do { \ * @{ */ typedef enum { - FLASH_CMD_AE = 0x000051AE, /**< Program area erase all */ - FLASH_CMD_PE = 0x00005EA1, /**< Page erase */ - FLASH_CMD_WP = 0x00005DA2, /**< Word program */ - FLASH_CMD_WP_FAST = 0x00005CA3, /**< Flash quickly program */ - FLASH_CMD_DATAPE = 0x00005BA4, /**< Data flash page page erase */ - FLASH_CMD_DATAWP = 0x00005AA5, /**< Data flash word program */ - FLASH_CMD_DATAWP_FAST = 0x000059A6, /**< Data flash quickly program */ - FLASH_CMD_NP_AE = 0x000050AF, /**< No-private area erase all */ + FLASH_CMD_AE = 0x000051AEU, /**< Program area erase all */ + FLASH_CMD_PE = 0x00005EA1U, /**< Page erase */ + FLASH_CMD_WP = 0x00005DA2U, /**< Word program */ + FLASH_CMD_WP_FAST = 0x00005CA3U, /**< Flash quickly program */ + FLASH_CMD_DATAPE = 0x00005BA4U, /**< Data flash page page erase */ + FLASH_CMD_DATAWP = 0x00005AA5U, /**< Data flash word program */ + FLASH_CMD_DATAWP_FAST = 0x000059A6U, /**< Data flash quickly program */ + FLASH_CMD_NP_AE = 0x000050AFU, /**< No-private area erase all */ } flash_cmd_type; typedef enum { - OP_FLASH = 0, /**< Operate Pragram area */ - OP_INFO = 1, /**< Operate info area */ + OP_FLASH = 0U, /**< Operate Pragram area */ + OP_INFO = 1U, /**< Operate info area */ } op_cmd_type; /** diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h index 8b35b0908e0d571ce7b2b9f37bc90018067d63a5..4731c34a67c3a14cdf1275a0bb6910e15ac9580f 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h @@ -66,68 +66,68 @@ * @brief GPIO mode */ typedef enum { - GPIO_MODE_CLOSE = 0x0, /**< Digital close Analog open */ - GPIO_MODE_INPUT = 0x1, /**< Input */ - GPIO_MODE_OUTPUT = 0x2, /**< Output */ + GPIO_MODE_CLOSE = 0x0U, /**< Digital close Analog open */ + GPIO_MODE_INPUT = 0x1U, /**< Input */ + GPIO_MODE_OUTPUT = 0x2U, /**< Output */ } gpio_mode_t; /** * @brief GPIO open-drain or push-pull */ typedef enum { - GPIO_PUSH_PULL = 0x0, /**< Push-Pull */ - GPIO_OPEN_DRAIN = 0x2, /**< Open-Drain */ - GPIO_OPEN_SOURCE = 0x3, /**< Open-Source */ + GPIO_PUSH_PULL = 0x0U, /**< Push-Pull */ + GPIO_OPEN_DRAIN = 0x2U, /**< Open-Drain. Can't output high level */ + GPIO_OPEN_SOURCE = 0x3U, /**< Open-Source. Can't output low level */ } gpio_odos_t; /** * @brief GPIO push-up or push-down */ typedef enum { - GPIO_FLOATING = 0x0,/**< Floating */ - GPIO_PUSH_UP = 0x1,/**< Push-Up */ - GPIO_PUSH_DOWN = 0x2,/**< Push-Down */ - GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */ + GPIO_FLOATING = 0x0U, /**< Floating */ + GPIO_PUSH_UP = 0x1U, /**< Push-Up */ + GPIO_PUSH_DOWN = 0x2U, /**< Push-Down */ + GPIO_PUSH_UP_DOWN = 0x3U, /**< Push-Up and Push-Down */ } gpio_push_t; /** * @brief GPIO output drive */ typedef enum { - GPIO_OUT_DRIVE_0_1 = 0x0, /**< 0.1mA */ - GPIO_OUT_DRIVE_1 = 0x1, /**< 1mA */ - GPIO_OUT_DRIVE_6 = 0x2, /**< 6mA */ - GPIO_OUT_DRIVE_20 = 0x3, /**< 20mA */ + GPIO_OUT_DRIVE_0_1 = 0x0U, /**< 0.1mA */ + GPIO_OUT_DRIVE_1 = 0x1U, /**< 1mA */ + GPIO_OUT_DRIVE_6 = 0x2U, /**< 6mA */ + GPIO_OUT_DRIVE_20 = 0x3U, /**< 20mA */ } gpio_out_drive_t; /** * @brief GPIO filter */ typedef enum { - GPIO_FILTER_DISABLE = 0x0, /**< Disable filter */ - GPIO_FILTER_ENABLE = 0x1, /**< Enable filter */ + GPIO_FILTER_DISABLE = 0x0U, /**< Disable filter */ + GPIO_FILTER_ENABLE = 0x1U, /**< Enable filter */ } gpio_filter_t; /** * @brief GPIO type */ typedef enum { - GPIO_TYPE_CMOS = 0x0, /**< CMOS Type */ - GPIO_TYPE_TTL = 0x1, /**< TTL Type */ + GPIO_TYPE_CMOS = 0x0U, /**< CMOS Type */ + GPIO_TYPE_TTL = 0x1U, /**< TTL Type */ } gpio_type_t; /** * @brief GPIO functions */ typedef enum { - GPIO_FUNC_0 = 0, /**< function #0 */ - GPIO_FUNC_1 = 1, /**< function #1 */ - GPIO_FUNC_2 = 2, /**< function #2 */ - GPIO_FUNC_3 = 3, /**< function #3 */ - GPIO_FUNC_4 = 4, /**< function #4 */ - GPIO_FUNC_5 = 5, /**< function #5 */ - GPIO_FUNC_6 = 6, /**< function #6 */ - GPIO_FUNC_7 = 7, /**< function #7 */ + GPIO_FUNC_0 = 0U, /**< function #0 */ + GPIO_FUNC_1 = 1U, /**< function #1 */ + GPIO_FUNC_2 = 2U, /**< function #2 */ + GPIO_FUNC_3 = 3U, /**< function #3 */ + GPIO_FUNC_4 = 4U, /**< function #4 */ + GPIO_FUNC_5 = 5U, /**< function #5 */ + GPIO_FUNC_6 = 6U, /**< function #6 */ + GPIO_FUNC_7 = 7U, /**< function #7 */ } gpio_func_t; @@ -157,17 +157,17 @@ typedef struct { * @brief EXTI trigger style */ typedef enum { - EXTI_TRIGGER_RISING_EDGE = 0, /**< Rising edge trigger */ - EXTI_TRIGGER_TRAILING_EDGE = 1, /**< Trailing edge trigger */ - EXTI_TRIGGER_BOTH_EDGE = 2, /**< Rising and trailing edge trigger */ + EXTI_TRIGGER_RISING_EDGE = 0U, /**< Rising edge trigger */ + EXTI_TRIGGER_TRAILING_EDGE = 1U, /**< Trailing edge trigger */ + EXTI_TRIGGER_BOTH_EDGE = 2U, /**< Rising and trailing edge trigger */ } exti_trigger_style_t; /** * @brief EXTI filter clock select */ typedef enum { - EXTI_FILTER_CLOCK_10K = 0, /**< cks = 10KHz */ - EXTI_FILTER_CLOCK_32K = 1, /**< cks = 32KHz */ + EXTI_FILTER_CLOCK_10K = 0U, /**< cks = 10KHz */ + EXTI_FILTER_CLOCK_32K = 1U, /**< cks = 32KHz */ } exti_filter_clock_t; /** @@ -186,8 +186,8 @@ typedef struct { * @defgroup GPIO_Private_Macros GPIO Private Macros * @{ */ -#define PIN_MASK 0xFFFF -#define UNLOCK_KEY 0x55AA +#define PIN_MASK 0xFFFFU +#define UNLOCK_KEY 0x55AAU #define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0)) #define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h index 1a3705a37c5dc755e75fb74fd27663abda790370..7219542d60175c059e8e2e937de6781af91df629 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h @@ -41,91 +41,90 @@ extern "C" { * @brief I2C Error Code */ typedef enum { - I2C_ERROR_NONE = 0x0, /**< No error */ - I2C_ERROR_BERR = 0x1, /**< Berr error */ - I2C_ERROR_ARLO = 0x2, /**< Arlo error */ - I2C_ERROR_RUD = 0x4, /**< Rx underflow error */ - I2C_ERROR_AF = 0x8, /**< Af error */ - I2C_ERROR_ROV = 0x10, /**< Rx overflow error */ - I2C_ERROR_RF = 0x20, /**< Rx full error */ - I2C_ERROR_TUD = 0x40, /**< Tx underflow error */ - I2C_ERROR_TOV = 0x80, /**< Tx overflow error */ - I2C_ERROR_TE = 0x100, /**< Tx empty error */ - I2C_ERROR_DMA = 0x200, /**< Dma error */ - I2C_ERROR_TIMEOUT = 0x400 /**< Timeout error */ + I2C_ERROR_NONE = 0x0U, /**< No error */ + I2C_ERROR_BERR = 0x1U, /**< Berr error */ + I2C_ERROR_ARLO = 0x2U, /**< Arlo error */ + I2C_ERROR_RUD = 0x4U, /**< Rx underflow error */ + I2C_ERROR_AF = 0x8U, /**< Af error */ + I2C_ERROR_ROV = 0x10U, /**< Rx overflow error */ + I2C_ERROR_RF = 0x20U, /**< Rx full error */ + I2C_ERROR_TUD = 0x40U, /**< Tx underflow error */ + I2C_ERROR_TOV = 0x80U, /**< Tx overflow error */ + I2C_ERROR_TE = 0x100U, /**< Tx empty error */ + I2C_ERROR_DMA = 0x200U, /**< Dma error */ + I2C_ERROR_TIMEOUT = 0x400U, /**< Timeout error */ } i2c_error_t; /** * @brief I2C state structure definition */ typedef enum { - I2C_STATE_RESET = 0x0, /**< Peripheral is not yet Initialized */ - I2C_STATE_READY = 0x20, /**< Peripheral Initialized and ready for use */ - I2C_STATE_BUSY = 0x24, /**< An internal process is ongoing */ - I2C_STATE_BUSY_TX = 0x21, /**< Data Transmission process is ongoing */ - I2C_STATE_BUSY_RX = 0x22, /**< Data Reception process is ongoing */ - I2C_STATE_TIMEOUT = 0xA0, /**< timeout state */ - I2C_STATE_ERROR = 0xE0 /**< Error */ + I2C_STATE_RESET = 0x0U, /**< Peripheral is not yet Initialized */ + I2C_STATE_READY = 0x20U, /**< Peripheral Initialized and ready for use */ + I2C_STATE_BUSY = 0x24U, /**< An internal process is ongoing */ + I2C_STATE_BUSY_TX = 0x21U, /**< Data Transmission process is ongoing */ + I2C_STATE_BUSY_RX = 0x22U, /**< Data Reception process is ongoing */ + I2C_STATE_TIMEOUT = 0xA0U, /**< timeout state */ + I2C_STATE_ERROR = 0xE0U, /**< Error */ } i2c_state_t; /** * @brief I2C Addressing Mode */ typedef enum { - I2C_ADDR_7BIT = 0x0, /**< 7 bit address */ - I2C_ADDR_10BIT = 0x1, /**< 10 bit address */ + I2C_ADDR_7BIT = 0x0U, /**< 7 bit address */ + I2C_ADDR_10BIT = 0x1U, /**< 10 bit address */ } i2c_addr_t; /** * @brief I2C Dual Addressing Mode */ typedef enum { - I2C_DUALADDR_DISABLE = 0x0, /**< dual address is disable */ - I2C_DUALADDR_ENABLE = 0x1 /**< dual address is enable */ + I2C_DUALADDR_DISABLE = 0x0U, /**< dual address is disable */ + I2C_DUALADDR_ENABLE = 0x1U, /**< dual address is enable */ } i2c_dual_addr_t; /** * @brief I2C General Call Addressing mode */ typedef enum { - I2C_GENERALCALL_DISABLE = 0x0, /**< general call address is disable */ - I2C_GENERALCALL_ENABLE = 0x1 /**< general call address is enable */ + I2C_GENERALCALL_DISABLE = 0x0U, /**< general call address is disable */ + I2C_GENERALCALL_ENABLE = 0x1U, /**< general call address is enable */ } i2c_general_addr_t; /** * @brief I2C Nostretch Mode */ typedef enum { - I2C_NOSTRETCH_DISABLE = 0x0, /**< Nostretch disable */ - I2C_NOSTRETCH_ENABLE = 0x1 /**< Nostretch enable */ + I2C_NOSTRETCH_DISABLE = 0x0U, /**< Nostretch disable */ + I2C_NOSTRETCH_ENABLE = 0x1U, /**< Nostretch enable */ } i2c_nostretch_t; /** * @brief I2C Memory Address Size */ typedef enum { - I2C_MEMADD_SIZE_8BIT = 0x8, /**< 8 bit memory address size */ - I2C_MEMADD_SIZE_16BIT = 0x10 /**< 10 bit memory address size */ + I2C_MEMADD_SIZE_8BIT = 0x8U, /**< 8 bit memory address size */ + I2C_MEMADD_SIZE_16BIT = 0x10U, /**< 10 bit memory address size */ } i2c_addr_size_t; /** * @brief I2C mode structure definition */ -typedef enum -{ - I2C_MODE_NONE = 0x0, /**< No I2C communication on going */ - I2C_MODE_MASTER = 0x10, /**< I2C communication is in Master mode */ - I2C_MODE_SLAVE = 0x20, /**< I2C communication is in Slave mode */ - I2C_MODE_MEM = 0x40 /**< I2C communication is in Memory mode */ +typedef enum { + I2C_MODE_NONE = 0x0U, /**< No I2C communication on going */ + I2C_MODE_MASTER = 0x10U, /**< I2C communication is in Master mode */ + I2C_MODE_SLAVE = 0x20U, /**< I2C communication is in Slave mode */ + I2C_MODE_MEM = 0x40U, /**< I2C communication is in Memory mode */ } i2c_mode_t; /** * @brief I2C Clock */ typedef enum { - I2C_STANDARD_MODE_MAX_CLK = 100000, /**< Standard mode clock */ - I2C_FAST_MODE_MAX_CLK = 400000, /**< Fast mode clock */ - I2C_EXTREME_FAST_MODE_MAX_CLK = 1000000, /**< Extreme mode clock */ + I2C_STANDARD_MODE_MAX_CLK = 100000U, /**< Standard mode clock */ + I2C_FAST_MODE_MAX_CLK = 400000U, /**< Fast mode clock */ + I2C_EXTREME_FAST_MODE_MAX_CLK = 1000000U, /**< Extreme mode clock */ } i2c_clock_t; /** @@ -247,7 +246,7 @@ typedef enum { * @brief I2C TRISE Register */ typedef enum { - I2C_TRISE_TRISE = 0x3F, /**< TRISE BITS */ + I2C_TRISE_TRISE = 0x3FU, /**< TRISE BITS */ } i2c_trise_t; /** @@ -298,7 +297,7 @@ typedef struct i2c_handle_s { /** @defgroup I2C_Public_Macro I2C Public Macros * @{ */ -#define I2C_FLAG_MASK (0xFFFFFFFF) +#define I2C_FLAG_MASK (0xFFFFFFFFU) #define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET) #define I2C_ENABLE_IT(x, y) (SET_BIT((x)->perh->IER, (y))) #define I2C_DISABLE_IT(x, y) (SET_BIT((x)->perh->IDR, (y))) diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h index 94fedffd23c97839afe5ee56a19666a31a7c0396..46d0c36c8e0bb3cb50632f5a7e8192835aabb29f 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h @@ -40,74 +40,64 @@ * @brief Channel length */ typedef enum { - I2S_WIDE_16 = 0, /**< Channel length is 16 */ - I2S_WIDE_32 = 1, /**< Channel length is 32 */ + I2S_WIDE_16 = 0x0U, /**< Channel length is 16 */ + I2S_WIDE_32 = 0x1U, /**< Channel length is 32 */ } i2s_chlen_t; /** * @brief Data length */ typedef enum { - I2S_LEN_16 = 0, /**< Data length is 16 */ - I2S_LEN_24 = 1, /**< Data length is 24 */ - I2S_LEN_32 = 2, /**< Data length is 32 */ + I2S_LEN_16 = 0x0U, /**< Data length is 16 */ + I2S_LEN_24 = 0x1U, /**< Data length is 24 */ + I2S_LEN_32 = 0x2U, /**< Data length is 32 */ } i2s_datalen_t; /** * @brief Inactive state clock polarity */ typedef enum { - I2S_INACTIVE_LOW = 0, /**< Inactive state is low */ - I2S_INACTIVE_HIGH = 1, /**< Inactive state is high */ + I2S_INACTIVE_LOW = 0x0U, /**< Inactive state is low */ + I2S_INACTIVE_HIGH = 0x1U, /**< Inactive state is high */ } i2s_cpol_t; /** * @brief I2s standard */ typedef enum { - I2S_PHILIPS_STANDARD = 0, /**< Philips standard */ - I2S_MSB_JUSTIFIED_STANDARD = 1, /**< MSB standard */ - I2S_LSB_JUSTIFIED_STANDARD = 2, /**< LSB standard */ - I2S_PCM_STANDARD = 3, /**< PCM standard */ + I2S_STD_PHI = 0x0U, /**< Philips standard */ + I2S_STD_MSB = 0x1U, /**< MSB standard */ + I2S_STD_LSB = 0x2U, /**< LSB standard */ + I2S_STD_PCM = 0x3U, /**< PCM standard */ } i2s_standard_t; /** * @brief I2s configuration mode */ typedef enum { - I2S_SLAVE_TRANSMIT = 0, /**< I2S slaver transmit mode */ - I2S_SLAVE_RECEIVE = 1, /**< I2S slaver receive mode */ - I2S_MASTER_TRANSMIT = 2, /**< I2S master transmit mode */ - I2S_MASTER_RECEIVE = 3, /**< I2S master receive mode */ + I2S_MASTER_TRANSMIT = 0x2U, /**< I2S master transmit mode */ + I2S_MASTER_RECEIVE = 0x3U, /**< I2S master receive mode */ } i2s_cfg_t; /** * @brief Pcm frame synchronization */ typedef enum { - I2S_SHORT_FRAME = 0, /**< I2S PCM short frame */ - I2S_LONG_FRAME = 1, /**< I2S PCM long frame */ + I2S_FRAME_SHORT = 0x0U, /**< I2S PCM short frame */ + I2S_FRAME_LONG = 0x1U, /**< I2S PCM long frame */ } i2s_pcms_t; -/** - * @brief Odd factor for prescaler - */ -typedef enum { - I2S_ODD_0 = 0, /**< Odd factor 0 */ - I2S_ODD_1 = 1, /**< Odd factor 1 */ -} i2s_odd_t; - /** * @brief I2S error status */ typedef enum { - I2S_ERROR_NONE = 0, /**< none */ - I2S_ERROR_MODF = 1, /**< mode fault */ - I2S_ERROR_DMA = 2, /**< crc error */ - I2S_ERROR_FRE = 4, /**< frame error */ - I2S_ERROR_RXOV = 8, /**< receive over error */ - I2S_ERROR_TXOV = 0x10, /**< dma error */ - I2S_ERROR_FLAG = 0x20, /**< interrupt flag error */ + I2S_ERROR_NONE = 0x0U, /**< none */ + I2S_ERROR_MODF = 0x1U, /**< mode fault */ + I2S_ERROR_DMA = 0x2U, /**< crc error */ + I2S_ERROR_FRE = 0x4U, /**< frame error */ + I2S_ERROR_RXOV = 0x8U, /**< receive over error */ + I2S_ERROR_TXOV = 0x10U, /**< dma error */ + I2S_ERROR_FLAG = 0x20U, /**< interrupt flag error */ } i2s_error_t; /** @@ -130,36 +120,36 @@ typedef enum { * @brief I2S dma request definition */ typedef enum { - I2S_DMA_REQ_TX = 0, /**< TX dma request */ - I2S_DMA_REQ_RX = 1, /**< RX dma request */ + I2S_DMA_REQ_TX = 0U, /**< TX dma request */ + I2S_DMA_REQ_RX = 1U, /**< RX dma request */ } i2s_dma_req_t; /** * @brief interrupt flag */ typedef enum { - I2S_IF_TXE = (1U << 0), /**< Transmit fifo empty interrupt flag */ - I2S_IF_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt flag */ - I2S_IF_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt flag */ - I2S_IF_RXF = (1U << 9), /**< Receive fifo full interrupt flag */ - I2S_IF_RXOV = (1U << 10), /**< Receive fifo overflow interrupt flag */ - I2S_IF_RXUD = (1U << 11), /**< Receive fifo underflow interrupt flag */ - I2S_IF_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt flag */ - I2S_IF_FRE = (1U << 18), /**< Frame error interrupt flag */ + I2S_IF_TXE = (1U << 0), /**< Transmit fifo empty interrupt flag */ + I2S_IF_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt flag */ + I2S_IF_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt flag */ + I2S_IF_RXF = (1U << 9), /**< Receive fifo full interrupt flag */ + I2S_IF_RXOV = (1U << 10), /**< Receive fifo overflow interrupt flag */ + I2S_IF_RXUD = (1U << 11), /**< Receive fifo underflow interrupt flag */ + I2S_IF_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt flag */ + I2S_IF_FRE = (1U << 18), /**< Frame error interrupt flag */ } i2s_flag_t; /** * @brief I2S state structures definition */ typedef enum { - I2S_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - I2S_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - I2S_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - I2S_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */ - I2S_STATE_BUSY_RX = 0x21, /**< receive is ongoing */ - I2S_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */ - I2S_STATE_TIMEOUT = 0x03, /**< Timeout state */ - I2S_STATE_ERROR = 0x04, /**< Error */ + I2S_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + I2S_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + I2S_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + I2S_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */ + I2S_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */ + I2S_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */ + I2S_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + I2S_STATE_ERROR = 0x04U, /**< Error */ } i2s_state_t; /** @@ -182,20 +172,19 @@ typedef enum { * @brief Channel side */ typedef enum { - I2S_LEFT_SIDE = 0, /**< Sound channel is left */ - I2S_RIGHT_SIDE = 1 /**< Sound channel is right */ + I2S_SIDE_LEFT = 0U, /**< Sound channel is left */ + I2S_SIDE_RIGHT = 1U, /**< Sound channel is right */ } i2s_ch_side_t; /** * @brief I2S TXE/RXNE status definition */ typedef enum { - I2S_SR_TXE = 0, /**< STAT TXE set */ - I2S_SR_RXNE = 1, /**< STAT RXTH set */ - I2S_SR_TXE_RXNE = 2, /**< STAT TXE and RXTH set */ + I2S_SR_TXE = 0U, /**< STAT TXE set */ + I2S_SR_RXNE = 1U, /**< STAT RXTH set */ + I2S_SR_TXE_RXNE = 2U, /**< STAT TXE and RXTH set */ } i2s_sr_status_t; - /** * @brief I2S init structure definition */ @@ -205,10 +194,10 @@ typedef struct { i2s_cpol_t polarity; /**< Inactive clock polarity */ i2s_standard_t standard; /**< Standard choose */ i2s_pcms_t pcm_frame; /**< PCM frame synchronization */ - type_func_t ext_ck; /**< External clock choose */ + type_func_t ext_clk_en; /**< Choose external clock or APB1 clock */ + uint32_t ext_clk; /**< External clock, unit is Hz */ type_func_t mck_en; /**< Main clock output function */ - i2s_odd_t odd; /**< Odd frame choose */ - uint8_t div; /**< Clock divide */ + uint32_t sampling; /**< Sampling rate. eg. 192*1024-192KHz, 96*1024-96KHz */ } i2s_init_t; /** @@ -218,13 +207,14 @@ typedef struct i2s_handle_s { SPI_I2S_TypeDef *perh; /**< I2S registers base address */ i2s_init_t init; /**< I2S communication parameters */ uint16_t *tx_buf; /**< Pointer to I2S Tx transfer buffer */ - uint16_t tx_size; /**< I2S Tx transfer size */ - uint16_t tx_count; /**< I2S Tx transfer counter */ + uint32_t tx_size; /**< I2S Tx transfer size */ + uint32_t tx_count; /**< I2S Tx transfer counter */ uint16_t *rx_buf; /**< Pointer to I2S Rx transfer buffer */ - uint16_t rx_size; /**< I2S Rx Transfer size */ - uint16_t rx_count; /**< I2S Rx Transfer Counter */ + uint32_t rx_size; /**< I2S Rx Transfer size */ + uint32_t rx_count; /**< I2S Rx Transfer Counter */ #ifdef ALD_DMA - dma_handle_t hdma; /**< I2S DMA handle parameters */ + dma_handle_t hdmatx; /**< I2S DMA handle parameters */ + dma_handle_t hdmarx; /**< I2S DMA handle parameters */ #endif lock_state_t lock; /**< Locking object */ i2s_state_t state; /**< I2S communication state */ @@ -262,15 +252,12 @@ typedef struct i2s_handle_s { ((x) == I2S_LEN_32)) #define IS_I2S_CPOL(x) (((x) == I2S_INACTIVE_LOW) || \ ((x) == I2S_INACTIVE_HIGH)) -#define IS_I2S_STANDARD(x) (((x) == I2S_PHILIPS_STANDARD) || \ - ((x) == I2S_MSB_JUSTIFIED_STANDARD) || \ - ((x) == I2S_LSB_JUSTIFIED_STANDARD) || \ - ((x) == I2S_PCM_STANDARD)) -#define IS_I2S_PCMS(x) (((x) == I2S_SHORT_FRAME) || \ - ((x) == I2S_LONG_FRAME)) -#define IS_I2S_ODD(x) (((x) == I2S_ODD_0) || \ - ((x) == I2S_ODD_1)) -#define IS_I2S_DIV(x) ((x) >= 2) +#define IS_I2S_STANDARD(x) (((x) == I2S_STD_PHI) || \ + ((x) == I2S_STD_MSB) || \ + ((x) == I2S_STD_LSB) || \ + ((x) == I2S_STD_PCM)) +#define IS_I2S_PCMS(x) (((x) == I2S_FRAME_SHORT) || \ + ((x) == I2S_FRAME_LONG)) #define IS_I2S_IT(x) (((x) == I2S_IT_TXE) || \ ((x) == I2S_IT_TXOV) || \ ((x) == I2S_IT_TXUD) || \ @@ -332,19 +319,13 @@ void ald_i2s_reset(i2s_handle_t *hperh); /** @addtogroup I2S_Public_Functions_Group2 * @{ */ -ald_status_t ald_i2s_master_send(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_i2s_master_recv(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_i2s_slave_send(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_i2s_slave_recv(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size); -ald_status_t ald_i2s_master_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size); -ald_status_t ald_i2s_slave_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size); -ald_status_t ald_i2s_slave_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size); +ald_status_t ald_i2s_master_send(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2s_master_recv(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size); +ald_status_t ald_i2s_master_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size); #ifdef ALD_DMA -ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_i2s_master_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_i2s_slave_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_i2s_slave_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel); +ald_status_t ald_i2s_master_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch); ald_status_t ald_i2s_dma_pause(i2s_handle_t *hperh); ald_status_t ald_i2s_dma_resume(i2s_handle_t *hperh); ald_status_t ald_i2s_dma_stop(i2s_handle_t *hperh); @@ -359,9 +340,10 @@ ald_status_t ald_i2s_dma_stop(i2s_handle_t *hperh); void ald_i2s_irq_handler(i2s_handle_t *hperh); void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state); void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state); -flag_status_t ald_i2s_get_flag_status(i2s_handle_t *hperh, i2s_flag_t flag); +flag_status_t ald_i2s_get_status(i2s_handle_t *hperh, i2s_status_t status); it_status_t ald_i2s_get_it_status(i2s_handle_t *hperh, i2s_it_t it); -flag_status_t ald_i2s_get_it_flag_status(i2s_handle_t *hperh, i2s_flag_t flag); +flag_status_t ald_i2s_get_flag_status(i2s_handle_t *hperh, i2s_flag_t flag); +flag_status_t ald_i2s_get_mask_flag_status(i2s_handle_t *hperh, i2s_flag_t flag); void ald_i2s_clear_flag_status(i2s_handle_t *hperh, i2s_flag_t flag); /** * @} diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h index 1f15f0851d9bc15fdbe4f78d7887659eb6fb8d86..900cc43086ae4114acb92f0992a7e8cba9d6f551 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h @@ -36,10 +36,14 @@ extern "C" { * @defgroup IAP_Private_Macros IAP Private Macros * @{ */ -#define IAP_WSP_ADDR 0x10000000 -#define IAP_PE_ADDR 0x10000004 -#define IAP_WP_ADDR 0x10000008 -#define IAP_DWP_ADDR 0x1000000c +#define IAP_WSP_ADDR 0x10000000U +#define IAP_PE_ADDR 0x10000004U +#define IAP_WP_ADDR 0x10000008U +#define IAP_DWP_ADDR 0x1000000cU +#define IAP_WordsProgram_DF 0x10000010U +#define IAP_PageErase_DF 0x10000014U +#define IAP_WordProgram_DF 0x10000018U +#define IAP_DWordProgram_DF 0x1000001cU /** * @} */ @@ -62,6 +66,10 @@ uint32_t ald_iap_erase_page(uint32_t addr); uint32_t ald_iap_program_word(uint32_t addr, uint32_t data); uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h); uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); +uint32_t ald_iap_erase_page_df(uint32_t addr); +uint32_t ald_iap_program_word_df(uint32_t addr, uint32_t data); +uint32_t ald_iap_program_dword_df(uint32_t addr, uint32_t data_l, uint32_t data_h); +uint32_t ald_iap_program_words_df(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h index 91dd22f9efce036ece3313f048907f4fefd9094c..bf08b7de802f7ba2a4266f4073e60f3355819d2f 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h @@ -105,18 +105,18 @@ typedef struct #define NAND_WRITE_TIMEOUT 1000U #define CMD_AREA (1U<<16U) /* A16 = CLE high */ #define ADDR_AREA (1U<<17U) /* A17 = ALE high */ -#define NAND_CMD_AREA_A ((uint8_t)0x00) -#define NAND_CMD_AREA_B ((uint8_t)0x01) -#define NAND_CMD_AREA_C ((uint8_t)0x50) -#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) -#define NAND_CMD_WRITE0 ((uint8_t)0x80) -#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) -#define NAND_CMD_ERASE0 ((uint8_t)0x60) -#define NAND_CMD_ERASE1 ((uint8_t)0xD0) -#define NAND_CMD_READID ((uint8_t)0x90) -#define NAND_CMD_STATUS ((uint8_t)0x70) -#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) -#define NAND_CMD_RESET ((uint8_t)0xFF) +#define NAND_CMD_AREA_A ((uint8_t)0x00U) +#define NAND_CMD_AREA_B ((uint8_t)0x01U) +#define NAND_CMD_AREA_C ((uint8_t)0x50U) +#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U) +#define NAND_CMD_WRITE0 ((uint8_t)0x80U) +#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U) +#define NAND_CMD_ERASE0 ((uint8_t)0x60U) +#define NAND_CMD_ERASE1 ((uint8_t)0xD0U) +#define NAND_CMD_READID ((uint8_t)0x90U) +#define NAND_CMD_STATUS ((uint8_t)0x70U) +#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU) +#define NAND_CMD_RESET ((uint8_t)0xFFU) /* NAND memory status */ #define NAND_VALID_ADDRESS 0x00000100U #define NAND_INVALID_ADDRESS 0x00000200U diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h index 425b28042b2f1f673cd89f64c49a4d908a4149f2..83a200b34e8ed0f2c846b3b484044750cb2936e9 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h @@ -37,23 +37,23 @@ */ /* NOR device IDs addresses */ -#define MC_ADDRESS ((uint16_t)0x0000) -#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) -#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) -#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) +#define MC_ADDRESS ((uint16_t)0x0000U) +#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U) +#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU) +#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU) /* NOR CFI IDs addresses */ -#define CFI1_ADDRESS ((uint16_t)0x10) -#define CFI2_ADDRESS ((uint16_t)0x11) -#define CFI3_ADDRESS ((uint16_t)0x12) -#define CFI4_ADDRESS ((uint16_t)0x13) +#define CFI1_ADDRESS ((uint16_t)0x10U) +#define CFI2_ADDRESS ((uint16_t)0x11U) +#define CFI3_ADDRESS ((uint16_t)0x12U) +#define CFI4_ADDRESS ((uint16_t)0x13U) /* NOR operation wait timeout */ -#define NOR_TMEOUT ((uint16_t)0xFFFF) +#define NOR_TMEOUT ((uint16_t)0xFFFFU) /* NOR memory data width */ -#define NOR_MEMORY_8B ((uint8_t)0x0) -#define NOR_MEMORY_16B ((uint8_t)0x1) +#define NOR_MEMORY_8B ((uint8_t)0x0U) +#define NOR_MEMORY_16B ((uint8_t)0x1U) /* NOR memory device read/write start address */ #define NOR_MEMORY_ADRESS1 EBI_BANK1_1 @@ -61,29 +61,29 @@ #define NOR_MEMORY_ADRESS3 EBI_BANK1_3 #define NOR_MEMORY_ADRESS4 EBI_BANK1_4 -#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 -#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 -#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA -#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555 -#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555 -#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA -#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555 - -#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0 -#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA -#define NOR_CMD_DATA_SECOND (uint16_t)0x0055 -#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090 -#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0 -#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080 -#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA -#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055 -#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010 -#define NOR_CMD_DATA_CFI (uint16_t)0x0098 -#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25 -#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29 -#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30 -#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020 -#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040 +#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555U +#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055U +#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AAU +#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555U +#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555U +#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AAU +#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555U + +#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0U +#define NOR_CMD_DATA_FIRST (uint16_t)0x00AAU +#define NOR_CMD_DATA_SECOND (uint16_t)0x0055U +#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090U +#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0U +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080U +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AAU +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055U +#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010U +#define NOR_CMD_DATA_CFI (uint16_t)0x0098U +#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25U +#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29U +#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30U +#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020U +#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040U /** * @} */ @@ -118,10 +118,10 @@ typedef enum { * @brief EBI NOR Status typedef */ typedef enum { - ALD_NOR_STATUS_SUCCESS = 0, /**< NOR status success */ - ALD_NOR_STATUS_ONGOING, /**< NOR status ongoing */ - ALD_NOR_STATUS_ERROR, /**< NOR status error */ - ALD_NOR_STATUS_TIMEOUT, /**< NOR status timeout */ + ALD_NOR_STATUS_SUCCESS = 0U, /**< NOR status success */ + ALD_NOR_STATUS_ONGOING, /**< NOR status ongoing */ + ALD_NOR_STATUS_ERROR, /**< NOR status error */ + ALD_NOR_STATUS_TIMEOUT, /**< NOR status timeout */ } nor_status_t; /** diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h index bc47731ea16dfd6e9acf2fc5c9075b49165e6479..992b3790f0bfcfd394a805bab098678aac0938df 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h @@ -33,374 +33,360 @@ */ /** @defgroup PIS_Public_Types PIS Public Types + * @verbatim + In PIS module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F36xx series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> AD16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + + 2. For ES32F393x/ES32F336x/ES32F392x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> GP16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + @endverbatim * @{ */ /** * @brief Producer entry - * @note - * ES32F36xx - * AD16C4T0 TIMER0 - * AD16C4T1 TIMER1 - * GP32C4T0 TIMER2 - * GP32C4T1 TIMER3 - * BS16T0 TIMER4 - * BS16T1 TIMER5 - * GP16C4T0 TIMER6 - * GP16C4T1 TIMER7 - * - * ES32F393x/ES32F336x/ES32F392x - * GP16C4T0 TIMER0 - * GP16C4T1 TIMER1 - * GP32C4T0 TIMER2 - * GP32C4T1 TIMER3 - * BS16T0 TIMER4 - * BS16T1 TIMER5 - * GP16C4T2 TIMER6 - * GP16C4T3 TIMER7 */ typedef enum { - PIS_NON = 0x0, /**< No async */ - PIS_GPIO_PIN0 = 0x10, /**< Pin0, level,support async */ - PIS_GPIO_PIN1 = 0x11, /**< Pin1, level,support async */ - PIS_GPIO_PIN2 = 0x12, /**< Pin2, level,support async */ - PIS_GPIO_PIN3 = 0x13, /**< Pin3, level,support async */ - PIS_GPIO_PIN4 = 0x14, /**< Pin4, level,support async */ - PIS_GPIO_PIN5 = 0x15, /**< Pin5, level,support async */ - PIS_GPIO_PIN6 = 0x16, /**< Pin6, level,support async */ - PIS_GPIO_PIN7 = 0x17, /**< Pin7, level,support async */ - PIS_GPIO_PIN8 = 0x18, /**< Pin8, level,support async */ - PIS_GPIO_PIN9 = 0x19, /**< Pin9, level,support async */ - PIS_GPIO_PIN10 = 0x1a, /**< Pin10, level,support async */ - PIS_GPIO_PIN11 = 0x1b, /**< Pin11, level,support async */ - PIS_GPIO_PIN12 = 0x1c, /**< Pin12, level,support async */ - PIS_GPIO_PIN13 = 0x1d, /**< Pin13, level,support async */ - PIS_GPIO_PIN14 = 0x1e, /**< Pin14, level,support async */ - PIS_GPIO_PIN15 = 0x1f, /**< Pin15, level,support async */ - PIS_ACMP_OUT0 = 0x30, /**< Acmp0 output, level,support async */ - PIS_ACMP_OUT1 = 0x31, /**< Acmp1 output, level,support async */ - PIS_DAC0_CH0 = 0x40, /**< Dac0 channel 0, pclk2 pulse,support async */ - PIS_DAC0_CH1 = 0x41, /**< Dac0 channel 1, pclk2 pulse,support async */ - PIS_ADC0_INJECT = 0x60, /**< Adc0 inject, pclk2 pulse,support async */ - PIS_ADC0_REGULAT = 0x61, /**< Adc0 regulat, pclk2 pulse,support async */ - PIS_ADC0_RESERVE = 0x62, /**< Adc0 reserve */ - PIS_LVD = 0x70, /**< Lvd, level,support async */ - PIS_UART0_RESERVE0 = 0x80, /**< Uart0 reserve bit 0 */ - PIS_UART0_RESERVE1 = 0x81, /**< Uart0 reserve bit 1*/ - PIS_UART0_IRDAOUT = 0x82, /**< Uart0 irdaout, level,support async */ - PIS_UART0_RTSOUT = 0x83, /**< Uart0 rtsout, level,support async */ - PIS_UART0_TXOUT = 0x84, /**< Uart0 txout, level,support async */ - PIS_UART0_SYN_SEND = 0x85, /**< Uart0 syn send, pulse,support async */ - PIS_UART0_SYN_RECV = 0x86, /**< Uart0 syn recv, pulse,support async */ - PIS_UART1_RESERVE0 = 0x90, /**< Uart1 reserve bit 0 */ - PIS_UART1_RESERVE1 = 0x91, /**< Uart1 reserve bit 1*/ - PIS_UART1_IRDA = 0x92, /**< Uart1 irdaout, level,support async */ - PIS_UART1_RTS = 0x93, /**< Uart1 rtsout, level,support async */ - PIS_UART1_TXOUT = 0x94, /**< Uart1 txout, level,support async */ - PIS_UART1_SYN_SEND = 0x95, /**< Uart1 syn send, pulse,support async */ - PIS_UART1_SYN_RECV = 0x96, /**< Uart1 syn recv, pulse,support async */ - PIS_UART2_RESERVE0 = 0xa0, /**< Uart2 reserve bit 0 */ - PIS_UART2_RESERVE1 = 0xa1, /**< Uart2 reserve bit 1*/ - PIS_UART2_IRDA = 0xa2, /**< Uart2 irdaout, level,support async */ - PIS_UART2_RTS = 0xa3, /**< Uart2 rtsout, level,support async */ - PIS_UART2_TXOUT = 0xa4, /**< Uart2 txout, level,support async */ - PIS_UART2_SYN_SEND = 0xa5, /**< Uart2 syn send, pulse,support async */ - PIS_UART2_SYN_RECV = 0xa6, /**< Uart2 syn recv, pulse,support async */ - PIS_UART3_RESERVE0 = 0xb1, /**< Uart3 reserve bit 0 */ - PIS_UART3_RESERVE1 = 0xb2, /**< Uart3 reserve bit 1*/ - PIS_UART3_IRDA = 0xb3, /**< Uart3 irdaout, level,support async */ - PIS_UART3_RTS = 0xb4, /**< Uart3 rtsout, level,support async */ - PIS_UART3_TXOUT = 0xb5, /**< Uart3 txout, level,support async */ - PIS_UART3_SYN_SEND = 0xb6, /**< Uart3 syn send, pulse,support async */ - PIS_UART3_SYN_RECV = 0xb7, /**< Uart3 syn recv, pulse,support async */ - PIS_UART4_RECV = 0xc0, /**< uart4 recv, plck1 pulse */ - PIS_UART4_SEND = 0xc1, /**< uart4 send, plck1 pulse */ - PIS_UART4_TXOUT = 0xc2, /**< uart4 txout, plck1 level */ - PIS_UART5_RECV = 0xd0, /**< uart5 recv, plck1 pulse */ - PIS_UART5_SEND = 0xd1, /**< uart5 send, plck1 pulse */ - PIS_UART5_TXOUT = 0xd2, /**< uart5 txout, plck1 level */ - PIS_SPI0_RECV = 0xe0, /**< Spi0 recv, plck1 pulse */ - PIS_SPI0_SEND = 0xe1, /**< Spi0 send, plck1 pulse */ - PIS_SPI0_NE = 0xe2, /**< Spi0 ne, plck1 level */ - PIS_SPI1_RECV = 0xf0, /**< Spi1 recv, plck1 pulse */ - PIS_SPI1_SEND = 0xf1, /**< Spi1 send, plck1 pulse */ - PIS_SPI1_NE = 0xf2, /**< Spi1 ne, plck1 level */ - PIS_I2C0_RECV = 0x100, /**< I2c0 recv, plck1 level */ - PIS_I2C0_SEND = 0x101, /**< I2c0 send, plck1 level */ - PIS_I2C1_RECV = 0x110, /**< I2c1 recv, plck1 level */ - PIS_I2C1_SEND = 0x111, /**< I2c1 send, plck1 level */ - PIS_TIMER0_UPDATA = 0x120, /**< Timer0 updata, plck1 pulse */ - PIS_TIMER0_TRIG = 0x121, /**< Timer0 trig, plck1 pulse */ - PIS_TIMER0_INPUT_1 = 0x122, /**< Timer0 chan1 input catch, plck1 pulse */ - PIS_TIMER0_OUTPUT_1 = 0x123, /**< Timer0 chan1 output compare, plck1 pulse */ - PIS_TIMER0_INPUT_2 = 0x124, /**< Timer0 chan2 input catch, plck1 pulse */ - PIS_TIMER0_OUTPUT_2 = 0x125, /**< Timer0 chan2 output compare, plck1 pulse */ - PIS_TIMER0_INPUT_3 = 0x126, /**< Timer0 chan3 input catch, plck1 pulse */ - PIS_TIMER0_OUTPUT_3 = 0x127, /**< Timer0 chan3 output compare, plck1 pulse */ - PIS_TIMER0_INPUT_4 = 0x128, /**< Timer0 chan4 input catch, plck1 pulse */ - PIS_TIMER0_OUTPUT_4 = 0x129, /**< Timer0 chan4 output compare, plck1 pulse */ - PIS_TIMER1_UPDATA = 0x130, /**< Timer1 updata, plck1 pulse */ - PIS_TIMER1_TRIG = 0x131, /**< Timer1 trig, plck1 pulse */ - PIS_TIMER1_INPUT_1 = 0x132, /**< Timer1 chan1 input catch, plck1 pulse */ - PIS_TIMER1_OUTPUT_1 = 0x133, /**< Timer1 chan1 output compare, plck1 pulse */ - PIS_TIMER1_INPUT_2 = 0x134, /**< Timer1 chan2 input catch, plck1 pulse */ - PIS_TIMER1_OUTPUT_2 = 0x135, /**< Timer1 chan2 output compare, plck1 pulse */ - PIS_TIMER1_INPUT_3 = 0x136, /**< Timer1 chan3 input catch, plck1 pulse */ - PIS_TIMER1_OUTPUT_3 = 0x137, /**< Timer1 chan3 output compare, plck1 pulse */ - PIS_TIMER1_INPUT_4 = 0x138, /**< Timer1 chan4 input catch, plck1 pulse */ - PIS_TIMER1_OUTPUT_4 = 0x139, /**< Timer1 chan4 output compare, plck1 pulse */ - PIS_TIMER2_UPDATA = 0x140, /**< Timer2 updata, plck1 pulse */ - PIS_TIMER2_TRIG = 0x141, /**< Timer2 trig, plck1 pulse */ - PIS_TIMER2_INPUT_1 = 0x142, /**< Timer2 chan1 input catch, plck1 pulse */ - PIS_TIMER2_OUTPUT_1 = 0x143, /**< Timer2 chan1 output compare, plck1 pulse */ - PIS_TIMER2_INPUT_2 = 0x144, /**< Timer2 chan2 input catch, plck1 pulse */ - PIS_TIMER2_OUTPUT_2 = 0x145, /**< Timer2 chan2 output compare, plck1 pulse */ - PIS_TIMER2_INPUT_3 = 0x146, /**< Timer2 chan3 input catch, plck1 pulse */ - PIS_TIMER2_OUTPUT_3 = 0x147, /**< Timer2 chan3 output compare, plck1 pulse */ - PIS_TIMER2_INPUT_4 = 0x148, /**< Timer2 chan4 input catch, plck1 pulse */ - PIS_TIMER2_OUTPUT_4 = 0x149, /**< Timer2 chan4 output compare, plck1 pulse */ - PIS_TIMER3_UPDATA = 0x150, /**< Timer3 updata, plck1 pulse */ - PIS_TIMER3_TRIG = 0x151, /**< Timer3 trig, plck1 pulse */ - PIS_TIMER3_INPUT_1 = 0x152, /**< Timer3 chan1 input catch, plck1 pulse */ - PIS_TIMER3_OUTPUT_1 = 0x153, /**< Timer3 chan1 output compare, plck1 pulse */ - PIS_TIMER3_INPUT_2 = 0x154, /**< Timer3 chan2 input catch, plck1 pulse */ - PIS_TIMER3_OUTPUT_2 = 0x155, /**< Timer3 chan2 output compare, plck1 pulse */ - PIS_TIMER3_INPUT_3 = 0x156, /**< Timer3 chan3 input catch, plck1 pulse */ - PIS_TIMER3_OUTPUT_3 = 0x157, /**< Timer3 chan3 output compare, plck1 pulse */ - PIS_TIMER3_INPUT_4 = 0x158, /**< Timer3 chan4 input catch, plck1 pulse */ - PIS_TIMER3_OUTPUT_4 = 0x159, /**< Timer3 chan4 output compare, plck1 pulse */ - PIS_RTC_CLOCK = 0x160, /**< Rtc clock, pulse,support async */ - PIS_RTC_ALARM = 0x161, /**< Rtc alarm, pulse,support async */ - PIS_LPTIMER0_SYN_UPDATA = 0x170, /**< Lptimer0 syn updata, pulse,support async */ - PIS_LPTIMER0_ASY_UPDATA = 0x171, /**< Lptimer0 asy updata, pulse,support async */ - PIS_LPUART0_ASY_RECV = 0x180, /**< Lpuart0 asy recv, pulse,support async */ - PIS_LPUART0_ASY_SEND = 0x181, /**< Lpuart0 asy send, pulse,support async */ - PIS_LPUART0_SYN_RECV = 0x182, /**< Lpuart0 syn recv, pulse,support async */ - PIS_LPUART0_SYN_SEND = 0x183, /**< Lpuart0 syn recv, pulse,support async */ - PIS_DMA = 0x190, /**< Dma, pulse,support async */ - PIS_ADC1_INJECT = 0x1a0, /**< Adc1 inject, pclk2 pulse,support async */ - PIS_ADC1_REGULAT = 0x1a1, /**< Adc1 regulat, pclk2 pulse,support async */ - PIS_ADC1_RESERVE = 0x1a2, /**< Adc1 reserve */ + PIS_NON = 0x0U, /**< No async */ + PIS_GPIO_PIN0 = 0x10U, /**< Pin0, level,support async */ + PIS_GPIO_PIN1 = 0x11U, /**< Pin1, level,support async */ + PIS_GPIO_PIN2 = 0x12U, /**< Pin2, level,support async */ + PIS_GPIO_PIN3 = 0x13U, /**< Pin3, level,support async */ + PIS_GPIO_PIN4 = 0x14U, /**< Pin4, level,support async */ + PIS_GPIO_PIN5 = 0x15U, /**< Pin5, level,support async */ + PIS_GPIO_PIN6 = 0x16U, /**< Pin6, level,support async */ + PIS_GPIO_PIN7 = 0x17U, /**< Pin7, level,support async */ + PIS_GPIO_PIN8 = 0x18U, /**< Pin8, level,support async */ + PIS_GPIO_PIN9 = 0x19U, /**< Pin9, level,support async */ + PIS_GPIO_PIN10 = 0x1aU, /**< Pin10, level,support async */ + PIS_GPIO_PIN11 = 0x1bU, /**< Pin11, level,support async */ + PIS_GPIO_PIN12 = 0x1cU, /**< Pin12, level,support async */ + PIS_GPIO_PIN13 = 0x1dU, /**< Pin13, level,support async */ + PIS_GPIO_PIN14 = 0x1eU, /**< Pin14, level,support async */ + PIS_GPIO_PIN15 = 0x1fU, /**< Pin15, level,support async */ + PIS_ACMP_OUT0 = 0x30U, /**< Acmp0 output, level,support async */ + PIS_ACMP_OUT1 = 0x31U, /**< Acmp1 output, level,support async */ + PIS_DAC0_CH0 = 0x40U, /**< Dac0 channel 0, pclk2 pulse,support async */ + PIS_DAC0_CH1 = 0x41U, /**< Dac0 channel 1, pclk2 pulse,support async */ + PIS_ADC0_INSERT = 0x60U, /**< Adc0 insert, pclk2 pulse,support async */ + PIS_ADC0_NORMAL = 0x61U, /**< Adc0 normal, pclk2 pulse,support async */ + PIS_ADC0_RESERVE = 0x62U, /**< Adc0 reserve */ + PIS_LVD = 0x70U, /**< Lvd, level,support async */ + PIS_UART0_RESERVE0 = 0x80U, /**< Uart0 reserve bit 0 */ + PIS_UART0_RESERVE1 = 0x81U, /**< Uart0 reserve bit 1*/ + PIS_UART0_IRDAOUT = 0x82U, /**< Uart0 irdaout, level,support async */ + PIS_UART0_RTSOUT = 0x83U, /**< Uart0 rtsout, level,support async */ + PIS_UART0_TXOUT = 0x84U, /**< Uart0 txout, level,support async */ + PIS_UART0_SYN_SEND = 0x85U, /**< Uart0 syn send, pulse,support async */ + PIS_UART0_SYN_RECV = 0x86U, /**< Uart0 syn recv, pulse,support async */ + PIS_UART1_RESERVE0 = 0x90U, /**< Uart1 reserve bit 0 */ + PIS_UART1_RESERVE1 = 0x91U, /**< Uart1 reserve bit 1*/ + PIS_UART1_IRDA = 0x92U, /**< Uart1 irdaout, level,support async */ + PIS_UART1_RTS = 0x93U, /**< Uart1 rtsout, level,support async */ + PIS_UART1_TXOUT = 0x94U, /**< Uart1 txout, level,support async */ + PIS_UART1_SYN_SEND = 0x95U, /**< Uart1 syn send, pulse,support async */ + PIS_UART1_SYN_RECV = 0x96U, /**< Uart1 syn recv, pulse,support async */ + PIS_UART2_RESERVE0 = 0xa0U, /**< Uart2 reserve bit 0 */ + PIS_UART2_RESERVE1 = 0xa1U, /**< Uart2 reserve bit 1*/ + PIS_UART2_IRDA = 0xa2U, /**< Uart2 irdaout, level,support async */ + PIS_UART2_RTS = 0xa3U, /**< Uart2 rtsout, level,support async */ + PIS_UART2_TXOUT = 0xa4U, /**< Uart2 txout, level,support async */ + PIS_UART2_SYN_SEND = 0xa5U, /**< Uart2 syn send, pulse,support async */ + PIS_UART2_SYN_RECV = 0xa6U, /**< Uart2 syn recv, pulse,support async */ + PIS_UART3_RESERVE0 = 0xb1U, /**< Uart3 reserve bit 0 */ + PIS_UART3_RESERVE1 = 0xb2U, /**< Uart3 reserve bit 1*/ + PIS_UART3_IRDA = 0xb3U, /**< Uart3 irdaout, level,support async */ + PIS_UART3_RTS = 0xb4U, /**< Uart3 rtsout, level,support async */ + PIS_UART3_TXOUT = 0xb5U, /**< Uart3 txout, level,support async */ + PIS_UART3_SYN_SEND = 0xb6U, /**< Uart3 syn send, pulse,support async */ + PIS_UART3_SYN_RECV = 0xb7U, /**< Uart3 syn recv, pulse,support async */ + PIS_UART4_RECV = 0xc0U, /**< uart4 recv, plck1 pulse */ + PIS_UART4_SEND = 0xc1U, /**< uart4 send, plck1 pulse */ + PIS_UART4_TXOUT = 0xc2U, /**< uart4 txout, plck1 level */ + PIS_UART5_RECV = 0xd0U, /**< uart5 recv, plck1 pulse */ + PIS_UART5_SEND = 0xd1U, /**< uart5 send, plck1 pulse */ + PIS_UART5_TXOUT = 0xd2U, /**< uart5 txout, plck1 level */ + PIS_SPI0_RECV = 0xe0U, /**< Spi0 recv, plck1 pulse */ + PIS_SPI0_SEND = 0xe1U, /**< Spi0 send, plck1 pulse */ + PIS_SPI0_NE = 0xe2U, /**< Spi0 ne, plck1 level */ + PIS_SPI1_RECV = 0xf0U, /**< Spi1 recv, plck1 pulse */ + PIS_SPI1_SEND = 0xf1U, /**< Spi1 send, plck1 pulse */ + PIS_SPI1_NE = 0xf2U, /**< Spi1 ne, plck1 level */ + PIS_I2C0_RECV = 0x100U, /**< I2c0 recv, plck1 level */ + PIS_I2C0_SEND = 0x101U, /**< I2c0 send, plck1 level */ + PIS_I2C1_RECV = 0x110U, /**< I2c1 recv, plck1 level */ + PIS_I2C1_SEND = 0x111U, /**< I2c1 send, plck1 level */ + PIS_TIMER0_UPDATA = 0x120U, /**< Timer0 updata, plck1 pulse */ + PIS_TIMER0_TRIG = 0x121U, /**< Timer0 trig, plck1 pulse */ + PIS_TIMER0_INPUT_1 = 0x122U, /**< Timer0 chan1 input catch, plck1 pulse */ + PIS_TIMER0_OUTPUT_1 = 0x123U, /**< Timer0 chan1 output compare, plck1 pulse */ + PIS_TIMER0_INPUT_2 = 0x124U, /**< Timer0 chan2 input catch, plck1 pulse */ + PIS_TIMER0_OUTPUT_2 = 0x125U, /**< Timer0 chan2 output compare, plck1 pulse */ + PIS_TIMER0_INPUT_3 = 0x126U, /**< Timer0 chan3 input catch, plck1 pulse */ + PIS_TIMER0_OUTPUT_3 = 0x127U, /**< Timer0 chan3 output compare, plck1 pulse */ + PIS_TIMER0_INPUT_4 = 0x128U, /**< Timer0 chan4 input catch, plck1 pulse */ + PIS_TIMER0_OUTPUT_4 = 0x129U, /**< Timer0 chan4 output compare, plck1 pulse */ + PIS_TIMER1_UPDATA = 0x130U, /**< Timer1 updata, plck1 pulse */ + PIS_TIMER1_TRIG = 0x131U, /**< Timer1 trig, plck1 pulse */ + PIS_TIMER1_INPUT_1 = 0x132U, /**< Timer1 chan1 input catch, plck1 pulse */ + PIS_TIMER1_OUTPUT_1 = 0x133U, /**< Timer1 chan1 output compare, plck1 pulse */ + PIS_TIMER1_INPUT_2 = 0x134U, /**< Timer1 chan2 input catch, plck1 pulse */ + PIS_TIMER1_OUTPUT_2 = 0x135U, /**< Timer1 chan2 output compare, plck1 pulse */ + PIS_TIMER1_INPUT_3 = 0x136U, /**< Timer1 chan3 input catch, plck1 pulse */ + PIS_TIMER1_OUTPUT_3 = 0x137U, /**< Timer1 chan3 output compare, plck1 pulse */ + PIS_TIMER1_INPUT_4 = 0x138U, /**< Timer1 chan4 input catch, plck1 pulse */ + PIS_TIMER1_OUTPUT_4 = 0x139U, /**< Timer1 chan4 output compare, plck1 pulse */ + PIS_TIMER2_UPDATA = 0x140U, /**< Timer2 updata, plck1 pulse */ + PIS_TIMER2_TRIG = 0x141U, /**< Timer2 trig, plck1 pulse */ + PIS_TIMER2_INPUT_1 = 0x142U, /**< Timer2 chan1 input catch, plck1 pulse */ + PIS_TIMER2_OUTPUT_1 = 0x143U, /**< Timer2 chan1 output compare, plck1 pulse */ + PIS_TIMER2_INPUT_2 = 0x144U, /**< Timer2 chan2 input catch, plck1 pulse */ + PIS_TIMER2_OUTPUT_2 = 0x145U, /**< Timer2 chan2 output compare, plck1 pulse */ + PIS_TIMER2_INPUT_3 = 0x146U, /**< Timer2 chan3 input catch, plck1 pulse */ + PIS_TIMER2_OUTPUT_3 = 0x147U, /**< Timer2 chan3 output compare, plck1 pulse */ + PIS_TIMER2_INPUT_4 = 0x148U, /**< Timer2 chan4 input catch, plck1 pulse */ + PIS_TIMER2_OUTPUT_4 = 0x149U, /**< Timer2 chan4 output compare, plck1 pulse */ + PIS_TIMER3_UPDATA = 0x150U, /**< Timer3 updata, plck1 pulse */ + PIS_TIMER3_TRIG = 0x151U, /**< Timer3 trig, plck1 pulse */ + PIS_TIMER3_INPUT_1 = 0x152U, /**< Timer3 chan1 input catch, plck1 pulse */ + PIS_TIMER3_OUTPUT_1 = 0x153U, /**< Timer3 chan1 output compare, plck1 pulse */ + PIS_TIMER3_INPUT_2 = 0x154U, /**< Timer3 chan2 input catch, plck1 pulse */ + PIS_TIMER3_OUTPUT_2 = 0x155U, /**< Timer3 chan2 output compare, plck1 pulse */ + PIS_TIMER3_INPUT_3 = 0x156U, /**< Timer3 chan3 input catch, plck1 pulse */ + PIS_TIMER3_OUTPUT_3 = 0x157U, /**< Timer3 chan3 output compare, plck1 pulse */ + PIS_TIMER3_INPUT_4 = 0x158U, /**< Timer3 chan4 input catch, plck1 pulse */ + PIS_TIMER3_OUTPUT_4 = 0x159U, /**< Timer3 chan4 output compare, plck1 pulse */ + PIS_RTC_CLOCK = 0x160U, /**< Rtc clock, pulse,support async */ + PIS_RTC_ALARM = 0x161U, /**< Rtc alarm, pulse,support async */ + PIS_LPTIMER0_SYN_UPDATA = 0x170U, /**< Lptimer0 syn updata, pulse,support async */ + PIS_LPTIMER0_ASY_UPDATA = 0x171U, /**< Lptimer0 asy updata, pulse,support async */ + PIS_LPUART0_ASY_RECV = 0x180U, /**< Lpuart0 asy recv, pulse,support async */ + PIS_LPUART0_ASY_SEND = 0x181U, /**< Lpuart0 asy send, pulse,support async */ + PIS_LPUART0_SYN_RECV = 0x182U, /**< Lpuart0 syn recv, pulse,support async */ + PIS_LPUART0_SYN_SEND = 0x183U, /**< Lpuart0 syn recv, pulse,support async */ + PIS_DMA = 0x190U, /**< Dma, pulse,support async */ + PIS_ADC1_INSERT = 0x1a0U, /**< Adc1 insert, pclk2 pulse,support async */ + PIS_ADC1_NORMAL = 0x1a1U, /**< Adc1 normal, pclk2 pulse,support async */ + PIS_ADC1_RESERVE = 0x1a2U, /**< Adc1 reserve */ } pis_src_t; /** * @brief Consumer entry */ typedef enum { - PIS_CH12_TIMER0_ITR0 = 0x003C, /** Tim0 internal input chan0 */ - PIS_CH13_TIMER0_ITR1 = 0x003D, /** Tim0 internal input chan1 */ - PIS_CH14_TIMER0_ITR2 = 0x003E, /** Tim0 internal input chan2 */ - PIS_CH15_TIMER0_ITR3 = 0x003F, /** Tim0 internal input chan3 */ - PIS_CH12_TIMER1_ITR0 = 0x003C, /** Tim1 internal input chan0 */ - PIS_CH13_TIMER1_ITR1 = 0x003D, /** Tim1 internal input chan1 */ - PIS_CH14_TIMER1_ITR2 = 0x003E, /** Tim1 internal input chan2 */ - PIS_CH15_TIMER1_ITR3 = 0x003F, /** Tim1 internal input chan3 */ - PIS_CH12_TIMER2_ITR0 = 0x003C, /** Tim2 internal input chan0 */ - PIS_CH13_TIMER2_ITR1 = 0x003D, /** Tim2 internal input chan1 */ - PIS_CH14_TIMER2_ITR2 = 0x003E, /** Tim2 internal input chan2 */ - PIS_CH15_TIMER2_ITR3 = 0x003F, /** Tim2 internal input chan3 */ - PIS_CH12_TIMER3_ITR0 = 0x003C, /** Tim3 internal input chan0 */ - PIS_CH13_TIMER3_ITR1 = 0x003D, /** Tim3 internal input chan1 */ - PIS_CH14_TIMER3_ITR2 = 0x003E, /** Tim3 internal input chan2 */ - PIS_CH15_TIMER3_ITR3 = 0x003F, /** Tim3 internal input chan3 */ - PIS_CH6_ADC0_REGULAT = 0x0036, /** ADC0 regulat transform */ - PIS_CH7_ADC0_INJECT = 0x0037, /** ADC0 inject transform */ - PIS_CH0_LPTIM0_EXT0 = 0x0030, /** Lptim0 external trigger 0 */ - PIS_CH1_LPTIM0_EXT1 = 0x0031, /** Lptim0 external trigger 1 */ - PIS_CH2_LPTIM0_EXT2 = 0x0032, /** Lptim0 external trigger 2 */ - PIS_CH3_LPTIM0_EXT3 = 0x0033, /** Lptim0 external trigger 3 */ - PIS_CH4_LPTIM0_EXT4 = 0x0034, /** Lptim0 external trigger 4 */ - PIS_CH5_LPTIM0_EXT5 = 0x0035, /** Lptim0 external trigger 5 */ - PIS_CH6_LPTIM0_EXT6 = 0x0036, /** Lptim0 external trigger 6 */ - PIS_CH7_LPTIM0_EXT7 = 0x0037, /** Lptim0 external trigger 7 */ - PIS_CH7_DMA_REQUEST = 0x0037, /** DMA request 7 */ - PIS_CH15_LPUART0_RXD = 0x081F, /**< Lpuart Rx data */ - PIS_CH14_UART5_RXD = 0x071E, /**< Uart5 Rx data */ - PIS_CH13_UART4_RXD = 0x061D, /**< Uart4 Rx data */ - PIS_CH12_UART3_RXD = 0x031C, /**< Uart3 Rx data */ - PIS_CH11_UART2_RXD = 0x021B, /**< Uart2 Rx data */ - PIS_CH10_UART1_RXD = 0x011A, /**< Uart1 Rx data */ - PIS_CH9_UART0_RXD = 0x0019, /**< Uart0 Rx data */ - PIS_CH8_TIMER3_CH4IN = 0x1B08, /**< Tim3 input chan4 */ - PIS_CH8_TIMER2_CH4IN = 0x1308, /**< Tim2 input chan4 */ - PIS_CH8_SPI1_CLK = 0x0F18, /**< Spi1 clk */ - PIS_CH7_TIMER3_CH3IN = 0x1A07, /**< Tim3 input chan3 */ - PIS_CH7_TIMER2_CH3IN = 0x1207, /**< Tim2 input chan3 */ - PIS_CH7_SPI1_RX = 0x0E17, /**< Spi1 rx */ - PIS_CH6_TIMER3_CH2IN = 0x1906, /**< Tim3 input chan2 */ - PIS_CH6_TIMER2_CH2IN = 0x1106, /**< Tim2 input chan2 */ - PIS_CH6_SPI0_CLK = 0x0D16, /**< SPI0 CLK */ - PIS_CH5_TIMER3_CH1IN = 0x1805, /**< Tim3 input chan1 */ - PIS_CH5_TIMER2_CH1IN = 0x1005, /**< Tim2 input chan1 */ - PIS_CH5_SPI0_RX = 0x0C15, /**< SPI0 RX */ - PIS_CH4_TIMER1_CH4IN = 0x0B04, /**< Tim1 input chan4 */ - PIS_CH4_TIMER0_CH4IN = 0x0304, /**< Tim0 input chan4 */ - PIS_CH3_TIMER1_CH3IN = 0x0A03, /**< Tim1 input chan3 */ - PIS_CH3_TIMER0_CH3IN = 0x0203, /**< Tim0 input chan3 */ - PIS_CH2_TIMER1_CH2IN = 0x0902, /**< Tim1 input chan2 */ - PIS_CH2_TIMER0_CH2IN = 0x0102, /**< Tim0 input chan2 */ - PIS_CH1_TIMER1_CH1IN = 0x0801, /**< Tim1 input chan1 */ - PIS_CH0_TIMER0_CH1IN = 0x0000, /**< Tim0 input chan1 */ - PIS_CH0_TIMER0_BRKIN = 0x0400, /**< Tim0 break in */ - PIS_CH0_TIMER1_BRKIN = 0x0C00, /**< Tim1 break in */ - PIS_TRIG_RESERVE = 0xFFFF, /**< Other Consumer */ + PIS_CH12_TIMER0_ITR0 = 0x003CU, /** Tim0 internal input chan0 */ + PIS_CH13_TIMER0_ITR1 = 0x003DU, /** Tim0 internal input chan1 */ + PIS_CH14_TIMER0_ITR2 = 0x003EU, /** Tim0 internal input chan2 */ + PIS_CH15_TIMER0_ITR3 = 0x003FU, /** Tim0 internal input chan3 */ + PIS_CH12_TIMER1_ITR0 = 0x003CU, /** Tim1 internal input chan0 */ + PIS_CH13_TIMER1_ITR1 = 0x003DU, /** Tim1 internal input chan1 */ + PIS_CH14_TIMER1_ITR2 = 0x003EU, /** Tim1 internal input chan2 */ + PIS_CH15_TIMER1_ITR3 = 0x003FU, /** Tim1 internal input chan3 */ + PIS_CH12_TIMER2_ITR0 = 0x003CU, /** Tim2 internal input chan0 */ + PIS_CH13_TIMER2_ITR1 = 0x003DU, /** Tim2 internal input chan1 */ + PIS_CH14_TIMER2_ITR2 = 0x003EU, /** Tim2 internal input chan2 */ + PIS_CH15_TIMER2_ITR3 = 0x003FU, /** Tim2 internal input chan3 */ + PIS_CH12_TIMER3_ITR0 = 0x003CU, /** Tim3 internal input chan0 */ + PIS_CH13_TIMER3_ITR1 = 0x003DU, /** Tim3 internal input chan1 */ + PIS_CH14_TIMER3_ITR2 = 0x003EU, /** Tim3 internal input chan2 */ + PIS_CH15_TIMER3_ITR3 = 0x003FU, /** Tim3 internal input chan3 */ + PIS_CH6_ADC0_NORMAL = 0x0036U, /** ADC0 normal transform */ + PIS_CH7_ADC0_INSERT = 0x0037U, /** ADC0 insert transform */ + PIS_CH0_ADC1_NORMAL = 0x0030U, /** ADC1 normal transform */ + PIS_CH1_ADC1_INSERT = 0x0031U, /** ADC1 insert transform */ + PIS_CH0_LPTIM0_EXT0 = 0x0030U, /** Lptim0 external trigger 0 */ + PIS_CH1_LPTIM0_EXT1 = 0x0031U, /** Lptim0 external trigger 1 */ + PIS_CH2_LPTIM0_EXT2 = 0x0032U, /** Lptim0 external trigger 2 */ + PIS_CH3_LPTIM0_EXT3 = 0x0033U, /** Lptim0 external trigger 3 */ + PIS_CH4_LPTIM0_EXT4 = 0x0034U, /** Lptim0 external trigger 4 */ + PIS_CH5_LPTIM0_EXT5 = 0x0035U, /** Lptim0 external trigger 5 */ + PIS_CH6_LPTIM0_EXT6 = 0x0036U, /** Lptim0 external trigger 6 */ + PIS_CH7_LPTIM0_EXT7 = 0x0037U, /** Lptim0 external trigger 7 */ + PIS_CH7_DMA_REQUEST = 0x0037U, /** DMA request 7 */ + PIS_CH15_LPUART0_RXD = 0x081FU, /**< Lpuart Rx data */ + PIS_CH14_UART5_RXD = 0x071EU, /**< Uart5 Rx data */ + PIS_CH13_UART4_RXD = 0x061DU, /**< Uart4 Rx data */ + PIS_CH12_UART3_RXD = 0x031CU, /**< Uart3 Rx data */ + PIS_CH11_UART2_RXD = 0x021BU, /**< Uart2 Rx data */ + PIS_CH10_UART1_RXD = 0x011AU, /**< Uart1 Rx data */ + PIS_CH9_UART0_RXD = 0x0019U, /**< Uart0 Rx data */ + PIS_CH8_TIMER3_CH4IN = 0x1B08U, /**< Tim3 input chan4 */ + PIS_CH8_TIMER2_CH4IN = 0x1308U, /**< Tim2 input chan4 */ + PIS_CH8_SPI1_CLK = 0x0F18U, /**< Spi1 clk */ + PIS_CH7_TIMER3_CH3IN = 0x1A07U, /**< Tim3 input chan3 */ + PIS_CH7_TIMER2_CH3IN = 0x1207U, /**< Tim2 input chan3 */ + PIS_CH7_SPI1_RX = 0x0E17U, /**< Spi1 rx */ + PIS_CH6_TIMER3_CH2IN = 0x1906U, /**< Tim3 input chan2 */ + PIS_CH6_TIMER2_CH2IN = 0x1106U, /**< Tim2 input chan2 */ + PIS_CH6_SPI0_CLK = 0x0D16U, /**< SPI0 CLK */ + PIS_CH5_TIMER3_CH1IN = 0x1805U, /**< Tim3 input chan1 */ + PIS_CH5_TIMER2_CH1IN = 0x1005U, /**< Tim2 input chan1 */ + PIS_CH5_SPI0_RX = 0x0C15U, /**< SPI0 RX */ + PIS_CH4_TIMER1_CH4IN = 0x0B04U, /**< Tim1 input chan4 */ + PIS_CH4_TIMER0_CH4IN = 0x0304U, /**< Tim0 input chan4 */ + PIS_CH3_TIMER1_CH3IN = 0x0A03U, /**< Tim1 input chan3 */ + PIS_CH3_TIMER0_CH3IN = 0x0203U, /**< Tim0 input chan3 */ + PIS_CH2_TIMER1_CH2IN = 0x0902U, /**< Tim1 input chan2 */ + PIS_CH2_TIMER0_CH2IN = 0x0102U, /**< Tim0 input chan2 */ + PIS_CH1_TIMER1_CH1IN = 0x0801U, /**< Tim1 input chan1 */ + PIS_CH0_TIMER0_CH1IN = 0x0000U, /**< Tim0 input chan1 */ + PIS_CH0_TIMER0_BRKIN = 0x0400U, /**< Tim0 break in */ + PIS_CH0_TIMER1_BRKIN = 0x0C00U, /**< Tim1 break in */ + PIS_TRIG_RESERVE = 0xFFFFU, /**< Other Consumer */ } pis_trig_t; /** * @brief Clock select */ typedef enum { - PIS_CLK_PCLK1 = 0, /**< APB1 peripherals clock */ - PIS_CLK_PCLK2 = 1, /**< APB2 peripherals clock */ - PIS_CLK_SYS = 2, /**< AHB peripherals clock */ - PIS_CLK_RESERVE = 3, /**< reserve clock */ + PIS_CLK_PCLK1 = 0U, /**< APB1 peripherals clock */ + PIS_CLK_PCLK2 = 1U, /**< APB2 peripherals clock */ + PIS_CLK_SYS = 2U, /**< AHB peripherals clock */ + PIS_CLK_RESERVE = 3U, /**< reserve clock */ } pis_clock_t; /** * @brief Level select */ typedef enum { - PIS_EDGE_NONE = 0, /**< None edge */ - PIS_EDGE_UP = 1, /**< Up edge */ - PIS_EDGE_DOWN = 2, /**< Down edge */ - PIS_EDGE_UP_DOWN = 3, /**< Up and down edge */ + PIS_EDGE_NONE = 0U, /**< None edge */ + PIS_EDGE_UP = 1U, /**< Up edge */ + PIS_EDGE_DOWN = 2U, /**< Down edge */ + PIS_EDGE_UP_DOWN = 3U, /**< Up and down edge */ } pis_edge_t; /** * @brief Output style */ typedef enum { - PIS_OUT_LEVEL = 0, /**< Level */ - PIS_OUT_PULSE = 1, /**< Pulse */ + PIS_OUT_LEVEL = 0U, /**< Level */ + PIS_OUT_PULSE = 1U, /**< Pulse */ } pis_output_t; /** * @brief Sync select */ typedef enum { - PIS_SYN_DIRECT = 0, /**< Direct */ - PIS_SYN_LEVEL_ASY_APB1 = 1, /**< Producer level signal and Consumer in APB1 */ - PIS_SYN_LEVEL_ASY_APB2 = 2, /**< Producer level signal and Consumer in APB2 */ - PIS_SYN_LEVEL_ASY_AHB = 3, /**< Producer level signal and Consumer in AHB */ - PIS_SYN_PULSE_ASY_APB1 = 4, /**< Producer Pulse signal and Consumer in APB1 */ - PIS_SYN_PULSE_ASY_APB2 = 5, /**< Producer Pulse signal and Consumer in APB2 */ - PIS_SYN_PULSE_ASY_AHB = 6, /**< Producer Pulse signal and Consumer in AHB */ + PIS_SYN_DIRECT = 0U, /**< Direct */ + PIS_SYN_LEVEL_ASY_APB1 = 1U, /**< Producer level signal and Consumer in APB1 */ + PIS_SYN_LEVEL_ASY_APB2 = 2U, /**< Producer level signal and Consumer in APB2 */ + PIS_SYN_LEVEL_ASY_AHB = 3U, /**< Producer level signal and Consumer in AHB */ + PIS_SYN_PULSE_ASY_APB1 = 4U, /**< Producer Pulse signal and Consumer in APB1 */ + PIS_SYN_PULSE_ASY_APB2 = 5U, /**< Producer Pulse signal and Consumer in APB2 */ + PIS_SYN_PULSE_ASY_AHB = 6U, /**< Producer Pulse signal and Consumer in AHB */ } pis_syncsel_t; /** * @brief Pis channel */ typedef enum { - PIS_CH_0 = 0, /**< Channel 0 */ - PIS_CH_1 = 1, /**< Channel 1 */ - PIS_CH_2 = 2, /**< Channel 2 */ - PIS_CH_3 = 3, /**< Channel 3 */ - PIS_CH_4 = 4, /**< Channel 4 */ - PIS_CH_5 = 5, /**< Channel 5 */ - PIS_CH_6 = 6, /**< Channel 6 */ - PIS_CH_7 = 7, /**< Channel 7 */ - PIS_CH_8 = 8, /**< Channel 8 */ - PIS_CH_9 = 9, /**< Channel 9 */ - PIS_CH_10 = 10, /**< Channel 10 */ - PIS_CH_11 = 11, /**< Channel 11 */ - PIS_CH_12 = 12, /**< Channel 12 */ - PIS_CH_13 = 13, /**< Channel 13 */ - PIS_CH_14 = 14, /**< Channel 14 */ - PIS_CH_15 = 15, /**< Channel 15 */ + PIS_CH_0 = 0U, /**< Channel 0 */ + PIS_CH_1 = 1U, /**< Channel 1 */ + PIS_CH_2 = 2U, /**< Channel 2 */ + PIS_CH_3 = 3U, /**< Channel 3 */ + PIS_CH_4 = 4U, /**< Channel 4 */ + PIS_CH_5 = 5U, /**< Channel 5 */ + PIS_CH_6 = 6U, /**< Channel 6 */ + PIS_CH_7 = 7U, /**< Channel 7 */ + PIS_CH_8 = 8U, /**< Channel 8 */ + PIS_CH_9 = 9U, /**< Channel 9 */ + PIS_CH_10 = 10U,/**< Channel 10 */ + PIS_CH_11 = 11U,/**< Channel 11 */ + PIS_CH_12 = 12U,/**< Channel 12 */ + PIS_CH_13 = 13U,/**< Channel 13 */ + PIS_CH_14 = 14U,/**< Channel 14 */ + PIS_CH_15 = 15U,/**< Channel 15 */ } pis_ch_t; /** * @brief Pis output channel */ typedef enum { - PIS_OUT_CH_0 = 0, /**< Channel 0 */ - PIS_OUT_CH_1 = 1, /**< Channel 1 */ - PIS_OUT_CH_2 = 2, /**< Channel 2 */ - PIS_OUT_CH_3 = 3, /**< Channel 3 */ + PIS_OUT_CH_0 = 0U, /**< Channel 0 */ + PIS_OUT_CH_1 = 1U, /**< Channel 1 */ + PIS_OUT_CH_2 = 2U, /**< Channel 2 */ + PIS_OUT_CH_3 = 3U, /**< Channel 3 */ } pis_out_ch_t; /** * @brief Indirect value,no care of it. */ typedef enum { - PIS_CON_0 = 0, /**< Con 0 */ - PIS_CON_1 = 1, /**< Con 1 */ - PIS_CON_NONE = 2, /**< None */ + PIS_CON_0 = 0U, /**< Con 0 */ + PIS_CON_1 = 1U, /**< Con 1 */ + PIS_CON_NONE = 2U, /**< None */ } pis_con_t; -/** - * @brief Indirect value,no care of it. - */ -typedef union { - struct { - uint8_t ch :4; /**< Channel */ - uint8_t con :4; /**< Contorl */ - uint8_t shift :8; /**< Shift */ - }; - uint16_t HalfWord; -} pis_divide_t; - /** * @brief PIS state structures definition */ typedef enum { - PIS_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - PIS_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - PIS_STATE_BUSY = 0x02, /**< An internal process is ongoing */ - PIS_STATE_TIMEOUT = 0x03, /**< Timeout state */ - PIS_STATE_ERROR = 0x04, /**< Error */ + PIS_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + PIS_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + PIS_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ + PIS_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + PIS_STATE_ERROR = 0x04U, /**< Error */ } pis_state_t; /** * @brief PIS modulate target */ typedef enum { - PIS_UART0_TX = 0, /**< Modulate uart0 tx */ - PIS_UART1_TX = 1, /**< Modulate uart1 tx */ - PIS_UART2_TX = 2, /**< Modulate uart2 tx */ - PIS_UART3_TX = 3, /**< Modulate uart3 tx */ - PIS_LPUART0_TX = 4, /**< Modulate lpuart0 tx */ + PIS_UART0_TX = 0U, /**< Modulate uart0 tx */ + PIS_UART1_TX = 1U, /**< Modulate uart1 tx */ + PIS_UART2_TX = 2U, /**< Modulate uart2 tx */ + PIS_UART3_TX = 3U, /**< Modulate uart3 tx */ + PIS_LPUART0_TX = 4U, /**< Modulate lpuart0 tx */ } pis_modu_targ_t; /** * @brief PIS modulate level */ typedef enum { - PIS_LOW_LEVEL = 0, /**< Modulate low level */ - PIS_HIGH_LEVEL = 1, /**< Modulate high level */ + PIS_LOW_LEVEL = 0U, /**< Modulate low level */ + PIS_HIGH_LEVEL = 1U, /**< Modulate high level */ } pis_modu_level_t; /** * @brief PIS modulate source */ typedef enum { - PIS_SRC_NONE = 0, /**< Stop modulate */ - PIS_SRC_TIMER0 = 1, /**< Modulate source is TIMER0 */ - PIS_SRC_TIMER1 = 2, /**< Modulate source is TIMER1 */ - PIS_SRC_TIMER2 = 3, /**< Modulate source is TIMER2 */ - PIS_SRC_TIMER3 = 4, /**< Modulate source is TIMER3 */ - PIS_SRC_TIMER6 = 5, /**< Modulate source is TIMER6 */ - PIS_SRC_TIMER7 = 6, /**< Modulate source is TIMER7 */ - PIS_SRC_LPTIM0 = 7, /**< Modulate source is LPTIM0 */ - PIS_SRC_BUZ = 8, /**< Modulate source is buz */ + PIS_SRC_NONE = 0U, /**< Stop modulate */ + PIS_SRC_TIMER0 = 1U, /**< Modulate source is TIMER0 */ + PIS_SRC_TIMER1 = 2U, /**< Modulate source is TIMER1 */ + PIS_SRC_TIMER2 = 3U, /**< Modulate source is TIMER2 */ + PIS_SRC_TIMER3 = 4U, /**< Modulate source is TIMER3 */ + PIS_SRC_TIMER6 = 5U, /**< Modulate source is TIMER6 */ + PIS_SRC_TIMER7 = 6U, /**< Modulate source is TIMER7 */ + PIS_SRC_LPTIM0 = 7U, /**< Modulate source is LPTIM0 */ + PIS_SRC_BUZ = 8U, /**< Modulate source is buz */ } pis_modu_src_t; /** * @brief PIS modulate channel */ typedef enum { - PIS_TIMER_CH1 = 0, /**< Src is TIMERx and choose channel 1 */ - PIS_TIMER_CH2 = 1, /**< Src is TIMERx and choose channel 2 */ - PIS_TIMER_CH3 = 2, /**< Src is TIMERx and choose channel 3 */ - PIS_TIMER_CH4 = 3, /**< Src is TIMERx and choose channel 4 */ + PIS_TIMER_CH1 = 0U, /**< Src is TIMERx and choose channel 1 */ + PIS_TIMER_CH2 = 1U, /**< Src is TIMERx and choose channel 2 */ + PIS_TIMER_CH3 = 2U, /**< Src is TIMERx and choose channel 3 */ + PIS_TIMER_CH4 = 3U, /**< Src is TIMERx and choose channel 4 */ } pis_modu_channel_t; /** * @brief PIS input channel chose */ typedef enum { - PIS_NONE_INPUT = 0, /**< Consumer input none */ - PIS_PORT_INPUT = 1, /**< Consumer input choose external port */ - PIS_CHAN_INPUT = 2 /**< Consumer input choose pis channel */ + PIS_NONE_INPUT = 0U, /**< Consumer input none */ + PIS_PORT_INPUT = 1U, /**< Consumer input choose external port */ + PIS_CHAN_INPUT = 2U, /**< Consumer input choose pis channel */ } pis_input_sel_t; /** @@ -469,8 +455,8 @@ typedef struct pis_handle_s { ((x) == PIS_ACMP_OUT1) || \ ((x) == PIS_DAC0_CH0) || \ ((x) == PIS_DAC0_CH1) || \ - ((x) == PIS_ADC0_INJECT) || \ - ((x) == PIS_ADC0_REGULAT) || \ + ((x) == PIS_ADC0_INSERT) || \ + ((x) == PIS_ADC0_NORMAL) || \ ((x) == PIS_ADC0_RESERVE) || \ ((x) == PIS_LVD) || \ ((x) == PIS_UART0_RESERVE0) || \ @@ -544,7 +530,31 @@ typedef struct pis_handle_s { ((x) == PIS_TIMER2_INPUT_2) || \ ((x) == PIS_TIMER2_OUTPUT_2) || \ ((x) == PIS_TIMER2_INPUT_3) || \ - ((x) == PIS_TIMER2_OUTPUT_3)) + ((x) == PIS_TIMER2_OUTPUT_3) || \ + ((x) == PIS_TIMER2_INPUT_4) || \ + ((x) == PIS_TIMER2_OUTPUT_4) || \ + ((x) == PIS_TIMER3_UPDATA) || \ + ((x) == PIS_TIMER3_TRIG) || \ + ((x) == PIS_TIMER3_INPUT_1) || \ + ((x) == PIS_TIMER3_OUTPUT_1) || \ + ((x) == PIS_TIMER3_INPUT_2) || \ + ((x) == PIS_TIMER3_OUTPUT_2) || \ + ((x) == PIS_TIMER3_INPUT_3) || \ + ((x) == PIS_TIMER3_OUTPUT_3) || \ + ((x) == PIS_TIMER3_INPUT_4) || \ + ((x) == PIS_TIMER3_OUTPUT_4) || \ + ((x) == PIS_RTC_CLOCK) || \ + ((x) == PIS_RTC_ALARM) || \ + ((x) == PIS_LPTIMER0_SYN_UPDATA) || \ + ((x) == PIS_LPTIMER0_ASY_UPDATA) || \ + ((x) == PIS_LPUART0_ASY_RECV) || \ + ((x) == PIS_LPUART0_ASY_SEND) || \ + ((x) == PIS_LPUART0_SYN_RECV) || \ + ((x) == PIS_LPUART0_SYN_SEND) || \ + ((x) == PIS_DMA) || \ + ((x) == PIS_ADC1_INSERT) || \ + ((x) == PIS_ADC1_NORMAL) || \ + ((x) == PIS_ADC1_RESERVE)) #define IS_PIS_TRIG(x) (((x) == PIS_CH12_TIMER0_ITR0) || \ ((x) == PIS_CH13_TIMER0_ITR1) || \ ((x) == PIS_CH14_TIMER0_ITR2) || \ @@ -561,8 +571,10 @@ typedef struct pis_handle_s { ((x) == PIS_CH13_TIMER3_ITR1) || \ ((x) == PIS_CH14_TIMER3_ITR2) || \ ((x) == PIS_CH15_TIMER3_ITR3) || \ - ((x) == PIS_CH6_ADC0_REGULAT) || \ - ((x) == PIS_CH7_ADC0_INJECT) || \ + ((x) == PIS_CH6_ADC0_NORMAL ) || \ + ((x) == PIS_CH7_ADC0_INSERT) || \ + ((x) == PIS_CH0_ADC1_NORMAL) || \ + ((x) == PIS_CH1_ADC1_INSERT) || \ ((x) == PIS_CH0_LPTIM0_EXT0) || \ ((x) == PIS_CH1_LPTIM0_EXT1) || \ ((x) == PIS_CH2_LPTIM0_EXT2) || \ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h index 79f644b55953611cef62e1b9294d6deaddb63ffb..d58c34db24d2246ea20cea554d7d39df316058fc 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h @@ -37,29 +37,41 @@ extern "C" { /** @defgroup PMU_Public_Macros PMU Public Macros * @{ */ -#define PMU_LPSTOP_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \ - SYSCFG_LOCK(); \ +#define PMU_LPSTOP_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define PMU_LPSTOP_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \ - SYSCFG_LOCK(); \ +#define PMU_LPSTOP_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define PMU_MTSTOP_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \ - SYSCFG_LOCK(); \ +#define PMU_FLASH_MODE_IDLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR0, PMU_CR0_SFPD_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define PMU_MTSTOP_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \ - SYSCFG_LOCK(); \ +#define PMU_FLASH_MODE_WAIT() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR0, PMU_CR0_SFPD_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define PMU_MTSTOP_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define PMU_MTSTOP_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); \ + SYSCFG_LOCK(); \ } while (0) #define PMU_VREF_ENABLE() \ do { \ @@ -87,11 +99,21 @@ do { \ * @brief Low power mode */ typedef enum { - PMU_LP_STOP1 = 0x0, /**< Stop1 */ - PMU_LP_STOP2 = 0x1, /**< Stop2 */ - PMU_LP_STANDBY = 0x2, /**< Standby */ + PMU_LP_STOP1 = 0x0U, /**< Stop1 */ + PMU_LP_STOP2 = 0x1U, /**< Stop2 */ + PMU_LP_STANDBY = 0x2U, /**< Standby */ } pmu_lp_mode_t; +/** + * @brief LDO_18 mode + */ +typedef enum { + PMU_LDO_18_DRV_HIGH = 0x0U, /**< High drive */ + PMU_LDO_18_DRV_LOW = 0x1U, /**< Low drive */ + PMU_LDO_18_HOLD = 0x2U, /**< Hold */ + PMU_LDO_18_OFF = 0x3U, /**< Turn off */ +} pmu_ldo_18_mode_t; + typedef enum { PMU_SR_WUF = (1U << 0), /**< WakeUp status */ PMU_SR_STANDBYF = (1U << 1), /**< Standby status */ @@ -103,55 +125,55 @@ typedef enum { * @brief LVD voltage select */ typedef enum { - PMU_LVD_VOL_SEL_2_2 = 0x0, /**< 2.2V ~ 2.25V */ - PMU_LVD_VOL_SEL_2_4 = 0x1, /**< 2.4V ~ 2.45V */ - PMU_LVD_VOL_SEL_2_6 = 0x2, /**< 2.6V ~ 2.65V */ - PMU_LVD_VOL_SEL_2_8 = 0x3, /**< 2.8V ~ 2.85V */ - PMU_LVD_VOL_SEL_3_0 = 0x4, /**< 3.0V ~ 3.05V */ - PMU_LVD_VOL_SEL_3_2 = 0x5, /**< 3.2V ~ 3.25V */ - PMU_LVD_VOL_SEL_3_4 = 0x6, /**< 3.4V ~ 3.45V */ - PMU_LVD_VOL_SEL_3_6 = 0x7, /**< 3.6V ~ 3.65V */ - PMU_LVD_VOL_SEL_3_8 = 0x8, /**< 3.8V ~ 3.85V */ - PMU_LVD_VOL_SEL_4_0 = 0x9, /**< 4.0V ~ 4.05V */ - PMU_LVD_VOL_SEL_4_2 = 0x9, /**< 4.2V ~ 4.25V */ - PMU_LVD_VOL_SEL_4_4 = 0x9, /**< 4.4V ~ 4.45V */ - PMU_LVD_VOL_SEL_4_6 = 0x9, /**< 4.6V ~ 4.65V */ - PMU_LVD_VOL_SEL_4_8 = 0x9, /**< 4.8V ~ 4.85V */ - PMU_LVD_VOL_SEL_EXT = 0xF, /**< Select external input. It must be 1.2V */ + PMU_LVD_VOL_SEL_2_2 = 0x0U, /**< 2.2V ~ 2.25V */ + PMU_LVD_VOL_SEL_2_4 = 0x1U, /**< 2.4V ~ 2.45V */ + PMU_LVD_VOL_SEL_2_6 = 0x2U, /**< 2.6V ~ 2.65V */ + PMU_LVD_VOL_SEL_2_8 = 0x3U, /**< 2.8V ~ 2.85V */ + PMU_LVD_VOL_SEL_3_0 = 0x4U, /**< 3.0V ~ 3.05V */ + PMU_LVD_VOL_SEL_3_2 = 0x5U, /**< 3.2V ~ 3.25V */ + PMU_LVD_VOL_SEL_3_4 = 0x6U, /**< 3.4V ~ 3.45V */ + PMU_LVD_VOL_SEL_3_6 = 0x7U, /**< 3.6V ~ 3.65V */ + PMU_LVD_VOL_SEL_3_8 = 0x8U, /**< 3.8V ~ 3.85V */ + PMU_LVD_VOL_SEL_4_0 = 0x9U, /**< 4.0V ~ 4.05V */ + PMU_LVD_VOL_SEL_4_2 = 0xAU, /**< 4.2V ~ 4.25V */ + PMU_LVD_VOL_SEL_4_4 = 0xBU, /**< 4.4V ~ 4.45V */ + PMU_LVD_VOL_SEL_4_6 = 0xCU, /**< 4.6V ~ 4.65V */ + PMU_LVD_VOL_SEL_4_8 = 0xDU, /**< 4.8V ~ 4.85V */ + PMU_LVD_VOL_SEL_EXT = 0xFU, /**< Select external input. It must be 1.2V */ } pmu_lvd_voltage_sel_t; /** * @brief LVD trigger mode */ typedef enum { - PMU_LVD_TRIGGER_RISING_EDGE = 0x0, /**< Rising edge */ - PMU_LVD_TRIGGER_FALLING_EDGE = 0x1, /**< Falling edge */ - PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2, /**< High level */ - PMU_LVD_TRIGGER_LOW_LEVEL = 0x3, /**< Low level */ - PMU_LVD_TRIGGER_RISING_FALLING = 0x4, /**< Rising and falling edge */ + PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, /**< Rising edge */ + PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, /**< Falling edge */ + PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, /**< High level */ + PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U, /**< Low level */ + PMU_LVD_TRIGGER_RISING_FALLING = 0x4U, /**< Rising and falling edge */ } pmu_lvd_trigger_mode_t; /** * @brief LDO output voltage selest in low power mode */ typedef enum { - PMU_LDO_LPMODE_OUTPUT_0_9 = 0x0, /**< 0.9V */ - PMU_LDO_LPMODE_OUTPUT_1_0 = 0x1, /**< 1.0V */ - PMU_LDO_LPMODE_OUTPUT_1_1 = 0x2, /**< 1.1V */ - PMU_LDO_LPMODE_OUTPUT_1_2 = 0x3, /**< 1.2V */ + PMU_LDO_LPMODE_OUTPUT_0_9 = 0x0U, /**< 0.9V */ + PMU_LDO_LPMODE_OUTPUT_1_0 = 0x1U, /**< 1.0V */ + PMU_LDO_LPMODE_OUTPUT_1_1 = 0x2U, /**< 1.1V */ + PMU_LDO_LPMODE_OUTPUT_1_2 = 0x3U, /**< 1.2V */ } pmu_ldo_lpmode_output_t; typedef enum { - PMU_POWER_SRAM0 = 0x1, /**< SRAM0 */ - PMU_POWER_SRAM1 = 0x2, /**< SRAM1 */ - PMU_POWER_SRAM2 = 0x4, /**< SRAM2 */ - PMU_POWER_SRAM3 = 0x8, /**< SRAM3 */ - PMU_POWER_SRAM4 = 0x10, /**< SRAM4 */ - PMU_POWER_SRAM5 = 0x20, /**< SRAM5 */ - PMU_POWER_CAN = 0x100, /**< CAN */ - PMU_POWER_QSPI = 0x400, /**< QSPI */ - PMU_POWER_USB = 0x800, /**< USB */ - PMU_POWER_ROM = 0x1000, /**< ROM */ + PMU_POWER_SRAM0 = 0x1U, /**< SRAM0 */ + PMU_POWER_SRAM1 = 0x2U, /**< SRAM1 */ + PMU_POWER_SRAM2 = 0x4U, /**< SRAM2 */ + PMU_POWER_SRAM3 = 0x8U, /**< SRAM3 */ + PMU_POWER_SRAM4 = 0x10U, /**< SRAM4 */ + PMU_POWER_SRAM5 = 0x20U, /**< SRAM5 */ + PMU_POWER_CAN = 0x100U, /**< CAN */ + PMU_POWER_QSPI = 0x400U, /**< QSPI */ + PMU_POWER_USB = 0x800U, /**< USB */ + PMU_POWER_ROM = 0x1000U, /**< ROM */ } pmu_perh_power_t; /** @@ -165,6 +187,10 @@ typedef enum { #define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \ ((x) == PMU_LP_STOP2) || \ ((x) == PMU_LP_STANDBY)) +#define IS_PMU_LDO18_MODE(x) (((x) == PMU_LDO_18_DRV_HIGH) || \ + ((x) == PMU_LDO_18_DRV_LOW) || \ + ((x) == PMU_LDO_18_HOLD) || \ + ((x) == PMU_LDO_18_OFF)) #define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || \ ((x) == PMU_SR_STANDBYF) || \ ((x) == PMU_SR_USBRDY) || \ @@ -229,7 +255,11 @@ __STATIC_INLINE__ void ald_pmu_sleep_deep() void ald_pmu_stop1_enter(void); void ald_pmu_stop2_enter(void); void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level); +void ald_pmu_ldo_12_config(type_func_t state); +void ald_pmu_ldo_18_config(pmu_ldo_18_mode_t mode); +#ifdef ES32F336x /* MCU Series: ES32F336x */ void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state); +#endif flag_status_t ald_pmu_get_status(pmu_status_t sr); void ald_pmu_clear_status(pmu_status_t sr); void ald_pmu_perh_power_config(pmu_perh_power_t perh, type_func_t state); diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h index a8a2a500cc2a7101bd3435257e11341071e460c3..a8e80b09d8a974b33bd9e9a590cf3be486314828 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h @@ -35,91 +35,91 @@ extern "C" { * @brief ALD QSPI state */ typedef enum { - QSPI_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - QSPI_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ + QSPI_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ + QSPI_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ } qspi_state_t; /** * @brief QSPI Instruction Transfer Type */ typedef enum { - QSPI_XFER_SINGLE = 0x00, /**< Instruction shifted on DQ0 only*/ - QSPI_XFER_DUAL = 0x01, /**< Instruction,Address and data sent on DQ0 and DQ1*/ - QSPI_XFER_QUAD = 0x02, /**< Instruction,Address and data sent on DQ0,DQ1 and DQ2*/ + QSPI_XFER_SINGLE = 0x00U, /**< Instruction shifted on DQ0 only*/ + QSPI_XFER_DUAL = 0x01U, /**< Instruction,Address and data sent on DQ0 and DQ1*/ + QSPI_XFER_QUAD = 0x02U, /**< Instruction,Address and data sent on DQ0,DQ1 and DQ2*/ } qspi_xfer_t; /** * @brief QSPI Indirect Access SRAM fill level */ typedef enum { - QSPI_SRAM_RD = 0, /**< SRAM fill level(indirect write partition)in units of words(4bytes)*/ - QSPI_SRAM_WR = 1, /**< SRAM fill level(indirect read partition)in units of words(4bytes)*/ + QSPI_SRAM_RD = 0U, /**< SRAM fill level(indirect write partition)in units of words(4bytes)*/ + QSPI_SRAM_WR = 1U, /**< SRAM fill level(indirect read partition)in units of words(4bytes)*/ } qspi_sram_t; /** * @brief QSPI Clock Phase */ typedef enum { - QSPI_CPHA_1E = 0, /**< First edge*/ - QSPI_CPHA_2E = 1, /**< Second edge*/ + QSPI_CPHA_1E = 0U, /**< First edge*/ + QSPI_CPHA_2E = 1U, /**< Second edge*/ } qspi_cpha_t; /** * @brief QSPI_Clock_Polarity QSPI Clock Polarity */ typedef enum { - QSPI_CPOL_L = 0, /**< QSPI clock polarity low */ - QSPI_CPOL_H = 1, /**< QSPI clock polarity high */ + QSPI_CPOL_L = 0U, /**< QSPI clock polarity low */ + QSPI_CPOL_H = 1U, /**< QSPI clock polarity high */ } qspi_cpol_t; /** * @brief QSPI peripheral select decode */ typedef enum { - QSPI_SINGLE_CHIP = 0x0, /**< Only 1 of 4 selects n_ss_out[3:0] is active */ - QSPI_MULTI_CHIP = 0x1, /**< Allow external 4-to-16 decode */ + QSPI_SINGLE_CHIP = 0x0U, /**< Only 1 of 4 selects n_ss_out[3:0] is active */ + QSPI_MULTI_CHIP = 0x1U, /**< Allow external 4-to-16 decode */ } qspi_nss_decode_t; /** * @brief QSPI_Baud_Rate_Clock_Prescaler QSPI Baud Rate Clock Prescaler */ typedef enum { - QSPI_DIV_2 = 0x0, /**< Master mode baud rate dibisor 2*/ - QSPI_DIV_4 = 0x1, /**< Master mode baud rate dibisor 4*/ - QSPI_DIV_6 = 0x2, /**< Master mode baud rate dibisor 6*/ - QSPI_DIV_8 = 0x3, /**< Master mode baud rate dibisor 8*/ - QSPI_DIV_10 = 0x4, /**< Master mode baud rate dibisor 10*/ - QSPI_DIV_12 = 0x5, /**< Master mode baud rate dibisor 12*/ - QSPI_DIV_14 = 0x6, /**< Master mode baud rate dibisor 14*/ - QSPI_DIV_16 = 0x7, /**< Master mode baud rate dibisor 16*/ - QSPI_DIV_18 = 0x8, /**< Master mode baud rate dibisor 18*/ - QSPI_DIV_20 = 0x9, /**< Master mode baud rate dibisor 20*/ - QSPI_DIV_22 = 0xA, /**< Master mode baud rate dibisor 22*/ - QSPI_DIV_24 = 0xB, /**< Master mode baud rate dibisor 24*/ - QSPI_DIV_26 = 0xC, /**< Master mode baud rate dibisor 26*/ - QSPI_DIV_28 = 0xD, /**< Master mode baud rate dibisor 28*/ - QSPI_DIV_30 = 0xE, /**< Master mode baud rate dibisor 30*/ - QSPI_DIV_32 = 0xF, /**< Master mode baud rate dibisor 32*/ + QSPI_DIV_2 = 0x0U, /**< Master mode baud rate dibisor 2*/ + QSPI_DIV_4 = 0x1U, /**< Master mode baud rate dibisor 4*/ + QSPI_DIV_6 = 0x2U, /**< Master mode baud rate dibisor 6*/ + QSPI_DIV_8 = 0x3U, /**< Master mode baud rate dibisor 8*/ + QSPI_DIV_10 = 0x4U, /**< Master mode baud rate dibisor 10*/ + QSPI_DIV_12 = 0x5U, /**< Master mode baud rate dibisor 12*/ + QSPI_DIV_14 = 0x6U, /**< Master mode baud rate dibisor 14*/ + QSPI_DIV_16 = 0x7U, /**< Master mode baud rate dibisor 16*/ + QSPI_DIV_18 = 0x8U, /**< Master mode baud rate dibisor 18*/ + QSPI_DIV_20 = 0x9U, /**< Master mode baud rate dibisor 20*/ + QSPI_DIV_22 = 0xAU, /**< Master mode baud rate dibisor 22*/ + QSPI_DIV_24 = 0xBU, /**< Master mode baud rate dibisor 24*/ + QSPI_DIV_26 = 0xCU, /**< Master mode baud rate dibisor 26*/ + QSPI_DIV_28 = 0xDU, /**< Master mode baud rate dibisor 28*/ + QSPI_DIV_30 = 0xEU, /**< Master mode baud rate dibisor 30*/ + QSPI_DIV_32 = 0xFU, /**< Master mode baud rate dibisor 32*/ } qspi_clk_div_t; /** * @brief QSPI Peripheral chip select decode */ typedef enum { - QSPI_CS_NSS0 = 0x0, /**< NSS0 active*/ - QSPI_CS_NSS1 = 0x1, /**< NSS1 active*/ - QSPI_CS_NSS2 = 0x3, /**< NSS2 active*/ - QSPI_CS_NSS3 = 0x7, /**< NSS3 active*/ + QSPI_CS_NSS0 = 0x0U, /**< NSS0 active*/ + QSPI_CS_NSS1 = 0x1U, /**< NSS1 active*/ + QSPI_CS_NSS2 = 0x3U, /**< NSS2 active*/ + QSPI_CS_NSS3 = 0x7U, /**< NSS3 active*/ } qspi_nss_t; /** *@brief Size of flash connected to CS[x](x = 0 ~ 3)pin */ typedef enum { - QSPI_NSS_512M = 0x0, /**< size of 512Mb*/ - QSPI_NSS_1G = 0x1, /**< size of 1Gb*/ - QSPI_NSS_2G = 0x2, /**< size of 2Gb*/ - QSPI_NSS_4G = 0x3, /**< size of 3Gb*/ + QSPI_NSS_512M = 0x0U, /**< size of 512Mb*/ + QSPI_NSS_1G = 0x1U, /**< size of 1Gb*/ + QSPI_NSS_2G = 0x2U, /**< size of 2Gb*/ + QSPI_NSS_4G = 0x3U, /**< size of 3Gb*/ } qspi_nss_size_t; /** @@ -139,8 +139,8 @@ typedef struct { * @brief QSPI Sample Edge Selection */ typedef enum { - QSPI_FALLING_E = 0x0, /**< Data outputs from flash are sampled on falling edge of the ref_clk*/ - QSPI_RISING_E = 0x1, /**< Data outputs from flash are sampled on rising edge of the ref_clk*/ + QSPI_FALLING_E = 0x0U, /**< Data outputs from flash are sampled on falling edge of the ref_clk*/ + QSPI_RISING_E = 0x1U, /**< Data outputs from flash are sampled on rising edge of the ref_clk*/ } qspi_data_sampled_t; /** @@ -451,10 +451,10 @@ typedef enum { * @defgroup QSPI_Public_Macros QSPI Public Macros * @{ */ -#define QSPI_MEMORY_ADDRESS 0x90000000 -#define QSPI_SRAM_SIZE 255 +#define QSPI_MEMORY_ADDRESS 0x90000000U +#define QSPI_SRAM_SIZE 255U #define QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5s */ -#define QSPI_SRAM_DEPTH 0xFF +#define QSPI_SRAM_DEPTH 0xFFU #define QSPI_DAC_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK) #define QSPI_DAC_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK) #define QSPI_LEGACY_SPI_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK) diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h index 3aaf0116928321000f525147290f405c2dd9468e..07319306b0ff4d14d9d0543da65ba073d952ae68 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h @@ -38,35 +38,35 @@ extern "C" { * @brief RMU BOR fliter */ typedef enum { - RMU_BORFLT_1 = 0x1, /**< 1 cycle */ - RMU_BORFLT_2 = 0x2, /**< 2 cycles */ - RMU_BORFLT_3 = 0x3, /**< 3 cycles */ - RMU_BORFLT_4 = 0x4, /**< 4 cycles */ - RMU_BORFLT_5 = 0x5, /**< 5 cycles */ - RMU_BORFLT_6 = 0x6, /**< 6 cycles */ - RMU_BORFLT_7 = 0x7, /**< 7 cycles */ + RMU_BORFLT_1 = 0x1U, /**< 1 cycle */ + RMU_BORFLT_2 = 0x2U, /**< 2 cycles */ + RMU_BORFLT_3 = 0x3U, /**< 3 cycles */ + RMU_BORFLT_4 = 0x4U, /**< 4 cycles */ + RMU_BORFLT_5 = 0x5U, /**< 5 cycles */ + RMU_BORFLT_6 = 0x6U, /**< 6 cycles */ + RMU_BORFLT_7 = 0x7U, /**< 7 cycles */ } rmu_bor_filter_t; /** * @brief RMU BOR voltage */ typedef enum { - RMU_VOL_NONE = 0x0, /**< Disable */ - RMU_VOL_2_0 = 0x1, /**< 2.0V */ - RMU_VOL_2_2 = 0x2, /**< 2.2V */ - RMU_VOL_2_4 = 0x3, /**< 2.4V */ - RMU_VOL_2_6 = 0x4, /**< 2.6V */ - RMU_VOL_2_8 = 0x5, /**< 2.8V */ - RMU_VOL_3_0 = 0x6, /**< 3.0V */ - RMU_VOL_3_2 = 0x7, /**< 3.2V */ - RMU_VOL_3_4 = 0x8, /**< 3.4V */ - RMU_VOL_3_6 = 0x9, /**< 3.6V */ - RMU_VOL_3_8 = 0xA, /**< 3.8V */ - RMU_VOL_4_0 = 0xB, /**< 4.0V */ - RMU_VOL_4_2 = 0xC, /**< 4.2V */ - RMU_VOL_4_4 = 0xD, /**< 4.4V */ - RMU_VOL_4_6 = 0xE, /**< 4.6V */ - RMU_VOL_4_8 = 0xF, /**< 4.8V */ + RMU_VOL_NONE = 0x0U, /**< Disable */ + RMU_VOL_2_0 = 0x1U, /**< 2.0V */ + RMU_VOL_2_2 = 0x2U, /**< 2.2V */ + RMU_VOL_2_4 = 0x3U, /**< 2.4V */ + RMU_VOL_2_6 = 0x4U, /**< 2.6V */ + RMU_VOL_2_8 = 0x5U, /**< 2.8V */ + RMU_VOL_3_0 = 0x6U, /**< 3.0V */ + RMU_VOL_3_2 = 0x7U, /**< 3.2V */ + RMU_VOL_3_4 = 0x8U, /**< 3.4V */ + RMU_VOL_3_6 = 0x9U, /**< 3.6V */ + RMU_VOL_3_8 = 0xAU, /**< 3.8V */ + RMU_VOL_4_0 = 0xBU, /**< 4.0V */ + RMU_VOL_4_2 = 0xCU, /**< 4.2V */ + RMU_VOL_4_4 = 0xDU, /**< 4.4V */ + RMU_VOL_4_6 = 0xEU, /**< 4.6V */ + RMU_VOL_4_8 = 0xFU, /**< 4.8V */ } rmu_bor_vol_t; /** @@ -85,10 +85,35 @@ typedef enum { RMU_RST_CPU = (1U << 9), /**< CPU */ RMU_RST_CFG = (1U << 10), /**< CFG */ RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ + RMU_RST_ALL = (0xFFFFFU), /**< ALL */ } rmu_state_t; /** * @brief RMU periperal select bit + * @verbatim + In this module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F36xx series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> AD16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + TIMER4 ----> BS16T0 + TIMER5 ----> BS16T1 + TIMER6 ----> GP16C4T0 + TIMER7 ----> GP16C4T1 + + 2. For ES32F393x/ES32F336x/ES32F392x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> GP16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + TIMER4 ----> BS16T0 + TIMER5 ----> BS16T1 + TIMER6 ----> GP16C4T2 + TIMER7 ----> GP16C4T3 + @endverbatim */ typedef enum { RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ @@ -182,7 +207,8 @@ typedef enum { ((x) == RMU_RST_MCU) || \ ((x) == RMU_RST_CPU) || \ ((x) == RMU_RST_CFG) || \ - ((x) == RMU_RST_CFGERR)) + ((x) == RMU_RST_CFGERR) || \ + ((x) == RMU_RST_ALL)) #define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \ ((x) == RMU_RST_WAKEUP) || \ ((x) == RMU_RST_BOR) || \ @@ -193,7 +219,8 @@ typedef enum { ((x) == RMU_RST_CHIP) || \ ((x) == RMU_RST_MCU) || \ ((x) == RMU_RST_CPU) || \ - ((x) == RMU_RST_CFG)) + ((x) == RMU_RST_CFG) || \ + ((x) == RMU_RST_ALL)) #define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \ ((x) == RMU_PERH_CRC) || \ ((x) == RMU_PERH_CALC) || \ @@ -250,7 +277,7 @@ typedef enum { * @{ */ void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state); -flag_status_t ald_rmu_get_reset_status(rmu_state_t state); +uint32_t ald_rmu_get_reset_status(rmu_state_t state); void ald_rmu_clear_reset_status(rmu_state_t state); void ald_rmu_reset_periperal(rmu_peripheral_t perh); /** diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h index 0dd6f676b5ecc6f5bd8a9a1b607d235efd749b3e..4c31312e84afc76744dc192f20e421fad047c48e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h @@ -39,26 +39,26 @@ extern "C" { * @brief Hours format */ typedef enum { - RTC_HOUR_FORMAT_24 = 0x0, /**< 24-hours format */ - RTC_HOUR_FORMAT_12 = 0x1, /**< 12-hours format */ + RTC_HOUR_FORMAT_24 = 0x0U, /**< 24-hours format */ + RTC_HOUR_FORMAT_12 = 0x1U, /**< 12-hours format */ } rtc_hour_format_t; /** * @brief Output mode */ typedef enum { - RTC_OUTPUT_DISABLE = 0x0, /**< Disable output */ - RTC_OUTPUT_ALARM_A = 0x1, /**< Output alarm_a signal */ - RTC_OUTPUT_ALARM_B = 0x2, /**< Output alarm_b signal */ - RTC_OUTPUT_WAKEUP = 0x3, /**< Output wakeup signal */ + RTC_OUTPUT_DISABLE = 0x0U, /**< Disable output */ + RTC_OUTPUT_ALARM_A = 0x1U, /**< Output alarm_a signal */ + RTC_OUTPUT_ALARM_B = 0x2U, /**< Output alarm_b signal */ + RTC_OUTPUT_WAKEUP = 0x3U, /**< Output wakeup signal */ } rtc_output_select_t; /** * @brief Output polarity */ typedef enum { - RTC_OUTPUT_POLARITY_HIGH = 0x0, /**< Polarity is high */ - RTC_OUTPUT_POLARITY_LOW = 0x1, /**< Polarity is low */ + RTC_OUTPUT_POLARITY_HIGH = 0x0U, /**< Polarity is high */ + RTC_OUTPUT_POLARITY_LOW = 0x1U, /**< Polarity is low */ } rtc_output_polarity_t; /** @@ -76,10 +76,10 @@ typedef struct { * @brief Source select */ typedef enum { - RTC_SOURCE_LOSC = 0x0, /**< LOSC */ - RTC_SOURCE_LRC = 0x1, /**< LRC */ - RTC_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ - RTC_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ + RTC_SOURCE_LOSC = 0x0U, /**< LOSC */ + RTC_SOURCE_LRC = 0x1U, /**< LRC */ + RTC_SOURCE_HRC_DIV_1M = 0x2U, /**< HRC divide to 1MHz */ + RTC_SOURCE_HOSC_DIV_1M = 0x3U, /**< HOSC divide to 1MHz */ } rtc_source_sel_t; /** @@ -106,57 +106,57 @@ typedef struct { * @brief Data format */ typedef enum { - RTC_FORMAT_DEC = 0, /**< Decimal */ - RTC_FORMAT_BCD = 1, /**< BSD */ + RTC_FORMAT_DEC = 0U, /**< Decimal */ + RTC_FORMAT_BCD = 1U, /**< BSD */ } rtc_format_t; /** * @brief Index of alarm */ typedef enum { - RTC_ALARM_A = 0x0, /**< Alarm-A */ - RTC_ALARM_B = 0x1, /**< Alarm-B */ + RTC_ALARM_A = 0x0U, /**< Alarm-A */ + RTC_ALARM_B = 0x1U, /**< Alarm-B */ } rtc_alarm_idx_t; /** * @brief Alarm mask */ typedef enum { - RTC_ALARM_MASK_NONE = 0x0, /**< Mask is disable */ + RTC_ALARM_MASK_NONE = 0x0U, /**< Mask is disable */ RTC_ALARM_MASK_WEEK_DAY = (1U << 30), /**< Mask week or day */ RTC_ALARM_MASK_HOUR = (1U << 23), /**< Mask hour */ RTC_ALARM_MASK_MINUTE = (1U << 15), /**< Mask minute */ RTC_ALARM_MASK_SECOND = (1U << 7), /**< Mask second */ - RTC_ALARM_MASK_ALL = 0x40808080, /**< Mask all */ + RTC_ALARM_MASK_ALL = 0x40808080U, /**< Mask all */ } rtc_alarm_mask_t; /** * @brief Alarm sub-second mask */ typedef enum { - RTC_ALARM_SS_MASK_NONE = 0xF, /**< Mask is disable */ - RTC_ALARM_SS_MASK_14_1 = 0x1, /**< Mask bit(1-14) */ - RTC_ALARM_SS_MASK_14_2 = 0x2, /**< Mask bit(2-14) */ - RTC_ALARM_SS_MASK_14_3 = 0x3, /**< Mask bit(3-14) */ - RTC_ALARM_SS_MASK_14_4 = 0x4, /**< Mask bit(4-14) */ - RTC_ALARM_SS_MASK_14_5 = 0x5, /**< Mask bit(5-14) */ - RTC_ALARM_SS_MASK_14_6 = 0x6, /**< Mask bit(6-14) */ - RTC_ALARM_SS_MASK_14_7 = 0x7, /**< Mask bit(7-14) */ - RTC_ALARM_SS_MASK_14_8 = 0x8, /**< Mask bit(8-14) */ - RTC_ALARM_SS_MASK_14_9 = 0x9, /**< Mask bit(9-14) */ - RTC_ALARM_SS_MASK_14_10 = 0xA, /**< Mask bit(10-14) */ - RTC_ALARM_SS_MASK_14_11 = 0xB, /**< Mask bit(11-14) */ - RTC_ALARM_SS_MASK_14_12 = 0xC, /**< Mask bit(12-14) */ - RTC_ALARM_SS_MASK_14_13 = 0xD, /**< Mask bit(13-14) */ - RTC_ALARM_SS_MASK_14 = 0xE, /**< Mask bit14 */ - RTC_ALARM_SS_MASK_ALL = 0x0, /**< Mask bit(0-14) */ + RTC_ALARM_SS_MASK_NONE = 0xFU, /**< Mask is disable */ + RTC_ALARM_SS_MASK_14_1 = 0x1U, /**< Mask bit(1-14) */ + RTC_ALARM_SS_MASK_14_2 = 0x2U, /**< Mask bit(2-14) */ + RTC_ALARM_SS_MASK_14_3 = 0x3U, /**< Mask bit(3-14) */ + RTC_ALARM_SS_MASK_14_4 = 0x4U, /**< Mask bit(4-14) */ + RTC_ALARM_SS_MASK_14_5 = 0x5U, /**< Mask bit(5-14) */ + RTC_ALARM_SS_MASK_14_6 = 0x6U, /**< Mask bit(6-14) */ + RTC_ALARM_SS_MASK_14_7 = 0x7U, /**< Mask bit(7-14) */ + RTC_ALARM_SS_MASK_14_8 = 0x8U, /**< Mask bit(8-14) */ + RTC_ALARM_SS_MASK_14_9 = 0x9U, /**< Mask bit(9-14) */ + RTC_ALARM_SS_MASK_14_10 = 0xAU, /**< Mask bit(10-14) */ + RTC_ALARM_SS_MASK_14_11 = 0xBU, /**< Mask bit(11-14) */ + RTC_ALARM_SS_MASK_14_12 = 0xCU, /**< Mask bit(12-14) */ + RTC_ALARM_SS_MASK_14_13 = 0xDU, /**< Mask bit(13-14) */ + RTC_ALARM_SS_MASK_14 = 0xEU, /**< Mask bit14 */ + RTC_ALARM_SS_MASK_ALL = 0x0U, /**< Mask bit(0-14) */ } rtc_sub_second_mask_t; /** * @brief Alarm select week or day */ typedef enum { - RTC_SELECT_DAY = 0x0, /**< Alarm select day */ - RTC_SELECT_WEEK = 0x1, /**< Alarm select week */ + RTC_SELECT_DAY = 0x0U, /**< Alarm select day */ + RTC_SELECT_WEEK = 0x1U, /**< Alarm select week */ } rtc_week_day_sel_t; /** @@ -179,56 +179,56 @@ typedef struct { * @brief Time stamp signel select */ typedef enum { - RTC_TS_SIGNAL_SEL_TAMPER0 = 0, /**< Select tamper0 */ - RTC_TS_SIGNAL_SEL_TAMPER1 = 1, /**< Select tamper1 */ + RTC_TS_SIGNAL_SEL_TAMPER0 = 0U, /**< Select tamper0 */ + RTC_TS_SIGNAL_SEL_TAMPER1 = 1U, /**< Select tamper1 */ } rtc_ts_signal_sel_t; /** * @brief Time stamp trigger style */ typedef enum { - RTC_TS_RISING_EDGE = 0, /**< Rising edge */ - RTC_TS_FALLING_EDGE = 1, /**< Falling edge */ + RTC_TS_RISING_EDGE = 0U, /**< Rising edge */ + RTC_TS_FALLING_EDGE = 1U, /**< Falling edge */ } rtc_ts_trigger_style_t; /** * @brief Index of tamper */ typedef enum { - RTC_TAMPER_0 = 0, /**< Tamper0 */ - RTC_TAMPER_1 = 1, /**< Tamper1 */ + RTC_TAMPER_0 = 0U, /**< Tamper0 */ + RTC_TAMPER_1 = 1U, /**< Tamper1 */ } rtc_tamper_idx_t; /** * @brief Tamper trigger type */ typedef enum { - RTC_TAMPER_TRIGGER_LOW = 0, /**< High trigger */ - RTC_TAMPER_TRIGGER_HIGH = 1, /**< Low trigger */ + RTC_TAMPER_TRIGGER_LOW = 0U, /**< High trigger */ + RTC_TAMPER_TRIGGER_HIGH = 1U, /**< Low trigger */ } rtc_tamper_trigger_t; /** * @brief Tamper sampling frequency */ typedef enum { - RTC_TAMPER_SAMPLING_FREQ_32768 = 0, /**< RTCCLK / 32768 */ - RTC_TAMPER_SAMPLING_FREQ_16384 = 1, /**< RTCCLK / 16384 */ - RTC_TAMPER_SAMPLING_FREQ_8192 = 2, /**< RTCCLK / 8192 */ - RTC_TAMPER_SAMPLING_FREQ_4096 = 3, /**< RTCCLK / 4096 */ - RTC_TAMPER_SAMPLING_FREQ_2048 = 4, /**< RTCCLK / 2048 */ - RTC_TAMPER_SAMPLING_FREQ_1024 = 5, /**< RTCCLK / 1024 */ - RTC_TAMPER_SAMPLING_FREQ_512 = 6, /**< RTCCLK / 512 */ - RTC_TAMPER_SAMPLING_FREQ_256 = 7, /**< RTCCLK / 256 */ + RTC_TAMPER_SAMPLING_FREQ_32768 = 0U, /**< RTCCLK / 32768 */ + RTC_TAMPER_SAMPLING_FREQ_16384 = 1U, /**< RTCCLK / 16384 */ + RTC_TAMPER_SAMPLING_FREQ_8192 = 2U, /**< RTCCLK / 8192 */ + RTC_TAMPER_SAMPLING_FREQ_4096 = 3U, /**< RTCCLK / 4096 */ + RTC_TAMPER_SAMPLING_FREQ_2048 = 4U, /**< RTCCLK / 2048 */ + RTC_TAMPER_SAMPLING_FREQ_1024 = 5U, /**< RTCCLK / 1024 */ + RTC_TAMPER_SAMPLING_FREQ_512 = 6U, /**< RTCCLK / 512 */ + RTC_TAMPER_SAMPLING_FREQ_256 = 7U, /**< RTCCLK / 256 */ } rtc_tamper_sampling_freq_t; /** * @brief Tamper filter time */ typedef enum { - RTC_TAMPER_DURATION_1 = 0, /**< Duration 1 sampling */ - RTC_TAMPER_DURATION_2 = 1, /**< Duration 2 sampling */ - RTC_TAMPER_DURATION_4 = 2, /**< Duration 4 sampling */ - RTC_TAMPER_DURATION_8 = 3, /**< Duration 8 sampling */ + RTC_TAMPER_DURATION_1 = 0U, /**< Duration 1 sampling */ + RTC_TAMPER_DURATION_2 = 1U, /**< Duration 2 sampling */ + RTC_TAMPER_DURATION_4 = 2U, /**< Duration 4 sampling */ + RTC_TAMPER_DURATION_8 = 3U, /**< Duration 8 sampling */ } rtc_tamper_duration_t; /** @@ -246,70 +246,70 @@ typedef struct { * @brief Wake-up clock */ typedef enum { - RTC_WAKEUP_CLOCK_DIV_16 = 0, /**< RTCCLK / 16 */ - RTC_WAKEUP_CLOCK_DIV_8 = 1, /**< RTCCLK / 8 */ - RTC_WAKEUP_CLOCK_DIV_4 = 2, /**< RTCCLK / 4 */ - RTC_WAKEUP_CLOCK_DIV_2 = 3, /**< RTCCLK / 2 */ - RTC_WAKEUP_CLOCK_1HZ = 4, /**< 1Hz */ - RTC_WAKEUP_CLOCK_1HZ_PULS = 6, /**< 1Hz and WUT + 65536 */ + RTC_WAKEUP_CLOCK_DIV_16 = 0U, /**< RTCCLK / 16 */ + RTC_WAKEUP_CLOCK_DIV_8 = 1U, /**< RTCCLK / 8 */ + RTC_WAKEUP_CLOCK_DIV_4 = 2U, /**< RTCCLK / 4 */ + RTC_WAKEUP_CLOCK_DIV_2 = 3U, /**< RTCCLK / 2 */ + RTC_WAKEUP_CLOCK_1HZ = 4U, /**< 1Hz */ + RTC_WAKEUP_CLOCK_1HZ_PULS = 6U, /**< 1Hz and WUT + 65536 */ } rtc_wakeup_clock_t; /** * @brief RTC clock output type */ typedef enum { - RTC_CLOCK_OUTPUT_32768 = 0, /**< 32768Hz */ - RTC_CLOCK_OUTPUT_1024 = 1, /**< 1024Hz */ - RTC_CLOCK_OUTPUT_32 = 2, /**< 32Hz */ - RTC_CLOCK_OUTPUT_1 = 3, /**< 1Hz */ - RTC_CLOCK_OUTPUT_CAL_1 = 4, /**< 1Hz after calibration */ - RTC_CLOCK_OUTPUT_EXA_1 = 5, /**< Exact 1Hz */ + RTC_CLOCK_OUTPUT_32768 = 0U, /**< 32768Hz */ + RTC_CLOCK_OUTPUT_1024 = 1U, /**< 1024Hz */ + RTC_CLOCK_OUTPUT_32 = 2U, /**< 32Hz */ + RTC_CLOCK_OUTPUT_1 = 3U, /**< 1Hz */ + RTC_CLOCK_OUTPUT_CAL_1 = 4U, /**< 1Hz after calibration */ + RTC_CLOCK_OUTPUT_EXA_1 = 5U, /**< Exact 1Hz */ } rtc_clock_output_t; /** * @ Calibration frequency */ typedef enum { - RTC_CALI_FREQ_10_SEC = 0, /**< Calibrate every 10 seconds */ - RTC_CALI_FREQ_20_SEC = 1, /**< Calibrate every 20 seconds */ - RTC_CALI_FREQ_1_MIN = 2, /**< Calibrate every 1 minute */ - RTC_CALI_FREQ_2_MIN = 3, /**< Calibrate every 2 minutes */ - RTC_CALI_FREQ_5_MIN = 4, /**< Calibrate every 5 minutes */ - RTC_CALI_FREQ_10_MIN = 5, /**< Calibrate every 10 minutes */ - RTC_CALI_FREQ_20_MIN = 6, /**< Calibrate every 20 minutes */ - RTC_CALI_FREQ_1_SEC = 7, /**< Calibrate every 1 second */ + RTC_CALI_FREQ_10_SEC = 0U, /**< Calibrate every 10 seconds */ + RTC_CALI_FREQ_20_SEC = 1U, /**< Calibrate every 20 seconds */ + RTC_CALI_FREQ_1_MIN = 2U, /**< Calibrate every 1 minute */ + RTC_CALI_FREQ_2_MIN = 3U, /**< Calibrate every 2 minutes */ + RTC_CALI_FREQ_5_MIN = 4U, /**< Calibrate every 5 minutes */ + RTC_CALI_FREQ_10_MIN = 5U, /**< Calibrate every 10 minutes */ + RTC_CALI_FREQ_20_MIN = 6U, /**< Calibrate every 20 minutes */ + RTC_CALI_FREQ_1_SEC = 7U, /**< Calibrate every 1 second */ } rtc_cali_freq_t; /** * @brief Temperature compensate type */ typedef enum { - RTC_CALI_TC_NONE = 0, /**< Temperature compensate disable */ - RTC_CALI_TC_AUTO_BY_HW = 1, /**< Temperature compensate by hardware */ - RTC_CALI_TC_AUTO_BY_SF = 2, /**< Temperature compensate by software */ - RTC_CALI_TC_AUTO_BY_HW_SF = 3, /**< Temperature compensate by hardware, trigger by software */ + RTC_CALI_TC_NONE = 0U, /**< Temperature compensate disable */ + RTC_CALI_TC_AUTO_BY_HW = 1U, /**< Temperature compensate by hardware */ + RTC_CALI_TC_AUTO_BY_SF = 2U, /**< Temperature compensate by software */ + RTC_CALI_TC_AUTO_BY_HW_SF = 3U, /**< Temperature compensate by hardware, trigger by software */ } rtc_cali_tc_t; /** * @ Calculate frequency */ typedef enum { - RTC_CALI_CALC_FREQ_10_SEC = 0, /**< Calculate every 10 seconds */ - RTC_CALI_CALC_FREQ_20_SEC = 1, /**< Calculate every 20 seconds */ - RTC_CALI_CALC_FREQ_1_MIN = 2, /**< Calculate every 1 minute */ - RTC_CALI_CALC_FREQ_2_MIN = 3, /**< Calculate every 2 minutes */ - RTC_CALI_CALC_FREQ_5_MIN = 4, /**< Calculate every 5 minutes */ - RTC_CALI_CALC_FREQ_10_MIN = 5, /**< Calculate every 10 minutes */ - RTC_CALI_CALC_FREQ_20_MIN = 6, /**< Calculate every 20 minutes */ - RTC_CALI_CALC_FREQ_1_HOUR = 7, /**< Calculate every 1 hour */ + RTC_CALI_CALC_FREQ_10_SEC = 0U, /**< Calculate every 10 seconds */ + RTC_CALI_CALC_FREQ_20_SEC = 1U, /**< Calculate every 20 seconds */ + RTC_CALI_CALC_FREQ_1_MIN = 2U, /**< Calculate every 1 minute */ + RTC_CALI_CALC_FREQ_2_MIN = 3U, /**< Calculate every 2 minutes */ + RTC_CALI_CALC_FREQ_5_MIN = 4U, /**< Calculate every 5 minutes */ + RTC_CALI_CALC_FREQ_10_MIN = 5U, /**< Calculate every 10 minutes */ + RTC_CALI_CALC_FREQ_20_MIN = 6U, /**< Calculate every 20 minutes */ + RTC_CALI_CALC_FREQ_1_HOUR = 7U, /**< Calculate every 1 hour */ } rtc_cali_calc_freq_t; /** * @brief Calibration algorithm */ typedef enum { - RTC_CALI_CALC_4 = 0, /**< 4-polynomial */ - RTC_CALI_CALC_2 = 1, /**< 2-parabola */ + RTC_CALI_CALC_4 = 0U, /**< 4-polynomial */ + RTC_CALI_CALC_2 = 1U, /**< 2-parabola */ } rtc_cali_calc_t; /** @@ -375,8 +375,8 @@ typedef enum { /** @defgroup RTC_Public_Macro RTC Public Macros * @{ */ -#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55)) -#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0)) +#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55U)) +#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0U)) #define RTC_BY_PASS_ENABLE() \ do { \ RTC_UNLOCK(); \ @@ -420,8 +420,8 @@ do { \ /** @defgroup CAN_Private_Macros CAN Private Macros * @{ */ -#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AA)) -#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0)) +#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AAU)) +#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0U)) #define ALARM_MASK_ALL 0x40808080 #define RTC_TIMEOUT_VALUE 100 diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h index 1756f25f36e9f6759d1ae97798160d41302bd304..55cbbfec47adbea175cb67e0a8376cc9555d4b86 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h @@ -39,8 +39,8 @@ extern "C" { * @brief Hardware calibration algorithm */ typedef enum { - RTC_CALI_MODE_NORMAL = 0, /**< Normal mode */ - RTC_CALI_MODE_SLEEP = 1, /**< Low power mode */ + RTC_CALI_MODE_NORMAL = 0U, /**< Normal mode */ + RTC_CALI_MODE_SLEEP = 1U, /**< Low power mode */ } rtc_hw_cali_mode_t; /** @@ -111,16 +111,16 @@ typedef struct { * @{ */ #ifndef RTC_LOCK -#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0)) -#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55)) +#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0U)) +#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55U)) #endif #ifndef TSENSE_LOCK -#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0)) -#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669)) +#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U)) +#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U)) #endif -#define RTCINFO ((RTCINFO_TypeDef *)0x81000) +#define RTCINFO ((RTCINFO_TypeDef *)0x81000U) /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h index c3084576fff08cb06eb4fb8c0396f07051d3ab08..63a4a01f563a35f99b08443c246af68546e73e7d 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h @@ -40,67 +40,67 @@ * @brief clock phase */ typedef enum { - SPI_CPHA_FIRST = 0, /**< Transiting data in the first edge */ - SPI_CPHA_SECOND = 1, /**< Transiting data in the seconde edge */ + SPI_CPHA_FIRST = 0U, /**< Transiting data in the first edge */ + SPI_CPHA_SECOND = 1U, /**< Transiting data in the seconde edge */ } spi_cpha_t; /** * @brief clock polarity */ typedef enum { - SPI_CPOL_LOW = 0, /**< Polarity hold low when spi-bus is idle */ - SPI_CPOL_HIGH = 1, /**< Polarity hold high when spi-bus is idle */ + SPI_CPOL_LOW = 0U, /**< Polarity hold low when spi-bus is idle */ + SPI_CPOL_HIGH = 1U, /**< Polarity hold high when spi-bus is idle */ } spi_cpol_t; /** * @brief master selection */ typedef enum { - SPI_MODE_SLAVER = 0, /**< Slave mode */ - SPI_MODE_MASTER = 1, /**< Master mode */ + SPI_MODE_SLAVER = 0U, /**< Slave mode */ + SPI_MODE_MASTER = 1U, /**< Master mode */ } spi_mode_t; /** * @brief baud rate control */ typedef enum { - SPI_BAUD_2 = 0, /**< fpclk/2 */ - SPI_BAUD_4 = 1, /**< fpclk/4 */ - SPI_BAUD_8 = 2, /**< fpclk/8 */ - SPI_BAUD_16 = 3, /**< fpclk/16 */ - SPI_BAUD_32 = 4, /**< fpclk/32 */ - SPI_BAUD_64 = 5, /**< fpclk/64 */ - SPI_BAUD_128 = 6, /**< fpclk/128 */ - SPI_BAUD_256 = 7, /**< fpclk/256 */ + SPI_BAUD_2 = 0U, /**< fpclk/2 */ + SPI_BAUD_4 = 1U, /**< fpclk/4 */ + SPI_BAUD_8 = 2U, /**< fpclk/8 */ + SPI_BAUD_16 = 3U, /**< fpclk/16 */ + SPI_BAUD_32 = 4U, /**< fpclk/32 */ + SPI_BAUD_64 = 5U, /**< fpclk/64 */ + SPI_BAUD_128 = 6U, /**< fpclk/128 */ + SPI_BAUD_256 = 7U, /**< fpclk/256 */ } spi_baud_t; /** * @brief frame format */ typedef enum { - SPI_FIRSTBIT_MSB = 0, /**< MSB transmitted first */ - SPI_FIRSTBIT_LSB = 1, /**< LSB transmitted first */ + SPI_FIRSTBIT_MSB = 0U, /**< MSB transmitted first */ + SPI_FIRSTBIT_LSB = 1U, /**< LSB transmitted first */ } spi_firstbit_t; /** * @brief data frame format */ typedef enum { - SPI_DATA_SIZE_8 = 0, /**< 8-bit data frame format is selected for transmission/reception */ - SPI_DATA_SIZE_16 = 1, /**< 16-bit data frame format is selected for transmission/reception */ + SPI_DATA_SIZE_8 = 0U, /**< 8-bit data frame format is selected for transmission/reception */ + SPI_DATA_SIZE_16 = 1U, /**< 16-bit data frame format is selected for transmission/reception */ } spi_datasize_t; /** * @brief SPI error status */ typedef enum { - SPI_ERROR_NONE = 0, /**< none */ - SPI_ERROR_MODF = 1, /**< mode fault */ - SPI_ERROR_CRC = 2, /**< crc error */ - SPI_ERROR_FRE = 4, /**< frame error */ - SPI_ERROR_RXOV = 8, /**< receive over error */ - SPI_ERROR_TXOV = 0x10, /**< dma error */ - SPI_ERROR_FLAG = 0x20, /**< interrupt flag error */ + SPI_ERROR_NONE = 0U, /**< none */ + SPI_ERROR_MODF = 1U, /**< mode fault */ + SPI_ERROR_CRC = 2U, /**< crc error */ + SPI_ERROR_FRE = 4U, /**< frame error */ + SPI_ERROR_RXOV = 8U, /**< receive over error */ + SPI_ERROR_TXOV = 0x10U, /**< dma error */ + SPI_ERROR_FLAG = 0x20U, /**< interrupt flag error */ } spi_error_t; /** @@ -141,14 +141,14 @@ typedef enum { * @brief SPI state structures definition */ typedef enum { - SPI_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - SPI_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - SPI_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - SPI_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */ - SPI_STATE_BUSY_RX = 0x21, /**< receive is ongoing */ - SPI_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */ - SPI_STATE_TIMEOUT = 0x03, /**< Timeout state */ - SPI_STATE_ERROR = 0x04, /**< Error */ + SPI_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + SPI_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + SPI_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + SPI_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */ + SPI_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */ + SPI_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */ + SPI_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + SPI_STATE_ERROR = 0x04U, /**< Error */ } spi_state_t; @@ -156,26 +156,26 @@ typedef enum { * @brief SPI direction definition */ typedef enum { - SPI_DIRECTION_2LINES = 0, /**< 2 lines */ - SPI_DIRECTION_2LINES_RXONLY = 1, /**< 2 lines only rx */ - SPI_DIRECTION_1LINE = 2, /**< 1 line */ - SPI_DIRECTION_1LINE_RX = 3, /**< 1 line only rx */ + SPI_DIRECTION_2LINES = 0U, /**< 2 lines */ + SPI_DIRECTION_2LINES_RXONLY = 1U, /**< 2 lines only rx */ + SPI_DIRECTION_1LINE = 2U, /**< 1 line */ + SPI_DIRECTION_1LINE_RX = 3U, /**< 1 line only rx */ } spi_direction_t; /** * @brief SPI dma request definition */ typedef enum { - SPI_DMA_REQ_TX = 0, /**< TX dma request */ - SPI_DMA_REQ_RX = 1, /**< RX dma request */ + SPI_DMA_REQ_TX = 0U, /**< TX dma request */ + SPI_DMA_REQ_RX = 1U, /**< RX dma request */ } spi_dma_req_t; /** * @brief SPI crc length definition */ typedef enum { - SPI_FRAME_MOTOROLA = 0, /**< SPI motorola mode */ - SPI_FRAME_TI = 1 /**< SPI TI mode */ + SPI_FRAME_MOTOROLA = 0U, /**< SPI motorola mode */ + SPI_FRAME_TI = 1U, /**< SPI TI mode */ } spi_frame_t; /** @@ -199,9 +199,9 @@ typedef enum { * @brief SPI TXE/RXNE status definition */ typedef enum { - SPI_SR_TXE = 0, /**< SR.TXE set */ - SPI_SR_RXNE = 1, /**< SR.RXTH set */ - SPI_SR_TXE_RXNE = 2, /**< SR.TXE and SR.RXNE set */ + SPI_SR_TXE = 0U, /**< SR.TXE set */ + SPI_SR_RXNE = 1U, /**< SR.RXTH set */ + SPI_SR_TXE_RXNE = 2U, /**< SR.TXE and SR.RXNE set */ } spi_sr_status_t; @@ -362,13 +362,24 @@ void ald_spi_reset(spi_handle_t *hperh); /** * @} */ - /** @addtogroup SPI_Public_Functions_Group2 * @{ */ int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data); int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data); uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh, int *status); +ald_status_t ald_spi_send_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_spi_master_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_spi_slave_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_spi_send_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_spi_master_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_spi_slave_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +/** + * @} + */ +/** @addtogroup SPI_Public_Functions_Group3 + * @{ + */ ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); @@ -386,8 +397,7 @@ ald_status_t ald_spi_dma_stop(spi_handle_t *hperh); /** * @} */ - -/** @addtogroup SPI_Public_Functions_Group3 +/** @addtogroup SPI_Public_Functions_Group4 * @{ */ void ald_spi_irq_handler(spi_handle_t *hperh); @@ -401,8 +411,7 @@ void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag); /** * @} */ - -/** @addtogroup SPI_Public_Functions_Group4 +/** @addtogroup SPI_Public_Functions_Group5 * @{ */ spi_state_t ald_spi_get_state(spi_handle_t *hperh); @@ -410,15 +419,12 @@ uint32_t ald_spi_get_error(spi_handle_t *hperh); /** * @} */ - /** * @} */ - /** * @} */ - /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h index 29890a9ae43df895ca3639232cb67723e656f640..c541c714edfb2a22ef1435a144ea8fbd15e73775 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h @@ -36,54 +36,36 @@ /** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros * @{ */ -#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0) -#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996) +#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0U) +#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996U) #define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK) -#define BOOT_FROM_BOOT_ROM() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) - -#define BOOT_FROM_BOOT_FLASH() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) - -#define BOOT_FROM_FLASH() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) +#define SYSCFG_BOOTFLASH_MAPPING_ENABLE() SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK) +#define SYSCFG_BOOTFLASH_MAPPING_DISABLE() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK) /** * @} */ - /** @defgroup SYSCFG_Public_Functions SYSCFG Public Functions * @{ */ +/** + * @brief Set the offset of the interrup vector map + * @param offset: Offset of the interrup vector map + * @param status: ENABLE/DISABLE + * @retval None + */ __STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status) { - SCB->VTOR = status ? (offset & ~0x3F) : 0; + SCB->VTOR = status ? (offset & ~0x3FU) : 0; return; } /** * @} */ - /** * @} */ - /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h index 650a33dcbeb14d78a1626d16c81050ab07c9e4b7..1805c3f95ada906fbaa81f818f5291dd87e9b310 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h @@ -41,93 +41,93 @@ * @brief TIMER counter mode */ typedef enum { - TIMER_CNT_MODE_UP = 0, /**< Counter mode up */ - TIMER_CNT_MODE_DOWN = 1, /**< Counter mode down */ - TIMER_CNT_MODE_CENTER1 = 2, /**< Counter mode center1 */ - TIMER_CNT_MODE_CENTER2 = 3, /**< Counter mode center2 */ - TIMER_CNT_MODE_CENTER3 = 4, /**< Counter mode center3 */ + TIMER_CNT_MODE_UP = 0U, /**< Counter mode up */ + TIMER_CNT_MODE_DOWN = 1U, /**< Counter mode down */ + TIMER_CNT_MODE_CENTER1 = 2U, /**< Counter mode center1 */ + TIMER_CNT_MODE_CENTER2 = 3U, /**< Counter mode center2 */ + TIMER_CNT_MODE_CENTER3 = 4U, /**< Counter mode center3 */ } timer_cnt_mode_t; /** * @brief TIMER clock division */ typedef enum { - TIMER_CLOCK_DIV1 = 0, /**< No prescaler is used */ - TIMER_CLOCK_DIV2 = 1, /** Clock is divided by 2 */ - TIMER_CLOCK_DIV4 = 2, /** Clock is divided by 4 */ + TIMER_CLOCK_DIV1 = 0U, /**< No prescaler is used */ + TIMER_CLOCK_DIV2 = 1U, /** Clock is divided by 2 */ + TIMER_CLOCK_DIV4 = 2U, /** Clock is divided by 4 */ } timer_clock_division_t; /** * @brief TIMER output compare and PWM modes */ typedef enum { - TIMER_OC_MODE_TIMERING = 0, /**< Output compare mode is timering */ - TIMER_OC_MODE_ACTIVE = 1, /**< Output compare mode is active */ - TIMER_OC_MODE_INACTIVE = 2, /**< Output compare mode is inactive */ - TIMER_OC_MODE_TOGGLE = 3, /**< Output compare mode is toggle */ - TIMER_OC_MODE_FORCE_INACTIVE = 4, /**< Output compare mode is force inactive */ - TIMER_OC_MODE_FORCE_ACTIVE = 5, /**< Output compare mode is force active */ - TIMER_OC_MODE_PWM1 = 6, /**< Output compare mode is pwm1 */ - TIMER_OC_MODE_PWM2 = 7, /**< Output compare mode is pwm2 */ + TIMER_OC_MODE_TIMERING = 0U, /**< Output compare mode is timering */ + TIMER_OC_MODE_ACTIVE = 1U, /**< Output compare mode is active */ + TIMER_OC_MODE_INACTIVE = 2U, /**< Output compare mode is inactive */ + TIMER_OC_MODE_TOGGLE = 3U, /**< Output compare mode is toggle */ + TIMER_OC_MODE_FORCE_INACTIVE = 4U, /**< Output compare mode is force inactive */ + TIMER_OC_MODE_FORCE_ACTIVE = 5U, /**< Output compare mode is force active */ + TIMER_OC_MODE_PWM1 = 6U, /**< Output compare mode is pwm1 */ + TIMER_OC_MODE_PWM2 = 7U, /**< Output compare mode is pwm2 */ } timer_oc_mode_t; /** * @brief TIMER output compare polarity */ typedef enum { - TIMER_OC_POLARITY_HIGH = 0, /**< Output compare polarity is high */ - TIMER_OC_POLARITY_LOW = 1, /**< Output compare polarity is low */ + TIMER_OC_POLARITY_HIGH = 0U, /**< Output compare polarity is high */ + TIMER_OC_POLARITY_LOW = 1U, /**< Output compare polarity is low */ } timer_oc_polarity_t; /** * @brief TIMER complementary output compare polarity */ typedef enum { - TIMER_OCN_POLARITY_HIGH = 0, /**< Complementary output compare polarity is high */ - TIMER_OCN_POLARITY_LOW = 1, /**< Complementary output compare polarity is low */ + TIMER_OCN_POLARITY_HIGH = 0U, /**< Complementary output compare polarity is high */ + TIMER_OCN_POLARITY_LOW = 1U, /**< Complementary output compare polarity is low */ } timer_ocn_polarity_t; /** * @brief TIMER output compare idle state */ typedef enum { - TIMER_OC_IDLE_RESET = 0, /**< Output compare idle state is reset */ - TIMER_OC_IDLE_SET = 1, /**< Output compare idle state is set */ + TIMER_OC_IDLE_RESET = 0U, /**< Output compare idle state is reset */ + TIMER_OC_IDLE_SET = 1U, /**< Output compare idle state is set */ } timer_oc_idle_t; /** * @brief TIMER complementary output compare idle state */ typedef enum { - TIMER_OCN_IDLE_RESET = 0, /**< Complementary output compare idle state is reset */ - TIMER_OCN_IDLE_SET = 1, /**< Complementary output compare idle state is set */ + TIMER_OCN_IDLE_RESET = 0U, /**< Complementary output compare idle state is reset */ + TIMER_OCN_IDLE_SET = 1U, /**< Complementary output compare idle state is set */ } timer_ocn_idle_t; /** * @brief TIMER channel */ typedef enum { - TIMER_CHANNEL_1 = 0, /**< Channel 1 */ - TIMER_CHANNEL_2 = 1, /**< Channel 2 */ - TIMER_CHANNEL_3 = 2, /**< Channel 3 */ - TIMER_CHANNEL_4 = 4, /**< Channel 4 */ - TIMER_CHANNEL_ALL = 0xF, /**< All channel */ + TIMER_CHANNEL_1 = 0U, /**< Channel 1 */ + TIMER_CHANNEL_2 = 1U, /**< Channel 2 */ + TIMER_CHANNEL_3 = 2U, /**< Channel 3 */ + TIMER_CHANNEL_4 = 3U, /**< Channel 4 */ + TIMER_CHANNEL_ALL = 0xFU, /**< All channel */ } timer_channel_t; /** * @brief TIMER one pulse mode */ typedef enum { - TIMER_OP_MODE_REPEAT = 0, /**< Repetitive */ - TIMER_OP_MODE_SINGLE = 1, /**< single */ + TIMER_OP_MODE_REPEAT = 0U, /**< Repetitive */ + TIMER_OP_MODE_SINGLE = 1U, /**< single */ } timer_op_mode_t; /** * @brief TIMER one pulse output channel */ typedef enum { - TIMER_OP_OUTPUT_CHANNEL_1 = 0, /**< One pulse output channal 1 */ - TIMER_OP_OUTPUT_CHANNEL_2 = 1, /**< One pulse output channal 2 */ + TIMER_OP_OUTPUT_CHANNEL_1 = 0U, /**< One pulse output channal 1 */ + TIMER_OP_OUTPUT_CHANNEL_2 = 1U, /**< One pulse output channal 2 */ } timer_op_output_channel_t; /** @@ -158,22 +158,22 @@ typedef struct { * @brief State structures definition */ typedef enum { - TIMER_STATE_RESET = 0x00, /**< Peripheral not yet initialized or disabled */ - TIMER_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - TIMER_STATE_BUSY = 0x02, /**< An internal process is ongoing */ - TIMER_STATE_TIMEREOUT = 0x03, /**< Timeout state */ - TIMER_STATE_ERROR = 0x04, /**< Reception process is ongoing */ + TIMER_STATE_RESET = 0x00U, /**< Peripheral not yet initialized or disabled */ + TIMER_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + TIMER_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ + TIMER_STATE_TIMEREOUT = 0x03U, /**< Timeout state */ + TIMER_STATE_ERROR = 0x04U, /**< Reception process is ongoing */ } timer_state_t; /** * @brief Active channel structures definition */ typedef enum { - TIMER_ACTIVE_CHANNEL_1 = 0x01, /**< The active channel is 1 */ - TIMER_ACTIVE_CHANNEL_2 = 0x02, /**< The active channel is 2 */ - TIMER_ACTIVE_CHANNEL_3 = 0x04, /**< The active channel is 3 */ - TIMER_ACTIVE_CHANNEL_4 = 0x08, /**< The active channel is 4 */ - TIMER_ACTIVE_CHANNEL_CLEARED = 0x00, /**< All active channels cleared */ + TIMER_ACTIVE_CHANNEL_1 = 0x01U, /**< The active channel is 1 */ + TIMER_ACTIVE_CHANNEL_2 = 0x02U, /**< The active channel is 2 */ + TIMER_ACTIVE_CHANNEL_3 = 0x04U, /**< The active channel is 3 */ + TIMER_ACTIVE_CHANNEL_4 = 0x08U, /**< The active channel is 4 */ + TIMER_ACTIVE_CHANNEL_CLEARED = 0x00U, /**< All active channels cleared */ } timer_active_channel_t; /** @@ -185,6 +185,11 @@ typedef struct timer_handle_s { timer_active_channel_t ch; /**< Active channel */ lock_state_t lock; /**< Locking object */ timer_state_t state; /**< TIMER operation state */ + +#ifdef ALD_DMA + dma_handle_t hdma1; /**< Timer DMA handle parameters */ + dma_handle_t hdma2; +#endif void (*period_elapse_cbk)(struct timer_handle_s *arg); /**< Period elapse callback */ void (*delay_elapse_cbk)(struct timer_handle_s *arg); /**< Delay_elapse callback */ @@ -201,36 +206,36 @@ typedef struct timer_handle_s { * @brief TIMER encoder mode */ typedef enum { - TIMER_ENC_MODE_TI1 = 1, /**< encoder mode 1 */ - TIMER_ENC_MODE_TI2 = 2, /**< encoder mode 2 */ - TIMER_ENC_MODE_TI12 = 3, /**< encoder mode 3 */ + TIMER_ENC_MODE_TI1 = 1U, /**< encoder mode 1 */ + TIMER_ENC_MODE_TI2 = 2U, /**< encoder mode 2 */ + TIMER_ENC_MODE_TI12 = 3U, /**< encoder mode 3 */ } timer_encoder_mode_t; /** * @brief TIMER input capture polarity */ typedef enum { - TIMER_IC_POLARITY_RISE = 0, /**< Input capture polarity rising */ - TIMER_IC_POLARITY_FALL = 1, /**< Input capture polarity falling */ + TIMER_IC_POLARITY_RISE = 0U, /**< Input capture polarity rising */ + TIMER_IC_POLARITY_FALL = 1U, /**< Input capture polarity falling */ } timer_ic_polarity_t; /** *@brief TIMER input capture selection */ typedef enum { - TIMER_IC_SEL_DIRECT = 1, /**< IC1 -- TI1 */ - TIMER_IC_SEL_INDIRECT = 2, /**< IC1 -- TI2 */ - TIMER_IC_SEL_TRC = 3, /**< IC1 -- TRC */ + TIMER_IC_SEL_DIRECT = 1U, /**< IC1 -- TI1 */ + TIMER_IC_SEL_INDIRECT = 2U, /**< IC1 -- TI2 */ + TIMER_IC_SEL_TRC = 3U, /**< IC1 -- TRC */ } timer_ic_select_t; /** * @brief TIMER input capture prescaler */ typedef enum { - TIMER_IC_PSC_DIV1 = 0, /**< Capture performed once every 1 events */ - TIMER_IC_PSC_DIV2 = 1, /**< Capture performed once every 2 events */ - TIMER_IC_PSC_DIV4 = 2, /**< Capture performed once every 4 events */ - TIMER_IC_PSC_DIV8 = 3, /**< Capture performed once every 4 events */ + TIMER_IC_PSC_DIV1 = 0U, /**< Capture performed once every 1 events */ + TIMER_IC_PSC_DIV2 = 1U, /**< Capture performed once every 2 events */ + TIMER_IC_PSC_DIV4 = 2U, /**< Capture performed once every 4 events */ + TIMER_IC_PSC_DIV8 = 3U, /**< Capture performed once every 4 events */ } timer_ic_prescaler_t; /** @@ -276,31 +281,31 @@ typedef struct { /** @brief TIMER clear input source */ typedef enum { - TIMER_INPUT_NONE = 0, /**< Clear input none */ - TIMER_INPUT_ETR = 1, /**< Clear input etr */ + TIMER_INPUT_NONE = 0U, /**< Clear input none */ + TIMER_INPUT_ETR = 1U, /**< Clear input etr */ } timer_clear_input_source_t; /** @brief TIMER clear input polarity */ typedef enum { - TIMER_POLARITY_NO_INV = 0, /**< Polarity for ETRx pin */ - TIMER_POLARITY_INV = 1, /**< Polarity for ETRx pin */ + TIMER_POLARITY_NO_INV = 0U, /**< Polarity for ETRx pin */ + TIMER_POLARITY_INV = 1U, /**< Polarity for ETRx pin */ } timer_clear_input_polarity_t; /** @brief TIMER clear input polarity */ typedef enum { - TIMER_ETR_PSC_DIV1 = 0, /**< No prescaler is used */ - TIMER_ETR_PSC_DIV2 = 1, /**< ETR input source is divided by 2 */ - TIMER_ETR_PSC_DIV4 = 2, /**< ETR input source is divided by 4 */ - TIMER_ETR_PSC_DIV8 = 3, /**< ETR input source is divided by 8 */ + TIMER_ETR_PSC_DIV1 = 0U, /**< No prescaler is used */ + TIMER_ETR_PSC_DIV2 = 1U, /**< ETR input source is divided by 2 */ + TIMER_ETR_PSC_DIV4 = 2U, /**< ETR input source is divided by 4 */ + TIMER_ETR_PSC_DIV8 = 3U, /**< ETR input source is divided by 8 */ } timer_etr_psc_t; /** @brief TIMER CHnREF Clear Select */ typedef enum { - TIMER_CHNREF_CLR_CMP_IN = 0, /**< Comparator CMP_IN */ - TIMER_CHNREF_CLR_ETF = 1, /**< External Trigger Signal ETF */ + TIMER_CHNREF_CLR_CMP_IN = 0U, /**< Comparator CMP_IN */ + TIMER_CHNREF_CLR_ETF = 1U, /**< External Trigger Signal ETF */ }timer_chnref_clr_sel_t;/** * @brief TIMER clear input configuration handle structure definition */ @@ -316,26 +321,26 @@ typedef struct { /** @brief TIMER clock source */ typedef enum { - TIMER_SRC_ETRMODE2 = 0, /**< Clock source is etr mode2 */ - TIMER_SRC_INTER = 1, /**< Clock source is etr internal */ - TIMER_SRC_ITR0 = 2, /**< Clock source is etr itr0 */ - TIMER_SRC_ITR1 = 3, /**< Clock source is etr itr1 */ - TIMER_SRC_ITR2 = 4, /**< Clock source is etr itr2 */ - TIMER_SRC_ITR3 = 5, /**< Clock source is etr itr3 */ - TIMER_SRC_TI1ED = 6, /**< Clock source is etr ti1ed */ - TIMER_SRC_TI1 = 7, /**< Clock source is etr ti1 */ - TIMER_SRC_TI2 = 8, /**< Clock source is etr ti2 */ - TIMER_SRC_ETRMODE1 = 9, /**< Clock source is etr mode1 */ + TIMER_SRC_ETRMODE2 = 0U, /**< Clock source is etr mode2 */ + TIMER_SRC_INTER = 1U, /**< Clock source is etr internal */ + TIMER_SRC_ITR0 = 2U, /**< Clock source is etr itr0 */ + TIMER_SRC_ITR1 = 3U, /**< Clock source is etr itr1 */ + TIMER_SRC_ITR2 = 4U, /**< Clock source is etr itr2 */ + TIMER_SRC_ITR3 = 5U, /**< Clock source is etr itr3 */ + TIMER_SRC_TI1ED = 6U, /**< Clock source is etr ti1ed */ + TIMER_SRC_TI1 = 7U, /**< Clock source is etr ti1 */ + TIMER_SRC_TI2 = 8U, /**< Clock source is etr ti2 */ + TIMER_SRC_ETRMODE1 = 9U, /**< Clock source is etr mode1 */ } timer_clock_source_t; /** @brief TIMER clock polarity */ typedef enum { - TIMER_CLK_POLARITY_INV = 1, /**< Polarity for ETRx clock sources */ - TIMER_CLK_POLARITY_NO_INV = 0, /**< Polarity for ETRx clock sources */ - TIMER_CLK_POLARITY_RISE = 0, /**< Polarity for TIx clock sources */ - TIMER_CLK_POLARITY_FALL = 1, /**< Polarity for TIx clock sources */ - TIMER_CLK_POLARITY_BOTH = 3, /**< Polarity for TIx clock sources */ + TIMER_CLK_POLARITY_INV = 1U, /**< Polarity for ETRx clock sources */ + TIMER_CLK_POLARITY_NO_INV = 0U, /**< Polarity for ETRx clock sources */ + TIMER_CLK_POLARITY_RISE = 0U, /**< Polarity for TIx clock sources */ + TIMER_CLK_POLARITY_FALL = 1U, /**< Polarity for TIx clock sources */ + TIMER_CLK_POLARITY_BOTH = 3U, /**< Polarity for TIx clock sources */ } timer_clock_polarity_t; /** @@ -352,28 +357,28 @@ typedef struct { * @brief TIMER slave mode */ typedef enum { - TIMER_MODE_DISABLE = 0, /**< Slave mode is disable */ - TIMER_MODE_ENC1 = 1, /**< Slave mode is encoder1 */ - TIMER_MODE_ENC2 = 2, /**< Slave mode is encoder2 */ - TIMER_MODE_ENC3 = 3, /**< Slave mode is encoder3 */ - TIMER_MODE_RESET = 4, /**< Slave mode is reset */ - TIMER_MODE_GATED = 5, /**< Slave mode is gated */ - TIMER_MODE_TRIG = 6, /**< Slave mode is trigger */ - TIMER_MODE_EXTERNAL1 = 7, /**< Slave mode is external1 */ + TIMER_MODE_DISABLE = 0U, /**< Slave mode is disable */ + TIMER_MODE_ENC1 = 1U, /**< Slave mode is encoder1 */ + TIMER_MODE_ENC2 = 2U, /**< Slave mode is encoder2 */ + TIMER_MODE_ENC3 = 3U, /**< Slave mode is encoder3 */ + TIMER_MODE_RESET = 4U, /**< Slave mode is reset */ + TIMER_MODE_GATED = 5U, /**< Slave mode is gated */ + TIMER_MODE_TRIG = 6U, /**< Slave mode is trigger */ + TIMER_MODE_EXTERNAL1 = 7U, /**< Slave mode is external1 */ } timer_slave_mode_t; /** * @brief TIMER ts definition */ typedef enum { - TIMER_TS_ITR0 = 0, /**< ITR0 */ - TIMER_TS_ITR1 = 1, /**< ITR1 */ - TIMER_TS_ITR2 = 2, /**< ITR2 */ - TIMER_TS_ITR3 = 3, /**< ITR3 */ - TIMER_TS_TI1F_ED = 4, /**< TI1F_ED */ - TIMER_TS_TI1FP1 = 5, /**< TI1FP1 */ - TIMER_TS_TI2FP2 = 6, /**< TI2FP2 */ - TIMER_TS_ETRF = 7, /**< ETRF */ + TIMER_TS_ITR0 = 0U, /**< ITR0 */ + TIMER_TS_ITR1 = 1U, /**< ITR1 */ + TIMER_TS_ITR2 = 2U, /**< ITR2 */ + TIMER_TS_ITR3 = 3U, /**< ITR3 */ + TIMER_TS_TI1F_ED = 4U, /**< TI1F_ED */ + TIMER_TS_TI1FP1 = 5U, /**< TI1FP1 */ + TIMER_TS_TI2FP2 = 6U, /**< TI2FP2 */ + TIMER_TS_ETRF = 7U, /**< ETRF */ } timer_ts_t; /** @@ -401,18 +406,18 @@ typedef struct { * @brief TIMER lock level */ typedef enum { - TIMER_LOCK_LEVEL_OFF = 0, /**< Lock off */ - TIMER_LOCK_LEVEL_1 = 1, /**< Lock level 1 */ - TIMER_LOCK_LEVEL_2 = 2, /**< Lock level 2 */ - TIMER_LOCK_LEVEL_3 = 3, /**< Lock level 3 */ + TIMER_LOCK_LEVEL_OFF = 0U, /**< Lock off */ + TIMER_LOCK_LEVEL_1 = 1U, /**< Lock level 1 */ + TIMER_LOCK_LEVEL_2 = 2U, /**< Lock level 2 */ + TIMER_LOCK_LEVEL_3 = 3U, /**< Lock level 3 */ } timer_lock_level_t; /** * @brief TIMER break polarity */ typedef enum { - TIMER_BREAK_POLARITY_LOW = 0, /**< LOW */ - TIMER_BREAK_POLARITY_HIGH = 1, /**< HIGH */ + TIMER_BREAK_POLARITY_LOW = 0U, /**< LOW */ + TIMER_BREAK_POLARITY_HIGH = 1U, /**< HIGH */ } timer_break_polarity_t; /** @@ -448,14 +453,14 @@ typedef struct { * @brief TIMER master mode selection */ typedef enum { - TIMER_TRGO_RESET = 0, /**< RESET */ - TIMER_TRGO_ENABLE = 1, /**< ENABLE */ - TIMER_TRGO_UPDATE = 2, /**< UPDATE */ - TIMER_TRGO_OC1 = 3, /**< OC1 */ - TIMER_TRGO_OC1REF = 4, /**< OC1REF */ - TIMER_TRGO_OC2REF = 5, /**< OC2REF */ - TIMER_TRGO_OC3REF = 6, /**< OC3REF */ - TIMER_TRGO_OC4REF = 7, /**< OC4REF */ + TIMER_TRGO_RESET = 0U, /**< RESET */ + TIMER_TRGO_ENABLE = 1U, /**< ENABLE */ + TIMER_TRGO_UPDATE = 2U, /**< UPDATE */ + TIMER_TRGO_OC1 = 3U, /**< OC1 */ + TIMER_TRGO_OC1REF = 4U, /**< OC1REF */ + TIMER_TRGO_OC2REF = 5U, /**< OC2REF */ + TIMER_TRGO_OC3REF = 6U, /**< OC3REF */ + TIMER_TRGO_OC4REF = 7U, /**< OC4REF */ } timer_master_mode_sel_t; /** @@ -996,7 +1001,7 @@ void ald_timer_base_stop(timer_handle_t *hperh); void ald_timer_base_start_by_it(timer_handle_t *hperh); void ald_timer_base_stop_by_it(timer_handle_t *hperh); #ifdef ALD_DMA -ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, +ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_base_stop_by_dma(timer_handle_t *hperh); #endif @@ -1015,7 +1020,7 @@ void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); + uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1036,7 +1041,7 @@ void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); + uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1054,7 +1059,7 @@ void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); + uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1078,15 +1083,15 @@ void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_chann * @{ */ /* Timer encoder functions */ -ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config); +ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config); void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, - uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2); + uint16_t *buf1, uint16_t *buf2, uint32_t len, + uint8_t dma_ch1, uint8_t dma_ch2); void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** @@ -1103,7 +1108,7 @@ void ald_timer_hall_sensor_stop(timer_handle_t *hperh); void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh); void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh); #ifdef ALD_DMA -ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, +ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh); #endif @@ -1120,7 +1125,7 @@ void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA -ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, +ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif @@ -1137,7 +1142,7 @@ void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA -ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, +ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h index a1d395f487103600c56ac0a13a72a2aa31488397..ff86dbbcbf781880e26511db073054a1416bce3f 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h @@ -39,20 +39,20 @@ extern "C" { * @brief Data width */ typedef enum { - TRNG_DSEL_1B = 0x0, /**< 1-bit */ - TRNG_DSEL_8B = 0x1, /**< 8-bits */ - TRNG_DSEL_16B = 0x2, /**< 16-bits */ - TRNG_DSEL_32B = 0x3, /**< 32-bits */ + TRNG_DSEL_1B = 0x0U, /**< 1-bit */ + TRNG_DSEL_8B = 0x1U, /**< 8-bits */ + TRNG_DSEL_16B = 0x2U, /**< 16-bits */ + TRNG_DSEL_32B = 0x3U, /**< 32-bits */ } trng_data_width_t; /** * @brief seed type */ typedef enum { - TRNG_SEED_TYPE_0 = 0x0, /**< Using 0 as seed */ - TRNG_SEED_TYPE_1 = 0x1, /**< Using 1 as seed */ - TRNG_SEED_TYPE_LAST = 0x2, /**< Using last seed */ - TRNG_SEED_TYPE_SEED = 0x3, /**< Using value of register */ + TRNG_SEED_TYPE_0 = 0x0U, /**< Using 0 as seed */ + TRNG_SEED_TYPE_1 = 0x1U, /**< Using 1 as seed */ + TRNG_SEED_TYPE_LAST = 0x2U, /**< Using last seed */ + TRNG_SEED_TYPE_SEED = 0x3U, /**< Using value of register */ } trng_seed_type_t; /** @@ -62,7 +62,7 @@ typedef struct { trng_data_width_t data_width; /**< The width of data */ trng_seed_type_t seed_type; /**< The seed type */ uint32_t seed; /**< The value of seed */ - uint16_t t_start; /**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */ + uint16_t t_start; /**< T(start) = T(trng) * 2 ^ (t_start + 1), T(start) > 1ms */ uint8_t adjc; /**< Adjust parameter */ type_func_t posten; /**< Data back handle function */ } trng_init_t; @@ -71,10 +71,10 @@ typedef struct { * @brief TRNG state structures definition */ typedef enum { - TRNG_STATE_RESET = 0x0, /**< Peripheral is not initialized */ - TRNG_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - TRNG_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - TRNG_STATE_ERROR = 0x4, /**< Error */ + TRNG_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ + TRNG_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + TRNG_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + TRNG_STATE_ERROR = 0x4U, /**< Error */ } trng_state_t; /** @@ -148,13 +148,14 @@ typedef struct trng_handle_s { #define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \ ((x) == TRNG_STATUS_DAVLD) || \ ((x) == TRNG_STATUS_SERR)) -#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \ - ((x) == TRNG_IT_DAVLD) || \ - ((x) == TRNG_IT_SERR)) -#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \ - ((x) == TRNG_IF_DAVLD) || \ - ((x) == TRNG_IF_SERR)) -#define IS_TRNG_ADJC(x) ((x) < 4) +#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \ + ((x) == TRNG_IT_DAVLD) || \ + ((x) == TRNG_IT_SERR)) +#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \ + ((x) == TRNG_IF_DAVLD) || \ + ((x) == TRNG_IF_SERR)) +#define IS_TRNG_ADJC(x) ((x) < 4) +#define IS_TRNG_T_START(x) ((x) < 8) /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h index 775098e1c505edeb73c9d363f66a157b5f3f0528..6aff4435b1d092aea38f2b97d76abb9edfe7305a 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h @@ -35,8 +35,8 @@ extern "C" { /** @defgroup TSENSE_Public_Macros TSENSE Public Macros * @{ */ -#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0)) -#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669)) +#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U)) +#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U)) #define TSENSE_ENABLE() \ do { \ TSENSE_UNLOCK(); \ @@ -114,30 +114,30 @@ do { \ * @brief Temperature update time */ typedef enum { - TSENSE_UPDATE_CYCLE_3 = 0x3, /**< 3 Cycles */ - TSENSE_UPDATE_CYCLE_4 = 0x4, /**< 4 Cycles */ - TSENSE_UPDATE_CYCLE_5 = 0x5, /**< 5 Cycles */ - TSENSE_UPDATE_CYCLE_6 = 0x6, /**< 6 Cycles */ - TSENSE_UPDATE_CYCLE_7 = 0x7, /**< 7 Cycles */ + TSENSE_UPDATE_CYCLE_3 = 0x3U, /**< 3 Cycles */ + TSENSE_UPDATE_CYCLE_4 = 0x4U, /**< 4 Cycles */ + TSENSE_UPDATE_CYCLE_5 = 0x5U, /**< 5 Cycles */ + TSENSE_UPDATE_CYCLE_6 = 0x6U, /**< 6 Cycles */ + TSENSE_UPDATE_CYCLE_7 = 0x7U, /**< 7 Cycles */ } tsense_update_cycle_t; /** * @brief Temperature output mode */ typedef enum { - TSENSE_OUTPUT_MODE_200 = 0x0, /**< 200 cycles update one temperature */ - TSENSE_OUTPUT_MODE_400 = 0x1, /**< 400 cycles update one temperature */ - TSENSE_OUTPUT_MODE_800 = 0x2, /**< 800 cycles update one temperature */ - TSENSE_OUTPUT_MODE_1600 = 0x3, /**< 1600 cycles update one temperature */ - TSENSE_OUTPUT_MODE_3200 = 0x4, /**< 3200 cycles update one temperature */ + TSENSE_OUTPUT_MODE_200 = 0x0U, /**< 200 cycles update one temperature */ + TSENSE_OUTPUT_MODE_400 = 0x1U, /**< 400 cycles update one temperature */ + TSENSE_OUTPUT_MODE_800 = 0x2U, /**< 800 cycles update one temperature */ + TSENSE_OUTPUT_MODE_1600 = 0x3U, /**< 1600 cycles update one temperature */ + TSENSE_OUTPUT_MODE_3200 = 0x4U, /**< 3200 cycles update one temperature */ } tsense_output_mode_t; /** * @brief Source select */ typedef enum { - TSENSE_SOURCE_LOSC = 0x0, /**< LOSC */ - TSENSE_SOURCE_LRC = 0x1, /**< LRC */ + TSENSE_SOURCE_LOSC = 0x0U, /**< LOSC */ + TSENSE_SOURCE_LRC = 0x1U, /**< LRC */ } tsense_source_sel_t; diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h index 636a126d60a11cc3991c13f6cc4ca9bb08bdaeef..a525f59783d100654f21f9d3c86917e58ca104f7 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h @@ -41,8 +41,8 @@ extern "C" { #define UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK)) #define UART_TX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK)) #define UART_TX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK)) -#define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RTOEN_MSK)) -#define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RTOEN_MSK)) +#define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK)) +#define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK)) #define UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK)) #define UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK)) #define UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK)) @@ -57,8 +57,8 @@ extern "C" { #define UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK)) #define UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCON, UART_FCON_TFRST_MSK)) #define UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCON, UART_FCON_RFRST_MSK)) -#define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_LBEN_MSK)) -#define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_LBEN_MSK)) +#define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK)) +#define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK)) #define UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK)) #define UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK)) #define UART_AUTOBR_REPT(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABRREPT_MSK)) @@ -81,75 +81,75 @@ extern "C" { * @brief UART word length */ typedef enum { - UART_WORD_LENGTH_8B = 0x0, /**< 8-bits */ - UART_WORD_LENGTH_7B = 0x1, /**< 7-bits */ - UART_WORD_LENGTH_6B = 0x2, /**< 6-bits */ - UART_WORD_LENGTH_5B = 0x3, /**< 5-bits */ + UART_WORD_LENGTH_8B = 0x0U, /**< 8-bits */ + UART_WORD_LENGTH_7B = 0x1U, /**< 7-bits */ + UART_WORD_LENGTH_6B = 0x2U, /**< 6-bits */ + UART_WORD_LENGTH_5B = 0x3U, /**< 5-bits */ } uart_word_length_t; /** * @brief UART stop bits */ typedef enum { - UART_STOP_BITS_1 = 0x0, /**< 1-bits */ - UART_STOP_BITS_2 = 0x1, /**< 2-bits */ - UART_STOP_BITS_0_5 = 0x0, /**< 0.5-bits, using smartcard mode */ - UART_STOP_BITS_1_5 = 0x1, /**< 1.5-bits, using smartcard mode */ + UART_STOP_BITS_1 = 0x0U, /**< 1-bits */ + UART_STOP_BITS_2 = 0x1U, /**< 2-bits */ + UART_STOP_BITS_0_5 = 0x0U, /**< 0.5-bits, using smartcard mode */ + UART_STOP_BITS_1_5 = 0x1U, /**< 1.5-bits, using smartcard mode */ } uart_stop_bits_t; /** * @brief UART parity */ typedef enum { - UART_PARITY_NONE = 0x0, /**< Not parity */ - UART_PARITY_ODD = 0x1, /**< Odd parity */ - UART_PARITY_EVEN = 0x3, /**< Even parity */ + UART_PARITY_NONE = 0x0U, /**< Not parity */ + UART_PARITY_ODD = 0x1U, /**< Odd parity */ + UART_PARITY_EVEN = 0x3U, /**< Even parity */ } uart_parity_t; /** * @brief UART mode */ typedef enum { - UART_MODE_UART = 0x0, /**< UART */ - UART_MODE_LIN = 0x1, /**< LIN */ - UART_MODE_IrDA = 0x2, /**< IrDA */ - UART_MODE_RS485 = 0x3, /**< RS485 */ - UART_MODE_HDSEL = 0x4, /**< Single-wire half-duplex */ - UART_MODE_SCARD = 0x5, /**< Smart card */ + UART_MODE_UART = 0x0U, /**< UART */ + UART_MODE_LIN = 0x1U, /**< LIN */ + UART_MODE_IrDA = 0x2U, /**< IrDA */ + UART_MODE_RS485 = 0x3U, /**< RS485 */ + UART_MODE_HDSEL = 0x4U, /**< Single-wire half-duplex */ + UART_MODE_SCARD = 0x5U, /**< Smart card */ } uart_mode_t; /** * @brief UART hardware flow control */ typedef enum { - UART_HW_FLOW_CTL_DISABLE = 0x0, /**< Auto-flow-control disable */ - UART_HW_FLOW_CTL_ENABLE = 0x1, /**< Auto-flow-control enable */ + UART_HW_FLOW_CTL_DISABLE = 0x0U, /**< Auto-flow-control disable */ + UART_HW_FLOW_CTL_ENABLE = 0x1U, /**< Auto-flow-control enable */ } uart_hw_flow_ctl_t; /** * @brief ALD UART state */ typedef enum { - UART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - UART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - UART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - UART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - UART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ - UART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ - UART_STATE_TIMEOUT = 0x03, /**< Timeout state */ - UART_STATE_ERROR = 0x04, /**< Error */ + UART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + UART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + UART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + UART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ + UART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ + UART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */ + UART_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + UART_STATE_ERROR = 0x04U, /**< Error */ } uart_state_t; /** * @brief UART error codes */ typedef enum { - UART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ - UART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ - UART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ - UART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ - UART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ - UART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ + UART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ + UART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ + UART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ + UART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ + UART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ + UART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ } uart_error_t; /** @@ -203,24 +203,24 @@ typedef struct { * @brief Smart_card clock division */ typedef enum { - SCARD_CLOCK_DIV1 = 0x0, /**< No prescaler is used */ - SCARD_CLOCK_DIV2 = 0x1, /** Clock is divided by 2 */ - SCARD_CLOCK_DIV4 = 0x2, /** Clock is divided by 4 */ - SCARD_CLOCK_DIV6 = 0x3, /** Clock is divided by 6 */ + SCARD_CLOCK_DIV1 = 0x0U, /**< No prescaler is used */ + SCARD_CLOCK_DIV2 = 0x1U, /** Clock is divided by 2 */ + SCARD_CLOCK_DIV4 = 0x2U, /** Clock is divided by 4 */ + SCARD_CLOCK_DIV6 = 0x3U, /** Clock is divided by 6 */ } scard_clk_div_t; /** * @brief Smart_card Rx/Tx handle retry time */ typedef enum { - SCARD_RETRY_CNT0 = 0x0, /**< retry time 0 */ - SCARD_RETRY_CNT1 = 0x1, /**< retry time 1 */ - SCARD_RETRY_CNT2 = 0x2, /**< retry time 2 */ - SCARD_RETRY_CNT3 = 0x3, /**< retry time 3 */ - SCARD_RETRY_CNT4 = 0x4, /**< retry time 4 */ - SCARD_RETRY_CNT5 = 0x5, /**< retry time 5 */ - SCARD_RETRY_CNT6 = 0x6, /**< retry time 6 */ - SCARD_RETRY_CNT7 = 0x7 /**< retry time 7 */ + SCARD_RETRY_CNT0 = 0x0U, /**< retry time 0 */ + SCARD_RETRY_CNT1 = 0x1U, /**< retry time 1 */ + SCARD_RETRY_CNT2 = 0x2U, /**< retry time 2 */ + SCARD_RETRY_CNT3 = 0x3U, /**< retry time 3 */ + SCARD_RETRY_CNT4 = 0x4U, /**< retry time 4 */ + SCARD_RETRY_CNT5 = 0x5U, /**< retry time 5 */ + SCARD_RETRY_CNT6 = 0x6U, /**< retry time 6 */ + SCARD_RETRY_CNT7 = 0x7U, /**< retry time 7 */ } scard_retry_t; /** @@ -238,45 +238,45 @@ typedef struct { * @brief LIN detection break length */ typedef enum { - LIN_BREAK_LEN_10B = 0x0, /**< 10-bit break */ - LIN_BREAK_LEN_11B = 0x1, /**< 11-bit break */ + LIN_BREAK_LEN_10B = 0x0U, /**< 10-bit break */ + LIN_BREAK_LEN_11B = 0x1U, /**< 11-bit break */ } uart_lin_break_len_t; /** * @brief UART TXFIFO size */ typedef enum { - UART_TXFIFO_EMPTY = 0x0, /**< Empty */ - UART_TXFIFO_2BYTE = 0x1, /**< 2-Bytes */ - UART_TXFIFO_4BYTE = 0x2, /**< 4-Bytes */ - UART_TXFIFO_8BYTE = 0x3, /**< 8-Bytes */ + UART_TXFIFO_EMPTY = 0x0U, /**< Empty */ + UART_TXFIFO_2BYTE = 0x1U, /**< 2-Bytes */ + UART_TXFIFO_4BYTE = 0x2U, /**< 4-Bytes */ + UART_TXFIFO_8BYTE = 0x3U, /**< 8-Bytes */ } uart_txfifo_t; /** * @brief UART RXFIFO size */ typedef enum { - UART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */ - UART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */ - UART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */ - UART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */ + UART_RXFIFO_1BYTE = 0x0U, /**< 1-Byte */ + UART_RXFIFO_4BYTE = 0x1U, /**< 4-Bytes */ + UART_RXFIFO_8BYTE = 0x2U, /**< 8-Bytes */ + UART_RXFIFO_14BYTE = 0x3U, /**< 14-Bytes */ } uart_rxfifo_t; /** * @brief UART auto-baud mode */ typedef enum { - UART_ABRMOD_1_TO_0 = 0x0, /**< Detect bit0:1, bit1:0 */ - UART_ABRMOD_1 = 0x1, /**< Detect bit0:1 */ - UART_ABRMOD_0_TO_1 = 0x2, /**< Detect bit0:0, bit1:1 */ + UART_ABRMOD_1_TO_0 = 0x0U, /**< Detect bit0:1, bit1:0 */ + UART_ABRMOD_1 = 0x1U, /**< Detect bit0:1 */ + UART_ABRMOD_0_TO_1 = 0x2U, /**< Detect bit0:0, bit1:1 */ } uart_auto_baud_mode_t; /** * @brief UART DMA Requests */ typedef enum { - UART_DMA_REQ_TX = 0x0, /**< TX dma */ - UART_DMA_REQ_RX = 0x1, /**< RX dma */ + UART_DMA_REQ_TX = 0x0U, /**< TX dma */ + UART_DMA_REQ_RX = 0x1U, /**< RX dma */ } uart_dma_req_t; /** @@ -317,7 +317,7 @@ typedef enum { UART_IT_RFFULL = (1U << 11), /**< Receive FIFO full */ UART_IT_RFOERR = (1U << 12), /**< Receive FIFO overrun */ UART_IT_RFUERR = (1U << 13), /**< Reveive FIFO underrun */ - UART_IT_TSEMPTY = (1U << 14), /**< Transmit shift register empty */ + UART_IT_TBC = (1U << 14), /**< Transmit shift register empty */ UART_IT_TFTH = (1U << 15), /**< Transmit FIFO trigger threshold */ UART_IT_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ UART_IT_TFOVER = (1U << 18), /**< Transmit FIFO overrun */ @@ -423,7 +423,7 @@ typedef enum { ((x) == UART_IT_RFFULL) || \ ((x) == UART_IT_RFOERR) || \ ((x) == UART_IT_RFUERR) || \ - ((x) == UART_IT_TSEMPTY) || \ + ((x) == UART_IT_TBC) || \ ((x) == UART_IT_TFTH) || \ ((x) == UART_IT_TFEMPTY) || \ ((x) == UART_IT_TFOVER)) @@ -483,7 +483,7 @@ ald_status_t ald_uart_send_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t s ald_status_t ald_uart_recv_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t ald_uart_recv_frame_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t t_out); +ald_status_t ald_uart_recv_frame_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out); #ifdef ALD_DMA ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); @@ -492,6 +492,7 @@ ald_status_t ald_uart_dma_resume(uart_handle_t *hperh); ald_status_t ald_uart_dma_stop(uart_handle_t *hperh); #endif void ald_uart_irq_handler(uart_handle_t *hperh); +void ald_uart_irq_handler_fast(uart_handle_t *hperh); /** * @} */ @@ -502,8 +503,8 @@ void ald_uart_irq_handler(uart_handle_t *hperh); /* Peripheral Control functions */ void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state); void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state); -void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config, uint8_t level); -void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); +void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config); +void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config); void uart_lin_break_detect_irq(uart_handle_t *hperh, type_func_t status); void ald_uart_lin_send_break(uart_handle_t *hperh); void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len); diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h index 436eba700e104dfc7b79ab153ca5eb5b785b73ff..38c991a7570ea1d680ae02122bfd270d93b8a17b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h @@ -38,398 +38,398 @@ extern "C" { * @{ */ -#define USB_POWER_ISOUP 0x00000080 -#define USB_POWER_SOFTCONN 0x00000040 -#define USB_POWER_HS_EN 0x00000020 -#define USB_POWER_HS_M 0x00000010 -#define USB_POWER_RESET 0x00000008 -#define USB_POWER_RESUME 0x00000004 -#define USB_POWER_SUSPEND 0x00000002 -#define USB_POWER_PWRDNPHY 0x00000001 - -#define USB_DEVCTL_DEV 0x00000080 -#define USB_DEVCTL_FSDEV 0x00000040 -#define USB_DEVCTL_LSDEV 0x00000020 -#define USB_DEVCTL_VBUS_M 0x00000018 -#define USB_DEVCTL_VBUS_NONE 0x00000000 -#define USB_DEVCTL_VBUS_SEND 0x00000008 -#define USB_DEVCTL_VBUS_AVALID 0x00000010 -#define USB_DEVCTL_VBUS_VALID 0x00000018 -#define USB_DEVCTL_HOST 0x00000004 -#define USB_DEVCTL_HOSTREQ 0x00000002 -#define USB_DEVCTL_SESSION 0x00000001 - -#define USB_RXCSRH1_AUTOCL 0x00000080 -#define USB_RXCSRH1_AUTORQ 0x00000040 -#define USB_RXCSRH1_ISO 0x00000040 -#define USB_RXCSRH1_DMAEN 0x00000020 -#define USB_RXCSRH1_DISNYET 0x00000010 -#define USB_RXCSRH1_PIDERR 0x00000010 -#define USB_RXCSRH1_DMAMOD 0x00000008 -#define USB_RXCSRH1_DTWE 0x00000004 -#define USB_RXCSRH1_DT 0x00000002 -#define USB_RXCSRH1_INCOMPRX 0x00000001 - -#define USB_CSRH0_DISPING 0x00000008 -#define USB_CSRH0_DTWE 0x00000004 -#define USB_CSRH0_DT 0x00000002 -#define USB_CSRH0_FLUSH 0x00000001 - -#define USB_TXCSRH1_AUTOSET 0x00000080 -#define USB_TXCSRH1_ISO 0x00000040 -#define USB_TXCSRH1_MODE 0x00000020 -#define USB_TXCSRH1_DMAEN 0x00000010 -#define USB_TXCSRH1_FDT 0x00000008 -#define USB_TXCSRH1_DMAMOD 0x00000004 -#define USB_TXCSRH1_DTWE 0x00000002 -#define USB_TXCSRH1_DT 0x00000001 - -#define USB_TXCSRL1_NAKTO 0x00000080 -#define USB_TXCSRL1_CLRDT 0x00000040 -#define USB_TXCSRL1_STALLED 0x00000020 -#define USB_TXCSRL1_STALL 0x00000010 -#define USB_TXCSRL1_SETUP 0x00000010 -#define USB_TXCSRL1_FLUSH 0x00000008 -#define USB_TXCSRL1_ERROR 0x00000004 -#define USB_TXCSRL1_UNDRN 0x00000004 -#define USB_TXCSRL1_FIFONE 0x00000002 -#define USB_TXCSRL1_TXRDY 0x00000001 - -#define USB_RXCSRL1_CLRDT 0x00000080 -#define USB_RXCSRL1_STALLED 0x00000040 -#define USB_RXCSRL1_STALL 0x00000020 -#define USB_RXCSRL1_REQPKT 0x00000020 -#define USB_RXCSRL1_FLUSH 0x00000010 -#define USB_RXCSRL1_DATAERR 0x00000008 -#define USB_RXCSRL1_NAKTO 0x00000008 -#define USB_RXCSRL1_OVER 0x00000004 -#define USB_RXCSRL1_ERROR 0x00000004 -#define USB_RXCSRL1_FULL 0x00000002 -#define USB_RXCSRL1_RXRDY 0x00000001 - -#define USB_CSRL0_NAKTO 0x00000080 -#define USB_CSRL0_SETENDC 0x00000080 -#define USB_CSRL0_STATUS 0x00000040 -#define USB_CSRL0_RXRDYC 0x00000040 -#define USB_CSRL0_REQPKT 0x00000020 -#define USB_CSRL0_STALL 0x00000020 -#define USB_CSRL0_SETEND 0x00000010 -#define USB_CSRL0_ERROR 0x00000010 -#define USB_CSRL0_DATAEND 0x00000008 -#define USB_CSRL0_SETUP 0x00000008 -#define USB_CSRL0_STALLED 0x00000004 -#define USB_CSRL0_TXRDY 0x00000002 -#define USB_CSRL0_RXRDY 0x00000001 - -#define USB_TYPE0_SPEED_M 0x000000C0 -#define USB_TYPE0_SPEED_HIGH 0x00000040 -#define USB_TYPE0_SPEED_FULL 0x00000080 -#define USB_TYPE0_SPEED_LOW 0x000000C0 - -#define USB_TXTYPE1_SPEED_M 0x000000C0 -#define USB_TXTYPE1_SPEED_DFLT 0x00000000 -#define USB_TXTYPE1_SPEED_HIGH 0x00000040 -#define USB_TXTYPE1_SPEED_FULL 0x00000080 -#define USB_TXTYPE1_SPEED_LOW 0x000000C0 -#define USB_TXTYPE1_PROTO_M 0x00000030 -#define USB_TXTYPE1_PROTO_CTRL 0x00000000 -#define USB_TXTYPE1_PROTO_ISOC 0x00000010 -#define USB_TXTYPE1_PROTO_BULK 0x00000020 -#define USB_TXTYPE1_PROTO_INT 0x00000030 -#define USB_TXTYPE1_TEP_M 0x0000000F -#define USB_TXTYPE1_TEP_S 0 - -#define USB_LPMATTR_ENDPT_M 0x0000F000 -#define USB_LPMATTR_RMTWAK 0x00000100 -#define USB_LPMATTR_HIRD_M 0x000000F0 -#define USB_LPMATTR_LS_M 0x0000000F -#define USB_LPMATTR_LS_L1 0x00000001 -#define USB_LPMATTR_ENDPT_S 12 -#define USB_LPMATTR_HIRD_S 4 - -#define USB_LPMCNTRL_LPMRES 0x00000002 -#define USB_LPMCNTRL_LPMXMT 0x00000001 -#define USB_LPMCNTRL_ENABLE 0x00000006 -#define USB_LPMCNTRL_DISABLE 0x00000000 - -#define USB_INTCTRL_ALL 0x000003FF -#define USB_INTCTRL_STATUS 0x000000FF -#define USB_INTCTRL_VBUS_ERR 0x00000080 -#define USB_INTCTRL_SESSION 0x00000040 -#define USB_INTCTRL_SESSION_END 0x00000040 -#define USB_INTCTRL_DISCONNECT 0x00000020 -#define USB_INTCTRL_CONNECT 0x00000010 -#define USB_INTCTRL_SOF 0x00000008 -#define USB_INTCTRL_BABBLE 0x00000004 -#define USB_INTCTRL_RESET 0x00000004 -#define USB_INTCTRL_RESUME 0x00000002 -#define USB_INTCTRL_SUSPEND 0x00000001 -#define USB_INTCTRL_MODE_DETECT 0x00000200 -#define USB_INTCTRL_POWER_FAULT 0x00000100 - -#define USB_INTEP_ALL 0xFFFFFFFF -#define USB_INTEP_HOST_IN 0xFFFE0000 -#define USB_INTEP_HOST_IN_15 0x80000000 -#define USB_INTEP_HOST_IN_14 0x40000000 -#define USB_INTEP_HOST_IN_13 0x20000000 -#define USB_INTEP_HOST_IN_12 0x10000000 -#define USB_INTEP_HOST_IN_11 0x08000000 -#define USB_INTEP_HOST_IN_10 0x04000000 -#define USB_INTEP_HOST_IN_9 0x02000000 -#define USB_INTEP_HOST_IN_8 0x01000000 -#define USB_INTEP_HOST_IN_7 0x00800000 -#define USB_INTEP_HOST_IN_6 0x00400000 -#define USB_INTEP_HOST_IN_5 0x00200000 -#define USB_INTEP_HOST_IN_4 0x00100000 -#define USB_INTEP_HOST_IN_3 0x00080000 -#define USB_INTEP_HOST_IN_2 0x00040000 -#define USB_INTEP_HOST_IN_1 0x00020000 - -#define USB_INTEP_DEV_OUT 0xFFFE0000 -#define USB_INTEP_DEV_OUT_15 0x80000000 -#define USB_INTEP_DEV_OUT_14 0x40000000 -#define USB_INTEP_DEV_OUT_13 0x20000000 -#define USB_INTEP_DEV_OUT_12 0x10000000 -#define USB_INTEP_DEV_OUT_11 0x08000000 -#define USB_INTEP_DEV_OUT_10 0x04000000 -#define USB_INTEP_DEV_OUT_9 0x02000000 -#define USB_INTEP_DEV_OUT_8 0x01000000 -#define USB_INTEP_DEV_OUT_7 0x00800000 -#define USB_INTEP_DEV_OUT_6 0x00400000 -#define USB_INTEP_DEV_OUT_5 0x00200000 -#define USB_INTEP_DEV_OUT_4 0x00100000 -#define USB_INTEP_DEV_OUT_3 0x00080000 -#define USB_INTEP_DEV_OUT_2 0x00040000 -#define USB_INTEP_DEV_OUT_1 0x00020000 - -#define USB_INTEP_HOST_OUT 0x0000FFFE -#define USB_INTEP_HOST_OUT_15 0x00008000 -#define USB_INTEP_HOST_OUT_14 0x00004000 -#define USB_INTEP_HOST_OUT_13 0x00002000 -#define USB_INTEP_HOST_OUT_12 0x00001000 -#define USB_INTEP_HOST_OUT_11 0x00000800 -#define USB_INTEP_HOST_OUT_10 0x00000400 -#define USB_INTEP_HOST_OUT_9 0x00000200 -#define USB_INTEP_HOST_OUT_8 0x00000100 -#define USB_INTEP_HOST_OUT_7 0x00000080 -#define USB_INTEP_HOST_OUT_6 0x00000040 -#define USB_INTEP_HOST_OUT_5 0x00000020 -#define USB_INTEP_HOST_OUT_4 0x00000010 -#define USB_INTEP_HOST_OUT_3 0x00000008 -#define USB_INTEP_HOST_OUT_2 0x00000004 -#define USB_INTEP_HOST_OUT_1 0x00000002 - -#define USB_INTEP_DEV_IN 0x0000FFFE -#define USB_INTEP_DEV_IN_15 0x00008000 -#define USB_INTEP_DEV_IN_14 0x00004000 -#define USB_INTEP_DEV_IN_13 0x00002000 -#define USB_INTEP_DEV_IN_12 0x00001000 -#define USB_INTEP_DEV_IN_11 0x00000800 -#define USB_INTEP_DEV_IN_10 0x00000400 -#define USB_INTEP_DEV_IN_9 0x00000200 -#define USB_INTEP_DEV_IN_8 0x00000100 -#define USB_INTEP_DEV_IN_7 0x00000080 -#define USB_INTEP_DEV_IN_6 0x00000040 -#define USB_INTEP_DEV_IN_5 0x00000020 -#define USB_INTEP_DEV_IN_4 0x00000010 -#define USB_INTEP_DEV_IN_3 0x00000008 -#define USB_INTEP_DEV_IN_2 0x00000004 -#define USB_INTEP_DEV_IN_1 0x00000002 - -#define USB_INTEP_0 0x00000001 - -#define USB_UNDEF_SPEED 0x80000000 -#define USB_HIGH_SPEED 0x00000002 -#define USB_FULL_SPEED 0x00000001 -#define USB_LOW_SPEED 0x00000000 - -#define USB_HOST_IN_STATUS 0x114F0000 -#define USB_HOST_IN_PID_ERROR 0x10000000 -#define USB_HOST_IN_NOT_COMP 0x01000000 -#define USB_HOST_IN_STALL 0x00400000 -#define USB_HOST_IN_DATA_ERROR 0x00080000 - -#define USB_HOST_IN_NAK_TO 0x00080000 - -#define USB_HOST_IN_ERROR 0x00040000 - -#define USB_HOST_IN_FIFO_FULL 0x00020000 -#define USB_HOST_IN_PKTRDY 0x00010000 -#define USB_HOST_OUT_STATUS 0x000000A7 -#define USB_HOST_OUT_NAK_TO 0x00000080 - -#define USB_HOST_OUT_NOT_COMP 0x00000080 - -#define USB_HOST_OUT_STALL 0x00000020 -#define USB_HOST_OUT_ERROR 0x00000004 - -#define USB_HOST_OUT_FIFO_NE 0x00000002 -#define USB_HOST_OUT_PKTPEND 0x00000001 -#define USB_HOST_EP0_NAK_TO 0x00000080 - -#define USB_HOST_EP0_STATUS 0x00000040 -#define USB_HOST_EP0_ERROR 0x00000010 - -#define USB_HOST_EP0_RX_STALL 0x00000004 -#define USB_HOST_EP0_RXPKTRDY 0x00000001 -#define USB_DEV_RX_PID_ERROR 0x01000000 - -#define USB_DEV_RX_SENT_STALL 0x00400000 -#define USB_DEV_RX_DATA_ERROR 0x00080000 -#define USB_DEV_RX_OVERRUN 0x00040000 - -#define USB_DEV_RX_FIFO_FULL 0x00020000 -#define USB_DEV_RX_PKT_RDY 0x00010000 -#define USB_DEV_TX_NOT_COMP 0x00000080 - -#define USB_DEV_TX_SENT_STALL 0x00000020 -#define USB_DEV_TX_UNDERRUN 0x00000004 -#define USB_DEV_TX_FIFO_NE 0x00000002 -#define USB_DEV_TX_TXPKTRDY 0x00000001 -#define USB_DEV_EP0_SETUP_END 0x00000010 - -#define USB_DEV_EP0_SENT_STALL 0x00000004 -#define USB_DEV_EP0_IN_PKTPEND 0x00000002 -#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 - -#define USB_EP_AUTO_SET 0x00000001 -#define USB_EP_AUTO_REQUEST 0x00000002 -#define USB_EP_AUTO_CLEAR 0x00000004 -#define USB_EP_DMA_MODE_0 0x00000008 -#define USB_EP_DMA_MODE_1 0x00000010 -#define USB_EP_DIS_NYET 0x00000020 - - -#define USB_EP_MODE_ISOC 0x00000000 -#define USB_EP_MODE_BULK 0x00000100 -#define USB_EP_MODE_INT 0x00000200 -#define USB_EP_MODE_CTRL 0x00000300 -#define USB_EP_MODE_MASK 0x00000300 -#define USB_EP_SPEED_LOW 0x00000000 -#define USB_EP_SPEED_FULL 0x00001000 -#define USB_EP_SPEED_HIGH 0x00004000 -#define USB_EP_HOST_IN 0x00000000 -#define USB_EP_HOST_OUT 0x00002000 -#define USB_EP_DEV_IN 0x00002000 -#define USB_EP_DEV_OUT 0x00000000 - -#define USB_HOST_PWRFLT_LOW 0x00000010 -#define USB_HOST_PWRFLT_HIGH 0x00000030 -#define USB_HOST_PWRFLT_EP_NONE 0x00000000 -#define USB_HOST_PWRFLT_EP_TRI 0x00000140 -#define USB_HOST_PWRFLT_EP_LOW 0x00000240 -#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 -#define USB_HOST_PWREN_MAN_LOW 0x00000000 -#define USB_HOST_PWREN_MAN_HIGH 0x00000001 -#define USB_HOST_PWREN_AUTOLOW 0x00000002 -#define USB_HOST_PWREN_AUTOHIGH 0x00000003 -#define USB_HOST_PWREN_FILTER 0x00010000 - -#define USB_HOST_LPM_RMTWAKE 0x00000100 -#define USB_HOST_LPM_L1 0x00000001 -#define USB_DEV_LPM_NAK 0x00000010 -#define USB_DEV_LPM_NONE 0x00000000 -#define USB_DEV_LPM_EN 0x0000000c -#define USB_DEV_LPM_EXTONLY 0x00000004 -#define USB_DEV_LPM_LS_RMTWAKE 0x00000100 -#define USB_DEV_LPM_LS_L1 0x00000001 -#define USB_INTLPM_ERROR 0x00000020 -#define USB_INTLPM_RESUME 0x00000010 -#define USB_INTLPM_INCOMPLETE 0x00000008 -#define USB_INTLPM_ACK 0x00000004 -#define USB_INTLPM_NYET 0x00000002 -#define USB_INTLPM_STALL 0x00000001 - -#define MAX_NAK_LIMIT 31 -#define DISABLE_NAK_LIMIT 0 - -#define MAX_PACKET_SIZE_EP0 64 -#define USB_EP_0 0 -#define USB_EP_1 1 -#define USB_EP_2 2 -#define USB_EP_3 3 -#define USB_EP_4 4 -#define USB_EP_5 5 -#define NUM_USB_EP 6 +#define USB_POWER_ISOUP 0x00000080U +#define USB_POWER_SOFTCONN 0x00000040U +#define USB_POWER_HS_EN 0x00000020U +#define USB_POWER_HS_M 0x00000010U +#define USB_POWER_RESET 0x00000008U +#define USB_POWER_RESUME 0x00000004U +#define USB_POWER_SUSPEND 0x00000002U +#define USB_POWER_PWRDNPHY 0x00000001U + +#define USB_DEVCTL_DEV 0x00000080U +#define USB_DEVCTL_FSDEV 0x00000040U +#define USB_DEVCTL_LSDEV 0x00000020U +#define USB_DEVCTL_VBUS_M 0x00000018U +#define USB_DEVCTL_VBUS_NONE 0x00000000U +#define USB_DEVCTL_VBUS_SEND 0x00000008U +#define USB_DEVCTL_VBUS_AVALID 0x00000010U +#define USB_DEVCTL_VBUS_VALID 0x00000018U +#define USB_DEVCTL_HOST 0x00000004U +#define USB_DEVCTL_HOSTREQ 0x00000002U +#define USB_DEVCTL_SESSION 0x00000001U + +#define USB_RXCSRH1_AUTOCL 0x00000080U +#define USB_RXCSRH1_AUTORQ 0x00000040U +#define USB_RXCSRH1_ISO 0x00000040U +#define USB_RXCSRH1_DMAEN 0x00000020U +#define USB_RXCSRH1_DISNYET 0x00000010U +#define USB_RXCSRH1_PIDERR 0x00000010U +#define USB_RXCSRH1_DMAMOD 0x00000008U +#define USB_RXCSRH1_DTWE 0x00000004U +#define USB_RXCSRH1_DT 0x00000002U +#define USB_RXCSRH1_INCOMPRX 0x00000001U + +#define USB_CSRH0_DISPING 0x00000008U +#define USB_CSRH0_DTWE 0x00000004U +#define USB_CSRH0_DT 0x00000002U +#define USB_CSRH0_FLUSH 0x00000001U + +#define USB_TXCSRH1_AUTOSET 0x00000080U +#define USB_TXCSRH1_ISO 0x00000040U +#define USB_TXCSRH1_MODE 0x00000020U +#define USB_TXCSRH1_DMAEN 0x00000010U +#define USB_TXCSRH1_FDT 0x00000008U +#define USB_TXCSRH1_DMAMOD 0x00000004U +#define USB_TXCSRH1_DTWE 0x00000002U +#define USB_TXCSRH1_DT 0x00000001U + +#define USB_TXCSRL1_NAKTO 0x00000080U +#define USB_TXCSRL1_CLRDT 0x00000040U +#define USB_TXCSRL1_STALLED 0x00000020U +#define USB_TXCSRL1_STALL 0x00000010U +#define USB_TXCSRL1_SETUP 0x00000010U +#define USB_TXCSRL1_FLUSH 0x00000008U +#define USB_TXCSRL1_ERROR 0x00000004U +#define USB_TXCSRL1_UNDRN 0x00000004U +#define USB_TXCSRL1_FIFONE 0x00000002U +#define USB_TXCSRL1_TXRDY 0x00000001U + +#define USB_RXCSRL1_CLRDT 0x00000080U +#define USB_RXCSRL1_STALLED 0x00000040U +#define USB_RXCSRL1_STALL 0x00000020U +#define USB_RXCSRL1_REQPKT 0x00000020U +#define USB_RXCSRL1_FLUSH 0x00000010U +#define USB_RXCSRL1_DATAERR 0x00000008U +#define USB_RXCSRL1_NAKTO 0x00000008U +#define USB_RXCSRL1_OVER 0x00000004U +#define USB_RXCSRL1_ERROR 0x00000004U +#define USB_RXCSRL1_FULL 0x00000002U +#define USB_RXCSRL1_RXRDY 0x00000001U + +#define USB_CSRL0_NAKTO 0x00000080U +#define USB_CSRL0_SETENDC 0x00000080U +#define USB_CSRL0_STATUS 0x00000040U +#define USB_CSRL0_RXRDYC 0x00000040U +#define USB_CSRL0_REQPKT 0x00000020U +#define USB_CSRL0_STALL 0x00000020U +#define USB_CSRL0_SETEND 0x00000010U +#define USB_CSRL0_ERROR 0x00000010U +#define USB_CSRL0_DATAEND 0x00000008U +#define USB_CSRL0_SETUP 0x00000008U +#define USB_CSRL0_STALLED 0x00000004U +#define USB_CSRL0_TXRDY 0x00000002U +#define USB_CSRL0_RXRDY 0x00000001U + +#define USB_TYPE0_SPEED_M 0x000000C0U +#define USB_TYPE0_SPEED_HIGH 0x00000040U +#define USB_TYPE0_SPEED_FULL 0x00000080U +#define USB_TYPE0_SPEED_LOW 0x000000C0U + +#define USB_TXTYPE1_SPEED_M 0x000000C0U +#define USB_TXTYPE1_SPEED_DFLT 0x00000000U +#define USB_TXTYPE1_SPEED_HIGH 0x00000040U +#define USB_TXTYPE1_SPEED_FULL 0x00000080U +#define USB_TXTYPE1_SPEED_LOW 0x000000C0U +#define USB_TXTYPE1_PROTO_M 0x00000030U +#define USB_TXTYPE1_PROTO_CTRL 0x00000000U +#define USB_TXTYPE1_PROTO_ISOC 0x00000010U +#define USB_TXTYPE1_PROTO_BULK 0x00000020U +#define USB_TXTYPE1_PROTO_INT 0x00000030U +#define USB_TXTYPE1_TEP_M 0x0000000FU +#define USB_TXTYPE1_TEP_S 0U + +#define USB_LPMATTR_ENDPT_M 0x0000F000U +#define USB_LPMATTR_RMTWAK 0x00000100U +#define USB_LPMATTR_HIRD_M 0x000000F0U +#define USB_LPMATTR_LS_M 0x0000000FU +#define USB_LPMATTR_LS_L1 0x00000001U +#define USB_LPMATTR_ENDPT_S 12U +#define USB_LPMATTR_HIRD_S 4U + +#define USB_LPMCNTRL_LPMRES 0x00000002U +#define USB_LPMCNTRL_LPMXMT 0x00000001U +#define USB_LPMCNTRL_ENABLE 0x00000006U +#define USB_LPMCNTRL_DISABLE 0x00000000U + +#define USB_INTCTRL_ALL 0x000003FFU +#define USB_INTCTRL_STATUS 0x000000FFU +#define USB_INTCTRL_VBUS_ERR 0x00000080U +#define USB_INTCTRL_SESSION 0x00000040U +#define USB_INTCTRL_SESSION_END 0x00000040U +#define USB_INTCTRL_DISCONNECT 0x00000020U +#define USB_INTCTRL_CONNECT 0x00000010U +#define USB_INTCTRL_SOF 0x00000008U +#define USB_INTCTRL_BABBLE 0x00000004U +#define USB_INTCTRL_RESET 0x00000004U +#define USB_INTCTRL_RESUME 0x00000002U +#define USB_INTCTRL_SUSPEND 0x00000001U +#define USB_INTCTRL_MODE_DETECT 0x00000200U +#define USB_INTCTRL_POWER_FAULT 0x00000100U + +#define USB_INTEP_ALL 0xFFFFFFFFU +#define USB_INTEP_HOST_IN 0xFFFE0000U +#define USB_INTEP_HOST_IN_15 0x80000000U +#define USB_INTEP_HOST_IN_14 0x40000000U +#define USB_INTEP_HOST_IN_13 0x20000000U +#define USB_INTEP_HOST_IN_12 0x10000000U +#define USB_INTEP_HOST_IN_11 0x08000000U +#define USB_INTEP_HOST_IN_10 0x04000000U +#define USB_INTEP_HOST_IN_9 0x02000000U +#define USB_INTEP_HOST_IN_8 0x01000000U +#define USB_INTEP_HOST_IN_7 0x00800000U +#define USB_INTEP_HOST_IN_6 0x00400000U +#define USB_INTEP_HOST_IN_5 0x00200000U +#define USB_INTEP_HOST_IN_4 0x00100000U +#define USB_INTEP_HOST_IN_3 0x00080000U +#define USB_INTEP_HOST_IN_2 0x00040000U +#define USB_INTEP_HOST_IN_1 0x00020000U + +#define USB_INTEP_DEV_OUT 0xFFFE0000U +#define USB_INTEP_DEV_OUT_15 0x80000000U +#define USB_INTEP_DEV_OUT_14 0x40000000U +#define USB_INTEP_DEV_OUT_13 0x20000000U +#define USB_INTEP_DEV_OUT_12 0x10000000U +#define USB_INTEP_DEV_OUT_11 0x08000000U +#define USB_INTEP_DEV_OUT_10 0x04000000U +#define USB_INTEP_DEV_OUT_9 0x02000000U +#define USB_INTEP_DEV_OUT_8 0x01000000U +#define USB_INTEP_DEV_OUT_7 0x00800000U +#define USB_INTEP_DEV_OUT_6 0x00400000U +#define USB_INTEP_DEV_OUT_5 0x00200000U +#define USB_INTEP_DEV_OUT_4 0x00100000U +#define USB_INTEP_DEV_OUT_3 0x00080000U +#define USB_INTEP_DEV_OUT_2 0x00040000U +#define USB_INTEP_DEV_OUT_1 0x00020000U + +#define USB_INTEP_HOST_OUT 0x0000FFFEU +#define USB_INTEP_HOST_OUT_15 0x00008000U +#define USB_INTEP_HOST_OUT_14 0x00004000U +#define USB_INTEP_HOST_OUT_13 0x00002000U +#define USB_INTEP_HOST_OUT_12 0x00001000U +#define USB_INTEP_HOST_OUT_11 0x00000800U +#define USB_INTEP_HOST_OUT_10 0x00000400U +#define USB_INTEP_HOST_OUT_9 0x00000200U +#define USB_INTEP_HOST_OUT_8 0x00000100U +#define USB_INTEP_HOST_OUT_7 0x00000080U +#define USB_INTEP_HOST_OUT_6 0x00000040U +#define USB_INTEP_HOST_OUT_5 0x00000020U +#define USB_INTEP_HOST_OUT_4 0x00000010U +#define USB_INTEP_HOST_OUT_3 0x00000008U +#define USB_INTEP_HOST_OUT_2 0x00000004U +#define USB_INTEP_HOST_OUT_1 0x00000002U + +#define USB_INTEP_DEV_IN 0x0000FFFEU +#define USB_INTEP_DEV_IN_15 0x00008000U +#define USB_INTEP_DEV_IN_14 0x00004000U +#define USB_INTEP_DEV_IN_13 0x00002000U +#define USB_INTEP_DEV_IN_12 0x00001000U +#define USB_INTEP_DEV_IN_11 0x00000800U +#define USB_INTEP_DEV_IN_10 0x00000400U +#define USB_INTEP_DEV_IN_9 0x00000200U +#define USB_INTEP_DEV_IN_8 0x00000100U +#define USB_INTEP_DEV_IN_7 0x00000080U +#define USB_INTEP_DEV_IN_6 0x00000040U +#define USB_INTEP_DEV_IN_5 0x00000020U +#define USB_INTEP_DEV_IN_4 0x00000010U +#define USB_INTEP_DEV_IN_3 0x00000008U +#define USB_INTEP_DEV_IN_2 0x00000004U +#define USB_INTEP_DEV_IN_1 0x00000002U + +#define USB_INTEP_0 0x00000001U + +#define USB_UNDEF_SPEED 0x80000000U +#define USB_HIGH_SPEED 0x00000002U +#define USB_FULL_SPEED 0x00000001U +#define USB_LOW_SPEED 0x00000000U + +#define USB_HOST_IN_STATUS 0x114F0000U +#define USB_HOST_IN_PID_ERROR 0x10000000U +#define USB_HOST_IN_NOT_COMP 0x01000000U +#define USB_HOST_IN_STALL 0x00400000U +#define USB_HOST_IN_DATA_ERROR 0x00080000U + +#define USB_HOST_IN_NAK_TO 0x00080000U + +#define USB_HOST_IN_ERROR 0x00040000U + +#define USB_HOST_IN_FIFO_FULL 0x00020000U +#define USB_HOST_IN_PKTRDY 0x00010000U +#define USB_HOST_OUT_STATUS 0x000000A7U +#define USB_HOST_OUT_NAK_TO 0x00000080U + +#define USB_HOST_OUT_NOT_COMP 0x00000080U + +#define USB_HOST_OUT_STALL 0x00000020U +#define USB_HOST_OUT_ERROR 0x00000004U + +#define USB_HOST_OUT_FIFO_NE 0x00000002U +#define USB_HOST_OUT_PKTPEND 0x00000001U +#define USB_HOST_EP0_NAK_TO 0x00000080U + +#define USB_HOST_EP0_STATUS 0x00000040U +#define USB_HOST_EP0_ERROR 0x00000010U + +#define USB_HOST_EP0_RX_STALL 0x00000004U +#define USB_HOST_EP0_RXPKTRDY 0x00000001U +#define USB_DEV_RX_PID_ERROR 0x01000000U + +#define USB_DEV_RX_SENT_STALL 0x00400000U +#define USB_DEV_RX_DATA_ERROR 0x00080000U +#define USB_DEV_RX_OVERRUN 0x00040000U + +#define USB_DEV_RX_FIFO_FULL 0x00020000U +#define USB_DEV_RX_PKT_RDY 0x00010000U +#define USB_DEV_TX_NOT_COMP 0x00000080U + +#define USB_DEV_TX_SENT_STALL 0x00000020U +#define USB_DEV_TX_UNDERRUN 0x00000004U +#define USB_DEV_TX_FIFO_NE 0x00000002U +#define USB_DEV_TX_TXPKTRDY 0x00000001U +#define USB_DEV_EP0_SETUP_END 0x00000010U + +#define USB_DEV_EP0_SENT_STALL 0x00000004U +#define USB_DEV_EP0_IN_PKTPEND 0x00000002U +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001U + +#define USB_EP_AUTO_SET 0x00000001U +#define USB_EP_AUTO_REQUEST 0x00000002U +#define USB_EP_AUTO_CLEAR 0x00000004U +#define USB_EP_DMA_MODE_0 0x00000008U +#define USB_EP_DMA_MODE_1 0x00000010U +#define USB_EP_DIS_NYET 0x00000020U + + +#define USB_EP_MODE_ISOC 0x00000000U +#define USB_EP_MODE_BULK 0x00000100U +#define USB_EP_MODE_INT 0x00000200U +#define USB_EP_MODE_CTRL 0x00000300U +#define USB_EP_MODE_MASK 0x00000300U +#define USB_EP_SPEED_LOW 0x00000000U +#define USB_EP_SPEED_FULL 0x00001000U +#define USB_EP_SPEED_HIGH 0x00004000U +#define USB_EP_HOST_IN 0x00000000U +#define USB_EP_HOST_OUT 0x00002000U +#define USB_EP_DEV_IN 0x00002000U +#define USB_EP_DEV_OUT 0x00000000U + +#define USB_HOST_PWRFLT_LOW 0x00000010U +#define USB_HOST_PWRFLT_HIGH 0x00000030U +#define USB_HOST_PWRFLT_EP_NONE 0x00000000U +#define USB_HOST_PWRFLT_EP_TRI 0x00000140U +#define USB_HOST_PWRFLT_EP_LOW 0x00000240U +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340U +#define USB_HOST_PWREN_MAN_LOW 0x00000000U +#define USB_HOST_PWREN_MAN_HIGH 0x00000001U +#define USB_HOST_PWREN_AUTOLOW 0x00000002U +#define USB_HOST_PWREN_AUTOHIGH 0x00000003U +#define USB_HOST_PWREN_FILTER 0x00010000U + +#define USB_HOST_LPM_RMTWAKE 0x00000100U +#define USB_HOST_LPM_L1 0x00000001U +#define USB_DEV_LPM_NAK 0x00000010U +#define USB_DEV_LPM_NONE 0x00000000U +#define USB_DEV_LPM_EN 0x0000000cU +#define USB_DEV_LPM_EXTONLY 0x00000004U +#define USB_DEV_LPM_LS_RMTWAKE 0x00000100U +#define USB_DEV_LPM_LS_L1 0x00000001U +#define USB_INTLPM_ERROR 0x00000020U +#define USB_INTLPM_RESUME 0x00000010U +#define USB_INTLPM_INCOMPLETE 0x00000008U +#define USB_INTLPM_ACK 0x00000004U +#define USB_INTLPM_NYET 0x00000002U +#define USB_INTLPM_STALL 0x00000001U + +#define MAX_NAK_LIMIT 31U +#define DISABLE_NAK_LIMIT 0U + +#define MAX_PACKET_SIZE_EP0 64U +#define USB_EP_0 0U +#define USB_EP_1 1U +#define USB_EP_2 2U +#define USB_EP_3 3U +#define USB_EP_4 4U +#define USB_EP_5 5U +#define NUM_USB_EP 6U #define IndexToUSBEP(x) ((x)) #define USBEPToIndex(x) ((x)) -#define USB_FIFO_SZ_8 0x00000000 -#define USB_FIFO_SZ_16 0x00000001 -#define USB_FIFO_SZ_32 0x00000002 -#define USB_FIFO_SZ_64 0x00000003 -#define USB_FIFO_SZ_128 0x00000004 -#define USB_FIFO_SZ_256 0x00000005 -#define USB_FIFO_SZ_512 0x00000006 -#define USB_FIFO_SZ_1024 0x00000007 -#define USB_FIFO_SZ_2048 0x00000008 +#define USB_FIFO_SZ_8 0x00000000U +#define USB_FIFO_SZ_16 0x00000001U +#define USB_FIFO_SZ_32 0x00000002U +#define USB_FIFO_SZ_64 0x00000003U +#define USB_FIFO_SZ_128 0x00000004U +#define USB_FIFO_SZ_256 0x00000005U +#define USB_FIFO_SZ_512 0x00000006U +#define USB_FIFO_SZ_1024 0x00000007U +#define USB_FIFO_SZ_2048 0x00000008U #define USBFIFOSizeToBytes(x) (8 << (x)) -#define USB_TRANS_OUT 0x00000102 -#define USB_TRANS_IN 0x00000102 -#define USB_TRANS_IN_LAST 0x0000010a -#define USB_TRANS_SETUP 0x0000110a -#define USB_TRANS_STATUS 0x00000142 - -#define USB_DUAL_MODE_HOST 0x00000001 -#define USB_DUAL_MODE_DEVICE 0x00000081 -#define USB_DUAL_MODE_NONE 0x00000080 -#define USB_OTG_MODE_ASIDE_HOST 0x0000001d -#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 -#define USB_OTG_MODE_ASIDE_SESS 0x00000009 -#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 -#define USB_OTG_MODE_ASIDE_DEV 0x00000019 -#define USB_OTG_MODE_BSIDE_HOST 0x0000009d -#define USB_OTG_MODE_BSIDE_DEV 0x00000099 -#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 -#define USB_OTG_MODE_NONE 0x00000080 - -#define USB_DMA_INT_CH8 0x00000080 -#define USB_DMA_INT_CH7 0x00000040 -#define USB_DMA_INT_CH6 0x00000020 -#define USB_DMA_INT_CH5 0x00000010 -#define USB_DMA_INT_CH4 0x00000008 -#define USB_DMA_INT_CH3 0x00000004 -#define USB_DMA_INT_CH2 0x00000002 -#define USB_DMA_INT_CH1 0x00000001 -#define USB_DMA_EP_CFG_TX 0x00000001 -#define USB_DMA_EP_CFG_RX_DEV 0x00000002 -#define USB_DMA_EP_CFG_RX_HOST 0x00000004 -#define USB_DMA_EP_TX_MSK 0x94 -#define USB_DMA_EP_RX_DEV_MSK 0xA8 -#define USB_DMA_EP_RX_HOST_MSK 0xE8 -#define USB_DMA_STATUS_ERROR 0x00000100 - -#define USB_MODE_HOST_VBUS 0x00000004 -#define USB_MODE_HOST 0x00000002 -#define USB_MODE_DEV_VBUS 0x00000005 -#define USB_MODE_DEV 0x00000003 -#define USB_MODE_OTG 0x00000000 - -#define USB_RX_EPSTATUS_SHIFT 16 -#define USB_INTEP_RX_SHIFT 16 - -#define USB_DMA_CFG_START 0x00000001 -#define USB_DMA_CFG_START_NO 0x00000000 -#define USB_DMA_CFG_DIR_WR 0x00000000 -#define USB_DMA_CFG_DIR_RD 0x00000002 -#define USB_DMA_CFG_MODE_0 0x00000000 -#define USB_DMA_CFG_MODE_1 0x00000004 -#define USB_DMA_CFG_IE_DIS 0x00000000 -#define USB_DMA_CFG_IE_EN 0x00000008 -#define USB_DMA_CFG_EP_1 0x00000010 -#define USB_DMA_CFG_EP_2 0x00000020 -#define USB_DMA_CFG_EP_3 0x00000030 -#define USB_DMA_CFG_EP_4 0x00000040 -#define USB_DMA_CFG_EP_5 0x00000050 -#define USB_DMA_CFG_BURST_NONE 0x00000000 -#define USB_DMA_CFG_BURST_4 0x00000200 -#define USB_DMA_CFG_BURST_8 0x00000400 -#define USB_DMA_CFG_BURST_16 0x00000600 -#define USB_DMA_CFG_MODE_MSK 0x00000004 -#define USB_DMA_CFG_EP_POS 0x00000004 -#define USB_DMA_CFG_EP_MSK 0x000000F0 -#define USB_DMA_CH_ERR_MSK 0x100 +#define USB_TRANS_OUT 0x00000102U +#define USB_TRANS_IN 0x00000102U +#define USB_TRANS_IN_LAST 0x0000010aU +#define USB_TRANS_SETUP 0x0000110aU +#define USB_TRANS_STATUS 0x00000142U + +#define USB_DUAL_MODE_HOST 0x00000001U +#define USB_DUAL_MODE_DEVICE 0x00000081U +#define USB_DUAL_MODE_NONE 0x00000080U +#define USB_OTG_MODE_ASIDE_HOST 0x0000001dU +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001U +#define USB_OTG_MODE_ASIDE_SESS 0x00000009U +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011U +#define USB_OTG_MODE_ASIDE_DEV 0x00000019U +#define USB_OTG_MODE_BSIDE_HOST 0x0000009dU +#define USB_OTG_MODE_BSIDE_DEV 0x00000099U +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081U +#define USB_OTG_MODE_NONE 0x00000080U + +#define USB_DMA_INT_CH8 0x00000080U +#define USB_DMA_INT_CH7 0x00000040U +#define USB_DMA_INT_CH6 0x00000020U +#define USB_DMA_INT_CH5 0x00000010U +#define USB_DMA_INT_CH4 0x00000008U +#define USB_DMA_INT_CH3 0x00000004U +#define USB_DMA_INT_CH2 0x00000002U +#define USB_DMA_INT_CH1 0x00000001U +#define USB_DMA_EP_CFG_TX 0x00000001U +#define USB_DMA_EP_CFG_RX_DEV 0x00000002U +#define USB_DMA_EP_CFG_RX_HOST 0x00000004U +#define USB_DMA_EP_TX_MSK 0x94U +#define USB_DMA_EP_RX_DEV_MSK 0xA8U +#define USB_DMA_EP_RX_HOST_MSK 0xE8U +#define USB_DMA_STATUS_ERROR 0x00000100U + +#define USB_MODE_HOST_VBUS 0x00000004U +#define USB_MODE_HOST 0x00000002U +#define USB_MODE_DEV_VBUS 0x00000005U +#define USB_MODE_DEV 0x00000003U +#define USB_MODE_OTG 0x00000000U + +#define USB_RX_EPSTATUS_SHIFT 16U +#define USB_INTEP_RX_SHIFT 16U + +#define USB_DMA_CFG_START 0x00000001U +#define USB_DMA_CFG_START_NO 0x00000000U +#define USB_DMA_CFG_DIR_WR 0x00000000U +#define USB_DMA_CFG_DIR_RD 0x00000002U +#define USB_DMA_CFG_MODE_0 0x00000000U +#define USB_DMA_CFG_MODE_1 0x00000004U +#define USB_DMA_CFG_IE_DIS 0x00000000U +#define USB_DMA_CFG_IE_EN 0x00000008U +#define USB_DMA_CFG_EP_1 0x00000010U +#define USB_DMA_CFG_EP_2 0x00000020U +#define USB_DMA_CFG_EP_3 0x00000030U +#define USB_DMA_CFG_EP_4 0x00000040U +#define USB_DMA_CFG_EP_5 0x00000050U +#define USB_DMA_CFG_BURST_NONE 0x00000000U +#define USB_DMA_CFG_BURST_4 0x00000200U +#define USB_DMA_CFG_BURST_8 0x00000400U +#define USB_DMA_CFG_BURST_16 0x00000600U +#define USB_DMA_CFG_MODE_MSK 0x00000004U +#define USB_DMA_CFG_EP_POS 0x00000004U +#define USB_DMA_CFG_EP_MSK 0x000000F0U +#define USB_DMA_CH_ERR_MSK 0x100U /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h index f0bef5603aae5f090418153613f4e87706931721..5629fafaa381bf77ef87356b73fe5b6e60f209ac 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h @@ -39,10 +39,10 @@ extern "C" { * @brief Wwdt no dog window */ typedef enum { - WWDT_WIN_25 = 0x0, /**< No dog window size: 25% */ - WWDT_WIN_50 = 0x1, /**< No dog window size: 50% */ - WWDT_WIN_75 = 0x2, /**< No dog window size: 75% */ - WWDT_WIN_00 = 0x3, /**< No dog window size: 0% */ + WWDT_WIN_25 = 0x0U, /**< No dog window size: 25% */ + WWDT_WIN_50 = 0x1U, /**< No dog window size: 50% */ + WWDT_WIN_75 = 0x2U, /**< No dog window size: 75% */ + WWDT_WIN_00 = 0x3U, /**< No dog window size: 0% */ } wwdt_win_t; /** @@ -53,10 +53,10 @@ typedef enum { * @defgroup WDT_Private_Macros WDT Private Macros * @{ */ -#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551);} -#define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFF);} -#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551);} -#define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFF);} +#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);} +#define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);} +#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);} +#define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);} /** * @} diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h index f09c9b06cf606aae1b67c48ec2faadf85435cae5..ea5bd889703b909f021269114d6982630df9bfeb 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h @@ -35,35 +35,35 @@ extern "C" { #define __isr__ typedef enum { - RESET = 0x0, - SET = 0x1, + RESET = 0x0U, + SET = 0x1U, } flag_status_t, it_status_t; typedef enum { - BIT_RESET = 0x0, - BIT_SET = 0x1, + BIT_RESET = 0x0U, + BIT_SET = 0x1U, } bit_status_t; typedef enum { - DISABLE = 0x0, - ENABLE = 0x1, + DISABLE = 0x0U, + ENABLE = 0x1U, } type_func_t; #define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) typedef enum { - FALSE = 0x0, - TRUE = 0x1, + FALSE = 0x0U, + TRUE = 0x1U, } type_bool_t; typedef enum { - UNLOCK = 0x0, - LOCK = 0x1, + UNLOCK = 0x0U, + LOCK = 0x1U, } lock_state_t; #define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) #define BIT(x) ((1U << (x))) -#define BITS(s, e) ((0xffffffff << (s)) & (0xffffffff >> (31 - (e)))) +#define BITS(s, e) ((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e)))) #define SET_BIT(reg, bit) ((reg) |= (bit)) #define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) #define READ_BIT(reg, bit) ((reg) & (bit)) diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h index 39398b771f7290cbffeeb0a62b821ac2c6341a17..1c6b1b942f1a091a02636c191d30ff683af5a293 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h @@ -52,31 +52,31 @@ extern uint32_t __systick_interval; * @brief ALD Status structures definition */ typedef enum { - OK = 0x0, /**< OK */ - ERROR = 0x1, /**< ERROR */ - BUSY = 0x2, /**< BUSY */ - TIMEOUT = 0x3 /**< TIMEOUT */ + OK = 0x0U, /**< OK */ + ERROR = 0x1U, /**< ERROR */ + BUSY = 0x2U, /**< BUSY */ + TIMEOUT = 0x3U, /**< TIMEOUT */ } ald_status_t; /** * @brief NVIC Preemption Priority Group */ typedef enum { - NVIC_PRIORITY_GROUP_0 = 0x7, /**< 0-bits for pre-emption priority 4-bits for subpriority */ - NVIC_PRIORITY_GROUP_1 = 0x6, /**< 1-bits for pre-emption priority 3-bits for subpriority */ - NVIC_PRIORITY_GROUP_2 = 0x5, /**< 2-bits for pre-emption priority 2-bits for subpriority */ - NVIC_PRIORITY_GROUP_3 = 0x4, /**< 3-bits for pre-emption priority 1-bits for subpriority */ - NVIC_PRIORITY_GROUP_4 = 0x3, /**< 4-bits for pre-emption priority 0-bits for subpriority */ + NVIC_PRIORITY_GROUP_0 = 0x7U, /**< 0-bits for pre-emption priority 4-bits for subpriority */ + NVIC_PRIORITY_GROUP_1 = 0x6U, /**< 1-bits for pre-emption priority 3-bits for subpriority */ + NVIC_PRIORITY_GROUP_2 = 0x5U, /**< 2-bits for pre-emption priority 2-bits for subpriority */ + NVIC_PRIORITY_GROUP_3 = 0x4U, /**< 3-bits for pre-emption priority 1-bits for subpriority */ + NVIC_PRIORITY_GROUP_4 = 0x3U, /**< 4-bits for pre-emption priority 0-bits for subpriority */ } nvic_priority_group_t; /** * @brief SysTick interval definition */ typedef enum { - SYSTICK_INTERVAL_1MS = 1000, /**< Interval is 1ms */ - SYSTICK_INTERVAL_10MS = 100, /**< Interval is 10ms */ - SYSTICK_INTERVAL_100MS = 10, /**< Interval is 100ms */ - SYSTICK_INTERVAL_1000MS = 1, /**< Interval is 1s */ + SYSTICK_INTERVAL_1MS = 1000U, /**< Interval is 1ms */ + SYSTICK_INTERVAL_10MS = 100U, /**< Interval is 10ms */ + SYSTICK_INTERVAL_100MS = 10U, /**< Interval is 100ms */ + SYSTICK_INTERVAL_1000MS = 1U, /**< Interval is 1s */ } systick_interval_t; /** * @} @@ -85,16 +85,10 @@ typedef enum { /** @defgroup ALD_Public_Macros Public Macros * @{ */ -#define ALD_MAX_DELAY 0xFFFFFFFF - +#define ALD_MAX_DELAY 0xFFFFFFFFU #define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET) #define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET) #define RESET_HANDLE_STATE(x) ((x)->state = 0) -#define DWT_CR *(uint32_t *)0xE0001000 -#define DWT_CYCCNT *(volatile uint32_t *)0xE0001004 -#define DEM_CR *(uint32_t *)0xE000EDFC -#define DEM_CR_TRCENA (1U << 24) -#define DWT_CR_CYCCNTEA (1U << 0) #define __LOCK(x) \ do { \ if ((x)->lock == LOCK) { \ @@ -120,6 +114,15 @@ do { \ /** @defgroup ALD_Private_Macros Private Macros * @{ */ +#define MCU_UID0_ADDR 0x000803E0U +#define MCU_UID1_ADDR 0x000803E8U +#define MCU_UID2_ADDR 0x000803F0U +#define MCU_CHIPID_ADDR 0x000803F8U +#define DWT_CR *(uint32_t *)0xE0001000U +#define DWT_CYCCNT *(volatile uint32_t *)0xE0001004U +#define DEM_CR *(uint32_t *)0xE000EDFCU +#define DEM_CR_TRCENA (1U << 24) +#define DWT_CR_CYCCNTEA (1U << 0) #define IS_PREEMPT_PRIO(x) ((x) < 16) #define IS_SUB_PRIO(x) ((x) < 16) #define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \ @@ -158,12 +161,14 @@ uint32_t ald_get_tick(void); void ald_suspend_tick(void); void ald_resume_tick(void); uint32_t ald_get_ald_version(void); +void ald_flash_wait_config(uint8_t cycle); ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout); void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status); -uint32_t ald_mcu_get_cpu_id(void); void ald_mcu_timestamp_init(void); uint32_t ald_mcu_get_timestamp(void); - +uint32_t ald_mcu_get_cpu_id(void); +void ald_mcu_get_uid(uint8_t *buf); +uint32_t ald_mcu_get_chipid(void); /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c index f98ad7199b12f71e83c6de7f9acbe4a3b3d09676..c239d074b21ed221b4b6c0139b82e722de5d6127 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c @@ -73,21 +73,16 @@ static void adc_dma_error(void *arg); */ ald_status_t ald_adc_init(adc_handle_t *hperh) { - ald_status_t tmp_status = OK; - - if (hperh == NULL) - return ERROR; - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.data_align)); - assert_param(IS_ADC_SCAN_MODE_TYPE(hperh->init.scan_mode)); - assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.clk_div)); - assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.neg_ref)); - assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.pos_ref)); - assert_param(IS_ADC_CONV_RES_TYPE(hperh->init.conv_res)); - assert_param(IS_ADC_NCH_LEN_TYPE(hperh->init.nch_len)); - assert_param(IS_ADC_DISC_NBR_TYPE(hperh->init.disc_nbr)); - assert_param(IS_FUNC_STATE(hperh->init.cont_mode)); + assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.align)); + assert_param(IS_FUNC_STATE(hperh->init.scan)); + assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.div)); + assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.n_ref)); + assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.p_ref)); + assert_param(IS_ADC_CONV_BIT_TYPE(hperh->init.data_bit)); + assert_param(IS_ADC_NCH_NR_TYPE(hperh->init.nch_nr)); + assert_param(IS_ADC_DISC_NR_TYPE(hperh->init.disc_nr)); + assert_param(IS_FUNC_STATE(hperh->init.cont)); assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_sel)); if (hperh->state == ADC_STATE_RESET ) { @@ -97,48 +92,52 @@ ald_status_t ald_adc_init(adc_handle_t *hperh) ADC_DISABLE(hperh); ald_adc_reset(hperh); - hperh->state = ADC_STATE_BUSY_INTERNAL; - MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.data_align << ADC_CON1_ALIGN_POS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont_mode << ADC_CON1_CM_POS); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.conv_res << ADC_CON0_RSEL_POSS); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan_mode << ADC_CON0_SCANEN_POS); - - /* Enable discontinuous mode only if continuous mode is enabled */ - if (hperh->init.disc_mode == ADC_NCH_DISC_EN) { - hperh->init.scan_mode = ENABLE; + hperh->state = ADC_STATE_BUSY; + MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.align << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.data_bit << ADC_CON0_RSEL_POSS); + + /* Enable discontinuous mode only if continuous mode is disable */ + if (hperh->init.disc == ADC_NCH_DISC_EN) { + hperh->init.scan = ENABLE; + hperh->init.cont = DISABLE; SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nbr << ADC_CON0_ETRGN_POSS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS); + } + else if (hperh->init.disc == ADC_ICH_DISC_EN) { + hperh->init.scan = ENABLE; + hperh->init.cont = DISABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS); } else { CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); } - if ((hperh->init.scan_mode == ENABLE) || (hperh->init.disc_mode == ADC_NCH_DISC_EN)) - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_len << ADC_CHSL_NSL_POSS); + if ((hperh->init.scan == ENABLE) || (hperh->init.disc == ADC_NCH_DISC_EN)) + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_nr << ADC_CHSL_NSL_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan << ADC_CON0_SCANEN_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS); - /* if the ADC CLK less than 1MHZ,PWRMOD should be Enable*/ + /* if the ADC clock less than 1MHz,PWRMOD should be disable*/ MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.clk_div << ADC_CCR_CKDIV_POSS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.neg_ref << ADC_CCR_VRNSEL_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.pos_ref << ADC_CCR_VRPSEL_POSS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.div << ADC_CCR_CKDIV_POSS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS); MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS); - - if (tmp_status == OK) { - hperh->error_code = ADC_ERROR_NONE; - hperh->state |= ADC_STATE_READY; - hperh->state &= ~(ADC_STATE_ERROR | ADC_STATE_NM_BUSY - | ADC_STATE_IST_BUSY | ADC_STATE_BUSY_INTERNAL); - } - ald_adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE); - return tmp_status; + ADC_ENABLE(hperh); + + hperh->error_code = ADC_ERROR_NONE; + hperh->state = ADC_STATE_READY; + return OK; } /** @@ -150,20 +149,10 @@ ald_status_t ald_adc_init(adc_handle_t *hperh) */ ald_status_t ald_adc_reset(adc_handle_t *hperh) { - if (hperh == NULL) - return ERROR; - assert_param(IS_ADC_TYPE(hperh->perh)); ADC_DISABLE(hperh); - - ald_adc_clear_flag_status(hperh, ADC_FLAG_AWD); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); - ald_adc_clear_flag_status(hperh, ADC_FLAG_OVR); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); - + WRITE_REG(hperh->perh->CLR, 0x30F); WRITE_REG(hperh->perh->CON0, 0x0); WRITE_REG(hperh->perh->CON1, 0x0); WRITE_REG(hperh->perh->CCR, 0x0); @@ -203,18 +192,10 @@ ald_status_t ald_adc_reset(adc_handle_t *hperh) */ ald_status_t ald_adc_normal_start(adc_handle_t *hperh) { - if (hperh == NULL) - return ERROR; - assert_param(IS_ADC_TYPE(hperh->perh)); - __LOCK(hperh); ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); - hperh->state |= ADC_STATE_NM_BUSY; - __UNLOCK(hperh); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS); SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); return OK; @@ -234,13 +215,9 @@ ald_status_t ald_adc_normal_stop(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - __LOCK(hperh); - ADC_DISABLE(hperh); - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_NM_EOC); - hperh->state |= ADC_STATE_READY; + hperh->state = ADC_STATE_READY; - __UNLOCK(hperh); return OK; } @@ -258,32 +235,21 @@ ald_status_t ald_adc_normal_stop(adc_handle_t *hperh) */ ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = 0; + uint32_t _tick; assert_param(IS_ADC_TYPE(hperh->perh)); - tickstart = ald_get_tick(); + _tick = ald_get_tick(); while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) { if (timeout != ALD_MAX_DELAY ) { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { - hperh->state |= ADC_STATE_TIMEOUT; - __UNLOCK(hperh); + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { + hperh->state = ADC_STATE_TIMEOUT; return TIMEOUT; } } } - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - - hperh->state |= ADC_STATE_NM_EOC; - - if ((hperh->init.cont_mode == DISABLE) && (hperh->init.scan_mode == DISABLE)) { - hperh->state &= ~ADC_STATE_NM_BUSY; - - if ((hperh->state & ADC_STATE_IST_BUSY) == 0) - hperh->state |= ADC_STATE_READY; - } + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCHS | ADC_FLAG_NCH); return OK; } @@ -299,24 +265,22 @@ ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t ti */ ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout) { - uint32_t tickstart = 0; + uint32_t _tick; assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_EVENT_TYPE(event_type)); - tickstart = ald_get_tick(); - + _tick = ald_get_tick(); while (ald_adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) { if (timeout != ALD_MAX_DELAY ) { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { - hperh->state |= ADC_STATE_TIMEOUT; - __UNLOCK(hperh); + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { + hperh->state = ADC_STATE_TIMEOUT; return TIMEOUT; } } } - hperh->state |= ADC_STATE_AWD; + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_WDG); return OK; } @@ -333,21 +297,10 @@ ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - __LOCK(hperh); + SET_BIT(hperh->state, ADC_STATE_BUSY_N); ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); - hperh->state |= ADC_STATE_NM_BUSY; - hperh->error_code = ADC_ERROR_NONE; - - if (READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)) { - hperh->state &= ~(ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_IST_BUSY; - } - - __UNLOCK(hperh); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH); ald_adc_interrupt_config(hperh, ADC_IT_NCH, ENABLE); - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); return OK; @@ -365,13 +318,10 @@ ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - __LOCK(hperh); ADC_DISABLE(hperh); ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); - hperh->state |= ADC_STATE_READY; - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); - __UNLOCK(hperh); return OK; } @@ -388,30 +338,12 @@ ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh) */ ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) { - if ((hperh == NULL) || (buf == NULL) || (size == 0) || (channel > 5)) + if ((buf == NULL) || (size == 0)) return ERROR; assert_param(IS_ADC_TYPE(hperh->perh)); - __LOCK(hperh); - ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); - hperh->state |= ADC_STATE_NM_BUSY; - - if (READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)) { - hperh->state &= ~(ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_IST_BUSY; - } - - if ((hperh->state & ADC_STATE_IST_BUSY) != 0) { - hperh->state &= ~(ADC_STATE_ERROR); - hperh->error_code &= ~(ADC_ERROR_OVR | ADC_ERROR_DMA); - } - else { - hperh->state &= ~(ADC_STATE_ERROR); - hperh->error_code = ADC_ERROR_NONE; - } - __UNLOCK(hperh); + SET_BIT(hperh->state, ADC_STATE_BUSY_N); if (hperh->hdma.perh == NULL) hperh->hdma.perh = DMA0; @@ -428,13 +360,14 @@ ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t s hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma.config.msel = DMA_MSEL_ADC0; + hperh->hdma.config.msel = hperh->perh == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1; hperh->hdma.config.msigsel = DMA_MSIGSEL_ADC; hperh->hdma.config.burst = ENABLE; hperh->hdma.config.channel = channel; ald_dma_config_basic(&hperh->hdma); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_DMA_MSK, 1 << ADC_CON1_DMA_POS); + ADC_ENABLE(hperh); + SET_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK); SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); return OK; @@ -446,19 +379,18 @@ ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t s * ADC peripheral. * @param hperh: Pointer to a adc_handle_t structure that contains * the configuration information for the specified ADC module. + * @param channel: The DMA channel * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_stop_dma(adc_handle_t *hperh) +ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel) { assert_param(IS_ADC_TYPE(hperh->perh)); - __LOCK(hperh); ADC_DISABLE(hperh); - ald_pis_destroy(&hperh->hpis); - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); - hperh->state |= ADC_STATE_READY; + CLEAR_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK); + ald_dma_channel_config(hperh->hdma.perh, channel, DISABLE); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); - __UNLOCK(hperh); return OK; } @@ -471,16 +403,18 @@ static void adc_dma_timer_trigger_cplt(void *arg) { adc_timer_config_t *hperh = (adc_timer_config_t *)arg; - ADC_DISABLE(&hperh->lh_adc); - ald_timer_base_stop(&hperh->lh_timer); + ald_timer_base_stop(&hperh->h_timer); + CLEAR_BIT(hperh->h_adc.perh->CON1, ADC_CON1_DMA_MSK); + ADC_DISABLE(&hperh->h_adc); + ald_dma_channel_config(hperh->h_dma.perh, hperh->dma_ch, DISABLE); + CLEAR_BIT(hperh->h_adc.state, ADC_STATE_BUSY_N); - __UNLOCK(hperh); - if (hperh->lh_adc.adc_reg_cplt_cbk != NULL) - hperh->lh_adc.adc_reg_cplt_cbk(&hperh->lh_adc); + if (hperh->h_adc.normal_cplt_cbk) + hperh->h_adc.normal_cplt_cbk(&hperh->h_adc); + return; } - /** * @brief Config Timer trigger adc function * @param config: Pointer to a adc_timer_config_t structure that @@ -489,101 +423,185 @@ static void adc_dma_timer_trigger_cplt(void *arg) */ ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) { - __LOCK(config); - - config->lh_pis.perh = PIS; - config->lh_pis.init.producer_clk = PIS_CLK_PCLK1; - config->lh_pis.init.producer_edge = PIS_EDGE_NONE; - config->lh_pis.init.consumer_clk = PIS_CLK_PCLK2; + config->h_pis.perh = PIS; + config->h_pis.init.producer_clk = PIS_CLK_PCLK1; + config->h_pis.init.producer_edge = PIS_EDGE_NONE; + config->h_pis.init.consumer_clk = PIS_CLK_PCLK2; #if defined(ES32F36xx) if (config->p_timer == AD16C4T0) - config->lh_pis.init.producer_src = PIS_TIMER0_UPDATA; + config->h_pis.init.producer_src = PIS_TIMER0_UPDATA; else if (config->p_timer == AD16C4T1) - config->lh_pis.init.producer_src = PIS_TIMER1_UPDATA; + config->h_pis.init.producer_src = PIS_TIMER1_UPDATA; else if (config->p_timer == GP32C4T0) - config->lh_pis.init.producer_src = PIS_TIMER2_UPDATA; + config->h_pis.init.producer_src = PIS_TIMER2_UPDATA; else if (config->p_timer == GP32C4T1) - config->lh_pis.init.producer_src = PIS_TIMER3_UPDATA; + config->h_pis.init.producer_src = PIS_TIMER3_UPDATA; else return ERROR; #elif defined(ES32F39xx) || defined(ES32F336x) if (config->p_timer == GP16C4T0) - config->lh_pis.init.producer_src = PIS_TIMER0_UPDATA; + config->h_pis.init.producer_src = PIS_TIMER0_UPDATA; else if (config->p_timer == GP16C4T1) - config->lh_pis.init.producer_src = PIS_TIMER1_UPDATA; + config->h_pis.init.producer_src = PIS_TIMER1_UPDATA; else if (config->p_timer == GP32C4T0) - config->lh_pis.init.producer_src = PIS_TIMER2_UPDATA; + config->h_pis.init.producer_src = PIS_TIMER2_UPDATA; else if (config->p_timer == GP32C4T1) - config->lh_pis.init.producer_src = PIS_TIMER3_UPDATA; + config->h_pis.init.producer_src = PIS_TIMER3_UPDATA; else return ERROR; #endif if (config->p_adc == ADC0) - config->lh_pis.init.consumer_trig = PIS_CH6_ADC0_REGULAT; + config->h_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL; else return ERROR; - ald_pis_create(&config->lh_pis); + ald_pis_create(&config->h_pis); /* Initialize TIMER0 */ - config->lh_timer.perh = config->p_timer; - config->lh_timer.init.prescaler = 0; - config->lh_timer.init.mode = TIMER_CNT_MODE_UP; - config->lh_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time); - config->lh_timer.init.clk_div = TIMER_CLOCK_DIV1; - config->lh_timer.init.re_cnt = 0; - ald_timer_base_init(&config->lh_timer); - - config->lh_adc.perh = config->p_adc; - config->lh_adc.init.data_align = ADC_DATAALIGN_RIGHT; - config->lh_adc.init.scan_mode = DISABLE; - config->lh_adc.init.cont_mode = DISABLE; - config->lh_adc.init.nch_len = ADC_NCH_LEN_1; - config->lh_adc.init.disc_mode = ADC_ALL_DISABLE; - config->lh_adc.init.disc_nbr = ADC_DISC_NBR_1; - config->lh_adc.init.conv_res = ADC_CONV_RES_12; - config->lh_adc.init.clk_div = ADC_CKDIV_16; - config->lh_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE; - config->lh_adc.init.neg_ref = config->n_ref; - config->lh_adc.init.pos_ref = config->p_ref; - config->lh_adc.adc_reg_cplt_cbk = config->adc_cplt_cbk; - config->lh_adc.adc_inj_cplt_cbk = NULL; - config->lh_adc.adc_out_of_win_cbk = NULL; - config->lh_adc.adc_error_cbk = NULL; - config->lh_adc.adc_ovr_cbk = NULL; - ald_adc_init(&config->lh_adc); - - MODIFY_REG(config->lh_adc.perh->CON1, ADC_CON1_DMA_MSK, 1 << ADC_CON1_DMA_POS); - - config->lh_adc.perh->CON1 |= 0x10000000; - config->lnm_config.channel = config->adc_ch; - config->lnm_config.rank = ADC_NCH_RANK_1; - config->lnm_config.samp_time = ADC_SAMPLETIME_1; - ald_adc_normal_channel_config(&config->lh_adc, &config->lnm_config); - - config->lh_dma.cplt_cbk = adc_dma_timer_trigger_cplt; - config->lh_dma.cplt_arg = config; - config->lh_dma.err_cbk = adc_dma_error; - config->lh_dma.err_arg = &config->lh_adc; - - ald_dma_config_struct(&config->lh_dma.config); - config->lh_dma.perh = DMA0; - config->lh_dma.config.src = (void *)&config->lh_adc.perh->NCHDR; - config->lh_dma.config.dst = (void *)config->buf; - config->lh_dma.config.size = config->size; - config->lh_dma.config.data_width = DMA_DATA_SIZE_HALFWORD; - config->lh_dma.config.src_inc = DMA_DATA_INC_NONE; - config->lh_dma.config.dst_inc = DMA_DATA_INC_HALFWORD; - config->lh_dma.config.msel = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1; - config->lh_dma.config.msigsel = DMA_MSIGSEL_ADC; - config->lh_dma.config.burst = ENABLE; - config->lh_dma.config.channel = config->dma_ch; - ald_dma_config_basic(&config->lh_dma); - - ADC_ENABLE(&config->lh_adc); - ald_timer_base_start(&config->lh_timer); + config->h_timer.perh = config->p_timer; + config->h_timer.init.prescaler = 0; + config->h_timer.init.mode = TIMER_CNT_MODE_UP; + config->h_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time); + config->h_timer.init.clk_div = TIMER_CLOCK_DIV1; + config->h_timer.init.re_cnt = 0; + ald_timer_base_init(&config->h_timer); + + config->h_adc.perh = config->p_adc; + config->h_adc.init.align = ADC_DATAALIGN_RIGHT; + config->h_adc.init.scan = DISABLE; + config->h_adc.init.cont = DISABLE; + config->h_adc.init.nch_nr = ADC_NCH_NR_1; + config->h_adc.init.disc = ADC_ALL_DISABLE; + config->h_adc.init.disc_nr = ADC_DISC_NR_1; + config->h_adc.init.data_bit = ADC_CONV_BIT_12; + config->h_adc.init.div = ADC_CKDIV_128; + config->h_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE; + config->h_adc.init.n_ref = config->n_ref; + config->h_adc.init.p_ref = config->p_ref; + config->h_adc.normal_cplt_cbk = config->cplt_cbk; + config->h_adc.insert_cplt_cbk = NULL; + config->h_adc.wdg_cbk = NULL; + config->h_adc.error_cbk = NULL; + config->h_adc.ovr_cbk = NULL; + ald_adc_init(&config->h_adc); + + + + config->h_adc.perh->CON1 |= 0x10000000; + config->config.ch = config->adc_ch; + config->config.idx = ADC_NCH_IDX_1; + config->config.samp = ADC_SAMPLETIME_4; + ald_adc_normal_channel_config(&config->h_adc, &config->config); + + config->h_dma.cplt_cbk = adc_dma_timer_trigger_cplt; + config->h_dma.cplt_arg = config; + config->h_dma.err_cbk = adc_dma_error; + config->h_dma.err_arg = &config->h_adc; + + ald_dma_config_struct(&config->h_dma.config); + config->h_dma.perh = DMA0; + config->h_dma.config.src = (void *)&config->h_adc.perh->NCHDR; + config->h_dma.config.dst = (void *)config->buf; + config->h_dma.config.size = config->size; + config->h_dma.config.data_width = DMA_DATA_SIZE_HALFWORD; + config->h_dma.config.src_inc = DMA_DATA_INC_NONE; + config->h_dma.config.dst_inc = DMA_DATA_INC_HALFWORD; + config->h_dma.config.msel = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1; + config->h_dma.config.msigsel = DMA_MSIGSEL_ADC; + config->h_dma.config.burst = ENABLE; + config->h_dma.config.channel = config->dma_ch; + ald_dma_config_basic(&config->h_dma); + + SET_BIT(config->h_adc.perh->CON1, ADC_CON1_DMA_MSK); + ADC_ENABLE(&config->h_adc); + ald_timer_base_start(&config->h_timer); + + return OK; +} + + +/** + * @brief Config timer trigger adc insert channel conversion. + * @param config: Pointer to a adc_timer_config_t structure that + * contains the configuration information for the specified function. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config) +{ + config->h_pis.perh = PIS; + config->h_pis.init.producer_clk = PIS_CLK_PCLK1; + config->h_pis.init.producer_edge = PIS_EDGE_NONE; + config->h_pis.init.consumer_clk = PIS_CLK_PCLK2; + + #if defined(ES32F36xx) + if (config->p_timer == AD16C4T0) + config->h_pis.init.producer_src = PIS_TIMER0_UPDATA; + else if (config->p_timer == AD16C4T1) + config->h_pis.init.producer_src = PIS_TIMER1_UPDATA; + else if (config->p_timer == GP32C4T0) + config->h_pis.init.producer_src = PIS_TIMER2_UPDATA; + else if (config->p_timer == GP32C4T1) + config->h_pis.init.producer_src = PIS_TIMER3_UPDATA; + else + return ERROR; + #elif defined(ES32F39xx) || defined(ES32F336x) + if (config->p_timer == GP16C4T0) + config->h_pis.init.producer_src = PIS_TIMER0_UPDATA; + else if (config->p_timer == GP16C4T1) + config->h_pis.init.producer_src = PIS_TIMER1_UPDATA; + else if (config->p_timer == GP32C4T0) + config->h_pis.init.producer_src = PIS_TIMER2_UPDATA; + else if (config->p_timer == GP32C4T1) + config->h_pis.init.producer_src = PIS_TIMER3_UPDATA; + else + return ERROR; + #endif + + if (config->p_adc == ADC0) + config->h_pis.init.consumer_trig = PIS_CH7_ADC0_INSERT; + else + return ERROR; + + ald_pis_create(&config->h_pis); + + /* Initialize TIMER */ + config->h_timer.perh = config->p_timer; + config->h_timer.init.prescaler = 0; + config->h_timer.init.mode = TIMER_CNT_MODE_UP; + config->h_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time); + config->h_timer.init.clk_div = TIMER_CLOCK_DIV1; + config->h_timer.init.re_cnt = 0; + ald_timer_base_init(&config->h_timer); + + config->h_adc.perh = config->p_adc; + config->h_adc.init.align = ADC_DATAALIGN_RIGHT; + config->h_adc.init.scan = DISABLE; + config->h_adc.init.cont = DISABLE; + config->h_adc.init.ich_nr = ADC_ICH_NR_1; + config->h_adc.init.disc = ADC_ALL_DISABLE; + config->h_adc.init.disc_nr = ADC_DISC_NR_1; + config->h_adc.init.data_bit = ADC_CONV_BIT_12; + config->h_adc.init.div = ADC_CKDIV_128; + config->h_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE; + config->h_adc.init.n_ref = config->n_ref; + config->h_adc.init.p_ref = config->p_ref; + config->h_adc.normal_cplt_cbk = config->cplt_cbk; + config->h_adc.insert_cplt_cbk = NULL; + config->h_adc.wdg_cbk = NULL; + config->h_adc.error_cbk = NULL; + config->h_adc.ovr_cbk = NULL; + ald_adc_init(&config->h_adc); + + config->h_adc.perh->CON1 |= 0x00100000; /* rising edge trigger insert channel convert */ + config->i_config.ch = config->adc_ch; + config->i_config.idx = ADC_ICH_IDX_1; + config->i_config.samp = ADC_SAMPLETIME_4; + config->i_config.auto_m = DISABLE; + ald_adc_insert_channel_config(&config->h_adc, &config->i_config); + ADC_ENABLE(&config->h_adc); + ald_timer_base_start(&config->h_timer); return OK; } @@ -599,7 +617,6 @@ uint32_t ald_adc_normal_get_value(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - hperh->state &= ~ADC_STATE_NM_EOC; return hperh->perh->NCHDR; } @@ -614,16 +631,8 @@ ald_status_t ald_adc_insert_start(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - __LOCK(hperh); ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_IST_BUSY; - - if ((hperh->state & ADC_STATE_NM_BUSY) == 0) - hperh->error_code = ADC_ERROR_NONE; - - __UNLOCK(hperh); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICH); if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); @@ -647,21 +656,8 @@ ald_status_t ald_adc_insert_stop(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - __LOCK(hperh); - - if (((hperh->state & ADC_STATE_NM_BUSY) == 0) - && (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))) { - ADC_DISABLE(hperh); - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY | ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_READY; - } - else { - hperh->state |= ADC_STATE_ERROR; - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); + ADC_DISABLE(hperh); + hperh->state = ADC_STATE_READY; return OK; } @@ -674,34 +670,22 @@ ald_status_t ald_adc_insert_stop(adc_handle_t *hperh) */ ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart; + uint32_t _tick; assert_param(IS_ADC_TYPE(hperh->perh)); - tickstart = ald_get_tick(); + _tick = ald_get_tick(); while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) { if (timeout != ALD_MAX_DELAY) { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { hperh->state |= ADC_STATE_TIMEOUT; - __UNLOCK(hperh); return TIMEOUT; } } } - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - - hperh->state |= ADC_STATE_IST_EOC; - - hperh->state &= ~(ADC_STATE_IST_BUSY); - if ((hperh->state & ADC_STATE_NM_BUSY) == 0) - hperh->state |= ADC_STATE_READY; - - hperh->state &= ~(ADC_STATE_TIMEOUT); - __UNLOCK(hperh); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICHS | ADC_FLAG_ICH); return OK; } @@ -717,16 +701,9 @@ ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - __LOCK(hperh); + SET_BIT(hperh->state, ADC_STATE_BUSY_I); ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_IST_EOC); - hperh->state |= ADC_STATE_IST_BUSY; - - if ((hperh->state & ADC_STATE_NM_BUSY) == 0) - hperh->error_code = ADC_ERROR_NONE; - - __UNLOCK(hperh); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICHS | ADC_FLAG_ICH); ald_adc_interrupt_config(hperh, ADC_IT_ICH, ENABLE); if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) @@ -752,23 +729,9 @@ ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - __LOCK(hperh); - - if (((hperh->state & ADC_STATE_NM_BUSY) == 0) - && (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))) { - ADC_DISABLE(hperh); - ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); - hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); - hperh->state |= ADC_STATE_READY; - } - else { - ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); - hperh->state |= ADC_STATE_ERROR; - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_I); + ADC_DISABLE(hperh); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); return OK; } @@ -776,35 +739,31 @@ ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh) * @brief Get ADC insert group conversion result. * @param hperh: Pointer to a adc_handle_t structure that contains * the configuration information for the specified ADC module. - * @param ih_rank: the converted ADC insert rank. - * This parameter can be one of the following values: - * @arg ADC_INJ_RANK_1: insert Channel1 selected - * @arg ADC_INJ_RANK_2: insert Channel2 selected - * @arg ADC_INJ_RANK_3: insert Channel3 selected - * @arg ADC_INJ_RANK_4: insert Channel4 selected + * @param idx: Index of converted ADC insert channel. * @retval ADC group insert conversion data */ -uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank) +uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t idx) { uint32_t tmp; assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_ICH_RANK_TYPE(ih_rank)); + assert_param(IS_ADC_ICH_IDX_TYPE(idx)); - switch (ih_rank) { - case ADC_ICH_RANK_1: + switch (idx) { + case ADC_ICH_IDX_1: tmp = hperh->perh->ICHDR1; break; - case ADC_ICH_RANK_2: + case ADC_ICH_IDX_2: tmp = hperh->perh->ICHDR2; break; - case ADC_ICH_RANK_3: + case ADC_ICH_IDX_3: tmp = hperh->perh->ICHDR3; break; - case ADC_ICH_RANK_4: + case ADC_ICH_IDX_4: tmp = hperh->perh->ICHDR4; break; default: + tmp = hperh->perh->ICHDR1; break; } @@ -822,58 +781,36 @@ void ald_adc_irq_handler(adc_handle_t *hperh) assert_param(IS_ADC_TYPE(hperh->perh)); if (ald_adc_get_it_status(hperh, ADC_IT_NCH) && ald_adc_get_flag_status(hperh, ADC_FLAG_NCH)) { - if ((hperh->state & ADC_STATE_ERROR) == 0) - hperh->state |= ADC_STATE_NM_EOC; + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); - if (hperh->init.cont_mode == DISABLE) { - ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); - hperh->state &= ~(ADC_STATE_NM_BUSY); - - if ((hperh->state & ADC_STATE_IST_BUSY) == 0) - hperh->state |= ADC_STATE_READY; - } - - if (hperh->adc_reg_cplt_cbk != NULL) - hperh->adc_reg_cplt_cbk(hperh); - - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); + if (hperh->normal_cplt_cbk) + hperh->normal_cplt_cbk(hperh); } if (ald_adc_get_it_status(hperh, ADC_IT_ICH) && ald_adc_get_flag_status(hperh, ADC_FLAG_ICH)) { - if ((hperh->state & ADC_STATE_ERROR) == 0) - hperh->state |= ADC_STATE_IST_EOC; + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICH | ADC_FLAG_ICHS); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_I); - if ((!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) && (hperh->init.cont_mode == DISABLE)) { - ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); - hperh->state &= ~(ADC_STATE_IST_BUSY); - - if ((hperh->state & ADC_STATE_NM_BUSY) == 0) - hperh->state |= ADC_STATE_READY; - } - if (hperh->adc_inj_cplt_cbk != NULL) - hperh->adc_inj_cplt_cbk(hperh); - - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); - ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + if (hperh->insert_cplt_cbk) + hperh->insert_cplt_cbk(hperh); } if (ald_adc_get_it_status(hperh, ADC_IT_AWD) && ald_adc_get_flag_status(hperh, ADC_FLAG_AWD)) { - hperh->state |= ADC_STATE_AWD; - - if (hperh->adc_out_of_win_cbk != NULL) - hperh->adc_out_of_win_cbk(hperh); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_WDG); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_AWD); - ald_adc_clear_flag_status(hperh, ADC_FLAG_AWD); + if (hperh->wdg_cbk) + hperh->wdg_cbk(hperh); } if (ald_adc_get_it_status(hperh, ADC_IT_OVR) && ald_adc_get_flag_status(hperh, ADC_FLAG_OVR)) { - ald_adc_clear_flag_status(hperh, ADC_FLAG_OVR); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_OVR); hperh->error_code |= ADC_ERROR_OVR; hperh->state |= ADC_STATE_ERROR; - if (hperh->adc_ovr_cbk != NULL) - hperh->adc_ovr_cbk(hperh); + if (hperh->ovr_cbk) + hperh->ovr_cbk(hperh); } } @@ -897,43 +834,40 @@ void ald_adc_irq_handler(adc_handle_t *hperh) ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config) { assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); - assert_param(IS_ADC_NCH_RANK_TYPE(config->rank)); - assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp_time)); + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + assert_param(IS_ADC_NCH_IDX_TYPE(config->idx)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp)); - __LOCK(hperh); - - if (config->rank <= ADC_NCH_RANK_4 ) { - hperh->perh->NCHS1 &= ~(0x1f << ((config->rank - 1) << 3)); - hperh->perh->NCHS1 |= (config->channel << ((config->rank - 1) << 3)); + if (config->idx <= ADC_NCH_IDX_4 ) { + hperh->perh->NCHS1 &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); + hperh->perh->NCHS1 |= (config->ch << (uint32_t)((config->idx - 1) << 3)); } - else if (config->rank <= ADC_NCH_RANK_8) { - hperh->perh->NCHS2 &= ~(0x1f << ((config->rank - 5) << 3)); - hperh->perh->NCHS2 |= (config->channel << ((config->rank - 5) << 3)); + else if (config->idx <= ADC_NCH_IDX_8) { + hperh->perh->NCHS2 &= ~(0x1f << (uint32_t)((config->idx - 5) << 3)); + hperh->perh->NCHS2 |= (config->ch << (uint32_t)((config->idx - 5) << 3)); } - else if (config->rank <= ADC_NCH_RANK_12) { - hperh->perh->NCHS3 &= ~(0x1f << ((config->rank - 9) << 3)); - hperh->perh->NCHS3 |= (config->channel << ((config->rank - 9) << 3)); + else if (config->idx <= ADC_NCH_IDX_12) { + hperh->perh->NCHS3 &= ~(0x1f << (uint32_t)((config->idx - 9) << 3)); + hperh->perh->NCHS3 |= (config->ch << (uint32_t)((config->idx - 9) << 3)); } else { - hperh->perh->NCHS4 &= ~(0x1f << ((config->rank - 13) << 3)); - hperh->perh->NCHS4 |= (config->channel << ((config->rank - 13) << 3)); + hperh->perh->NCHS4 &= ~(0x1f << (uint32_t)((config->idx - 13) << 3)); + hperh->perh->NCHS4 |= (config->ch << (uint32_t)((config->idx - 13) << 3)); } - if (config->channel < 8) { - hperh->perh->SMPT1 &= ~(0x0f << (config->channel << 2)); - hperh->perh->SMPT1 |= config->samp_time << (config->channel << 2); + if (config->ch < 8) { + hperh->perh->SMPT1 &= ~(0x0f << (uint32_t)(config->ch << 2)); + hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 2); } - else if (config->channel < 16) { - hperh->perh->SMPT2 &= ~(0x0f << ((config->channel - 8) << 2)); - hperh->perh->SMPT2 |= config->samp_time << ((config->channel - 8) << 2); + else if (config->ch < 16) { + hperh->perh->SMPT2 &= ~(0x0f << (uint32_t)((config->ch - 8) << 2)); + hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - 8) << 2); } else { - hperh->perh->SMPT3 &= ~(0x0f << ((config->channel - 16) << 2)); - hperh->perh->SMPT3 |= config->samp_time << ((config->channel - 16) << 2); + hperh->perh->SMPT3 &= ~(0x0f << (uint32_t)((config->ch - 16) << 2)); + hperh->perh->SMPT3 |= config->samp << (uint32_t)((config->ch - 16) << 2); } - __UNLOCK(hperh); return OK; } @@ -947,62 +881,27 @@ ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t * */ ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config) { - uint8_t tmp1, tmp2; ald_status_t tmp_status = OK; assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); - assert_param(IS_ADC_ICH_RANK_TYPE(config->rank)); - assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp_time)); + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + assert_param(IS_ADC_ICH_IDX_TYPE(config->idx)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp)); assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset)); - assert_param(IS_ADC_NBR_OF_IST_TYPE(config->ich_len)); - - __LOCK(hperh); - - if (hperh->init.scan_mode == DISABLE) { - switch (config->rank) { - case ADC_ICH_RANK_1: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS1_MSK, config->channel << ADC_ICHS_IS1_POSS); - break; - case ADC_ICH_RANK_2: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS2_MSK, config->channel << ADC_ICHS_IS2_POSS); - break; - case ADC_ICH_RANK_3: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS3_MSK, config->channel << ADC_ICHS_IS3_POSS); - break; - case ADC_ICH_RANK_4: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS4_MSK, config->channel << ADC_ICHS_IS4_POSS); - break; - default: - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_INTERNAL; - tmp_status = ERROR; - break; - } - } - else { - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->ich_len << ADC_CHSL_ISL_POSS); - tmp1 = config->rank ; - tmp2 = config->ich_len; - - if (tmp1 <= tmp2) { - hperh->perh->ICHS &= ~(0x1f << ((tmp1 - 1) << 3)); - hperh->perh->ICHS |= config->channel - << ((tmp1 - 1) << 3); - } - else { - hperh->perh->ICHS &= ~(0x1f << ((tmp1 - 1) << 3)); - hperh->perh->ICHS |= config->channel - << ((tmp1 - 1) << 3); - } - } + assert_param(IS_ADC_ICH_NR_TYPE(config->nr)); + assert_param(IS_FUNC_STATE(config->auto_m)); + + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nr << ADC_CHSL_ISL_POSS); + hperh->perh->ICHS &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); + hperh->perh->ICHS |= config->ch << (uint32_t)((config->idx - 1) << 3); - if (config->auto_inj == ENABLE) + if (config->auto_m == ENABLE) SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); + else + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); - if (hperh->init.disc_mode == ADC_ICH_DISC_EN) { - if (config->auto_inj == DISABLE) { - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->ich_len << ADC_CHSL_ISL_POSS); + if (hperh->init.disc == ADC_ICH_DISC_EN) { + if (config->auto_m == DISABLE) { SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); } else { @@ -1012,37 +911,36 @@ ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t * } } - if (config->channel < 8) { - hperh->perh->SMPT1 &= ~(0x03 << (config->channel << 2)); - hperh->perh->SMPT1 |= config->samp_time << (config->channel << 2); + if (config->ch < 8) { + hperh->perh->SMPT1 &= ~(0x0f << (uint32_t)(config->ch << 2)); + hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 2); } - else if (config->channel < 16) { - hperh->perh->SMPT2 &= ~(0x03 << ((config->channel - 8) << 2)); - hperh->perh->SMPT2 |= config->samp_time << ((config->channel - 8) << 2); + else if (config->ch < 16) { + hperh->perh->SMPT2 &= ~(0x0f << (uint32_t)((config->ch - 8) << 2)); + hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - 8) << 2); } else { - hperh->perh->SMPT3 &= ~(0x03 << ((config->channel - 16) << 2)); - hperh->perh->SMPT3 |= config->samp_time << ((config->channel - 16) << 2); + hperh->perh->SMPT3 &= ~(0x0f << (uint32_t)((config->ch - 16) << 2)); + hperh->perh->SMPT3 |= config->samp << (uint32_t)((config->ch - 16) << 2); } - switch (config->rank) { - case ADC_ICH_RANK_1: + switch (config->idx) { + case ADC_ICH_IDX_1: hperh->perh->ICHOFF1 = config->offset; break; - case ADC_ICH_RANK_2: + case ADC_ICH_IDX_2: hperh->perh->ICHOFF2 = config->offset; break; - case ADC_ICH_RANK_3: + case ADC_ICH_IDX_3: hperh->perh->ICHOFF3 = config->offset; break; - case ADC_ICH_RANK_4: + case ADC_ICH_IDX_4: hperh->perh->ICHOFF4 = config->offset; break; default: break; } - __UNLOCK(hperh); return tmp_status; } @@ -1055,21 +953,18 @@ ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t * */ ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config) { - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->watchdog_mode)); - assert_param(IS_FUNC_STATE(config->it_mode)); - assert_param(IS_HTR_TYPE(config->high_threshold)); - assert_param(IS_LTR_TYPE(config->low_threshold)); - - __LOCK(hperh); + assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->mode)); + assert_param(IS_FUNC_STATE(config->interrupt)); + assert_param(IS_HTR_TYPE(config->high_thrd)); + assert_param(IS_LTR_TYPE(config->low_thrd)); - if ((config->watchdog_mode == ADC_ANAWTD_SING_NM) - || (config->watchdog_mode == ADC_ANAWTD_SING_IST) - || (config->watchdog_mode == ADC_ANAWTD_SING_NMIST)) - assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); + if ((config->mode == ADC_ANAWTD_SING_NM) + || (config->mode == ADC_ANAWTD_SING_IST) + || (config->mode == ADC_ANAWTD_SING_NMIST)) + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); - if (config->it_mode == DISABLE) + if (config->interrupt == DISABLE) ald_adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE); else ald_adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE); @@ -1077,15 +972,15 @@ ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_ CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK); CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK); CLEAR_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK); - hperh->perh->CON0 |= config->watchdog_mode; + hperh->perh->CON0 |= config->mode; if (READ_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK)) - MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->channel << ADC_CON0_AWDCH_POSS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->ch << ADC_CON0_AWDCH_POSS); - WRITE_REG(hperh->perh->WDTL, config->low_threshold); - WRITE_REG(hperh->perh->WDTH, config->high_threshold); + WRITE_REG(hperh->perh->WDTL, config->low_thrd); + WRITE_REG(hperh->perh->WDTH, config->high_thrd); + SET_BIT(hperh->state, ADC_STATE_BUSY_WDG); - __UNLOCK(hperh); return OK; } @@ -1219,8 +1114,10 @@ static void adc_dma_normal_conv_cplt(void *arg) { adc_handle_t *hperh = (adc_handle_t *)arg; - if (hperh->adc_reg_cplt_cbk != NULL) - hperh->adc_reg_cplt_cbk(hperh); + CLEAR_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK); + + if (hperh->normal_cplt_cbk) + hperh->normal_cplt_cbk(hperh); } @@ -1235,8 +1132,8 @@ static void adc_dma_error(void *arg) hperh->state |= ADC_STATE_ERROR; hperh->error_code |= ADC_ERROR_DMA; - if (hperh->adc_error_cbk != NULL) - hperh->adc_error_cbk(hperh); + if (hperh->error_cbk) + hperh->error_cbk(hperh); } #endif /** diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c index f050818ee4bd4dc9c555ecf72cd975fd53b8c6dc..c0a5e86f8a22f54265aa06e68cb810246f542ed1 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c @@ -40,8 +40,9 @@ ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) ald_bkpc_ldo_config() API can configure LDO in backup field. - (+) ald_bkpc_bor_config() API can configure BOR in backup field. + (+) ald_bkpc_standby_wakeup_config() API can configure STANDBY wakeup. + (+) ald_bkpc_rtc_clock_config() API can configure RTC clock. + (+) ald_bkpc_tsense_clock_config() API can configure Tsense clock. @endverbatim * @{ @@ -58,8 +59,16 @@ void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t assert_param(IS_BKPC_WAKEUP_PORT(port)); assert_param(IS_BKPC_WAKEUP_LEVEL(level)); + if (port == PMU_STANDBY_PORT_SEL_NONE) { + BKPC_UNLOCK(); + CLEAR_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK); + SET_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK); + BKPC_LOCK(); + return; + } + BKPC_UNLOCK(); - SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK); + SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK | BKPC_CR_MRST_WKPEN_MSK); MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS); MODIFY_REG(BKPC->CR, BKPC_CR_WKPOL_MSK, level << BKPC_CR_WKPOL_POS); BKPC_LOCK(); diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c index e656bbdd7cbe955547940787825ebaa82e15e0fb..7a00c641fb32f6cdd3d020a797c1475091a0716c 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c @@ -36,8 +36,6 @@ ============================================================================== [..] This section provides functions allowing to: (+) Square root operation. - (+) Division. - (+) Get DZ flag. @endverbatim * @{ @@ -45,7 +43,7 @@ /** * @brief Square root operation. - * @param data: The data; + * @param data: The radicand. * @retval The value of square root. */ uint32_t ald_calc_sqrt(uint32_t data) @@ -55,59 +53,6 @@ uint32_t ald_calc_sqrt(uint32_t data) return READ_REG(CALC->SQRTRES); } - -/** - * @brief Calculating division. - * @param dividend: The value of the dividend. - * @param divisor: The value of the divisor. - * @param remainder: The value of the remainder. - * @retval The result of division. - */ -uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder) -{ - CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); - SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); - WRITE_REG(CALC->DIVDR, dividend); - WRITE_REG(CALC->DIVSR, divisor); - - while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); - - *remainder = READ_REG(CALC->DIVRR); - return READ_REG(CALC->DIVQR); -} - -/** - * @brief Calculating division. - * @param dividend: The value of the dividend. - * @param divisor: The value of the divisor. - * @param remainder: The value of the remainder. - * @retval The result of division. - */ -int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder) -{ - SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); - SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); - WRITE_REG(CALC->DIVDR, dividend); - WRITE_REG(CALC->DIVSR, divisor); - - while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); - - *remainder = READ_REG(CALC->DIVRR); - return READ_REG(CALC->DIVQR); -} - -/** - * @brief Get the flag of divisor is zero. - * @retval The status, SET/RESET. - */ -flag_status_t ald_calc_get_dz_status(void) -{ - if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK)) - return SET; - - return RESET; -} - /** * @} */ @@ -115,7 +60,6 @@ flag_status_t ald_calc_get_dz_status(void) /** * @} */ - /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c index 123d3719d565d5f502624879d673037c675ec27a..24cabd8cef37d5a8c373aedf202059e0282b97b9 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c @@ -84,7 +84,7 @@ */ static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num); static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err); -static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num); +static ald_status_t __can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num); /** * @} */ @@ -200,10 +200,8 @@ ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config) assert_param(IS_CAN_FILTER_SCALE(config->scale)); assert_param(IS_CAN_FILTER_FIFO(config->fifo)); assert_param(IS_FUNC_STATE(config->active)); - assert_param(IS_CAN_BANKNUMBER(config->bank_number)); pos = 1 << config->number; - SET_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK); CLEAR_BIT(hperh->perh->FLTGO, pos); @@ -355,7 +353,7 @@ ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg) assert_param(IS_CAN_RTR(msg->rtr)); assert_param(IS_CAN_DATA_LEN(msg->len)); - if ((hperh->state != CAN_STATE_READY) && (hperh->state != CAN_STATE_BUSY_RX)) + if ((hperh->state & CAN_STATE_TX_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY)) return BUSY; if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) @@ -416,9 +414,10 @@ ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t * assert_param(IS_CAN_ALL(hperh->perh)); assert_param(IS_CAN_FIFO(num)); + assert_param(msg != NULL); __LOCK(hperh); - SET_BIT(hperh->state, CAN_STATE_RX_MASK); + SET_BIT(hperh->state, num == CAN_RX_FIFO0 ? CAN_STATE_RX0_MASK : CAN_STATE_RX1_MASK); tick = ald_get_tick(); while (CAN_RX_MSG_PENDING(hperh, num) == 0) { @@ -451,7 +450,7 @@ ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t * msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF; can_rx_fifo_release(hperh, num); - CLEAR_BIT(hperh->state, CAN_STATE_RX_MASK); + CLEAR_BIT(hperh->state, num == CAN_RX_FIFO0 ? CAN_STATE_RX0_MASK : CAN_STATE_RX1_MASK); __UNLOCK(hperh); return OK; @@ -468,12 +467,22 @@ ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_m { assert_param(IS_CAN_ALL(hperh->perh)); assert_param(IS_CAN_FIFO(num)); + assert_param(msg != NULL); - if ((hperh->state != CAN_STATE_READY) && (hperh->state != CAN_STATE_BUSY_TX)) - return BUSY; + if (num == CAN_RX_FIFO0) { + if ((hperh->state & CAN_STATE_RX0_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY)) + return BUSY; + + SET_BIT(hperh->state, CAN_STATE_RX0_MASK); + hperh->rx0_msg = msg; + } + else { + if ((hperh->state & CAN_STATE_RX1_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY)) + return BUSY; - SET_BIT(hperh->state, CAN_STATE_RX_MASK); - hperh->rx_msg = msg; + SET_BIT(hperh->state, CAN_STATE_RX1_MASK); + hperh->rx1_msg = msg; + } ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE); ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE); @@ -857,8 +866,8 @@ flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag) */ void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag) { - uint32_t idx = (flag >> 20) & 0x7; - uint32_t _flag = flag & 0xFF8FFFFF; + uint32_t idx = ((uint32_t)flag >> 20) & 0x7; + uint32_t _flag = flag & 0xFF8FFFFFU; assert_param(IS_CAN_CLEAR_FLAG(flag)); @@ -978,47 +987,91 @@ static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err) return OK; } +/** + * @brief Check whether the data in the mailbox is contaminated. + * @param hperh: Pointer to a can_handle_t structure. + * @param num: Specify the FIFO number + * @retval status: + * - 0: Data is valid + * - 1: Data is invalid + */ +static int __can_rx_check(can_handle_t *hperh, can_rx_fifo_t num) +{ + int i; + + if (!(hperh->perh->RESERVED0[0] & 0x200000U)) + return 0; + + if (num == CAN_RX_FIFO0) { + for (i = 0; i < 3; ++i) { + if (hperh->perh->RXF0 & 0x3) + SET_BIT(hperh->perh->RXF0, CAN_RXF0_FREE_MSK); + else + break; + } + } + else { + for (i = 0; i < 3; ++i) { + if (hperh->perh->RXF1 & 0x3) + SET_BIT(hperh->perh->RXF1, CAN_RXF1_FREE_MSK); + else + break; + } + } + + hperh->perh->RESERVED0[0] |= 0x200000U; + return 1; +} + /** * @brief Receives a correct CAN frame using interrupt. * @param hperh: Pointer to a can_handle_t structure. * @param num: Specify the FIFO number * @retval Status, see ald_status_t. */ -static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num) +static ald_status_t __can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num) { uint32_t stid, exid; + can_rx_msg_t *_msg; + + if (__can_rx_check(hperh, num)) + return ERROR; stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS); exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS); - hperh->rx_msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS); - if (hperh->rx_msg->type == CAN_ID_STD) - hperh->rx_msg->std = stid; + _msg = num == CAN_RX_FIFO0 ? hperh->rx0_msg : hperh->rx1_msg; + _msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS); + + if (_msg->type == CAN_ID_STD) + _msg->std = stid; else - hperh->rx_msg->ext = (stid << 18) | exid; - - hperh->rx_msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS); - hperh->rx_msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS); - hperh->rx_msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS); - hperh->rx_msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF; - hperh->rx_msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF; - hperh->rx_msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF; - hperh->rx_msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF; - hperh->rx_msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF; - hperh->rx_msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF; - hperh->rx_msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF; - hperh->rx_msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF; + _msg->ext = (stid << 18) | exid; + + _msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS); + _msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS); + _msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS); + _msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF; + _msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF; + _msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF; + _msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF; + _msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF; + _msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF; + _msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF; + _msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF; if (num == CAN_RX_FIFO0) { can_rx_fifo_release(hperh, CAN_RX_FIFO0); ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE); + CLEAR_BIT(hperh->state, CAN_STATE_RX0_MASK); } else { can_rx_fifo_release(hperh, CAN_RX_FIFO1); ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE); + CLEAR_BIT(hperh->state, CAN_STATE_RX1_MASK); } - if (hperh->state == CAN_STATE_BUSY_RX) { + if (hperh->state == CAN_STATE_READY) { ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE); ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE); ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); @@ -1026,10 +1079,8 @@ static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num) ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); } - CLEAR_BIT(hperh->state, CAN_STATE_RX_MASK); - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); + hperh->rx_cplt_cbk(hperh, num); return OK; } diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c index 0ae8b42619cb32674cbd79832855449e0126ec6b..76c6e516be810ca383ee999244f9b9a8cee10d06 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c @@ -125,6 +125,7 @@ */ #include "ald_cmu.h" +#include "ald_flash.h" /** @addtogroup ES32FXXX_ALD @@ -140,7 +141,7 @@ * @defgroup CMU_Private_Variables CMU Private Variables * @{ */ -uint32_t __system_clock = 24000000; +uint32_t __system_clock = 24000000U; /** * @} */ @@ -383,6 +384,7 @@ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock) break; case CMU_CLOCK_PLL1: + for (cnt = 0; cnt < 5000; ++cnt); MODIFY_REG(CMU->CSR, CMU_CSR_CFT_CMD_MSK, 0xAA << CMU_CSR_CFT_CMD_POSS); MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS); while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); @@ -409,7 +411,7 @@ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock) if (clock == 72000000) { ald_cmu_div_config(CMU_PCLK_2, CMU_DIV_4); } - if (clock == 48000000) { + if ((clock == 48000000) || (clock == 36000000)) { ald_cmu_div_config(CMU_PCLK_2, CMU_DIV_2); } @@ -595,6 +597,18 @@ uint32_t ald_cmu_get_hclk1_clock(void) return (__system_clock >> sys_div) >> ahb_div; } +/** + * @brief Get AHB2 clock. + * @retval The value of AHB2 clock. + */ +uint32_t ald_cmu_get_hclk2_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK2DIV_MSK, CMU_CFGR_HCLK2DIV_POSS); + + return (__system_clock >> sys_div) >> ahb_div; +} + /** * @brief Get SYS clock * @retval The value of SYS clock @@ -742,6 +756,25 @@ void ald_cmu_pll_safe_config(type_func_t status) return; } +/** + * @brief Get current clock source. + * @param type: Type of source: HOSC/LOSC/PLL. + * @retval Status: + * - 0: Current clock is HOSC, LOSC or PLL + * - 1: Current clock is HRC, LRC or HRC + */ +uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type) +{ + assert_param(IS_CMU_SAFE_CLOCK_TYPE(type)); + + if (type == CMU_SAFE_CLK_HOSC) + return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK, CMU_HOSMCR_CLKS_POS); + else if (type == CMU_SAFE_CLK_LOSC) + return READ_BITS(CMU->LOSMCR, CMU_LOSMCR_CLKS_MSK, CMU_LOSMCR_CLKS_POS); + else + return READ_BITS(CMU->PULMCR, CMU_PULMCR_CLKS_MSK, CMU_PULMCR_CLKS_POS); +} + /** * @brief Get clock state. * @param sr: The state type, see @ref cmu_clock_state_t. @@ -1016,6 +1049,12 @@ void ald_cmu_usb_clock_config(cmu_usb_clock_sel_t clock, cmu_usb_div_t div) assert_param(IS_CMU_USB_DIV(div)); SYSCFG_UNLOCK(); + + if (clock == CMU_USB_CLOCK_SEL_HRC) + SET_BIT(SYSCFG->USBCFG, SYSCFG_USBCFG_CLKRDYBP_MSK); + else + CLEAR_BIT(SYSCFG->USBCFG, SYSCFG_USBCFG_CLKRDYBP_MSK); + MODIFY_REG(CMU->PERICR, CMU_PERICR_USBPHYCS_MSK, clock << CMU_PERICR_USBPHYCS_POSS); MODIFY_REG(CMU->PERIDIVR, CMU_PERIDIVR_USBPHYDIV_MSK, div << CMU_PERIDIVR_USBPHYDIV_POSS); SYSCFG_LOCK(); diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c index 65fd6ce7d4e439a3ce0413d02c747d0008429c7c..4d17afca3bd54fe62c36304aa203bf9609b35f27 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c @@ -145,11 +145,10 @@ ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t * key, crypt_ke uint32_t *temp = key; uint32_t i; - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; - if ((hperh == NULL) || (key == NULL)) return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; assert_param(IS_CRYPT(hperh->perh)); assert_param(IS_CRYPT_KEY_LEN(len)); @@ -161,14 +160,29 @@ ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t * key, crypt_ke case KEY_8_LEN: hperh->perh->KEY[7] = *temp++; hperh->perh->KEY[6] = *temp++; + hperh->perh->KEY[5] = *temp++; + hperh->perh->KEY[4] = *temp++; + hperh->perh->KEY[3] = *temp++; + hperh->perh->KEY[2] = *temp++; + hperh->perh->KEY[1] = *temp++; + hperh->perh->KEY[0] = *temp; + break; case KEY_6_LEN: hperh->perh->KEY[5] = *temp++; hperh->perh->KEY[4] = *temp++; + hperh->perh->KEY[3] = *temp++; + hperh->perh->KEY[2] = *temp++; + hperh->perh->KEY[1] = *temp++; + hperh->perh->KEY[0] = *temp; + break; case KEY_4_LEN: hperh->perh->KEY[3] = *temp++; hperh->perh->KEY[2] = *temp++; + hperh->perh->KEY[1] = *temp++; + hperh->perh->KEY[0] = *temp; + break; case KEY_2_LEN: hperh->perh->KEY[1] = *temp++; @@ -199,11 +213,10 @@ ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t * key, crypt_key { uint32_t *temp = key; - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; - if ((hperh == NULL) || (key == NULL)) return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; assert_param(IS_CRYPT(hperh->perh)); assert_param(IS_CRYPT_KEY_LEN(len)); @@ -212,18 +225,33 @@ ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t * key, crypt_key case KEY_8_LEN: *temp++ = hperh->perh->KEY[7]; *temp++ = hperh->perh->KEY[6]; + *temp++ = hperh->perh->KEY[5]; + *temp++ = hperh->perh->KEY[4]; + *temp++ = hperh->perh->KEY[3]; + *temp++ = hperh->perh->KEY[2]; + *temp++ = hperh->perh->KEY[1]; + *temp = hperh->perh->KEY[0]; + break; case KEY_6_LEN: *temp++ = hperh->perh->KEY[5]; *temp++ = hperh->perh->KEY[4]; + *temp++ = hperh->perh->KEY[3]; + *temp++ = hperh->perh->KEY[2]; + *temp++ = hperh->perh->KEY[1]; + *temp = hperh->perh->KEY[0]; + break; case KEY_4_LEN: *temp++ = hperh->perh->KEY[3]; *temp++ = hperh->perh->KEY[2]; + *temp++ = hperh->perh->KEY[1]; + *temp = hperh->perh->KEY[0]; + break; case KEY_2_LEN: *temp++ = hperh->perh->KEY[1]; - *temp = hperh->perh->KEY[0]; + *temp = hperh->perh->KEY[0]; break; default: @@ -245,11 +273,11 @@ ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t * iv, crypt_ivr { uint32_t *temp = iv; uint32_t i; - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; if ((hperh == NULL) || (iv == NULL)) return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; assert_param(IS_CRYPT(hperh->perh)); assert_param(IS_CRYPT_IV_LEN(len)); @@ -258,6 +286,9 @@ ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t * iv, crypt_ivr case IV_4_LEN: hperh->perh->IV[3] = *temp++; hperh->perh->IV[2] = *temp++; + hperh->perh->IV[1] = *temp++; + hperh->perh->IV[0] = *temp; + break; case IV_2_LEN: hperh->perh->IV[1] = *temp++; @@ -289,11 +320,10 @@ ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_l { uint32_t *temp = iv; - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; - if ((hperh == NULL) || (iv == NULL)) return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; assert_param(IS_CRYPT(hperh->perh)); assert_param(IS_CRYPT_IV_LEN(len)); @@ -302,10 +332,13 @@ ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_l case IV_4_LEN: *temp++ = hperh->perh->IV[3]; *temp++ = hperh->perh->IV[2]; + *temp++ = hperh->perh->IV[1]; + *temp = hperh->perh->IV[0]; + break; case IV_2_LEN: *temp++ = hperh->perh->IV[1]; - *temp = hperh->perh->IV[0]; + *temp = hperh->perh->IV[0]; break; default: @@ -512,7 +545,7 @@ ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, u } len += 4; - CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS); + CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS); CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS); ald_crypt_encrypt(hperh, ecb, ecb, 16); @@ -538,7 +571,7 @@ ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, u */ tag_temp = (uint32_t *)tag; ald_crypt_init(hperh); - CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS); + CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS); CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS); ald_crypt_write_key(hperh, hperh->key, KEY_4_LEN); hperh->iv[3] = 1; diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c index 812dd11d65cee28b5b38562d008389a2f37cd410..a314e72b29fd7384840583b93e5104237bc907b8 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c @@ -107,7 +107,7 @@ static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config assert_param(IS_FUNC_STATE(p->primary)); assert_param(IS_FUNC_STATE(p->burst)); assert_param(IS_FUNC_STATE(p->high_prio)); - assert_param(IS_FUNC_STATE(p->iterrupt)); + assert_param(IS_FUNC_STATE(p->interrupt)); assert_param(IS_DMA_MSEL_TYPE(p->msel)); assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel)); assert_param(IS_DMA_CHANNEL(p->channel)); @@ -120,12 +120,12 @@ static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config if (p->src_inc == DMA_DATA_INC_NONE) descr->src = p->src; else - descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << p->data_width)); + descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << (uint32_t)p->src_inc)); if (p->dst_inc == DMA_DATA_INC_NONE) descr->dst = p->dst; else - descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << p->data_width)); + descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << (uint32_t)p->dst_inc)); descr->ctrl.cycle_ctrl = mode; descr->ctrl.next_useburst = 0; @@ -153,7 +153,7 @@ static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config else WRITE_REG(DMAx->CHPRCLR, (1 << p->channel)); - if (p->iterrupt) + if (p->interrupt) SET_BIT(DMAx->IER, (1 << p->channel)); else CLEAR_BIT(DMAx->IER, (1 << p->channel)); @@ -226,6 +226,10 @@ void ald_dma_irq_handler(void) (+) ald_dma_config_struct(): Configure dma_config_t structure using default parameter. + (+) ald_dma_config_sg_alt_desc(): Configure dma_descriptor_t + structure using specified parameter. This function used + in scatter-gather mode(memory or peripheral). + @endverbatim * @{ */ @@ -296,7 +300,44 @@ void ald_dma_config_struct(dma_config_t *p) p->primary = ENABLE; p->burst = DISABLE; p->high_prio = DISABLE; - p->iterrupt = ENABLE; + p->interrupt = ENABLE; + + return; +} + +/** + * @brief Configure dma_descriptor_t structure using specified parameter. + * @note This function used in scatter-gather mode(memory or peripheral). + * @param desc: Address of the alternate descriptor. + * @param config: Pointer to the dma_config_t structure. + * @param memory: Memory or peripheral scatter-gather. + * @retval None + */ +void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory) +{ + if ((desc == NULL) || (config == NULL)) + return; + + if (config->src_inc == DMA_DATA_INC_NONE) + desc->src = config->src; + else + desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width)); + + if (config->dst_inc == DMA_DATA_INC_NONE) + desc->dst = config->dst; + else + desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width)); + + desc->ctrl.cycle_ctrl = memory ? DMA_CYCLE_CTRL_MEM_SG_ALTERNATE : DMA_CYCLE_CTRL_PER_SG_ALTERNATE; + desc->ctrl.next_useburst = memory ? 0 : 1; + desc->ctrl.n_minus_1 = config->size - 1; + desc->ctrl.R_power = config->R_power; + desc->ctrl.src_prot_ctrl = 0; + desc->ctrl.dst_prot_ctrl = 0; + desc->ctrl.src_size = config->data_width; + desc->ctrl.src_inc = config->src_inc; + desc->ctrl.dst_size = config->data_width; + desc->ctrl.dst_inc = config->dst_inc; return; } @@ -324,6 +365,7 @@ void ald_dma_config_struct(dma_config_t *p) (++) ald_dma_config_auto_easy(): Configure DMA channel according to the specified parameter. If you want use the dma easily, you can invoke this function. + (++) ald_dma_config_sg_mem(): Carry data used scatter-gather mode. (+) Carry data from peripheral to memory or from memory to peripheral, this mode APIs are: (++) ald_dma_config_basic(): Configure DMA channel according to @@ -332,6 +374,8 @@ void ald_dma_config_struct(dma_config_t *p) (++) ald_dma_config_basic_easy(): Configure DMA channel according to the specified parameter. If you want use the dma easily, you can invoke this function. + (++) ald_dma_ping_pong(): Carry data used ping-pong mode. + (++) ald_dma_config_sg_per(): Carry data used scatter-gather mode. @endverbatim * @{ @@ -383,14 +427,14 @@ void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t si if (hperh->config.src_inc == DMA_DATA_INC_NONE) descr->src = src; else - descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width)); + descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width)); } if (dst) { if (hperh->config.dst_inc == DMA_DATA_INC_NONE) descr->dst = dst; else - descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width)); + descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width)); } ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); @@ -489,14 +533,14 @@ void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t s if (hperh->config.src_inc == DMA_DATA_INC_NONE) descr->src = src; else - descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width)); + descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width)); } if (dst) { if (hperh->config.dst_inc == DMA_DATA_INC_NONE) descr->dst = dst; else - descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width)); + descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width)); } ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); @@ -556,6 +600,214 @@ void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t return; } +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is ping-pong. + * @note The ping-pong mode does not support memory to memory. + * @param DMAx: Pointer to DMA peripheral. + * @param config: Pointer to the dma_config_t structure which contains + * the specified parameters. + * @param first: Whether it is the first transmission. 1-first, 0-not first. + * @param cbk: DMA complete callback function. + * @retval None + */ +void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config, + uint8_t first, void (*cbk)(void *arg)) +{ + dma_descriptor_t *desc; + + assert_param(IS_DMA(DMAx)); + assert_param(config->src != NULL); + assert_param(config->dst != NULL); + assert_param(IS_DMA_DATA_SIZE(config->size)); + assert_param(IS_DMA_DATASIZE_TYPE(config->data_width)); + assert_param(IS_DMA_DATAINC_TYPE(config->src_inc)); + assert_param(IS_DMA_DATAINC_TYPE(config->dst_inc)); + assert_param(IS_DMA_ARBITERCONFIG_TYPE(config->R_power)); + assert_param(IS_FUNC_STATE(config->primary)); + assert_param(IS_FUNC_STATE(config->burst)); + assert_param(IS_FUNC_STATE(config->high_prio)); + assert_param(IS_FUNC_STATE(config->interrupt)); + assert_param(IS_DMA_MSEL_TYPE(config->msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(config->msigsel)); + assert_param(IS_DMA_CHANNEL(config->channel)); + + dma0_cbk[config->channel].cplt_cbk = cbk; + dma0_cbk[config->channel].err_cbk = NULL; + dma0_cbk[config->channel].cplt_arg = NULL; + dma0_cbk[config->channel].err_arg = NULL; + + if (config->primary) + desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + config->channel; + else + desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + config->channel; + + if (config->src_inc == DMA_DATA_INC_NONE) + desc->src = config->src; + else + desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width)); + + if (config->dst_inc == DMA_DATA_INC_NONE) + desc->dst = config->dst; + else + desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width)); + + desc->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PINGPONG; + desc->ctrl.next_useburst = 0; + desc->ctrl.n_minus_1 = config->size - 1; + desc->ctrl.R_power = config->R_power; + desc->ctrl.src_prot_ctrl = 0, + desc->ctrl.dst_prot_ctrl = 0, + desc->ctrl.src_size = config->data_width; + desc->ctrl.src_inc = config->src_inc; + desc->ctrl.dst_size = config->data_width; + desc->ctrl.dst_inc = config->dst_inc; + + if (!first) + return; + + if (config->primary) + WRITE_REG(DMAx->CHPRIALTCLR, (1 << config->channel)); + else + WRITE_REG(DMAx->CHPRIALTSET, (1 << config->channel)); + + if (config->burst) + WRITE_REG(DMAx->CHUSEBURSTSET, (1 << config->channel)); + else + WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << config->channel)); + + if (config->high_prio) + WRITE_REG(DMAx->CHPRSET, (1 << config->channel)); + else + WRITE_REG(DMAx->CHPRCLR, (1 << config->channel)); + + if (config->interrupt) + SET_BIT(DMAx->IER, (1 << config->channel)); + else + CLEAR_BIT(DMAx->IER, (1 << config->channel)); + + MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSEL_MSK, config->msel << DMA_CH0_SELCON_MSEL_POSS); + MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSIGSEL_MSK, config->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); + + WRITE_REG(DMAx->ICFR, (1 << config->channel)); + WRITE_REG(DMAx->CHENSET, (1 << config->channel)); + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is memory scatter-gather. + * @param DMAx: Pointer to DMA peripheral. + * @param desc: Pointer to first alternate descriptor. + * @param nr: Number of the alternate descriptor. + * @param channel: Channel index which will be used. + * @param cbk: DMA complete callback function. + * @retval None + */ +void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, + uint8_t channel, void (*cbk)(void *arg)) +{ + dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_CHANNEL(channel)); + + if ((desc == NULL) || (nr == 0)) + return; + + dma0_cbk[channel].cplt_cbk = cbk; + dma0_cbk[channel].err_cbk = NULL; + dma0_cbk[channel].cplt_arg = NULL; + dma0_cbk[channel].err_arg = NULL; + + tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD)); + tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD)); + tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_MEM_SG_PRIMARY; + tmp->ctrl.next_useburst = 0; + tmp->ctrl.n_minus_1 = (nr << 2) - 1; + tmp->ctrl.R_power = DMA_R_POWER_4; + tmp->ctrl.src_prot_ctrl = 0, + tmp->ctrl.dst_prot_ctrl = 0, + tmp->ctrl.src_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.src_inc = DMA_DATA_INC_WORD; + tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.dst_inc = DMA_DATA_INC_WORD; + + desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; + WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel)); + WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << channel)); + WRITE_REG(DMAx->CHPRCLR, (1 << channel)); + + WRITE_REG(DMAx->ICFR, (1 << channel)); + SET_BIT(DMAx->IER, (1 << channel)); + WRITE_REG(DMAx->CHENSET, (1 << channel)); + SET_BIT(DMAx->CHSWREQ, (1 << channel)); + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is peripheral scatter-gather. + * @note The size of the first transmission must be 5. + * @param DMAx: Pointer to DMA peripheral. + * @param desc: Pointer to first alternate descriptor. + * @param nr: Number of the alternate descriptor. + * @param burst: 1-Enable burst, 0-Disable burst. + * @param msel: Input source to DMA channel @ref dma_msel_t + * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t + * @param channel: Channel index which will be used. + * @param cbk: DMA complete callback function. + * @retval None + */ +void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, + dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) +{ + dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_MSEL_TYPE(msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(msigsel)); + assert_param(IS_DMA_CHANNEL(channel)); + + if ((desc == NULL) || (nr == 0)) + return; + + dma0_cbk[channel].cplt_cbk = cbk; + dma0_cbk[channel].err_cbk = NULL; + dma0_cbk[channel].cplt_arg = NULL; + dma0_cbk[channel].err_arg = NULL; + + tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD)); + tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD)); + tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PER_SG_PRIMARY; + tmp->ctrl.next_useburst = 0; + tmp->ctrl.n_minus_1 = (nr << 2) - 1; + tmp->ctrl.R_power = DMA_R_POWER_4; + tmp->ctrl.src_prot_ctrl = 0, + tmp->ctrl.dst_prot_ctrl = 0, + tmp->ctrl.src_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.src_inc = DMA_DATA_INC_WORD; + tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.dst_inc = DMA_DATA_INC_WORD; + + desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; + WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel)); + burst ? (DMAx->CHUSEBURSTSET = (1 << channel)) : (DMAx->CHUSEBURSTCLR, (1 << channel)); + WRITE_REG(DMAx->CHPRCLR, (1 << channel)); + + MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSEL_MSK, msel << DMA_CH0_SELCON_MSEL_POSS); + MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSIGSEL_MSK, msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); + + WRITE_REG(DMAx->ICFR, (1 << channel)); + SET_BIT(DMAx->IER, (1 << channel)); + WRITE_REG(DMAx->CHENSET, (1 << channel)); + + return; +} /** * @} */ @@ -706,6 +958,36 @@ void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel) return; } +/** + * @brief Get the completion status of the descriptor + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index + * @retval Completion status: + * - DMA_DESCP_CPLT_PRI: Primary descriptor has been completed + * - DMA_DESCP_CPLT_ALT: Alternate descriptor has been completed + * - DMA_DESCP_CPLT_ALL: Both primary and alternate descriptors have been completed + */ +dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel) +{ + uint8_t pri, alt; + dma_descriptor_t *desc; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + pri = desc->ctrl.cycle_ctrl; + desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + alt = desc->ctrl.cycle_ctrl; + + if ((pri == 0) && (alt == 0)) + return DMA_DESCP_CPLT_ALL; + + if (pri == 0) + return DMA_DESCP_CPLT_PRI; + else + return DMA_DESCP_CPLT_ALT; +} /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c index c17ba16b7a578648d7af12a63bc3c28dfe8b5065..48c7fe022841495aefc25b59b5d00dfac9743750 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c @@ -167,7 +167,7 @@ end: */ __RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo) { - uint16_t i; + uint16_t i = 0; uint16_t prog_len; uint32_t *p_data = data; uint16_t op_cmd = OP_CMD; diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c index 845b02e5fb75cacb03bf7ca9e28361f7530ed3a4..0c8f94b3a2d525f19b90fefb541633aa6127bd6b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c @@ -212,7 +212,6 @@ ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) index2 = 0; index = FLASH_PAGE_ADDR(start_write_addr); - para = FLASH_PAGE_ADDR(start_write_addr) + FLASH_PAGE_SIZE; len_index = FLASH_PAGE_SIZE; } else { @@ -250,7 +249,7 @@ ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) */ ald_status_t ald_flash_erase(uint32_t addr, uint16_t len) { - int32_t index; + uint32_t index; int32_t para; int32_t start_erase_addr; int32_t end_erase_addr; diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c index 58e1481908d1e431fba21efe5c36c2665391668c..686bb601d2cbeae919e7f4aee97ff612ae604e8d 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c @@ -93,9 +93,9 @@ init.odos = GPIO_PUSH_PULL; init.pupd = GPIO_PUSH_UP; init.podrv = GPIO_OUT_DRIVE_6; - init.nodrv = GPIO_OUT_DRIVE_6; + init.nodrv = GPIO_OUT_DRIVE_6; init.flt = GPIO_FILTER_DISABLE; - init.type = GPIO_TYPE_TTL; + init.type = GPIO_TYPE_CMOS; init.func = GPIO_FUNC_1; (#) In case of external interrupt/event mode selection, user need invoke @@ -332,12 +332,12 @@ void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) /* Select external interrupt line */ if (i <= 7) { - EXTI->EXTIPSR0 &= ~(0x7 << (i * 4)); + EXTI->EXTIPSR0 &= ~(0x7U << (i * 4)); EXTI->EXTIPSR0 |= (port << (i * 4)); } else { i -= 8; - EXTI->EXTIPSR1 &= ~(0x7 << (i * 4)); + EXTI->EXTIPSR1 &= ~(0x7U << (i * 4)); EXTI->EXTIPSR1 |= (port << (i * 4)); } @@ -376,8 +376,6 @@ void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. * @param pin: Specifies the pin to read. * @retval The input pin value - * - BIT_SET - * - BIT_RESET */ uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) { @@ -385,10 +383,9 @@ uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) assert_param(IS_GPIO_PIN(pin)); if (READ_BIT(GPIOx->DIN, pin)) - return BIT_SET; - + return 1; else - return BIT_RESET; + return 0; } /** @@ -513,8 +510,6 @@ void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) WRITE_REG(GPIOx->DOUT, val); return; } - - /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c index e08fd09c8bc246fe8b2c387d2aef7d8b72ef6141..419bb25481df2bacd2af7a0d2feaf8abe2363682 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c @@ -513,6 +513,7 @@ ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); while (size > 0) { + while(hperh->perh->STAT & (0x1 << 1)); hperh->perh->TXDATA = (*buf++); size--; hperh->xfer_count++; @@ -690,6 +691,7 @@ ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint32_t size SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); for (i = 0; i < 16; i++) { + while(hperh->perh->STAT & (0x1 << 1)); hperh->perh->TXDATA = (*buf++); --size; hperh->xfer_count++; @@ -706,6 +708,7 @@ ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint32_t size goto ERROR; for (i = 0; i < 8; i++) { + while(hperh->perh->STAT & (0x1 << 1)); hperh->perh->TXDATA = (*buf++); --size; hperh->xfer_count++; @@ -1318,6 +1321,7 @@ ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t hperh->xfer_count += 2; while (size > 0) { + while(hperh->perh->STAT & (0x1 << 1)); hperh->perh->TXDATA = (*buf++); --size; hperh->xfer_count++; @@ -1543,6 +1547,7 @@ ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uin I2C_CLEAR_IT(hperh , I2C_IT_TC); I2C_CLEAR_IT(hperh , I2C_IT_TCR); + while(hperh->perh->STAT & (0x1 << 1)); hperh->perh->TXDATA = (*hperh->p_buff++); hperh->xfer_count++; @@ -2153,6 +2158,7 @@ static ald_status_t i2c_master_send_tc(i2c_handle_t *hperh) static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh) { if (hperh->xfer_count != hperh->xfer_size) { + while(hperh->perh->STAT & (0x1 << 1)); hperh->perh->TXDATA = (*hperh->p_buff++); hperh->xfer_count++; } @@ -2195,9 +2201,14 @@ static ald_status_t i2c_master_recv_tc(i2c_handle_t *hperh) */ static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh) { - if (hperh->xfer_size - hperh->xfer_count > 0) { - (*hperh->p_buff++) = hperh->perh->RXDATA; - hperh->xfer_count++; + while (READ_BITS(hperh->perh->FCON, I2C_FCON_RXFLV_MSK, I2C_FCON_RXFLV_POSS) > 0) { + if (hperh->xfer_size - hperh->xfer_count > 0) { + (*hperh->p_buff++) = hperh->perh->RXDATA; + hperh->xfer_count++; + } + else { + return OK; + } } return OK; @@ -2212,6 +2223,7 @@ static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh) static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh) { if (hperh->xfer_size > hperh->xfer_count) { + while(hperh->perh->STAT & (0x1 << 1)); hperh->perh->TXDATA = (*hperh->p_buff++); hperh->xfer_count++; } @@ -2227,9 +2239,14 @@ static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh) { - if (hperh->xfer_size > hperh->xfer_count) { - (*hperh->p_buff++) = hperh->perh->RXDATA; - hperh->xfer_count++; + while (READ_BITS(hperh->perh->FCON, I2C_FCON_RXFLV_MSK, I2C_FCON_RXFLV_POSS) > 0) { + if (hperh->xfer_size > hperh->xfer_count) { + (*hperh->p_buff++) = hperh->perh->RXDATA; + hperh->xfer_count++; + } + else { + return OK; + } } return OK; @@ -2326,14 +2343,17 @@ static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, ui SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); if (add_size == I2C_MEMADD_SIZE_8BIT) { + while(hperh->perh->STAT & (0x1 << 1)); hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); } else { + while(hperh->perh->STAT & (0x1 << 1)); hperh->perh->TXDATA = I2C_MEM_ADD_MSB(mem_addr); if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) return ERROR; - + + while(hperh->perh->STAT & (0x1 << 1)); hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); } @@ -2365,9 +2385,11 @@ static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uin SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); if (add_size == I2C_MEMADD_SIZE_8BIT) { + while(hperh->perh->STAT & (0x1 << 1)); hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); } else { + while(hperh->perh->STAT & (0x1 << 1)); hperh->perh->TXDATA = I2C_MEM_ADD_MSB(mem_addr); if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { @@ -2380,6 +2402,7 @@ static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uin } } + while(hperh->perh->STAT & (0x1 << 1)); hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); } diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c index beb52f00de84c72f88438e3a4f0cd541ddd59dc2..9570ddf8f720d0dbe33bc9b45ff45a77999700bf 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c @@ -54,6 +54,7 @@ */ #include "ald_i2s.h" +#include "ald_cmu.h" /** @addtogroup ES32FXXX_ALD @@ -73,6 +74,7 @@ static ald_status_t i2s_wait_status(i2s_handle_t *hperh, i2s_status_t state, flag_status_t status, uint32_t timeout); static void __i2s_send_by_it(i2s_handle_t *hperh); static void __i2s_recv_by_it(i2s_handle_t *hperh); +static void __i2s_tx_recv_by_it(i2s_handle_t *hperh); #ifdef ALD_DMA static void i2s_dma_send_cplt(void *arg); static void i2s_dma_recv_cplt(void *arg); @@ -125,8 +127,8 @@ static void i2s_dma_error(void *arg); */ void ald_i2s_reset(i2s_handle_t *hperh) { - hperh->perh->I2SCFG = 0x0; - hperh->perh->I2SPR = 0x0; + hperh->perh->I2SCFG = 0x0; + hperh->perh->I2SPR = 0x0; I2S_RESET_HANDLE_STATE(hperh); __UNLOCK(hperh); @@ -143,40 +145,62 @@ void ald_i2s_reset(i2s_handle_t *hperh) */ ald_status_t ald_i2s_init(i2s_handle_t *hperh) { - uint32_t tmp = 0; + uint32_t tmp = 0, clk, _div; + + if (hperh == NULL) + return ERROR; assert_param(IS_I2S(hperh->perh)); assert_param(IS_I2S_CH_LEN(hperh->init.ch_len)); assert_param(IS_I2S_DATE_LEN(hperh->init.data_len)); assert_param(IS_I2S_CPOL(hperh->init.polarity)); assert_param(IS_I2S_STANDARD(hperh->init.standard)); - assert_param(IS_FUNC_STATE(hperh->init.ext_ck)); + assert_param(IS_FUNC_STATE(hperh->init.ext_clk_en)); assert_param(IS_FUNC_STATE(hperh->init.mck_en)); assert_param(IS_I2S_PCMS(hperh->init.pcm_frame)); - assert_param(IS_I2S_ODD(hperh->init.odd)); - assert_param(IS_I2S_DIV(hperh->init.div)); - - if (hperh == NULL) - return ERROR; ald_i2s_reset(hperh); + + tmp |= (hperh->init.ext_clk_en << SPI_I2SPR_EXTCKEN_POS); + + /* Get I2S clock */ + if (hperh->init.ext_clk_en) + clk = hperh->init.ext_clk; + else + clk = ald_cmu_get_pclk1_clock(); - tmp = hperh->perh->I2SPR; - - tmp |= ((hperh->init.ext_ck << SPI_I2SPR_EXTCKEN_POS) | (hperh->init.odd << SPI_I2SPR_ODD_POS) | - (hperh->init.div << SPI_I2SPR_I2SDIV_POSS)); + if (hperh->init.mck_en) { + _div = ((clk / hperh->init.sampling) >> 8); + } + else { + if (hperh->init.ch_len == I2S_WIDE_16) + _div = ((clk / hperh->init.sampling) >> 5); + else + _div = ((clk / hperh->init.sampling) >> 6); + } + + if (_div & 0x1) { + SET_BIT(tmp, SPI_I2SPR_ODD_MSK); + --_div; + } + else { + CLEAR_BIT(tmp, SPI_I2SPR_ODD_MSK); + } + + if (hperh->init.standard != I2S_STD_PCM) + MODIFY_REG(tmp, SPI_I2SPR_I2SDIV_MSK, (_div >> 1) << SPI_I2SPR_I2SDIV_POSS); + else + MODIFY_REG(tmp, SPI_I2SPR_I2SDIV_MSK, _div << SPI_I2SPR_I2SDIV_POSS); hperh->perh->I2SPR = tmp; - tmp = hperh->perh->I2SCFG; - + tmp = hperh->perh->I2SCFG; tmp |= ((hperh->init.ch_len << SPI_I2SCFG_CHLEN_POS) | (hperh->init.data_len << SPI_I2SCFG_DATLEN_POSS) | (hperh->init.polarity << SPI_I2SCFG_CKPOL_POS) | (hperh->init.standard << SPI_I2SCFG_I2SSTD_POSS) | (1 << SPI_I2SCFG_I2SMOD_POS)); - hperh->perh->I2SCFG = tmp; - if (hperh->init.standard == I2S_PCM_STANDARD) + if (hperh->init.standard == I2S_STD_PCM) hperh->perh->I2SCFG |= (hperh->init.pcm_frame << SPI_I2SCFG_PCMSYNC_POS); hperh->err_code = I2S_ERROR_NONE; @@ -227,62 +251,47 @@ ald_status_t ald_i2s_init(i2s_handle_t *hperh) * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_i2s_master_send(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_i2s_master_send(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout) { assert_param(IS_I2S(hperh->perh)); if (hperh->state != I2S_STATE_READY) return BUSY; - if (buf == NULL || size == 0) return ERROR; - __LOCK(hperh); - hperh->state = I2S_STATE_BUSY_TX; hperh->err_code = I2S_ERROR_NONE; - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = NULL; - hperh->rx_size = 0; - hperh->rx_count = 0; - MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); if (hperh->init.mck_en) MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); - if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) I2S_ENABLE(hperh); - while (hperh->tx_count > 0) { + while (size > 0) { if (i2s_wait_status(hperh, I2S_STATUS_TXE, SET, timeout) != OK) { I2S_DISABLE(hperh); hperh->state = I2S_STATE_READY; - __UNLOCK(hperh); return TIMEOUT; } - hperh->side = READ_BIT(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK); - hperh->perh->DATA = *hperh->tx_buf; - hperh->tx_buf++; - --hperh->tx_count; + hperh->side = READ_BITS(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK, SPI_STAT_CHSIDE_POS); + hperh->perh->DATA = *buf++; + --size; } if ((i2s_wait_status(hperh, I2S_STATUS_TXE, SET, timeout) != OK) || (i2s_wait_status(hperh, I2S_STATUS_BUSY, RESET, timeout) != OK)) { I2S_DISABLE(hperh); hperh->state = I2S_STATE_READY; - __UNLOCK(hperh); return TIMEOUT; } I2S_DISABLE(hperh); hperh->state = I2S_STATE_READY; - __UNLOCK(hperh); return OK; } @@ -295,7 +304,7 @@ ald_status_t ald_i2s_master_send(i2s_handle_t *hperh, uint16_t *buf, uint16_t si * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_i2s_master_recv(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_i2s_master_recv(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout) { assert_param(IS_I2S(hperh->perh)); @@ -304,160 +313,29 @@ ald_status_t ald_i2s_master_recv(i2s_handle_t *hperh, uint16_t *buf, uint16_t si if (buf == NULL || size == 0) return ERROR; - __LOCK(hperh); hperh->state = I2S_STATE_BUSY_RX; hperh->err_code = I2S_ERROR_NONE; - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; - MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); if (hperh->init.mck_en) MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); - if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) I2S_ENABLE(hperh); - while (hperh->rx_count > 0) { - *((uint16_t *)&(hperh->perh->DATA)) = 0xffff; + while (size > 0) { + hperh->perh->DATA = 0xffff; if (i2s_wait_status(hperh, I2S_STATUS_RXE, RESET, timeout) != OK) { I2S_DISABLE(hperh); hperh->state = I2S_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - *hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf++; - --hperh->rx_count; - - } - - hperh->state = I2S_STATE_READY; - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Slave mode transmit an amount of data in blocking mode. - * @param hperh: Pointer to a i2s_handle_t structure. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2s_slave_send(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout) -{ - uint8_t loop; - assert_param(IS_I2S(hperh->perh)); - - if (hperh->state != I2S_STATE_READY) - return BUSY; - - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - - hperh->state = I2S_STATE_BUSY_TX; - hperh->err_code = I2S_ERROR_NONE; - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = NULL; - hperh->rx_size = 0; - hperh->rx_count = 0; - - MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_SLAVE_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); - - if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) - I2S_ENABLE(hperh); - - while (hperh->tx_count > 0) { - if (i2s_wait_status(hperh, I2S_STATUS_TXE, SET, timeout) != OK) { - I2S_DISABLE(hperh); - - hperh->state = I2S_STATE_READY; - __UNLOCK(hperh); return TIMEOUT; } - hperh->side = READ_BIT(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK); - hperh->perh->DATA = *hperh->tx_buf; - hperh->tx_buf++; - --hperh->tx_count; + *buf++ = hperh->perh->DATA; + --size; } - if (i2s_wait_status(hperh, I2S_STATUS_TXE, SET, timeout) != OK) { - I2S_DISABLE(hperh); - hperh->state = I2S_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - for (loop = 0; loop < 200; loop++); - I2S_DISABLE(hperh); hperh->state = I2S_STATE_READY; - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Slave mode receive an amount of data in blocking mode. - * @param hperh: Pointer to a i2s_handle_t structure. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2s_slave_recv(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout) -{ - assert_param(IS_I2S(hperh->perh)); - - if (hperh->state != I2S_STATE_READY) - return BUSY; - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = I2S_STATE_BUSY_RX; - hperh->err_code = I2S_ERROR_NONE; - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; - - MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_SLAVE_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); - - if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) - I2S_ENABLE(hperh); - - while (hperh->rx_count > 0) { - if (i2s_wait_status(hperh, I2S_STATUS_RXE, RESET, timeout) != OK) { - I2S_DISABLE(hperh); - hperh->state = I2S_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - *hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf++; - --hperh->rx_count; - } - - hperh->state = I2S_STATE_READY; - __UNLOCK(hperh); - return OK; } @@ -468,7 +346,7 @@ ald_status_t ald_i2s_slave_recv(i2s_handle_t *hperh, uint16_t *buf, uint16_t siz * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size) +ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size) { assert_param(IS_I2S(hperh->perh)); @@ -477,28 +355,26 @@ ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint1 if (buf == NULL || size == 0) return ERROR; - __LOCK(hperh); hperh->state = I2S_STATE_BUSY_TX; hperh->err_code = I2S_ERROR_NONE; - hperh->tx_buf = buf; hperh->tx_size = size; hperh->tx_count = size; hperh->rx_buf = NULL; hperh->rx_size = 0; hperh->rx_count = 0; - + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + I2S_DISABLE(hperh); MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); if (hperh->init.mck_en) MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); - if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) I2S_ENABLE(hperh); ald_i2s_interrupt_config(hperh, I2S_IT_TXE, ENABLE); - - __UNLOCK(hperh); return OK; } @@ -509,7 +385,7 @@ ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint1 * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_i2s_master_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size) +ald_status_t ald_i2s_master_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size) { assert_param(IS_I2S(hperh->perh)); @@ -518,107 +394,28 @@ ald_status_t ald_i2s_master_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint1 if (buf == NULL || size == 0) return ERROR; - __LOCK(hperh); - hperh->state = I2S_STATE_BUSY_RX; + hperh->state = I2S_STATE_BUSY_TX_RX; hperh->err_code = I2S_ERROR_NONE; - hperh->rx_buf = buf; hperh->rx_size = size; hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; + hperh->tx_buf = 0; + hperh->tx_size = size; + hperh->tx_count = size; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + I2S_DISABLE(hperh); MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); if (hperh->init.mck_en) MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); - ald_i2s_interrupt_config(hperh, I2S_IT_RXF, ENABLE); - - __UNLOCK(hperh); - if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) I2S_ENABLE(hperh); - - return OK; -} - -/** - * @brief Wraps up slave mode transmission in non blocking mode. - * @param hperh: pointer to a i2s_handle_t structure. - * @param buf: Pointer to data transmitted buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2s_slave_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size) -{ - assert_param(IS_I2S(hperh->perh)); - - if (hperh->state != I2S_STATE_READY) - return BUSY; - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = I2S_STATE_BUSY_TX; - hperh->err_code = I2S_ERROR_NONE; - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size - 1; - hperh->rx_buf = NULL; - hperh->rx_size = 0; - hperh->rx_count = 0; - - MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_SLAVE_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); - - ald_i2s_interrupt_config(hperh, I2S_IT_TXE, ENABLE); - - __UNLOCK(hperh); - - if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) - I2S_ENABLE(hperh); - - return OK; -} - -/** - * @brief Slave mode receives an amount of data in non blocking mode - * @param hperh: Pointer to a i2s_handle_t structure. - * @param buf: Pointer to data received buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2s_slave_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size) -{ - assert_param(IS_I2S(hperh->perh)); - - if (hperh->state != I2S_STATE_READY) - return BUSY; - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = I2S_STATE_BUSY_RX; - hperh->err_code = I2S_ERROR_NONE; - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; - - MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_SLAVE_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); - - - __UNLOCK(hperh); - - if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) - I2S_ENABLE(hperh); - + ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, ENABLE); + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, ENABLE); return OK; } @@ -632,7 +429,7 @@ ald_status_t ald_i2s_slave_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16 * @param channel: DMA channel as I2S transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel) { assert_param(IS_I2S(hperh->perh)); @@ -641,44 +438,44 @@ ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint if (buf == NULL || size == 0) return ERROR; - __LOCK(hperh); hperh->state = I2S_STATE_BUSY_TX; hperh->err_code = I2S_ERROR_NONE; - hperh->tx_buf = buf; hperh->tx_size = size; hperh->tx_count = size; hperh->rx_buf = NULL; hperh->rx_size = 0; hperh->rx_count = 0; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + I2S_DISABLE(hperh); MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); if (hperh->init.mck_en) MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); - hperh->hdma.cplt_arg = (void *)hperh; - hperh->hdma.cplt_cbk = i2s_dma_send_cplt; - hperh->hdma.err_arg = (void *)hperh; - hperh->hdma.err_cbk = i2s_dma_error; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.cplt_cbk = i2s_dma_send_cplt; + hperh->hdmatx.err_arg = (void *)hperh; + hperh->hdmatx.err_cbk = i2s_dma_error; /* Configure I2S DMA transmit */ - ald_dma_config_struct(&(hperh->hdma.config)); - hperh->hdma.perh = DMA0; - hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma.config.src = (void *)buf; - hperh->hdma.config.dst = (void *)&hperh->perh->DATA; - hperh->hdma.config.size = size; - hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdma.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; - hperh->hdma.config.channel = channel; - hperh->hdma.config.burst = ENABLE; - ald_dma_config_basic(&(hperh->hdma)); - + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.perh = DMA0; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = channel; + hperh->hdmatx.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdmatx)); ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE); - __UNLOCK(hperh); if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) I2S_ENABLE(hperh); @@ -691,179 +488,82 @@ ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint * @param hperh: Pointer to a i2s_handle_t structure. * @param buf: Pointer to data buffer * @param size: Amount of data to be sent - * @param channel: DMA channel as I2S transmit + * @param dma_ch: DMA channel for I2S receive + * @param _dma_ch: DMA channel for sending clock * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_i2s_master_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_i2s_master_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch) { assert_param(IS_I2S(hperh->perh)); - + if (hperh->state != I2S_STATE_READY) return BUSY; if (buf == NULL || size == 0) return ERROR; - __LOCK(hperh); hperh->state = I2S_STATE_BUSY_RX; hperh->err_code = I2S_ERROR_NONE; - hperh->rx_buf = buf; hperh->rx_size = size; hperh->rx_count = size; hperh->tx_buf = NULL; hperh->tx_size = 0; hperh->tx_count = 0; + buf[size - 1] = 0xFFFF; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + I2S_DISABLE(hperh); MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); if (hperh->init.mck_en) MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); - hperh->hdma.cplt_arg = (void *)hperh; - hperh->hdma.cplt_cbk = i2s_dma_recv_cplt; - hperh->hdma.err_arg = (void *)hperh; - hperh->hdma.err_cbk = i2s_dma_error; - - /* Configure DMA Receive */ - ald_dma_config_struct(&(hperh->hdma.config)); - - hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma.config.src = (void *)&hperh->perh->DATA; - hperh->hdma.config.dst = (void *)buf; - hperh->hdma.config.size = size; - hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdma.config.msigsel = DMA_MSIGSEL_SPI_RNR; - hperh->hdma.config.channel = channel; - hperh->hdma.config.burst = ENABLE; - ald_dma_config_basic(&(hperh->hdma)); - - ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, ENABLE); - __UNLOCK(hperh); - - if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) - I2S_ENABLE(hperh); - - return OK; -} - -/** - * @brief Slave mode transmit an amount of data used dma channel - * @param hperh: Pointer to a i2s_handle_t structure. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param channel: DMA channel as I2S transmit - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2s_slave_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) -{ - assert_param(IS_I2S(hperh->perh)); - - if (hperh->state != I2S_STATE_READY) - return BUSY; - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = I2S_STATE_BUSY_TX; - hperh->err_code = I2S_ERROR_NONE; - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = NULL; - hperh->rx_size = 0; - hperh->rx_count = 0; - - MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_SLAVE_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); - - hperh->hdma.cplt_arg = (void *)hperh; - hperh->hdma.cplt_cbk = i2s_dma_send_cplt; - hperh->hdma.err_arg = (void *)hperh; - hperh->hdma.err_cbk = i2s_dma_error; - - /* Configure I2S DMA transmit */ - ald_dma_config_struct(&(hperh->hdma.config)); - - hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma.config.src = (void *)buf; - hperh->hdma.config.dst = (void *)&hperh->perh->DATA; - hperh->hdma.config.size = size; - hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdma.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; - hperh->hdma.config.channel = channel; - hperh->hdma.config.burst = ENABLE; - ald_dma_config_basic(&(hperh->hdma)); - + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.cplt_cbk = i2s_dma_send_cplt; + hperh->hdmatx.err_arg = (void *)hperh; + hperh->hdmatx.err_cbk = i2s_dma_error; + + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.perh = DMA0; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)&buf[size - 1]; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.channel = _dma_ch; + ald_dma_config_basic(&(hperh->hdmatx)); ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE); - __UNLOCK(hperh); - - if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) - I2S_ENABLE(hperh); - - return OK; -} - -/** - * @brief Slave mode receive an amount of data used dma channel - * @param hperh: Pointer to a i2s_handle_t structure. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param channel: DMA channel as I2S transmit - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2s_slave_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) -{ - assert_param(IS_I2S(hperh->perh)); - - if (hperh->state != I2S_STATE_READY) - return BUSY; - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = I2S_STATE_BUSY_RX; - hperh->err_code = I2S_ERROR_NONE; - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; - - MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_SLAVE_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); - - hperh->hdma.cplt_arg = (void *)hperh; - hperh->hdma.cplt_cbk = i2s_dma_recv_cplt; - hperh->hdma.err_arg = (void *)hperh; - hperh->hdma.err_cbk = i2s_dma_error; + + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.cplt_cbk = i2s_dma_recv_cplt; + hperh->hdmarx.err_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2s_dma_error; /* Configure DMA Receive */ - ald_dma_config_struct(&(hperh->hdma.config)); - - hperh->hdma.perh = DMA0; - hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma.config.src = (void *)&hperh->perh->DATA; - hperh->hdma.config.dst = (void *)buf; - hperh->hdma.config.size = size; - hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdma.config.msigsel = DMA_MSIGSEL_SPI_RNR; - hperh->hdma.config.channel = channel; - hperh->hdma.config.burst = ENABLE; - ald_dma_config_basic(&(hperh->hdma)); - + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.perh = DMA0; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.channel = dma_ch; + hperh->hdmarx.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdmarx)); ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, ENABLE); - __UNLOCK(hperh); if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) I2S_ENABLE(hperh); - + return OK; } @@ -876,10 +576,8 @@ ald_status_t ald_i2s_dma_pause(i2s_handle_t *hperh) { assert_param(IS_I2S(hperh->perh)); - __LOCK(hperh); ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE); ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE); - __UNLOCK(hperh); return OK; } @@ -893,10 +591,8 @@ ald_status_t ald_i2s_dma_resume(i2s_handle_t *hperh) { assert_param(IS_I2S(hperh->perh)); - __LOCK(hperh); ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE); ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, ENABLE); - __UNLOCK(hperh); return OK; } @@ -910,10 +606,8 @@ ald_status_t ald_i2s_dma_stop(i2s_handle_t *hperh) { assert_param(IS_I2S(hperh->perh)); - __LOCK(hperh); ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE); ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE); - __UNLOCK(hperh); hperh->state = I2S_STATE_READY; return OK; @@ -951,20 +645,23 @@ ald_status_t ald_i2s_dma_stop(i2s_handle_t *hperh) */ void ald_i2s_irq_handler(i2s_handle_t *hperh) { - if ((ald_i2s_get_it_status(hperh, I2S_IT_RXTH) != RESET) && (ald_i2s_get_it_flag_status(hperh, I2S_IF_RXTH) != RESET)) { + if (ald_i2s_get_mask_flag_status(hperh, I2S_IF_RXTH) == SET) { ald_i2s_clear_flag_status(hperh, I2S_IF_RXTH); - if (hperh->state == I2S_STATE_BUSY_RX) + if ((hperh->state == I2S_STATE_BUSY_TX_RX) || (hperh->state == I2S_STATE_BUSY_RX)) __i2s_recv_by_it(hperh); } - if ((ald_i2s_get_it_status(hperh, I2S_IT_TXE) != RESET) && (ald_i2s_get_it_flag_status(hperh, I2S_IF_TXE) != RESET)) { + + if (ald_i2s_get_mask_flag_status(hperh, I2S_IF_TXE) == SET) { ald_i2s_clear_flag_status(hperh, I2S_IF_TXE); if (hperh->state == I2S_STATE_BUSY_TX) __i2s_send_by_it(hperh); + else if (hperh->state == I2S_STATE_BUSY_TX_RX) + __i2s_tx_recv_by_it(hperh); + } - if (hperh->err_code != I2S_ERROR_NONE) { - ald_i2s_interrupt_config(hperh, I2S_IT_RXF, DISABLE); + ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE); ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE); hperh->state = I2S_STATE_READY; @@ -972,7 +669,6 @@ void ald_i2s_irq_handler(i2s_handle_t *hperh) hperh->err_cbk(hperh); } - return; } @@ -993,9 +689,9 @@ void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t stat assert_param(IS_FUNC_STATE(state)); if (state == ENABLE) - hperh->perh->IER |= (uint32_t)it; + hperh->perh->IER = (uint32_t)it; else - hperh->perh->IDR |= (uint32_t)it; + hperh->perh->IDR = (uint32_t)it; return; } @@ -1040,7 +736,7 @@ void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t * - SET * - RESET */ -flag_status_t i2s_get_status(i2s_handle_t *hperh, i2s_status_t status) +flag_status_t ald_i2s_get_status(i2s_handle_t *hperh, i2s_status_t status) { assert_param(IS_I2S(hperh->perh)); assert_param(IS_I2S_STATUS(status)); @@ -1071,8 +767,6 @@ it_status_t ald_i2s_get_it_status(i2s_handle_t *hperh, i2s_it_t it) return RESET; } - - /** @brief Check whether the specified I2S interrupt flag is set or not. * @param hperh: Pointer to a i2s_handle_t structure. * @param flag: specifies the flag to check. @@ -1081,7 +775,7 @@ it_status_t ald_i2s_get_it_status(i2s_handle_t *hperh, i2s_it_t it) * - SET * - RESET */ -flag_status_t ald_i2s_get_it_flag_status(i2s_handle_t *hperh, i2s_flag_t flag) +flag_status_t ald_i2s_get_flag_status(i2s_handle_t *hperh, i2s_flag_t flag) { assert_param(IS_I2S(hperh->perh)); assert_param(IS_I2S_IF(flag)); @@ -1092,71 +786,39 @@ flag_status_t ald_i2s_get_it_flag_status(i2s_handle_t *hperh, i2s_flag_t flag) return RESET; } -/** @brief Clear the specified I2S interrupt flags. +/** @brief Check whether the specified I2S interrupt flag is set or not. * @param hperh: Pointer to a i2s_handle_t structure. * @param flag: specifies the flag to check. * This parameter can be one of the @ref i2s_flag_t. - * @retval None + * @retval Status + * - SET + * - RESET */ -void ald_i2s_clear_flag_status(i2s_handle_t *hperh, i2s_flag_t flag) +flag_status_t ald_i2s_get_mask_flag_status(i2s_handle_t *hperh, i2s_flag_t flag) { assert_param(IS_I2S(hperh->perh)); assert_param(IS_I2S_IF(flag)); + if (hperh->perh->IFM & flag) + return SET; - hperh->perh->ICR |= flag; - return; -} - -/** - * @brief This function wait I2S status until timeout. - * @param hperh: Pointer to a i2s_handle_t structure. - * @param flag: specifies the I2S flag to check. - * @param status: The new Flag status (SET or RESET). - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2s_wait_status(i2s_handle_t *hperh, i2s_status_t flag, flag_status_t status, uint32_t timeout) -{ - uint32_t tick = ald_get_tick(); - - assert_param(timeout > 0); - - while ((i2s_get_status(hperh, flag)) != status) { - if (((ald_get_tick()) - tick) > timeout) { - ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE); - ald_i2s_interrupt_config(hperh, I2S_IT_RXF, DISABLE); - return TIMEOUT; - } - } - - return OK; + return RESET; } -/** - * @brief This function wait I2S busy status until timeout. +/** @brief Clear the specified I2S interrupt flags. * @param hperh: Pointer to a i2s_handle_t structure. - * @param status: The new Flag status (SET or RESET). - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref i2s_flag_t. + * @retval None */ -static ald_status_t i2s_wait_bsy_flag(i2s_handle_t *hperh, flag_status_t status, uint32_t timeout) +void ald_i2s_clear_flag_status(i2s_handle_t *hperh, i2s_flag_t flag) { - uint32_t tick = ald_get_tick(); - - assert_param(timeout > 0); - - while (READ_BIT(hperh->perh->STAT, SPI_STAT_BUSY_MSK) != status) { - if (((ald_get_tick()) - tick) > timeout) { - ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE); - ald_i2s_interrupt_config(hperh, I2S_IT_RXF, DISABLE); - return TIMEOUT; - } - } + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IF(flag)); - return OK; + hperh->perh->ICR = flag; + return; } - /** * @} */ @@ -1201,7 +863,6 @@ uint32_t ald_i2s_get_error(i2s_handle_t *hperh) /** * @} */ - /** * @} */ @@ -1210,6 +871,30 @@ uint32_t ald_i2s_get_error(i2s_handle_t *hperh) * @brief I2S Private functions * @{ */ +/** + * @brief This function wait I2S status until timeout. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the I2S flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2s_wait_status(i2s_handle_t *hperh, i2s_status_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + while ((ald_i2s_get_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) { + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE); + ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE); + return TIMEOUT; + } + } + + return OK; +} /** * @brief handle program when an tx empty interrupt flag arrived in non block mode @@ -1218,14 +903,18 @@ uint32_t ald_i2s_get_error(i2s_handle_t *hperh) */ static void __i2s_send_by_it(i2s_handle_t *hperh) { + int cnt = 8000; + if (hperh->tx_count == 0) { ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE); hperh->state = I2S_STATE_READY; - if ((i2s_wait_bsy_flag(hperh, RESET, 1000)) != OK) { + while ((hperh->perh->STAT & SPI_STAT_BUSY_MSK) && (--cnt)); + if (cnt == 0) { if (hperh->err_cbk) hperh->err_cbk(hperh); + ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE); return; } @@ -1235,9 +924,8 @@ static void __i2s_send_by_it(i2s_handle_t *hperh) return; } - hperh->side = READ_BIT(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK); - hperh->perh->DATA = *hperh->tx_buf; - hperh->tx_buf++; + hperh->side = READ_BITS(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK, SPI_STAT_CHSIDE_POS); + hperh->perh->DATA = *hperh->tx_buf++; --hperh->tx_count; return; @@ -1250,9 +938,10 @@ static void __i2s_send_by_it(i2s_handle_t *hperh) */ static void __i2s_recv_by_it(i2s_handle_t *hperh) { - *hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf++; - --hperh->rx_count; + while (READ_BITS(hperh->perh->STAT, SPI_STAT_RXFLV_MSK, SPI_STAT_RXFLV_POSS)) { + *(hperh->rx_buf++) = hperh->perh->DATA; + --hperh->rx_count; + } if (hperh->rx_count == 0) { ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE); @@ -1265,6 +954,22 @@ static void __i2s_recv_by_it(i2s_handle_t *hperh) return; } +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None. + */ +static void __i2s_tx_recv_by_it(i2s_handle_t *hperh) +{ + if (hperh->tx_count != 0) { + ald_i2s_clear_flag_status(hperh, I2S_IF_TXE); + hperh->perh->DATA = 0xffff; + --hperh->tx_count; + if (hperh->tx_count == 0) + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE); + } +} + #ifdef ALD_DMA /** * @brief DMA I2S transmit process complete callback. @@ -1273,13 +978,15 @@ static void __i2s_recv_by_it(i2s_handle_t *hperh) */ static void i2s_dma_send_cplt(void *arg) { + int cnt = 8000; i2s_handle_t *hperh = (i2s_handle_t *)arg; hperh->tx_count = 0; ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE); hperh->state = I2S_STATE_READY; - if ((i2s_wait_bsy_flag(hperh, RESET, 1000)) != OK) + while ((hperh->perh->STAT & SPI_STAT_BUSY_MSK) && (--cnt)); + if (cnt == 0) hperh->err_code |= I2S_ERROR_FLAG; if (hperh->err_code == I2S_ERROR_NONE) { @@ -1342,11 +1049,11 @@ static void i2s_dma_error(void *arg) return; } -#endif /* ALD_DMA */ +#endif /** * @} */ -#endif /* ALD_I2S */ +#endif /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c index 38a2aae19963f612370ff46f50e4aceefd0a54be..e350c0a3ac6082158588cfe204963ea64a3d8a53 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c @@ -136,6 +136,101 @@ uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint3 return !status; } + +/** + * @brief Erases a specified page of dataflash. + * @param addr: The beginning address of the page to be erased. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_erase_page_df(uint32_t addr) +{ + uint32_t status; + IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PageErase_DF); + + __disable_irq(); + status = (*iap_pe)(addr); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs a word at a specified address of dataflash. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data: Specifies the data to be programmed. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_program_word_df(uint32_t addr, uint32_t data) +{ + uint32_t status; + IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WordProgram_DF); + + if (addr & 0x3) + return 1; + + __disable_irq(); + status = (*iap_wp)(addr, data); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs double words at a specified address of dataflash. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data_l: Specifies the LSB data to be programmed. + * @param data_h: Specifies the MSB data to be programmed. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_program_dword_df(uint32_t addr, uint32_t data_l, uint32_t data_h) +{ + uint32_t status; + IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWordProgram_DF); + + if (addr & 0x3) + return 1; + + __disable_irq(); + status = (*iap_dwp)(addr, data_l, data_h); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs datas at a specified address of dataflash. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data: Specifies the data to be programmed. + * @param len: Specifies the data length to be programmed. + * Bit0-1 must be zero. + * @param erase: Erase page flag before programming. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_program_words_df(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase) +{ + uint32_t status; + IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WordsProgram_DF); + + if ((addr & 0x3) || (len & 0x3)) + return 1; + + __disable_irq(); + status = (*iap_wsp)(addr, data, len, erase); + __enable_irq(); + + return !status; +} /** * @} */ @@ -143,7 +238,6 @@ uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint3 /** * @} */ - /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c index 5ffac6ae2bdf6d61039411b4766993995bbb093c..e26037fcfcd30bf9b974d82661ae14099cd98a39 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c @@ -44,8 +44,6 @@ */ ald_status_t ald_pis_create(pis_handle_t *hperh) { - pis_divide_t temp; - if (hperh == NULL) return ERROR; @@ -61,10 +59,9 @@ ald_status_t ald_pis_create(pis_handle_t *hperh) /* get location of consumer in channel and position of con0/con1 * accord to comsumer_trig information */ - temp.HalfWord = (hperh->init.consumer_trig); - hperh->consumer_ch = (pis_ch_t)(temp.ch); - hperh->consumer_con = (pis_con_t)(temp.con); - hperh->consumer_pos = (1 << temp.shift); + hperh->consumer_ch = (pis_ch_t)(hperh->init.consumer_trig & 0x0F); + hperh->consumer_con = (pis_con_t)((hperh->init.consumer_trig >> 4) & 0x0F); + hperh->consumer_pos = (1U << (uint32_t)((hperh->init.consumer_trig >> 8) & 0xFF)); if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) { __UNLOCK(hperh); @@ -136,7 +133,7 @@ ald_status_t ald_pis_destroy(pis_handle_t *hperh) __LOCK(hperh); - CLEAR_BIT(PIS->CH_OER, (1 << hperh->consumer_ch)); + CLEAR_BIT(PIS->CH_OER, (1U << (uint32_t)hperh->consumer_ch)); WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0); switch (hperh->consumer_con) { diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c index 500bd1acc5a49508af599fd78fa97134daed0732..bb588747db52e34146ec92f474d40d7d18b8bf85 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c @@ -77,11 +77,20 @@ void ald_lvd_irq_handler(void) */ void ald_pmu_stop1_enter(void) { + int cnt = 4000; + SYSCFG_UNLOCK(); + + CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); +#ifdef ES32F336x /* MCU Series: ES32F336x */ SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); +#endif + MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, PMU_LDO_18_HOLD << PMU_CR1_LDO18MOD_POSS); MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP1 << PMU_CR0_LPM_POSS); SYSCFG_LOCK(); + while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--)); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; __WFI(); @@ -96,11 +105,20 @@ void ald_pmu_stop1_enter(void) */ void ald_pmu_stop2_enter(void) { + int cnt = 4000; + SYSCFG_UNLOCK(); + + SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); +#ifdef ES32F336x /* MCU Series: ES32F336x */ SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); +#endif + MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, PMU_LDO_18_HOLD << PMU_CR1_LDO18MOD_POSS); MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP2 << PMU_CR0_LPM_POSS); SYSCFG_LOCK(); + while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--)); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; __WFI(); @@ -120,7 +138,6 @@ void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level) ald_bkpc_standby_wakeup_config(port, level); SYSCFG_UNLOCK(); - SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STANDBY << PMU_CR0_LPM_POSS); SYSCFG_LOCK(); @@ -132,6 +149,46 @@ void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level) return; } +/** + * @brief Enable/Disable LDO(1.2V) hold mode. It must be disabled in STOP1. + * @param state: Enable/Disable + * @retval None + */ +void ald_pmu_ldo_12_config(type_func_t state) +{ + assert_param(IS_FUNC_STATE(state)); + SYSCFG_UNLOCK(); + + if (state) + SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); + else + CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Configure LDO(1.8V) mode + * @param mode: Mode of the LDO(1.8V) + * @retval None + */ +void ald_pmu_ldo_18_config(pmu_ldo_18_mode_t mode) +{ + uint32_t cnt = 4000; + + assert_param(IS_PMU_LDO18_MODE(mode)); + + SYSCFG_UNLOCK(); + MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, mode << PMU_CR1_LDO18MOD_POSS); + SYSCFG_LOCK(); + + while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--)); + return; +} + +#ifdef ES32F336x /* MCU Series: ES32F336x */ + /** * @brief Configures low power mode. The system clock must * be less than 2MHz. Such as: LOSC or LRC. @@ -157,6 +214,7 @@ void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state) SYSCFG_LOCK(); return; } +#endif /** * @brief Get wakup status. diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c index d8bd0c9430e727349e1151ab731a25cdc8453b3c..d0c0ecb3acd9781ed77210a566bea59b23512793 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c @@ -42,7 +42,7 @@ static ald_status_t qspi_wait_for_idle(qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout) { /* Wait until flag is in expected state */ - while (READ_BIT(hperh->perh->CR, QSPI_CR_IDLES_MSK) != QSPI_CR_IDLES) { + while (READ_BIT(hperh->perh->CR, QSPI_CR_IDLES_MSK) != QSPI_CR_IDLES_MSK) { /* Check for the Timeout */ if (timeout != ALD_MAX_DELAY) { if ((timeout == 0U) || ((ald_get_tick() - tickstart) > timeout)) { @@ -318,7 +318,7 @@ ald_status_t qspi_dac_config(qspi_handle_t * hperh, qspi_dac_cfg_t * dcfg) MODIFY_REG(hperh->perh->DWIR, QSPI_DWIR_WINST_MSK | QSPI_DWIR_DCYC_MSK | \ QSPI_DWIR_ADMODE_MSK | QSPI_DWIR_DMODE_MSK | \ - QSPI_DWIR_WELD_MSK, dcfg->wrinit.wrcde | dcfg->wrinit.autowel | \ + QSPI_DWIR_WELD_MSK, dcfg->wrinit.wrcde | dcfg->wrinit.autowel << 8 | \ (dcfg->wrinit.addxfer << 12) | \ (dcfg->wrinit.datxfer << 16) | \ (dcfg->wrinit.dcyles << 24)); @@ -329,7 +329,7 @@ ald_status_t qspi_dac_config(qspi_handle_t * hperh, qspi_dac_cfg_t * dcfg) MODIFY_REG(hperh->perh->CR, QSPI_CR_DTRM_MSK | QSPI_CR_ADEN_MSK | QSPI_CR_XIPIM_MSK | \ QSPI_CR_XIPNX_MSK | QSPI_CR_AREN_MSK | QSPI_CR_DMAEN_MSK, \ - dcfg->dtrprtcol | dcfg->ahbdecoder); + dcfg->dtrprtcol << 24 | dcfg->ahbdecoder << 23); QSPI_ENABLE(hperh); return OK; } @@ -456,6 +456,7 @@ ald_status_t ald_qspi_indac_transmit_by_poll(qspi_handle_t *hperh, uint32_t sadd /* Get transmit SRAM partition (unit:4bytes)*/ tmp = READ_REG(hperh->perh->SPR); txsm = QSPI_SRAM_SIZE - tmp; + if (txsm == 0) return ERROR; if (cnt <= txsm) { /* Trigger indirect write */ SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK); @@ -496,9 +497,9 @@ ald_status_t ald_qspi_indac_transmit_by_poll(qspi_handle_t *hperh, uint32_t sadd ald_status_t ald_qspi_indac_read_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size) { - uint32_t i, j = 0, cnt = 0; + uint32_t i = 0, j = 0, cnt = 0; uint32_t tmp = 0; - uint32_t idx = 0, rxsm = 0; + uint32_t idx = 0, rxsm = 1; assert_param(IS_QSPI_ALL(hperh->perh)); @@ -518,35 +519,35 @@ ald_status_t ald_qspi_indac_read_by_poll(qspi_handle_t *hperh, uint32_t saddr, u SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK); do { tmp = READ_REG(hperh->perh->SFLR); - tmp = tmp & 0x0000ffff; - } while ( tmp != cnt); + tmp = tmp & 0x0000ffffU; + } while (tmp != cnt); for (i = 0; i < cnt; ++i) - *(uint32_t *)(desbuf + 4 *i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; + *(uint32_t *)(desbuf + 4 * i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; } else { SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK); for (j = 0; j < (cnt / rxsm); ++j) { do { tmp = READ_REG(hperh->perh->SFLR); - tmp = tmp & 0x0000ffff; - } while ( tmp != rxsm); + tmp = tmp & 0x0000ffffU; + } while (tmp != rxsm); for (i = 0; i < rxsm; ++i) { - *(uint32_t *)(desbuf + idx + 4 *i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; + *(uint32_t *)(desbuf + idx + 4 * i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; } idx += rxsm * 4; } do { tmp = READ_REG(hperh->perh->SFLR); - tmp = tmp & 0x0000ffff; + tmp = tmp & 0x0000ffffU; } while ( tmp != (cnt % rxsm)); for (j = 0; j < (cnt % rxsm); ++j) { - *(uint32_t *)(desbuf + idx + 4 *i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; + *(uint32_t *)(desbuf + idx + 4 * i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; } } /* Wait for indirect read operation completely */ do { tmp = READ_REG(hperh->perh->IRTR); - } while ( tmp & 0x04); + } while (tmp & 0x04); return OK; } @@ -753,7 +754,6 @@ ald_status_t ald_qspi_indac_read_by_dma(qspi_handle_t *hperh, uint32_t addr, uin uint32_t *tmp = (uint32_t *)pdbuf; /* Get Indirect Read Trigger Address */ __IO uint32_t *data_reg = (uint32_t *)hperh->perh->IATR; - uint32_t tickstart = ald_get_tick(); assert_param(IS_QSPI_ALL(hperh->perh)); @@ -987,9 +987,9 @@ void ald_qspi_interrupt_config(qspi_handle_t *hperh, qspi_it_t it, type_func_t s assert_param(IS_FUNC_STATE(state)); if (state == ENABLE) - hperh->perh->IMR |= it; + hperh->perh->IMR |= (uint32_t)it; else - hperh->perh->IMR &= ~it; + hperh->perh->IMR &= (uint32_t)(~it); return; } diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c index 4e7cd0d3bdda07da89e41a6082d87ad23dd13dbb..c5bd06b325cd464d4506b79aa439d1b10922f88e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c @@ -63,12 +63,15 @@ void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t sta /** * @brief Get specified reset status * @param state: Speicifies the type of the reset, - * @retval The status: SET/RESET. + * @retval The status. */ -flag_status_t ald_rmu_get_reset_status(rmu_state_t state) +uint32_t ald_rmu_get_reset_status(rmu_state_t state) { assert_param(IS_RMU_STATE(state)); + if (state == RMU_RST_ALL) + return RMU->RSTSR; + if (READ_BIT(RMU->RSTSR, state)) return SET; @@ -101,7 +104,7 @@ void ald_rmu_reset_periperal(rmu_peripheral_t perh) assert_param(IS_RMU_PERH(perh)); - idx = (perh >> 27) & 0x7; + idx = ((uint32_t)perh >> 27) & 0x7; pos = perh & ~(0x7 << 27); SYSCFG_UNLOCK(); diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c index d288c6866cd489b7f7ae60f7314f84afec06dfb0..c0fd24b64f5a7c860cc8225b8ee2ba65d855accf 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c @@ -311,7 +311,7 @@ void ald_rtc_source_select(rtc_source_sel_t sel) * @param format: Data format. * @retval ALD status. */ -ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format) +ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format) { uint32_t tmp; @@ -336,7 +336,6 @@ ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format) RTC_UNLOCK(); WRITE_REG(RTC->TIME, tmp); - WRITE_REG(RTC->SSEC, time->sub_sec); RTC_LOCK(); tmp = ald_get_tick(); @@ -798,12 +797,12 @@ void ald_rtc_set_tamper(rtc_tamper_t *tamper) MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPFLT_MSK, tamper->dur << RTC_TAMPCON_TAMPFLT_POSS); if (tamper->idx == RTC_TAMPER_0) { - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP1LV_MSK, tamper->trig << RTC_TAMPCON_TAMP1LV_POS); - SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP0LV_MSK, tamper->trig << RTC_TAMPCON_TAMP0LV_POS); + SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP0EN_MSK); } else { - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP2LV_MSK, tamper->trig << RTC_TAMPCON_TAMP2LV_POS); - SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP1LV_MSK, tamper->trig << RTC_TAMPCON_TAMP1LV_POS); + SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); } RTC_LOCK(); @@ -824,9 +823,9 @@ void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx) RTC_UNLOCK(); if (idx == RTC_TAMPER_0) - CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); + CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP0EN_MSK); else - CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK); + CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); RTC_LOCK(); return; diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c index a2de0d5261367017359f1facefc0a9bd66b9a8e5..ce78e605a7ee24fca8fa5da83e03de56a84a9b0b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c @@ -73,7 +73,6 @@ * @{ */ -static ald_status_t spi_wait_status(spi_handle_t *hperh, spi_status_t state, flag_status_t status, uint32_t timeout); static void __spi_send_by_it(spi_handle_t *hperh); static void __spi_recv_by_it(spi_handle_t *hperh); static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); @@ -152,6 +151,9 @@ ald_status_t ald_spi_init(spi_handle_t *hperh) { uint32_t tmp = 0; + if (hperh == NULL) + return ERROR; + assert_param(IS_SPI(hperh->perh)); assert_param(IS_SPI_MODE(hperh->init.mode)); assert_param(IS_SPI_DIRECTION(hperh->init.dir)); @@ -164,11 +166,7 @@ ald_status_t ald_spi_init(spi_handle_t *hperh) assert_param(IS_SPI_CPOL(hperh->init.polarity)); assert_param(IS_SPI_FRAME(hperh->init.frame)); - if (hperh == NULL) - return ERROR; - ald_spi_reset(hperh); - tmp = hperh->perh->CON1; if (hperh->init.mode == SPI_MODE_MASTER) @@ -207,9 +205,7 @@ ald_status_t ald_spi_init(spi_handle_t *hperh) hperh->err_code = SPI_ERROR_NONE; hperh->state = SPI_STATE_READY; - if (hperh->init.dir == SPI_DIRECTION_2LINES) - SPI_ENABLE(hperh); - + SPI_ENABLE(hperh); return OK; } @@ -233,33 +229,15 @@ ald_status_t spi_fifo_threshold_config(spi_handle_t *hperh, uint8_t threshold) * @} */ -/** @defgroup SPI_Public_Functions_Group2 IO operation functions +/** @defgroup SPI_Public_Functions_Group2 IO fast functions * @brief SPI Transmit and Receive functions * * @verbatim ============================================================================== - ##### IO operation functions ##### + ##### IO fast functions ##### =============================================================================== This subsection provides a set of functions allowing to manage the SPI - data transfers. - - [..] The SPI supports master or slave mode: - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The ALD status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These APIs return the ALD status. - The end of the data processing will be indicated through the - dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk() user callbacks - will be executed respectivelly at the end of the transmit or Receive process - The hperh->err_cbk() user callback will be executed when a communication error is detected - - (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) - exist for 1Line (simplex) and 2Lines (full duplex) modes. + data transfers fast. * @endverbatim * @{ @@ -277,6 +255,7 @@ int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data) { uint16_t cnt = 5000, temp; + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); hperh->perh->DATA = data; while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); @@ -300,6 +279,7 @@ int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data) { uint16_t cnt = 5000; + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); hperh->perh->DATA = data; while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); @@ -328,6 +308,223 @@ uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh, int *status) return (uint8_t)hperh->perh->DATA; } +/** + * @brief Transmit some bytes fast in blocking mode. + * @note Bit width is 8-bits. Supports mode: Master/Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be sent. + * @param size: Length of data. + * @param timeout: Timeout between two bytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_send_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t i, tmp = 0; + + while (size--) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *buf++; + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + + for (i = 0; i < 16; ++i) { + if ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) + tmp = hperh->perh->DATA; + else + break; + } + + UNUSED(tmp); + return OK; +} + +/** + * @brief Receive some bytes fast in blocking mode. + * @note Bit width is 8-bits. Supports mode: Master. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_master_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + uint16_t cnt = 8000; + + while (size--) { + hperh->perh->DATA = 0xFF; + cnt = 8000; + while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt)); + + if (cnt) + *buf++ = (uint8_t)hperh->perh->DATA; + else + return TIMEOUT; + } + + return OK; +} + +/** + * @brief Receive some bytes fast in blocking mode. + * @note Bit width is 8-bits. Supports mode: Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. + * @param timeout: Timeout between two bytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_slave_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + + while (size--) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + + *buf++ = (uint8_t)hperh->perh->DATA; + } + + return OK; +} + +/** + * @brief Transmit some double-bytes fast in blocking mode. + * @note Bit width is 16-bits. Supports mode: Master/Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be sent. + * @param size: Length of data. Unit is double-bytes. + * @param timeout: Timeout between two dbytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_send_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t i, tmp = 0; + + while (size--) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)buf); + buf += 2; + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + + for (i = 0; i < 16; ++i) { + if ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) + tmp = hperh->perh->DATA; + else + break; + } + + UNUSED(tmp); + return OK; +} + +/** + * @brief Receive some double-bytes fast in blocking mode. + * @note Bit width is 16-bits. Supports mode: Master. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. Unit is double-bytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_master_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + uint16_t cnt = 8000; + + while (size--) { + hperh->perh->DATA = 0xFFFF; + cnt = 8000; + while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt)); + + if (cnt) { + *(uint16_t *)buf = (uint16_t)hperh->perh->DATA; + buf += 2; + } + else { + return TIMEOUT; + } + } + + return OK; +} + +/** + * @brief Receive some double-bytes fast in blocking mode. + * @note Bit width is 16-bits. Supports mode: Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. Unit is double-bytes. + * @param timeout: Timeout between two dbytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_slave_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + + while (size--) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + + *(uint16_t *)buf = (uint16_t)hperh->perh->DATA; + buf += 2; + } + + return OK; +} +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group3 IO operation functions + * @brief SPI Transmit and Receive functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master or slave mode: + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The ALD status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the ALD status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The hperh->err_cbk() user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + + * @endverbatim + * @{ + */ /** * @brief Transmit an amount of data in blocking mode. * @param hperh: Pointer to a spi_handle_t structure. @@ -338,6 +535,9 @@ uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh, int *status) */ ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { + uint32_t tick; + uint16_t temp; + assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) @@ -345,77 +545,86 @@ ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint if (buf == NULL || size == 0) return ERROR; - __LOCK(hperh); - - hperh->state = SPI_STATE_BUSY_TX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = NULL; - hperh->rx_size = 0; - hperh->rx_count = 0; + hperh->state = SPI_STATE_BUSY_TX; if (hperh->init.crc_calc) SPI_CRC_RESET(hperh); - if (hperh->init.dir == SPI_DIRECTION_1LINE) - SPI_1LINE_TX(hperh); - if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) - SPI_ENABLE(hperh); - if ((hperh->init.mode == SPI_MODE_SLAVER) || (hperh->tx_count == 1)) { + while (size > 1) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *((volatile uint8_t *)hperh->perh + 0x0c) = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *buf; + ++buf; } else { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)buf); + buf += 2; } + + --size; } - while (hperh->tx_count > 0) { - if (spi_wait_status(hperh, SPI_STATUS_TXE, SET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); + tick = ald_get_tick(); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; + while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.crc_calc) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *buf; + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)buf); } + SPI_CRCNEXT_ENABLE(hperh); + } + else { if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *((volatile uint8_t *)hperh->perh + 0x0c) = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *buf; } else { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)buf); } } - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); + while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } - if ((spi_wait_status(hperh, SPI_STATUS_TXE, SET, timeout) != OK) - || (spi_wait_status(hperh, SPI_STATUS_BUSY, RESET, timeout) != OK)) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); + while ((hperh->perh->STAT & SPI_STATUS_BUSY) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } + while ((spi_get_status(hperh, SPI_STATUS_RXE)) == RESET) { + temp = hperh->perh->DATA; + UNUSED(temp); + } hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return OK; +timeout: + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + return TIMEOUT; } /** @@ -428,7 +637,9 @@ ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint */ ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { + uint32_t tick; uint16_t temp; + assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) @@ -436,122 +647,65 @@ ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint if (buf == NULL || size == 0) return ERROR; - __LOCK(hperh); + if (hperh->init.mode == SPI_MODE_MASTER) + return ald_spi_send_recv(hperh, buf, buf, size, timeout); + hperh->state = SPI_STATE_BUSY_RX; hperh->err_code = SPI_ERROR_NONE; - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; - if (hperh->init.crc_calc) SPI_CRC_RESET(hperh); - if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) - SPI_1LINE_RX(hperh); - - if ((hperh->init.mode == SPI_MODE_MASTER) && (hperh->init.dir == SPI_DIRECTION_2LINES)) { - __UNLOCK(hperh); - hperh->state = SPI_STATE_READY; - return ald_spi_send_recv(hperh, buf, buf, size, timeout); - } - if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) - SPI_ENABLE(hperh); + while (size > 0) { + tick = ald_get_tick(); - if (hperh->rx_count > 0) { - if (hperh->init.data_size <= SPI_DATA_SIZE_8) { - *((uint8_t *)&(hperh->perh->DATA)) = 0xB1; - } - else { - *((uint16_t *)&(hperh->perh->DATA)) = 0xB2B1; - } - } - while (hperh->rx_count > 0) { - if (hperh->rx_count > 1) { - if (hperh->init.data_size <= SPI_DATA_SIZE_8) { - *((uint8_t *)&(hperh->perh->DATA)) = 0xB1; - } - else { - *((uint16_t *)&(hperh->perh->DATA)) = 0xB2B1; - } - } - - if (spi_wait_status(hperh, SPI_STATUS_RXE, RESET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if ((hperh->init.crc_calc == ENABLE) && (READ_BIT(hperh->perh->CON1, SPI_CON1_NXTCRC_MSK) == 0)) { - ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, ENABLE); - SET_BIT(hperh->perh->CON1, SPI_CON1_NXTCRC_MSK); + while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; } if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; + *buf = hperh->perh->DATA; + ++buf; } else { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; - --hperh->rx_count; + *(uint16_t *)buf = hperh->perh->DATA; + buf += 2; } - } - - if (spi_wait_status(hperh, SPI_STATUS_RXE, SET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; - --hperh->rx_count; + --size; } if (hperh->init.crc_calc) { - if (spi_wait_status(hperh, SPI_STATUS_RXTH, RESET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); + tick = ald_get_tick(); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; + while ((hperh->perh->STAT & SPI_STATUS_RXTH) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; } temp = hperh->perh->DATA; UNUSED(temp); - } - if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { - hperh->err_code |= SPI_ERROR_CRC; - SPI_CRC_RESET(hperh); - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return ERROR; + if ((hperh->perh->RIF & SPI_IF_CRCERR) != RESET) { + hperh->err_code |= SPI_ERROR_CRC; + SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + hperh->state = SPI_STATE_READY; + + return ERROR; + } } hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return OK; + +timeout: + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + return TIMEOUT; } /** @@ -565,6 +719,7 @@ ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint */ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) { + uint32_t tick; uint16_t temp; assert_param(IS_SPI(hperh->perh)); @@ -576,185 +731,133 @@ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx if (tx_buf == NULL || rx_buf == NULL || size == 0) return ERROR; - __LOCK(hperh); hperh->state = SPI_STATE_BUSY_TX_RX; hperh->err_code = SPI_ERROR_NONE; - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->rx_count = size; - if (hperh->init.crc_calc) SPI_CRC_RESET(hperh); - if (hperh->init.mode == SPI_MODE_SLAVER) { - if (spi_wait_status(hperh, SPI_STATUS_TXE, SET, timeout) != OK) { - SPI_DISABLE(hperh); + while (size > 1) { + tick = ald_get_tick(); - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; + while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; } - if (hperh->init.data_size <= SPI_DATA_SIZE_8) { - *((volatile uint8_t *)hperh->perh + 0x0c) = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *tx_buf; + ++tx_buf; } else { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)tx_buf); + tx_buf += 2; } - } - - if (hperh->tx_buf == 0) { - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - if (spi_wait_status(hperh, SPI_STATUS_RXE, RESET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); + tick = ald_get_tick(); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; + while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; } if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; + *rx_buf = (uint8_t)hperh->perh->DATA; + ++rx_buf; } else { - (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; - hperh->rx_buf += 2; - --hperh->rx_count; + (*(uint16_t *)rx_buf) = hperh->perh->DATA; + rx_buf += 2; } + + --size; } - while (hperh->tx_count > 0) { - if (spi_wait_status(hperh, SPI_STATUS_TXE, SET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); + tick = ald_get_tick(); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } + while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *((volatile uint8_t *)hperh->perh + 0x0c) = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *tx_buf; + SPI_CRCNEXT_ENABLE(hperh); } else { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; - } - - if (spi_wait_status(hperh, SPI_STATUS_RXE, RESET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *tx_buf; } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; + } + else { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)tx_buf); + SPI_CRCNEXT_ENABLE(hperh); } else { - (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; - - hperh->rx_buf += 2; - --hperh->rx_count; + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)tx_buf); } } - if (hperh->init.mode == SPI_MODE_SLAVER) { - if (spi_wait_status(hperh, SPI_STATUS_RXE, RESET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else { - (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; + tick = ald_get_tick(); - hperh->rx_buf += 2; - --hperh->rx_count; - } + while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; } - if (hperh->init.crc_calc) { - SPI_CRCNEXT_ENABLE(hperh); - - if (spi_wait_status(hperh, SPI_STATUS_TXE, SET, timeout) != OK) { - SPI_DISABLE(hperh); + if (hperh->init.data_size == SPI_DATA_SIZE_8) + *rx_buf = (uint8_t)hperh->perh->DATA; + else + (*(uint16_t *)rx_buf) = hperh->perh->DATA; - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); + if (hperh->init.crc_calc) { + tick = ald_get_tick(); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; + while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; } - if (spi_wait_status(hperh, SPI_STATUS_RXE, RESET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); + tick = ald_get_tick(); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; + while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; } temp = hperh->perh->DATA; UNUSED(temp); - } - if ((spi_wait_status(hperh, SPI_STATUS_BUSY, RESET, timeout) != OK)) { - if (hperh->init.crc_calc) + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) { + hperh->err_code |= SPI_ERROR_CRC; SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + hperh->state = SPI_STATE_READY; - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; + return ERROR; + } } - if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { - hperh->err_code |= SPI_ERROR_CRC; - SPI_CRC_RESET(hperh); - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - - return ERROR; + while ((hperh->perh->STAT & SPI_STATUS_BUSY) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; } hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return OK; +timeout: + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + return TIMEOUT; } /** @@ -788,12 +891,6 @@ ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size if (hperh->init.crc_calc) SPI_CRC_RESET(hperh); - if (hperh->init.dir == SPI_DIRECTION_1LINE) - SPI_1LINE_TX(hperh); - - if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) - SPI_ENABLE(hperh); - ald_spi_interrupt_config(hperh, SPI_IT_TXE, ENABLE); return OK; @@ -840,14 +937,11 @@ ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size ald_spi_interrupt_config(hperh, SPI_IT_RXTH, ENABLE); ald_spi_interrupt_config(hperh, SPI_IT_MODF, ENABLE); - if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) - SPI_ENABLE(hperh); - if (hperh->init.data_size <= SPI_DATA_SIZE_8) { - *((uint8_t *)&(hperh->perh->DATA)) = 0xB1; + *((uint8_t *)&(hperh->perh->DATA)) = 0xFF; } else { - *((uint16_t *)&(hperh->perh->DATA)) = 0xB2B1; + *((uint16_t *)&(hperh->perh->DATA)) = 0xFFFF; } return OK; @@ -1181,7 +1275,7 @@ ald_status_t ald_spi_dma_stop(spi_handle_t *hperh) * @} */ -/** @defgroup SPI_Public_Functions_Group3 Control functions +/** @defgroup SPI_Public_Functions_Group4 Control functions * @brief SPI Control functions * * @verbatim @@ -1305,7 +1399,7 @@ void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) assert_param(IS_SPI_BAUD(speed)); tmp = hperh->perh->CON1; - tmp &= ~(0x7 << SPI_CON1_BAUD_POSS); + tmp &= ~(0x7U << SPI_CON1_BAUD_POSS); tmp |= (speed << SPI_CON1_BAUD_POSS); hperh->perh->CON1 = tmp; return; @@ -1362,32 +1456,6 @@ flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status) return RESET; } -/** - * @brief This function handles SPI communication timeout. - * @param hperh: Pointer to a spi_handle_t structure. - * @param state: specifies the SPI flag to check. - * @param status: The new Flag status (SET or RESET). - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t spi_wait_status(spi_handle_t *hperh, spi_status_t state, flag_status_t status, uint32_t timeout) -{ - uint32_t tick = ald_get_tick(); - - assert_param(timeout > 0); - - while ((spi_get_status(hperh, state)) != status) { - if (((ald_get_tick()) - tick) > timeout) { - ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_MODF, DISABLE); - return TIMEOUT; - } - } - - return OK; -} - /** * @brief Checks whether the specified SPI interrupt has occurred or not. * @param hperh: Pointer to a spi_handle_t structure. @@ -1472,8 +1540,6 @@ static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag static ald_status_t spi_wait_bsy_flag(spi_handle_t *hperh, flag_status_t status, uint32_t timeout) { - uint32_t tick = ald_get_tick(); - assert_param(timeout > 0); while ((READ_BIT(hperh->perh->STAT, SPI_STAT_BUSY_MSK)) && (--timeout)); @@ -1493,7 +1559,7 @@ static ald_status_t spi_wait_bsy_flag(spi_handle_t *hperh, flag_status_t status, * @} */ -/** @defgroup SPI_Public_Functions_Group4 Peripheral State and Errors functions +/** @defgroup SPI_Public_Functions_Group5 Peripheral State and Errors functions * @brief SPI State and Errors functions * * @verbatim @@ -1550,6 +1616,8 @@ uint32_t ald_spi_get_error(spi_handle_t *hperh) */ static void __spi_send_by_it(spi_handle_t *hperh) { + uint16_t temp; + if (hperh->tx_count == 0) { ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE); hperh->state = SPI_STATE_READY; @@ -1565,6 +1633,11 @@ static void __spi_send_by_it(spi_handle_t *hperh) return; } + while ((spi_get_status(hperh, SPI_STATUS_RXE)) == RESET) { + temp = hperh->perh->DATA; + UNUSED(temp); + } + if (hperh->tx_cplt_cbk) hperh->tx_cplt_cbk(hperh); @@ -1573,21 +1646,48 @@ static void __spi_send_by_it(spi_handle_t *hperh) ald_spi_clear_flag_status(hperh, SPI_IF_TXE); - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *((volatile uint8_t *)hperh->perh + 0x0c) = *hperh->tx_buf; - ++hperh->tx_buf; + if (hperh->tx_count == 1) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + } + + ++hperh->tx_buf; + } + else { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + } + + hperh->tx_buf += 2; + } } else { - hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; - hperh->tx_buf += 2; - } - --hperh->tx_count; - - if (hperh->tx_count == 0) { - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } } + --hperh->tx_count; return; } @@ -1599,17 +1699,21 @@ static void __spi_send_by_it(spi_handle_t *hperh) static void __spi_recv_by_it(spi_handle_t *hperh) { uint16_t temp; - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - } - else { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; + + while (READ_BITS(hperh->perh->STAT, SPI_STAT_RXFLV_MSK, SPI_STAT_RXFLV_POSS)) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + + --hperh->rx_count; } ald_spi_clear_flag_status(hperh, SPI_IF_RXTH); - --hperh->rx_count; if (hperh->rx_count == 0) { ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE); @@ -1635,10 +1739,10 @@ static void __spi_recv_by_it(spi_handle_t *hperh) } if (hperh->init.data_size <= SPI_DATA_SIZE_8) { - *((uint8_t *)&(hperh->perh->DATA)) = 0xB1; + hperh->perh->DATA = 0xff; } else { - *((uint16_t *)&(hperh->perh->DATA)) = 0xB2B1; + hperh->perh->DATA = 0xffff; } return; @@ -1666,9 +1770,6 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) } --hperh->rx_count; } - - if ((hperh->rx_count == 0xffff) && (hperh->init.crc_calc == ENABLE)) - hperh->rx_count = 0; } } @@ -1677,34 +1778,47 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) ald_spi_clear_flag_status(hperh, SPI_IF_TXE); if (hperh->tx_count == 1) { if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *((volatile uint8_t *)hperh->perh + 0x0c) = *hperh->tx_buf; + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + } + ++hperh->tx_buf; } else { - hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; - hperh->tx_buf += 2; + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + } + + hperh->tx_buf += 2; } --hperh->tx_count; - - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); } else { if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *((volatile uint8_t *)hperh->perh + 0x0c) = *hperh->tx_buf; + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; ++hperh->tx_buf; } else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; hperh->tx_buf += 2; } - if (--hperh->tx_count == 0) { - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE); - } + --hperh->tx_count; } } } @@ -1732,7 +1846,6 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) return; } - #ifdef ALD_DMA /** * @brief DMA SPI transmit process complete callback. @@ -1741,13 +1854,18 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) */ static void spi_dma_send_cplt(void *arg) { - uint16_t delay; + uint16_t delay, temp; spi_handle_t *hperh = (spi_handle_t *)arg; hperh->tx_count = 0; ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); hperh->state = SPI_STATE_READY; + while ((spi_get_status(hperh, SPI_STATUS_RXE)) == RESET) { + temp = hperh->perh->DATA; + UNUSED(temp); + } + if (hperh->init.dir == SPI_DIRECTION_2LINES) ald_spi_clear_flag_status(hperh, SPI_IF_TXOV); diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c index 11deb8d11bc69f9b228475be1eb1f8e1da47c1bc..49e8ccee2cd9c7796c42097d97746d4b0949e74a 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c @@ -196,13 +196,12 @@ void ald_timer_base_stop_by_it(timer_handle_t *hperh) /** * @brief Starts the TIMER Base generation in DMA mode. * @param hperh: TIMER handle - * @param hdma: Pointer to dma_handle_t. * @param buf: The source Buffer address. * @param len: The length of buffer to be transferred from memory to TIMER peripheral * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, +ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); @@ -216,26 +215,26 @@ ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hd hperh->state = TIMER_STATE_BUSY; - if (hdma->perh == NULL) - hdma->perh = DMA0; - - hdma->cplt_cbk = timer_dma_period_elapse_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; - - ald_dma_config_struct(&hdma->config); - hdma->config.src = (void *)buf; - hdma->config.dst = (void *)&hperh->perh->AR; - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_HALFWORD; - hdma->config.dst_inc = DMA_DATA_INC_NONE; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_UPDATE; - hdma->config.channel = dma_ch; - - timer_dma_msel(hperh->perh, &hdma->config); - ald_dma_config_basic(hdma); + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; + + hperh->hdma1.cplt_cbk = timer_dma_period_elapse_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.dst = (void *)&hperh->perh->AR; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_UPDATE; + hperh->hdma1.config.channel = dma_ch; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE); TIMER_ENABLE(hperh); @@ -447,14 +446,13 @@ void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The source Buffer address. * @param len: The length of buffer to be transferred from memory to TIMER peripheral * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) + uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); @@ -467,54 +465,54 @@ ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch hperh->state = TIMER_STATE_BUSY; - if (hdma->perh == NULL) - hdma->perh = DMA0; + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; - hdma->cplt_cbk = timer_dma_oc_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; + hperh->hdma1.cplt_cbk = timer_dma_oc_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; - ald_dma_config_struct(&hdma->config); - hdma->config.src = (void *)buf; - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_HALFWORD; - hdma->config.dst_inc = DMA_DATA_INC_NONE; - hdma->config.channel = dma_ch; + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.channel = dma_ch; - timer_dma_msel(hperh->perh, &hdma->config); + timer_dma_msel(hperh->perh, &hperh->hdma1.config); switch (ch) { case TIMER_CHANNEL_1: - hdma->config.dst = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - ald_dma_config_basic(hdma); + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); hperh->ch = TIMER_ACTIVE_CHANNEL_1; break; case TIMER_CHANNEL_2: - hdma->config.dst = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - ald_dma_config_basic(hdma); + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); hperh->ch = TIMER_ACTIVE_CHANNEL_2; break; case TIMER_CHANNEL_3: - hdma->config.dst = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - ald_dma_config_basic(hdma); + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); hperh->ch = TIMER_ACTIVE_CHANNEL_3; break; case TIMER_CHANNEL_4: - hdma->config.dst = (void *)&hperh->perh->CCVAL4; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; - ald_dma_config_basic(hdma); + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL4; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); hperh->ch = TIMER_ACTIVE_CHANNEL_4; break; @@ -691,16 +689,15 @@ void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The source Buffer address. * @param len: The length of buffer to be transferred from memory to TIMER peripheral * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) + uint16_t *buf, uint32_t len, uint8_t dma_ch) { - return ald_timer_oc_start_by_dma(hperh, ch, hdma, buf, len, dma_ch); + return ald_timer_oc_start_by_dma(hperh, ch, buf, len, dma_ch); } /** @@ -728,8 +725,12 @@ void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) */ void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) { - uint32_t _arr = ald_cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1; + uint32_t _arr; + if (freq == 0) + return; + + _arr = ald_cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1; WRITE_REG(hperh->perh->AR, _arr); hperh->init.period = _arr; } @@ -966,14 +967,13 @@ void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The destination Buffer address. * @param len: The length of buffer to be transferred TIMER peripheral to memory * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) + uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); @@ -986,53 +986,53 @@ ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch hperh->state = TIMER_STATE_BUSY; - if (hdma->perh == NULL) - hdma->perh = DMA0; + if (hperh->perh == NULL) + hperh->hdma1.perh = DMA0; - hdma->cplt_cbk = timer_dma_capture_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; + hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; - ald_dma_config_struct(&hdma->config); - hdma->config.dst = (void *)buf; - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_NONE; - hdma->config.dst_inc = DMA_DATA_INC_HALFWORD; - hdma->config.channel = dma_ch; + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.dst = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.channel = dma_ch; - timer_dma_msel(hperh->perh, &hdma->config); + timer_dma_msel(hperh->perh, &hperh->hdma1.config); switch (ch) { case TIMER_CHANNEL_1: - hdma->config.src = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - ald_dma_config_basic(hdma); + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); hperh->ch = TIMER_ACTIVE_CHANNEL_1; break; case TIMER_CHANNEL_2: - hdma->config.src = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - ald_dma_config_basic(hdma); + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); hperh->ch = TIMER_ACTIVE_CHANNEL_2; break; case TIMER_CHANNEL_3: - hdma->config.src = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - ald_dma_config_basic(hdma); + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); hperh->ch = TIMER_ACTIVE_CHANNEL_3; break; case TIMER_CHANNEL_4: - hdma->config.src = (void *)&hperh->perh->CCVAL4; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; - ald_dma_config_basic(hdma); + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL4; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); hperh->ch = TIMER_ACTIVE_CHANNEL_4; break; @@ -1447,8 +1447,6 @@ void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected - * @param hdma1: Pointer to dma_handle_t. - * @param hdma2: Pointer to dma_handle_t. * @param buf1: The destination Buffer address. Reading data from CCR1. * @param buf2: The destination Buffer address. Reading data from CCR2. * @param len: The length of buffer to be transferred TIMER peripheral to memory @@ -1457,8 +1455,8 @@ void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @retval Status, see @ref ald_status_t. */ ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, - uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2) + uint16_t *buf1, uint16_t *buf2, uint32_t len, + uint8_t dma_ch1, uint8_t dma_ch2) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); @@ -1469,67 +1467,67 @@ ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel return ERROR; } - if (hdma1->perh == NULL) - hdma1->perh = DMA0; - if (hdma2->perh == NULL) - hdma2->perh = DMA0; + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; + if (hperh->hdma2.perh == NULL) + hperh->hdma2.perh = DMA0; hperh->state = TIMER_STATE_BUSY; - hdma1->cplt_cbk = timer_dma_capture_cplt; - hdma1->cplt_arg = (void *)hperh; - hdma1->err_cbk = timer_dma_error; - hdma1->err_arg = (void *)hperh; + hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; - ald_dma_config_struct(&hdma1->config); - hdma1->config.size = len; - hdma1->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma1->config.src_inc = DMA_DATA_INC_NONE; - hdma1->config.dst_inc = DMA_DATA_INC_HALFWORD; + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; - timer_dma_msel(hperh->perh, &hdma1->config); + timer_dma_msel(hperh->perh, &hperh->hdma1.config); switch (ch) { case TIMER_CHANNEL_1: - hdma1->config.src = (void *)&hperh->perh->CCVAL1; - hdma1->config.dst = (void *)buf1; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hdma1->config.channel = dma_ch1; - ald_dma_config_basic(hdma1); + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch1; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); TIMER_ENABLE(hperh); break; case TIMER_CHANNEL_2: - hdma1->config.src = (void *)&hperh->perh->CCVAL2; - hdma1->config.dst = (void *)buf2; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - hdma1->config.channel = dma_ch2; - ald_dma_config_basic(hdma1); + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.dst = (void *)buf2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hperh->hdma1.config.channel = dma_ch2; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); TIMER_ENABLE(hperh); break; default: - hdma2->cplt_cbk = timer_dma_capture_cplt; - hdma2->cplt_arg = (void *)hperh; - hdma2->err_cbk = timer_dma_error; - hdma2->err_arg = (void *)hperh; - memcpy(&hdma2->config, &hdma1->config, sizeof(dma_config_t)); - - hdma1->config.src = (void *)&hperh->perh->CCVAL1; - hdma1->config.dst = (void *)buf1; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hdma1->config.channel = dma_ch1; - ald_dma_config_basic(hdma1); + hperh->hdma2.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma2.cplt_arg = (void *)hperh; + hperh->hdma2.err_cbk = timer_dma_error; + hperh->hdma2.err_arg = (void *)hperh; + memcpy(&hperh->hdma2.config, &hperh->hdma1.config, sizeof(dma_config_t)); + + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch1; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hdma2->config.src = (void *)&hperh->perh->CCVAL2; - hdma2->config.dst = (void *)buf2; - hdma2->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - hdma2->config.channel = dma_ch2; - ald_dma_config_basic(hdma2); + hperh->hdma2.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma2.config.dst = (void *)buf2; + hperh->hdma2.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hperh->hdma2.config.channel = dma_ch2; + ald_dma_config_basic(&hperh->hdma2); ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); @@ -1708,13 +1706,12 @@ void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh) /** * @brief Starts the TIMER hall sensor interface in DMA mode. * @param hperh: TIMER handle - * @param hdma: Pointer to dma_handle_t. * @param buf: The destination Buffer address. Reading data from CCR1. * @param len: The length of buffer to be transferred TIMER peripheral to memory * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, +ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); @@ -1726,28 +1723,28 @@ ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handl return ERROR; } - if (hdma->perh == NULL) - hdma->perh = DMA0; + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; hperh->state = TIMER_STATE_BUSY; - hdma->cplt_cbk = timer_dma_capture_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; - - ald_dma_config_struct(&hdma->config); - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_NONE; - hdma->config.dst_inc = DMA_DATA_INC_HALFWORD; - - timer_dma_msel(hperh->perh, &hdma->config); - - hdma->config.src = (void *)&hperh->perh->CCVAL1; - hdma->config.dst = (void *)buf; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hdma->config.channel = dma_ch; - ald_dma_config_basic(hdma); + hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); TIMER_ENABLE(hperh); @@ -1929,13 +1926,12 @@ void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The destination Buffer address. Reading data from CCRx. * @param len: The length of buffer to be transferred TIMER peripheral to memory * @param dma_ch: Channel of DMA. * @retval None */ -ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, +ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); @@ -1949,44 +1945,44 @@ ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdm hperh->state = TIMER_STATE_BUSY; - if (hdma->perh == NULL) - hdma->perh = DMA0; + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; - hdma->cplt_cbk = timer_dma_oc_cplt; - hdma->cplt_arg = (void *)hperh; - hdma->err_cbk = timer_dma_error; - hdma->err_arg = (void *)hperh; + hperh->hdma1.cplt_cbk = timer_dma_oc_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; - ald_dma_config_struct(&hdma->config); - hdma->config.src = (void *)buf; - hdma->config.size = len; - hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; - hdma->config.src_inc = DMA_DATA_INC_HALFWORD; - hdma->config.dst_inc = DMA_DATA_INC_NONE; - hdma->config.channel = dma_ch; - hdma->config.msel = DMA_MSEL_TIMER0; + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.channel = dma_ch; + hperh->hdma1.config.msel = DMA_MSEL_TIMER0; switch (ch) { case TIMER_CHANNEL_1: - hdma->config.dst = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - ald_dma_config_basic(hdma); + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); hperh->ch = TIMER_ACTIVE_CHANNEL_1; break; case TIMER_CHANNEL_2: - hdma->config.dst = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - ald_dma_config_basic(hdma); + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); hperh->ch = TIMER_ACTIVE_CHANNEL_2; break; case TIMER_CHANNEL_3: - hdma->config.dst = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - ald_dma_config_basic(hdma); + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); hperh->ch = TIMER_ACTIVE_CHANNEL_3; break; @@ -2136,16 +2132,15 @@ void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @param hdma: Pointer to dma_handle_t. * @param buf: The destination Buffer address. Reading data from CCRx. * @param len: The length of buffer to be transferred TIMER peripheral to memory * @param dma_ch: Channel of DMA. * @retval None */ -ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, +ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) { - return ald_timer_ocn_start_by_dma(hperh, hdma, ch, buf, len, dma_ch); + return ald_timer_ocn_start_by_dma(hperh, ch, buf, len, dma_ch); } /** @@ -2726,6 +2721,7 @@ uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) tmp = hperh->perh->CCVAL4; break; default: + tmp = hperh->perh->CCVAL1; break; } diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c index 59b7d7105c3b699593d99dffda51d497ffc6ece0..200f8db8bceeaa55fcec68743e4f64c9a5bb75fd 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c @@ -76,6 +76,8 @@ ald_status_t ald_trng_init(trng_handle_t *hperh) assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width)); assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type)); assert_param(IS_TRNG_ADJC(hperh->init.adjc)); + assert_param(IS_FUNC_STATE(hperh->init.posten)); + assert_param(IS_TRNG_T_START(hperh->init.t_start)); __LOCK(hperh); trng_reset(hperh); diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c index 1ffae7bf0e732c9b47757c3ad5ae77b7037626b6..b5bbc8534b1a3626ce16ccd2bfe77d1df88268b9 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c @@ -77,8 +77,8 @@ void ald_tsense_init(void) MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, 0x3 << TSENSE_CR_TOM_POSS); MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, 0x1 << TSENSE_PSR_PRS_POSS); - TSENSE->HTGR = 0x1FD0C; - TSENSE->LTGR = 0x21BC1; + TSENSE->HTGR = 0x8564F; + TSENSE->LTGR = 0x87037; tempt = *(volatile uint16_t *)0x80348; temptinv = *(volatile uint16_t *)0x8034A; tscic = *(volatile uint32_t *)0x80350; @@ -90,7 +90,7 @@ void ald_tsense_init(void) } else { TSENSE->TBDR = 0x1E00; - TSENSE->TCALBDR = 0x1FE70; + TSENSE->TCALBDR = 0x1F849; } TSENSE_LOCK(); @@ -160,15 +160,23 @@ ald_status_t ald_tsense_get_value(uint16_t *tsense) while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000)); - if (tmp >= 1000000) + if (tmp >= 1000000) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); return TIMEOUT; + } TSENSE_UNLOCK(); SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); TSENSE_LOCK(); - if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) + if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); return ERROR; + } *tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS); @@ -207,8 +215,12 @@ void ald_tsense_irq_handler(void) SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); TSENSE_LOCK(); - if (__tsense_cbk == NULL) + if (__tsense_cbk == NULL) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); return; + } if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) { TSENSE_UNLOCK(); diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c index 2e5fc5cdd04bf9d82acb06b3e0fa06a236998321..f747967e328e3a1a62ae2e2a647a32a57789a6e1 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c @@ -117,7 +117,7 @@ static void uart_dma_send_cplt(void *arg) ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE); hperh->tx_count = 0; - ald_uart_interrupt_config(hperh, UART_IT_TSEMPTY, ENABLE); + ald_uart_interrupt_config(hperh, UART_IT_TBC, ENABLE); CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); return; @@ -202,12 +202,13 @@ static ald_status_t __uart_send_by_it(uart_handle_t *hperh) if ((hperh->state & UART_STATE_TX_MASK) == 0x0) return BUSY; + while(hperh->perh->STAT & (0x1 << 17)); hperh->perh->TXBUF = (uint8_t)(*hperh->tx_buf++ & 0x00FF); hperh->tx_count++; if (hperh->tx_count >= hperh->tx_size) { ald_uart_interrupt_config(hperh, UART_IT_TFTH, DISABLE); - ald_uart_interrupt_config(hperh, UART_IT_TSEMPTY, ENABLE); + ald_uart_interrupt_config(hperh, UART_IT_TBC, ENABLE); } return OK; @@ -220,12 +221,16 @@ static ald_status_t __uart_send_by_it(uart_handle_t *hperh) */ static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh) { - ald_uart_interrupt_config(hperh, UART_IT_TSEMPTY, DISABLE); + uint32_t cnt = 0xFFFFFF; + + ald_uart_interrupt_config(hperh, UART_IT_TBC, DISABLE); CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + while ((hperh->perh->STAT & UART_STATUS_TSBUSY) && (cnt--)); + ald_uart_clear_flag_status(hperh, UART_IF_TBC); if (hperh->tx_cplt_cbk) hperh->tx_cplt_cbk(hperh); - + return OK; } @@ -239,8 +244,13 @@ static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) if ((hperh->state & UART_STATE_RX_MASK) == 0x0) return BUSY; - *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); - hperh->rx_count++; + while (READ_BITS(hperh->perh->FCON, UART_FCON_RXFL_MSK, UART_FCON_RXFL_POSS)) { + *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + hperh->rx_count++; + + if (hperh->rx_count >= hperh->rx_size) + break; + } if (hperh->rx_count >= hperh->rx_size) { ald_uart_interrupt_config(hperh, UART_IT_RFTH, DISABLE); @@ -252,16 +262,12 @@ static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) return OK; } - - /** * @} */ - /** @defgroup UART_Public_Functions UART Public Functions * @{ */ - /** @defgroup UART_Public_Functions_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @@ -349,7 +355,6 @@ void ald_uart_init(uart_handle_t *hperh) } MODIFY_REG(hperh->perh->MCON, UART_MCON_AFCEN_MSK, hperh->init.fctl << UART_MCON_AFCEN_POS); - hperh->perh->BRR = (ald_cmu_get_pclk1_clock() + (hperh->init.baud >> 1)) / hperh->init.baud; if (hperh->init.mode == UART_MODE_LIN) @@ -421,9 +426,6 @@ void ald_uart_scard_config(uart_handle_t *hperh, uart_scard_config_t *config) return; } - - - /** * @} */ @@ -508,12 +510,13 @@ ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, ui hperh->state = UART_STATE_READY; return TIMEOUT; } - + + while(hperh->perh->STAT & (0x1 << 17)); hperh->perh->TXBUF = (*buf++ & 0xFF); hperh->tx_count++; } - if (uart_wait_flag(hperh, UART_STATUS_TFEMPTY, SET, timeout) != OK) { + if (uart_wait_flag(hperh, UART_STATUS_TSBUSY, RESET, timeout) != OK) { __UNLOCK(hperh); hperh->state = UART_STATE_READY; return TIMEOUT; @@ -599,12 +602,13 @@ ald_status_t ald_uart_send_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t s hperh->state = UART_STATE_READY; return TIMEOUT; } - + + while(hperh->perh->STAT & (0x1 << 17)); hperh->perh->TXBUF = (*buf++ & 0xFF); hperh->tx_count++; } - if (uart_wait_flag(hperh, UART_STATUS_TFEMPTY, SET, timeout) != OK) { + if (uart_wait_flag(hperh, UART_STATUS_TSBUSY, RESET, timeout) != OK) { hperh->state = UART_STATE_READY; return TIMEOUT; } @@ -726,14 +730,14 @@ ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t si * @param t_out: Timeout duration. * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_uart_recv_frame_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t t_out) +ald_status_t ald_uart_recv_frame_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out) { assert_param(IS_UART_ALL(hperh->perh)); if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) return BUSY; - if ((buf == NULL ) || (t_out == 0) || (size == 0)) + if ((buf == NULL ) || (t_out == 0) || (t_out > 0xFFFFFF) || (size == 0)) return ERROR; __LOCK(hperh); @@ -1021,6 +1025,67 @@ void ald_uart_irq_handler(uart_handle_t *hperh) hperh->error_cbk(hperh); } } + +/** + * @brief This function handles UART interrupt request. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval None + */ +void ald_uart_irq_handler_fast(uart_handle_t *hperh) +{ + volatile uint32_t tmp = hperh->perh->IFM; + + /* Transmit */ + if (tmp & 0x8000) { + hperh->perh->ICR = 0x8000; + while(hperh->perh->STAT & (0x1 << 17)); + hperh->perh->TXBUF = *hperh->tx_buf++; + ++hperh->tx_count; + + if (hperh->tx_count >= hperh->tx_size) { + hperh->perh->IDR = 0x8000; + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + } + /* End Transmit */ + if (tmp & 0x10000) { + hperh->perh->ICR = 0x10000; + hperh->perh->IDR = 0x10000; + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + + /* Receive*/ + if (tmp & 0x200) { + hperh->perh->ICR = 0x200; + *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + ++hperh->rx_count; + + if (hperh->rx_count >= hperh->rx_size) { + hperh->perh->IDR = 0x200; + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + } + /* Receive frame */ + if (tmp & 0x10) { + hperh->perh->ICR = 0x10; + hperh->perh->IDR = 0x10; + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return; +} /** * @} */ @@ -1112,17 +1177,15 @@ void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func * @brief Configure transmit fifo parameters. * @param hperh: Pointer to a uart_handle_t structure. * @param config: Transmit fifo trigger level. - * @param level: Transmit fifo level. * @retval None */ -void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config, uint8_t level) +void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_TXFIFO_TYPE(config)); SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK); MODIFY_REG(hperh->perh->FCON, UART_FCON_TXTH_MSK, config << UART_FCON_TXTH_POSS); - MODIFY_REG(hperh->perh->FCON, UART_FCON_TXFL_MSK, config << UART_FCON_TXFL_POSS); return; } @@ -1131,17 +1194,15 @@ void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config, uint8_t * @brief Configure receive fifo parameters. * @param hperh: Pointer to a uart_handle_t structure. * @param config: Receive fifo trigger level. - * @param level: Receive fifo level. * @retval None */ -void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) +void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_RXFIFO_TYPE(config)); SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); MODIFY_REG(hperh->perh->FCON, UART_FCON_RXTH_MSK, config << UART_FCON_RXTH_POSS); - MODIFY_REG(hperh->perh->FCON, UART_FCON_RXFL_MSK, level << UART_FCON_RXFL_POSS); return; } @@ -1176,7 +1237,7 @@ void ald_uart_lin_send_break(uart_handle_t *hperh) assert_param(IS_UART_ALL(hperh->perh)); SET_BIT(hperh->perh->LIN, UART_LIN_LINBKREQ_MSK); - + while(hperh->perh->STAT & (0x1 << 17)); hperh->perh->TXBUF = (0x55); return; @@ -1241,6 +1302,7 @@ ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint3 return TIMEOUT; } + while(hperh->perh->STAT & (0x1 << 17)); WRITE_REG(hperh->perh->TXBUF, (addr | 0x100)); if (uart_wait_flag(hperh, UART_STATUS_TFEMPTY, SET, timeout) != OK) { @@ -1396,16 +1458,13 @@ uint32_t ald_uart_get_error(uart_handle_t *hperh) /** * @} */ - /** * @} */ #endif /* ALD_UART */ - /** * @} */ - /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c index 4749587ddbac7d89726ac2edc011ffe4317fd66d..26605cd791e655b5429a1980a43146b7706691fc 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c @@ -481,16 +481,16 @@ void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags) } if (ep_idx == USB_EP_0) { - USB0->CSR0H = ((USB0->CSR0H & ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | + USB0->CSR0H = (uint8_t)((USB0->CSR0H & ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | (tmp | USB_CSRH0_DTWE)); } else if (flags == USB_EP_HOST_IN) { - USB0->CSR[ep_idx - 1].RXxCSRH = ((USB0->CSR[ep_idx - 1].RXxCSRH & + USB0->CSR[ep_idx - 1].RXxCSRH = (uint8_t)((USB0->CSR[ep_idx - 1].RXxCSRH & ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) | (tmp | USB_RXCSRH1_DTWE)); } else { - USB0->CSR[ep_idx - 1].TXxCSRH = ((USB0->CSR[ep_idx - 1].TXxCSRH & + USB0->CSR[ep_idx - 1].TXxCSRH = (uint8_t)((USB0->CSR[ep_idx - 1].TXxCSRH & ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) | (tmp | USB_TXCSRH1_DTWE)); } @@ -1184,7 +1184,7 @@ void ald_usb_dma_channel_start(uint8_t ch) */ void ald_usb_dma_channel_stop(uint8_t ch) { - USB0->DMA_CH[ch].DMA_CNTL &= ~0x1; + USB0->DMA_CH[ch].DMA_CNTL &= (uint32_t)(~0x1); return; } diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c index 0de76adf1ebd2af9b9540e0808ffc41e16e895ec..bd247fc055eba38a012ab0425f2d8344ec04f3ac 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c @@ -14,6 +14,7 @@ ********************************************************************************* */ +#include #include "utils.h" #include "ald_dma.h" #include "ald_cmu.h" @@ -184,9 +185,12 @@ void ald_systick_interval_select(systick_interval_t value) (+) Waiting for flag (+) Configure the interrupt (+) Provide system tick value - (+) Get CPU ID (+) Initialize core timestamp (+) Get core timestamp + (+) Get CPU ID + (+) Get UID + (+) Get CHIPID + @endverbatim * @{ */ @@ -312,6 +316,22 @@ uint32_t ald_get_ald_version(void) return __ALD_VERSION; } +/** + * @brief Configure the flash wait period. + * @param cycle: The period. + * @retval None + */ +void ald_flash_wait_config(uint8_t cycle) +{ + uint32_t tmp; + + tmp = MSC->MEMWAIT; + MODIFY_REG(tmp, MSC_MEMWAIT_FLASH_W_MSK, (0x30U | cycle) << MSC_MEMWAIT_FLASH_W_POSS); + MSC->MEMWAIT = tmp; + + return; +} + /** * @brief Waiting the specified bit in the register change to SET/RESET. * @param reg: The register address. @@ -380,15 +400,6 @@ void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, t return; } -/** - * @brief Get the CPU ID. - * @retval CPU ID. - */ -uint32_t ald_mcu_get_cpu_id(void) -{ - return SCB->CPUID; -} - /** * @brief Initialize core timestamp. * @retval None @@ -411,6 +422,37 @@ uint32_t ald_mcu_get_timestamp(void) return (uint32_t)DWT_CYCCNT; } +/** + * @brief Get the CPU ID. + * @retval CPU ID. + */ +uint32_t ald_mcu_get_cpu_id(void) +{ + return SCB->CPUID; +} + +/** + * @brief Get the UID. + * @param buf: Pointer to UID, len: 12Bytes(96-bits) + * @retval None + */ +void ald_mcu_get_uid(uint8_t *buf) +{ + memcpy(&buf[0], (void *)MCU_UID0_ADDR, 4); + memcpy(&buf[4], (void *)MCU_UID1_ADDR, 4); + memcpy(&buf[8], (void *)MCU_UID2_ADDR, 4); + + return; +} + +/** + * @brief Get the CHIPID + * @retval CHPID + */ +uint32_t ald_mcu_get_chipid(void) +{ + return (uint32_t)*(uint32_t *)MCU_CHIPID_ADDR; +} /** * @} */ diff --git a/bsp/essemi/es32f369x/project.uvoptx b/bsp/essemi/es32f369x/project.uvoptx index 8d3f54f7f57c43802e344af795ef0131a184de07..9820d88eaacc974c74029f2cc61c08ffa0bc34ad 100644 --- a/bsp/essemi/es32f369x/project.uvoptx +++ b/bsp/essemi/es32f369x/project.uvoptx @@ -73,7 +73,7 @@ 0 - 0 + 1 0 1 @@ -101,7 +101,9 @@ 0 0 1 - 2 + 0 + 0 + 3 @@ -165,7 +167,1039 @@ + + + + + + Applications + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + cpu + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m3\cpuport.c + cpuport.c + 0 + 0 + + + 2 + 6 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m3\context_rvds.S + context_rvds.S + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\can\can.c + can.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\hwtimer\hwtimer.c + hwtimer.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 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+ 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 4 + 27 + 1 + 0 + 0 + 0 + drivers\board.c + board.c + 0 + 0 + + + 4 + 28 + 1 + 0 + 0 + 0 + drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 4 + 29 + 1 + 0 + 0 + 0 + drivers\drv_uart.c + drv_uart.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 5 + 32 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 6 + 33 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\src\device.c + device.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 6 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ald_i2s.c + 0 + 0 + + + 7 + 63 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c + ald_iap.c + 0 + 0 + + + 7 + 64 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c + ald_nand.c + 0 + 0 + + + 7 + 65 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c + ald_nor_lcd.c + 0 + 0 + + + 7 + 66 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c + ald_pis.c + 0 + 0 + + + 7 + 67 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c + ald_pmu.c + 0 + 0 + + + 7 + 68 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c + ald_qspi.c + 0 + 0 + + + 7 + 69 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c + ald_rmu.c + 0 + 0 + + + 7 + 70 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c + ald_rtc.c + 0 + 0 + + + 7 + 71 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c + ald_rtchw.c + 0 + 0 + + + 7 + 72 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c + ald_spi.c + 0 + 0 + + + 7 + 73 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c + ald_sram.c + 0 + 0 + + + 7 + 74 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c + ald_timer.c + 0 + 0 + + + 7 + 75 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c + ald_trng.c + 0 + 0 + + + 7 + 76 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c + ald_tsense.c + 0 + 0 + + + 7 + 77 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c + ald_uart.c + 0 + 0 + + + 7 + 78 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c + ald_usb.c + 0 + 0 + + + 7 + 79 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c + ald_wdt.c + 0 + 0 + + + 7 + 80 + 1 + 0 + 0 + 0 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c + utils.c + 0 + 0 + + + 7 + 81 + 2 + 0 + 0 + 0 + libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s + startup_es32f36xx.s + 0 + 0 + + + diff --git a/bsp/essemi/es32f369x/project.uvprojx b/bsp/essemi/es32f369x/project.uvprojx index 88764924d852dd5977cb8951757205d69a035b2e..bca6765ef1b0560e972c97a0b8b2f965d09694fe 100644 --- a/bsp/essemi/es32f369x/project.uvprojx +++ b/bsp/essemi/es32f369x/project.uvprojx @@ -1,41 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread 0x4 ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 ES32F3696LT Eastsoft - Eastsoft.ES32_DFP.1.0.5 + Eastsoft.ES32_DFP.7.2350 http://www.essemi.com IRAM(0x20000000,0x00018000) IROM(0x00000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0es32f36xx -FS00 -FL080000 -FP0($$Device:ES32F3696LT$Flash\es32f36xx.FLM)) 0 $$Device:ES32F3696LT$Device\Include\es32f36xx.h - - - - - - - - - + + + + + + + + + $$Device:ES32F3696LT$SVD\es32f36xx.svd 0 0 - - - - - + + + + + 0 0 @@ -57,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -67,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -78,14 +83,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -99,8 +104,8 @@ 0 0 3 - - + + 1 @@ -133,11 +138,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -170,7 +175,7 @@ 0 0 "Cortex-M3" - + 0 0 0 @@ -179,6 +184,7 @@ 0 0 0 + 0 0 0 8 @@ -302,7 +308,7 @@ 0x0 - + 1 @@ -319,6 +325,7 @@ 0 0 1 + 0 0 1 1 @@ -328,10 +335,10 @@ 0 0 - + ES32F36xx - - .;..\..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\ES32F36xx\Include;libraries\CMSIS\Include;libraries\ES32F36xx_ALD_StdPeriph_Driver\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common + + applications;.;drivers;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;libraries\CMSIS\Device\EastSoft\ES32F36xx\Include;libraries\CMSIS\Include;libraries\ES32F36xx_ALD_StdPeriph_Driver\Include @@ -346,10 +353,10 @@ 0 0 - - - - + + + + @@ -361,17 +368,271 @@ 0 0x08000000 0x20000000 - - - - - - - + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + cpu + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m3\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m3\context_rvds.S + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + can.c + 1 + ..\..\..\components\drivers\can\can.c + + + hwtimer.c + 1 + ..\..\..\components\drivers\hwtimer\hwtimer.c + + + i2c_core.c + 1 + ..\..\..\components\drivers\i2c\i2c_core.c + + + i2c_dev.c + 1 + ..\..\..\components\drivers\i2c\i2c_dev.c + + + i2c-bit-ops.c + 1 + ..\..\..\components\drivers\i2c\i2c-bit-ops.c + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + adc.c + 1 + ..\..\..\components\drivers\misc\adc.c + + + rt_drv_pwm.c + 1 + ..\..\..\components\drivers\misc\rt_drv_pwm.c + + + pm.c + 1 + ..\..\..\components\drivers\pm\pm.c + + + rtc.c + 1 + ..\..\..\components\drivers\rtc\rtc.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + spi_core.c + 1 + ..\..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\..\components\drivers\spi\spi_dev.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + Kernel @@ -380,92 +641,66 @@ 1 ..\..\..\src\clock.c - - components.c 1 ..\..\..\src\components.c - - device.c 1 ..\..\..\src\device.c - - idle.c 1 ..\..\..\src\idle.c - - ipc.c 1 ..\..\..\src\ipc.c - - irq.c 1 ..\..\..\src\irq.c - - kservice.c 1 ..\..\..\src\kservice.c - - mem.c 1 ..\..\..\src\mem.c - - mempool.c 1 ..\..\..\src\mempool.c - - object.c 1 ..\..\..\src\object.c - - scheduler.c 1 ..\..\..\src\scheduler.c - - signal.c 1 ..\..\..\src\signal.c - - thread.c 1 ..\..\..\src\thread.c - - timer.c 1 @@ -473,40 +708,6 @@ - - Applications - - - main.c - 1 - applications\main.c - - - - - Drivers - - - board.c - 1 - drivers\board.c - - - - - drv_gpio.c - 1 - drivers\drv_gpio.c - - - - - drv_uart.c - 1 - drivers\drv_uart.c - - - Libraries @@ -515,239 +716,171 @@ 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c - - ald_adc.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c - - ald_bkpc.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c - - ald_calc.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c - - ald_can.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c - - ald_cmu.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c - - ald_crc.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c - - ald_crypt.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c - - ald_dac.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c - - ald_dma.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c - - ald_ebi.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c - - ald_flash.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c - - ald_flash_ext.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c - - ald_gpio.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c - - ald_i2c.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c - - ald_i2s.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c - - ald_iap.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c - - ald_nand.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c - - ald_nor_lcd.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c - - ald_pis.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c - - ald_pmu.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c - - ald_qspi.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c - - ald_rmu.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c - - ald_rtc.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c - - ald_rtchw.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c - - ald_spi.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c - - ald_sram.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c - - ald_timer.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c - - ald_trng.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c - - ald_tsense.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c - - ald_uart.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c - - ald_usb.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c - - ald_wdt.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c - - utils.c 1 libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c - - startup_es32f36xx.s 2 @@ -755,140 +888,14 @@ - - cpu - - - backtrace.c - 1 - ..\..\..\libcpu\arm\common\backtrace.c - - - - - div0.c - 1 - ..\..\..\libcpu\arm\common\div0.c - - - - - showmem.c - 1 - ..\..\..\libcpu\arm\common\showmem.c - - - - - cpuport.c - 1 - ..\..\..\libcpu\arm\cortex-m3\cpuport.c - - - - - context_rvds.S - 2 - ..\..\..\libcpu\arm\cortex-m3\context_rvds.S - - - - - DeviceDrivers - - - pin.c - 1 - ..\..\..\components\drivers\misc\pin.c - - - - - serial.c - 1 - ..\..\..\components\drivers\serial\serial.c - - - - - completion.c - 1 - ..\..\..\components\drivers\src\completion.c - - - - - dataqueue.c - 1 - ..\..\..\components\drivers\src\dataqueue.c - - - - - pipe.c - 1 - ..\..\..\components\drivers\src\pipe.c - - - - - ringblk_buf.c - 1 - ..\..\..\components\drivers\src\ringblk_buf.c - - - - - ringbuffer.c - 1 - ..\..\..\components\drivers\src\ringbuffer.c - - - - - waitqueue.c - 1 - ..\..\..\components\drivers\src\waitqueue.c - - - - - workqueue.c - 1 - ..\..\..\components\drivers\src\workqueue.c - - - - - finsh - - - shell.c - 1 - ..\..\..\components\finsh\shell.c - - - - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - - - - - msh.c - 1 - ..\..\..\components\finsh\msh.c - - - + - - - + + + + diff --git a/bsp/essemi/es32f369x/rtconfig.h b/bsp/essemi/es32f369x/rtconfig.h index 546a2b0087784554c4b8d143640c145c8bbd8565..54bd07901b0e5945fe2e66811cb8bea4f5bbe743 100644 --- a/bsp/essemi/es32f369x/rtconfig.h +++ b/bsp/essemi/es32f369x/rtconfig.h @@ -76,7 +76,16 @@ #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_CAN +#define RT_USING_HWTIMER +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS #define RT_USING_PIN +#define RT_USING_ADC +#define RT_USING_PWM +#define RT_USING_PM +#define RT_USING_RTC +#define RT_USING_SPI /* Using USB */ @@ -176,9 +185,14 @@ /* PWM Drivers */ +/* PM Drivers */ + + /* Onboard Peripheral Drivers */ /* Offboard Peripheral Drivers */ +/* Peripheral Drivers test example */ + #endif