From 57630ae4bd634f97e3c1f7b21002ce5283e6b3dc Mon Sep 17 00:00:00 2001 From: Gavin Liu Date: Mon, 16 Sep 2019 18:56:09 +0800 Subject: [PATCH] imxrt:sdram: Add sdram support for imxrt1052-nxp-evk 1. Add sdram item in bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig 2. Add sdram configuration header file for imxrt1052-nxp-evk 3. Update the sdram space assignment for memheap Signed-off-by: Gavin Liu --- bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig | 4 ++ .../board/ports/sdram_port.h | 49 +++++++++++++++++++ bsp/imxrt/libraries/drivers/drv_sdram.c | 13 +++-- 3 files changed, 63 insertions(+), 3 deletions(-) create mode 100644 bsp/imxrt/imxrt1052-nxp-evk/board/ports/sdram_port.h diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig b/bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig index d472ca9d71..c464fa3a28 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig +++ b/bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig @@ -90,6 +90,10 @@ endmenu menu "Onboard Peripheral Drivers" + config BSP_USING_SDRAM + bool "Enable SDRAM" + default n + endmenu menu "Board extended module Drivers" diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/ports/sdram_port.h b/bsp/imxrt/imxrt1052-nxp-evk/board/ports/sdram_port.h new file mode 100644 index 0000000000..477987b4e7 --- /dev/null +++ b/bsp/imxrt/imxrt1052-nxp-evk/board/ports/sdram_port.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-05 zylx The first version for STM32F4xx + * 2019-4-25 misonyo port to IMXRT + */ + +#ifndef SDRAM_PORT_H__ +#define SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ + +#define SDRAM_BANK_ADDR ((uint32_t)0x80000000U) +/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */ +#define SDRAM_REGION kSEMC_SDRAM_CS0 +/* CS pin: kSEMC_MUXCSX0/1/2/3 */ +#define SDRAM_CS_PIN kSEMC_MUXCSX0 +/* size(kbyte):32MB = 32*1024*1KBytes */ +#define SDRAM_SIZE ((uint32_t)0x8000) +/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */ +#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit +/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */ +#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit +/* cas latency clock number: kSEMC_LatencyOne/Two/Three */ +#define SDRAM_CAS_LATENCY kSEMC_LatencyThree + +/* Timing configuration for W9825G6KH */ +/* TRP:precharge to active command time (ns) */ +#define SDRAM_TRP 18 +/* TRCD:active to read/write command delay time (ns) */ +#define SDRAM_TRCD 18 +/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */ +#define SDRAM_REFRESH_RECOVERY 67 +/* TWR:write recovery time (ns). */ +#define SDRAM_TWR 12 +/* TRAS:active to precharge command time (ns). */ +#define SDRAM_TRAS 42 +/* TRC time (ns). */ +#define SDRAM_TRC 60 +/* active to active time (ns). */ +#define SDRAM_ACT2ACT 60 +/* refresh time (ns). 64ms */ +#define SDRAM_REFRESH_ROW 64 * 1000000 / 8192 + +#endif /* SDRAM_PORT_H__ */ diff --git a/bsp/imxrt/libraries/drivers/drv_sdram.c b/bsp/imxrt/libraries/drivers/drv_sdram.c index b4453ad8ff..a0dbe7afe2 100644 --- a/bsp/imxrt/libraries/drivers/drv_sdram.c +++ b/bsp/imxrt/libraries/drivers/drv_sdram.c @@ -66,10 +66,17 @@ int rt_hw_sdram_Init(void) } else { - LOG_D("sdram init success, mapped at 0x%X, size is %d bytes.", SDRAM_BANK_ADDR, SDRAM_SIZE); + LOG_D("sdram init success, mapped at 0x%X, size is %d Kbytes.", SDRAM_BANK_ADDR, SDRAM_SIZE); #ifdef RT_USING_MEMHEAP_AS_HEAP - /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */ - rt_memheap_init(&system_heap, "sdram", (void *)SDRAM_BANK_ADDR, SDRAM_SIZE); + /* + * If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap. + * The heap start address is (base + half size), and the size is (half size - 2M). + * The reasons are: + * 1. Reserve the half space for SDRAM link case + * 2. Reserve the 2M for non-cache space + */ + rt_memheap_init(&system_heap, "sdram", (void *)(SDRAM_BANK_ADDR + (SDRAM_SIZE * 1024)/2), + (SDRAM_SIZE * 1024)/2 - (2 * 1024 * 1024)); #endif } -- GitLab