From 2288481814e18559ce336671310787c2920c5eab Mon Sep 17 00:00:00 2001 From: wangyq2018 Date: Wed, 13 Feb 2019 11:06:34 +0800 Subject: [PATCH] [bsp] add bsp es32f0654 --- bsp/es32f0654/.config | 333 + bsp/es32f0654/Kconfig | 25 + bsp/es32f0654/README.md | 95 + bsp/es32f0654/SConscript | 14 + bsp/es32f0654/SConstruct | 39 + bsp/es32f0654/applications/SConscript | 11 + bsp/es32f0654/applications/main.c | 31 + bsp/es32f0654/drivers/Kconfig | 41 + bsp/es32f0654/drivers/SConscript | 19 + bsp/es32f0654/drivers/board.c | 114 + bsp/es32f0654/drivers/board.h | 36 + bsp/es32f0654/drivers/drv_gpio.c | 490 ++ bsp/es32f0654/drivers/drv_gpio.h | 17 + bsp/es32f0654/drivers/drv_usart.c | 339 + bsp/es32f0654/drivers/drv_usart.h | 17 + bsp/es32f0654/drivers/linker_scripts/link.sct | 14 + .../figures/ES-PDS-ES32F0654-V1.0.jpg | Bin 0 -> 126021 bytes bsp/es32f0654/figures/ESLinkII-mini.jpg | Bin 0 -> 143565 bytes .../CMSIS_END_USER_LICENCE_AGREEMENT.pdf | Bin 0 -> 172641 bytes .../CMSIS_END_USER_LICENCE_AGREEMENT.rtf | 793 ++ .../EastSoft/ES32F065x/Include/es32f065x.h | 6665 +++++++++++++++ .../ES32F065x/Startup/iar/startup_es32f065x.s | 266 + .../Startup/keil/startup_es32f065x.s | 335 + .../ES32F065x/System/system_es32f065x.c | 28 + .../CMSIS/Include/arm_common_tables.h | 136 + .../CMSIS/Include/arm_const_structs.h | 79 + .../libraries/CMSIS/Include/arm_math.h | 7154 +++++++++++++++++ .../libraries/CMSIS/Include/cmsis_armcc.h | 734 ++ .../libraries/CMSIS/Include/cmsis_armcc_V6.h | 1800 +++++ .../libraries/CMSIS/Include/cmsis_gcc.h | 1373 ++++ .../libraries/CMSIS/Include/core_cm0.h | 668 ++ .../libraries/CMSIS/Include/core_cm0plus.h | 914 +++ .../libraries/CMSIS/Include/core_cm3.h | 1763 ++++ .../libraries/CMSIS/Include/core_cm4.h | 1937 +++++ .../libraries/CMSIS/Include/core_cm7.h | 2512 ++++++ .../libraries/CMSIS/Include/core_cmFunc.h | 636 ++ .../libraries/CMSIS/Include/core_cmInstr.h | 688 ++ .../libraries/CMSIS/Include/core_cmSimd.h | 96 + .../libraries/CMSIS/Include/core_sc000.h | 926 +++ .../libraries/CMSIS/Include/core_sc300.h | 1745 ++++ .../libraries/CMSIS/RTOS/Template/cmsis_os.h | 707 ++ bsp/es32f0654/libraries/CMSIS/index.html | 14 + .../Include/ald_acmp.h | 374 + .../Include/ald_adc.h | 585 ++ .../Include/ald_bkpc.h | 186 + .../Include/ald_calc.h | 57 + .../Include/ald_can.h | 485 ++ .../Include/ald_cmu.h | 632 ++ .../Include/ald_conf.h | 55 + .../Include/ald_crc.h | 197 + .../Include/ald_crypt.h | 264 + .../Include/ald_dbgc.h | 160 + .../Include/ald_dma.h | 389 + .../Include/ald_flash.h | 122 + .../Include/ald_gpio.h | 288 + .../Include/ald_i2c.h | 534 ++ .../Include/ald_iap.h | 80 + .../Include/ald_pis.h | 633 ++ .../Include/ald_pmu.h | 241 + .../Include/ald_rmu.h | 265 + .../Include/ald_rtc.h | 699 ++ .../Include/ald_smartcard.h | 279 + .../Include/ald_spi.h | 377 + .../Include/ald_syscfg.h | 107 + .../Include/ald_temp.h | 203 + .../Include/ald_timer.h | 1130 +++ .../Include/ald_trng.h | 182 + .../Include/ald_uart.h | 478 ++ .../Include/ald_usart.h | 580 ++ .../Include/ald_wdt.h | 117 + .../Include/type.h | 127 + .../Include/utils.h | 163 + .../ReleaseNote.html | 14 + .../Source/ald_acmp.c | 331 + .../Source/ald_adc.c | 1345 ++++ .../Source/ald_bkpc.c | 154 + .../Source/ald_calc.c | 121 + .../Source/ald_can.c | 1049 +++ .../Source/ald_cmu.c | 1101 +++ .../Source/ald_crc.c | 342 + .../Source/ald_crypt.c | 1027 +++ .../Source/ald_dma.c | 744 ++ .../Source/ald_flash.c | 530 ++ .../Source/ald_gpio.c | 645 ++ .../Source/ald_i2c.c | 3365 ++++++++ .../Source/ald_iap.c | 149 + .../Source/ald_pis.c | 322 + .../Source/ald_pmu.c | 257 + .../Source/ald_rmu.c | 146 + .../Source/ald_rtc.c | 1229 +++ .../Source/ald_smartcard.c | 937 +++ .../Source/ald_spi.c | 1840 +++++ .../Source/ald_temp.c | 213 + .../Source/ald_timer.c | 3774 +++++++++ .../Source/ald_trng.c | 222 + .../Source/ald_uart.c | 1200 +++ .../Source/ald_usart.c | 2442 ++++++ .../Source/ald_wdt.c | 214 + .../Source/utils.c | 421 + bsp/es32f0654/libraries/SConscript | 28 + bsp/es32f0654/project.uvoptx | 176 + bsp/es32f0654/project.uvprojx | 936 +++ bsp/es32f0654/rtconfig.h | 169 + bsp/es32f0654/rtconfig.py | 135 + bsp/es32f0654/template.uvoptx | 176 + bsp/es32f0654/template.uvprojx | 386 + 106 files changed, 69733 insertions(+) create mode 100644 bsp/es32f0654/.config create mode 100644 bsp/es32f0654/Kconfig create mode 100644 bsp/es32f0654/README.md create mode 100644 bsp/es32f0654/SConscript create mode 100644 bsp/es32f0654/SConstruct create mode 100644 bsp/es32f0654/applications/SConscript create mode 100644 bsp/es32f0654/applications/main.c create mode 100644 bsp/es32f0654/drivers/Kconfig create mode 100644 bsp/es32f0654/drivers/SConscript create mode 100644 bsp/es32f0654/drivers/board.c create mode 100644 bsp/es32f0654/drivers/board.h create mode 100644 bsp/es32f0654/drivers/drv_gpio.c create mode 100644 bsp/es32f0654/drivers/drv_gpio.h create mode 100644 bsp/es32f0654/drivers/drv_usart.c create mode 100644 bsp/es32f0654/drivers/drv_usart.h create mode 100644 bsp/es32f0654/drivers/linker_scripts/link.sct create mode 100644 bsp/es32f0654/figures/ES-PDS-ES32F0654-V1.0.jpg create mode 100644 bsp/es32f0654/figures/ESLinkII-mini.jpg create mode 100644 bsp/es32f0654/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf create mode 100644 bsp/es32f0654/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf create mode 100644 bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s create mode 100644 bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s create mode 100644 bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/System/system_es32f065x.c create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/arm_common_tables.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/arm_const_structs.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/arm_math.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc_V6.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/cmsis_gcc.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/core_cm0.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/core_cm0plus.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/core_cm3.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/core_cm4.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/core_cm7.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/core_cmFunc.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/core_cmInstr.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/core_cmSimd.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/core_sc000.h create mode 100644 bsp/es32f0654/libraries/CMSIS/Include/core_sc300.h create mode 100644 bsp/es32f0654/libraries/CMSIS/RTOS/Template/cmsis_os.h create mode 100644 bsp/es32f0654/libraries/CMSIS/index.html create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_temp.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/ReleaseNote.html create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_temp.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c create mode 100644 bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c create mode 100644 bsp/es32f0654/libraries/SConscript create mode 100644 bsp/es32f0654/project.uvoptx create mode 100644 bsp/es32f0654/project.uvprojx create mode 100644 bsp/es32f0654/rtconfig.h create mode 100644 bsp/es32f0654/rtconfig.py create mode 100644 bsp/es32f0654/template.uvoptx create mode 100644 bsp/es32f0654/template.uvprojx diff --git a/bsp/es32f0654/.config b/bsp/es32f0654/.config new file mode 100644 index 0000000000..6e404d1fde --- /dev/null +++ b/bsp/es32f0654/.config @@ -0,0 +1,333 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +CONFIG_RT_VER_NUM=0x40001 +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_STM32F4_HAL is not set +# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set +CONFIG_SOC_ES32F0654LT=y + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y + +# +# UART Drivers +# +# CONFIG_BSP_USING_UART0 is not set +# CONFIG_BSP_USING_UART1 is not set +CONFIG_BSP_USING_UART2=y +# CONFIG_BSP_USING_UART3 is not set + +# +# Onboard Peripheral Drivers +# + +# +# Offboard Peripheral Drivers +# diff --git a/bsp/es32f0654/Kconfig b/bsp/es32f0654/Kconfig new file mode 100644 index 0000000000..f04098be6f --- /dev/null +++ b/bsp/es32f0654/Kconfig @@ -0,0 +1,25 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_ES32F0654LT + bool + default y + +source "drivers/Kconfig" diff --git a/bsp/es32f0654/README.md b/bsp/es32f0654/README.md new file mode 100644 index 0000000000..d1436a2a30 --- /dev/null +++ b/bsp/es32f0654/README.md @@ -0,0 +1,95 @@ +# ES-PDS-ES32F0654 开发板 BSP 说明 +标签： EastSoft、国产MCU、Cortex-M0、ES32F0654LT + +## 1. 简介 + +本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F0654 开发板提供的 BSP (板级支持包) 说明。 +通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +### 1.1 开发板介绍 + +主要内容如下： +ES-PDS-ES32F0654 是东软载波微电子官方推出的一款基于 ARM Cortex-M0 内核的开发板，最高主频为 48Mhz(实际使用24Mhz)，可满足基础功能测试及高端功能扩展等开发需求。 + +开发板外观如下图所示： + +ES-PDS-ES32F0654-V1.0 + +![ES32F0654](figures/ES-PDS-ES32F0654-V1.0.jpg) + +该开发板常用 **板载资源** 如下： + +- MCU：ES32F0654LT，主频 24MHz，256KB FLASH，32KB RAM，54 GPIOs +- 外部 FLASH：W25Q128（SPI，16MB）、EEPROM（24c02） +- 常用外设 + - LED：2个，(红色，PC8-PC9) + - 按键：3个，K1(PF00)，K2（PF01)，RESET(MRST) +- 常用接口：串口、GPIO、SPI、I2C +- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载 + +外设支持: + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :---------------- | :----------: | :------------------------------------ | +| GPIO | 支持 | 54 GPIOs | +| UART | 支持 | UART0/1/2/3 | + +| **片上外设** | **支持情况** | **备注** | + +| **扩展模块** | **支持情况** | **备注** | + +更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/) + +## 2. 快速上手 + +本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +### 硬件连接 + +使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART2_TX(PC12)、UART2_RX(PD2)、GND 接到串口工具上。 + +使用ESlinkⅡ(mini)连接开发板如下图所示： + +ESLinkⅡ(mini) + ES-PDS-ES32F0654-V1.0 + +![ESLinkII](figures/ESLinkII-mini.jpg) + +### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。 + +### 运行结果 + +下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。 + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Jan 28 2019 + 2006 - 2018 Copyright by rt-thread team +msh > +``` +## 3. 进阶使用 + +此 BSP 默认只开启了 GPIO 和 uart2 的功能，如果需使用 Flash 等更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/) + +## 4. 联系人信息 + +- [wangyongquan](https://github.com/wangyq2018) + +## 5. 参考 + +- [ EastSoft 官网](http://www.essemi.com) + diff --git a/bsp/es32f0654/SConscript b/bsp/es32f0654/SConscript new file mode 100644 index 0000000000..468297b6a9 --- /dev/null +++ b/bsp/es32f0654/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +objs = [] +cwd = str(Dir('#')) +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/es32f0654/SConstruct b/bsp/es32f0654/SConstruct new file mode 100644 index 0000000000..713fe15443 --- /dev/null +++ b/bsp/es32f0654/SConstruct @@ -0,0 +1,39 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/es32f0654/applications/SConscript b/bsp/es32f0654/applications/SConscript new file mode 100644 index 0000000000..e0c84e8f14 --- /dev/null +++ b/bsp/es32f0654/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') + +CPPPATH = [cwd, str(Dir('#'))] +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/es32f0654/applications/main.c b/bsp/es32f0654/applications/main.c new file mode 100644 index 0000000000..ad340b6989 --- /dev/null +++ b/bsp/es32f0654/applications/main.c @@ -0,0 +1,31 @@ +/* + * File : main.c + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-28 wangyq first implementation + */ + +#include +#include + +#define LED_PIN 39 + +int main(void) +{ + int count = 1; + /* set PC08 pin mode to output */ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + return RT_EOK; +} diff --git a/bsp/es32f0654/drivers/Kconfig b/bsp/es32f0654/drivers/Kconfig new file mode 100644 index 0000000000..e175649d01 --- /dev/null +++ b/bsp/es32f0654/drivers/Kconfig @@ -0,0 +1,41 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menu "UART Drivers" + config BSP_USING_UART0 + bool "Enable UART0 PB10/PB11(T/R)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART1 + bool "Enable UART1 PC10/PC11(T/R)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART2 + bool "Enable UART2 PC12/PD02(T/R)" + select RT_USING_SERIAL + default y + + config BSP_USING_UART3 + bool "Enable UART3 PC04/PC05(T/R)" + select RT_USING_SERIAL + default n + endmenu + + endmenu + + menu "Onboard Peripheral Drivers" + + endmenu + + menu "Offboard Peripheral Drivers" + + endmenu + +endmenu diff --git a/bsp/es32f0654/drivers/SConscript b/bsp/es32f0654/drivers/SConscript new file mode 100644 index 0000000000..81e6b3f8e2 --- /dev/null +++ b/bsp/es32f0654/drivers/SConscript @@ -0,0 +1,19 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(''' +board.c +''') + +# add gpio drivers. +if GetDepend('RT_USING_PIN'): + src += ['drv_gpio.c'] +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_usart.c'] + +CPPPATH = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/es32f0654/drivers/board.c b/bsp/es32f0654/drivers/board.c new file mode 100644 index 0000000000..cb177829e2 --- /dev/null +++ b/bsp/es32f0654/drivers/board.c @@ -0,0 +1,114 @@ +/* + * File : board.c + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-23 wangyq the first version + */ + +#include +#include +#include "board.h" +#include "drv_usart.h" +#include "drv_gpio.h" +#include +#include + +/** + * @addtogroup es32f0 + */ + +/*@{*/ + +/******************************************************************************* +* Function Name : NVIC_Configuration +* Description : Configures Vector Table base location. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_Configuration(void) +{ +} + +/******************************************************************************* + * Function Name : SystemClock_Configuration + * Description : Configures the System Clock. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SystemClock_Config(void) +{ + /* hosc 8MHz, from hosc/2 pll to 48MHz */ + cmu_pll1_config(CMU_PLL1_INPUT_HOSC_2, CMU_PLL1_OUTPUT_48M); + + /* MCLK 48MHz*/ + cmu_clock_config(CMU_CLOCK_PLL1, 48000000); + + /* SYSCLK 24MHz */ + cmu_div_config(CMU_SYS, CMU_DIV_2); +} + +/******************************************************************************* + * Function Name : SysTick_Configuration + * Description : Configures the SysTick for OS tick. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SysTick_Configuration(void) +{ + rt_uint32_t _mclk; + rt_uint32_t _sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + + /* get hrc clock*/ + _mclk = cmu_get_clock(); + + /* SYSCLK = MCLK/SYSDIV */ + SysTick_Config(_mclk / (RT_TICK_PER_SECOND << _sys_div)); +} + +/** + * This is the timer interrupt service routine. + * + */ +void systick_irq_cbk(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/*@}*/ +/** + * This function will initial ES32F0 board. + */ +void rt_hw_board_init(void) +{ + /* NVIC Configuration */ + NVIC_Configuration(); + + /*System Clock Configuration */ + SystemClock_Config(); + + /* Configure the SysTick */ + SysTick_Configuration(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} diff --git a/bsp/es32f0654/drivers/board.h b/bsp/es32f0654/drivers/board.h new file mode 100644 index 0000000000..5b27f1208b --- /dev/null +++ b/bsp/es32f0654/drivers/board.h @@ -0,0 +1,36 @@ +/* + * File : board.h + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-23 wangyq the first version + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#define ES32F0_SRAM_SIZE 0x8000 +#define ES32F0_SRAM_END (0x20000000 + ES32F0_SRAM_SIZE) + +#ifdef __CC_ARM + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section="HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END ES32F0_SRAM_END + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/es32f0654/drivers/drv_gpio.c b/bsp/es32f0654/drivers/drv_gpio.c new file mode 100644 index 0000000000..09171d93ae --- /dev/null +++ b/bsp/es32f0654/drivers/drv_gpio.c @@ -0,0 +1,490 @@ +/* + * File : drv_gpio.c + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-23 wangyq the first version + */ + +#include +#include +#include "board.h" +#include "drv_gpio.h" +#include +#include + +#ifdef RT_USING_PIN + +#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index} +#define __ES32F0_PIN_DEFAULT {-1, 0, 0} + +/* ES32F0 GPIO driver */ +struct pin_index +{ + int index; + GPIO_TypeDef *gpio; + uint32_t pin; +}; + +static const struct pin_index pins[] = +{ + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(2, C, 13), + __ES32F0_PIN(3, C, 14), + __ES32F0_PIN(4, C, 15), + __ES32F0_PIN(5, H, 0), + __ES32F0_PIN(6, H, 1), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(8, C, 0), + __ES32F0_PIN(9, C, 1), + __ES32F0_PIN(10, C, 2), + __ES32F0_PIN(11, C, 3), + __ES32F0_PIN(12, H, 3), + __ES32F0_PIN(13, H, 4), + __ES32F0_PIN(14, A, 0), + __ES32F0_PIN(15, A, 1), + __ES32F0_PIN(16, A, 2), + __ES32F0_PIN(17, A, 3), + __ES32F0_PIN(18, F, 0), + __ES32F0_PIN(19, F, 1), + __ES32F0_PIN(20, A, 4), + __ES32F0_PIN(21, A, 5), + __ES32F0_PIN(22, A, 6), + __ES32F0_PIN(23, A, 7), + __ES32F0_PIN(24, C, 4), + __ES32F0_PIN(25, C, 5), + __ES32F0_PIN(26, B, 0), + __ES32F0_PIN(27, B, 1), + __ES32F0_PIN(28, B, 2), + __ES32F0_PIN(29, B, 10), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(33, B, 12), + __ES32F0_PIN(34, B, 13), + __ES32F0_PIN(35, B, 14), + __ES32F0_PIN(36, B, 15), + __ES32F0_PIN(37, C, 6), + __ES32F0_PIN(38, C, 7), + __ES32F0_PIN(39, C, 8), + __ES32F0_PIN(40, C, 9), + __ES32F0_PIN(41, A, 8), + __ES32F0_PIN(42, A, 9), + __ES32F0_PIN(43, A, 10), + __ES32F0_PIN(44, A, 11), + __ES32F0_PIN(45, A, 12), + __ES32F0_PIN(46, A, 13), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(49, A, 14), + __ES32F0_PIN(50, A, 15), + __ES32F0_PIN(51, C, 10), + __ES32F0_PIN(52, C, 11), + __ES32F0_PIN(53, C, 12), + __ES32F0_PIN(54, D, 2), + __ES32F0_PIN(55, B, 3), + __ES32F0_PIN(56, B, 4), + __ES32F0_PIN(57, B, 5), + __ES32F0_PIN(58, B, 6), + __ES32F0_PIN(59, B, 7), + __ES32F0_PIN(60, H, 2), + __ES32F0_PIN(61, B, 8), + __ES32F0_PIN(62, B, 9), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EXTI0_3_IRQn}, + {GPIO_PIN_1, EXTI0_3_IRQn}, + {GPIO_PIN_2, EXTI0_3_IRQn}, + {GPIO_PIN_3, EXTI0_3_IRQn}, + {GPIO_PIN_4, EXTI4_7_IRQn}, + {GPIO_PIN_5, EXTI4_7_IRQn}, + {GPIO_PIN_6, EXTI4_7_IRQn}, + {GPIO_PIN_7, EXTI4_7_IRQn}, + {GPIO_PIN_8, EXTI8_11_IRQn}, + {GPIO_PIN_9, EXTI8_11_IRQn}, + {GPIO_PIN_10, EXTI8_11_IRQn}, + {GPIO_PIN_11, EXTI8_11_IRQn}, + {GPIO_PIN_12, EXTI12_15_IRQn}, + {GPIO_PIN_13, EXTI12_15_IRQn}, + {GPIO_PIN_14, EXTI12_15_IRQn}, + {GPIO_PIN_15, EXTI12_15_IRQn}, +}; + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + return index; +}; + +void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + gpio_write_pin(index->gpio, index->pin, value); +} + +int es32f0_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + value = PIN_LOW; + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + value = gpio_read_pin(index->gpio, index->pin); + return value; +} + +void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + gpio_init_t gpio_initstruct; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* Configure GPIO_InitStructure */ + gpio_initstruct.mode = GPIO_MODE_OUTPUT; + gpio_initstruct.func = GPIO_FUNC_1; + gpio_initstruct.odrv = GPIO_OUT_DRIVE_NORMAL; + gpio_initstruct.type = GPIO_TYPE_CMOS; + gpio_initstruct.pupd = GPIO_FLOATING; + gpio_initstruct.odos = GPIO_PUSH_PULL; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + gpio_initstruct.mode = GPIO_MODE_OUTPUT; + gpio_initstruct.pupd = GPIO_FLOATING; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + gpio_initstruct.mode = GPIO_MODE_INPUT; + gpio_initstruct.pupd = GPIO_FLOATING; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + gpio_initstruct.mode = GPIO_MODE_INPUT; + gpio_initstruct.pupd = GPIO_PUSH_UP; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + gpio_initstruct.mode = GPIO_MODE_INPUT; + gpio_initstruct.pupd = GPIO_PUSH_DOWN; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + gpio_initstruct.mode = GPIO_MODE_OUTPUT; + gpio_initstruct.pupd = GPIO_FLOATING; + gpio_initstruct.odos = GPIO_OPEN_DRAIN; + } + gpio_init(index->gpio, index->pin, &gpio_initstruct); +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin) +{ + rt_int32_t mapindex = gpio_pin & 0x00FF; + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; + +rt_err_t es32f0_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + /**pin no. convert to dec no.**/ + for (irqindex = 0; irqindex < 16; irqindex++) + { + if ((0x01 << irqindex) == index->pin) + { + break; + } + } + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +rt_err_t es32f0_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = index->pin & 0x00FF; + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + /*Configure GPIO_InitStructure & EXTI_InitStructure*/ + gpio_init_t gpio_initstruct; + exti_init_t exti_initstruct; + exti_initstruct.filter = DISABLE; + exti_initstruct.cks = EXTI_FILTER_CLOCK_10K; + exti_initstruct.filter_time = 0x0; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + if (enabled == PIN_IRQ_ENABLE) + { + /**pin no. convert to dec no.**/ + for (irqindex = 0; irqindex < 16; irqindex++) + { + if ((0x01 << irqindex) == index->pin) + { + break; + } + } + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + irqmap = &pin_irq_map[irqindex]; + gpio_exti_init(index->gpio, index->pin, &exti_initstruct); + /* Configure GPIO_InitStructure */ + gpio_initstruct.mode = GPIO_MODE_INPUT; + gpio_initstruct.func = GPIO_FUNC_1; + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + gpio_initstruct.pupd = GPIO_PUSH_DOWN; + gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE); + break; + case PIN_IRQ_MODE_FALLING: + gpio_initstruct.pupd = GPIO_PUSH_UP; + gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE); + break; + case PIN_IRQ_MODE_RISING_FALLING: + gpio_initstruct.pupd = GPIO_FLOATING; + gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE); + break; + } + gpio_init(index->gpio, index->pin, &gpio_initstruct); + NVIC_EnableIRQ(irqmap->irqno); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_ENOSYS; + } + NVIC_DisableIRQ(irqmap->irqno); + } + else + { + return RT_ENOSYS; + } + return RT_EOK; +} + +const static struct rt_pin_ops _es32f0_pin_ops = +{ + es32f0_pin_mode, + es32f0_pin_write, + es32f0_pin_read, + es32f0_pin_attach_irq, + es32f0_pin_detach_irq, + es32f0_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + int result; + cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); + result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) +{ + uint16_t irqno; + /**pin no. convert to dec no.**/ + for (irqno = 0; irqno < 16; irqno++) + { + if ((0x01 << irqno) == GPIO_Pin) + { + break; + } + } + if (irqno == 16) + return; + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + if (gpio_exti_get_flag_status(GPIO_Pin) != RESET) + { + gpio_exti_clear_flag_status(GPIO_Pin); + pin_irq_hdr(GPIO_Pin); + } +} + +void EXTI0_3_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_0); + GPIO_EXTI_Callback(GPIO_PIN_1); + GPIO_EXTI_Callback(GPIO_PIN_2); + GPIO_EXTI_Callback(GPIO_PIN_3); + rt_interrupt_leave(); +} + +void EXTI4_7_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_4); + GPIO_EXTI_Callback(GPIO_PIN_5); + GPIO_EXTI_Callback(GPIO_PIN_6); + GPIO_EXTI_Callback(GPIO_PIN_7); + rt_interrupt_leave(); +} + +void EXTI8_11_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_8); + GPIO_EXTI_Callback(GPIO_PIN_9); + GPIO_EXTI_Callback(GPIO_PIN_10); + GPIO_EXTI_Callback(GPIO_PIN_11); + rt_interrupt_leave(); +} + +void EXTI12_15_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_12); + GPIO_EXTI_Callback(GPIO_PIN_13); + GPIO_EXTI_Callback(GPIO_PIN_14); + GPIO_EXTI_Callback(GPIO_PIN_15); + rt_interrupt_leave(); +} + +#endif diff --git a/bsp/es32f0654/drivers/drv_gpio.h b/bsp/es32f0654/drivers/drv_gpio.h new file mode 100644 index 0000000000..869300b792 --- /dev/null +++ b/bsp/es32f0654/drivers/drv_gpio.h @@ -0,0 +1,17 @@ +/* + * File : drv_gpio.h + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-23 wangyq the first version + */ + +#ifndef DRV_GPIO_H__ +#define DRV_GPIO_H__ + +int rt_hw_pin_init(void); + +#endif diff --git a/bsp/es32f0654/drivers/drv_usart.c b/bsp/es32f0654/drivers/drv_usart.c new file mode 100644 index 0000000000..144f59d49d --- /dev/null +++ b/bsp/es32f0654/drivers/drv_usart.c @@ -0,0 +1,339 @@ +/* + * File : drv_usart.c + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-23 wangyq the first version + */ + +#include +#include +#include +#include "board.h" +#include "drv_usart.h" +#include +#include + +#ifdef RT_USING_SERIAL + +/* es32 uart driver */ +struct es32_uart +{ + uart_handle_t huart; + IRQn_Type irq; +}; + +static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + gpio_init_t gpio_init_initstructure; + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + /* Initialize tx pin */ + gpio_init_initstructure.mode = GPIO_MODE_OUTPUT; + gpio_init_initstructure.odos = GPIO_PUSH_PULL; + gpio_init_initstructure.pupd = GPIO_PUSH_UP; + gpio_init_initstructure.odrv = GPIO_OUT_DRIVE_NORMAL; + gpio_init_initstructure.flt = GPIO_FILTER_DISABLE; + gpio_init_initstructure.type = GPIO_TYPE_TTL; + +#ifdef BSP_USING_UART0 + + gpio_init_initstructure.func = GPIO_FUNC_3; + gpio_init(GPIOB, GPIO_PIN_10, &gpio_init_initstructure); + + /* Initialize rx pin ,the same as txpin except mode*/ + gpio_init_initstructure.mode = GPIO_MODE_INPUT; + gpio_init(GPIOB, GPIO_PIN_11, &gpio_init_initstructure); + + NVIC_EnableIRQ(UART0_IRQn); + +#endif /* uart0 gpio init */ + +#ifdef BSP_USING_UART1 + + gpio_init_initstructure.func = GPIO_FUNC_3; + gpio_init(GPIOC, GPIO_PIN_10, &gpio_init_initstructure); + + /* Initialize rx pin ,the same as txpin except mode*/ + gpio_init_initstructure.mode = GPIO_MODE_INPUT; + gpio_init(GPIOC, GPIO_PIN_11, &gpio_init_initstructure); + + NVIC_EnableIRQ(UART1_IRQn); + +#endif /* uart1 gpio init */ + +#ifdef BSP_USING_UART2 + + gpio_init_initstructure.func = GPIO_FUNC_5; + gpio_init(GPIOC, GPIO_PIN_12, &gpio_init_initstructure); + + /* Initialize rx pin ,the same as txpin except mode*/ + gpio_init_initstructure.mode = GPIO_MODE_INPUT; + gpio_init(GPIOD, GPIO_PIN_2, &gpio_init_initstructure); + + NVIC_EnableIRQ(BS16T1_UART2_IRQn); + +#endif /* uart2 gpio init */ + +#ifdef BSP_USING_UART3 + + gpio_init_initstructure.func = GPIO_FUNC_4; + gpio_init(GPIOC, GPIO_PIN_4, &gpio_init_initstructure); + + /* Initialize rx pin ,the same as txpin except mode*/ + gpio_init_initstructure.mode = GPIO_MODE_INPUT; + gpio_init(GPIOC, GPIO_PIN_5, &gpio_init_initstructure); + + NVIC_EnableIRQ(BS16T2_UART3_IRQn); + +#endif /* uart3 gpio init */ + + uart->huart.init.mode = UART_MODE_UART; + uart->huart.init.baud = cfg->baud_rate; + uart->huart.init.word_length = (uart_word_length_t)(cfg->data_bits - 5); + uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); + uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; + uart_init(&uart->huart); + + if (cfg->bit_order == BIT_ORDER_MSB) + { + UART_MSB_FIRST_ENABLE(&uart->huart); + } + else + { + UART_MSB_FIRST_DISABLE(&uart->huart); + } + + if (cfg->invert == NRZ_INVERTED) + { + UART_DATA_INV_ENABLE(&uart->huart); + } + else + { + UART_DATA_INV_DISABLE(&uart->huart); + } + + /*enable rx int*/ + uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); + + return RT_EOK; +} + +static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = (struct es32_uart *)serial->parent.user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + /* disable interrupt */ + uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + /* enable interrupt */ + uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); + break; + } + + return RT_EOK; +} + +static int es32f0x_putc(struct rt_serial_device *serial, char c) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + while (!(uart->huart.perh->SR & 0x40)) ; + WRITE_REG(uart->huart.perh->TBR, c); + + return 1; +} + +static int es32f0x_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct es32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + if (uart->huart.perh->SR & 0x01) + { + ch = (uint8_t)(uart->huart.perh->RBR & 0xFF); + } + + return ch; +} + +static const struct rt_uart_ops es32f0x_uart_ops = +{ + es32f0x_configure, + es32f0x_control, + es32f0x_putc, + es32f0x_getc, +}; + +#ifdef BSP_USING_UART0 +/* UART0 device driver structure */ +struct es32_uart uart0 = +{ + {UART0}, + UART0_IRQn +}; + +struct rt_serial_device serial0; + +void UART0_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (UART0->RIF & 0x01) + { + rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART0 */ + +#ifdef BSP_USING_UART1 +/* UART1 device driver structure */ +struct es32_uart uart1 = +{ + {UART1}, + UART1_IRQn +}; + +struct rt_serial_device serial1; + +void UART1_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (UART1->RIF & 0x01) + { + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 +/* UART2 device driver structure */ +struct es32_uart uart2 = +{ + {UART2}, + BS16T1_UART2_IRQn +}; + +struct rt_serial_device serial2; + +void BS16T1_UART2_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (UART2->RIF & 0x01) + { + rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART3 +/* UART3 device driver structure */ +struct es32_uart uart3 = +{ + {UART3}, + BS16T2_UART3_IRQn +}; + +struct rt_serial_device serial3; + +void BS16T2_UART3_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (UART3->RIF & 0x01) + { + rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +int rt_hw_usart_init(void) +{ + struct es32_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef BSP_USING_UART0 + uart = &uart0; + serial0.ops = &es32f0x_uart_ops; + serial0.config = config; + + /* register UART0 device */ + rt_hw_serial_register(&serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART0 */ + +#ifdef BSP_USING_UART1 + uart = &uart1; + serial1.ops = &es32f0x_uart_ops; + serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 + uart = &uart2; + serial2.ops = &es32f0x_uart_ops; + serial2.config = config; + + /* register UART2 device */ + rt_hw_serial_register(&serial2, "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART3 + uart = &uart3; + serial3.ops = &es32f0x_uart_ops; + serial3.config = config; + + /* register UART3 device */ + rt_hw_serial_register(&serial3, "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART3 */ + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_usart_init); + +#endif diff --git a/bsp/es32f0654/drivers/drv_usart.h b/bsp/es32f0654/drivers/drv_usart.h new file mode 100644 index 0000000000..cd7391c7ce --- /dev/null +++ b/bsp/es32f0654/drivers/drv_usart.h @@ -0,0 +1,17 @@ +/* + * File : drv_usart.h + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-23 wangyq the first version + */ + +#ifndef DRV_USART_H__ +#define DRV_USART_H__ + +int rt_hw_usart_init(void); + +#endif diff --git a/bsp/es32f0654/drivers/linker_scripts/link.sct b/bsp/es32f0654/drivers/linker_scripts/link.sct new file mode 100644 index 0000000000..2e4d8a774f --- /dev/null +++ b/bsp/es32f0654/drivers/linker_scripts/link.sct @@ -0,0 +1,14 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00040000 { ; load region size_region + ER_IROM1 0x00000000 0x00040000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00008000 { ; RW data + .ANY (+RW +ZI) + } +} diff --git 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zMVcWTn+Y~91)E3qo)a-%o{CuU`2jnByV@3f!>Hy;bTFgu?BKL>{}KMNZ(2L~TNBR@T>0HYv- zprDW-2haa^j@Jf+O)VS@?dXIpemK0wGS{~@FrqboW9t5}ZL$2d5#eL8@w~{bA%y z(`y?xAgdmT2ntsonx7(@+=f|2ol^9{3%SVjqg@k$@uG;ra#7BP$V4xuwC!gqe3y_R zK2xe0w}z}OsCi8jf!&FW-39Te#ZiecXZ?}{f!2@($(aS$lm!jULgF4r(nj~@Lw}D4 z-$fDDP9E05F6oU&O7KqM^9N}D&jFtV2|gNs4m3^tsg~&Ls_HGI>SHL{&O!VGs;UB( zLbMChqMg&CgVaD5%dP^lxdPgi{5!IE1(IRm{7JdT!QwL8Vxq>1f&Gq(nWGEp9h5OC z)ytb>>SAYTgaAwbI(!_jKmPk-WWr}`edVi2qq1 zJ2M;eUm6SZtFQkf9~;MCws6oh|I=m$RtDyO_6q|mGyOlyGBR+m|D`c9vi-9xBQrb4 zKW$-T=3x0J2O|qT{a^h|PtVBw_gKD;+h60$$ohuH_J+p(hQ{%?#zg;y#_)#5_=fg| z|1rJ6@#>*}aWK8X@#c8yqZeaIn6?@j6HR)duSu z9IS6}u)e{;`UVH<8yu`}aIn6?@j5sCWgpuc9BglJu)V>-_6Eo69QJn`Z*Z`^!SOm5 z|6TSC4z@Qq*x%rIo!9=VkNph}_BS}#-{4?>gMwNkj+Uvs2`Z_oLZ_UB(hpC03 z9Rlp@7W2P1mK^`T? +#include "core_cm0.h" + +#if defined (__CC_ARM) +#pragma anon_unions +#endif + +/* Peripheral register define */ + +/****************** Bit definition for SYSCFG_PROT register ************************/ + +#define SYSCFG_PROT_KEY_POSS 1U +#define SYSCFG_PROT_KEY_POSE 31U +#define SYSCFG_PROT_KEY_MSK BITS(SYSCFG_PROT_KEY_POSS,SYSCFG_PROT_KEY_POSE) + +#define SYSCFG_PROT_PROT_POS 0U +#define SYSCFG_PROT_PROT_MSK BIT(SYSCFG_PROT_PROT_POS) + +/****************** Bit definition for SYSCFG_MEMRMP register ************************/ + +#define SYSCFG_MEMRMP_VTOEN_POS 16U +#define SYSCFG_MEMRMP_VTOEN_MSK BIT(SYSCFG_MEMRMP_VTOEN_POS) + +#define SYSCFG_MEMRMP_BFRMPEN_POS 8U +#define SYSCFG_MEMRMP_BFRMPEN_MSK BIT(SYSCFG_MEMRMP_BFRMPEN_POS) + +#define SYSCFG_MEMRMP_BRRMPEN_POS 0U +#define SYSCFG_MEMRMP_BRRMPEN_MSK BIT(SYSCFG_MEMRMP_BRRMPEN_POS) + +/****************** Bit definition for SYSCFG_VTOR register ************************/ + +#define SYSCFG_VTOR_VTO_POSS 0U +#define SYSCFG_VTOR_VTO_POSE 29U +#define SYSCFG_VTOR_VTO_MSK BITS(SYSCFG_VTOR_VTO_POSS,SYSCFG_VTOR_VTO_POSE) + +typedef struct +{ + __IO uint32_t PROT; + __IO uint32_t MEMRMP; + __IO uint32_t VTOR; +} SYSCFG_TypeDef; + +/****************** Bit definition for MSC_FLASHKEY register ************************/ + +#define MSC_FLASHKEY_STATUS_POSS 0U +#define MSC_FLASHKEY_STATUS_POSE 1U +#define MSC_FLASHKEY_STATUS_MSK BITS(MSC_FLASHKEY_STATUS_POSS,MSC_FLASHKEY_STATUS_POSE) + +/****************** Bit definition for MSC_INFOKEY register ************************/ + +#define MSC_INFOKEY_STATUS_POSS 0U +#define MSC_INFOKEY_STATUS_POSE 1U +#define MSC_INFOKEY_STATUS_MSK BITS(MSC_INFOKEY_STATUS_POSS,MSC_INFOKEY_STATUS_POSE) + +/****************** Bit definition for MSC_FLASHADDR register ************************/ + +#define MSC_FLASHADDR_IFREN_POS 18U +#define MSC_FLASHADDR_IFREN_MSK BIT(MSC_FLASHADDR_IFREN_POS) + +#define MSC_FLASHADDR_ADDR_POSS 0U +#define MSC_FLASHADDR_ADDR_POSE 17U +#define MSC_FLASHADDR_ADDR_MSK BITS(MSC_FLASHADDR_ADDR_POSS,MSC_FLASHADDR_ADDR_POSE) + +/****************** Bit definition for MSC_FLASHFIFO register ************************/ + +#define MSC_FLASHFIFO_FIFO_POSS 0U +#define MSC_FLASHFIFO_FIFO_POSE 31U +#define MSC_FLASHFIFO_FIFO_MSK BITS(MSC_FLASHFIFO_FIFO_POSS,MSC_FLASHFIFO_FIFO_POSE) + +/****************** Bit definition for MSC_FLASHDL register ************************/ + +#define MSC_FLASHDL_DATAL_POSS 0U +#define MSC_FLASHDL_DATAL_POSE 31U +#define MSC_FLASHDL_DATAL_MSK BITS(MSC_FLASHDL_DATAL_POSS,MSC_FLASHDL_DATAL_POSE) + +/****************** Bit definition for MSC_FLASHDH register ************************/ + +#define MSC_FLASHDH_DATAH_POSS 0U +#define MSC_FLASHDH_DATAH_POSE 31U +#define MSC_FLASHDH_DATAH_MSK BITS(MSC_FLASHDH_DATAH_POSS,MSC_FLASHDH_DATAH_POSE) + +/****************** Bit definition for MSC_FLASHCMD register ************************/ + +#define MSC_FLASHCMD_CMD_POSS 0U +#define MSC_FLASHCMD_CMD_POSE 31U +#define MSC_FLASHCMD_CMD_MSK BITS(MSC_FLASHCMD_CMD_POSS,MSC_FLASHCMD_CMD_POSE) + +/****************** Bit definition for MSC_FLASHCR register ************************/ + +#define MSC_FLASHCR_FIFOEN_POS 5U +#define MSC_FLASHCR_FIFOEN_MSK BIT(MSC_FLASHCR_FIFOEN_POS) + +#define MSC_FLASHCR_FLASHREQ_POS 4U +#define MSC_FLASHCR_FLASHREQ_MSK BIT(MSC_FLASHCR_FLASHREQ_POS) + +#define MSC_FLASHCR_IAPRST_POS 1U +#define MSC_FLASHCR_IAPRST_MSK BIT(MSC_FLASHCR_IAPRST_POS) + +#define MSC_FLASHCR_IAPEN_POS 0U +#define MSC_FLASHCR_IAPEN_MSK BIT(MSC_FLASHCR_IAPEN_POS) + +/****************** Bit definition for MSC_FLASHSR register ************************/ + +#define MSC_FLASHSR_TIMEOUT_POS 7U +#define MSC_FLASHSR_TIMEOUT_MSK BIT(MSC_FLASHSR_TIMEOUT_POS) + +#define MSC_FLASHSR_PROG_POS 6U +#define MSC_FLASHSR_PROG_MSK BIT(MSC_FLASHSR_PROG_POS) + +#define MSC_FLASHSR_SERA_POS 5U +#define MSC_FLASHSR_SERA_MSK BIT(MSC_FLASHSR_SERA_POS) + +#define MSC_FLASHSR_MASE_POS 4U +#define MSC_FLASHSR_MASE_MSK BIT(MSC_FLASHSR_MASE_POS) + +#define MSC_FLASHSR_ADDR_OV_POS 3U +#define MSC_FLASHSR_ADDR_OV_MSK BIT(MSC_FLASHSR_ADDR_OV_POS) + +#define MSC_FLASHSR_WRP_FLAG_POS 2U +#define MSC_FLASHSR_WRP_FLAG_MSK BIT(MSC_FLASHSR_WRP_FLAG_POS) + +#define MSC_FLASHSR_BUSY_POS 1U +#define MSC_FLASHSR_BUSY_MSK BIT(MSC_FLASHSR_BUSY_POS) + +#define MSC_FLASHSR_FLASHACK_POS 0U +#define MSC_FLASHSR_FLASHACK_MSK BIT(MSC_FLASHSR_FLASHACK_POS) + +/****************** Bit definition for MSC_FLASHPL register ************************/ + +#define MSC_FLASHPL_PROG_LEN_POSS 0U +#define MSC_FLASHPL_PROG_LEN_POSE 15U +#define MSC_FLASHPL_PROG_LEN_MSK BITS(MSC_FLASHPL_PROG_LEN_POSS,MSC_FLASHPL_PROG_LEN_POSE) + +/****************** Bit definition for MSC_MEMWAIT register ************************/ + +#define MSC_MEMWAIT_SRAM_W_POSS 8U +#define MSC_MEMWAIT_SRAM_W_POSE 9U +#define MSC_MEMWAIT_SRAM_W_MSK BITS(MSC_MEMWAIT_SRAM_W_POSS,MSC_MEMWAIT_SRAM_W_POSE) + +#define MSC_MEMWAIT_FLASH_W_POSS 0U +#define MSC_MEMWAIT_FLASH_W_POSE 3U +#define MSC_MEMWAIT_FLASH_W_MSK BITS(MSC_MEMWAIT_FLASH_W_POSS,MSC_MEMWAIT_FLASH_W_POSE) + +typedef struct +{ + __IO uint32_t FLASHKEY; + __IO uint32_t INFOKEY; + __IO uint32_t FLASHADDR; + __O uint32_t FLASHFIFO; + __IO uint32_t FLASHDL; + __IO uint32_t FLASHDH; + __O uint32_t FLASHCMD; + __IO uint32_t FLASHCR; + __I uint32_t FLASHSR; + __IO uint32_t FLASHPL; + __IO uint32_t MEMWAIT; +} MSC_TypeDef; + +/****************** Bit definition for BKPC_PROT register ************************/ + +#define BKPC_PROT_KEY_POSS 1U +#define BKPC_PROT_KEY_POSE 31U +#define BKPC_PROT_KEY_MSK BITS(BKPC_PROT_KEY_POSS,BKPC_PROT_KEY_POSE) + +#define BKPC_PROT_PROT_POS 0U +#define BKPC_PROT_PROT_MSK BIT(BKPC_PROT_PROT_POS) + +/****************** Bit definition for BKPC_CR register ************************/ + +#define BKPC_CR_LDO_VSEL_POSS 24U +#define BKPC_CR_LDO_VSEL_POSE 26U +#define BKPC_CR_LDO_VSEL_MSK BITS(BKPC_CR_LDO_VSEL_POSS,BKPC_CR_LDO_VSEL_POSE) + +#define BKPC_CR_MT_STDB_POS 19U +#define BKPC_CR_MT_STDB_MSK BIT(BKPC_CR_MT_STDB_POS) + +#define BKPC_CR_VR1P5_VSEL_POSS 16U +#define BKPC_CR_VR1P5_VSEL_POSE 18U +#define BKPC_CR_VR1P5_VSEL_MSK BITS(BKPC_CR_VR1P5_VSEL_POSS,BKPC_CR_VR1P5_VSEL_POSE) + +#define BKPC_CR_TC_PWRDWN_POS 13U +#define BKPC_CR_TC_PWRDWN_MSK BIT(BKPC_CR_TC_PWRDWN_POS) + +#define BKPC_CR_WKPOL_POS 12U +#define BKPC_CR_WKPOL_MSK BIT(BKPC_CR_WKPOL_POS) + +#define BKPC_CR_WKPS_POSS 9U +#define BKPC_CR_WKPS_POSE 11U +#define BKPC_CR_WKPS_MSK BITS(BKPC_CR_WKPS_POSS,BKPC_CR_WKPS_POSE) + +#define BKPC_CR_WKPEN_POS 8U +#define BKPC_CR_WKPEN_MSK BIT(BKPC_CR_WKPEN_POS) + +#define BKPC_CR_LRCEN_POS 2U +#define BKPC_CR_LRCEN_MSK BIT(BKPC_CR_LRCEN_POS) + +#define BKPC_CR_LOSMEN_POS 1U +#define BKPC_CR_LOSMEN_MSK BIT(BKPC_CR_LOSMEN_POS) + +#define BKPC_CR_LOSCEN_POS 0U +#define BKPC_CR_LOSCEN_MSK BIT(BKPC_CR_LOSCEN_POS) + +/****************** Bit definition for BKPC_PCCR register ************************/ + +#define BKPC_PCCR_TEMPCS_POSS 4U +#define BKPC_PCCR_TEMPCS_POSE 5U +#define BKPC_PCCR_TEMPCS_MSK BITS(BKPC_PCCR_TEMPCS_POSS,BKPC_PCCR_TEMPCS_POSE) + +#define BKPC_PCCR_RTCCS_POSS 0U +#define BKPC_PCCR_RTCCS_POSE 1U +#define BKPC_PCCR_RTCCS_MSK BITS(BKPC_PCCR_RTCCS_POSS,BKPC_PCCR_RTCCS_POSE) + +/****************** Bit definition for BKPC_PCR register ************************/ + +#define BKPC_PCR_BORS_POSS 1U +#define BKPC_PCR_BORS_POSE 4U +#define BKPC_PCR_BORS_MSK BITS(BKPC_PCR_BORS_POSS,BKPC_PCR_BORS_POSE) + +#define BKPC_PCR_BOREN_POS 0U +#define BKPC_PCR_BOREN_MSK BIT(BKPC_PCR_BOREN_POS) + +typedef struct +{ + __IO uint32_t PROT; + __IO uint32_t CR; + __IO uint32_t PCCR; + __IO uint32_t PCR; +} BKPC_TypeDef; + +/****************** Bit definition for PMU_CR register ************************/ + +#define PMU_CR_MTSTOP_POS 21U +#define PMU_CR_MTSTOP_MSK BIT(PMU_CR_MTSTOP_POS) + +#define PMU_CR_LPSTOP_POS 20U +#define PMU_CR_LPSTOP_MSK BIT(PMU_CR_LPSTOP_POS) + +#define PMU_CR_LPRUN_POS 19U +#define PMU_CR_LPRUN_MSK BIT(PMU_CR_LPRUN_POS) + +#define PMU_CR_LPVS_POSS 16U +#define PMU_CR_LPVS_POSE 18U +#define PMU_CR_LPVS_MSK BITS(PMU_CR_LPVS_POSS,PMU_CR_LPVS_POSE) + +#define PMU_CR_WKPS_POSS 9U +#define PMU_CR_WKPS_POSE 11U +#define PMU_CR_WKPS_MSK BITS(PMU_CR_WKPS_POSS,PMU_CR_WKPS_POSE) + +#define PMU_CR_WKPEN_POS 8U +#define PMU_CR_WKPEN_MSK BIT(PMU_CR_WKPEN_POS) + +#define PMU_CR_CSTANDBYF_POS 3U +#define PMU_CR_CSTANDBYF_MSK BIT(PMU_CR_CSTANDBYF_POS) + +#define PMU_CR_CWUF_POS 2U +#define PMU_CR_CWUF_MSK BIT(PMU_CR_CWUF_POS) + +#define PMU_CR_LPM_POSS 0U +#define PMU_CR_LPM_POSE 1U +#define PMU_CR_LPM_MSK BITS(PMU_CR_LPM_POSS,PMU_CR_LPM_POSE) + +/****************** Bit definition for PMU_SR register ************************/ + +#define PMU_SR_STANDBYF_POS 1U +#define PMU_SR_STANDBYF_MSK BIT(PMU_SR_STANDBYF_POS) + +#define PMU_SR_WUF_POS 0U +#define PMU_SR_WUF_MSK BIT(PMU_SR_WUF_POS) + +/****************** Bit definition for PMU_LVDCR register ************************/ + +#define PMU_LVDCR_LVDO_POS 15U +#define PMU_LVDCR_LVDO_MSK BIT(PMU_LVDCR_LVDO_POS) + +#define PMU_LVDCR_LVDFLT_POS 11U +#define PMU_LVDCR_LVDFLT_MSK BIT(PMU_LVDCR_LVDFLT_POS) + +#define PMU_LVDCR_LVIFS_POSS 8U +#define PMU_LVDCR_LVIFS_POSE 10U +#define PMU_LVDCR_LVIFS_MSK BITS(PMU_LVDCR_LVIFS_POSS,PMU_LVDCR_LVIFS_POSE) + +#define PMU_LVDCR_LVDS_POSS 4U +#define PMU_LVDCR_LVDS_POSE 7U +#define PMU_LVDCR_LVDS_MSK BITS(PMU_LVDCR_LVDS_POSS,PMU_LVDCR_LVDS_POSE) + +#define PMU_LVDCR_LVDCIF_POS 3U +#define PMU_LVDCR_LVDCIF_MSK BIT(PMU_LVDCR_LVDCIF_POS) + +#define PMU_LVDCR_LVDIF_POS 2U +#define PMU_LVDCR_LVDIF_MSK BIT(PMU_LVDCR_LVDIF_POS) + +#define PMU_LVDCR_LVDIE_POS 1U +#define PMU_LVDCR_LVDIE_MSK BIT(PMU_LVDCR_LVDIE_POS) + +#define PMU_LVDCR_LVDEN_POS 0U +#define PMU_LVDCR_LVDEN_MSK BIT(PMU_LVDCR_LVDEN_POS) + +/****************** Bit definition for PMU_PWRCR register ************************/ + +#define PMU_PWRCR_BXCAN_POS 4U +#define PMU_PWRCR_BXCAN_MSK BIT(PMU_PWRCR_BXCAN_POS) + +#define PMU_PWRCR_SRAM_POSS 0U +#define PMU_PWRCR_SRAM_POSE 1U +#define PMU_PWRCR_SRAM_MSK BITS(PMU_PWRCR_SRAM_POSS,PMU_PWRCR_SRAM_POSE) + +/****************** Bit definition for PMU_TWUR register ************************/ + +#define PMU_TWUR_TWU_POSS 0U +#define PMU_TWUR_TWU_POSE 11U +#define PMU_TWUR_TWU_MSK BITS(PMU_TWUR_TWU_POSS,PMU_TWUR_TWU_POSE) + +/****************** Bit definition for PMU_VREFCR register ************************/ + +#define PMU_VREFCR_FLTS_POSS 13U +#define PMU_VREFCR_FLTS_POSE 14U +#define PMU_VREFCR_FLTS_MSK BITS(PMU_VREFCR_FLTS_POSS,PMU_VREFCR_FLTS_POSE) + +#define PMU_VREFCR_CHOPCS_POSS 10U +#define PMU_VREFCR_CHOPCS_POSE 12U +#define PMU_VREFCR_CHOPCS_MSK BITS(PMU_VREFCR_CHOPCS_POSS,PMU_VREFCR_CHOPCS_POSE) + +#define PMU_VREFCR_CHOP1EN_POS 9U +#define PMU_VREFCR_CHOP1EN_MSK BIT(PMU_VREFCR_CHOP1EN_POS) + +#define PMU_VREFCR_CHOPEN_POS 8U +#define PMU_VREFCR_CHOPEN_MSK BIT(PMU_VREFCR_CHOPEN_POS) + +#define PMU_VREFCR_VREFEN_POS 0U +#define PMU_VREFCR_VREFEN_MSK BIT(PMU_VREFCR_VREFEN_POS) + +typedef struct +{ + __IO uint32_t CR; + __I uint32_t SR; + __IO uint32_t LVDCR; + __IO uint32_t PWRCR; + __IO uint32_t TWUR; + __IO uint32_t VREFCR; +} PMU_TypeDef; + +/****************** Bit definition for RMU_CR register ************************/ + +#define RMU_CR_BORVS_POSS 4U +#define RMU_CR_BORVS_POSE 7U +#define RMU_CR_BORVS_MSK BITS(RMU_CR_BORVS_POSS,RMU_CR_BORVS_POSE) + +#define RMU_CR_BORFLT_POSS 1U +#define RMU_CR_BORFLT_POSE 3U +#define RMU_CR_BORFLT_MSK BITS(RMU_CR_BORFLT_POSS,RMU_CR_BORFLT_POSE) + +#define RMU_CR_BOREN_POS 0U +#define RMU_CR_BOREN_MSK BIT(RMU_CR_BOREN_POS) + +/****************** Bit definition for RMU_RSTSR register ************************/ + +#define RMU_RSTSR_CFGERR_POS 16U +#define RMU_RSTSR_CFGERR_MSK BIT(RMU_RSTSR_CFGERR_POS) + +#define RMU_RSTSR_CFG_POS 10U +#define RMU_RSTSR_CFG_MSK BIT(RMU_RSTSR_CFG_POS) + +#define RMU_RSTSR_CPU_POS 9U +#define RMU_RSTSR_CPU_MSK BIT(RMU_RSTSR_CPU_POS) + +#define RMU_RSTSR_MCU_POS 8U +#define RMU_RSTSR_MCU_MSK BIT(RMU_RSTSR_MCU_POS) + +#define RMU_RSTSR_CHIP_POS 7U +#define RMU_RSTSR_CHIP_MSK BIT(RMU_RSTSR_CHIP_POS) + +#define RMU_RSTSR_LOCKUP_POS 6U +#define RMU_RSTSR_LOCKUP_MSK BIT(RMU_RSTSR_LOCKUP_POS) + +#define RMU_RSTSR_WWDT_POS 5U +#define RMU_RSTSR_WWDT_MSK BIT(RMU_RSTSR_WWDT_POS) + +#define RMU_RSTSR_IWDT_POS 4U +#define RMU_RSTSR_IWDT_MSK BIT(RMU_RSTSR_IWDT_POS) + +#define RMU_RSTSR_NMRST_POS 3U +#define RMU_RSTSR_NMRST_MSK BIT(RMU_RSTSR_NMRST_POS) + +#define RMU_RSTSR_BOR_POS 2U +#define RMU_RSTSR_BOR_MSK BIT(RMU_RSTSR_BOR_POS) + +#define RMU_RSTSR_WAKEUP_POS 1U +#define RMU_RSTSR_WAKEUP_MSK BIT(RMU_RSTSR_WAKEUP_POS) + +#define RMU_RSTSR_POR_POS 0U +#define RMU_RSTSR_POR_MSK BIT(RMU_RSTSR_POR_POS) + +/****************** Bit definition for RMU_CRSTSR register ************************/ + +#define RMU_CRSTSR_CFG_POS 10U +#define RMU_CRSTSR_CFG_MSK BIT(RMU_CRSTSR_CFG_POS) + +#define RMU_CRSTSR_CPU_POS 9U +#define RMU_CRSTSR_CPU_MSK BIT(RMU_CRSTSR_CPU_POS) + +#define RMU_CRSTSR_MCU_POS 8U +#define RMU_CRSTSR_MCU_MSK BIT(RMU_CRSTSR_MCU_POS) + +#define RMU_CRSTSR_CHIP_POS 7U +#define RMU_CRSTSR_CHIP_MSK BIT(RMU_CRSTSR_CHIP_POS) + +#define RMU_CRSTSR_LOCKUP_POS 6U +#define RMU_CRSTSR_LOCKUP_MSK BIT(RMU_CRSTSR_LOCKUP_POS) + +#define RMU_CRSTSR_WWDT_POS 5U +#define RMU_CRSTSR_WWDT_MSK BIT(RMU_CRSTSR_WWDT_POS) + +#define RMU_CRSTSR_IWDT_POS 4U +#define RMU_CRSTSR_IWDT_MSK BIT(RMU_CRSTSR_IWDT_POS) + +#define RMU_CRSTSR_NMRST_POS 3U +#define RMU_CRSTSR_NMRST_MSK BIT(RMU_CRSTSR_NMRST_POS) + +#define RMU_CRSTSR_BOR_POS 2U +#define RMU_CRSTSR_BOR_MSK BIT(RMU_CRSTSR_BOR_POS) + +#define RMU_CRSTSR_WAKEUP_POS 1U +#define RMU_CRSTSR_WAKEUP_MSK BIT(RMU_CRSTSR_WAKEUP_POS) + +#define RMU_CRSTSR_POR_POS 0U +#define RMU_CRSTSR_POR_MSK BIT(RMU_CRSTSR_POR_POS) + +/****************** Bit definition for RMU_AHB1RSTR register ************************/ + +#define RMU_AHB1RSTR_PISRST_POS 5U +#define RMU_AHB1RSTR_PISRST_MSK BIT(RMU_AHB1RSTR_PISRST_POS) + +#define RMU_AHB1RSTR_TRNGRST_POS 4U +#define RMU_AHB1RSTR_TRNGRST_MSK BIT(RMU_AHB1RSTR_TRNGRST_POS) + +#define RMU_AHB1RSTR_CRYPTRST_POS 3U +#define RMU_AHB1RSTR_CRYPTRST_MSK BIT(RMU_AHB1RSTR_CRYPTRST_POS) + +#define RMU_AHB1RSTR_CALCRST_POS 2U +#define RMU_AHB1RSTR_CALCRST_MSK BIT(RMU_AHB1RSTR_CALCRST_POS) + +#define RMU_AHB1RSTR_CRCRST_POS 1U +#define RMU_AHB1RSTR_CRCRST_MSK BIT(RMU_AHB1RSTR_CRCRST_POS) + +#define RMU_AHB1RSTR_GPIORST_POS 0U +#define RMU_AHB1RSTR_GPIORST_MSK BIT(RMU_AHB1RSTR_GPIORST_POS) + +/****************** Bit definition for RMU_AHB2RSTR register ************************/ + +#define RMU_AHB2RSTR_CPURST_POS 1U +#define RMU_AHB2RSTR_CPURST_MSK BIT(RMU_AHB2RSTR_CPURST_POS) + +#define RMU_AHB2RSTR_CHIPRST_POS 0U +#define RMU_AHB2RSTR_CHIPRST_MSK BIT(RMU_AHB2RSTR_CHIPRST_POS) + +/****************** Bit definition for RMU_APB1RSTR register ************************/ + +#define RMU_APB1RSTR_CAN0RST_POS 24U +#define RMU_APB1RSTR_CAN0RST_MSK BIT(RMU_APB1RSTR_CAN0RST_POS) + +#define RMU_APB1RSTR_I2C1RST_POS 21U +#define RMU_APB1RSTR_I2C1RST_MSK BIT(RMU_APB1RSTR_I2C1RST_POS) + +#define RMU_APB1RSTR_I2C0RST_POS 20U +#define RMU_APB1RSTR_I2C0RST_MSK BIT(RMU_APB1RSTR_I2C0RST_POS) + +#define RMU_APB1RSTR_SPI2RST_POS 18U +#define RMU_APB1RSTR_SPI2RST_MSK BIT(RMU_APB1RSTR_SPI2RST_POS) + +#define RMU_APB1RSTR_SPI1RST_POS 17U +#define RMU_APB1RSTR_SPI1RST_MSK BIT(RMU_APB1RSTR_SPI1RST_POS) + +#define RMU_APB1RSTR_SPI0RST_POS 16U +#define RMU_APB1RSTR_SPI0RST_MSK BIT(RMU_APB1RSTR_SPI0RST_POS) + +#define RMU_APB1RSTR_USART1RST_POS 13U +#define RMU_APB1RSTR_USART1RST_MSK BIT(RMU_APB1RSTR_USART1RST_POS) + +#define RMU_APB1RSTR_USART0RST_POS 12U +#define RMU_APB1RSTR_USART0RST_MSK BIT(RMU_APB1RSTR_USART0RST_POS) + +#define RMU_APB1RSTR_UART3RST_POS 11U +#define RMU_APB1RSTR_UART3RST_MSK BIT(RMU_APB1RSTR_UART3RST_POS) + +#define RMU_APB1RSTR_UART2RST_POS 10U +#define RMU_APB1RSTR_UART2RST_MSK BIT(RMU_APB1RSTR_UART2RST_POS) + +#define RMU_APB1RSTR_UART1RST_POS 9U +#define RMU_APB1RSTR_UART1RST_MSK BIT(RMU_APB1RSTR_UART1RST_POS) + +#define RMU_APB1RSTR_UART0RST_POS 8U +#define RMU_APB1RSTR_UART0RST_MSK BIT(RMU_APB1RSTR_UART0RST_POS) + +#define RMU_APB1RSTR_TIM7RST_POS 7U +#define RMU_APB1RSTR_TIM7RST_MSK BIT(RMU_APB1RSTR_TIM7RST_POS) + +#define RMU_APB1RSTR_TIM6RST_POS 6U +#define RMU_APB1RSTR_TIM6RST_MSK BIT(RMU_APB1RSTR_TIM6RST_POS) + +#define RMU_APB1RSTR_TIM5RST_POS 5U +#define RMU_APB1RSTR_TIM5RST_MSK BIT(RMU_APB1RSTR_TIM5RST_POS) + +#define RMU_APB1RSTR_TIM4RST_POS 4U +#define RMU_APB1RSTR_TIM4RST_MSK BIT(RMU_APB1RSTR_TIM4RST_POS) + +#define RMU_APB1RSTR_TIM3RST_POS 3U +#define RMU_APB1RSTR_TIM3RST_MSK BIT(RMU_APB1RSTR_TIM3RST_POS) + +#define RMU_APB1RSTR_TIM2RST_POS 2U +#define RMU_APB1RSTR_TIM2RST_MSK BIT(RMU_APB1RSTR_TIM2RST_POS) + +#define RMU_APB1RSTR_TIM1RST_POS 1U +#define RMU_APB1RSTR_TIM1RST_MSK BIT(RMU_APB1RSTR_TIM1RST_POS) + +#define RMU_APB1RSTR_TIM0RST_POS 0U +#define RMU_APB1RSTR_TIM0RST_MSK BIT(RMU_APB1RSTR_TIM0RST_POS) + +/****************** Bit definition for RMU_APB2RSTR register ************************/ + +#define RMU_APB2RSTR_BKPRAMRST_POS 18U +#define RMU_APB2RSTR_BKPRAMRST_MSK BIT(RMU_APB2RSTR_BKPRAMRST_POS) + +#define RMU_APB2RSTR_BKPCRST_POS 17U +#define RMU_APB2RSTR_BKPCRST_MSK BIT(RMU_APB2RSTR_BKPCRST_POS) + +#define RMU_APB2RSTR_TEMPRST_POS 16U +#define RMU_APB2RSTR_TEMPRST_MSK BIT(RMU_APB2RSTR_TEMPRST_POS) + +#define RMU_APB2RSTR_RTCRST_POS 15U +#define RMU_APB2RSTR_RTCRST_MSK BIT(RMU_APB2RSTR_RTCRST_POS) + +#define RMU_APB2RSTR_IWDTRST_POS 14U +#define RMU_APB2RSTR_IWDTRST_MSK BIT(RMU_APB2RSTR_IWDTRST_POS) + +#define RMU_APB2RSTR_LCDRST_POS 13U +#define RMU_APB2RSTR_LCDRST_MSK BIT(RMU_APB2RSTR_LCDRST_POS) + +#define RMU_APB2RSTR_WWDTRST_POS 12U +#define RMU_APB2RSTR_WWDTRST_MSK BIT(RMU_APB2RSTR_WWDTRST_POS) + +#define RMU_APB2RSTR_OPAMPRST_POS 8U +#define RMU_APB2RSTR_OPAMPRST_MSK BIT(RMU_APB2RSTR_OPAMPRST_POS) + +#define RMU_APB2RSTR_ACMP1RST_POS 7U +#define RMU_APB2RSTR_ACMP1RST_MSK BIT(RMU_APB2RSTR_ACMP1RST_POS) + +#define RMU_APB2RSTR_ACMP0RST_POS 6U +#define RMU_APB2RSTR_ACMP0RST_MSK BIT(RMU_APB2RSTR_ACMP0RST_POS) + +#define RMU_APB2RSTR_ADC0RST_POS 4U +#define RMU_APB2RSTR_ADC0RST_MSK BIT(RMU_APB2RSTR_ADC0RST_POS) + +#define RMU_APB2RSTR_LPUART0RST_POS 2U +#define RMU_APB2RSTR_LPUART0RST_MSK BIT(RMU_APB2RSTR_LPUART0RST_POS) + +#define RMU_APB2RSTR_LPTIM0RST_POS 0U +#define RMU_APB2RSTR_LPTIM0RST_MSK BIT(RMU_APB2RSTR_LPTIM0RST_POS) + +typedef struct +{ + __IO uint32_t CR; + uint32_t RESERVED0[3] ; + __I uint32_t RSTSR; + __O uint32_t CRSTSR; + uint32_t RESERVED1[2] ; + __O uint32_t AHB1RSTR; + __O uint32_t AHB2RSTR; + uint32_t RESERVED2[2] ; + __O uint32_t APB1RSTR; + __O uint32_t APB2RSTR; +} RMU_TypeDef; + +/****************** Bit definition for CMU_CSR register ************************/ + +#define CMU_CSR_CFT_RDYN_POS 25U +#define CMU_CSR_CFT_RDYN_MSK BIT(CMU_CSR_CFT_RDYN_POS) + +#define CMU_CSR_CFT_STU_POS 24U +#define CMU_CSR_CFT_STU_MSK BIT(CMU_CSR_CFT_STU_POS) + +#define CMU_CSR_CFT_CMD_POSS 16U +#define CMU_CSR_CFT_CMD_POSE 23U +#define CMU_CSR_CFT_CMD_MSK BITS(CMU_CSR_CFT_CMD_POSS,CMU_CSR_CFT_CMD_POSE) + +#define CMU_CSR_SYS_RDYN_POS 12U +#define CMU_CSR_SYS_RDYN_MSK BIT(CMU_CSR_SYS_RDYN_POS) + +#define CMU_CSR_SYS_STU_POSS 8U +#define CMU_CSR_SYS_STU_POSE 10U +#define CMU_CSR_SYS_STU_MSK BITS(CMU_CSR_SYS_STU_POSS,CMU_CSR_SYS_STU_POSE) + +#define CMU_CSR_SYS_CMD_POSS 0U +#define CMU_CSR_SYS_CMD_POSE 2U +#define CMU_CSR_SYS_CMD_MSK BITS(CMU_CSR_SYS_CMD_POSS,CMU_CSR_SYS_CMD_POSE) + +/****************** Bit definition for CMU_CFGR register ************************/ + +#define CMU_CFGR_HRCFST_POS 25U +#define CMU_CFGR_HRCFST_MSK BIT(CMU_CFGR_HRCFST_POS) + +#define CMU_CFGR_HRCFSW_POS 24U +#define CMU_CFGR_HRCFSW_MSK BIT(CMU_CFGR_HRCFSW_POS) + +#define CMU_CFGR_PCLK2DIV_POSS 20U +#define CMU_CFGR_PCLK2DIV_POSE 23U +#define CMU_CFGR_PCLK2DIV_MSK BITS(CMU_CFGR_PCLK2DIV_POSS,CMU_CFGR_PCLK2DIV_POSE) + +#define CMU_CFGR_PCLK1DIV_POSS 16U +#define CMU_CFGR_PCLK1DIV_POSE 19U +#define CMU_CFGR_PCLK1DIV_MSK BITS(CMU_CFGR_PCLK1DIV_POSS,CMU_CFGR_PCLK1DIV_POSE) + +#define CMU_CFGR_SYSDIV_POSS 12U +#define CMU_CFGR_SYSDIV_POSE 15U +#define CMU_CFGR_SYSDIV_MSK BITS(CMU_CFGR_SYSDIV_POSS,CMU_CFGR_SYSDIV_POSE) + +#define CMU_CFGR_HCLK1DIV_POSS 0U +#define CMU_CFGR_HCLK1DIV_POSE 3U +#define CMU_CFGR_HCLK1DIV_MSK BITS(CMU_CFGR_HCLK1DIV_POSS,CMU_CFGR_HCLK1DIV_POSE) + +/****************** Bit definition for CMU_CLKENR register ************************/ + +#define CMU_CLKENR_PLL2EN_POS 9U +#define CMU_CLKENR_PLL2EN_MSK BIT(CMU_CLKENR_PLL2EN_POS) + +#define CMU_CLKENR_PLL1EN_POS 8U +#define CMU_CLKENR_PLL1EN_MSK BIT(CMU_CLKENR_PLL1EN_POS) + +#define CMU_CLKENR_ULRCEN_POS 4U +#define CMU_CLKENR_ULRCEN_MSK BIT(CMU_CLKENR_ULRCEN_POS) + +#define CMU_CLKENR_LRCEN_POS 3U +#define CMU_CLKENR_LRCEN_MSK BIT(CMU_CLKENR_LRCEN_POS) + +#define CMU_CLKENR_HRCEN_POS 2U +#define CMU_CLKENR_HRCEN_MSK BIT(CMU_CLKENR_HRCEN_POS) + +#define CMU_CLKENR_LOSCEN_POS 1U +#define CMU_CLKENR_LOSCEN_MSK BIT(CMU_CLKENR_LOSCEN_POS) + +#define CMU_CLKENR_HOSCEN_POS 0U +#define CMU_CLKENR_HOSCEN_MSK BIT(CMU_CLKENR_HOSCEN_POS) + +/****************** Bit definition for CMU_CLKSR register ************************/ + +#define CMU_CLKSR_PLL2RDY_POS 25U +#define CMU_CLKSR_PLL2RDY_MSK BIT(CMU_CLKSR_PLL2RDY_POS) + +#define CMU_CLKSR_PLL1RDY_POS 24U +#define CMU_CLKSR_PLL1RDY_MSK BIT(CMU_CLKSR_PLL1RDY_POS) + +#define CMU_CLKSR_LRCRDY_POS 19U +#define CMU_CLKSR_LRCRDY_MSK BIT(CMU_CLKSR_LRCRDY_POS) + +#define CMU_CLKSR_HRCRDY_POS 18U +#define CMU_CLKSR_HRCRDY_MSK BIT(CMU_CLKSR_HRCRDY_POS) + +#define CMU_CLKSR_LOSCRDY_POS 17U +#define CMU_CLKSR_LOSCRDY_MSK BIT(CMU_CLKSR_LOSCRDY_POS) + +#define CMU_CLKSR_HOSCRDY_POS 16U +#define CMU_CLKSR_HOSCRDY_MSK BIT(CMU_CLKSR_HOSCRDY_POS) + +#define CMU_CLKSR_PLL2ACT_POS 9U +#define CMU_CLKSR_PLL2ACT_MSK BIT(CMU_CLKSR_PLL2ACT_POS) + +#define CMU_CLKSR_PLL1ACT_POS 8U +#define CMU_CLKSR_PLL1ACT_MSK BIT(CMU_CLKSR_PLL1ACT_POS) + +#define CMU_CLKSR_ULRCACT_POS 4U +#define CMU_CLKSR_ULRCACT_MSK BIT(CMU_CLKSR_ULRCACT_POS) + +#define CMU_CLKSR_LRCACT_POS 3U +#define CMU_CLKSR_LRCACT_MSK BIT(CMU_CLKSR_LRCACT_POS) + +#define CMU_CLKSR_HRCACT_POS 2U +#define CMU_CLKSR_HRCACT_MSK BIT(CMU_CLKSR_HRCACT_POS) + +#define CMU_CLKSR_LOSCACT_POS 1U +#define CMU_CLKSR_LOSCACT_MSK BIT(CMU_CLKSR_LOSCACT_POS) + +#define CMU_CLKSR_HOSCACT_POS 0U +#define CMU_CLKSR_HOSCACT_MSK BIT(CMU_CLKSR_HOSCACT_POS) + +/****************** Bit definition for CMU_PLLCFG register ************************/ + +#define CMU_PLLCFG_PLL2LCKN_POS 17U +#define CMU_PLLCFG_PLL2LCKN_MSK BIT(CMU_PLLCFG_PLL2LCKN_POS) + +#define CMU_PLLCFG_PLL1LCKN_POS 16U +#define CMU_PLLCFG_PLL1LCKN_MSK BIT(CMU_PLLCFG_PLL1LCKN_POS) + +#define CMU_PLLCFG_PLL2RFS_POSS 8U +#define CMU_PLLCFG_PLL2RFS_POSE 9U +#define CMU_PLLCFG_PLL2RFS_MSK BITS(CMU_PLLCFG_PLL2RFS_POSS,CMU_PLLCFG_PLL2RFS_POSE) + +#define CMU_PLLCFG_PLL1OS_POS 4U +#define CMU_PLLCFG_PLL1OS_MSK BIT(CMU_PLLCFG_PLL1OS_POS) + +#define CMU_PLLCFG_PLL1RFS_POSS 0U +#define CMU_PLLCFG_PLL1RFS_POSE 2U +#define CMU_PLLCFG_PLL1RFS_MSK BITS(CMU_PLLCFG_PLL1RFS_POSS,CMU_PLLCFG_PLL1RFS_POSE) + +/****************** Bit definition for CMU_HOSCCFG register ************************/ + +#define CMU_HOSCCFG_FREQ_POSS 0U +#define CMU_HOSCCFG_FREQ_POSE 4U +#define CMU_HOSCCFG_FREQ_MSK BITS(CMU_HOSCCFG_FREQ_POSS,CMU_HOSCCFG_FREQ_POSE) + +/****************** Bit definition for CMU_HOSMCR register ************************/ + +#define CMU_HOSMCR_NMIE_POS 20U +#define CMU_HOSMCR_NMIE_MSK BIT(CMU_HOSMCR_NMIE_POS) + +#define CMU_HOSMCR_STPIF_POS 19U +#define CMU_HOSMCR_STPIF_MSK BIT(CMU_HOSMCR_STPIF_POS) + +#define CMU_HOSMCR_STRIF_POS 18U +#define CMU_HOSMCR_STRIF_MSK BIT(CMU_HOSMCR_STRIF_POS) + +#define CMU_HOSMCR_STPIE_POS 17U +#define CMU_HOSMCR_STPIE_MSK BIT(CMU_HOSMCR_STPIE_POS) + +#define CMU_HOSMCR_STRIE_POS 16U +#define CMU_HOSMCR_STRIE_MSK BIT(CMU_HOSMCR_STRIE_POS) + +#define CMU_HOSMCR_FRQS_POSS 8U +#define CMU_HOSMCR_FRQS_POSE 10U +#define CMU_HOSMCR_FRQS_MSK BITS(CMU_HOSMCR_FRQS_POSS,CMU_HOSMCR_FRQS_POSE) + +#define CMU_HOSMCR_CLKS_POS 1U +#define CMU_HOSMCR_CLKS_MSK BIT(CMU_HOSMCR_CLKS_POS) + +#define CMU_HOSMCR_EN_POS 0U +#define CMU_HOSMCR_EN_MSK BIT(CMU_HOSMCR_EN_POS) + +/****************** Bit definition for CMU_LOSMCR register ************************/ + +#define CMU_LOSMCR_NMIE_POS 20U +#define CMU_LOSMCR_NMIE_MSK BIT(CMU_LOSMCR_NMIE_POS) + +#define CMU_LOSMCR_STPIF_POS 19U +#define CMU_LOSMCR_STPIF_MSK BIT(CMU_LOSMCR_STPIF_POS) + +#define CMU_LOSMCR_STRIF_POS 18U +#define CMU_LOSMCR_STRIF_MSK BIT(CMU_LOSMCR_STRIF_POS) + +#define CMU_LOSMCR_STPIE_POS 17U +#define CMU_LOSMCR_STPIE_MSK BIT(CMU_LOSMCR_STPIE_POS) + +#define CMU_LOSMCR_STRIE_POS 16U +#define CMU_LOSMCR_STRIE_MSK BIT(CMU_LOSMCR_STRIE_POS) + +#define CMU_LOSMCR_CLKS_POS 1U +#define CMU_LOSMCR_CLKS_MSK BIT(CMU_LOSMCR_CLKS_POS) + +#define CMU_LOSMCR_EN_POS 0U +#define CMU_LOSMCR_EN_MSK BIT(CMU_LOSMCR_EN_POS) + +/****************** Bit definition for CMU_PULMCR register ************************/ + +#define CMU_PULMCR_NMIE_POS 20U +#define CMU_PULMCR_NMIE_MSK BIT(CMU_PULMCR_NMIE_POS) + +#define CMU_PULMCR_ULKIF_POS 19U +#define CMU_PULMCR_ULKIF_MSK BIT(CMU_PULMCR_ULKIF_POS) + +#define CMU_PULMCR_LCKIF_POS 18U +#define CMU_PULMCR_LCKIF_MSK BIT(CMU_PULMCR_LCKIF_POS) + +#define CMU_PULMCR_ULKIE_POS 17U +#define CMU_PULMCR_ULKIE_MSK BIT(CMU_PULMCR_ULKIE_POS) + +#define CMU_PULMCR_LCKIE_POS 16U +#define CMU_PULMCR_LCKIE_MSK BIT(CMU_PULMCR_LCKIE_POS) + +#define CMU_PULMCR_MODE_POSS 8U +#define CMU_PULMCR_MODE_POSE 9U +#define CMU_PULMCR_MODE_MSK BITS(CMU_PULMCR_MODE_POSS,CMU_PULMCR_MODE_POSE) + +#define CMU_PULMCR_CLKS_POS 1U +#define CMU_PULMCR_CLKS_MSK BIT(CMU_PULMCR_CLKS_POS) + +#define CMU_PULMCR_EN_POS 0U +#define CMU_PULMCR_EN_MSK BIT(CMU_PULMCR_EN_POS) + +/****************** Bit definition for CMU_CLKOCR register ************************/ + +#define CMU_CLKOCR_LSCOS_POSS 24U +#define CMU_CLKOCR_LSCOS_POSE 26U +#define CMU_CLKOCR_LSCOS_MSK BITS(CMU_CLKOCR_LSCOS_POSS,CMU_CLKOCR_LSCOS_POSE) + +#define CMU_CLKOCR_LSCOEN_POS 16U +#define CMU_CLKOCR_LSCOEN_MSK BIT(CMU_CLKOCR_LSCOEN_POS) + +#define CMU_CLKOCR_HSCODIV_POSS 12U +#define CMU_CLKOCR_HSCODIV_POSE 14U +#define CMU_CLKOCR_HSCODIV_MSK BITS(CMU_CLKOCR_HSCODIV_POSS,CMU_CLKOCR_HSCODIV_POSE) + +#define CMU_CLKOCR_HSCOS_POSS 8U +#define CMU_CLKOCR_HSCOS_POSE 10U +#define CMU_CLKOCR_HSCOS_MSK BITS(CMU_CLKOCR_HSCOS_POSS,CMU_CLKOCR_HSCOS_POSE) + +#define CMU_CLKOCR_HSCOEN_POS 0U +#define CMU_CLKOCR_HSCOEN_MSK BIT(CMU_CLKOCR_HSCOEN_POS) + +/****************** Bit definition for CMU_BUZZCR register ************************/ + +#define CMU_BUZZCR_DAT_POSS 16U +#define CMU_BUZZCR_DAT_POSE 31U +#define CMU_BUZZCR_DAT_MSK BITS(CMU_BUZZCR_DAT_POSS,CMU_BUZZCR_DAT_POSE) + +#define CMU_BUZZCR_DIV_POSS 8U +#define CMU_BUZZCR_DIV_POSE 10U +#define CMU_BUZZCR_DIV_MSK BITS(CMU_BUZZCR_DIV_POSS,CMU_BUZZCR_DIV_POSE) + +#define CMU_BUZZCR_EN_POS 0U +#define CMU_BUZZCR_EN_MSK BIT(CMU_BUZZCR_EN_POS) + +/****************** Bit definition for CMU_AHB1ENR register ************************/ + +#define CMU_AHB1ENR_PISEN_POS 5U +#define CMU_AHB1ENR_PISEN_MSK BIT(CMU_AHB1ENR_PISEN_POS) + +#define CMU_AHB1ENR_TRNGEN_POS 4U +#define CMU_AHB1ENR_TRNGEN_MSK BIT(CMU_AHB1ENR_TRNGEN_POS) + +#define CMU_AHB1ENR_CRYPTEN_POS 3U +#define CMU_AHB1ENR_CRYPTEN_MSK BIT(CMU_AHB1ENR_CRYPTEN_POS) + +#define CMU_AHB1ENR_CALCEN_POS 2U +#define CMU_AHB1ENR_CALCEN_MSK BIT(CMU_AHB1ENR_CALCEN_POS) + +#define CMU_AHB1ENR_CRCEN_POS 1U +#define CMU_AHB1ENR_CRCEN_MSK BIT(CMU_AHB1ENR_CRCEN_POS) + +#define CMU_AHB1ENR_GPIOEN_POS 0U +#define CMU_AHB1ENR_GPIOEN_MSK BIT(CMU_AHB1ENR_GPIOEN_POS) + +/****************** Bit definition for CMU_APB1ENR register ************************/ + +#define CMU_APB1ENR_CAN0EN_POS 24U +#define CMU_APB1ENR_CAN0EN_MSK BIT(CMU_APB1ENR_CAN0EN_POS) + +#define CMU_APB1ENR_I2C1EN_POS 21U +#define CMU_APB1ENR_I2C1EN_MSK BIT(CMU_APB1ENR_I2C1EN_POS) + +#define CMU_APB1ENR_I2C0EN_POS 20U +#define CMU_APB1ENR_I2C0EN_MSK BIT(CMU_APB1ENR_I2C0EN_POS) + +#define CMU_APB1ENR_SPI2EN_POS 18U +#define CMU_APB1ENR_SPI2EN_MSK BIT(CMU_APB1ENR_SPI2EN_POS) + +#define CMU_APB1ENR_SPI1EN_POS 17U +#define CMU_APB1ENR_SPI1EN_MSK BIT(CMU_APB1ENR_SPI1EN_POS) + +#define CMU_APB1ENR_SPI0EN_POS 16U +#define CMU_APB1ENR_SPI0EN_MSK BIT(CMU_APB1ENR_SPI0EN_POS) + +#define CMU_APB1ENR_USART1EN_POS 13U +#define CMU_APB1ENR_USART1EN_MSK BIT(CMU_APB1ENR_USART1EN_POS) + +#define CMU_APB1ENR_USART0EN_POS 12U +#define CMU_APB1ENR_USART0EN_MSK BIT(CMU_APB1ENR_USART0EN_POS) + +#define CMU_APB1ENR_UART3EN_POS 11U +#define CMU_APB1ENR_UART3EN_MSK BIT(CMU_APB1ENR_UART3EN_POS) + +#define CMU_APB1ENR_UART2EN_POS 10U +#define CMU_APB1ENR_UART2EN_MSK BIT(CMU_APB1ENR_UART2EN_POS) + +#define CMU_APB1ENR_UART1EN_POS 9U +#define CMU_APB1ENR_UART1EN_MSK BIT(CMU_APB1ENR_UART1EN_POS) + +#define CMU_APB1ENR_UART0EN_POS 8U +#define CMU_APB1ENR_UART0EN_MSK BIT(CMU_APB1ENR_UART0EN_POS) + +#define CMU_APB1ENR_TIM7EN_POS 7U +#define CMU_APB1ENR_TIM7EN_MSK BIT(CMU_APB1ENR_TIM7EN_POS) + +#define CMU_APB1ENR_TIM6EN_POS 6U +#define CMU_APB1ENR_TIM6EN_MSK BIT(CMU_APB1ENR_TIM6EN_POS) + +#define CMU_APB1ENR_TIM5EN_POS 5U +#define CMU_APB1ENR_TIM5EN_MSK BIT(CMU_APB1ENR_TIM5EN_POS) + +#define CMU_APB1ENR_TIM4EN_POS 4U +#define CMU_APB1ENR_TIM4EN_MSK BIT(CMU_APB1ENR_TIM4EN_POS) + +#define CMU_APB1ENR_TIM3EN_POS 3U +#define CMU_APB1ENR_TIM3EN_MSK BIT(CMU_APB1ENR_TIM3EN_POS) + +#define CMU_APB1ENR_TIM2EN_POS 2U +#define CMU_APB1ENR_TIM2EN_MSK BIT(CMU_APB1ENR_TIM2EN_POS) + +#define CMU_APB1ENR_TIM1EN_POS 1U +#define CMU_APB1ENR_TIM1EN_MSK BIT(CMU_APB1ENR_TIM1EN_POS) + +#define CMU_APB1ENR_TIM0EN_POS 0U +#define CMU_APB1ENR_TIM0EN_MSK BIT(CMU_APB1ENR_TIM0EN_POS) + +/****************** Bit definition for CMU_APB2ENR register ************************/ + +#define CMU_APB2ENR_DBGCEN_POS 19U +#define CMU_APB2ENR_DBGCEN_MSK BIT(CMU_APB2ENR_DBGCEN_POS) + +#define CMU_APB2ENR_BKPCEN_POS 17U +#define CMU_APB2ENR_BKPCEN_MSK BIT(CMU_APB2ENR_BKPCEN_POS) + +#define CMU_APB2ENR_TEMPEN_POS 16U +#define CMU_APB2ENR_TEMPEN_MSK BIT(CMU_APB2ENR_TEMPEN_POS) + +#define CMU_APB2ENR_RTCEN_POS 15U +#define CMU_APB2ENR_RTCEN_MSK BIT(CMU_APB2ENR_RTCEN_POS) + +#define CMU_APB2ENR_IWDTEN_POS 14U +#define CMU_APB2ENR_IWDTEN_MSK BIT(CMU_APB2ENR_IWDTEN_POS) + +#define CMU_APB2ENR_LCDEN_POS 13U +#define CMU_APB2ENR_LCDEN_MSK BIT(CMU_APB2ENR_LCDEN_POS) + +#define CMU_APB2ENR_WWDTEN_POS 12U +#define CMU_APB2ENR_WWDTEN_MSK BIT(CMU_APB2ENR_WWDTEN_POS) + +#define CMU_APB2ENR_OPAMPEN_POS 8U +#define CMU_APB2ENR_OPAMPEN_MSK BIT(CMU_APB2ENR_OPAMPEN_POS) + +#define CMU_APB2ENR_ACMP1EN_POS 7U +#define CMU_APB2ENR_ACMP1EN_MSK BIT(CMU_APB2ENR_ACMP1EN_POS) + +#define CMU_APB2ENR_ACMP0EN_POS 6U +#define CMU_APB2ENR_ACMP0EN_MSK BIT(CMU_APB2ENR_ACMP0EN_POS) + +#define CMU_APB2ENR_ADC0EN_POS 4U +#define CMU_APB2ENR_ADC0EN_MSK BIT(CMU_APB2ENR_ADC0EN_POS) + +#define CMU_APB2ENR_LPUART0EN_POS 2U +#define CMU_APB2ENR_LPUART0EN_MSK BIT(CMU_APB2ENR_LPUART0EN_POS) + +#define CMU_APB2ENR_LPTIM0EN_POS 0U +#define CMU_APB2ENR_LPTIM0EN_MSK BIT(CMU_APB2ENR_LPTIM0EN_POS) + +/****************** Bit definition for CMU_LPENR register ************************/ + +#define CMU_LPENR_HOSCEN_POS 3U +#define CMU_LPENR_HOSCEN_MSK BIT(CMU_LPENR_HOSCEN_POS) + +#define CMU_LPENR_HRCEN_POS 2U +#define CMU_LPENR_HRCEN_MSK BIT(CMU_LPENR_HRCEN_POS) + +#define CMU_LPENR_LOSCEN_POS 1U +#define CMU_LPENR_LOSCEN_MSK BIT(CMU_LPENR_LOSCEN_POS) + +#define CMU_LPENR_LRCEN_POS 0U +#define CMU_LPENR_LRCEN_MSK BIT(CMU_LPENR_LRCEN_POS) + +/****************** Bit definition for CMU_PERICR register ************************/ + +#define CMU_PERICR_LCD_POSS 16U +#define CMU_PERICR_LCD_POSE 18U +#define CMU_PERICR_LCD_MSK BITS(CMU_PERICR_LCD_POSS,CMU_PERICR_LCD_POSE) + +#define CMU_PERICR_LPUART0_POSS 8U +#define CMU_PERICR_LPUART0_POSE 11U +#define CMU_PERICR_LPUART0_MSK BITS(CMU_PERICR_LPUART0_POSS,CMU_PERICR_LPUART0_POSE) + +#define CMU_PERICR_LPTIM0_POSS 0U +#define CMU_PERICR_LPTIM0_POSE 3U +#define CMU_PERICR_LPTIM0_MSK BITS(CMU_PERICR_LPTIM0_POSS,CMU_PERICR_LPTIM0_POSE) + +/****************** Bit definition for CMU_HRCACR register ************************/ + +#define CMU_HRCACR_IB_POSS 28U +#define CMU_HRCACR_IB_POSE 29U +#define CMU_HRCACR_IB_MSK BITS(CMU_HRCACR_IB_POSS,CMU_HRCACR_IB_POSE) + +#define CMU_HRCACR_CAP_POSS 26U +#define CMU_HRCACR_CAP_POSE 27U +#define CMU_HRCACR_CAP_MSK BITS(CMU_HRCACR_CAP_POSS,CMU_HRCACR_CAP_POSE) + +#define CMU_HRCACR_CAL_POSS 16U +#define CMU_HRCACR_CAL_POSE 25U +#define CMU_HRCACR_CAL_MSK BITS(CMU_HRCACR_CAL_POSS,CMU_HRCACR_CAL_POSE) + +#define CMU_HRCACR_IBSET_POSS 14U +#define CMU_HRCACR_IBSET_POSE 15U +#define CMU_HRCACR_IBSET_MSK BITS(CMU_HRCACR_IBSET_POSS,CMU_HRCACR_IBSET_POSE) + +#define CMU_HRCACR_CAPSET_POSS 12U +#define CMU_HRCACR_CAPSET_POSE 13U +#define CMU_HRCACR_CAPSET_MSK BITS(CMU_HRCACR_CAPSET_POSS,CMU_HRCACR_CAPSET_POSE) + +#define CMU_HRCACR_STA_POSS 9U +#define CMU_HRCACR_STA_POSE 10U +#define CMU_HRCACR_STA_MSK BITS(CMU_HRCACR_STA_POSS,CMU_HRCACR_STA_POSE) + +#define CMU_HRCACR_BUSY_POS 8U +#define CMU_HRCACR_BUSY_MSK BIT(CMU_HRCACR_BUSY_POS) + +#define CMU_HRCACR_WRTRG_POS 7U +#define CMU_HRCACR_WRTRG_MSK BIT(CMU_HRCACR_WRTRG_POS) + +#define CMU_HRCACR_AC_POSS 4U +#define CMU_HRCACR_AC_POSE 6U +#define CMU_HRCACR_AC_MSK BITS(CMU_HRCACR_AC_POSS,CMU_HRCACR_AC_POSE) + +#define CMU_HRCACR_IBS_POS 3U +#define CMU_HRCACR_IBS_MSK BIT(CMU_HRCACR_IBS_POS) + +#define CMU_HRCACR_RFSEL_POS 2U +#define CMU_HRCACR_RFSEL_MSK BIT(CMU_HRCACR_RFSEL_POS) + +#define CMU_HRCACR_FREQ_POS 1U +#define CMU_HRCACR_FREQ_MSK BIT(CMU_HRCACR_FREQ_POS) + +#define CMU_HRCACR_EN_POS 0U +#define CMU_HRCACR_EN_MSK BIT(CMU_HRCACR_EN_POS) + +typedef struct +{ + __O uint32_t CSR; + __IO uint32_t CFGR; + uint32_t RESERVED0[2] ; + __IO uint32_t CLKENR; + __I uint32_t CLKSR; + __IO uint32_t PLLCFG; + __IO uint32_t HOSCCFG; + __IO uint32_t HOSMCR; + __IO uint32_t LOSMCR; + __IO uint32_t PULMCR; + uint32_t RESERVED1 ; + __IO uint32_t CLKOCR; + __IO uint32_t BUZZCR; + uint32_t RESERVED2[2] ; + __IO uint32_t AHB1ENR; + uint32_t RESERVED3[3] ; + __IO uint32_t APB1ENR; + __IO uint32_t APB2ENR; + uint32_t RESERVED4[2] ; + __IO uint32_t LPENR; + uint32_t RESERVED5[7] ; + __IO uint32_t PERICR; + uint32_t RESERVED6[3] ; + __IO uint32_t HRCACR; +} CMU_TypeDef; + +/****************** Bit definition for DMA_STATUS register ************************/ + +#define DMA_STATUS_STATUS_POSS 4U +#define DMA_STATUS_STATUS_POSE 7U +#define DMA_STATUS_STATUS_MSK BITS(DMA_STATUS_STATUS_POSS,DMA_STATUS_STATUS_POSE) + +#define DMA_STATUS_MASTER_ENABLE_POS 0U +#define DMA_STATUS_MASTER_ENABLE_MSK BIT(DMA_STATUS_MASTER_ENABLE_POS) + +/****************** Bit definition for DMA_CFG register ************************/ + +#define DMA_CFG_CHNL_PROT_CTRL_POSS 5U +#define DMA_CFG_CHNL_PROT_CTRL_POSE 7U +#define DMA_CFG_CHNL_PROT_CTRL_MSK BITS(DMA_CFG_CHNL_PROT_CTRL_POSS,DMA_CFG_CHNL_PROT_CTRL_POSE) + +#define DMA_CFG_MASTER_ENABLE_POS 0U +#define DMA_CFG_MASTER_ENABLE_MSK BIT(DMA_CFG_MASTER_ENABLE_POS) + +/****************** Bit definition for DMA_CTRLBASE register ************************/ + +#define DMA_CTRLBASE_CTRL_BASE_PTR_POSS 9U +#define DMA_CTRLBASE_CTRL_BASE_PTR_POSE 31U +#define DMA_CTRLBASE_CTRL_BASE_PTR_MSK BITS(DMA_CTRLBASE_CTRL_BASE_PTR_POSS,DMA_CTRLBASE_CTRL_BASE_PTR_POSE) + +/****************** Bit definition for DMA_ALTCTRLBASE register ************************/ + +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS 0U +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE 31U +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_MSK BITS(DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS,DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE) + +/****************** Bit definition for DMA_CHWAITSTATUS register ************************/ + +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS 0U +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE 31U +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_MSK BITS(DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS,DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE) + +/****************** Bit definition for DMA_CHSWREQ register ************************/ + +#define DMA_CHSWREQ_CHSWREQ_POSS 0U +#define DMA_CHSWREQ_CHSWREQ_POSE 31U +#define DMA_CHSWREQ_CHSWREQ_MSK BITS(DMA_CHSWREQ_CHSWREQ_POSS,DMA_CHSWREQ_CHSWREQ_POSE) + +/****************** Bit definition for DMA_CHUSEBURSTSET register ************************/ + +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS 0U +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE 31U +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_MSK BITS(DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS,DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE) + +/****************** Bit definition for DMA_CHUSEBURSTCLR register ************************/ + +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS 0U +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE 31U +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_MSK BITS(DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS,DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE) + +/****************** Bit definition for DMA_CHREQMASKSET register ************************/ + +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS 0U +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE 31U +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_MSK BITS(DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS,DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE) + +/****************** Bit definition for DMA_CHREQMASKCLR register ************************/ + +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS 0U +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE 31U +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_MSK BITS(DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS,DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE) + +/****************** Bit definition for DMA_CHENSET register ************************/ + +#define DMA_CHENSET_CHNL_ENABLE_SET_POSS 0U +#define DMA_CHENSET_CHNL_ENABLE_SET_POSE 31U +#define DMA_CHENSET_CHNL_ENABLE_SET_MSK BITS(DMA_CHENSET_CHNL_ENABLE_SET_POSS,DMA_CHENSET_CHNL_ENABLE_SET_POSE) + +/****************** Bit definition for DMA_CHENCLR register ************************/ + +#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSS 0U +#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSE 31U +#define DMA_CHENCLR_CHNL_ENABLE_CLR_MSK BITS(DMA_CHENCLR_CHNL_ENABLE_CLR_POSS,DMA_CHENCLR_CHNL_ENABLE_CLR_POSE) + +/****************** Bit definition for DMA_CHPRIALTSET register ************************/ + +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS 0U +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE 31U +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_MSK BITS(DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS,DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE) + +/****************** Bit definition for DMA_CHPRIALTCLR register ************************/ + +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS 0U +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE 31U +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_MSK BITS(DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS,DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE) + +/****************** Bit definition for DMA_CHPRSET register ************************/ + +#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSS 0U +#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSE 31U +#define DMA_CHPRSET_CHNL_PRIORITY_SET_MSK BITS(DMA_CHPRSET_CHNL_PRIORITY_SET_POSS,DMA_CHPRSET_CHNL_PRIORITY_SET_POSE) + +/****************** Bit definition for DMA_CHPRCLR register ************************/ + +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS 0U +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE 31U +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_MSK BITS(DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS,DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE) + +/****************** Bit definition for DMA_ERRCLR register ************************/ + +#define DMA_ERRCLR_ERR_CLR_POS 0U +#define DMA_ERRCLR_ERR_CLR_MSK BIT(DMA_ERRCLR_ERR_CLR_POS) + +/****************** Bit definition for DMA_IFLAG register ************************/ + +#define DMA_IFLAG_DMAERRIF_POS 31U +#define DMA_IFLAG_DMAERRIF_MSK BIT(DMA_IFLAG_DMAERRIF_POS) + +#define DMA_IFLAG_CH5DONEIF_POS 5U +#define DMA_IFLAG_CH5DONEIF_MSK BIT(DMA_IFLAG_CH5DONEIF_POS) + +#define DMA_IFLAG_CH4DONEIF_POS 4U +#define DMA_IFLAG_CH4DONEIF_MSK BIT(DMA_IFLAG_CH4DONEIF_POS) + +#define DMA_IFLAG_CH3DONEIF_POS 3U +#define DMA_IFLAG_CH3DONEIF_MSK BIT(DMA_IFLAG_CH3DONEIF_POS) + +#define DMA_IFLAG_CH2DONEIF_POS 2U +#define DMA_IFLAG_CH2DONEIF_MSK BIT(DMA_IFLAG_CH2DONEIF_POS) + +#define DMA_IFLAG_CH1DONEIF_POS 1U +#define DMA_IFLAG_CH1DONEIF_MSK BIT(DMA_IFLAG_CH1DONEIF_POS) + +#define DMA_IFLAG_CH0DONEIF_POS 0U +#define DMA_IFLAG_CH0DONEIF_MSK BIT(DMA_IFLAG_CH0DONEIF_POS) + +/****************** Bit definition for DMA_ICFR register ************************/ + +#define DMA_ICFR_DMAERRC_POS 31U +#define DMA_ICFR_DMAERRC_MSK BIT(DMA_ICFR_DMAERRC_POS) + +#define DMA_ICFR_CH5DONEC_POS 5U +#define DMA_ICFR_CH5DONEC_MSK BIT(DMA_ICFR_CH5DONEC_POS) + +#define DMA_ICFR_CH4DONEC_POS 4U +#define DMA_ICFR_CH4DONEC_MSK BIT(DMA_ICFR_CH4DONEC_POS) + +#define DMA_ICFR_CH3DONEC_POS 3U +#define DMA_ICFR_CH3DONEC_MSK BIT(DMA_ICFR_CH3DONEC_POS) + +#define DMA_ICFR_CH2DONEC_POS 2U +#define DMA_ICFR_CH2DONEC_MSK BIT(DMA_ICFR_CH2DONEC_POS) + +#define DMA_ICFR_CH1DONEC_POS 1U +#define DMA_ICFR_CH1DONEC_MSK BIT(DMA_ICFR_CH1DONEC_POS) + +#define DMA_ICFR_CH0DONEC_POS 0U +#define DMA_ICFR_CH0DONEC_MSK BIT(DMA_ICFR_CH0DONEC_POS) + +/****************** Bit definition for DMA_IER register ************************/ + +#define DMA_IER_DMAERRIE_POS 31U +#define DMA_IER_DMAERRIE_MSK BIT(DMA_IER_DMAERRIE_POS) + +#define DMA_IER_CH5DONEIE_POS 5U +#define DMA_IER_CH5DONEIE_MSK BIT(DMA_IER_CH5DONEIE_POS) + +#define DMA_IER_CH4DONEIE_POS 4U +#define DMA_IER_CH4DONEIE_MSK BIT(DMA_IER_CH4DONEIE_POS) + +#define DMA_IER_CH3DONEIE_POS 3U +#define DMA_IER_CH3DONEIE_MSK BIT(DMA_IER_CH3DONEIE_POS) + +#define DMA_IER_CH2DONEIE_POS 2U +#define DMA_IER_CH2DONEIE_MSK BIT(DMA_IER_CH2DONEIE_POS) + +#define DMA_IER_CH1DONEIE_POS 1U +#define DMA_IER_CH1DONEIE_MSK BIT(DMA_IER_CH1DONEIE_POS) + +#define DMA_IER_CH0DONEIE_POS 0U +#define DMA_IER_CH0DONEIE_MSK BIT(DMA_IER_CH0DONEIE_POS) + +/****************** Bit definition for DMA_CH0_SELCON register ************************/ + +#define DMA_CH0_SELCON_MSEL_POSS 8U +#define DMA_CH0_SELCON_MSEL_POSE 13U +#define DMA_CH0_SELCON_MSEL_MSK BITS(DMA_CH0_SELCON_MSEL_POSS,DMA_CH0_SELCON_MSEL_POSE) + +#define DMA_CH0_SELCON_MSIGSEL_POSS 0U +#define DMA_CH0_SELCON_MSIGSEL_POSE 3U +#define DMA_CH0_SELCON_MSIGSEL_MSK BITS(DMA_CH0_SELCON_MSIGSEL_POSS,DMA_CH0_SELCON_MSIGSEL_POSE) + +typedef struct +{ + __I uint32_t STATUS; + __IO uint32_t CFG; + __IO uint32_t CTRLBASE; + __I uint32_t ALTCTRLBASE; + __I uint32_t CHWAITSTATUS; + __IO uint32_t CHSWREQ; + __IO uint32_t CHUSEBURSTSET; + __O uint32_t CHUSEBURSTCLR; + __IO uint32_t CHREQMASKSET; + __O uint32_t CHREQMASKCLR; + __IO uint32_t CHENSET; + __O uint32_t CHENCLR; + __IO uint32_t CHPRIALTSET; + __O uint32_t CHPRIALTCLR; + __IO uint32_t CHPRSET; + __O uint32_t CHPRCLR; + uint32_t RESERVED0[3] ; + __IO uint32_t ERRCLR; + uint32_t RESERVED1[1004] ; + __I uint32_t IFLAG; + uint32_t RESERVED2 ; + __O uint32_t ICFR; + __IO uint32_t IER; + uint32_t RESERVED3[60] ; + __IO uint32_t CH_SELCON[6]; +} DMA_TypeDef; + +/****************** Bit definition for PIS_CH0_CON register ************************/ + +#define PIS_CH0_CON_SYNCSEL_POSS 24U +#define PIS_CH0_CON_SYNCSEL_POSE 26U +#define PIS_CH0_CON_SYNCSEL_MSK BITS(PIS_CH0_CON_SYNCSEL_POSS,PIS_CH0_CON_SYNCSEL_POSE) + +#define PIS_CH0_CON_PULCK_POSS 18U +#define PIS_CH0_CON_PULCK_POSE 19U +#define PIS_CH0_CON_PULCK_MSK BITS(PIS_CH0_CON_PULCK_POSS,PIS_CH0_CON_PULCK_POSE) + +#define PIS_CH0_CON_EDGS_POSS 16U +#define PIS_CH0_CON_EDGS_POSE 17U +#define PIS_CH0_CON_EDGS_MSK BITS(PIS_CH0_CON_EDGS_POSS,PIS_CH0_CON_EDGS_POSE) + +#define PIS_CH0_CON_SRCS_POSS 8U +#define PIS_CH0_CON_SRCS_POSE 13U +#define PIS_CH0_CON_SRCS_MSK BITS(PIS_CH0_CON_SRCS_POSS,PIS_CH0_CON_SRCS_POSE) + +#define PIS_CH0_CON_MSIGS_POSS 0U +#define PIS_CH0_CON_MSIGS_POSE 3U +#define PIS_CH0_CON_MSIGS_MSK BITS(PIS_CH0_CON_MSIGS_POSS,PIS_CH0_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH_OER register ************************/ + +#define PIS_CH_OER_CH3OE_POS 3U +#define PIS_CH_OER_CH3OE_MSK BIT(PIS_CH_OER_CH3OE_POS) + +#define PIS_CH_OER_CH2OE_POS 2U +#define PIS_CH_OER_CH2OE_MSK BIT(PIS_CH_OER_CH2OE_POS) + +#define PIS_CH_OER_CH1OE_POS 1U +#define PIS_CH_OER_CH1OE_MSK BIT(PIS_CH_OER_CH1OE_POS) + +#define PIS_CH_OER_CH0OE_POS 0U +#define PIS_CH_OER_CH0OE_MSK BIT(PIS_CH_OER_CH0OE_POS) + +/****************** Bit definition for PIS_TAR_CON0 register ************************/ + +#define PIS_TAR_CON0_TIM3_CH2IN_SEL_POS 25U +#define PIS_TAR_CON0_TIM3_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH1IN_SEL_POS 24U +#define PIS_TAR_CON0_TIM3_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH2IN_SEL_POS 17U +#define PIS_TAR_CON0_TIM2_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH1IN_SEL_POS 16U +#define PIS_TAR_CON0_TIM2_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_BRKIN_SEL_POS 4U +#define PIS_TAR_CON0_TIM0_BRKIN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_BRKIN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH4IN_SEL_POS 3U +#define PIS_TAR_CON0_TIM0_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH3IN_SEL_POS 2U +#define PIS_TAR_CON0_TIM0_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH2IN_SEL_POS 1U +#define PIS_TAR_CON0_TIM0_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH1IN_SEL_POS 0U +#define PIS_TAR_CON0_TIM0_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH1IN_SEL_POS) + +/****************** Bit definition for PIS_TAR_CON1 register ************************/ + +#define PIS_TAR_CON1_SPI1_CLK_SEL_POS 15U +#define PIS_TAR_CON1_SPI1_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI1_CLK_SEL_POS) + +#define PIS_TAR_CON1_SPI1_RX_SEL_POS 14U +#define PIS_TAR_CON1_SPI1_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI1_RX_SEL_POS) + +#define PIS_TAR_CON1_SPI0_CLK_SEL_POS 13U +#define PIS_TAR_CON1_SPI0_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI0_CLK_SEL_POS) + +#define PIS_TAR_CON1_SPI0_RX_SEL_POS 12U +#define PIS_TAR_CON1_SPI0_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI0_RX_SEL_POS) + +#define PIS_TAR_CON1_LPUART0_RXD_SEL_POS 8U +#define PIS_TAR_CON1_LPUART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_LPUART0_RXD_SEL_POS) + +#define PIS_TAR_CON1_USART1_RXD_SEL_POS 7U +#define PIS_TAR_CON1_USART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_USART1_RXD_SEL_POS) + +#define PIS_TAR_CON1_USART0_RXD_SEL_POS 6U +#define PIS_TAR_CON1_USART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_USART0_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART3_RXD_SEL_POS 3U +#define PIS_TAR_CON1_UART3_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART3_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART2_RXD_SEL_POS 2U +#define PIS_TAR_CON1_UART2_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART2_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART1_RXD_SEL_POS 1U +#define PIS_TAR_CON1_UART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART1_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART0_RXD_SEL_POS 0U +#define PIS_TAR_CON1_UART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART0_RXD_SEL_POS) + +/****************** Bit definition for PIS_TXMCR register ************************/ + +#define PIS_TXMCR_TXMLVLS_POS 8U +#define PIS_TXMCR_TXMLVLS_MSK BIT(PIS_TXMCR_TXMLVLS_POS) + +#define PIS_TXMCR_TXMSS_POSS 4U +#define PIS_TXMCR_TXMSS_POSE 7U +#define PIS_TXMCR_TXMSS_MSK BITS(PIS_TXMCR_TXMSS_POSS,PIS_TXMCR_TXMSS_POSE) + +#define PIS_TXMCR_TXSIGS_POSS 0U +#define PIS_TXMCR_TXSIGS_POSE 3U +#define PIS_TXMCR_TXSIGS_MSK BITS(PIS_TXMCR_TXSIGS_POSS,PIS_TXMCR_TXSIGS_POSE) + +typedef struct +{ + __IO uint32_t CH_CON[8]; + uint32_t RESERVED0[8] ; + __IO uint32_t CH_OER; + __IO uint32_t TAR_CON0; + __IO uint32_t TAR_CON1; + uint32_t RESERVED1[5] ; + __IO uint32_t UART0_TXMCR; + __IO uint32_t UART1_TXMCR; + __IO uint32_t UART2_TXMCR; + __IO uint32_t UART3_TXMCR; + __IO uint32_t LPUART0_TXMCR; +} PIS_TypeDef; + +/****************** Bit definition for GPIO_DIN register ************************/ + +#define GPIO_DIN_DIN_POSS 0U +#define GPIO_DIN_DIN_POSE 15U +#define GPIO_DIN_DIN_MSK BITS(GPIO_DIN_DIN_POSS,GPIO_DIN_DIN_POSE) + +/****************** Bit definition for GPIO_DOUT register ************************/ + +#define GPIO_DOUT_DOUT_POSS 0U +#define GPIO_DOUT_DOUT_POSE 15U +#define GPIO_DOUT_DOUT_MSK BITS(GPIO_DOUT_DOUT_POSS,GPIO_DOUT_DOUT_POSE) + +/****************** Bit definition for GPIO_BSRR register ************************/ + +#define GPIO_BSRR_BRR_POSS 16U +#define GPIO_BSRR_BRR_POSE 31U +#define GPIO_BSRR_BRR_MSK BITS(GPIO_BSRR_BRR_POSS,GPIO_BSRR_BRR_POSE) + +#define GPIO_BSRR_BSR_POSS 0U +#define GPIO_BSRR_BSR_POSE 15U +#define GPIO_BSRR_BSR_MSK BITS(GPIO_BSRR_BSR_POSS,GPIO_BSRR_BSR_POSE) + +/****************** Bit definition for GPIO_BIR register ************************/ + +#define GPIO_BIR_BIR_POSS 0U +#define GPIO_BIR_BIR_POSE 15U +#define GPIO_BIR_BIR_MSK BITS(GPIO_BIR_BIR_POSS,GPIO_BIR_BIR_POSE) + +/****************** Bit definition for GPIO_MODE register ************************/ + +#define GPIO_MODE_MODE_POSS 0U +#define GPIO_MODE_MODE_POSE 31U +#define GPIO_MODE_MODE_MSK BITS(GPIO_MODE_MODE_POSS,GPIO_MODE_MODE_POSE) + +/****************** Bit definition for GPIO_ODOS register ************************/ + +#define GPIO_ODOS_ODOS_POSS 0U +#define GPIO_ODOS_ODOS_POSE 31U +#define GPIO_ODOS_ODOS_MSK BITS(GPIO_ODOS_ODOS_POSS,GPIO_ODOS_ODOS_POSE) + +/****************** Bit definition for GPIO_PUPD register ************************/ + +#define GPIO_PUPD_PUPD_POSS 0U +#define GPIO_PUPD_PUPD_POSE 31U +#define GPIO_PUPD_PUPD_MSK BITS(GPIO_PUPD_PUPD_POSS,GPIO_PUPD_PUPD_POSE) + +/****************** Bit definition for GPIO_ODRV register ************************/ + +#define GPIO_ODRV_ODRV_POSS 0U +#define GPIO_ODRV_ODRV_POSE 31U +#define GPIO_ODRV_ODRV_MSK BITS(GPIO_ODRV_ODRV_POSS,GPIO_ODRV_ODRV_POSE) + +/****************** Bit definition for GPIO_FLT register ************************/ + +#define GPIO_FLT_FLT_POSS 0U +#define GPIO_FLT_FLT_POSE 15U +#define GPIO_FLT_FLT_MSK BITS(GPIO_FLT_FLT_POSS,GPIO_FLT_FLT_POSE) + +/****************** Bit definition for GPIO_TYPE register ************************/ + +#define GPIO_TYPE_TYPE_POSS 0U +#define GPIO_TYPE_TYPE_POSE 15U +#define GPIO_TYPE_TYPE_MSK BITS(GPIO_TYPE_TYPE_POSS,GPIO_TYPE_TYPE_POSE) + +/****************** Bit definition for GPIO_FUNC0 register ************************/ + +#define GPIO_FUNC0_FSEL_IO7_POSS 28U +#define GPIO_FUNC0_FSEL_IO7_POSE 31U +#define GPIO_FUNC0_FSEL_IO7_MSK BITS(GPIO_FUNC0_FSEL_IO7_POSS,GPIO_FUNC0_FSEL_IO7_POSE) + +#define GPIO_FUNC0_FSEL_IO6_POSS 24U +#define GPIO_FUNC0_FSEL_IO6_POSE 27U +#define GPIO_FUNC0_FSEL_IO6_MSK BITS(GPIO_FUNC0_FSEL_IO6_POSS,GPIO_FUNC0_FSEL_IO6_POSE) + +#define GPIO_FUNC0_FSEL_IO5_POSS 20U +#define GPIO_FUNC0_FSEL_IO5_POSE 23U +#define GPIO_FUNC0_FSEL_IO5_MSK BITS(GPIO_FUNC0_FSEL_IO5_POSS,GPIO_FUNC0_FSEL_IO5_POSE) + +#define GPIO_FUNC0_FSEL_IO4_POSS 16U +#define GPIO_FUNC0_FSEL_IO4_POSE 19U +#define GPIO_FUNC0_FSEL_IO4_MSK BITS(GPIO_FUNC0_FSEL_IO4_POSS,GPIO_FUNC0_FSEL_IO4_POSE) + +#define GPIO_FUNC0_FSEL_IO3_POSS 12U +#define GPIO_FUNC0_FSEL_IO3_POSE 15U +#define GPIO_FUNC0_FSEL_IO3_MSK BITS(GPIO_FUNC0_FSEL_IO3_POSS,GPIO_FUNC0_FSEL_IO3_POSE) + +#define GPIO_FUNC0_FSEL_IO2_POSS 8U +#define GPIO_FUNC0_FSEL_IO2_POSE 11U +#define GPIO_FUNC0_FSEL_IO2_MSK BITS(GPIO_FUNC0_FSEL_IO2_POSS,GPIO_FUNC0_FSEL_IO2_POSE) + +#define GPIO_FUNC0_FSEL_IO1_POSS 4U +#define GPIO_FUNC0_FSEL_IO1_POSE 7U +#define GPIO_FUNC0_FSEL_IO1_MSK BITS(GPIO_FUNC0_FSEL_IO1_POSS,GPIO_FUNC0_FSEL_IO1_POSE) + +#define GPIO_FUNC0_FSEL_IO0_POSS 0U +#define GPIO_FUNC0_FSEL_IO0_POSE 3U +#define GPIO_FUNC0_FSEL_IO0_MSK BITS(GPIO_FUNC0_FSEL_IO0_POSS,GPIO_FUNC0_FSEL_IO0_POSE) + +/****************** Bit definition for GPIO_FUNC1 register ************************/ + +#define GPIO_FUNC1_FSEL_IO15_POSS 28U +#define GPIO_FUNC1_FSEL_IO15_POSE 31U +#define GPIO_FUNC1_FSEL_IO15_MSK BITS(GPIO_FUNC1_FSEL_IO15_POSS,GPIO_FUNC1_FSEL_IO15_POSE) + +#define GPIO_FUNC1_FSEL_IO14_POSS 24U +#define GPIO_FUNC1_FSEL_IO14_POSE 27U +#define GPIO_FUNC1_FSEL_IO14_MSK BITS(GPIO_FUNC1_FSEL_IO14_POSS,GPIO_FUNC1_FSEL_IO14_POSE) + +#define GPIO_FUNC1_FSEL_IO13_POSS 20U +#define GPIO_FUNC1_FSEL_IO13_POSE 23U +#define GPIO_FUNC1_FSEL_IO13_MSK BITS(GPIO_FUNC1_FSEL_IO13_POSS,GPIO_FUNC1_FSEL_IO13_POSE) + +#define GPIO_FUNC1_FSEL_IO12_POSS 16U +#define GPIO_FUNC1_FSEL_IO12_POSE 19U +#define GPIO_FUNC1_FSEL_IO12_MSK BITS(GPIO_FUNC1_FSEL_IO12_POSS,GPIO_FUNC1_FSEL_IO12_POSE) + +#define GPIO_FUNC1_FSEL_IO11_POSS 12U +#define GPIO_FUNC1_FSEL_IO11_POSE 15U +#define GPIO_FUNC1_FSEL_IO11_MSK BITS(GPIO_FUNC1_FSEL_IO11_POSS,GPIO_FUNC1_FSEL_IO11_POSE) + +#define GPIO_FUNC1_FSEL_IO10_POSS 8U +#define GPIO_FUNC1_FSEL_IO10_POSE 11U +#define GPIO_FUNC1_FSEL_IO10_MSK BITS(GPIO_FUNC1_FSEL_IO10_POSS,GPIO_FUNC1_FSEL_IO10_POSE) + +#define GPIO_FUNC1_FSEL_IO9_POSS 4U +#define GPIO_FUNC1_FSEL_IO9_POSE 7U +#define GPIO_FUNC1_FSEL_IO9_MSK BITS(GPIO_FUNC1_FSEL_IO9_POSS,GPIO_FUNC1_FSEL_IO9_POSE) + +#define GPIO_FUNC1_FSEL_IO8_POSS 0U +#define GPIO_FUNC1_FSEL_IO8_POSE 3U +#define GPIO_FUNC1_FSEL_IO8_MSK BITS(GPIO_FUNC1_FSEL_IO8_POSS,GPIO_FUNC1_FSEL_IO8_POSE) + +/****************** Bit definition for GPIO_LOCK register ************************/ + +#define GPIO_LOCK_KEY_POSS 16U +#define GPIO_LOCK_KEY_POSE 31U +#define GPIO_LOCK_KEY_MSK BITS(GPIO_LOCK_KEY_POSS,GPIO_LOCK_KEY_POSE) + +#define GPIO_LOCK_LOCK_POSS 0U +#define GPIO_LOCK_LOCK_POSE 15U +#define GPIO_LOCK_LOCK_MSK BITS(GPIO_LOCK_LOCK_POSS,GPIO_LOCK_LOCK_POSE) + +typedef struct +{ + __I uint32_t DIN; + __IO uint32_t DOUT; + __O uint32_t BSRR; + __O uint32_t BIR; + __IO uint32_t MODE; + __IO uint32_t ODOS; + __IO uint32_t PUPD; + __IO uint32_t ODRV; + __IO uint32_t FLT; + __IO uint32_t TYPE; + __IO uint32_t FUNC0; + __IO uint32_t FUNC1; + __IO uint32_t LOCK; +} GPIO_TypeDef; + +/****************** Bit definition for GPIO_EXTIRER register ************************/ + +#define GPIO_EXTIRER_EXTIRER_POSS 0U +#define GPIO_EXTIRER_EXTIRER_POSE 15U +#define GPIO_EXTIRER_EXTIRER_MSK BITS(GPIO_EXTIRER_EXTIRER_POSS,GPIO_EXTIRER_EXTIRER_POSE) + +/****************** Bit definition for GPIO_EXTIFER register ************************/ + +#define GPIO_EXTIFER_EXTIFER_POSS 0U +#define GPIO_EXTIFER_EXTIFER_POSE 15U +#define GPIO_EXTIFER_EXTIFER_MSK BITS(GPIO_EXTIFER_EXTIFER_POSS,GPIO_EXTIFER_EXTIFER_POSE) + +/****************** Bit definition for GPIO_EXTIEN register ************************/ + +#define GPIO_EXTIEN_EXTIEN_POSS 0U +#define GPIO_EXTIEN_EXTIEN_POSE 15U +#define GPIO_EXTIEN_EXTIEN_MSK BITS(GPIO_EXTIEN_EXTIEN_POSS,GPIO_EXTIEN_EXTIEN_POSE) + +/****************** Bit definition for GPIO_EXTIFLAG register ************************/ + +#define GPIO_EXTIFLAG_EXTIFLAG_POSS 0U +#define GPIO_EXTIFLAG_EXTIFLAG_POSE 15U +#define GPIO_EXTIFLAG_EXTIFLAG_MSK BITS(GPIO_EXTIFLAG_EXTIFLAG_POSS,GPIO_EXTIFLAG_EXTIFLAG_POSE) + +/****************** Bit definition for GPIO_EXTISFR register ************************/ + +#define GPIO_EXTISFR_EXTISFR_POSS 0U +#define GPIO_EXTISFR_EXTISFR_POSE 15U +#define GPIO_EXTISFR_EXTISFR_MSK BITS(GPIO_EXTISFR_EXTISFR_POSS,GPIO_EXTISFR_EXTISFR_POSE) + +/****************** Bit definition for GPIO_EXTICFR register ************************/ + +#define GPIO_EXTICFR_EXTICFR_POSS 0U +#define GPIO_EXTICFR_EXTICFR_POSE 15U +#define GPIO_EXTICFR_EXTICFR_MSK BITS(GPIO_EXTICFR_EXTICFR_POSS,GPIO_EXTICFR_EXTICFR_POSE) + +/****************** Bit definition for GPIO_EXTIPSR0 register ************************/ + +#define GPIO_EXTIPSR0_EXTIS7_POSS 28U +#define GPIO_EXTIPSR0_EXTIS7_POSE 30U +#define GPIO_EXTIPSR0_EXTIS7_MSK BITS(GPIO_EXTIPSR0_EXTIS7_POSS,GPIO_EXTIPSR0_EXTIS7_POSE) + +#define GPIO_EXTIPSR0_EXTIS6_POSS 24U +#define GPIO_EXTIPSR0_EXTIS6_POSE 26U +#define GPIO_EXTIPSR0_EXTIS6_MSK BITS(GPIO_EXTIPSR0_EXTIS6_POSS,GPIO_EXTIPSR0_EXTIS6_POSE) + +#define GPIO_EXTIPSR0_EXTIS5_POSS 20U +#define GPIO_EXTIPSR0_EXTIS5_POSE 22U +#define GPIO_EXTIPSR0_EXTIS5_MSK BITS(GPIO_EXTIPSR0_EXTIS5_POSS,GPIO_EXTIPSR0_EXTIS5_POSE) + +#define GPIO_EXTIPSR0_EXTIS4_POSS 16U +#define GPIO_EXTIPSR0_EXTIS4_POSE 18U +#define GPIO_EXTIPSR0_EXTIS4_MSK BITS(GPIO_EXTIPSR0_EXTIS4_POSS,GPIO_EXTIPSR0_EXTIS4_POSE) + +#define GPIO_EXTIPSR0_EXTIS3_POSS 12U +#define GPIO_EXTIPSR0_EXTIS3_POSE 14U +#define GPIO_EXTIPSR0_EXTIS3_MSK BITS(GPIO_EXTIPSR0_EXTIS3_POSS,GPIO_EXTIPSR0_EXTIS3_POSE) + +#define GPIO_EXTIPSR0_EXTIS2_POSS 8U +#define GPIO_EXTIPSR0_EXTIS2_POSE 10U +#define GPIO_EXTIPSR0_EXTIS2_MSK BITS(GPIO_EXTIPSR0_EXTIS2_POSS,GPIO_EXTIPSR0_EXTIS2_POSE) + +#define GPIO_EXTIPSR0_EXTIS1_POSS 4U +#define GPIO_EXTIPSR0_EXTIS1_POSE 6U +#define GPIO_EXTIPSR0_EXTIS1_MSK BITS(GPIO_EXTIPSR0_EXTIS1_POSS,GPIO_EXTIPSR0_EXTIS1_POSE) + +#define GPIO_EXTIPSR0_EXTIS0_POSS 0U +#define GPIO_EXTIPSR0_EXTIS0_POSE 2U +#define GPIO_EXTIPSR0_EXTIS0_MSK BITS(GPIO_EXTIPSR0_EXTIS0_POSS,GPIO_EXTIPSR0_EXTIS0_POSE) + +/****************** Bit definition for GPIO_EXTIPSR1 register ************************/ + +#define GPIO_EXTIPSR1_EXTIS15_POSS 28U +#define GPIO_EXTIPSR1_EXTIS15_POSE 30U +#define GPIO_EXTIPSR1_EXTIS15_MSK BITS(GPIO_EXTIPSR1_EXTIS15_POSS,GPIO_EXTIPSR1_EXTIS15_POSE) + +#define GPIO_EXTIPSR1_EXTIS14_POSS 24U +#define GPIO_EXTIPSR1_EXTIS14_POSE 26U +#define GPIO_EXTIPSR1_EXTIS14_MSK BITS(GPIO_EXTIPSR1_EXTIS14_POSS,GPIO_EXTIPSR1_EXTIS14_POSE) + +#define GPIO_EXTIPSR1_EXTIS13_POSS 20U +#define GPIO_EXTIPSR1_EXTIS13_POSE 22U +#define GPIO_EXTIPSR1_EXTIS13_MSK BITS(GPIO_EXTIPSR1_EXTIS13_POSS,GPIO_EXTIPSR1_EXTIS13_POSE) + +#define GPIO_EXTIPSR1_EXTIS12_POSS 16U +#define GPIO_EXTIPSR1_EXTIS12_POSE 18U +#define GPIO_EXTIPSR1_EXTIS12_MSK BITS(GPIO_EXTIPSR1_EXTIS12_POSS,GPIO_EXTIPSR1_EXTIS12_POSE) + +#define GPIO_EXTIPSR1_EXTIS11_POSS 12U +#define GPIO_EXTIPSR1_EXTIS11_POSE 14U +#define GPIO_EXTIPSR1_EXTIS11_MSK BITS(GPIO_EXTIPSR1_EXTIS11_POSS,GPIO_EXTIPSR1_EXTIS11_POSE) + +#define GPIO_EXTIPSR1_EXTIS10_POSS 8U +#define GPIO_EXTIPSR1_EXTIS10_POSE 10U +#define GPIO_EXTIPSR1_EXTIS10_MSK BITS(GPIO_EXTIPSR1_EXTIS10_POSS,GPIO_EXTIPSR1_EXTIS10_POSE) + +#define GPIO_EXTIPSR1_EXTIS9_POSS 4U +#define GPIO_EXTIPSR1_EXTIS9_POSE 6U +#define GPIO_EXTIPSR1_EXTIS9_MSK BITS(GPIO_EXTIPSR1_EXTIS9_POSS,GPIO_EXTIPSR1_EXTIS9_POSE) + +#define GPIO_EXTIPSR1_EXTIS8_POSS 0U +#define GPIO_EXTIPSR1_EXTIS8_POSE 2U +#define GPIO_EXTIPSR1_EXTIS8_MSK BITS(GPIO_EXTIPSR1_EXTIS8_POSS,GPIO_EXTIPSR1_EXTIS8_POSE) + +/****************** Bit definition for GPIO_EXTIFLTCR register ************************/ + +#define GPIO_EXTIFLTCR_FLTCKS_POSS 24U +#define GPIO_EXTIFLTCR_FLTCKS_POSE 25U +#define GPIO_EXTIFLTCR_FLTCKS_MSK BITS(GPIO_EXTIFLTCR_FLTCKS_POSS,GPIO_EXTIFLTCR_FLTCKS_POSE) + +#define GPIO_EXTIFLTCR_FLTSEL_POSS 16U +#define GPIO_EXTIFLTCR_FLTSEL_POSE 23U +#define GPIO_EXTIFLTCR_FLTSEL_MSK BITS(GPIO_EXTIFLTCR_FLTSEL_POSS,GPIO_EXTIFLTCR_FLTSEL_POSE) + +#define GPIO_EXTIFLTCR_FLTEN_POSS 0U +#define GPIO_EXTIFLTCR_FLTEN_POSE 15U +#define GPIO_EXTIFLTCR_FLTEN_MSK BITS(GPIO_EXTIFLTCR_FLTEN_POSS,GPIO_EXTIFLTCR_FLTEN_POSE) + +typedef struct +{ + __IO uint32_t EXTIRER; + uint32_t RESERVED0 ; + __IO uint32_t EXTIFER; + uint32_t RESERVED1 ; + __IO uint32_t EXTIEN; + uint32_t RESERVED2 ; + __I uint32_t EXTIFLAG; + uint32_t RESERVED3 ; + __O uint32_t EXTISFR; + uint32_t RESERVED4 ; + __O uint32_t EXTICFR; + uint32_t RESERVED5 ; + __IO uint32_t EXTIPSR0; + __IO uint32_t EXTIPSR1; + uint32_t RESERVED6[2] ; + __IO uint32_t EXTIFLTCR; +} EXTI_TypeDef; + +/****************** Bit definition for RTC_WPR register ************************/ + +#define RTC_WPR_WP_POS 0U +#define RTC_WPR_WP_MSK BIT(RTC_WPR_WP_POS) + +/****************** Bit definition for RTC_CON register ************************/ + +#define RTC_CON_SSEC_POS 25U +#define RTC_CON_SSEC_MSK BIT(RTC_CON_SSEC_POS) + +#define RTC_CON_BUSY_POS 24U +#define RTC_CON_BUSY_MSK BIT(RTC_CON_BUSY_POS) + +#define RTC_CON_POL_POS 22U +#define RTC_CON_POL_MSK BIT(RTC_CON_POL_POS) + +#define RTC_CON_EOS_POSS 20U +#define RTC_CON_EOS_POSE 21U +#define RTC_CON_EOS_MSK BITS(RTC_CON_EOS_POSS,RTC_CON_EOS_POSE) + +#define RTC_CON_CKOS_POSS 17U +#define RTC_CON_CKOS_POSE 19U +#define RTC_CON_CKOS_MSK BITS(RTC_CON_CKOS_POSS,RTC_CON_CKOS_POSE) + +#define RTC_CON_CKOE_POS 16U +#define RTC_CON_CKOE_MSK BIT(RTC_CON_CKOE_POS) + +#define RTC_CON_WUCKS_POSS 13U +#define RTC_CON_WUCKS_POSE 15U +#define RTC_CON_WUCKS_MSK BITS(RTC_CON_WUCKS_POSS,RTC_CON_WUCKS_POSE) + +#define RTC_CON_WUTE_POS 12U +#define RTC_CON_WUTE_MSK BIT(RTC_CON_WUTE_POS) + +#define RTC_CON_DSTS_POS 10U +#define RTC_CON_DSTS_MSK BIT(RTC_CON_DSTS_POS) + +#define RTC_CON_SUB1H_POS 9U +#define RTC_CON_SUB1H_MSK BIT(RTC_CON_SUB1H_POS) + +#define RTC_CON_ADD1H_POS 8U +#define RTC_CON_ADD1H_MSK BIT(RTC_CON_ADD1H_POS) + +#define RTC_CON_TSPIN_POS 7U +#define RTC_CON_TSPIN_MSK BIT(RTC_CON_TSPIN_POS) + +#define RTC_CON_TSSEL_POS 6U +#define RTC_CON_TSSEL_MSK BIT(RTC_CON_TSSEL_POS) + +#define RTC_CON_TSEN_POS 5U +#define RTC_CON_TSEN_MSK BIT(RTC_CON_TSEN_POS) + +#define RTC_CON_SHDBP_POS 4U +#define RTC_CON_SHDBP_MSK BIT(RTC_CON_SHDBP_POS) + +#define RTC_CON_HFM_POS 3U +#define RTC_CON_HFM_MSK BIT(RTC_CON_HFM_POS) + +#define RTC_CON_ALMBEN_POS 2U +#define RTC_CON_ALMBEN_MSK BIT(RTC_CON_ALMBEN_POS) + +#define RTC_CON_ALMAEN_POS 1U +#define RTC_CON_ALMAEN_MSK BIT(RTC_CON_ALMAEN_POS) + +#define RTC_CON_GO_POS 0U +#define RTC_CON_GO_MSK BIT(RTC_CON_GO_POS) + +/****************** Bit definition for RTC_PSR register ************************/ + +#define RTC_PSR_APRS_POSS 16U +#define RTC_PSR_APRS_POSE 22U +#define RTC_PSR_APRS_MSK BITS(RTC_PSR_APRS_POSS,RTC_PSR_APRS_POSE) + +#define RTC_PSR_SPRS_POSS 0U +#define RTC_PSR_SPRS_POSE 14U +#define RTC_PSR_SPRS_MSK BITS(RTC_PSR_SPRS_POSS,RTC_PSR_SPRS_POSE) + +/****************** Bit definition for RTC_TAMPCON register ************************/ + +#define RTC_TAMPCON_TAMPFLT_POSS 20U +#define RTC_TAMPCON_TAMPFLT_POSE 21U +#define RTC_TAMPCON_TAMPFLT_MSK BITS(RTC_TAMPCON_TAMPFLT_POSS,RTC_TAMPCON_TAMPFLT_POSE) + +#define RTC_TAMPCON_TAMPCKS_POSS 17U +#define RTC_TAMPCON_TAMPCKS_POSE 19U +#define RTC_TAMPCON_TAMPCKS_MSK BITS(RTC_TAMPCON_TAMPCKS_POSS,RTC_TAMPCON_TAMPCKS_POSE) + +#define RTC_TAMPCON_TAMPTS_POS 16U +#define RTC_TAMPCON_TAMPTS_MSK BIT(RTC_TAMPCON_TAMPTS_POS) + +#define RTC_TAMPCON_TAMP2LV_POS 9U +#define RTC_TAMPCON_TAMP2LV_MSK BIT(RTC_TAMPCON_TAMP2LV_POS) + +#define RTC_TAMPCON_TAMP2EN_POS 8U +#define RTC_TAMPCON_TAMP2EN_MSK BIT(RTC_TAMPCON_TAMP2EN_POS) + +#define RTC_TAMPCON_TAMP1LV_POS 1U +#define RTC_TAMPCON_TAMP1LV_MSK BIT(RTC_TAMPCON_TAMP1LV_POS) + +#define RTC_TAMPCON_TAMP1EN_POS 0U +#define RTC_TAMPCON_TAMP1EN_MSK BIT(RTC_TAMPCON_TAMP1EN_POS) + +/****************** Bit definition for RTC_TIME register ************************/ + +#define RTC_TIME_PM_POS 22U +#define RTC_TIME_PM_MSK BIT(RTC_TIME_PM_POS) + +#define RTC_TIME_HRT_POSS 20U +#define RTC_TIME_HRT_POSE 21U +#define RTC_TIME_HRT_MSK BITS(RTC_TIME_HRT_POSS,RTC_TIME_HRT_POSE) + +#define RTC_TIME_HRU_POSS 16U +#define RTC_TIME_HRU_POSE 19U +#define RTC_TIME_HRU_MSK BITS(RTC_TIME_HRU_POSS,RTC_TIME_HRU_POSE) + +#define RTC_TIME_MINT_POSS 12U +#define RTC_TIME_MINT_POSE 14U +#define RTC_TIME_MINT_MSK BITS(RTC_TIME_MINT_POSS,RTC_TIME_MINT_POSE) + +#define RTC_TIME_MINU_POSS 8U +#define RTC_TIME_MINU_POSE 11U +#define RTC_TIME_MINU_MSK BITS(RTC_TIME_MINU_POSS,RTC_TIME_MINU_POSE) + +#define RTC_TIME_SECT_POSS 4U +#define RTC_TIME_SECT_POSE 6U +#define RTC_TIME_SECT_MSK BITS(RTC_TIME_SECT_POSS,RTC_TIME_SECT_POSE) + +#define RTC_TIME_SECU_POSS 0U +#define RTC_TIME_SECU_POSE 3U +#define RTC_TIME_SECU_MSK BITS(RTC_TIME_SECU_POSS,RTC_TIME_SECU_POSE) + +/****************** Bit definition for RTC_DATE register ************************/ + +#define RTC_DATE_WD_POSS 24U +#define RTC_DATE_WD_POSE 26U +#define RTC_DATE_WD_MSK BITS(RTC_DATE_WD_POSS,RTC_DATE_WD_POSE) + +#define RTC_DATE_YRT_POSS 20U +#define RTC_DATE_YRT_POSE 23U +#define RTC_DATE_YRT_MSK BITS(RTC_DATE_YRT_POSS,RTC_DATE_YRT_POSE) + +#define RTC_DATE_YRU_POSS 16U +#define RTC_DATE_YRU_POSE 19U +#define RTC_DATE_YRU_MSK BITS(RTC_DATE_YRU_POSS,RTC_DATE_YRU_POSE) + +#define RTC_DATE_MONT_POS 12U +#define RTC_DATE_MONT_MSK BIT(RTC_DATE_MONT_POS) + +#define RTC_DATE_MONU_POSS 8U +#define RTC_DATE_MONU_POSE 11U +#define RTC_DATE_MONU_MSK BITS(RTC_DATE_MONU_POSS,RTC_DATE_MONU_POSE) + +#define RTC_DATE_DAYT_POSS 4U +#define RTC_DATE_DAYT_POSE 5U +#define RTC_DATE_DAYT_MSK BITS(RTC_DATE_DAYT_POSS,RTC_DATE_DAYT_POSE) + +#define RTC_DATE_DAYU_POSS 0U +#define RTC_DATE_DAYU_POSE 3U +#define RTC_DATE_DAYU_MSK BITS(RTC_DATE_DAYU_POSS,RTC_DATE_DAYU_POSE) + +/****************** Bit definition for RTC_SSEC register ************************/ + +#define RTC_SSEC_VAL_POSS 0U +#define RTC_SSEC_VAL_POSE 15U +#define RTC_SSEC_VAL_MSK BITS(RTC_SSEC_VAL_POSS,RTC_SSEC_VAL_POSE) + +/****************** Bit definition for RTC_WUMAT register ************************/ + +#define RTC_WUMAT_VAL_POSS 0U +#define RTC_WUMAT_VAL_POSE 15U +#define RTC_WUMAT_VAL_MSK BITS(RTC_WUMAT_VAL_POSS,RTC_WUMAT_VAL_POSE) + +/****************** Bit definition for RTC_ALMA register ************************/ + +#define RTC_ALMA_WDS_POS 31U +#define RTC_ALMA_WDS_MSK BIT(RTC_ALMA_WDS_POS) + +#define RTC_ALMA_DAWD_POSS 24U +#define RTC_ALMA_DAWD_POSE 30U +#define RTC_ALMA_DAWD_MSK BITS(RTC_ALMA_DAWD_POSS,RTC_ALMA_DAWD_POSE) + +#define RTC_ALMA_DAYMSK_POS 30U +#define RTC_ALMA_DAYMSK_MSK BIT(RTC_ALMA_DAYMSK_POS) + +#define RTC_ALMA_DAWD_DAYT_POSS 28U +#define RTC_ALMA_DAWD_DAYT_POSE 29U +#define RTC_ALMA_DAWD_DAYT_MSK BITS(RTC_ALMA_DAWD_DAYT_POSS, RTC_ALMA_DAWD_DAYT_POSE) + +#define RTC_ALMA_DAWD_DAYU_POSS 24U +#define RTC_ALMA_DAWD_DAYU_POSE 27U +#define RTC_ALMA_DAWD_DAYU_MSK BITS(RTC_ALMA_DAWD_DAYU_POSS, RTC_ALMA_DAWD_DAYU_POSE) + +#define RTC_ALMA_HRMSK_POS 23U +#define RTC_ALMA_HRMSK_MSK BIT(RTC_ALMA_HRMSK_POS) + +#define RTC_ALMA_PM_POS 22U +#define RTC_ALMA_PM_MSK BIT(RTC_ALMA_PM_POS) + +#define RTC_ALMA_HRT_POSS 20U +#define RTC_ALMA_HRT_POSE 21U +#define RTC_ALMA_HRT_MSK BITS(RTC_ALMA_HRT_POSS,RTC_ALMA_HRT_POSE) + +#define RTC_ALMA_HRU_POSS 16U +#define RTC_ALMA_HRU_POSE 19U +#define RTC_ALMA_HRU_MSK BITS(RTC_ALMA_HRU_POSS,RTC_ALMA_HRU_POSE) + +#define RTC_ALMA_MINMSK_POS 15U +#define RTC_ALMA_MINMSK_MSK BIT(RTC_ALMA_MINMSK_POS) + +#define RTC_ALMA_MINT_POSS 12U +#define RTC_ALMA_MINT_POSE 14U +#define RTC_ALMA_MINT_MSK BITS(RTC_ALMA_MINT_POSS,RTC_ALMA_MINT_POSE) + +#define RTC_ALMA_MINU_POSS 8U +#define RTC_ALMA_MINU_POSE 11U +#define RTC_ALMA_MINU_MSK BITS(RTC_ALMA_MINU_POSS,RTC_ALMA_MINU_POSE) + +#define RTC_ALMA_SECMSK_POS 7U +#define RTC_ALMA_SECMSK_MSK BIT(RTC_ALMA_SECMSK_POS) + +#define RTC_ALMA_SECT_POSS 4U +#define RTC_ALMA_SECT_POSE 6U +#define RTC_ALMA_SECT_MSK BITS(RTC_ALMA_SECT_POSS,RTC_ALMA_SECT_POSE) + +#define RTC_ALMA_SECU_POSS 0U +#define RTC_ALMA_SECU_POSE 3U +#define RTC_ALMA_SECU_MSK BITS(RTC_ALMA_SECU_POSS,RTC_ALMA_SECU_POSE) + +/****************** Bit definition for RTC_ALMB register ************************/ + +#define RTC_ALMB_WDS_POS 31U +#define RTC_ALMB_WDS_MSK BIT(RTC_ALMB_WDS_POS) + +#define RTC_ALMB_DAWD_POSS 24U +#define RTC_ALMB_DAWD_POSE 30U +#define RTC_ALMB_DAWD_MSK BITS(RTC_ALMB_DAWD_POSS,RTC_ALMB_DAWD_POSE) + +#define RTC_ALMB_DAYMSK_POS 30U +#define RTC_ALMB_DAYMSK_MSK BIT(RTC_ALMB_DAYMSK_POS) + +#define RTC_ALMB_DAWD_DAYT_POSS 28U +#define RTC_ALMB_DAWD_DAYT_POSE 29U +#define RTC_ALMB_DAWD_DAYT_MSK BITS(RTC_ALMB_DAWD_DAYT_POSS, RTC_ALMB_DAWD_DAYT_POSE) + +#define RTC_ALMB_DAWD_DAYU_POSS 24U +#define RTC_ALMB_DAWD_DAYU_POSE 27U +#define RTC_ALMB_DAWD_DAYU_MSK BITS(RTC_ALMB_DAWD_DAYU_POSS, RTC_ALMB_DAWD_DAYU_POSE) + +#define RTC_ALMB_HRMSK_POS 23U +#define RTC_ALMB_HRMSK_MSK BIT(RTC_ALMB_HRMSK_POS) + +#define RTC_ALMB_PM_POS 22U +#define RTC_ALMB_PM_MSK BIT(RTC_ALMB_PM_POS) + +#define RTC_ALMB_HRT_POSS 20U +#define RTC_ALMB_HRT_POSE 21U +#define RTC_ALMB_HRT_MSK BITS(RTC_ALMB_HRT_POSS,RTC_ALMB_HRT_POSE) + +#define RTC_ALMB_HRU_POSS 16U +#define RTC_ALMB_HRU_POSE 19U +#define RTC_ALMB_HRU_MSK BITS(RTC_ALMB_HRU_POSS,RTC_ALMB_HRU_POSE) + +#define RTC_ALMB_MINMSK_POS 15U +#define RTC_ALMB_MINMSK_MSK BIT(RTC_ALMB_MINMSK_POS) + +#define RTC_ALMB_MINT_POSS 12U +#define RTC_ALMB_MINT_POSE 14U +#define RTC_ALMB_MINT_MSK BITS(RTC_ALMB_MINT_POSS,RTC_ALMB_MINT_POSE) + +#define RTC_ALMB_MINU_POSS 8U +#define RTC_ALMB_MINU_POSE 11U +#define RTC_ALMB_MINU_MSK BITS(RTC_ALMB_MINU_POSS,RTC_ALMB_MINU_POSE) + +#define RTC_ALMB_SECMSK_POS 7U +#define RTC_ALMB_SECMSK_MSK BIT(RTC_ALMB_SECMSK_POS) + +#define RTC_ALMB_SECT_POSS 4U +#define RTC_ALMB_SECT_POSE 6U +#define RTC_ALMB_SECT_MSK BITS(RTC_ALMB_SECT_POSS,RTC_ALMB_SECT_POSE) + +#define RTC_ALMB_SECU_POSS 0U +#define RTC_ALMB_SECU_POSE 3U +#define RTC_ALMB_SECU_MSK BITS(RTC_ALMB_SECU_POSS,RTC_ALMB_SECU_POSE) + +/****************** Bit definition for RTC_ALMASSEC register ************************/ + +#define RTC_ALMASSEC_SSECM_POSS 24U +#define RTC_ALMASSEC_SSECM_POSE 27U +#define RTC_ALMASSEC_SSECM_MSK BITS(RTC_ALMASSEC_SSECM_POSS,RTC_ALMASSEC_SSECM_POSE) + +#define RTC_ALMASSEC_SSEC_POSS 0U +#define RTC_ALMASSEC_SSEC_POSE 14U +#define RTC_ALMASSEC_SSEC_MSK BITS(RTC_ALMASSEC_SSEC_POSS,RTC_ALMASSEC_SSEC_POSE) + +/****************** Bit definition for RTC_ALMBSSEC register ************************/ + +#define RTC_ALMBSSEC_SSECM_POSS 24U +#define RTC_ALMBSSEC_SSECM_POSE 27U +#define RTC_ALMBSSEC_SSECM_MSK BITS(RTC_ALMBSSEC_SSECM_POSS,RTC_ALMBSSEC_SSECM_POSE) + +#define RTC_ALMBSSEC_SSEC_POSS 0U +#define RTC_ALMBSSEC_SSEC_POSE 14U +#define RTC_ALMBSSEC_SSEC_MSK BITS(RTC_ALMBSSEC_SSEC_POSS,RTC_ALMBSSEC_SSEC_POSE) + +/****************** Bit definition for RTC_TSTIME register ************************/ + +#define RTC_TSTIME_PM_POS 22U +#define RTC_TSTIME_PM_MSK BIT(RTC_TSTIME_PM_POS) + +#define RTC_TSTIME_HRT_POSS 20U +#define RTC_TSTIME_HRT_POSE 21U +#define RTC_TSTIME_HRT_MSK BITS(RTC_TSTIME_HRT_POSS,RTC_TSTIME_HRT_POSE) + +#define RTC_TSTIME_HRU_POSS 16U +#define RTC_TSTIME_HRU_POSE 19U +#define RTC_TSTIME_HRU_MSK BITS(RTC_TSTIME_HRU_POSS,RTC_TSTIME_HRU_POSE) + +#define RTC_TSTIME_MINT_POSS 12U +#define RTC_TSTIME_MINT_POSE 14U +#define RTC_TSTIME_MINT_MSK BITS(RTC_TSTIME_MINT_POSS,RTC_TSTIME_MINT_POSE) + +#define RTC_TSTIME_MINU_POSS 8U +#define RTC_TSTIME_MINU_POSE 11U +#define RTC_TSTIME_MINU_MSK BITS(RTC_TSTIME_MINU_POSS,RTC_TSTIME_MINU_POSE) + +#define RTC_TSTIME_SECT_POSS 4U +#define RTC_TSTIME_SECT_POSE 6U +#define RTC_TSTIME_SECT_MSK BITS(RTC_TSTIME_SECT_POSS,RTC_TSTIME_SECT_POSE) + +#define RTC_TSTIME_SECU_POSS 0U +#define RTC_TSTIME_SECU_POSE 3U +#define RTC_TSTIME_SECU_MSK BITS(RTC_TSTIME_SECU_POSS,RTC_TSTIME_SECU_POSE) + +/****************** Bit definition for RTC_TSDATE register ************************/ + +#define RTC_TSDATE_WD_POSS 24U +#define RTC_TSDATE_WD_POSE 26U +#define RTC_TSDATE_WD_MSK BITS(RTC_TSDATE_WD_POSS,RTC_TSDATE_WD_POSE) + +#define RTC_TSDATE_YRT_POSS 20U +#define RTC_TSDATE_YRT_POSE 23U +#define RTC_TSDATE_YRT_MSK BITS(RTC_TSDATE_YRT_POSS,RTC_TSDATE_YRT_POSE) + +#define RTC_TSDATE_YRU_POSS 16U +#define RTC_TSDATE_YRU_POSE 19U +#define RTC_TSDATE_YRU_MSK BITS(RTC_TSDATE_YRU_POSS,RTC_TSDATE_YRU_POSE) + +#define RTC_TSDATE_MONT_POS 12U +#define RTC_TSDATE_MONT_MSK BIT(RTC_TSDATE_MONT_POS) + +#define RTC_TSDATE_MONU_POSS 8U +#define RTC_TSDATE_MONU_POSE 11U +#define RTC_TSDATE_MONU_MSK BITS(RTC_TSDATE_MONU_POSS,RTC_TSDATE_MONU_POSE) + +#define RTC_TSDATE_DAYT_POSS 4U +#define RTC_TSDATE_DAYT_POSE 5U +#define RTC_TSDATE_DAYT_MSK BITS(RTC_TSDATE_DAYT_POSS,RTC_TSDATE_DAYT_POSE) + +#define RTC_TSDATE_DAYU_POSS 0U +#define RTC_TSDATE_DAYU_POSE 3U +#define RTC_TSDATE_DAYU_MSK BITS(RTC_TSDATE_DAYU_POSS,RTC_TSDATE_DAYU_POSE) + +/****************** Bit definition for RTC_TSSSEC register ************************/ + +#define RTC_TSSSEC_SSEC_POSS 0U +#define RTC_TSSSEC_SSEC_POSE 15U +#define RTC_TSSSEC_SSEC_MSK BITS(RTC_TSSSEC_SSEC_POSS,RTC_TSSSEC_SSEC_POSE) + +/****************** Bit definition for RTC_SSECTR register ************************/ + +#define RTC_SSECTR_INC_POS 31U +#define RTC_SSECTR_INC_MSK BIT(RTC_SSECTR_INC_POS) + +#define RTC_SSECTR_TRIM_POSS 0U +#define RTC_SSECTR_TRIM_POSE 14U +#define RTC_SSECTR_TRIM_MSK BITS(RTC_SSECTR_TRIM_POSS,RTC_SSECTR_TRIM_POSE) + +/****************** Bit definition for RTC_IER register ************************/ + +#define RTC_IER_TCE_POS 25U +#define RTC_IER_TCE_MSK BIT(RTC_IER_TCE_POS) + +#define RTC_IER_TCC_POS 24U +#define RTC_IER_TCC_MSK BIT(RTC_IER_TCC_POS) + +#define RTC_IER_WU_POS 18U +#define RTC_IER_WU_MSK BIT(RTC_IER_WU_POS) + +#define RTC_IER_SSTC_POS 17U +#define RTC_IER_SSTC_MSK BIT(RTC_IER_SSTC_POS) + +#define RTC_IER_RSC_POS 16U +#define RTC_IER_RSC_MSK BIT(RTC_IER_RSC_POS) + +#define RTC_IER_TAMP2_POS 13U +#define RTC_IER_TAMP2_MSK BIT(RTC_IER_TAMP2_POS) + +#define RTC_IER_TAMP1_POS 12U +#define RTC_IER_TAMP1_MSK BIT(RTC_IER_TAMP1_POS) + +#define RTC_IER_TSOV_POS 11U +#define RTC_IER_TSOV_MSK BIT(RTC_IER_TSOV_POS) + +#define RTC_IER_TS_POS 10U +#define RTC_IER_TS_MSK BIT(RTC_IER_TS_POS) + +#define RTC_IER_ALMB_POS 9U +#define RTC_IER_ALMB_MSK BIT(RTC_IER_ALMB_POS) + +#define RTC_IER_ALMA_POS 8U +#define RTC_IER_ALMA_MSK BIT(RTC_IER_ALMA_POS) + +#define RTC_IER_YR_POS 5U +#define RTC_IER_YR_MSK BIT(RTC_IER_YR_POS) + +#define RTC_IER_MON_POS 4U +#define RTC_IER_MON_MSK BIT(RTC_IER_MON_POS) + +#define RTC_IER_DAY_POS 3U +#define RTC_IER_DAY_MSK BIT(RTC_IER_DAY_POS) + +#define RTC_IER_HR_POS 2U +#define RTC_IER_HR_MSK BIT(RTC_IER_HR_POS) + +#define RTC_IER_MIN_POS 1U +#define RTC_IER_MIN_MSK BIT(RTC_IER_MIN_POS) + +#define RTC_IER_SEC_POS 0U +#define RTC_IER_SEC_MSK BIT(RTC_IER_SEC_POS) + +/****************** Bit definition for RTC_IFR register ************************/ + +#define RTC_IFR_TCEF_POS 25U +#define RTC_IFR_TCEF_MSK BIT(RTC_IFR_TCEF_POS) + +#define RTC_IFR_TCCF_POS 24U +#define RTC_IFR_TCCF_MSK BIT(RTC_IFR_TCCF_POS) + +#define RTC_IFR_WUF_POS 18U +#define RTC_IFR_WUF_MSK BIT(RTC_IFR_WUF_POS) + +#define RTC_IFR_SSTCF_POS 17U +#define RTC_IFR_SSTCF_MSK BIT(RTC_IFR_SSTCF_POS) + +#define RTC_IFR_RSCF_POS 16U +#define RTC_IFR_RSCF_MSK BIT(RTC_IFR_RSCF_POS) + +#define RTC_IFR_TAMP2F_POS 13U +#define RTC_IFR_TAMP2F_MSK BIT(RTC_IFR_TAMP2F_POS) + +#define RTC_IFR_TAMP1F_POS 12U +#define RTC_IFR_TAMP1F_MSK BIT(RTC_IFR_TAMP1F_POS) + +#define RTC_IFR_TSOVF_POS 11U +#define RTC_IFR_TSOVF_MSK BIT(RTC_IFR_TSOVF_POS) + +#define RTC_IFR_TSF_POS 10U +#define RTC_IFR_TSF_MSK BIT(RTC_IFR_TSF_POS) + +#define RTC_IFR_ALMBF_POS 9U +#define RTC_IFR_ALMBF_MSK BIT(RTC_IFR_ALMBF_POS) + +#define RTC_IFR_ALMAF_POS 8U +#define RTC_IFR_ALMAF_MSK BIT(RTC_IFR_ALMAF_POS) + +#define RTC_IFR_YRF_POS 5U +#define RTC_IFR_YRF_MSK BIT(RTC_IFR_YRF_POS) + +#define RTC_IFR_MONF_POS 4U +#define RTC_IFR_MONF_MSK BIT(RTC_IFR_MONF_POS) + +#define RTC_IFR_DAYF_POS 3U +#define RTC_IFR_DAYF_MSK BIT(RTC_IFR_DAYF_POS) + +#define RTC_IFR_HRF_POS 2U +#define RTC_IFR_HRF_MSK BIT(RTC_IFR_HRF_POS) + +#define RTC_IFR_MINF_POS 1U +#define RTC_IFR_MINF_MSK BIT(RTC_IFR_MINF_POS) + +#define RTC_IFR_SECF_POS 0U +#define RTC_IFR_SECF_MSK BIT(RTC_IFR_SECF_POS) + +/****************** Bit definition for RTC_IFCR register ************************/ + +#define RTC_IFCR_TCEFC_POS 25U +#define RTC_IFCR_TCEFC_MSK BIT(RTC_IFCR_TCEFC_POS) + +#define RTC_IFCR_TCCFC_POS 24U +#define RTC_IFCR_TCCFC_MSK BIT(RTC_IFCR_TCCFC_POS) + +#define RTC_IFCR_WUFC_POS 18U +#define RTC_IFCR_WUFC_MSK BIT(RTC_IFCR_WUFC_POS) + +#define RTC_IFCR_SSTCFC_POS 17U +#define RTC_IFCR_SSTCFC_MSK BIT(RTC_IFCR_SSTCFC_POS) + +#define RTC_IFCR_RSCFC_POS 16U +#define RTC_IFCR_RSCFC_MSK BIT(RTC_IFCR_RSCFC_POS) + +#define RTC_IFCR_TAMP2FC_POS 13U +#define RTC_IFCR_TAMP2FC_MSK BIT(RTC_IFCR_TAMP2FC_POS) + +#define RTC_IFCR_TAMP1FC_POS 12U +#define RTC_IFCR_TAMP1FC_MSK BIT(RTC_IFCR_TAMP1FC_POS) + +#define RTC_IFCR_TSOVFC_POS 11U +#define RTC_IFCR_TSOVFC_MSK BIT(RTC_IFCR_TSOVFC_POS) + +#define RTC_IFCR_TSSTC_POS 10U +#define RTC_IFCR_TSSTC_MSK BIT(RTC_IFCR_TSSTC_POS) + +#define RTC_IFCR_ALMBFC_POS 9U +#define RTC_IFCR_ALMBFC_MSK BIT(RTC_IFCR_ALMBFC_POS) + +#define RTC_IFCR_ALMAFC_POS 8U +#define RTC_IFCR_ALMAFC_MSK BIT(RTC_IFCR_ALMAFC_POS) + +#define RTC_IFCR_YRFC_POS 5U +#define RTC_IFCR_YRFC_MSK BIT(RTC_IFCR_YRFC_POS) + +#define RTC_IFCR_MONFC_POS 4U +#define RTC_IFCR_MONFC_MSK BIT(RTC_IFCR_MONFC_POS) + +#define RTC_IFCR_DAYFC_POS 3U +#define RTC_IFCR_DAYFC_MSK BIT(RTC_IFCR_DAYFC_POS) + +#define RTC_IFCR_HRFC_POS 2U +#define RTC_IFCR_HRFC_MSK BIT(RTC_IFCR_HRFC_POS) + +#define RTC_IFCR_MINFC_POS 1U +#define RTC_IFCR_MINFC_MSK BIT(RTC_IFCR_MINFC_POS) + +#define RTC_IFCR_SECFC_POS 0U +#define RTC_IFCR_SECFC_MSK BIT(RTC_IFCR_SECFC_POS) + +/****************** Bit definition for RTC_ISR register ************************/ + +#define RTC_ISR_TCEF_POS 25U +#define RTC_ISR_TCEF_MSK BIT(RTC_ISR_TCEF_POS) + +#define RTC_ISR_TCCF_POS 24U +#define RTC_ISR_TCCF_MSK BIT(RTC_ISR_TCCF_POS) + +#define RTC_ISR_WUF_POS 18U +#define RTC_ISR_WUF_MSK BIT(RTC_ISR_WUF_POS) + +#define RTC_ISR_SSTCF_POS 17U +#define RTC_ISR_SSTCF_MSK BIT(RTC_ISR_SSTCF_POS) + +#define RTC_ISR_RSCF_POS 16U +#define RTC_ISR_RSCF_MSK BIT(RTC_ISR_RSCF_POS) + +#define RTC_ISR_TAMP2F_POS 13U +#define RTC_ISR_TAMP2F_MSK BIT(RTC_ISR_TAMP2F_POS) + +#define RTC_ISR_TAMP1F_POS 12U +#define RTC_ISR_TAMP1F_MSK BIT(RTC_ISR_TAMP1F_POS) + +#define RTC_ISR_TSOVF_POS 11U +#define RTC_ISR_TSOVF_MSK BIT(RTC_ISR_TSOVF_POS) + +#define RTC_ISR_TSF_POS 10U +#define RTC_ISR_TSF_MSK BIT(RTC_ISR_TSF_POS) + +#define RTC_ISR_ALMBF_POS 9U +#define RTC_ISR_ALMBF_MSK BIT(RTC_ISR_ALMBF_POS) + +#define RTC_ISR_ALMAF_POS 8U +#define RTC_ISR_ALMAF_MSK BIT(RTC_ISR_ALMAF_POS) + +#define RTC_ISR_YRF_POS 5U +#define RTC_ISR_YRF_MSK BIT(RTC_ISR_YRF_POS) + +#define RTC_ISR_MONF_POS 4U +#define RTC_ISR_MONF_MSK BIT(RTC_ISR_MONF_POS) + +#define RTC_ISR_DAYF_POS 3U +#define RTC_ISR_DAYF_MSK BIT(RTC_ISR_DAYF_POS) + +#define RTC_ISR_HRF_POS 2U +#define RTC_ISR_HRF_MSK BIT(RTC_ISR_HRF_POS) + +#define RTC_ISR_MINF_POS 1U +#define RTC_ISR_MINF_MSK BIT(RTC_ISR_MINF_POS) + +#define RTC_ISR_SECF_POS 0U +#define RTC_ISR_SECF_MSK BIT(RTC_ISR_SECF_POS) + +/****************** Bit definition for RTC_CALWPR register ************************/ + +#define RTC_CALWPR_WP_POS 0U +#define RTC_CALWPR_WP_MSK BIT(RTC_CALWPR_WP_POS) + +/****************** Bit definition for RTC_CALCON register ************************/ + +#define RTC_CALCON_DCMACC_POS 24U +#define RTC_CALCON_DCMACC_MSK BIT(RTC_CALCON_DCMACC_POS) + +#define RTC_CALCON_ALG_POS 23U +#define RTC_CALCON_ALG_MSK BIT(RTC_CALCON_ALG_POS) + +#define RTC_CALCON_TCP_POSS 20U +#define RTC_CALCON_TCP_POSE 22U +#define RTC_CALCON_TCP_MSK BITS(RTC_CALCON_TCP_POSS,RTC_CALCON_TCP_POSE) + +#define RTC_CALCON_ERR_POS 19U +#define RTC_CALCON_ERR_MSK BIT(RTC_CALCON_ERR_POS) + +#define RTC_CALCON_BUSY_POS 18U +#define RTC_CALCON_BUSY_MSK BIT(RTC_CALCON_BUSY_POS) + +#define RTC_CALCON_TCM_POSS 16U +#define RTC_CALCON_TCM_POSE 17U +#define RTC_CALCON_TCM_MSK BITS(RTC_CALCON_TCM_POSS,RTC_CALCON_TCM_POSE) + +#define RTC_CALCON_CALP_POSS 1U +#define RTC_CALCON_CALP_POSE 3U +#define RTC_CALCON_CALP_MSK BITS(RTC_CALCON_CALP_POSS,RTC_CALCON_CALP_POSE) + +#define RTC_CALCON_CALEN_POS 0U +#define RTC_CALCON_CALEN_MSK BIT(RTC_CALCON_CALEN_POS) + +/****************** Bit definition for RTC_CALDR register ************************/ + +#define RTC_CALDR_DATA_POSS 16U +#define RTC_CALDR_DATA_POSE 31U +#define RTC_CALDR_DATA_MSK BITS(RTC_CALDR_DATA_POSS,RTC_CALDR_DATA_POSE) + +#define RTC_CALDR_VAL_POSS 0U +#define RTC_CALDR_VAL_POSE 15U +#define RTC_CALDR_VAL_MSK BITS(RTC_CALDR_VAL_POSS,RTC_CALDR_VAL_POSE) + +/****************** Bit definition for RTC_TEMPR register ************************/ + +#define RTC_TEMPR_DATA_POSS 16U +#define RTC_TEMPR_DATA_POSE 31U +#define RTC_TEMPR_DATA_MSK BITS(RTC_TEMPR_DATA_POSS,RTC_TEMPR_DATA_POSE) + +#define RTC_TEMPR_VAL_POSS 0U +#define RTC_TEMPR_VAL_POSE 15U +#define RTC_TEMPR_VAL_MSK BITS(RTC_TEMPR_VAL_POSS,RTC_TEMPR_VAL_POSE) + +/****************** Bit definition for RTC_TEMPBDR register ************************/ + +#define RTC_TEMPBDR_VAL_POSS 0U +#define RTC_TEMPBDR_VAL_POSE 15U +#define RTC_TEMPBDR_VAL_MSK BITS(RTC_TEMPBDR_VAL_POSS,RTC_TEMPBDR_VAL_POSE) + +/****************** Bit definition for RTC_BKP register ************************/ + +#define RTC_BKP_BKP_POSS 0U +#define RTC_BKP_BKP_POSE 31U +#define RTC_BKP_BKP_MSK BITS(RTC_BKP_BKP_POSS,RTC_BKP_BKP_POSE) + +typedef struct +{ + __IO uint32_t WPR; + __IO uint32_t CON; + __IO uint32_t PSR; + __IO uint32_t TAMPCON; + __IO uint32_t TIME; + __IO uint32_t DATE; + __IO uint32_t SSEC; + __IO uint32_t WUMAT; + __IO uint32_t ALMA; + __IO uint32_t ALMB; + __IO uint32_t ALMASSEC; + __IO uint32_t ALMBSSEC; + __I uint32_t TSTIME; + __I uint32_t TSDATE; + __I uint32_t TSSSEC; + __O uint32_t SSECTR; + __IO uint32_t IER; + __I uint32_t IFR; + __O uint32_t IFCR; + __I uint32_t ISR; + __IO uint32_t CALWPR; + __IO uint32_t CALCON; + __IO uint32_t CALDR; + __IO uint32_t TEMPR; + __IO uint32_t LTCAR; + __IO uint32_t LTCBR; + __IO uint32_t LTCCR; + __IO uint32_t LTCDR; + __IO uint32_t LTCER; + __IO uint32_t HTCAR; + __IO uint32_t HTCBR; + __IO uint32_t HTCCR; + __IO uint32_t HTCDR; + __IO uint32_t HTCER; + __IO uint32_t TEMPBDR; + uint32_t RESERVED0[29] ; + __IO uint32_t BKPR[32]; +} RTC_TypeDef; + +/****************** Bit definition for TIMER_CON1 register ************************/ + +#define TIMER_CON1_DFCKSEL_POSS 8U +#define TIMER_CON1_DFCKSEL_POSE 9U +#define TIMER_CON1_DFCKSEL_MSK BITS(TIMER_CON1_DFCKSEL_POSS,TIMER_CON1_DFCKSEL_POSE) + +#define TIMER_CON1_ARPEN_POS 7U +#define TIMER_CON1_ARPEN_MSK BIT(TIMER_CON1_ARPEN_POS) + +#define TIMER_CON1_CMSEL_POSS 5U +#define TIMER_CON1_CMSEL_POSE 6U +#define TIMER_CON1_CMSEL_MSK BITS(TIMER_CON1_CMSEL_POSS,TIMER_CON1_CMSEL_POSE) + +#define TIMER_CON1_DIRSEL_POS 4U +#define TIMER_CON1_DIRSEL_MSK BIT(TIMER_CON1_DIRSEL_POS) + +#define TIMER_CON1_SPMEN_POS 3U +#define TIMER_CON1_SPMEN_MSK BIT(TIMER_CON1_SPMEN_POS) + +#define TIMER_CON1_UERSEL_POS 2U +#define TIMER_CON1_UERSEL_MSK BIT(TIMER_CON1_UERSEL_POS) + +#define TIMER_CON1_DISUE_POS 1U +#define TIMER_CON1_DISUE_MSK BIT(TIMER_CON1_DISUE_POS) + +#define TIMER_CON1_CNTEN_POS 0U +#define TIMER_CON1_CNTEN_MSK BIT(TIMER_CON1_CNTEN_POS) + +/****************** Bit definition for TIMER_CON2 register ************************/ + +#define TIMER_CON2_OISS4_POS 14U +#define TIMER_CON2_OISS4_MSK BIT(TIMER_CON2_OISS4_POS) + +#define TIMER_CON2_OISS3N_POS 13U +#define TIMER_CON2_OISS3N_MSK BIT(TIMER_CON2_OISS3N_POS) + +#define TIMER_CON2_OISS3_POS 12U +#define TIMER_CON2_OISS3_MSK BIT(TIMER_CON2_OISS3_POS) + +#define TIMER_CON2_OISS2N_POS 11U +#define TIMER_CON2_OISS2N_MSK BIT(TIMER_CON2_OISS2N_POS) + +#define TIMER_CON2_OISS2_POS 10U +#define TIMER_CON2_OISS2_MSK BIT(TIMER_CON2_OISS2_POS) + +#define TIMER_CON2_OISS1N_POS 9U +#define TIMER_CON2_OISS1N_MSK BIT(TIMER_CON2_OISS1N_POS) + +#define TIMER_CON2_OISS1_POS 8U +#define TIMER_CON2_OISS1_MSK BIT(TIMER_CON2_OISS1_POS) + +#define TIMER_CON2_I1FSEL_POS 7U +#define TIMER_CON2_I1FSEL_MSK BIT(TIMER_CON2_I1FSEL_POS) + +#define TIMER_CON2_TRGOSEL_POSS 4U +#define TIMER_CON2_TRGOSEL_POSE 6U +#define TIMER_CON2_TRGOSEL_MSK BITS(TIMER_CON2_TRGOSEL_POSS,TIMER_CON2_TRGOSEL_POSE) + +#define TIMER_CON2_CCDMASEL_POS 3U +#define TIMER_CON2_CCDMASEL_MSK BIT(TIMER_CON2_CCDMASEL_POS) + +#define TIMER_CON2_CCUSEL_POS 2U +#define TIMER_CON2_CCUSEL_MSK BIT(TIMER_CON2_CCUSEL_POS) + +#define TIMER_CON2_CCPCEN_POS 0U +#define TIMER_CON2_CCPCEN_MSK BIT(TIMER_CON2_CCPCEN_POS) + +/****************** Bit definition for TIMER_SMCON register ************************/ + +#define TIMER_SMCON_ETPOL_POS 15U +#define TIMER_SMCON_ETPOL_MSK BIT(TIMER_SMCON_ETPOL_POS) + +#define TIMER_SMCON_ECM2EN_POS 14U +#define TIMER_SMCON_ECM2EN_MSK BIT(TIMER_SMCON_ECM2EN_POS) + +#define TIMER_SMCON_ETPSEL_POSS 12U +#define TIMER_SMCON_ETPSEL_POSE 13U +#define TIMER_SMCON_ETPSEL_MSK BITS(TIMER_SMCON_ETPSEL_POSS,TIMER_SMCON_ETPSEL_POSE) + +#define TIMER_SMCON_ETFLT_POSS 8U +#define TIMER_SMCON_ETFLT_POSE 11U +#define TIMER_SMCON_ETFLT_MSK BITS(TIMER_SMCON_ETFLT_POSS,TIMER_SMCON_ETFLT_POSE) + +#define TIMER_SMCON_MSCFG_POS 7U +#define TIMER_SMCON_MSCFG_MSK BIT(TIMER_SMCON_MSCFG_POS) + +#define TIMER_SMCON_TSSEL_POSS 4U +#define TIMER_SMCON_TSSEL_POSE 6U +#define TIMER_SMCON_TSSEL_MSK BITS(TIMER_SMCON_TSSEL_POSS,TIMER_SMCON_TSSEL_POSE) + +#define TIMER_SMCON_SMODS_POSS 0U +#define TIMER_SMCON_SMODS_POSE 2U +#define TIMER_SMCON_SMODS_MSK BITS(TIMER_SMCON_SMODS_POSS,TIMER_SMCON_SMODS_POSE) + +/****************** Bit definition for TIMER_DIER register ************************/ + +#define TIMER_DIER_TRGDMA_POS 14U +#define TIMER_DIER_TRGDMA_MSK BIT(TIMER_DIER_TRGDMA_POS) + +#define TIMER_DIER_COMDMA_POS 13U +#define TIMER_DIER_COMDMA_MSK BIT(TIMER_DIER_COMDMA_POS) + +#define TIMER_DIER_CC4DMA_POS 12U +#define TIMER_DIER_CC4DMA_MSK BIT(TIMER_DIER_CC4DMA_POS) + +#define TIMER_DIER_CC3DMA_POS 11U +#define TIMER_DIER_CC3DMA_MSK BIT(TIMER_DIER_CC3DMA_POS) + +#define TIMER_DIER_CC2DMA_POS 10U +#define TIMER_DIER_CC2DMA_MSK BIT(TIMER_DIER_CC2DMA_POS) + +#define TIMER_DIER_CC1DMA_POS 9U +#define TIMER_DIER_CC1DMA_MSK BIT(TIMER_DIER_CC1DMA_POS) + +#define TIMER_DIER_UDMA_POS 8U +#define TIMER_DIER_UDMA_MSK BIT(TIMER_DIER_UDMA_POS) + +#define TIMER_DIER_BRKIT_POS 7U +#define TIMER_DIER_BRKIT_MSK BIT(TIMER_DIER_BRKIT_POS) + +#define TIMER_DIER_TRGIT_POS 6U +#define TIMER_DIER_TRGIT_MSK BIT(TIMER_DIER_TRGIT_POS) + +#define TIMER_DIER_COMIT_POS 5U +#define TIMER_DIER_COMIT_MSK BIT(TIMER_DIER_COMIT_POS) + +#define TIMER_DIER_CC4IT_POS 4U +#define TIMER_DIER_CC4IT_MSK BIT(TIMER_DIER_CC4IT_POS) + +#define TIMER_DIER_CC3IT_POS 3U +#define TIMER_DIER_CC3IT_MSK BIT(TIMER_DIER_CC3IT_POS) + +#define TIMER_DIER_CC2IT_POS 2U +#define TIMER_DIER_CC2IT_MSK BIT(TIMER_DIER_CC2IT_POS) + +#define TIMER_DIER_CC1IT_POS 1U +#define TIMER_DIER_CC1IT_MSK BIT(TIMER_DIER_CC1IT_POS) + +#define TIMER_DIER_UIT_POS 0U +#define TIMER_DIER_UIT_MSK BIT(TIMER_DIER_UIT_POS) + +/****************** Bit definition for TIMER_DIDR register ************************/ + +#define TIMER_DIDR_TRGDMA_POS 14U +#define TIMER_DIDR_TRGDMA_MSK BIT(TIMER_DIDR_TRGDMA_POS) + +#define TIMER_DIDR_COMD_POS 13U +#define TIMER_DIDR_COMD_MSK BIT(TIMER_DIDR_COMD_POS) + +#define TIMER_DIDR_CC4D_POS 12U +#define TIMER_DIDR_CC4D_MSK BIT(TIMER_DIDR_CC4D_POS) + +#define TIMER_DIDR_CC3D_POS 11U +#define TIMER_DIDR_CC3D_MSK BIT(TIMER_DIDR_CC3D_POS) + +#define TIMER_DIDR_CC2D_POS 10U +#define TIMER_DIDR_CC2D_MSK BIT(TIMER_DIDR_CC2D_POS) + +#define TIMER_DIDR_CC1D_POS 9U +#define TIMER_DIDR_CC1D_MSK BIT(TIMER_DIDR_CC1D_POS) + +#define TIMER_DIDR_UD_POS 8U +#define TIMER_DIDR_UD_MSK BIT(TIMER_DIDR_UD_POS) + +#define TIMER_DIDR_BRKI_POS 7U +#define TIMER_DIDR_BRKI_MSK BIT(TIMER_DIDR_BRKI_POS) + +#define TIMER_DIDR_TRGI_POS 6U +#define TIMER_DIDR_TRGI_MSK BIT(TIMER_DIDR_TRGI_POS) + +#define TIMER_DIDR_COMI_POS 5U +#define TIMER_DIDR_COMI_MSK BIT(TIMER_DIDR_COMI_POS) + +#define TIMER_DIDR_CC4I_POS 4U +#define TIMER_DIDR_CC4I_MSK BIT(TIMER_DIDR_CC4I_POS) + +#define TIMER_DIDR_CC3I_POS 3U +#define TIMER_DIDR_CC3I_MSK BIT(TIMER_DIDR_CC3I_POS) + +#define TIMER_DIDR_CC2I_POS 2U +#define TIMER_DIDR_CC2I_MSK BIT(TIMER_DIDR_CC2I_POS) + +#define TIMER_DIDR_CC1I_POS 1U +#define TIMER_DIDR_CC1I_MSK BIT(TIMER_DIDR_CC1I_POS) + +#define TIMER_DIDR_UI_POS 0U +#define TIMER_DIDR_UI_MSK BIT(TIMER_DIDR_UI_POS) + +/****************** Bit definition for TIMER_DIVS register ************************/ + +#define TIMER_DIVS_TRGDMA_POS 14U +#define TIMER_DIVS_TRGDMA_MSK BIT(TIMER_DIVS_TRGDMA_POS) + +#define TIMER_DIVS_COMDMA_POS 13U +#define TIMER_DIVS_COMDMA_MSK BIT(TIMER_DIVS_COMDMA_POS) + +#define TIMER_DIVS_CC4DMA_POS 12U +#define TIMER_DIVS_CC4DMA_MSK BIT(TIMER_DIVS_CC4DMA_POS) + +#define TIMER_DIVS_CC3DMA_POS 11U +#define TIMER_DIVS_CC3DMA_MSK BIT(TIMER_DIVS_CC3DMA_POS) + +#define TIMER_DIVS_CC2DMA_POS 10U +#define TIMER_DIVS_CC2DMA_MSK BIT(TIMER_DIVS_CC2DMA_POS) + +#define TIMER_DIVS_CC1DMA_POS 9U +#define TIMER_DIVS_CC1DMA_MSK BIT(TIMER_DIVS_CC1DMA_POS) + +#define TIMER_DIVS_UEDTR_POS 8U +#define TIMER_DIVS_UEDTR_MSK BIT(TIMER_DIVS_UEDTR_POS) + +#define TIMER_DIVS_BKI_POS 7U +#define TIMER_DIVS_BKI_MSK BIT(TIMER_DIVS_BKI_POS) + +#define TIMER_DIVS_TRGI_POS 6U +#define TIMER_DIVS_TRGI_MSK BIT(TIMER_DIVS_TRGI_POS) + +#define TIMER_DIVS_COMI_POS 5U +#define TIMER_DIVS_COMI_MSK BIT(TIMER_DIVS_COMI_POS) + +#define TIMER_DIVS_CC4I_POS 4U +#define TIMER_DIVS_CC4I_MSK BIT(TIMER_DIVS_CC4I_POS) + +#define TIMER_DIVS_CC3I_POS 3U +#define TIMER_DIVS_CC3I_MSK BIT(TIMER_DIVS_CC3I_POS) + +#define TIMER_DIVS_CC2I_POS 2U +#define TIMER_DIVS_CC2I_MSK BIT(TIMER_DIVS_CC2I_POS) + +#define TIMER_DIVS_CC1I_POS 1U +#define TIMER_DIVS_CC1I_MSK BIT(TIMER_DIVS_CC1I_POS) + +#define TIMER_DIVS_UEI_POS 0U +#define TIMER_DIVS_UEI_MSK BIT(TIMER_DIVS_UEI_POS) + +/****************** Bit definition for TIMER_RIF register ************************/ + +#define TIMER_RIF_CH4OVIF_POS 12U +#define TIMER_RIF_CH4OVIF_MSK BIT(TIMER_RIF_CH4OVIF_POS) + +#define TIMER_RIF_CH3OVIF_POS 11U +#define TIMER_RIF_CH3OVIF_MSK BIT(TIMER_RIF_CH3OVIF_POS) + +#define TIMER_RIF_CH2OVIF_POS 10U +#define TIMER_RIF_CH2OVIF_MSK BIT(TIMER_RIF_CH2OVIF_POS) + +#define TIMER_RIF_CH1OVIF_POS 9U +#define TIMER_RIF_CH1OVIF_MSK BIT(TIMER_RIF_CH1OVIF_POS) + +#define TIMER_RIF_BRKIF_POS 7U +#define TIMER_RIF_BRKIF_MSK BIT(TIMER_RIF_BRKIF_POS) + +#define TIMER_RIF_TRGIF_POS 6U +#define TIMER_RIF_TRGIF_MSK BIT(TIMER_RIF_TRGIF_POS) + +#define TIMER_RIF_COMIF_POS 5U +#define TIMER_RIF_COMIF_MSK BIT(TIMER_RIF_COMIF_POS) + +#define TIMER_RIF_CH4IF_POS 4U +#define TIMER_RIF_CH4IF_MSK BIT(TIMER_RIF_CH4IF_POS) + +#define TIMER_RIF_CH3IF_POS 3U +#define TIMER_RIF_CH3IF_MSK BIT(TIMER_RIF_CH3IF_POS) + +#define TIMER_RIF_CH2IF_POS 2U +#define TIMER_RIF_CH2IF_MSK BIT(TIMER_RIF_CH2IF_POS) + +#define TIMER_RIF_CH1IF_POS 1U +#define TIMER_RIF_CH1IF_MSK BIT(TIMER_RIF_CH1IF_POS) + +#define TIMER_RIF_UEVTIF_POS 0U +#define TIMER_RIF_UEVTIF_MSK BIT(TIMER_RIF_UEVTIF_POS) + +/****************** Bit definition for TIMER_IFM register ************************/ + +#define TIMER_IFM_BRKIM_POS 7U +#define TIMER_IFM_BRKIM_MSK BIT(TIMER_IFM_BRKIM_POS) + +#define TIMER_IFM_TRGI_POS 6U +#define TIMER_IFM_TRGI_MSK BIT(TIMER_IFM_TRGI_POS) + +#define TIMER_IFM_COMI_POS 5U +#define TIMER_IFM_COMI_MSK BIT(TIMER_IFM_COMI_POS) + +#define TIMER_IFM_CH4CCI_POS 4U +#define TIMER_IFM_CH4CCI_MSK BIT(TIMER_IFM_CH4CCI_POS) + +#define TIMER_IFM_CH3CCI_POS 3U +#define TIMER_IFM_CH3CCI_MSK BIT(TIMER_IFM_CH3CCI_POS) + +#define TIMER_IFM_CH2CCI_POS 2U +#define TIMER_IFM_CH2CCI_MSK BIT(TIMER_IFM_CH2CCI_POS) + +#define TIMER_IFM_CH1CCI_POS 1U +#define TIMER_IFM_CH1CCI_MSK BIT(TIMER_IFM_CH1CCI_POS) + +#define TIMER_IFM_UEI_POS 0U +#define TIMER_IFM_UEI_MSK BIT(TIMER_IFM_UEI_POS) + +/****************** Bit definition for TIMER_ICR register ************************/ + +#define TIMER_ICR_BRKIC_POS 7U +#define TIMER_ICR_BRKIC_MSK BIT(TIMER_ICR_BRKIC_POS) + +#define TIMER_ICR_TRGIC_POS 6U +#define TIMER_ICR_TRGIC_MSK BIT(TIMER_ICR_TRGIC_POS) + +#define TIMER_ICR_COMIC_POS 5U +#define TIMER_ICR_COMIC_MSK BIT(TIMER_ICR_COMIC_POS) + +#define TIMER_ICR_CH4CCIC_POS 4U +#define TIMER_ICR_CH4CCIC_MSK BIT(TIMER_ICR_CH4CCIC_POS) + +#define TIMER_ICR_CH3CCIC_POS 3U +#define TIMER_ICR_CH3CCIC_MSK BIT(TIMER_ICR_CH3CCIC_POS) + +#define TIMER_ICR_CH2CCIC_POS 2U +#define TIMER_ICR_CH2CCIC_MSK BIT(TIMER_ICR_CH2CCIC_POS) + +#define TIMER_ICR_CH1CCIC_POS 1U +#define TIMER_ICR_CH1CCIC_MSK BIT(TIMER_ICR_CH1CCIC_POS) + +#define TIMER_ICR_UEIC_POS 0U +#define TIMER_ICR_UEIC_MSK BIT(TIMER_ICR_UEIC_POS) + +/****************** Bit definition for TIMER_SGE register ************************/ + +#define TIMER_SGE_SGBRK_POS 7U +#define TIMER_SGE_SGBRK_MSK BIT(TIMER_SGE_SGBRK_POS) + +#define TIMER_SGE_SGTRG_POS 6U +#define TIMER_SGE_SGTRG_MSK BIT(TIMER_SGE_SGTRG_POS) + +#define TIMER_SGE_SGCOM_POS 5U +#define TIMER_SGE_SGCOM_MSK BIT(TIMER_SGE_SGCOM_POS) + +#define TIMER_SGE_SGCC4E_POS 4U +#define TIMER_SGE_SGCC4E_MSK BIT(TIMER_SGE_SGCC4E_POS) + +#define TIMER_SGE_SGCC3E_POS 3U +#define TIMER_SGE_SGCC3E_MSK BIT(TIMER_SGE_SGCC3E_POS) + +#define TIMER_SGE_SGCC2E_POS 2U +#define TIMER_SGE_SGCC2E_MSK BIT(TIMER_SGE_SGCC2E_POS) + +#define TIMER_SGE_SGCC1E_POS 1U +#define TIMER_SGE_SGCC1E_MSK BIT(TIMER_SGE_SGCC1E_POS) + +#define TIMER_SGE_SGU_POS 0U +#define TIMER_SGE_SGU_MSK BIT(TIMER_SGE_SGU_POS) + +/****************** Bit definition for TIMER_CHMR1 register ************************/ +/* Output */ +#define TIMER_CHMR1_CH2OCLREN_POS 15U +#define TIMER_CHMR1_CH2OCLREN_MSK BIT(TIMER_CHMR1_CH2OCLREN_POS) + +#define TIMER_CHMR1_CH2OMOD_POSS 12U +#define TIMER_CHMR1_CH2OMOD_POSE 14U +#define TIMER_CHMR1_CH2OMOD_MSK BITS(TIMER_CHMR1_CH2OMOD_POSS,TIMER_CHMR1_CH2OMOD_POSE) + +#define TIMER_CHMR1_CH2OPEN_POS 11U +#define TIMER_CHMR1_CH2OPEN_MSK BIT(TIMER_CHMR1_CH2OPEN_POS) + +#define TIMER_CHMR1_CH2OFEN_POS 10U +#define TIMER_CHMR1_CH2OFEN_MSK BIT(TIMER_CHMR1_CH2OFEN_POS) + +#define TIMER_CHMR1_CC2SSEL_POSS 8U +#define TIMER_CHMR1_CC2SSEL_POSE 9U +#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) + +#define TIMER_CHMR1_CH1OCLREN_POS 7U +#define TIMER_CHMR1_CH1OCLREN_MSK BIT(TIMER_CHMR1_CH1OCLREN_POS) + +#define TIMER_CHMR1_CH1OMOD_POSS 4U +#define TIMER_CHMR1_CH1OMOD_POSE 6U +#define TIMER_CHMR1_CH1OMOD_MSK BITS(TIMER_CHMR1_CH1OMOD_POSS,TIMER_CHMR1_CH1OMOD_POSE) + +#define TIMER_CHMR1_CH1OPREN_POS 3U +#define TIMER_CHMR1_CH1OPREN_MSK BIT(TIMER_CHMR1_CH1OPREN_POS) + +#define TIMER_CHMR1_CH1OHSEN_POS 2U +#define TIMER_CHMR1_CH1OHSEN_MSK BIT(TIMER_CHMR1_CH1OHSEN_POS) + +#define TIMER_CHMR1_CC1SSEL_POSS 0U +#define TIMER_CHMR1_CC1SSEL_POSE 1U +#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) + +/* Input */ +#define TIMER_CHMR1_I2FLT_POSS 12U +#define TIMER_CHMR1_I2FLT_POSE 15U +#define TIMER_CHMR1_I2FLT_MSK BITS(TIMER_CHMR1_I2FLT_POSS,TIMER_CHMR1_I2FLT_POSE) + +#define TIMER_CHMR1_IC2PRES_POSS 10U +#define TIMER_CHMR1_IC2PRES_POSE 11U +#define TIMER_CHMR1_IC2PRES_MSK BITS(TIMER_CHMR1_IC2PRES_POSS,TIMER_CHMR1_IC2PRES_POSE) + +#define TIMER_CHMR1_CC2SSEL_POSS 8U +#define TIMER_CHMR1_CC2SSEL_POSE 9U +#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) + +#define TIMER_CHMR1_I1FLT_POSS 4U +#define TIMER_CHMR1_I1FLT_POSE 7U +#define TIMER_CHMR1_I1FLT_MSK BITS(TIMER_CHMR1_I1FLT_POSS,TIMER_CHMR1_I1FLT_POSE) + +#define TIMER_CHMR1_IC1PRES_POSS 2U +#define TIMER_CHMR1_IC1PRES_POSE 3U +#define TIMER_CHMR1_IC1PRES_MSK BITS(TIMER_CHMR1_IC1PRES_POSS,TIMER_CHMR1_IC1PRES_POSE) + +#define TIMER_CHMR1_CC1SSEL_POSS 0U +#define TIMER_CHMR1_CC1SSEL_POSE 1U +#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) + +/****************** Bit definition for TIMER_CHMR2 register ************************/ +/* Output */ +#define TIMER_CHMR2_CH4OCLREN_POS 15U +#define TIMER_CHMR2_CH4OCLREN_MSK BIT(TIMER_CHMR2_CH4OCLREN_POS) + +#define TIMER_CHMR2_CH4OMOD_POSS 12U +#define TIMER_CHMR2_CH4OMOD_POSE 14U +#define TIMER_CHMR2_CH4OMOD_MSK BITS(TIMER_CHMR2_CH4OMOD_POSS,TIMER_CHMR2_CH4OMOD_POSE) + +#define TIMER_CHMR2_CH4OPEN_POS 11U +#define TIMER_CHMR2_CH4OPEN_MSK BIT(TIMER_CHMR2_CH4OPEN_POS) + +#define TIMER_CHMR2_CH4OHSEN_POS 10U +#define TIMER_CHMR2_CH4OHSEN_MSK BIT(TIMER_CHMR2_CH4OHSEN_POS) + +#define TIMER_CHMR2_CC4SSEL_POSS 8U +#define TIMER_CHMR2_CC4SSEL_POSE 9U +#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) + +#define TIMER_CHMR2_CH3OCLREN_POS 7U +#define TIMER_CHMR2_CH3OCLREN_MSK BIT(TIMER_CHMR2_CH3OCLREN_POS) + +#define TIMER_CHMR2_CH3OMOD_POSS 4U +#define TIMER_CHMR2_CH3OMOD_POSE 6U +#define TIMER_CHMR2_CH3OMOD_MSK BITS(TIMER_CHMR2_CH3OMOD_POSS,TIMER_CHMR2_CH3OMOD_POSE) + +#define TIMER_CHMR2_CH3OPEN_POS 3U +#define TIMER_CHMR2_CH3OPEN_MSK BIT(TIMER_CHMR2_CH3OPEN_POS) + +#define TIMER_CHMR2_CH3OFEN_POS 2U +#define TIMER_CHMR2_CH3OFEN_MSK BIT(TIMER_CHMR2_CH3OFEN_POS) + +#define TIMER_CHMR2_CC3SSEL_POSS 0U +#define TIMER_CHMR2_CC3SSEL_POSE 1U +#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) + +/* Input */ +#define TIMER_CHMR2_I4FLT_POSS 12U +#define TIMER_CHMR2_I4FLT_POSE 15U +#define TIMER_CHMR2_I4FLT_MSK BITS(TIMER_CHMR2_I4FLT_POSS,TIMER_CHMR2_I4FLT_POSE) + +#define TIMER_CHMR2_IC4PRES_POSS 10U +#define TIMER_CHMR2_IC4PRES_POSE 11U +#define TIMER_CHMR2_IC4PRES_MSK BITS(TIMER_CHMR2_IC4PRES_POSS,TIMER_CHMR2_IC4PRES_POSE) + +#define TIMER_CHMR2_CC4SSEL_POSS 8U +#define TIMER_CHMR2_CC4SSEL_POSE 9U +#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) + +#define TIMER_CHMR2_I3FLT_POSS 4U +#define TIMER_CHMR2_I3FLT_POSE 7U +#define TIMER_CHMR2_I3FLT_MSK BITS(TIMER_CHMR2_I3FLT_POSS,TIMER_CHMR2_I3FLT_POSE) + +#define TIMER_CHMR2_IC3PRES_POSS 2U +#define TIMER_CHMR2_IC3PRES_POSE 3U +#define TIMER_CHMR2_IC3PRES_MSK BITS(TIMER_CHMR2_IC3PRES_POSS,TIMER_CHMR2_IC3PRES_POSE) + +#define TIMER_CHMR2_CC3SSEL_POSS 0U +#define TIMER_CHMR2_CC3SSEL_POSE 1U +#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) + +/****************** Bit definition for TIMER_CCEP register ************************/ + +#define TIMER_CCEP_CC4POL_POS 13U +#define TIMER_CCEP_CC4POL_MSK BIT(TIMER_CCEP_CC4POL_POS) + +#define TIMER_CCEP_CC4EN_POS 12U +#define TIMER_CCEP_CC4EN_MSK BIT(TIMER_CCEP_CC4EN_POS) + +#define TIMER_CCEP_CC3NPOL_POS 11U +#define TIMER_CCEP_CC3NPOL_MSK BIT(TIMER_CCEP_CC3NPOL_POS) + +#define TIMER_CCEP_CC3NEN_POS 10U +#define TIMER_CCEP_CC3NEN_MSK BIT(TIMER_CCEP_CC3NEN_POS) + +#define TIMER_CCEP_CC3POL_POS 9U +#define TIMER_CCEP_CC3POL_MSK BIT(TIMER_CCEP_CC3POL_POS) + +#define TIMER_CCEP_CC3EN_POS 8U +#define TIMER_CCEP_CC3EN_MSK BIT(TIMER_CCEP_CC3EN_POS) + +#define TIMER_CCEP_CC2NPOL_POS 7U +#define TIMER_CCEP_CC2NPOL_MSK BIT(TIMER_CCEP_CC2NPOL_POS) + +#define TIMER_CCEP_CC2NEN_POS 6U +#define TIMER_CCEP_CC2NEN_MSK BIT(TIMER_CCEP_CC2NEN_POS) + +#define TIMER_CCEP_CC2POL_POS 5U +#define TIMER_CCEP_CC2POL_MSK BIT(TIMER_CCEP_CC2POL_POS) + +#define TIMER_CCEP_CC2EN_POS 4U +#define TIMER_CCEP_CC2EN_MSK BIT(TIMER_CCEP_CC2EN_POS) + +#define TIMER_CCEP_CC1NPOL_POS 3U +#define TIMER_CCEP_CC1NPOL_MSK BIT(TIMER_CCEP_CC1NPOL_POS) + +#define TIMER_CCEP_CC1NEN_POS 2U +#define TIMER_CCEP_CC1NEN_MSK BIT(TIMER_CCEP_CC1NEN_POS) + +#define TIMER_CCEP_CC1POL_POS 1U +#define TIMER_CCEP_CC1POL_MSK BIT(TIMER_CCEP_CC1POL_POS) + +#define TIMER_CCEP_CC1EN_POS 0U +#define TIMER_CCEP_CC1EN_MSK BIT(TIMER_CCEP_CC1EN_POS) + +/****************** Bit definition for TIMER_COUNT register ************************/ + +#define TIMER_COUNT_CNTV_POSS 0U +#define TIMER_COUNT_CNTV_POSE 15U +#define TIMER_COUNT_CNTV_MSK BITS(TIMER_COUNT_CNTV_POSS,TIMER_COUNT_CNTV_POSE) + +/****************** Bit definition for TIMER_PRES register ************************/ + +#define TIMER_PRES_PSCV_POSS 0U +#define TIMER_PRES_PSCV_POSE 15U +#define TIMER_PRES_PSCV_MSK BITS(TIMER_PRES_PSCV_POSS,TIMER_PRES_PSCV_POSE) + +/****************** Bit definition for TIMER_AR register ************************/ + +#define TIMER_AR_ARRV_POSS 0U +#define TIMER_AR_ARRV_POSE 15U +#define TIMER_AR_ARRV_MSK BITS(TIMER_AR_ARRV_POSS,TIMER_AR_ARRV_POSE) + +/****************** Bit definition for TIMER_REPAR register ************************/ + +#define TIMER_REPAR_REPV_POSS 0U +#define TIMER_REPAR_REPV_POSE 7U +#define TIMER_REPAR_REPV_MSK BITS(TIMER_REPAR_REPV_POSS,TIMER_REPAR_REPV_POSE) + +/****************** Bit definition for TIMER_CCVAL1 register ************************/ + +#define TIMER_CCVAL1_CCRV1_POSS 0U +#define TIMER_CCVAL1_CCRV1_POSE 15U +#define TIMER_CCVAL1_CCRV1_MSK BITS(TIMER_CCVAL1_CCRV1_POSS,TIMER_CCVAL1_CCRV1_POSE) + +/****************** Bit definition for TIMER_CCVAL2 register ************************/ + +#define TIMER_CCVAL2_CCRV2_POSS 0U +#define TIMER_CCVAL2_CCRV2_POSE 15U +#define TIMER_CCVAL2_CCRV2_MSK BITS(TIMER_CCVAL2_CCRV2_POSS,TIMER_CCVAL2_CCRV2_POSE) + +/****************** Bit definition for TIMER_CCVAL3 register ************************/ + +#define TIMER_CCVAL3_CCRV3_POSS 0U +#define TIMER_CCVAL3_CCRV3_POSE 15U +#define TIMER_CCVAL3_CCRV3_MSK BITS(TIMER_CCVAL3_CCRV3_POSS,TIMER_CCVAL3_CCRV3_POSE) + +/****************** Bit definition for TIMER_CCVAL4 register ************************/ + +#define TIMER_CCVAL4_CCRV4_POSS 0U +#define TIMER_CCVAL4_CCRV4_POSE 15U +#define TIMER_CCVAL4_CCRV4_MSK BITS(TIMER_CCVAL4_CCRV4_POSS,TIMER_CCVAL4_CCRV4_POSE) + +/****************** Bit definition for TIMER_BDCFG register ************************/ + +#define TIMER_BDCFG_GOEN_POS 15U +#define TIMER_BDCFG_GOEN_MSK BIT(TIMER_BDCFG_GOEN_POS) + +#define TIMER_BDCFG_AOEN_POS 14U +#define TIMER_BDCFG_AOEN_MSK BIT(TIMER_BDCFG_AOEN_POS) + +#define TIMER_BDCFG_BRKP_POS 13U +#define TIMER_BDCFG_BRKP_MSK BIT(TIMER_BDCFG_BRKP_POS) + +#define TIMER_BDCFG_BRKEN_POS 12U +#define TIMER_BDCFG_BRKEN_MSK BIT(TIMER_BDCFG_BRKEN_POS) + +#define TIMER_BDCFG_OFFSSR_POS 11U +#define TIMER_BDCFG_OFFSSR_MSK BIT(TIMER_BDCFG_OFFSSR_POS) + +#define TIMER_BDCFG_OFFSSI_POS 10U +#define TIMER_BDCFG_OFFSSI_MSK BIT(TIMER_BDCFG_OFFSSI_POS) + +#define TIMER_BDCFG_LOCKLVL_POSS 8U +#define TIMER_BDCFG_LOCKLVL_POSE 9U +#define TIMER_BDCFG_LOCKLVL_MSK BITS(TIMER_BDCFG_LOCKLVL_POSS,TIMER_BDCFG_LOCKLVL_POSE) + +#define TIMER_BDCFG_DT_POSS 0U +#define TIMER_BDCFG_DT_POSE 7U +#define TIMER_BDCFG_DT_MSK BITS(TIMER_BDCFG_DT_POSS,TIMER_BDCFG_DT_POSE) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t SMCON; + __O uint32_t DIER; + __O uint32_t DIDR; + __I uint32_t DIVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __O uint32_t SGE; + __IO uint32_t CHMR1; + __IO uint32_t CHMR2; + __IO uint32_t CCEP; + __IO uint32_t COUNT; + __IO uint32_t PRES; + __IO uint32_t AR; + __IO uint32_t REPAR; + __IO uint32_t CCVAL1; + __IO uint32_t CCVAL2; + __IO uint32_t CCVAL3; + __IO uint32_t CCVAL4; + __IO uint32_t BDCFG; +} TIMER_TypeDef; + +/****************** Bit definition for USART_STAT register ************************/ + +#define USART_STAT_CTSIF_POS 9U +#define USART_STAT_CTSIF_MSK BIT(USART_STAT_CTSIF_POS) + +#define USART_STAT_TXEMPIF_POS 7U +#define USART_STAT_TXEMPIF_MSK BIT(USART_STAT_TXEMPIF_POS) + +#define USART_STAT_TXCIF_POS 6U +#define USART_STAT_TXCIF_MSK BIT(USART_STAT_TXCIF_POS) + +#define USART_STAT_RXNEIF_POS 5U +#define USART_STAT_RXNEIF_MSK BIT(USART_STAT_RXNEIF_POS) + +#define USART_STAT_IDLEIF_POS 4U +#define USART_STAT_IDLEIF_MSK BIT(USART_STAT_IDLEIF_POS) + +#define USART_STAT_OVRIF_POS 3U +#define USART_STAT_OVRIF_MSK BIT(USART_STAT_OVRIF_POS) + +#define USART_STAT_NDETIF_POS 2U +#define USART_STAT_NDETIF_MSK BIT(USART_STAT_NDETIF_POS) + +#define USART_STAT_FERRIF_POS 1U +#define USART_STAT_FERRIF_MSK BIT(USART_STAT_FERRIF_POS) + +#define USART_STAT_PERRIF_POS 0U +#define USART_STAT_PERRIF_MSK BIT(USART_STAT_PERRIF_POS) + +/****************** Bit definition for USART_DATA register ************************/ + +#define USART_DATA_VAL_POSS 0U +#define USART_DATA_VAL_POSE 8U +#define USART_DATA_VAL_MSK BITS(USART_DATA_VAL_POSS,USART_DATA_VAL_POSE) + +/****************** Bit definition for USART_BAUDCON register ************************/ + +#define USART_BAUDCON_DIV_M_POSS 4U +#define USART_BAUDCON_DIV_M_POSE 15U +#define USART_BAUDCON_DIV_M_MSK BITS(USART_BAUDCON_DIV_M_POSS,USART_BAUDCON_DIV_M_POSE) + +#define USART_BAUDCON_DIV_F_POSS 0U +#define USART_BAUDCON_DIV_F_POSE 3U +#define USART_BAUDCON_DIV_F_MSK BITS(USART_BAUDCON_DIV_F_POSS,USART_BAUDCON_DIV_F_POSE) + +/****************** Bit definition for USART_CON0 register ************************/ + +#define USART_CON0_EN_POS 13U +#define USART_CON0_EN_MSK BIT(USART_CON0_EN_POS) + +#define USART_CON0_DLEN_POS 12U +#define USART_CON0_DLEN_MSK BIT(USART_CON0_DLEN_POS) + +#define USART_CON0_WKMOD_POS 11U +#define USART_CON0_WKMOD_MSK BIT(USART_CON0_WKMOD_POS) + +#define USART_CON0_PEN_POS 10U +#define USART_CON0_PEN_MSK BIT(USART_CON0_PEN_POS) + +#define USART_CON0_PSEL_POS 9U +#define USART_CON0_PSEL_MSK BIT(USART_CON0_PSEL_POS) + +#define USART_CON0_PERRIE_POS 8U +#define USART_CON0_PERRIE_MSK BIT(USART_CON0_PERRIE_POS) + +#define USART_CON0_TXEMPIE_POS 7U +#define USART_CON0_TXEMPIE_MSK BIT(USART_CON0_TXEMPIE_POS) + +#define USART_CON0_TXCIE_POS 6U +#define USART_CON0_TXCIE_MSK BIT(USART_CON0_TXCIE_POS) + +#define USART_CON0_RXNEIE_POS 5U +#define USART_CON0_RXNEIE_MSK BIT(USART_CON0_RXNEIE_POS) + +#define USART_CON0_IDLEIE_POS 4U +#define USART_CON0_IDLEIE_MSK BIT(USART_CON0_IDLEIE_POS) + +#define USART_CON0_TXEN_POS 3U +#define USART_CON0_TXEN_MSK BIT(USART_CON0_TXEN_POS) + +#define USART_CON0_RXEN_POS 2U +#define USART_CON0_RXEN_MSK BIT(USART_CON0_RXEN_POS) + +#define USART_CON0_RXWK_POS 1U +#define USART_CON0_RXWK_MSK BIT(USART_CON0_RXWK_POS) + +/****************** Bit definition for USART_CON1 register ************************/ + +#define USART_CON1_STPLEN_POSS 12U +#define USART_CON1_STPLEN_POSE 13U +#define USART_CON1_STPLEN_MSK BITS(USART_CON1_STPLEN_POSS,USART_CON1_STPLEN_POSE) + +#define USART_CON1_SCKEN_POS 11U +#define USART_CON1_SCKEN_MSK BIT(USART_CON1_SCKEN_POS) + +#define USART_CON1_SCKPOL_POS 10U +#define USART_CON1_SCKPOL_MSK BIT(USART_CON1_SCKPOL_POS) + +#define USART_CON1_SCKPHA_POS 9U +#define USART_CON1_SCKPHA_MSK BIT(USART_CON1_SCKPHA_POS) + +#define USART_CON1_LBCP_POS 8U +#define USART_CON1_LBCP_MSK BIT(USART_CON1_LBCP_POS) + +#define USART_CON1_ADDR_POSS 0U +#define USART_CON1_ADDR_POSE 3U +#define USART_CON1_ADDR_MSK BITS(USART_CON1_ADDR_POSS,USART_CON1_ADDR_POSE) + +/****************** Bit definition for USART_CON2 register ************************/ + +#define USART_CON2_CTSIE_POS 10U +#define USART_CON2_CTSIE_MSK BIT(USART_CON2_CTSIE_POS) + +#define USART_CON2_CTSEN_POS 9U +#define USART_CON2_CTSEN_MSK BIT(USART_CON2_CTSEN_POS) + +#define USART_CON2_RTSEN_POS 8U +#define USART_CON2_RTSEN_MSK BIT(USART_CON2_RTSEN_POS) + +#define USART_CON2_TXDMAEN_POS 7U +#define USART_CON2_TXDMAEN_MSK BIT(USART_CON2_TXDMAEN_POS) + +#define USART_CON2_RXDMAEN_POS 6U +#define USART_CON2_RXDMAEN_MSK BIT(USART_CON2_RXDMAEN_POS) + +#define USART_CON2_SMARTEN_POS 5U +#define USART_CON2_SMARTEN_MSK BIT(USART_CON2_SMARTEN_POS) + +#define USART_CON2_NACK_POS 4U +#define USART_CON2_NACK_MSK BIT(USART_CON2_NACK_POS) + +#define USART_CON2_HDPSEL_POS 3U +#define USART_CON2_HDPSEL_MSK BIT(USART_CON2_HDPSEL_POS) + +#define USART_CON2_IREN_POS 1U +#define USART_CON2_IREN_MSK BIT(USART_CON2_IREN_POS) + +#define USART_CON2_ERRIE_POS 0U +#define USART_CON2_ERRIE_MSK BIT(USART_CON2_ERRIE_POS) + +/****************** Bit definition for USART_GP register ************************/ + +#define USART_GP_GTVAL_POSS 8U +#define USART_GP_GTVAL_POSE 15U +#define USART_GP_GTVAL_MSK BITS(USART_GP_GTVAL_POSS,USART_GP_GTVAL_POSE) + +#define USART_GP_PSC_POSS 0U +#define USART_GP_PSC_POSE 7U +#define USART_GP_PSC_MSK BITS(USART_GP_PSC_POSS,USART_GP_PSC_POSE) + +typedef struct +{ + __IO uint32_t STAT; + __IO uint32_t DATA; + __IO uint32_t BAUDCON; + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t GP; +} USART_TypeDef; + +/****************** Bit definition for UART_RBR register ************************/ + +#define UART_RBR_RBR_POSS 0U +#define UART_RBR_RBR_POSE 8U +#define UART_RBR_RBR_MSK BITS(UART_RBR_RBR_POSS,UART_RBR_RBR_POSE) + +/****************** Bit definition for UART_TBR register ************************/ + +#define UART_TBR_TBR_POSS 0U +#define UART_TBR_TBR_POSE 8U +#define UART_TBR_TBR_MSK BITS(UART_TBR_TBR_POSS,UART_TBR_TBR_POSE) + +/****************** Bit definition for UART_BRR register ************************/ + +#define UART_BRR_BRR_POSS 0U +#define UART_BRR_BRR_POSE 15U +#define UART_BRR_BRR_MSK BITS(UART_BRR_BRR_POSS,UART_BRR_BRR_POSE) + +/****************** Bit definition for UART_LCR register ************************/ + +#define UART_LCR_SWAP_POS 13U +#define UART_LCR_SWAP_MSK BIT(UART_LCR_SWAP_POS) + +#define UART_LCR_TXINV_POS 12U +#define UART_LCR_TXINV_MSK BIT(UART_LCR_TXINV_POS) + +#define UART_LCR_RXINV_POS 11U +#define UART_LCR_RXINV_MSK BIT(UART_LCR_RXINV_POS) + +#define UART_LCR_DATAINV_POS 10U +#define UART_LCR_DATAINV_MSK BIT(UART_LCR_DATAINV_POS) + +#define UART_LCR_MSBFIRST_POS 9U +#define UART_LCR_MSBFIRST_MSK BIT(UART_LCR_MSBFIRST_POS) + +#define UART_LCR_RTOEN_POS 8U +#define UART_LCR_RTOEN_MSK BIT(UART_LCR_RTOEN_POS) + +#define UART_LCR_BRWEN_POS 7U +#define UART_LCR_BRWEN_MSK BIT(UART_LCR_BRWEN_POS) + +#define UART_LCR_BC_POS 6U +#define UART_LCR_BC_MSK BIT(UART_LCR_BC_POS) + +#define UART_LCR_RXEN_POS 5U +#define UART_LCR_RXEN_MSK BIT(UART_LCR_RXEN_POS) + +#define UART_LCR_PS_POS 4U +#define UART_LCR_PS_MSK BIT(UART_LCR_PS_POS) + +#define UART_LCR_PEN_POS 3U +#define UART_LCR_PEN_MSK BIT(UART_LCR_PEN_POS) + +#define UART_LCR_STOP_POS 2U +#define UART_LCR_STOP_MSK BIT(UART_LCR_STOP_POS) + +#define UART_LCR_DLS_POSS 0U +#define UART_LCR_DLS_POSE 1U +#define UART_LCR_DLS_MSK BITS(UART_LCR_DLS_POSS,UART_LCR_DLS_POSE) + +/****************** Bit definition for UART_MCR register ************************/ + +#define UART_MCR_HDSEL_POS 22U +#define UART_MCR_HDSEL_MSK BIT(UART_MCR_HDSEL_POS) + +#define UART_MCR_ABRRS_POS 15U +#define UART_MCR_ABRRS_MSK BIT(UART_MCR_ABRRS_POS) + +#define UART_MCR_ABRMOD_POSS 13U +#define UART_MCR_ABRMOD_POSE 14U +#define UART_MCR_ABRMOD_MSK BITS(UART_MCR_ABRMOD_POSS,UART_MCR_ABRMOD_POSE) + +#define UART_MCR_ABREN_POS 12U +#define UART_MCR_ABREN_MSK BIT(UART_MCR_ABREN_POS) + +#define UART_MCR_DMAEN_POS 11U +#define UART_MCR_DMAEN_MSK BIT(UART_MCR_DMAEN_POS) + +#define UART_MCR_LINBDL_POS 10U +#define UART_MCR_LINBDL_MSK BIT(UART_MCR_LINBDL_POS) + +#define UART_MCR_BKREQ_POS 9U +#define UART_MCR_BKREQ_MSK BIT(UART_MCR_BKREQ_POS) + +#define UART_MCR_LINEN_POS 8U +#define UART_MCR_LINEN_MSK BIT(UART_MCR_LINEN_POS) + +#define UART_MCR_AADINV_POS 7U +#define UART_MCR_AADINV_MSK BIT(UART_MCR_AADINV_POS) + +#define UART_MCR_AADDIR_POS 6U +#define UART_MCR_AADDIR_MSK BIT(UART_MCR_AADDIR_POS) + +#define UART_MCR_AADNOR_POS 5U +#define UART_MCR_AADNOR_MSK BIT(UART_MCR_AADNOR_POS) + +#define UART_MCR_AADEN_POS 4U +#define UART_MCR_AADEN_MSK BIT(UART_MCR_AADEN_POS) + +#define UART_MCR_RTSCTRL_POS 3U +#define UART_MCR_RTSCTRL_MSK BIT(UART_MCR_RTSCTRL_POS) + +#define UART_MCR_AFCEN_POS 2U +#define UART_MCR_AFCEN_MSK BIT(UART_MCR_AFCEN_POS) + +#define UART_MCR_LBEN_POS 1U +#define UART_MCR_LBEN_MSK BIT(UART_MCR_LBEN_POS) + +#define UART_MCR_IREN_POS 0U +#define UART_MCR_IREN_MSK BIT(UART_MCR_IREN_POS) + +/****************** Bit definition for UART_CR register ************************/ + +#define UART_CR_PSC_POSS 16U +#define UART_CR_PSC_POSE 23U +#define UART_CR_PSC_MSK BITS(UART_CR_PSC_POSS,UART_CR_PSC_POSE) + +#define UART_CR_DLY_POSS 8U +#define UART_CR_DLY_POSE 15U +#define UART_CR_DLY_MSK BITS(UART_CR_DLY_POSS,UART_CR_DLY_POSE) + +#define UART_CR_ADDR_POSS 0U +#define UART_CR_ADDR_POSE 7U +#define UART_CR_ADDR_MSK BITS(UART_CR_ADDR_POSS,UART_CR_ADDR_POSE) + +/****************** Bit definition for UART_RTOR register ************************/ + +#define UART_RTOR_BLEN_POSS 24U +#define UART_RTOR_BLEN_POSE 31U +#define UART_RTOR_BLEN_MSK BITS(UART_RTOR_BLEN_POSS,UART_RTOR_BLEN_POSE) + +#define UART_RTOR_RTO_POSS 0U +#define UART_RTOR_RTO_POSE 23U +#define UART_RTOR_RTO_MSK BITS(UART_RTOR_RTO_POSS,UART_RTOR_RTO_POSE) + +/****************** Bit definition for UART_FCR register ************************/ + +#define UART_FCR_TXFL_POSS 12U +#define UART_FCR_TXFL_POSE 15U +#define UART_FCR_TXFL_MSK BITS(UART_FCR_TXFL_POSS,UART_FCR_TXFL_POSE) + +#define UART_FCR_RXFL_POSS 8U +#define UART_FCR_RXFL_POSE 11U +#define UART_FCR_RXFL_MSK BITS(UART_FCR_RXFL_POSS,UART_FCR_RXFL_POSE) + +#define UART_FCR_TXTL_POSS 6U +#define UART_FCR_TXTL_POSE 7U +#define UART_FCR_TXTL_MSK BITS(UART_FCR_TXTL_POSS,UART_FCR_TXTL_POSE) + +#define UART_FCR_RXTL_POSS 4U +#define UART_FCR_RXTL_POSE 5U +#define UART_FCR_RXTL_MSK BITS(UART_FCR_RXTL_POSS,UART_FCR_RXTL_POSE) + +#define UART_FCR_TFRST_POS 2U +#define UART_FCR_TFRST_MSK BIT(UART_FCR_TFRST_POS) + +#define UART_FCR_RFRST_POS 1U +#define UART_FCR_RFRST_MSK BIT(UART_FCR_RFRST_POS) + +#define UART_FCR_FIFOEN_POS 0U +#define UART_FCR_FIFOEN_MSK BIT(UART_FCR_FIFOEN_POS) + +/****************** Bit definition for UART_SR register ************************/ + +#define UART_SR_CTS_POS 14U +#define UART_SR_CTS_MSK BIT(UART_SR_CTS_POS) + +#define UART_SR_DCTS_POS 13U +#define UART_SR_DCTS_MSK BIT(UART_SR_DCTS_POS) + +#define UART_SR_RFF_POS 12U +#define UART_SR_RFF_MSK BIT(UART_SR_RFF_POS) + +#define UART_SR_RFNE_POS 11U +#define UART_SR_RFNE_MSK BIT(UART_SR_RFNE_POS) + +#define UART_SR_TFEM_POS 10U +#define UART_SR_TFEM_MSK BIT(UART_SR_TFEM_POS) + +#define UART_SR_TFNF_POS 9U +#define UART_SR_TFNF_MSK BIT(UART_SR_TFNF_POS) + +#define UART_SR_BUSY_POS 8U +#define UART_SR_BUSY_MSK BIT(UART_SR_BUSY_POS) + +#define UART_SR_RFE_POS 7U +#define UART_SR_RFE_MSK BIT(UART_SR_RFE_POS) + +#define UART_SR_TEM_POS 6U +#define UART_SR_TEM_MSK BIT(UART_SR_TEM_POS) + +#define UART_SR_TBEM_POS 5U +#define UART_SR_TBEM_MSK BIT(UART_SR_TBEM_POS) + +#define UART_SR_BF_POS 4U +#define UART_SR_BF_MSK BIT(UART_SR_BF_POS) + +#define UART_SR_FE_POS 3U +#define UART_SR_FE_MSK BIT(UART_SR_FE_POS) + +#define UART_SR_PE_POS 2U +#define UART_SR_PE_MSK BIT(UART_SR_PE_POS) + +#define UART_SR_OE_POS 1U +#define UART_SR_OE_MSK BIT(UART_SR_OE_POS) + +#define UART_SR_DR_POS 0U +#define UART_SR_DR_MSK BIT(UART_SR_DR_POS) + +/****************** Bit definition for UART_IER register ************************/ + +#define UART_IER_CMIE_POS 11U +#define UART_IER_CMIE_MSK BIT(UART_IER_CMIE_POS) + +#define UART_IER_EOBIE_POS 10U +#define UART_IER_EOBIE_MSK BIT(UART_IER_EOBIE_POS) + +#define UART_IER_TCIE_POS 9U +#define UART_IER_TCIE_MSK BIT(UART_IER_TCIE_POS) + +#define UART_IER_LINBKIE_POS 8U +#define UART_IER_LINBKIE_MSK BIT(UART_IER_LINBKIE_POS) + +#define UART_IER_ABTOIE_POS 7U +#define UART_IER_ABTOIE_MSK BIT(UART_IER_ABTOIE_POS) + +#define UART_IER_ABEIE_POS 6U +#define UART_IER_ABEIE_MSK BIT(UART_IER_ABEIE_POS) + +#define UART_IER_BZIE_POS 5U +#define UART_IER_BZIE_MSK BIT(UART_IER_BZIE_POS) + +#define UART_IER_RTOIE_POS 4U +#define UART_IER_RTOIE_MSK BIT(UART_IER_RTOIE_POS) + +#define UART_IER_MDSIE_POS 3U +#define UART_IER_MDSIE_MSK BIT(UART_IER_MDSIE_POS) + +#define UART_IER_RXSIE_POS 2U +#define UART_IER_RXSIE_MSK BIT(UART_IER_RXSIE_POS) + +#define UART_IER_TXSIE_POS 1U +#define UART_IER_TXSIE_MSK BIT(UART_IER_TXSIE_POS) + +#define UART_IER_RXRDIE_POS 0U +#define UART_IER_RXRDIE_MSK BIT(UART_IER_RXRDIE_POS) + +/****************** Bit definition for UART_IDR register ************************/ + +#define UART_IDR_CMID_POS 11U +#define UART_IDR_CMID_MSK BIT(UART_IDR_CMID_POS) + +#define UART_IDR_EOBID_POS 10U +#define UART_IDR_EOBID_MSK BIT(UART_IDR_EOBID_POS) + +#define UART_IDR_TCID_POS 9U +#define UART_IDR_TCID_MSK BIT(UART_IDR_TCID_POS) + +#define UART_IDR_LINBKID_POS 8U +#define UART_IDR_LINBKID_MSK BIT(UART_IDR_LINBKID_POS) + +#define UART_IDR_ABTOID_POS 7U +#define UART_IDR_ABTOID_MSK BIT(UART_IDR_ABTOID_POS) + +#define UART_IDR_ABEID_POS 6U +#define UART_IDR_ABEID_MSK BIT(UART_IDR_ABEID_POS) + +#define UART_IDR_BZID_POS 5U +#define UART_IDR_BZID_MSK BIT(UART_IDR_BZID_POS) + +#define UART_IDR_RTOID_POS 4U +#define UART_IDR_RTOID_MSK BIT(UART_IDR_RTOID_POS) + +#define UART_IDR_MDSID_POS 3U +#define UART_IDR_MDSID_MSK BIT(UART_IDR_MDSID_POS) + +#define UART_IDR_RXSID_POS 2U +#define UART_IDR_RXSID_MSK BIT(UART_IDR_RXSID_POS) + +#define UART_IDR_TXSID_POS 1U +#define UART_IDR_TXSID_MSK BIT(UART_IDR_TXSID_POS) + +#define UART_IDR_RXRDID_POS 0U +#define UART_IDR_RXRDID_MSK BIT(UART_IDR_RXRDID_POS) + +/****************** Bit definition for UART_IVS register ************************/ + +#define UART_IVS_CMIS_POS 11U +#define UART_IVS_CMIS_MSK BIT(UART_IVS_CMIS_POS) + +#define UART_IVS_EOBIS_POS 10U +#define UART_IVS_EOBIS_MSK BIT(UART_IVS_EOBIS_POS) + +#define UART_IVS_TCIS_POS 9U +#define UART_IVS_TCIS_MSK BIT(UART_IVS_TCIS_POS) + +#define UART_IVS_LINBKIS_POS 8U +#define UART_IVS_LINBKIS_MSK BIT(UART_IVS_LINBKIS_POS) + +#define UART_IVS_ABTOIS_POS 7U +#define UART_IVS_ABTOIS_MSK BIT(UART_IVS_ABTOIS_POS) + +#define UART_IVS_ABEIS_POS 6U +#define UART_IVS_ABEIS_MSK BIT(UART_IVS_ABEIS_POS) + +#define UART_IVS_BZIS_POS 5U +#define UART_IVS_BZIS_MSK BIT(UART_IVS_BZIS_POS) + +#define UART_IVS_RTOIS_POS 4U +#define UART_IVS_RTOIS_MSK BIT(UART_IVS_RTOIS_POS) + +#define UART_IVS_MDSIS_POS 3U +#define UART_IVS_MDSIS_MSK BIT(UART_IVS_MDSIS_POS) + +#define UART_IVS_RXSIS_POS 2U +#define UART_IVS_RXSIS_MSK BIT(UART_IVS_RXSIS_POS) + +#define UART_IVS_TXSIS_POS 1U +#define UART_IVS_TXSIS_MSK BIT(UART_IVS_TXSIS_POS) + +#define UART_IVS_RXRDIS_POS 0U +#define UART_IVS_RXRDIS_MSK BIT(UART_IVS_RXRDIS_POS) + +/****************** Bit definition for UART_RIF register ************************/ + +#define UART_RIF_CMIF_POS 11U +#define UART_RIF_CMIF_MSK BIT(UART_RIF_CMIF_POS) + +#define UART_RIF_EOBIF_POS 10U +#define UART_RIF_EOBIF_MSK BIT(UART_RIF_EOBIF_POS) + +#define UART_RIF_TCIF_POS 9U +#define UART_RIF_TCIF_MSK BIT(UART_RIF_TCIF_POS) + +#define UART_RIF_LINBKIF_POS 8U +#define UART_RIF_LINBKIF_MSK BIT(UART_RIF_LINBKIF_POS) + +#define UART_RIF_ABTOIF_POS 7U +#define UART_RIF_ABTOIF_MSK BIT(UART_RIF_ABTOIF_POS) + +#define UART_RIF_ABEIF_POS 6U +#define UART_RIF_ABEIF_MSK BIT(UART_RIF_ABEIF_POS) + +#define UART_RIF_BZIF_POS 5U +#define UART_RIF_BZIF_MSK BIT(UART_RIF_BZIF_POS) + +#define UART_RIF_RTOIF_POS 4U +#define UART_RIF_RTOIF_MSK BIT(UART_RIF_RTOIF_POS) + +#define UART_RIF_MDSIF_POS 3U +#define UART_RIF_MDSIF_MSK BIT(UART_RIF_MDSIF_POS) + +#define UART_RIF_RXSIF_POS 2U +#define UART_RIF_RXSIF_MSK BIT(UART_RIF_RXSIF_POS) + +#define UART_RIF_TXSIF_POS 1U +#define UART_RIF_TXSIF_MSK BIT(UART_RIF_TXSIF_POS) + +#define UART_RIF_RXRDIF_POS 0U +#define UART_RIF_RXRDIF_MSK BIT(UART_RIF_RXRDIF_POS) + +/****************** Bit definition for UART_IFM register ************************/ + +#define UART_IFM_CMIM_POS 11U +#define UART_IFM_CMIM_MSK BIT(UART_IFM_CMIM_POS) + +#define UART_IFM_EOBIM_POS 10U +#define UART_IFM_EOBIM_MSK BIT(UART_IFM_EOBIM_POS) + +#define UART_IFM_TCIM_POS 9U +#define UART_IFM_TCIM_MSK BIT(UART_IFM_TCIM_POS) + +#define UART_IFM_LINBKIM_POS 8U +#define UART_IFM_LINBKIM_MSK BIT(UART_IFM_LINBKIM_POS) + +#define UART_IFM_ABTOIM_POS 7U +#define UART_IFM_ABTOIM_MSK BIT(UART_IFM_ABTOIM_POS) + +#define UART_IFM_ABEIM_POS 6U +#define UART_IFM_ABEIM_MSK BIT(UART_IFM_ABEIM_POS) + +#define UART_IFM_BZIM_POS 5U +#define UART_IFM_BZIM_MSK BIT(UART_IFM_BZIM_POS) + +#define UART_IFM_RTOIM_POS 4U +#define UART_IFM_RTOIM_MSK BIT(UART_IFM_RTOIM_POS) + +#define UART_IFM_MDSIM_POS 3U +#define UART_IFM_MDSIM_MSK BIT(UART_IFM_MDSIM_POS) + +#define UART_IFM_RXSIM_POS 2U +#define UART_IFM_RXSIM_MSK BIT(UART_IFM_RXSIM_POS) + +#define UART_IFM_TXSIM_POS 1U +#define UART_IFM_TXSIM_MSK BIT(UART_IFM_TXSIM_POS) + +#define UART_IFM_RXRDIM_POS 0U +#define UART_IFM_RXRDIM_MSK BIT(UART_IFM_RXRDIM_POS) + +/****************** Bit definition for UART_ICR register ************************/ + +#define UART_ICR_CMIC_POS 11U +#define UART_ICR_CMIC_MSK BIT(UART_ICR_CMIC_POS) + +#define UART_ICR_EOBIC_POS 10U +#define UART_ICR_EOBIC_MSK BIT(UART_ICR_EOBIC_POS) + +#define UART_ICR_TCIC_POS 9U +#define UART_ICR_TCIC_MSK BIT(UART_ICR_TCIC_POS) + +#define UART_ICR_LINBKIC_POS 8U +#define UART_ICR_LINBKIC_MSK BIT(UART_ICR_LINBKIC_POS) + +#define UART_ICR_ABTOIC_POS 7U +#define UART_ICR_ABTOIC_MSK BIT(UART_ICR_ABTOIC_POS) + +#define UART_ICR_ABEIC_POS 6U +#define UART_ICR_ABEIC_MSK BIT(UART_ICR_ABEIC_POS) + +#define UART_ICR_BZIC_POS 5U +#define UART_ICR_BZIC_MSK BIT(UART_ICR_BZIC_POS) + +#define UART_ICR_CHTOIC_POS 4U +#define UART_ICR_CHTOIC_MSK BIT(UART_ICR_CHTOIC_POS) + +#define UART_ICR_MDSIC_POS 3U +#define UART_ICR_MDSIC_MSK BIT(UART_ICR_MDSIC_POS) + +#define UART_ICR_RXSIC_POS 2U +#define UART_ICR_RXSIC_MSK BIT(UART_ICR_RXSIC_POS) + +#define UART_ICR_TXSIC_POS 1U +#define UART_ICR_TXSIC_MSK BIT(UART_ICR_TXSIC_POS) + +#define UART_ICR_RXRDIC_POS 0U +#define UART_ICR_RXRDIC_MSK BIT(UART_ICR_RXRDIC_POS) + +typedef struct +{ + __I uint32_t RBR; + __IO uint32_t TBR; + __IO uint32_t BRR; + __IO uint32_t LCR; + __IO uint32_t MCR; + __IO uint32_t CR; + __IO uint32_t RTOR; + __IO uint32_t FCR; + __I uint32_t SR; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} UART_TypeDef; + +/****************** Bit definition for LPUART_CON0 register ************************/ + +#define LPUART_CON0_MODESEL_POSS 30U +#define LPUART_CON0_MODESEL_POSE 31U +#define LPUART_CON0_MODESEL_MSK BITS(LPUART_CON0_MODESEL_POSS,LPUART_CON0_MODESEL_POSE) + +#define LPUART_CON0_TXDMAE_POS 29U +#define LPUART_CON0_TXDMAE_MSK BIT(LPUART_CON0_TXDMAE_POS) + +#define LPUART_CON0_RXDMAE_POS 28U +#define LPUART_CON0_RXDMAE_MSK BIT(LPUART_CON0_RXDMAE_POS) + +#define LPUART_CON0_INTERVAL_POSS 16U +#define LPUART_CON0_INTERVAL_POSE 23U +#define LPUART_CON0_INTERVAL_MSK BITS(LPUART_CON0_INTERVAL_POSS,LPUART_CON0_INTERVAL_POSE) + +#define LPUART_CON0_SYNCBP_POS 15U +#define LPUART_CON0_SYNCBP_MSK BIT(LPUART_CON0_SYNCBP_POS) + +#define LPUART_CON0_CTSPOL_POS 13U +#define LPUART_CON0_CTSPOL_MSK BIT(LPUART_CON0_CTSPOL_POS) + +#define LPUART_CON0_RTSPOL_POS 12U +#define LPUART_CON0_RTSPOL_MSK BIT(LPUART_CON0_RTSPOL_POS) + +#define LPUART_CON0_ATCTSE_POS 11U +#define LPUART_CON0_ATCTSE_MSK BIT(LPUART_CON0_ATCTSE_POS) + +#define LPUART_CON0_ATRTSE_POS 10U +#define LPUART_CON0_ATRTSE_MSK BIT(LPUART_CON0_ATRTSE_POS) + +#define LPUART_CON0_BRKCE_POS 8U +#define LPUART_CON0_BRKCE_MSK BIT(LPUART_CON0_BRKCE_POS) + +#define LPUART_CON0_LPBMOD_POS 7U +#define LPUART_CON0_LPBMOD_MSK BIT(LPUART_CON0_LPBMOD_POS) + +#define LPUART_CON0_STICKPARSEL_POS 6U +#define LPUART_CON0_STICKPARSEL_MSK BIT(LPUART_CON0_STICKPARSEL_POS) + +#define LPUART_CON0_EVENPARSEL_POS 5U +#define LPUART_CON0_EVENPARSEL_MSK BIT(LPUART_CON0_EVENPARSEL_POS) + +#define LPUART_CON0_PARCHKE_POS 4U +#define LPUART_CON0_PARCHKE_MSK BIT(LPUART_CON0_PARCHKE_POS) + +#define LPUART_CON0_STPLENTH_POS 3U +#define LPUART_CON0_STPLENTH_MSK BIT(LPUART_CON0_STPLENTH_POS) + +#define LPUART_CON0_DATLENTH_POSS 0U +#define LPUART_CON0_DATLENTH_POSE 2U +#define LPUART_CON0_DATLENTH_MSK BITS(LPUART_CON0_DATLENTH_POSS,LPUART_CON0_DATLENTH_POSE) + +/****************** Bit definition for LPUART_CON1 register ************************/ + +#define LPUART_CON1_ADDCMP_POSS 24U +#define LPUART_CON1_ADDCMP_POSE 31U +#define LPUART_CON1_ADDCMP_MSK BITS(LPUART_CON1_ADDCMP_POSS,LPUART_CON1_ADDCMP_POSE) + +#define LPUART_CON1_ADETE_POS 23U +#define LPUART_CON1_ADETE_MSK BIT(LPUART_CON1_ADETE_POS) + +#define LPUART_CON1_ATDIRM_POS 22U +#define LPUART_CON1_ATDIRM_MSK BIT(LPUART_CON1_ATDIRM_POS) + +#define LPUART_CON1_ATADETE_POS 21U +#define LPUART_CON1_ATADETE_MSK BIT(LPUART_CON1_ATADETE_POS) + +#define LPUART_CON1_NMPMOD_POS 20U +#define LPUART_CON1_NMPMOD_MSK BIT(LPUART_CON1_NMPMOD_POS) + +#define LPUART_CON1_IRWIDTH_POS 16U +#define LPUART_CON1_IRWIDTH_MSK BIT(LPUART_CON1_IRWIDTH_POS) + +#define LPUART_CON1_TOICMP_POSS 8U +#define LPUART_CON1_TOICMP_POSE 15U +#define LPUART_CON1_TOICMP_MSK BITS(LPUART_CON1_TOICMP_POSS,LPUART_CON1_TOICMP_POSE) + +#define LPUART_CON1_TOCNTE_POS 7U +#define LPUART_CON1_TOCNTE_MSK BIT(LPUART_CON1_TOCNTE_POS) + +#define LPUART_CON1_IRTXINV_POS 3U +#define LPUART_CON1_IRTXINV_MSK BIT(LPUART_CON1_IRTXINV_POS) + +#define LPUART_CON1_IRRXINV_POS 2U +#define LPUART_CON1_IRRXINV_MSK BIT(LPUART_CON1_IRRXINV_POS) + +#define LPUART_CON1_IRTXE_POS 1U +#define LPUART_CON1_IRTXE_MSK BIT(LPUART_CON1_IRTXE_POS) + +#define LPUART_CON1_RTS_POS 0U +#define LPUART_CON1_RTS_MSK BIT(LPUART_CON1_RTS_POS) + +/****************** Bit definition for LPUART_CLKDIV register ************************/ + +#define LPUART_CLKDIV_CLKDIV_POSS 0U +#define LPUART_CLKDIV_CLKDIV_POSE 19U +#define LPUART_CLKDIV_CLKDIV_MSK BITS(LPUART_CLKDIV_CLKDIV_POSS,LPUART_CLKDIV_CLKDIV_POSE) + +/****************** Bit definition for LPUART_FIFOCON register ************************/ + +#define LPUART_FIFOCON_RTSTRGLVL_POSS 12U +#define LPUART_FIFOCON_RTSTRGLVL_POSE 15U +#define LPUART_FIFOCON_RTSTRGLVL_MSK BITS(LPUART_FIFOCON_RTSTRGLVL_POSS,LPUART_FIFOCON_RTSTRGLVL_POSE) + +#define LPUART_FIFOCON_RXTRGLVL_POSS 8U +#define LPUART_FIFOCON_RXTRGLVL_POSE 11U +#define LPUART_FIFOCON_RXTRGLVL_MSK BITS(LPUART_FIFOCON_RXTRGLVL_POSS,LPUART_FIFOCON_RXTRGLVL_POSE) + +#define LPUART_FIFOCON_NMPMRXDIS_POS 2U +#define LPUART_FIFOCON_NMPMRXDIS_MSK BIT(LPUART_FIFOCON_NMPMRXDIS_POS) + +#define LPUART_FIFOCON_TXRESET_POS 1U +#define LPUART_FIFOCON_TXRESET_MSK BIT(LPUART_FIFOCON_TXRESET_POS) + +#define LPUART_FIFOCON_RXRESET_POS 0U +#define LPUART_FIFOCON_RXRESET_MSK BIT(LPUART_FIFOCON_RXRESET_POS) + +/****************** Bit definition for LPUART_RXDR register ************************/ + +#define LPUART_RXDR_FERR_POS 15U +#define LPUART_RXDR_FERR_MSK BIT(LPUART_RXDR_FERR_POS) + +#define LPUART_RXDR_PERR_POS 14U +#define LPUART_RXDR_PERR_MSK BIT(LPUART_RXDR_PERR_POS) + +#define LPUART_RXDR_RXDR_POSS 0U +#define LPUART_RXDR_RXDR_POSE 8U +#define LPUART_RXDR_RXDR_MSK BITS(LPUART_RXDR_RXDR_POSS,LPUART_RXDR_RXDR_POSE) + +/****************** Bit definition for LPUART_TXDR register ************************/ + +#define LPUART_TXDR_TXDR_POSS 0U +#define LPUART_TXDR_TXDR_POSE 8U +#define LPUART_TXDR_TXDR_MSK BITS(LPUART_TXDR_TXDR_POSS,LPUART_TXDR_TXDR_POSE) + +/****************** Bit definition for LPUART_STAT register ************************/ + +#define LPUART_STAT_RTSSTAT_POS 18U +#define LPUART_STAT_RTSSTAT_MSK BIT(LPUART_STAT_RTSSTAT_POS) + +#define LPUART_STAT_CTSSTAT_POS 17U +#define LPUART_STAT_CTSSTAT_MSK BIT(LPUART_STAT_CTSSTAT_POS) + +#define LPUART_STAT_TXIDLE_POS 16U +#define LPUART_STAT_TXIDLE_MSK BIT(LPUART_STAT_TXIDLE_POS) + +#define LPUART_STAT_TXFULL_POS 15U +#define LPUART_STAT_TXFULL_MSK BIT(LPUART_STAT_TXFULL_POS) + +#define LPUART_STAT_TXEMP_POS 14U +#define LPUART_STAT_TXEMP_MSK BIT(LPUART_STAT_TXEMP_POS) + +#define LPUART_STAT_TXPTR_POSS 8U +#define LPUART_STAT_TXPTR_POSE 13U +#define LPUART_STAT_TXPTR_MSK BITS(LPUART_STAT_TXPTR_POSS,LPUART_STAT_TXPTR_POSE) + +#define LPUART_STAT_RXFULL_POS 7U +#define LPUART_STAT_RXFULL_MSK BIT(LPUART_STAT_RXFULL_POS) + +#define LPUART_STAT_RXEMP_POS 6U +#define LPUART_STAT_RXEMP_MSK BIT(LPUART_STAT_RXEMP_POS) + +#define LPUART_STAT_RXPTR_POSS 0U +#define LPUART_STAT_RXPTR_POSE 5U +#define LPUART_STAT_RXPTR_MSK BITS(LPUART_STAT_RXPTR_POSS,LPUART_STAT_RXPTR_POSE) + +/****************** Bit definition for LPUART_IER register ************************/ + +#define LPUART_IER_TCIE_POS 15U +#define LPUART_IER_TCIE_MSK BIT(LPUART_IER_TCIE_POS) + +#define LPUART_IER_ADETIE_POS 12U +#define LPUART_IER_ADETIE_MSK BIT(LPUART_IER_ADETIE_POS) + +#define LPUART_IER_BRKERRIE_POS 11U +#define LPUART_IER_BRKERRIE_MSK BIT(LPUART_IER_BRKERRIE_POS) + +#define LPUART_IER_FERRIE_POS 10U +#define LPUART_IER_FERRIE_MSK BIT(LPUART_IER_FERRIE_POS) + +#define LPUART_IER_PERRIE_POS 9U +#define LPUART_IER_PERRIE_MSK BIT(LPUART_IER_PERRIE_POS) + +#define LPUART_IER_DATWKIE_POS 8U +#define LPUART_IER_DATWKIE_MSK BIT(LPUART_IER_DATWKIE_POS) + +#define LPUART_IER_CTSWKIE_POS 7U +#define LPUART_IER_CTSWKIE_MSK BIT(LPUART_IER_CTSWKIE_POS) + +#define LPUART_IER_TXOVIE_POS 5U +#define LPUART_IER_TXOVIE_MSK BIT(LPUART_IER_TXOVIE_POS) + +#define LPUART_IER_RXOVIE_POS 4U +#define LPUART_IER_RXOVIE_MSK BIT(LPUART_IER_RXOVIE_POS) + +#define LPUART_IER_RXTOIE_POS 3U +#define LPUART_IER_RXTOIE_MSK BIT(LPUART_IER_RXTOIE_POS) + +#define LPUART_IER_CTSDETIE_POS 2U +#define LPUART_IER_CTSDETIE_MSK BIT(LPUART_IER_CTSDETIE_POS) + +#define LPUART_IER_TBEMPIE_POS 1U +#define LPUART_IER_TBEMPIE_MSK BIT(LPUART_IER_TBEMPIE_POS) + +#define LPUART_IER_RBRIE_POS 0U +#define LPUART_IER_RBRIE_MSK BIT(LPUART_IER_RBRIE_POS) + +/****************** Bit definition for LPUART_IFLAG register ************************/ + +#define LPUART_IFLAG_TCIF_POS 15U +#define LPUART_IFLAG_TCIF_MSK BIT(LPUART_IFLAG_TCIF_POS) + +#define LPUART_IFLAG_ADETIF_POS 12U +#define LPUART_IFLAG_ADETIF_MSK BIT(LPUART_IFLAG_ADETIF_POS) + +#define LPUART_IFLAG_BRKERRIF_POS 11U +#define LPUART_IFLAG_BRKERRIF_MSK BIT(LPUART_IFLAG_BRKERRIF_POS) + +#define LPUART_IFLAG_FERRIF_POS 10U +#define LPUART_IFLAG_FERRIF_MSK BIT(LPUART_IFLAG_FERRIF_POS) + +#define LPUART_IFLAG_PERRIF_POS 9U +#define LPUART_IFLAG_PERRIF_MSK BIT(LPUART_IFLAG_PERRIF_POS) + +#define LPUART_IFLAG_DATWKIF_POS 8U +#define LPUART_IFLAG_DATWKIF_MSK BIT(LPUART_IFLAG_DATWKIF_POS) + +#define LPUART_IFLAG_CTSWKIF_POS 7U +#define LPUART_IFLAG_CTSWKIF_MSK BIT(LPUART_IFLAG_CTSWKIF_POS) + +#define LPUART_IFLAG_TXOVIF_POS 5U +#define LPUART_IFLAG_TXOVIF_MSK BIT(LPUART_IFLAG_TXOVIF_POS) + +#define LPUART_IFLAG_RXOVIF_POS 4U +#define LPUART_IFLAG_RXOVIF_MSK BIT(LPUART_IFLAG_RXOVIF_POS) + +#define LPUART_IFLAG_RXTOIF_POS 3U +#define LPUART_IFLAG_RXTOIF_MSK BIT(LPUART_IFLAG_RXTOIF_POS) + +#define LPUART_IFLAG_CTSDETIF_POS 2U +#define LPUART_IFLAG_CTSDETIF_MSK BIT(LPUART_IFLAG_CTSDETIF_POS) + +#define LPUART_IFLAG_TBEMPIF_POS 1U +#define LPUART_IFLAG_TBEMPIF_MSK BIT(LPUART_IFLAG_TBEMPIF_POS) + +#define LPUART_IFLAG_RBRIF_POS 0U +#define LPUART_IFLAG_RBRIF_MSK BIT(LPUART_IFLAG_RBRIF_POS) + +/****************** Bit definition for LPUART_IFC register ************************/ + +#define LPUART_IFC_TCIFC_POS 15U +#define LPUART_IFC_TCIFC_MSK BIT(LPUART_IFC_TCIFC_POS) + +#define LPUART_IFC_ADETIFC_POS 12U +#define LPUART_IFC_ADETIFC_MSK BIT(LPUART_IFC_ADETIFC_POS) + +#define LPUART_IFC_BRKERRIFC_POS 11U +#define LPUART_IFC_BRKERRIFC_MSK BIT(LPUART_IFC_BRKERRIFC_POS) + +#define LPUART_IFC_FERRIFC_POS 10U +#define LPUART_IFC_FERRIFC_MSK BIT(LPUART_IFC_FERRIFC_POS) + +#define LPUART_IFC_PERRIFC_POS 9U +#define LPUART_IFC_PERRIFC_MSK BIT(LPUART_IFC_PERRIFC_POS) + +#define LPUART_IFC_DATWKIFC_POS 8U +#define LPUART_IFC_DATWKIFC_MSK BIT(LPUART_IFC_DATWKIFC_POS) + +#define LPUART_IFC_CTSWKIFC_POS 7U +#define LPUART_IFC_CTSWKIFC_MSK BIT(LPUART_IFC_CTSWKIFC_POS) + +#define LPUART_IFC_TXOVIFC_POS 5U +#define LPUART_IFC_TXOVIFC_MSK BIT(LPUART_IFC_TXOVIFC_POS) + +#define LPUART_IFC_RXOVIFC_POS 4U +#define LPUART_IFC_RXOVIFC_MSK BIT(LPUART_IFC_RXOVIFC_POS) + +#define LPUART_IFC_CTSDETIFC_POS 2U +#define LPUART_IFC_CTSDETIFC_MSK BIT(LPUART_IFC_CTSDETIFC_POS) + +#define LPUART_IFC_TBEMPIFC_POS 1U +#define LPUART_IFC_TBEMPIFC_MSK BIT(LPUART_IFC_TBEMPIFC_POS) + +#define LPUART_IFC_RBRIFC_POS 0U +#define LPUART_IFC_RBRIFC_MSK BIT(LPUART_IFC_RBRIFC_POS) + +/****************** Bit definition for LPUART_ISTAT register ************************/ + +#define LPUART_ISTAT_TCINT_POS 15U +#define LPUART_ISTAT_TCINT_MSK BIT(LPUART_ISTAT_TCINT_POS) + +#define LPUART_ISTAT_RXSTATINT_POS 9U +#define LPUART_ISTAT_RXSTATINT_MSK BIT(LPUART_ISTAT_RXSTATINT_POS) + +#define LPUART_ISTAT_DATWKINT_POS 8U +#define LPUART_ISTAT_DATWKINT_MSK BIT(LPUART_ISTAT_DATWKINT_POS) + +#define LPUART_ISTAT_CTSWKINT_POS 7U +#define LPUART_ISTAT_CTSWKINT_MSK BIT(LPUART_ISTAT_CTSWKINT_POS) + +#define LPUART_ISTAT_BUFERRINT_POS 4U +#define LPUART_ISTAT_BUFERRINT_MSK BIT(LPUART_ISTAT_BUFERRINT_POS) + +#define LPUART_ISTAT_RXTOINT_POS 3U +#define LPUART_ISTAT_RXTOINT_MSK BIT(LPUART_ISTAT_RXTOINT_POS) + +#define LPUART_ISTAT_CTSDETINT_POS 2U +#define LPUART_ISTAT_CTSDETINT_MSK BIT(LPUART_ISTAT_CTSDETINT_POS) + +#define LPUART_ISTAT_TBEMPINT_POS 1U +#define LPUART_ISTAT_TBEMPINT_MSK BIT(LPUART_ISTAT_TBEMPINT_POS) + +#define LPUART_ISTAT_RBRINT_POS 0U +#define LPUART_ISTAT_RBRINT_MSK BIT(LPUART_ISTAT_RBRINT_POS) + +/****************** Bit definition for LPUART_UPDATE register ************************/ + +#define LPUART_UPDATE_UDIS_POS 0U +#define LPUART_UPDATE_UDIS_MSK BIT(LPUART_UPDATE_UDIS_POS) + +/****************** Bit definition for LPUART_SYNCSTAT register ************************/ + +#define LPUART_SYNCSTAT_FIFOCONWBSY_POS 3U +#define LPUART_SYNCSTAT_FIFOCONWBSY_MSK BIT(LPUART_SYNCSTAT_FIFOCONWBSY_POS) + +#define LPUART_SYNCSTAT_CLKDIVWBSY_POS 2U +#define LPUART_SYNCSTAT_CLKDIVWBSY_MSK BIT(LPUART_SYNCSTAT_CLKDIVWBSY_POS) + +#define LPUART_SYNCSTAT_CON1WBSY_POS 1U +#define LPUART_SYNCSTAT_CON1WBSY_MSK BIT(LPUART_SYNCSTAT_CON1WBSY_POS) + +#define LPUART_SYNCSTAT_CON0WBSY_POS 0U +#define LPUART_SYNCSTAT_CON0WBSY_MSK BIT(LPUART_SYNCSTAT_CON0WBSY_POS) + +typedef struct +{ + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t CLKDIV; + __IO uint32_t FIFOCON; + uint32_t RESERVED0 ; + __I uint32_t RXDR; + __O uint32_t TXDR; + __I uint32_t STAT; + __IO uint32_t IER; + __I uint32_t IFLAG; + __O uint32_t IFC; + __I uint32_t ISTAT; + uint32_t RESERVED1[2] ; + __IO uint32_t UPDATE; + __I uint32_t SYNCSTAT; +} LPUART_TypeDef; + +/****************** Bit definition for SPI_CON1 register ************************/ + +#define SPI_CON1_BIDEN_POS 15U +#define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS) + +#define SPI_CON1_BIDOEN_POS 14U +#define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS) + +#define SPI_CON1_CRCEN_POS 13U +#define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS) + +#define SPI_CON1_NXTCRC_POS 12U +#define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS) + +#define SPI_CON1_FLEN_POS 11U +#define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS) + +#define SPI_CON1_RXO_POS 10U +#define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS) + +#define SPI_CON1_SSEN_POS 9U +#define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS) + +#define SPI_CON1_SSOUT_POS 8U +#define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS) + +#define SPI_CON1_LSBFST_POS 7U +#define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS) + +#define SPI_CON1_SPIEN_POS 6U +#define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS) + +#define SPI_CON1_BAUD_POSS 3U +#define SPI_CON1_BAUD_POSE 5U +#define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS,SPI_CON1_BAUD_POSE) + +#define SPI_CON1_MSTREN_POS 2U +#define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS) + +#define SPI_CON1_CPOL_POS 1U +#define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS) + +#define SPI_CON1_CPHA_POS 0U +#define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS) + +/****************** Bit definition for SPI_CON2 register ************************/ + +#define SPI_CON2_TXBEIE_POS 7U +#define SPI_CON2_TXBEIE_MSK BIT(SPI_CON2_TXBEIE_POS) + +#define SPI_CON2_RXBNEIE_POS 6U +#define SPI_CON2_RXBNEIE_MSK BIT(SPI_CON2_RXBNEIE_POS) + +#define SPI_CON2_ERRIE_POS 5U +#define SPI_CON2_ERRIE_MSK BIT(SPI_CON2_ERRIE_POS) + +#define SPI_CON2_NSSOE_POS 2U +#define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS) + +#define SPI_CON2_TXDMA_POS 1U +#define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS) + +#define SPI_CON2_RXDMA_POS 0U +#define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS) + +/****************** Bit definition for SPI_STAT register ************************/ + +#define SPI_STAT_BUSY_POS 7U +#define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS) + +#define SPI_STAT_OVERR_POS 6U +#define SPI_STAT_OVERR_MSK BIT(SPI_STAT_OVERR_POS) + +#define SPI_STAT_MODERR_POS 5U +#define SPI_STAT_MODERR_MSK BIT(SPI_STAT_MODERR_POS) + +#define SPI_STAT_CRCERR_POS 4U +#define SPI_STAT_CRCERR_MSK BIT(SPI_STAT_CRCERR_POS) + +#define SPI_STAT_TXBE_POS 1U +#define SPI_STAT_TXBE_MSK BIT(SPI_STAT_TXBE_POS) + +#define SPI_STAT_RXBNE_POS 0U +#define SPI_STAT_RXBNE_MSK BIT(SPI_STAT_RXBNE_POS) + +/****************** Bit definition for SPI_DATA register ************************/ + +#define SPI_DATA_VALUE_POSS 0U +#define SPI_DATA_VALUE_POSE 15U +#define SPI_DATA_VALUE_MSK BITS(SPI_DATA_VALUE_POSS,SPI_DATA_VALUE_POSE) + +/****************** Bit definition for SPI_CRCPOLY register ************************/ + +#define SPI_CRCPOLY_VALUE_POSS 0U +#define SPI_CRCPOLY_VALUE_POSE 15U +#define SPI_CRCPOLY_VALUE_MSK BITS(SPI_CRCPOLY_VALUE_POSS,SPI_CRCPOLY_VALUE_POSE) + +/****************** Bit definition for SPI_RXCRC register ************************/ + +#define SPI_RXCRC_CRCVAL_POSS 0U +#define SPI_RXCRC_CRCVAL_POSE 15U +#define SPI_RXCRC_CRCVAL_MSK BITS(SPI_RXCRC_CRCVAL_POSS,SPI_RXCRC_CRCVAL_POSE) + +/****************** Bit definition for SPI_TXCRC register ************************/ + +#define SPI_TXCRC_CRCVAL_POSS 0U +#define SPI_TXCRC_CRCVAL_POSE 15U +#define SPI_TXCRC_CRCVAL_MSK BITS(SPI_TXCRC_CRCVAL_POSS,SPI_TXCRC_CRCVAL_POSE) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t STAT; + __IO uint32_t DATA; + __IO uint32_t CRCPOLY; + __I uint32_t RXCRC; + __I uint32_t TXCRC; +} SPI_TypeDef; + +/****************** Bit definition for I2C_CON1 register ************************/ + +#define I2C_CON1_SRST_POS 15U +#define I2C_CON1_SRST_MSK BIT(I2C_CON1_SRST_POS) + +#define I2C_CON1_ALARM_POS 13U +#define I2C_CON1_ALARM_MSK BIT(I2C_CON1_ALARM_POS) + +#define I2C_CON1_TRPEC_POS 12U +#define I2C_CON1_TRPEC_MSK BIT(I2C_CON1_TRPEC_POS) + +#define I2C_CON1_POSAP_POS 11U +#define I2C_CON1_POSAP_MSK BIT(I2C_CON1_POSAP_POS) + +#define I2C_CON1_ACKEN_POS 10U +#define I2C_CON1_ACKEN_MSK BIT(I2C_CON1_ACKEN_POS) + +#define I2C_CON1_STOP_POS 9U +#define I2C_CON1_STOP_MSK BIT(I2C_CON1_STOP_POS) + +#define I2C_CON1_START_POS 8U +#define I2C_CON1_START_MSK BIT(I2C_CON1_START_POS) + +#define I2C_CON1_DISCS_POS 7U +#define I2C_CON1_DISCS_MSK BIT(I2C_CON1_DISCS_POS) + +#define I2C_CON1_GCEN_POS 6U +#define I2C_CON1_GCEN_MSK BIT(I2C_CON1_GCEN_POS) + +#define I2C_CON1_PECEN_POS 5U +#define I2C_CON1_PECEN_MSK BIT(I2C_CON1_PECEN_POS) + +#define I2C_CON1_ARPEN_POS 4U +#define I2C_CON1_ARPEN_MSK BIT(I2C_CON1_ARPEN_POS) + +#define I2C_CON1_SMBMOD_POS 3U +#define I2C_CON1_SMBMOD_MSK BIT(I2C_CON1_SMBMOD_POS) + +#define I2C_CON1_PMOD_POS 1U +#define I2C_CON1_PMOD_MSK BIT(I2C_CON1_PMOD_POS) + +#define I2C_CON1_PEN_POS 0U +#define I2C_CON1_PEN_MSK BIT(I2C_CON1_PEN_POS) + +/****************** Bit definition for I2C_CON2 register ************************/ + +#define I2C_CON2_LDMA_POS 12U +#define I2C_CON2_LDMA_MSK BIT(I2C_CON2_LDMA_POS) + +#define I2C_CON2_DMAEN_POS 11U +#define I2C_CON2_DMAEN_MSK BIT(I2C_CON2_DMAEN_POS) + +#define I2C_CON2_BUFIE_POS 10U +#define I2C_CON2_BUFIE_MSK BIT(I2C_CON2_BUFIE_POS) + +#define I2C_CON2_EVTIE_POS 9U +#define I2C_CON2_EVTIE_MSK BIT(I2C_CON2_EVTIE_POS) + +#define I2C_CON2_ERRIE_POS 8U +#define I2C_CON2_ERRIE_MSK BIT(I2C_CON2_ERRIE_POS) + +#define I2C_CON2_CLKF_POSS 0U +#define I2C_CON2_CLKF_POSE 5U +#define I2C_CON2_CLKF_MSK BITS(I2C_CON2_CLKF_POSS,I2C_CON2_CLKF_POSE) + +/****************** Bit definition for I2C_ADDR1 register ************************/ + +#define I2C_ADDR1_ADDTYPE_POS 15U +#define I2C_ADDR1_ADDTYPE_MSK BIT(I2C_ADDR1_ADDTYPE_POS) + +#define I2C_ADDR1_ADDH_POSS 8U +#define I2C_ADDR1_ADDH_POSE 9U +#define I2C_ADDR1_ADDH_MSK BITS(I2C_ADDR1_ADDH_POSS,I2C_ADDR1_ADDH_POSE) + +#define I2C_ADDR1_ADD_POSS 1U +#define I2C_ADDR1_ADD_POSE 7U +#define I2C_ADDR1_ADD_MSK BITS(I2C_ADDR1_ADD_POSS,I2C_ADDR1_ADD_POSE) + +#define I2C_ADDR1_ADDLSB_POS 0U +#define I2C_ADDR1_ADDLSB_MSK BIT(I2C_ADDR1_ADDLSB_POS) + +/****************** Bit definition for I2C_ADDR2 register ************************/ + +#define I2C_ADDR2_ADD_POSS 1U +#define I2C_ADDR2_ADD_POSE 7U +#define I2C_ADDR2_ADD_MSK BITS(I2C_ADDR2_ADD_POSS,I2C_ADDR2_ADD_POSE) + +#define I2C_ADDR2_DUALEN_POS 0U +#define I2C_ADDR2_DUALEN_MSK BIT(I2C_ADDR2_DUALEN_POS) + +/****************** Bit definition for I2C_DATA register ************************/ + +#define I2C_DATA_TRBUF_POSS 0U +#define I2C_DATA_TRBUF_POSE 7U +#define I2C_DATA_TRBUF_MSK BITS(I2C_DATA_TRBUF_POSS,I2C_DATA_TRBUF_POSE) + +/****************** Bit definition for I2C_STAT1 register ************************/ + +#define I2C_STAT1_SMBALARM_POS 15U +#define I2C_STAT1_SMBALARM_MSK BIT(I2C_STAT1_SMBALARM_POS) + +#define I2C_STAT1_SMBTO_POS 14U +#define I2C_STAT1_SMBTO_MSK BIT(I2C_STAT1_SMBTO_POS) + +#define I2C_STAT1_PECERR_POS 12U +#define I2C_STAT1_PECERR_MSK BIT(I2C_STAT1_PECERR_POS) + +#define I2C_STAT1_ROUERR_POS 11U +#define I2C_STAT1_ROUERR_MSK BIT(I2C_STAT1_ROUERR_POS) + +#define I2C_STAT1_ACKERR_POS 10U +#define I2C_STAT1_ACKERR_MSK BIT(I2C_STAT1_ACKERR_POS) + +#define I2C_STAT1_LARB_POS 9U +#define I2C_STAT1_LARB_MSK BIT(I2C_STAT1_LARB_POS) + +#define I2C_STAT1_BUSERR_POS 8U +#define I2C_STAT1_BUSERR_MSK BIT(I2C_STAT1_BUSERR_POS) + +#define I2C_STAT1_TXBE_POS 7U +#define I2C_STAT1_TXBE_MSK BIT(I2C_STAT1_TXBE_POS) + +#define I2C_STAT1_RXBNE_POS 6U +#define I2C_STAT1_RXBNE_MSK BIT(I2C_STAT1_RXBNE_POS) + +#define I2C_STAT1_DETSTP_POS 4U +#define I2C_STAT1_DETSTP_MSK BIT(I2C_STAT1_DETSTP_POS) + +#define I2C_STAT1_SENDADD10_POS 3U +#define I2C_STAT1_SENDADD10_MSK BIT(I2C_STAT1_SENDADD10_POS) + +#define I2C_STAT1_BTC_POS 2U +#define I2C_STAT1_BTC_MSK BIT(I2C_STAT1_BTC_POS) + +#define I2C_STAT1_ADDR_POS 1U +#define I2C_STAT1_ADDR_MSK BIT(I2C_STAT1_ADDR_POS) + +#define I2C_STAT1_SENDSTR_POS 0U +#define I2C_STAT1_SENDSTR_MSK BIT(I2C_STAT1_SENDSTR_POS) + +/****************** Bit definition for I2C_STAT2 register ************************/ + +#define I2C_STAT2_PECV_POSS 8U +#define I2C_STAT2_PECV_POSE 15U +#define I2C_STAT2_PECV_MSK BITS(I2C_STAT2_PECV_POSS,I2C_STAT2_PECV_POSE) + +#define I2C_STAT2_DMF_POS 7U +#define I2C_STAT2_DMF_MSK BIT(I2C_STAT2_DMF_POS) + +#define I2C_STAT2_SMBHH_POS 6U +#define I2C_STAT2_SMBHH_MSK BIT(I2C_STAT2_SMBHH_POS) + +#define I2C_STAT2_SMBDEF_POS 5U +#define I2C_STAT2_SMBDEF_MSK BIT(I2C_STAT2_SMBDEF_POS) + +#define I2C_STAT2_RXGCF_POS 4U +#define I2C_STAT2_RXGCF_MSK BIT(I2C_STAT2_RXGCF_POS) + +#define I2C_STAT2_TRF_POS 2U +#define I2C_STAT2_TRF_MSK BIT(I2C_STAT2_TRF_POS) + +#define I2C_STAT2_BSYF_POS 1U +#define I2C_STAT2_BSYF_MSK BIT(I2C_STAT2_BSYF_POS) + +#define I2C_STAT2_MASTER_POS 0U +#define I2C_STAT2_MASTER_MSK BIT(I2C_STAT2_MASTER_POS) + +/****************** Bit definition for I2C_CKCFG register ************************/ + +#define I2C_CKCFG_CLKMOD_POS 15U +#define I2C_CKCFG_CLKMOD_MSK BIT(I2C_CKCFG_CLKMOD_POS) + +#define I2C_CKCFG_DUTY_POS 14U +#define I2C_CKCFG_DUTY_MSK BIT(I2C_CKCFG_DUTY_POS) + +#define I2C_CKCFG_CLKSET_POSS 0U +#define I2C_CKCFG_CLKSET_POSE 11U +#define I2C_CKCFG_CLKSET_MSK BITS(I2C_CKCFG_CLKSET_POSS,I2C_CKCFG_CLKSET_POSE) + +/****************** Bit definition for I2C_RT register ************************/ + +#define I2C_RT_RISET_POSS 0U +#define I2C_RT_RISET_POSE 5U +#define I2C_RT_RISET_MSK BITS(I2C_RT_RISET_POSS,I2C_RT_RISET_POSE) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t ADDR1; + __IO uint32_t ADDR2; + __IO uint32_t DATA; + __IO uint32_t STAT1; + __I uint32_t STAT2; + __IO uint32_t CKCFG; + __IO uint32_t RT; +} I2C_TypeDef; + +/****************** Bit definition for CAN_CON register ************************/ + +#define CAN_CON_DBGSTP_POS 16U +#define CAN_CON_DBGSTP_MSK BIT(CAN_CON_DBGSTP_POS) + +#define CAN_CON_RST_POS 15U +#define CAN_CON_RST_MSK BIT(CAN_CON_RST_POS) + +#define CAN_CON_TTCEN_POS 7U +#define CAN_CON_TTCEN_MSK BIT(CAN_CON_TTCEN_POS) + +#define CAN_CON_ABOFFEN_POS 6U +#define CAN_CON_ABOFFEN_MSK BIT(CAN_CON_ABOFFEN_POS) + +#define CAN_CON_AWKEN_POS 5U +#define CAN_CON_AWKEN_MSK BIT(CAN_CON_AWKEN_POS) + +#define CAN_CON_ARTXDIS_POS 4U +#define CAN_CON_ARTXDIS_MSK BIT(CAN_CON_ARTXDIS_POS) + +#define CAN_CON_RXFOPM_POS 3U +#define CAN_CON_RXFOPM_MSK BIT(CAN_CON_RXFOPM_POS) + +#define CAN_CON_TXMP_POS 2U +#define CAN_CON_TXMP_MSK BIT(CAN_CON_TXMP_POS) + +#define CAN_CON_SLPREQ_POS 1U +#define CAN_CON_SLPREQ_MSK BIT(CAN_CON_SLPREQ_POS) + +#define CAN_CON_INIREQ_POS 0U +#define CAN_CON_INIREQ_MSK BIT(CAN_CON_INIREQ_POS) + +/****************** Bit definition for CAN_STAT register ************************/ + +#define CAN_STAT_RX_POS 11U +#define CAN_STAT_RX_MSK BIT(CAN_STAT_RX_POS) + +#define CAN_STAT_PRESMP_POS 10U +#define CAN_STAT_PRESMP_MSK BIT(CAN_STAT_PRESMP_POS) + +#define CAN_STAT_RXSTAT_POS 9U +#define CAN_STAT_RXSTAT_MSK BIT(CAN_STAT_RXSTAT_POS) + +#define CAN_STAT_TXSTAT_POS 8U +#define CAN_STAT_TXSTAT_MSK BIT(CAN_STAT_TXSTAT_POS) + +#define CAN_STAT_SLPIF_POS 4U +#define CAN_STAT_SLPIF_MSK BIT(CAN_STAT_SLPIF_POS) + +#define CAN_STAT_WKIF_POS 3U +#define CAN_STAT_WKIF_MSK BIT(CAN_STAT_WKIF_POS) + +#define CAN_STAT_ERRIF_POS 2U +#define CAN_STAT_ERRIF_MSK BIT(CAN_STAT_ERRIF_POS) + +#define CAN_STAT_SLPSTAT_POS 1U +#define CAN_STAT_SLPSTAT_MSK BIT(CAN_STAT_SLPSTAT_POS) + +#define CAN_STAT_INISTAT_POS 0U +#define CAN_STAT_INISTAT_MSK BIT(CAN_STAT_INISTAT_POS) + +/****************** Bit definition for CAN_IFC register ************************/ + +#define CAN_IFC_SLPIFC_POS 4U +#define CAN_IFC_SLPIFC_MSK BIT(CAN_IFC_SLPIFC_POS) + +#define CAN_IFC_WKIFC_POS 3U +#define CAN_IFC_WKIFC_MSK BIT(CAN_IFC_WKIFC_POS) + +#define CAN_IFC_ERRIFC_POS 2U +#define CAN_IFC_ERRIFC_MSK BIT(CAN_IFC_ERRIFC_POS) + +/****************** Bit definition for CAN_TXSTAT register ************************/ + +#define CAN_TXSTAT_TXM2LPF_POS 31U +#define CAN_TXSTAT_TXM2LPF_MSK BIT(CAN_TXSTAT_TXM2LPF_POS) + +#define CAN_TXSTAT_TXM1LPF_POS 30U +#define CAN_TXSTAT_TXM1LPF_MSK BIT(CAN_TXSTAT_TXM1LPF_POS) + +#define CAN_TXSTAT_TXM0LPF_POS 29U +#define CAN_TXSTAT_TXM0LPF_MSK BIT(CAN_TXSTAT_TXM0LPF_POS) + +#define CAN_TXSTAT_TXM2EF_POS 28U +#define CAN_TXSTAT_TXM2EF_MSK BIT(CAN_TXSTAT_TXM2EF_POS) + +#define CAN_TXSTAT_TXM1EF_POS 27U +#define CAN_TXSTAT_TXM1EF_MSK BIT(CAN_TXSTAT_TXM1EF_POS) + +#define CAN_TXSTAT_TXM0EF_POS 26U +#define CAN_TXSTAT_TXM0EF_MSK BIT(CAN_TXSTAT_TXM0EF_POS) + +#define CAN_TXSTAT_CODE_POSS 24U +#define CAN_TXSTAT_CODE_POSE 25U +#define CAN_TXSTAT_CODE_MSK BITS(CAN_TXSTAT_CODE_POSS,CAN_TXSTAT_CODE_POSE) + +#define CAN_TXSTAT_M2STPREQ_POS 23U +#define CAN_TXSTAT_M2STPREQ_MSK BIT(CAN_TXSTAT_M2STPREQ_POS) + +#define CAN_TXSTAT_M2TXERR_POS 19U +#define CAN_TXSTAT_M2TXERR_MSK BIT(CAN_TXSTAT_M2TXERR_POS) + +#define CAN_TXSTAT_M2ARBLST_POS 18U +#define CAN_TXSTAT_M2ARBLST_MSK BIT(CAN_TXSTAT_M2ARBLST_POS) + +#define CAN_TXSTAT_M2TXC_POS 17U +#define CAN_TXSTAT_M2TXC_MSK BIT(CAN_TXSTAT_M2TXC_POS) + +#define CAN_TXSTAT_M2REQC_POS 16U +#define CAN_TXSTAT_M2REQC_MSK BIT(CAN_TXSTAT_M2REQC_POS) + +#define CAN_TXSTAT_M1STPREQ_POS 15U +#define CAN_TXSTAT_M1STPREQ_MSK BIT(CAN_TXSTAT_M1STPREQ_POS) + +#define CAN_TXSTAT_M1TXERR_POS 11U +#define CAN_TXSTAT_M1TXERR_MSK BIT(CAN_TXSTAT_M1TXERR_POS) + +#define CAN_TXSTAT_M1ARBLST_POS 10U +#define CAN_TXSTAT_M1ARBLST_MSK BIT(CAN_TXSTAT_M1ARBLST_POS) + +#define CAN_TXSTAT_M1TXC_POS 9U +#define CAN_TXSTAT_M1TXC_MSK BIT(CAN_TXSTAT_M1TXC_POS) + +#define CAN_TXSTAT_M1REQC_POS 8U +#define CAN_TXSTAT_M1REQC_MSK BIT(CAN_TXSTAT_M1REQC_POS) + +#define CAN_TXSTAT_M0STPREQ_POS 7U +#define CAN_TXSTAT_M0STPREQ_MSK BIT(CAN_TXSTAT_M0STPREQ_POS) + +#define CAN_TXSTAT_M0TXERR_POS 3U +#define CAN_TXSTAT_M0TXERR_MSK BIT(CAN_TXSTAT_M0TXERR_POS) + +#define CAN_TXSTAT_M0ARBLST_POS 2U +#define CAN_TXSTAT_M0ARBLST_MSK BIT(CAN_TXSTAT_M0ARBLST_POS) + +#define CAN_TXSTAT_M0TXC_POS 1U +#define CAN_TXSTAT_M0TXC_MSK BIT(CAN_TXSTAT_M0TXC_POS) + +#define CAN_TXSTAT_M0REQC_POS 0U +#define CAN_TXSTAT_M0REQC_MSK BIT(CAN_TXSTAT_M0REQC_POS) + +/****************** Bit definition for CAN_TXSTATC register ************************/ + +#define CAN_TXSTATC_M2TXERR_POS 19U +#define CAN_TXSTATC_M2TXERR_MSK BIT(CAN_TXSTATC_M2TXERR_POS) + +#define CAN_TXSTATC_M2ARBLST_POS 18U +#define CAN_TXSTATC_M2ARBLST_MSK BIT(CAN_TXSTATC_M2ARBLST_POS) + +#define CAN_TXSTATC_M2TXC_POS 17U +#define CAN_TXSTATC_M2TXC_MSK BIT(CAN_TXSTATC_M2TXC_POS) + +#define CAN_TXSTATC_M2REQC_POS 16U +#define CAN_TXSTATC_M2REQC_MSK BIT(CAN_TXSTATC_M2REQC_POS) + +#define CAN_TXSTATC_M1TXERR_POS 11U +#define CAN_TXSTATC_M1TXERR_MSK BIT(CAN_TXSTATC_M1TXERR_POS) + +#define CAN_TXSTATC_M1ARBLST_POS 10U +#define CAN_TXSTATC_M1ARBLST_MSK BIT(CAN_TXSTATC_M1ARBLST_POS) + +#define CAN_TXSTATC_M1TXC_POS 9U +#define CAN_TXSTATC_M1TXC_MSK BIT(CAN_TXSTATC_M1TXC_POS) + +#define CAN_TXSTATC_M1REQC_POS 8U +#define CAN_TXSTATC_M1REQC_MSK BIT(CAN_TXSTATC_M1REQC_POS) + +#define CAN_TXSTATC_M0TXERR_POS 3U +#define CAN_TXSTATC_M0TXERR_MSK BIT(CAN_TXSTATC_M0TXERR_POS) + +#define CAN_TXSTATC_M0ARBLST_POS 2U +#define CAN_TXSTATC_M0ARBLST_MSK BIT(CAN_TXSTATC_M0ARBLST_POS) + +#define CAN_TXSTATC_M0TXC_POS 1U +#define CAN_TXSTATC_M0TXC_MSK BIT(CAN_TXSTATC_M0TXC_POS) + +#define CAN_TXSTATC_M0REQC_POS 0U +#define CAN_TXSTATC_M0REQC_MSK BIT(CAN_TXSTATC_M0REQC_POS) + +/****************** Bit definition for CAN_RXF0 register ************************/ + +#define CAN_RXF0_FREE_POS 5U +#define CAN_RXF0_FREE_MSK BIT(CAN_RXF0_FREE_POS) + +#define CAN_RXF0_OVR_POS 4U +#define CAN_RXF0_OVR_MSK BIT(CAN_RXF0_OVR_POS) + +#define CAN_RXF0_FULL_POS 3U +#define CAN_RXF0_FULL_MSK BIT(CAN_RXF0_FULL_POS) + +#define CAN_RXF0_PEND_POSS 0U +#define CAN_RXF0_PEND_POSE 1U +#define CAN_RXF0_PEND_MSK BITS(CAN_RXF0_PEND_POSS,CAN_RXF0_PEND_POSE) + +/****************** Bit definition for CAN_RXF0C register ************************/ + +#define CAN_RXF0C_OVRC_POS 4U +#define CAN_RXF0C_OVRC_MSK BIT(CAN_RXF0C_OVRC_POS) + +#define CAN_RXF0C_FULLC_POS 3U +#define CAN_RXF0C_FULLC_MSK BIT(CAN_RXF0C_FULLC_POS) + +/****************** Bit definition for CAN_RXF1 register ************************/ + +#define CAN_RXF1_FREE_POS 5U +#define CAN_RXF1_FREE_MSK BIT(CAN_RXF1_FREE_POS) + +#define CAN_RXF1_OVR_POS 4U +#define CAN_RXF1_OVR_MSK BIT(CAN_RXF1_OVR_POS) + +#define CAN_RXF1_FULL_POS 3U +#define CAN_RXF1_FULL_MSK BIT(CAN_RXF1_FULL_POS) + +#define CAN_RXF1_PEND_POSS 0U +#define CAN_RXF1_PEND_POSE 1U +#define CAN_RXF1_PEND_MSK BITS(CAN_RXF1_PEND_POSS,CAN_RXF1_PEND_POSE) + +/****************** Bit definition for CAN_RXF1C register ************************/ + +#define CAN_RXF1C_OVRC_POS 4U +#define CAN_RXF1C_OVRC_MSK BIT(CAN_RXF1C_OVRC_POS) + +#define CAN_RXF1C_FULLC_POS 3U +#define CAN_RXF1C_FULLC_MSK BIT(CAN_RXF1C_FULLC_POS) + +/****************** Bit definition for CAN_IE register ************************/ + +#define CAN_IE_SLPIE_POS 17U +#define CAN_IE_SLPIE_MSK BIT(CAN_IE_SLPIE_POS) + +#define CAN_IE_WKIE_POS 16U +#define CAN_IE_WKIE_MSK BIT(CAN_IE_WKIE_POS) + +#define CAN_IE_ERRIE_POS 15U +#define CAN_IE_ERRIE_MSK BIT(CAN_IE_ERRIE_POS) + +#define CAN_IE_PRERRIE_POS 11U +#define CAN_IE_PRERRIE_MSK BIT(CAN_IE_PRERRIE_POS) + +#define CAN_IE_BOFFIE_POS 10U +#define CAN_IE_BOFFIE_MSK BIT(CAN_IE_BOFFIE_POS) + +#define CAN_IE_PERRIE_POS 9U +#define CAN_IE_PERRIE_MSK BIT(CAN_IE_PERRIE_POS) + +#define CAN_IE_WARNIE_POS 8U +#define CAN_IE_WARNIE_MSK BIT(CAN_IE_WARNIE_POS) + +#define CAN_IE_F1OVRIE_POS 6U +#define CAN_IE_F1OVRIE_MSK BIT(CAN_IE_F1OVRIE_POS) + +#define CAN_IE_F1FULIE_POS 5U +#define CAN_IE_F1FULIE_MSK BIT(CAN_IE_F1FULIE_POS) + +#define CAN_IE_F1PIE_POS 4U +#define CAN_IE_F1PIE_MSK BIT(CAN_IE_F1PIE_POS) + +#define CAN_IE_F0OVRIE_POS 3U +#define CAN_IE_F0OVRIE_MSK BIT(CAN_IE_F0OVRIE_POS) + +#define CAN_IE_F0FULIE_POS 2U +#define CAN_IE_F0FULIE_MSK BIT(CAN_IE_F0FULIE_POS) + +#define CAN_IE_F0PIE_POS 1U +#define CAN_IE_F0PIE_MSK BIT(CAN_IE_F0PIE_POS) + +#define CAN_IE_TXMEIE_POS 0U +#define CAN_IE_TXMEIE_MSK BIT(CAN_IE_TXMEIE_POS) + +/****************** Bit definition for CAN_ERRSTAT register ************************/ + +#define CAN_ERRSTAT_RXERRC_POSS 24U +#define CAN_ERRSTAT_RXERRC_POSE 31U +#define CAN_ERRSTAT_RXERRC_MSK BITS(CAN_ERRSTAT_RXERRC_POSS,CAN_ERRSTAT_RXERRC_POSE) + +#define CAN_ERRSTAT_TXERRC_POSS 16U +#define CAN_ERRSTAT_TXERRC_POSE 23U +#define CAN_ERRSTAT_TXERRC_MSK BITS(CAN_ERRSTAT_TXERRC_POSS,CAN_ERRSTAT_TXERRC_POSE) + +#define CAN_ERRSTAT_PRERRF_POSS 4U +#define CAN_ERRSTAT_PRERRF_POSE 6U +#define CAN_ERRSTAT_PRERRF_MSK BITS(CAN_ERRSTAT_PRERRF_POSS,CAN_ERRSTAT_PRERRF_POSE) + +#define CAN_ERRSTAT_BOFF_POS 2U +#define CAN_ERRSTAT_BOFF_MSK BIT(CAN_ERRSTAT_BOFF_POS) + +#define CAN_ERRSTAT_PERRF_POS 1U +#define CAN_ERRSTAT_PERRF_MSK BIT(CAN_ERRSTAT_PERRF_POS) + +#define CAN_ERRSTAT_WARNF_POS 0U +#define CAN_ERRSTAT_WARNF_MSK BIT(CAN_ERRSTAT_WARNF_POS) + +/****************** Bit definition for CAN_BTIME register ************************/ + +#define CAN_BTIME_SILENT_POS 31U +#define CAN_BTIME_SILENT_MSK BIT(CAN_BTIME_SILENT_POS) + +#define CAN_BTIME_LOOP_POS 30U +#define CAN_BTIME_LOOP_MSK BIT(CAN_BTIME_LOOP_POS) + +#define CAN_BTIME_RESJW_POSS 24U +#define CAN_BTIME_RESJW_POSE 25U +#define CAN_BTIME_RESJW_MSK BITS(CAN_BTIME_RESJW_POSS,CAN_BTIME_RESJW_POSE) + +#define CAN_BTIME_SEG2_POSS 20U +#define CAN_BTIME_SEG2_POSE 22U +#define CAN_BTIME_SEG2_MSK BITS(CAN_BTIME_SEG2_POSS,CAN_BTIME_SEG2_POSE) + +#define CAN_BTIME_SEG1_POSS 16U +#define CAN_BTIME_SEG1_POSE 19U +#define CAN_BTIME_SEG1_MSK BITS(CAN_BTIME_SEG1_POSS,CAN_BTIME_SEG1_POSE) + +#define CAN_BTIME_BPSC_POSS 0U +#define CAN_BTIME_BPSC_POSE 9U +#define CAN_BTIME_BPSC_MSK BITS(CAN_BTIME_BPSC_POSS,CAN_BTIME_BPSC_POSE) + +/****************** Bit definition for CAN_TXID0 register ************************/ + +#define CAN_TXID0_STDID_POSS 21U +#define CAN_TXID0_STDID_POSE 31U +#define CAN_TXID0_STDID_MSK BITS(CAN_TXID0_STDID_POSS,CAN_TXID0_STDID_POSE) + +#define CAN_TXID0_EXID_POSS 3U +#define CAN_TXID0_EXID_POSE 20U +#define CAN_TXID0_EXID_MSK BITS(CAN_TXID0_EXID_POSS,CAN_TXID0_EXID_POSE) + +#define CAN_TXID0_IDE_POS 2U +#define CAN_TXID0_IDE_MSK BIT(CAN_TXID0_IDE_POS) + +#define CAN_TXID0_RTR_POS 1U +#define CAN_TXID0_RTR_MSK BIT(CAN_TXID0_RTR_POS) + +#define CAN_TXID0_TXMREQ_POS 0U +#define CAN_TXID0_TXMREQ_MSK BIT(CAN_TXID0_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON0 register ************************/ + +#define CAN_TXFCON0_STAMP_POSS 16U +#define CAN_TXFCON0_STAMP_POSE 31U +#define CAN_TXFCON0_STAMP_MSK BITS(CAN_TXFCON0_STAMP_POSS,CAN_TXFCON0_STAMP_POSE) + +#define CAN_TXFCON0_TXGT_POS 8U +#define CAN_TXFCON0_TXGT_MSK BIT(CAN_TXFCON0_TXGT_POS) + +#define CAN_TXFCON0_DLEN_POSS 0U +#define CAN_TXFCON0_DLEN_POSE 3U +#define CAN_TXFCON0_DLEN_MSK BITS(CAN_TXFCON0_DLEN_POSS,CAN_TXFCON0_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL0 register ************************/ + +#define CAN_TXDL0_BYTE3_POSS 24U +#define CAN_TXDL0_BYTE3_POSE 31U +#define CAN_TXDL0_BYTE3_MSK BITS(CAN_TXDL0_BYTE3_POSS,CAN_TXDL0_BYTE3_POSE) + +#define CAN_TXDL0_BYTE2_POSS 16U +#define CAN_TXDL0_BYTE2_POSE 23U +#define CAN_TXDL0_BYTE2_MSK BITS(CAN_TXDL0_BYTE2_POSS,CAN_TXDL0_BYTE2_POSE) + +#define CAN_TXDL0_BYTE1_POSS 8U +#define CAN_TXDL0_BYTE1_POSE 15U +#define CAN_TXDL0_BYTE1_MSK BITS(CAN_TXDL0_BYTE1_POSS,CAN_TXDL0_BYTE1_POSE) + +#define CAN_TXDL0_BYTE0_POSS 0U +#define CAN_TXDL0_BYTE0_POSE 7U +#define CAN_TXDL0_BYTE0_MSK BITS(CAN_TXDL0_BYTE0_POSS,CAN_TXDL0_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH0 register ************************/ + +#define CAN_TXDH0_BYTE7_POSS 24U +#define CAN_TXDH0_BYTE7_POSE 31U +#define CAN_TXDH0_BYTE7_MSK BITS(CAN_TXDH0_BYTE7_POSS,CAN_TXDH0_BYTE7_POSE) + +#define CAN_TXDH0_BYTE6_POSS 16U +#define CAN_TXDH0_BYTE6_POSE 23U +#define CAN_TXDH0_BYTE6_MSK BITS(CAN_TXDH0_BYTE6_POSS,CAN_TXDH0_BYTE6_POSE) + +#define CAN_TXDH0_BYTE5_POSS 8U +#define CAN_TXDH0_BYTE5_POSE 15U +#define CAN_TXDH0_BYTE5_MSK BITS(CAN_TXDH0_BYTE5_POSS,CAN_TXDH0_BYTE5_POSE) + +#define CAN_TXDH0_BYTE4_POSS 0U +#define CAN_TXDH0_BYTE4_POSE 7U +#define CAN_TXDH0_BYTE4_MSK BITS(CAN_TXDH0_BYTE4_POSS,CAN_TXDH0_BYTE4_POSE) + +/****************** Bit definition for CAN_TXID1 register ************************/ + +#define CAN_TXID1_STDID_POSS 21U +#define CAN_TXID1_STDID_POSE 31U +#define CAN_TXID1_STDID_MSK BITS(CAN_TXID1_STDID_POSS,CAN_TXID1_STDID_POSE) + +#define CAN_TXID1_EXID_POSS 3U +#define CAN_TXID1_EXID_POSE 20U +#define CAN_TXID1_EXID_MSK BITS(CAN_TXID1_EXID_POSS,CAN_TXID1_EXID_POSE) + +#define CAN_TXID1_IDE_POS 2U +#define CAN_TXID1_IDE_MSK BIT(CAN_TXID1_IDE_POS) + +#define CAN_TXID1_RTR_POS 1U +#define CAN_TXID1_RTR_MSK BIT(CAN_TXID1_RTR_POS) + +#define CAN_TXID1_TXMREQ_POS 0U +#define CAN_TXID1_TXMREQ_MSK BIT(CAN_TXID1_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON1 register ************************/ + +#define CAN_TXFCON1_STAMP_POSS 16U +#define CAN_TXFCON1_STAMP_POSE 31U +#define CAN_TXFCON1_STAMP_MSK BITS(CAN_TXFCON1_STAMP_POSS,CAN_TXFCON1_STAMP_POSE) + +#define CAN_TXFCON1_TXGT_POS 8U +#define CAN_TXFCON1_TXGT_MSK BIT(CAN_TXFCON1_TXGT_POS) + +#define CAN_TXFCON1_DLEN_POSS 0U +#define CAN_TXFCON1_DLEN_POSE 3U +#define CAN_TXFCON1_DLEN_MSK BITS(CAN_TXFCON1_DLEN_POSS,CAN_TXFCON1_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL1 register ************************/ + +#define CAN_TXDL1_BYTE3_POSS 24U +#define CAN_TXDL1_BYTE3_POSE 31U +#define CAN_TXDL1_BYTE3_MSK BITS(CAN_TXDL1_BYTE3_POSS,CAN_TXDL1_BYTE3_POSE) + +#define CAN_TXDL1_BYTE2_POSS 16U +#define CAN_TXDL1_BYTE2_POSE 23U +#define CAN_TXDL1_BYTE2_MSK BITS(CAN_TXDL1_BYTE2_POSS,CAN_TXDL1_BYTE2_POSE) + +#define CAN_TXDL1_BYTE1_POSS 8U +#define CAN_TXDL1_BYTE1_POSE 15U +#define CAN_TXDL1_BYTE1_MSK BITS(CAN_TXDL1_BYTE1_POSS,CAN_TXDL1_BYTE1_POSE) + +#define CAN_TXDL1_BYTE0_POSS 0U +#define CAN_TXDL1_BYTE0_POSE 7U +#define CAN_TXDL1_BYTE0_MSK BITS(CAN_TXDL1_BYTE0_POSS,CAN_TXDL1_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH1 register ************************/ + +#define CAN_TXDH1_BYTE7_POSS 24U +#define CAN_TXDH1_BYTE7_POSE 31U +#define CAN_TXDH1_BYTE7_MSK BITS(CAN_TXDH1_BYTE7_POSS,CAN_TXDH1_BYTE7_POSE) + +#define CAN_TXDH1_BYTE6_POSS 16U +#define CAN_TXDH1_BYTE6_POSE 23U +#define CAN_TXDH1_BYTE6_MSK BITS(CAN_TXDH1_BYTE6_POSS,CAN_TXDH1_BYTE6_POSE) + +#define CAN_TXDH1_BYTE5_POSS 8U +#define CAN_TXDH1_BYTE5_POSE 15U +#define CAN_TXDH1_BYTE5_MSK BITS(CAN_TXDH1_BYTE5_POSS,CAN_TXDH1_BYTE5_POSE) + +#define CAN_TXDH1_BYTE4_POSS 0U +#define CAN_TXDH1_BYTE4_POSE 7U +#define CAN_TXDH1_BYTE4_MSK BITS(CAN_TXDH1_BYTE4_POSS,CAN_TXDH1_BYTE4_POSE) + +/****************** Bit definition for CAN_TXID2 register ************************/ + +#define CAN_TXID2_STDID_POSS 21U +#define CAN_TXID2_STDID_POSE 31U +#define CAN_TXID2_STDID_MSK BITS(CAN_TXID2_STDID_POSS,CAN_TXID2_STDID_POSE) + +#define CAN_TXID2_EXID_POSS 3U +#define CAN_TXID2_EXID_POSE 20U +#define CAN_TXID2_EXID_MSK BITS(CAN_TXID2_EXID_POSS,CAN_TXID2_EXID_POSE) + +#define CAN_TXID2_IDE_POS 2U +#define CAN_TXID2_IDE_MSK BIT(CAN_TXID2_IDE_POS) + +#define CAN_TXID2_RTR_POS 1U +#define CAN_TXID2_RTR_MSK BIT(CAN_TXID2_RTR_POS) + +#define CAN_TXID2_TXMREQ_POS 0U +#define CAN_TXID2_TXMREQ_MSK BIT(CAN_TXID2_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON2 register ************************/ + +#define CAN_TXFCON2_STAMP_POSS 16U +#define CAN_TXFCON2_STAMP_POSE 31U +#define CAN_TXFCON2_STAMP_MSK BITS(CAN_TXFCON2_STAMP_POSS,CAN_TXFCON2_STAMP_POSE) + +#define CAN_TXFCON2_TXGT_POS 8U +#define CAN_TXFCON2_TXGT_MSK BIT(CAN_TXFCON2_TXGT_POS) + +#define CAN_TXFCON2_DLEN_POSS 0U +#define CAN_TXFCON2_DLEN_POSE 3U +#define CAN_TXFCON2_DLEN_MSK BITS(CAN_TXFCON2_DLEN_POSS,CAN_TXFCON2_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL2 register ************************/ + +#define CAN_TXDL2_BYTE3_POSS 24U +#define CAN_TXDL2_BYTE3_POSE 31U +#define CAN_TXDL2_BYTE3_MSK BITS(CAN_TXDL2_BYTE3_POSS,CAN_TXDL2_BYTE3_POSE) + +#define CAN_TXDL2_BYTE2_POSS 16U +#define CAN_TXDL2_BYTE2_POSE 23U +#define CAN_TXDL2_BYTE2_MSK BITS(CAN_TXDL2_BYTE2_POSS,CAN_TXDL2_BYTE2_POSE) + +#define CAN_TXDL2_BYTE1_POSS 8U +#define CAN_TXDL2_BYTE1_POSE 15U +#define CAN_TXDL2_BYTE1_MSK BITS(CAN_TXDL2_BYTE1_POSS,CAN_TXDL2_BYTE1_POSE) + +#define CAN_TXDL2_BYTE0_POSS 0U +#define CAN_TXDL2_BYTE0_POSE 7U +#define CAN_TXDL2_BYTE0_MSK BITS(CAN_TXDL2_BYTE0_POSS,CAN_TXDL2_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH2 register ************************/ + +#define CAN_TXDH2_BYTE7_POSS 24U +#define CAN_TXDH2_BYTE7_POSE 31U +#define CAN_TXDH2_BYTE7_MSK BITS(CAN_TXDH2_BYTE7_POSS,CAN_TXDH2_BYTE7_POSE) + +#define CAN_TXDH2_BYTE6_POSS 16U +#define CAN_TXDH2_BYTE6_POSE 23U +#define CAN_TXDH2_BYTE6_MSK BITS(CAN_TXDH2_BYTE6_POSS,CAN_TXDH2_BYTE6_POSE) + +#define CAN_TXDH2_BYTE5_POSS 8U +#define CAN_TXDH2_BYTE5_POSE 15U +#define CAN_TXDH2_BYTE5_MSK BITS(CAN_TXDH2_BYTE5_POSS,CAN_TXDH2_BYTE5_POSE) + +#define CAN_TXDH2_BYTE4_POSS 0U +#define CAN_TXDH2_BYTE4_POSE 7U +#define CAN_TXDH2_BYTE4_MSK BITS(CAN_TXDH2_BYTE4_POSS,CAN_TXDH2_BYTE4_POSE) + +/****************** Bit definition for CAN_RXF0ID register ************************/ + +#define CAN_RXF0ID_STDID_POSS 21U +#define CAN_RXF0ID_STDID_POSE 31U +#define CAN_RXF0ID_STDID_MSK BITS(CAN_RXF0ID_STDID_POSS,CAN_RXF0ID_STDID_POSE) + +#define CAN_RXF0ID_EXID_POSS 3U +#define CAN_RXF0ID_EXID_POSE 20U +#define CAN_RXF0ID_EXID_MSK BITS(CAN_RXF0ID_EXID_POSS,CAN_RXF0ID_EXID_POSE) + +#define CAN_RXF0ID_IDE_POS 2U +#define CAN_RXF0ID_IDE_MSK BIT(CAN_RXF0ID_IDE_POS) + +#define CAN_RXF0ID_RTR_POS 1U +#define CAN_RXF0ID_RTR_MSK BIT(CAN_RXF0ID_RTR_POS) + +/****************** Bit definition for CAN_RXF0INF register ************************/ + +#define CAN_RXF0INF_STAMP_POSS 16U +#define CAN_RXF0INF_STAMP_POSE 31U +#define CAN_RXF0INF_STAMP_MSK BITS(CAN_RXF0INF_STAMP_POSS,CAN_RXF0INF_STAMP_POSE) + +#define CAN_RXF0INF_FLTIDX_POSS 8U +#define CAN_RXF0INF_FLTIDX_POSE 15U +#define CAN_RXF0INF_FLTIDX_MSK BITS(CAN_RXF0INF_FLTIDX_POSS,CAN_RXF0INF_FLTIDX_POSE) + +#define CAN_RXF0INF_DLEN_POSS 0U +#define CAN_RXF0INF_DLEN_POSE 3U +#define CAN_RXF0INF_DLEN_MSK BITS(CAN_RXF0INF_DLEN_POSS,CAN_RXF0INF_DLEN_POSE) + +/****************** Bit definition for CAN_RXF0DL register ************************/ + +#define CAN_RXF0DL_BYTE3_POSS 24U +#define CAN_RXF0DL_BYTE3_POSE 31U +#define CAN_RXF0DL_BYTE3_MSK BITS(CAN_RXF0DL_BYTE3_POSS,CAN_RXF0DL_BYTE3_POSE) + +#define CAN_RXF0DL_BYTE2_POSS 16U +#define CAN_RXF0DL_BYTE2_POSE 23U +#define CAN_RXF0DL_BYTE2_MSK BITS(CAN_RXF0DL_BYTE2_POSS,CAN_RXF0DL_BYTE2_POSE) + +#define CAN_RXF0DL_BYTE1_POSS 8U +#define CAN_RXF0DL_BYTE1_POSE 15U +#define CAN_RXF0DL_BYTE1_MSK BITS(CAN_RXF0DL_BYTE1_POSS,CAN_RXF0DL_BYTE1_POSE) + +#define CAN_RXF0DL_BYTE0_POSS 0U +#define CAN_RXF0DL_BYTE0_POSE 7U +#define CAN_RXF0DL_BYTE0_MSK BITS(CAN_RXF0DL_BYTE0_POSS,CAN_RXF0DL_BYTE0_POSE) + +/****************** Bit definition for CAN_RXF0DH register ************************/ + +#define CAN_RXF0DH_BYTE7_POSS 24U +#define CAN_RXF0DH_BYTE7_POSE 31U +#define CAN_RXF0DH_BYTE7_MSK BITS(CAN_RXF0DH_BYTE7_POSS,CAN_RXF0DH_BYTE7_POSE) + +#define CAN_RXF0DH_BYTE6_POSS 16U +#define CAN_RXF0DH_BYTE6_POSE 23U +#define CAN_RXF0DH_BYTE6_MSK BITS(CAN_RXF0DH_BYTE6_POSS,CAN_RXF0DH_BYTE6_POSE) + +#define CAN_RXF0DH_BYTE5_POSS 8U +#define CAN_RXF0DH_BYTE5_POSE 15U +#define CAN_RXF0DH_BYTE5_MSK BITS(CAN_RXF0DH_BYTE5_POSS,CAN_RXF0DH_BYTE5_POSE) + +#define CAN_RXF0DH_BYTE4_POSS 0U +#define CAN_RXF0DH_BYTE4_POSE 7U +#define CAN_RXF0DH_BYTE4_MSK BITS(CAN_RXF0DH_BYTE4_POSS,CAN_RXF0DH_BYTE4_POSE) + +/****************** Bit definition for CAN_RXF1ID register ************************/ + +#define CAN_RXF1ID_STDID_POSS 21U +#define CAN_RXF1ID_STDID_POSE 31U +#define CAN_RXF1ID_STDID_MSK BITS(CAN_RXF1ID_STDID_POSS,CAN_RXF1ID_STDID_POSE) + +#define CAN_RXF1ID_EXID_POSS 3U +#define CAN_RXF1ID_EXID_POSE 20U +#define CAN_RXF1ID_EXID_MSK BITS(CAN_RXF1ID_EXID_POSS,CAN_RXF1ID_EXID_POSE) + +#define CAN_RXF1ID_IDE_POS 2U +#define CAN_RXF1ID_IDE_MSK BIT(CAN_RXF1ID_IDE_POS) + +#define CAN_RXF1ID_RTR_POS 1U +#define CAN_RXF1ID_RTR_MSK BIT(CAN_RXF1ID_RTR_POS) + +/****************** Bit definition for CAN_RXF1INF register ************************/ + +#define CAN_RXF1INF_STAMP_POSS 16U +#define CAN_RXF1INF_STAMP_POSE 31U +#define CAN_RXF1INF_STAMP_MSK BITS(CAN_RXF1INF_STAMP_POSS,CAN_RXF1INF_STAMP_POSE) + +#define CAN_RXF1INF_FLTIDX_POSS 8U +#define CAN_RXF1INF_FLTIDX_POSE 15U +#define CAN_RXF1INF_FLTIDX_MSK BITS(CAN_RXF1INF_FLTIDX_POSS,CAN_RXF1INF_FLTIDX_POSE) + +#define CAN_RXF1INF_DLEN_POSS 0U +#define CAN_RXF1INF_DLEN_POSE 3U +#define CAN_RXF1INF_DLEN_MSK BITS(CAN_RXF1INF_DLEN_POSS,CAN_RXF1INF_DLEN_POSE) + +/****************** Bit definition for CAN_RXF1DL register ************************/ + +#define CAN_RXF1DL_BYTE3_POSS 24U +#define CAN_RXF1DL_BYTE3_POSE 31U +#define CAN_RXF1DL_BYTE3_MSK BITS(CAN_RXF1DL_BYTE3_POSS,CAN_RXF1DL_BYTE3_POSE) + +#define CAN_RXF1DL_BYTE2_POSS 16U +#define CAN_RXF1DL_BYTE2_POSE 23U +#define CAN_RXF1DL_BYTE2_MSK BITS(CAN_RXF1DL_BYTE2_POSS,CAN_RXF1DL_BYTE2_POSE) + +#define CAN_RXF1DL_BYTE1_POSS 8U +#define CAN_RXF1DL_BYTE1_POSE 15U +#define CAN_RXF1DL_BYTE1_MSK BITS(CAN_RXF1DL_BYTE1_POSS,CAN_RXF1DL_BYTE1_POSE) + +#define CAN_RXF1DL_BYTE0_POSS 0U +#define CAN_RXF1DL_BYTE0_POSE 7U +#define CAN_RXF1DL_BYTE0_MSK BITS(CAN_RXF1DL_BYTE0_POSS,CAN_RXF1DL_BYTE0_POSE) + +/****************** Bit definition for CAN_RXF1DH register ************************/ + +#define CAN_RXF1DH_BYTE7_POSS 24U +#define CAN_RXF1DH_BYTE7_POSE 31U +#define CAN_RXF1DH_BYTE7_MSK BITS(CAN_RXF1DH_BYTE7_POSS,CAN_RXF1DH_BYTE7_POSE) + +#define CAN_RXF1DH_BYTE6_POSS 16U +#define CAN_RXF1DH_BYTE6_POSE 23U +#define CAN_RXF1DH_BYTE6_MSK BITS(CAN_RXF1DH_BYTE6_POSS,CAN_RXF1DH_BYTE6_POSE) + +#define CAN_RXF1DH_BYTE5_POSS 8U +#define CAN_RXF1DH_BYTE5_POSE 15U +#define CAN_RXF1DH_BYTE5_MSK BITS(CAN_RXF1DH_BYTE5_POSS,CAN_RXF1DH_BYTE5_POSE) + +#define CAN_RXF1DH_BYTE4_POSS 0U +#define CAN_RXF1DH_BYTE4_POSE 7U +#define CAN_RXF1DH_BYTE4_MSK BITS(CAN_RXF1DH_BYTE4_POSS,CAN_RXF1DH_BYTE4_POSE) + +/****************** Bit definition for CAN_FLTCON register ************************/ + +#define CAN_FLTCON_FLTINI_POS 0U +#define CAN_FLTCON_FLTINI_MSK BIT(CAN_FLTCON_FLTINI_POS) + +/****************** Bit definition for CAN_FLTM register ************************/ + +#define CAN_FLTM_MOD_POSS 0U +#define CAN_FLTM_MOD_POSE 13U +#define CAN_FLTM_MOD_MSK BITS(CAN_FLTM_MOD_POSS,CAN_FLTM_MOD_POSE) + +/****************** Bit definition for CAN_FLTWS register ************************/ + +#define CAN_FLTWS_SEL_POSS 0U +#define CAN_FLTWS_SEL_POSE 13U +#define CAN_FLTWS_SEL_MSK BITS(CAN_FLTWS_SEL_POSS,CAN_FLTWS_SEL_POSE) + +/****************** Bit definition for CAN_FLTAS register ************************/ + +#define CAN_FLTAS_ASSIGN_POSS 0U +#define CAN_FLTAS_ASSIGN_POSE 13U +#define CAN_FLTAS_ASSIGN_MSK BITS(CAN_FLTAS_ASSIGN_POSS,CAN_FLTAS_ASSIGN_POSE) + +/****************** Bit definition for CAN_FLTGO register ************************/ + +#define CAN_FLTGO_GO_POSS 0U +#define CAN_FLTGO_GO_POSE 13U +#define CAN_FLTGO_GO_MSK BITS(CAN_FLTGO_GO_POSS,CAN_FLTGO_GO_POSE) + +typedef struct { + __IO uint32_t TXID; + __IO uint32_t TXFCON; + __IO uint32_t TXDL; + __IO uint32_t TXDH; +} CAN_TxMailBox_Typedef; + +typedef struct { + __IO uint32_t RXFID; + __IO uint32_t RXFINF; + __IO uint32_t RXFDL; + __IO uint32_t RXFDH; +} CAN_RxFIFO_Typedef; + +typedef struct { + __IO uint32_t FLT1; + __IO uint32_t FLT2; +} CAN_Filter_Typedef; + +typedef struct +{ + __IO uint32_t CON; + __I uint32_t STAT; + __O uint32_t IFC; + __IO uint32_t TXSTAT; + __O uint32_t TXSTATC; + __IO uint32_t RXF0; + __O uint32_t RXF0C; + __IO uint32_t RXF1; + __O uint32_t RXF1C; + __IO uint32_t IE; + __IO uint32_t ERRSTAT; + __IO uint32_t BTIME; + uint32_t RESERVED0[84] ; + CAN_TxMailBox_Typedef TxMailBox[3]; + CAN_RxFIFO_Typedef RxFIFO[2]; + uint32_t RESERVED1[12] ; + __IO uint32_t FLTCON; + __IO uint32_t FLTM; + uint32_t RESERVED2 ; + __IO uint32_t FLTWS; + uint32_t RESERVED3 ; + __IO uint32_t FLTAS; + uint32_t RESERVED4 ; + __IO uint32_t FLTGO; + uint32_t RESERVED5[8] ; + CAN_Filter_Typedef Filter[14]; +} CAN_TypeDef; + +/****************** Bit definition for CRC_CR register ************************/ +#define CRC_CR_BYTORD_POS 24U +#define CRC_CR_BYTORD_MSK BIT(CRC_CR_BYTORD_POS) + +#define CRC_CR_DATLEN_POSS 22U +#define CRC_CR_DATLEN_POSE 23U +#define CRC_CR_DATLEN_MSK BITS(CRC_CR_DATLEN_POSS,CRC_CR_DATLEN_POSE) + +#define CRC_CR_MODE_POSS 20U +#define CRC_CR_MODE_POSE 21U +#define CRC_CR_MODE_MSK BITS(CRC_CR_MODE_POSS,CRC_CR_MODE_POSE) + +#define CRC_CR_CHSINV_POS 19U +#define CRC_CR_CHSINV_MSK BIT(CRC_CR_CHSINV_POS) + +#define CRC_CR_DATINV_POS 18U +#define CRC_CR_DATINV_MSK BIT(CRC_CR_DATINV_POS) + +#define CRC_CR_CHSREV_POS 17U +#define CRC_CR_CHSREV_MSK BIT(CRC_CR_CHSREV_POS) + +#define CRC_CR_DATREV_POS 16U +#define CRC_CR_DATREV_MSK BIT(CRC_CR_DATREV_POS) + +#define CRC_CR_DMAEN_POS 4U +#define CRC_CR_DMAEN_MSK BIT(CRC_CR_DMAEN_POS) + +#define CRC_CR_CWERR_POS 3U +#define CRC_CR_CWERR_MSK BIT(CRC_CR_CWERR_POS) + +#define CRC_CR_WERR_POS 2U +#define CRC_CR_WERR_MSK BIT(CRC_CR_WERR_POS) + +#define CRC_CR_RST_POS 1U +#define CRC_CR_RST_MSK BIT(CRC_CR_RST_POS) + +#define CRC_CR_EN_POS 0U +#define CRC_CR_EN_MSK BIT(CRC_CR_EN_POS) + +/****************** Bit definition for CRC_DATA register ************************/ + +#define CRC_DATA_DATA_POSS 0U +#define CRC_DATA_DATA_POSE 31U +#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE) + +/****************** Bit definition for CRC_SEED register ************************/ + +#define CRC_SEED_SEED_POSS 0U +#define CRC_SEED_SEED_POSE 31U +#define CRC_SEED_SEED_MSK BITS(CRC_SEED_SEED_POSS,CRC_SEED_SEED_POSE) + +/****************** Bit definition for CRC_CHECKSUM register ************************/ + +#define CRC_CHECKSUM_CHECKSUM_POSS 0U +#define CRC_CHECKSUM_CHECKSUM_POSE 31U +#define CRC_CHECKSUM_CHECKSUM_MSK BITS(CRC_CHECKSUM_CHECKSUM_POSS,CRC_CHECKSUM_CHECKSUM_POSE) + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t DATA; + __IO uint32_t SEED; + __I uint32_t CHECKSUM; +} CRC_TypeDef; + +/****************** Bit definition for CRYPT_CON register ************************/ + +#define CRYPT_CON_CRYSEL_POS 31U +#define CRYPT_CON_CRYSEL_MSK BIT(CRYPT_CON_CRYSEL_POS) + +#define CRYPT_CON_RESCLR_POS 15U +#define CRYPT_CON_RESCLR_MSK BIT(CRYPT_CON_RESCLR_POS) + +#define CRYPT_CON_DMAEN_POS 14U +#define CRYPT_CON_DMAEN_MSK BIT(CRYPT_CON_DMAEN_POS) + +#define CRYPT_CON_FIFOODR_POS 13U +#define CRYPT_CON_FIFOODR_MSK BIT(CRYPT_CON_FIFOODR_POS) + +#define CRYPT_CON_FIFOEN_POS 12U +#define CRYPT_CON_FIFOEN_MSK BIT(CRYPT_CON_FIFOEN_POS) + +#define CRYPT_CON_DESKS_POS 11U +#define CRYPT_CON_DESKS_MSK BIT(CRYPT_CON_DESKS_POS) + +#define CRYPT_CON_TDES_POS 10U +#define CRYPT_CON_TDES_MSK BIT(CRYPT_CON_TDES_POS) + +#define CRYPT_CON_TYPE_POSS 8U +#define CRYPT_CON_TYPE_POSE 9U +#define CRYPT_CON_TYPE_MSK BITS(CRYPT_CON_TYPE_POSS,CRYPT_CON_TYPE_POSE) + +#define CRYPT_CON_IE_POS 7U +#define CRYPT_CON_IE_MSK BIT(CRYPT_CON_IE_POS) + +#define CRYPT_CON_IVEN_POS 6U +#define CRYPT_CON_IVEN_MSK BIT(CRYPT_CON_IVEN_POS) + +#define CRYPT_CON_MODE_POSS 4U +#define CRYPT_CON_MODE_POSE 5U +#define CRYPT_CON_MODE_MSK BITS(CRYPT_CON_MODE_POSS,CRYPT_CON_MODE_POSE) + +#define CRYPT_CON_AESKS_POSS 2U +#define CRYPT_CON_AESKS_POSE 3U +#define CRYPT_CON_AESKS_MSK BITS(CRYPT_CON_AESKS_POSS,CRYPT_CON_AESKS_POSE) + +#define CRYPT_CON_ENCS_POS 1U +#define CRYPT_CON_ENCS_MSK BIT(CRYPT_CON_ENCS_POS) + +#define CRYPT_CON_GO_POS 0U +#define CRYPT_CON_GO_MSK BIT(CRYPT_CON_GO_POS) + +/****************** Bit definition for CRYPT_IF register ************************/ + +#define CRYPT_IF_DONE_POS 8U +#define CRYPT_IF_DONE_MSK BIT(CRYPT_IF_DONE_POS) + +#define CRYPT_IF_MULTHIF_POS 2U +#define CRYPT_IF_MULTHIF_MSK BIT(CRYPT_IF_MULTHIF_POS) + +#define CRYPT_IF_DESIF_POS 1U +#define CRYPT_IF_DESIF_MSK BIT(CRYPT_IF_DESIF_POS) + +#define CRYPT_IF_AESIF_POS 0U +#define CRYPT_IF_AESIF_MSK BIT(CRYPT_IF_AESIF_POS) + +/****************** Bit definition for CRYPT_IFC register ************************/ + +#define CRYPT_IFC_MULTHIFC_POS 2U +#define CRYPT_IFC_MULTHIFC_MSK BIT(CRYPT_IFC_MULTHIFC_POS) + +#define CRYPT_IFC_DESIFC_POS 1U +#define CRYPT_IFC_DESIFC_MSK BIT(CRYPT_IFC_DESIFC_POS) + +#define CRYPT_IFC_AESIFC_POS 0U +#define CRYPT_IFC_AESIFC_MSK BIT(CRYPT_IFC_AESIFC_POS) + +/****************** Bit definition for CRYPT_FIFO register ************************/ + +#define CRYPT_FIFO_FIFO_POSS 0U +#define CRYPT_FIFO_FIFO_POSE 31U +#define CRYPT_FIFO_FIFO_MSK BITS(CRYPT_FIFO_FIFO_POSS,CRYPT_FIFO_FIFO_POSE) + +typedef struct +{ + __IO uint32_t DATA[4]; + __IO uint32_t KEY[8]; + __IO uint32_t IV[4]; + __I uint32_t RES[4]; + __IO uint32_t CON; + __I uint32_t IF; + __O uint32_t IFC; + __IO uint32_t FIFO; +} CRYPT_TypeDef; + +/****************** Bit definition for LCD_CR register ************************/ + +#define LCD_CR_VCHPS_POSS 24U +#define LCD_CR_VCHPS_POSE 25U +#define LCD_CR_VCHPS_MSK BITS(LCD_CR_VCHPS_POSS,LCD_CR_VCHPS_POSE) + +#define LCD_CR_DSLD_POSS 20U +#define LCD_CR_DSLD_POSE 23U +#define LCD_CR_DSLD_MSK BITS(LCD_CR_DSLD_POSS,LCD_CR_DSLD_POSE) + +#define LCD_CR_DSHD_POSS 16U +#define LCD_CR_DSHD_POSE 19U +#define LCD_CR_DSHD_MSK BITS(LCD_CR_DSHD_POSS,LCD_CR_DSHD_POSE) + +#define LCD_CR_VBUFLD_POS 15U +#define LCD_CR_VBUFLD_MSK BIT(LCD_CR_VBUFLD_POS) + +#define LCD_CR_VBUFHD_POS 14U +#define LCD_CR_VBUFHD_MSK BIT(LCD_CR_VBUFHD_POS) + +#define LCD_CR_RESLD_POSS 12U +#define LCD_CR_RESLD_POSE 13U +#define LCD_CR_RESLD_MSK BITS(LCD_CR_RESLD_POSS,LCD_CR_RESLD_POSE) + +#define LCD_CR_RESHD_POSS 10U +#define LCD_CR_RESHD_POSE 11U +#define LCD_CR_RESHD_MSK BITS(LCD_CR_RESHD_POSS,LCD_CR_RESHD_POSE) + +#define LCD_CR_BIAS_POSS 8U +#define LCD_CR_BIAS_POSE 9U +#define LCD_CR_BIAS_MSK BITS(LCD_CR_BIAS_POSS,LCD_CR_BIAS_POSE) + +#define LCD_CR_DUTY_POSS 4U +#define LCD_CR_DUTY_POSE 6U +#define LCD_CR_DUTY_MSK BITS(LCD_CR_DUTY_POSS,LCD_CR_DUTY_POSE) + +#define LCD_CR_OE_POS 3U +#define LCD_CR_OE_MSK BIT(LCD_CR_OE_POS) + +#define LCD_CR_VSEL_POSS 1U +#define LCD_CR_VSEL_POSE 2U +#define LCD_CR_VSEL_MSK BITS(LCD_CR_VSEL_POSS,LCD_CR_VSEL_POSE) + +#define LCD_CR_EN_POS 0U +#define LCD_CR_EN_MSK BIT(LCD_CR_EN_POS) + +/****************** Bit definition for LCD_FCR register ************************/ + +#define LCD_FCR_WFS_POS 31U +#define LCD_FCR_WFS_MSK BIT(LCD_FCR_WFS_POS) + +#define LCD_FCR_PRS_POSS 24U +#define LCD_FCR_PRS_POSE 27U +#define LCD_FCR_PRS_MSK BITS(LCD_FCR_PRS_POSS,LCD_FCR_PRS_POSE) + +#define LCD_FCR_DIV_POSS 20U +#define LCD_FCR_DIV_POSE 23U +#define LCD_FCR_DIV_MSK BITS(LCD_FCR_DIV_POSS,LCD_FCR_DIV_POSE) + +#define LCD_FCR_BLMOD_POSS 16U +#define LCD_FCR_BLMOD_POSE 17U +#define LCD_FCR_BLMOD_MSK BITS(LCD_FCR_BLMOD_POSS,LCD_FCR_BLMOD_POSE) + +#define LCD_FCR_BLFRQ_POSS 12U +#define LCD_FCR_BLFRQ_POSE 14U +#define LCD_FCR_BLFRQ_MSK BITS(LCD_FCR_BLFRQ_POSS,LCD_FCR_BLFRQ_POSE) + +#define LCD_FCR_DEAD_POSS 8U +#define LCD_FCR_DEAD_POSE 10U +#define LCD_FCR_DEAD_MSK BITS(LCD_FCR_DEAD_POSS,LCD_FCR_DEAD_POSE) + +#define LCD_FCR_HD_POS 7U +#define LCD_FCR_HD_MSK BIT(LCD_FCR_HD_POS) + +#define LCD_FCR_PON_POSS 4U +#define LCD_FCR_PON_POSE 6U +#define LCD_FCR_PON_MSK BITS(LCD_FCR_PON_POSS,LCD_FCR_PON_POSE) + +#define LCD_FCR_VGS_POSS 0U +#define LCD_FCR_VGS_POSE 3U +#define LCD_FCR_VGS_MSK BITS(LCD_FCR_VGS_POSS,LCD_FCR_VGS_POSE) + +/****************** Bit definition for LCD_SEGCR0 register ************************/ + +#define LCD_SEGCR0_SEG_OE_POSS 0U +#define LCD_SEGCR0_SEG_OE_POSE 31U +#define LCD_SEGCR0_SEG_OE_MSK BITS(LCD_SEGCR0_SEG_OE_POSS,LCD_SEGCR0_SEG_OE_POSE) + +/****************** Bit definition for LCD_SEGCR1 register ************************/ + +#define LCD_SEGCR1_SEG_OE_POSS 0U +#define LCD_SEGCR1_SEG_OE_POSE 11U +#define LCD_SEGCR1_SEG_OE_MSK BITS(LCD_SEGCR1_SEG_OE_POSS,LCD_SEGCR1_SEG_OE_POSE) + +/****************** Bit definition for LCD_IE register ************************/ + +#define LCD_IE_UDDIE_POS 1U +#define LCD_IE_UDDIE_MSK BIT(LCD_IE_UDDIE_POS) + +#define LCD_IE_SOFIE_POS 0U +#define LCD_IE_SOFIE_MSK BIT(LCD_IE_SOFIE_POS) + +/****************** Bit definition for LCD_IF register ************************/ + +#define LCD_IF_UDDIF_POS 1U +#define LCD_IF_UDDIF_MSK BIT(LCD_IF_UDDIF_POS) + +#define LCD_IF_SOFIF_POS 0U +#define LCD_IF_SOFIF_MSK BIT(LCD_IF_SOFIF_POS) + +/****************** Bit definition for LCD_IFCR register ************************/ + +#define LCD_IFCR_UDDIFC_POS 1U +#define LCD_IFCR_UDDIFC_MSK BIT(LCD_IFCR_UDDIFC_POS) + +#define LCD_IFCR_SOFIFC_POS 0U +#define LCD_IFCR_SOFIFC_MSK BIT(LCD_IFCR_SOFIFC_POS) + +/****************** Bit definition for LCD_SR register ************************/ + +#define LCD_SR_FCRSF_POS 3U +#define LCD_SR_FCRSF_MSK BIT(LCD_SR_FCRSF_POS) + +#define LCD_SR_UDR_POS 2U +#define LCD_SR_UDR_MSK BIT(LCD_SR_UDR_POS) + +#define LCD_SR_ENS_POS 1U +#define LCD_SR_ENS_MSK BIT(LCD_SR_ENS_POS) + +#define LCD_SR_RDY_POS 0U +#define LCD_SR_RDY_MSK BIT(LCD_SR_RDY_POS) + +/****************** Bit definition for LCD_BUF register ************************/ + +#define LCD_BUF_SEG_DATA_POSS 0U +#define LCD_BUF_SEG_DATA_POSE 31U +#define LCD_BUF_SEG_DATA_MSK BITS(LCD_BUF_SEG_DATA_POSS,LCD_BUF_SEG_DATA_POSE) + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t FCR; + __IO uint32_t SEGCR0; + __IO uint32_t SEGCR1; + __IO uint32_t IE; + __I uint32_t IF; + __O uint32_t IFCR; + __I uint32_t SR; + uint32_t RESERVED0[8] ; + __IO uint32_t BUF[16]; +} LCD_TypeDef; + +/****************** Bit definition for ADC_STAT register ************************/ + +#define ADC_STAT_ICHS_POS 9U +#define ADC_STAT_ICHS_MSK BIT(ADC_STAT_ICHS_POS) + +#define ADC_STAT_NCHS_POS 8U +#define ADC_STAT_NCHS_MSK BIT(ADC_STAT_NCHS_POS) + +#define ADC_STAT_OVR_POS 3U +#define ADC_STAT_OVR_MSK BIT(ADC_STAT_OVR_POS) + +#define ADC_STAT_ICHE_POS 2U +#define ADC_STAT_ICHE_MSK BIT(ADC_STAT_ICHE_POS) + +#define ADC_STAT_NCHE_POS 1U +#define ADC_STAT_NCHE_MSK BIT(ADC_STAT_NCHE_POS) + +#define ADC_STAT_AWDF_POS 0U +#define ADC_STAT_AWDF_MSK BIT(ADC_STAT_AWDF_POS) + +/****************** Bit definition for ADC_CLR register ************************/ + +#define ADC_CLR_ICHS_POS 9U +#define ADC_CLR_ICHS_MSK BIT(ADC_CLR_ICHS_POS) + +#define ADC_CLR_NCHS_POS 8U +#define ADC_CLR_NCHS_MSK BIT(ADC_CLR_NCHS_POS) + +#define ADC_CLR_OVR_POS 3U +#define ADC_CLR_OVR_MSK BIT(ADC_CLR_OVR_POS) + +#define ADC_CLR_ICHE_POS 2U +#define ADC_CLR_ICHE_MSK BIT(ADC_CLR_ICHE_POS) + +#define ADC_CLR_NCHE_POS 1U +#define ADC_CLR_NCHE_MSK BIT(ADC_CLR_NCHE_POS) + +#define ADC_CLR_AWDF_POS 0U +#define ADC_CLR_AWDF_MSK BIT(ADC_CLR_AWDF_POS) + +/****************** Bit definition for ADC_CON0 register ************************/ + +#define ADC_CON0_OVRIE_POS 26U +#define ADC_CON0_OVRIE_MSK BIT(ADC_CON0_OVRIE_POS) + +#define ADC_CON0_RSEL_POSS 24U +#define ADC_CON0_RSEL_POSE 25U +#define ADC_CON0_RSEL_MSK BITS(ADC_CON0_RSEL_POSS,ADC_CON0_RSEL_POSE) + +#define ADC_CON0_NCHWDEN_POS 23U +#define ADC_CON0_NCHWDEN_MSK BIT(ADC_CON0_NCHWDEN_POS) + +#define ADC_CON0_ICHWDTEN_POS 22U +#define ADC_CON0_ICHWDTEN_MSK BIT(ADC_CON0_ICHWDTEN_POS) + +#define ADC_CON0_ETRGN_POSS 13U +#define ADC_CON0_ETRGN_POSE 15U +#define ADC_CON0_ETRGN_MSK BITS(ADC_CON0_ETRGN_POSS,ADC_CON0_ETRGN_POSE) + +#define ADC_CON0_ICHDCEN_POS 12U +#define ADC_CON0_ICHDCEN_MSK BIT(ADC_CON0_ICHDCEN_POS) + +#define ADC_CON0_NCHDCEN_POS 11U +#define ADC_CON0_NCHDCEN_MSK BIT(ADC_CON0_NCHDCEN_POS) + +#define ADC_CON0_IAUTO_POS 10U +#define ADC_CON0_IAUTO_MSK BIT(ADC_CON0_IAUTO_POS) + +#define ADC_CON0_AWDSGL_POS 9U +#define ADC_CON0_AWDSGL_MSK BIT(ADC_CON0_AWDSGL_POS) + +#define ADC_CON0_SCANEN_POS 8U +#define ADC_CON0_SCANEN_MSK BIT(ADC_CON0_SCANEN_POS) + +#define ADC_CON0_ICHEIE_POS 7U +#define ADC_CON0_ICHEIE_MSK BIT(ADC_CON0_ICHEIE_POS) + +#define ADC_CON0_AWDIE_POS 6U +#define ADC_CON0_AWDIE_MSK BIT(ADC_CON0_AWDIE_POS) + +#define ADC_CON0_NCHEIE_POS 5U +#define ADC_CON0_NCHEIE_MSK BIT(ADC_CON0_NCHEIE_POS) + +#define ADC_CON0_AWDCH_POSS 0U +#define ADC_CON0_AWDCH_POSE 4U +#define ADC_CON0_AWDCH_MSK BITS(ADC_CON0_AWDCH_POSS,ADC_CON0_AWDCH_POSE) + +/****************** Bit definition for ADC_CON1 register ************************/ + +#define ADC_CON1_NCHTRG_POS 30U +#define ADC_CON1_NCHTRG_MSK BIT(ADC_CON1_NCHTRG_POS) + +#define ADC_CON1_ICHTRG_POS 22U +#define ADC_CON1_ICHTRG_MSK BIT(ADC_CON1_ICHTRG_POS) + +#define ADC_CON1_ALIGN_POS 11U +#define ADC_CON1_ALIGN_MSK BIT(ADC_CON1_ALIGN_POS) + +#define ADC_CON1_NCHESEL_POS 10U +#define ADC_CON1_NCHESEL_MSK BIT(ADC_CON1_NCHESEL_POS) + +#define ADC_CON1_OVRDIS_POS 8U +#define ADC_CON1_OVRDIS_MSK BIT(ADC_CON1_OVRDIS_POS) + +#define ADC_CON1_CM_POS 1U +#define ADC_CON1_CM_MSK BIT(ADC_CON1_CM_POS) + +#define ADC_CON1_ADCEN_POS 0U +#define ADC_CON1_ADCEN_MSK BIT(ADC_CON1_ADCEN_POS) + +/****************** Bit definition for ADC_SMPT1 register ************************/ + +#define ADC_SMPT1_CHT_POSS 0U +#define ADC_SMPT1_CHT_POSE 31U +#define ADC_SMPT1_CHT_MSK BITS(ADC_SMPT1_CHT_POSS,ADC_SMPT1_CHT_POSE) + +/****************** Bit definition for ADC_SMPT2 register ************************/ + +#define ADC_SMPT2_CHT_POSS 0U +#define ADC_SMPT2_CHT_POSE 7U +#define ADC_SMPT2_CHT_MSK BITS(ADC_SMPT2_CHT_POSS,ADC_SMPT2_CHT_POSE) + +/****************** Bit definition for ADC_ICHOFF1 register ************************/ + +#define ADC_ICHOFF1_IOFF_POSS 0U +#define ADC_ICHOFF1_IOFF_POSE 11U +#define ADC_ICHOFF1_IOFF_MSK BITS(ADC_ICHOFF1_IOFF_POSS,ADC_ICHOFF1_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF2 register ************************/ + +#define ADC_ICHOFF2_IOFF_POSS 0U +#define ADC_ICHOFF2_IOFF_POSE 11U +#define ADC_ICHOFF2_IOFF_MSK BITS(ADC_ICHOFF2_IOFF_POSS,ADC_ICHOFF2_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF3 register ************************/ + +#define ADC_ICHOFF3_IOFF_POSS 0U +#define ADC_ICHOFF3_IOFF_POSE 11U +#define ADC_ICHOFF3_IOFF_MSK BITS(ADC_ICHOFF3_IOFF_POSS,ADC_ICHOFF3_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF4 register ************************/ + +#define ADC_ICHOFF4_IOFF_POSS 0U +#define ADC_ICHOFF4_IOFF_POSE 11U +#define ADC_ICHOFF4_IOFF_MSK BITS(ADC_ICHOFF4_IOFF_POSS,ADC_ICHOFF4_IOFF_POSE) + +/****************** Bit definition for ADC_WDTH register ************************/ + +#define ADC_WDTH_HT_POSS 0U +#define ADC_WDTH_HT_POSE 11U +#define ADC_WDTH_HT_MSK BITS(ADC_WDTH_HT_POSS,ADC_WDTH_HT_POSE) + +/****************** Bit definition for ADC_WDTL register ************************/ + +#define ADC_WDTL_LT_POSS 0U +#define ADC_WDTL_LT_POSE 11U +#define ADC_WDTL_LT_MSK BITS(ADC_WDTL_LT_POSS,ADC_WDTL_LT_POSE) + +/****************** Bit definition for ADC_NCHS1 register ************************/ + +#define ADC_NCHS1_NS4_POSS 24U +#define ADC_NCHS1_NS4_POSE 28U +#define ADC_NCHS1_NS4_MSK BITS(ADC_NCHS1_NS4_POSS,ADC_NCHS1_NS4_POSE) + +#define ADC_NCHS1_NS3_POSS 16U +#define ADC_NCHS1_NS3_POSE 20U +#define ADC_NCHS1_NS3_MSK BITS(ADC_NCHS1_NS3_POSS,ADC_NCHS1_NS3_POSE) + +#define ADC_NCHS1_NS2_POSS 8U +#define ADC_NCHS1_NS2_POSE 12U +#define ADC_NCHS1_NS2_MSK BITS(ADC_NCHS1_NS2_POSS,ADC_NCHS1_NS2_POSE) + +#define ADC_NCHS1_NS1_POSS 0U +#define ADC_NCHS1_NS1_POSE 4U +#define ADC_NCHS1_NS1_MSK BITS(ADC_NCHS1_NS1_POSS,ADC_NCHS1_NS1_POSE) + +/****************** Bit definition for ADC_NCHS2 register ************************/ + +#define ADC_NCHS2_NS8_POSS 24U +#define ADC_NCHS2_NS8_POSE 28U +#define ADC_NCHS2_NS8_MSK BITS(ADC_NCHS2_NS8_POSS,ADC_NCHS2_NS8_POSE) + +#define ADC_NCHS2_NS7_POSS 16U +#define ADC_NCHS2_NS7_POSE 20U +#define ADC_NCHS2_NS7_MSK BITS(ADC_NCHS2_NS7_POSS,ADC_NCHS2_NS7_POSE) + +#define ADC_NCHS2_NS6_POSS 8U +#define ADC_NCHS2_NS6_POSE 12U +#define ADC_NCHS2_NS6_MSK BITS(ADC_NCHS2_NS6_POSS,ADC_NCHS2_NS6_POSE) + +#define ADC_NCHS2_NS5_POSS 0U +#define ADC_NCHS2_NS5_POSE 4U +#define ADC_NCHS2_NS5_MSK BITS(ADC_NCHS2_NS5_POSS,ADC_NCHS2_NS5_POSE) + +/****************** Bit definition for ADC_NCHS3 register ************************/ + +#define ADC_NCHS3_NS12_POSS 24U +#define ADC_NCHS3_NS12_POSE 28U +#define ADC_NCHS3_NS12_MSK BITS(ADC_NCHS3_NS12_POSS,ADC_NCHS3_NS12_POSE) + +#define ADC_NCHS3_NS11_POSS 16U +#define ADC_NCHS3_NS11_POSE 20U +#define ADC_NCHS3_NS11_MSK BITS(ADC_NCHS3_NS11_POSS,ADC_NCHS3_NS11_POSE) + +#define ADC_NCHS3_NS10_POSS 8U +#define ADC_NCHS3_NS10_POSE 12U +#define ADC_NCHS3_NS10_MSK BITS(ADC_NCHS3_NS10_POSS,ADC_NCHS3_NS10_POSE) + +#define ADC_NCHS3_NS9_POSS 0U +#define ADC_NCHS3_NS9_POSE 4U +#define ADC_NCHS3_NS9_MSK BITS(ADC_NCHS3_NS9_POSS,ADC_NCHS3_NS9_POSE) + +/****************** Bit definition for ADC_NCHS4 register ************************/ + +#define ADC_NCHS4_NS16_POSS 24U +#define ADC_NCHS4_NS16_POSE 28U +#define ADC_NCHS4_NS16_MSK BITS(ADC_NCHS4_NS16_POSS,ADC_NCHS4_NS16_POSE) + +#define ADC_NCHS4_NS15_POSS 16U +#define ADC_NCHS4_NS15_POSE 20U +#define ADC_NCHS4_NS15_MSK BITS(ADC_NCHS4_NS15_POSS,ADC_NCHS4_NS15_POSE) + +#define ADC_NCHS4_NS14_POSS 8U +#define ADC_NCHS4_NS14_POSE 12U +#define ADC_NCHS4_NS14_MSK BITS(ADC_NCHS4_NS14_POSS,ADC_NCHS4_NS14_POSE) + +#define ADC_NCHS4_NS13_POSS 0U +#define ADC_NCHS4_NS13_POSE 4U +#define ADC_NCHS4_NS13_MSK BITS(ADC_NCHS4_NS13_POSS,ADC_NCHS4_NS13_POSE) + +/****************** Bit definition for ADC_ICHS register ************************/ + +#define ADC_ICHS_IS4_POSS 24U +#define ADC_ICHS_IS4_POSE 28U +#define ADC_ICHS_IS4_MSK BITS(ADC_ICHS_IS4_POSS,ADC_ICHS_IS4_POSE) + +#define ADC_ICHS_IS3_POSS 16U +#define ADC_ICHS_IS3_POSE 20U +#define ADC_ICHS_IS3_MSK BITS(ADC_ICHS_IS3_POSS,ADC_ICHS_IS3_POSE) + +#define ADC_ICHS_IS2_POSS 8U +#define ADC_ICHS_IS2_POSE 12U +#define ADC_ICHS_IS2_MSK BITS(ADC_ICHS_IS2_POSS,ADC_ICHS_IS2_POSE) + +#define ADC_ICHS_IS1_POSS 0U +#define ADC_ICHS_IS1_POSE 4U +#define ADC_ICHS_IS1_MSK BITS(ADC_ICHS_IS1_POSS,ADC_ICHS_IS1_POSE) + +/****************** Bit definition for ADC_CHSL register ************************/ + +#define ADC_CHSL_ISL_POSS 8U +#define ADC_CHSL_ISL_POSE 9U +#define ADC_CHSL_ISL_MSK BITS(ADC_CHSL_ISL_POSS,ADC_CHSL_ISL_POSE) + +#define ADC_CHSL_NSL_POSS 0U +#define ADC_CHSL_NSL_POSE 3U +#define ADC_CHSL_NSL_MSK BITS(ADC_CHSL_NSL_POSS,ADC_CHSL_NSL_POSE) + +/****************** Bit definition for ADC_ICHDR1 register ************************/ + +#define ADC_ICHDR1_VAL_POSS 0U +#define ADC_ICHDR1_VAL_POSE 15U +#define ADC_ICHDR1_VAL_MSK BITS(ADC_ICHDR1_VAL_POSS,ADC_ICHDR1_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR2 register ************************/ + +#define ADC_ICHDR2_VAL_POSS 0U +#define ADC_ICHDR2_VAL_POSE 15U +#define ADC_ICHDR2_VAL_MSK BITS(ADC_ICHDR2_VAL_POSS,ADC_ICHDR2_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR3 register ************************/ + +#define ADC_ICHDR3_VAL_POSS 0U +#define ADC_ICHDR3_VAL_POSE 15U +#define ADC_ICHDR3_VAL_MSK BITS(ADC_ICHDR3_VAL_POSS,ADC_ICHDR3_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR4 register ************************/ + +#define ADC_ICHDR4_VAL_POSS 0U +#define ADC_ICHDR4_VAL_POSE 15U +#define ADC_ICHDR4_VAL_MSK BITS(ADC_ICHDR4_VAL_POSS,ADC_ICHDR4_VAL_POSE) + +/****************** Bit definition for ADC_NCHDR register ************************/ + +#define ADC_NCHDR_VAL_POSS 0U +#define ADC_NCHDR_VAL_POSE 15U +#define ADC_NCHDR_VAL_MSK BITS(ADC_NCHDR_VAL_POSS,ADC_NCHDR_VAL_POSE) + +/****************** Bit definition for ADC_CCR register ************************/ + +#define ADC_CCR_TRMEN_POS 28U +#define ADC_CCR_TRMEN_MSK BIT(ADC_CCR_TRMEN_POS) + +#define ADC_CCR_GAINCALEN_POS 25U +#define ADC_CCR_GAINCALEN_MSK BIT(ADC_CCR_GAINCALEN_POS) + +#define ADC_CCR_OFFCALEN_POS 24U +#define ADC_CCR_OFFCALEN_MSK BIT(ADC_CCR_OFFCALEN_POS) + +#define ADC_CCR_VREFOEN_POS 19U +#define ADC_CCR_VREFOEN_MSK BIT(ADC_CCR_VREFOEN_POS) + +#define ADC_CCR_VRNSEL_POS 18U +#define ADC_CCR_VRNSEL_MSK BIT(ADC_CCR_VRNSEL_POS) + +#define ADC_CCR_VRPSEL_POSS 16U +#define ADC_CCR_VRPSEL_POSE 17U +#define ADC_CCR_VRPSEL_MSK BITS(ADC_CCR_VRPSEL_POSS,ADC_CCR_VRPSEL_POSE) + +#define ADC_CCR_PWRMODSEL_POS 15U +#define ADC_CCR_PWRMODSEL_MSK BIT(ADC_CCR_PWRMODSEL_POS) + +#define ADC_CCR_DIFFEN_POS 12U +#define ADC_CCR_DIFFEN_MSK BIT(ADC_CCR_DIFFEN_POS) + +#define ADC_CCR_IREFEN_POS 11U +#define ADC_CCR_IREFEN_MSK BIT(ADC_CCR_IREFEN_POS) + +#define ADC_CCR_VRBUFEN_POS 10U +#define ADC_CCR_VRBUFEN_MSK BIT(ADC_CCR_VRBUFEN_POS) + +#define ADC_CCR_VCMBUFEN_POS 9U +#define ADC_CCR_VCMBUFEN_MSK BIT(ADC_CCR_VCMBUFEN_POS) + +#define ADC_CCR_VREFEN_POS 8U +#define ADC_CCR_VREFEN_MSK BIT(ADC_CCR_VREFEN_POS) + +#define ADC_CCR_CKDIV_POSS 0U +#define ADC_CCR_CKDIV_POSE 2U +#define ADC_CCR_CKDIV_MSK BITS(ADC_CCR_CKDIV_POSS,ADC_CCR_CKDIV_POSE) + +typedef struct +{ + __I uint32_t STAT; + __O uint32_t CLR; + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t SMPT1; + __IO uint32_t SMPT2; + __IO uint32_t ICHOFF[4]; + __IO uint32_t WDTH; + __IO uint32_t WDTL; + __IO uint32_t NCHS1; + __IO uint32_t NCHS2; + __IO uint32_t NCHS3; + __IO uint32_t NCHS4; + __IO uint32_t ICHS; + __IO uint32_t CHSL; + __I uint32_t ICHDR[4]; + __I uint32_t NCHDR; + __IO uint32_t CCR; +} ADC_TypeDef; + +/****************** Bit definition for ACMP_CON register ************************/ + +#define ACMP_CON_FALLEN_POS 17U +#define ACMP_CON_FALLEN_MSK BIT(ACMP_CON_FALLEN_POS) + +#define ACMP_CON_RISEEN_POS 16U +#define ACMP_CON_RISEEN_MSK BIT(ACMP_CON_RISEEN_POS) + +#define ACMP_CON_MODSEL_POSS 14U +#define ACMP_CON_MODSEL_POSE 15U +#define ACMP_CON_MODSEL_MSK BITS(ACMP_CON_MODSEL_POSS,ACMP_CON_MODSEL_POSE) + +#define ACMP_CON_WARMUPT_POSS 8U +#define ACMP_CON_WARMUPT_POSE 10U +#define ACMP_CON_WARMUPT_MSK BITS(ACMP_CON_WARMUPT_POSS,ACMP_CON_WARMUPT_POSE) + +#define ACMP_CON_HYSTSEL_POSS 4U +#define ACMP_CON_HYSTSEL_POSE 6U +#define ACMP_CON_HYSTSEL_MSK BITS(ACMP_CON_HYSTSEL_POSS,ACMP_CON_HYSTSEL_POSE) + +#define ACMP_CON_OUTINV_POS 3U +#define ACMP_CON_OUTINV_MSK BIT(ACMP_CON_OUTINV_POS) + +#define ACMP_CON_INACTV_POS 2U +#define ACMP_CON_INACTV_MSK BIT(ACMP_CON_INACTV_POS) + +#define ACMP_CON_EN_POS 0U +#define ACMP_CON_EN_MSK BIT(ACMP_CON_EN_POS) + +/****************** Bit definition for ACMP_INPUTSEL register ************************/ + +#define ACMP_INPUTSEL_VDDLVL_POSS 8U +#define ACMP_INPUTSEL_VDDLVL_POSE 13U +#define ACMP_INPUTSEL_VDDLVL_MSK BITS(ACMP_INPUTSEL_VDDLVL_POSS,ACMP_INPUTSEL_VDDLVL_POSE) + +#define ACMP_INPUTSEL_NSEL_POSS 4U +#define ACMP_INPUTSEL_NSEL_POSE 7U +#define ACMP_INPUTSEL_NSEL_MSK BITS(ACMP_INPUTSEL_NSEL_POSS,ACMP_INPUTSEL_NSEL_POSE) + +#define ACMP_INPUTSEL_PSEL_POSS 0U +#define ACMP_INPUTSEL_PSEL_POSE 2U +#define ACMP_INPUTSEL_PSEL_MSK BITS(ACMP_INPUTSEL_PSEL_POSS,ACMP_INPUTSEL_PSEL_POSE) + +/****************** Bit definition for ACMP_STAT register ************************/ + +#define ACMP_STAT_OUT_POS 1U +#define ACMP_STAT_OUT_MSK BIT(ACMP_STAT_OUT_POS) + +#define ACMP_STAT_ACT_POS 0U +#define ACMP_STAT_ACT_MSK BIT(ACMP_STAT_ACT_POS) + +/****************** Bit definition for ACMP_IES register ************************/ + +#define ACMP_IES_WARMUP_POS 1U +#define ACMP_IES_WARMUP_MSK BIT(ACMP_IES_WARMUP_POS) + +#define ACMP_IES_EDGE_POS 0U +#define ACMP_IES_EDGE_MSK BIT(ACMP_IES_EDGE_POS) + +/****************** Bit definition for ACMP_IEV register ************************/ + +#define ACMP_IEV_WARMUP_POS 1U +#define ACMP_IEV_WARMUP_MSK BIT(ACMP_IEV_WARMUP_POS) + +#define ACMP_IEV_EDGE_POS 0U +#define ACMP_IEV_EDGE_MSK BIT(ACMP_IEV_EDGE_POS) + +/****************** Bit definition for ACMP_IEC register ************************/ + +#define ACMP_IEC_WARMUP_POS 1U +#define ACMP_IEC_WARMUP_MSK BIT(ACMP_IEC_WARMUP_POS) + +#define ACMP_IEC_EDGE_POS 0U +#define ACMP_IEC_EDGE_MSK BIT(ACMP_IEC_EDGE_POS) + +/****************** Bit definition for ACMP_RIF register ************************/ + +#define ACMP_RIF_WARMUP_POS 1U +#define ACMP_RIF_WARMUP_MSK BIT(ACMP_RIF_WARMUP_POS) + +#define ACMP_RIF_EDGE_POS 0U +#define ACMP_RIF_EDGE_MSK BIT(ACMP_RIF_EDGE_POS) + +/****************** Bit definition for ACMP_IFM register ************************/ + +#define ACMP_IFM_WARMUP_POS 1U +#define ACMP_IFM_WARMUP_MSK BIT(ACMP_IFM_WARMUP_POS) + +#define ACMP_IFM_EDGE_POS 0U +#define ACMP_IFM_EDGE_MSK BIT(ACMP_IFM_EDGE_POS) + +/****************** Bit definition for ACMP_IFC register ************************/ + +#define ACMP_IFC_WARMUP_POS 1U +#define ACMP_IFC_WARMUP_MSK BIT(ACMP_IFC_WARMUP_POS) + +#define ACMP_IFC_EDGE_POS 0U +#define ACMP_IFC_EDGE_MSK BIT(ACMP_IFC_EDGE_POS) + +/****************** Bit definition for ACMP_PORT register ************************/ + +#define ACMP_PORT_PEN_POS 0U +#define ACMP_PORT_PEN_MSK BIT(ACMP_PORT_PEN_POS) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t INPUTSEL; + __I uint32_t STAT; + __O uint32_t IES; + __I uint32_t IEV; + __O uint32_t IEC; + __I uint32_t RIF; + __O uint32_t IFM; + __O uint32_t IFC; + __IO uint32_t PORT; +} ACMP_TypeDef; + +/****************** Bit definition for CALC_SQRTSR register ************************/ + +#define CALC_SQRTSR_BUSY_POS 0U +#define CALC_SQRTSR_BUSY_MSK BIT(CALC_SQRTSR_BUSY_POS) + +/****************** Bit definition for CALC_RDCND register ************************/ + +#define CALC_RDCND_RADICAND_POSS 0U +#define CALC_RDCND_RADICAND_POSE 31U +#define CALC_RDCND_RADICAND_MSK BITS(CALC_RDCND_RADICAND_POSS,CALC_RDCND_RADICAND_POSE) + +/****************** Bit definition for CALC_SQRTRES register ************************/ + +#define CALC_SQRTRES_RESULT_POSS 0U +#define CALC_SQRTRES_RESULT_POSE 15U +#define CALC_SQRTRES_RESULT_MSK BITS(CALC_SQRTRES_RESULT_POSS,CALC_SQRTRES_RESULT_POSE) + +/****************** Bit definition for CALC_DIVDR register ************************/ + +#define CALC_DIVDR_DIVD_POSS 0U +#define CALC_DIVDR_DIVD_POSE 31U +#define CALC_DIVDR_DIVD_MSK BITS(CALC_DIVDR_DIVD_POSS,CALC_DIVDR_DIVD_POSE) + +/****************** Bit definition for CALC_DIVSR register ************************/ + +#define CALC_DIVSR_DIVS_POSS 0U +#define CALC_DIVSR_DIVS_POSE 31U +#define CALC_DIVSR_DIVS_MSK BITS(CALC_DIVSR_DIVS_POSS,CALC_DIVSR_DIVS_POSE) + +/****************** Bit definition for CALC_DIVQR register ************************/ + +#define CALC_DIVQR_DIVQ_POSS 0U +#define CALC_DIVQR_DIVQ_POSE 31U +#define CALC_DIVQR_DIVQ_MSK BITS(CALC_DIVQR_DIVQ_POSS,CALC_DIVQR_DIVQ_POSE) + +/****************** Bit definition for CALC_DIVRR register ************************/ + +#define CALC_DIVRR_DIVS_POSS 0U +#define CALC_DIVRR_DIVS_POSE 31U +#define CALC_DIVRR_DIVS_MSK BITS(CALC_DIVRR_DIVS_POSS,CALC_DIVRR_DIVS_POSE) + +/****************** Bit definition for CALC_DIVCSR register ************************/ + +#define CALC_DIVCSR_TRM_POS 9U +#define CALC_DIVCSR_TRM_MSK BIT(CALC_DIVCSR_TRM_POS) + +#define CALC_DIVCSR_SIGN_POS 8U +#define CALC_DIVCSR_SIGN_MSK BIT(CALC_DIVCSR_SIGN_POS) + +#define CALC_DIVCSR_DZ_POS 1U +#define CALC_DIVCSR_DZ_MSK BIT(CALC_DIVCSR_DZ_POS) + +#define CALC_DIVCSR_BUSY_POS 0U +#define CALC_DIVCSR_BUSY_MSK BIT(CALC_DIVCSR_BUSY_POS) + +typedef struct +{ + __I uint32_t SQRTSR; + __IO uint32_t RDCND; + __I uint32_t SQRTRES; + uint32_t RESERVED0[5] ; + __IO uint32_t DIVDR; + __IO uint32_t DIVSR; + __I uint32_t DIVQR; + __I uint32_t DIVRR; + __IO uint32_t DIVCSR; +} CALC_TypeDef; + +/****************** Bit definition for TRNG_CR register ************************/ + +#define TRNG_CR_ADJC_POSS 16U +#define TRNG_CR_ADJC_POSE 17U +#define TRNG_CR_ADJC_MSK BITS(TRNG_CR_ADJC_POSS,TRNG_CR_ADJC_POSE) + +#define TRNG_CR_SDSEL_POSS 10U +#define TRNG_CR_SDSEL_POSE 11U +#define TRNG_CR_SDSEL_MSK BITS(TRNG_CR_SDSEL_POSS,TRNG_CR_SDSEL_POSE) + +#define TRNG_CR_DSEL_POSS 8U +#define TRNG_CR_DSEL_POSE 9U +#define TRNG_CR_DSEL_MSK BITS(TRNG_CR_DSEL_POSS,TRNG_CR_DSEL_POSE) + +#define TRNG_CR_POSTEN_POS 3U +#define TRNG_CR_POSTEN_MSK BIT(TRNG_CR_POSTEN_POS) + +#define TRNG_CR_TRNGSEL_POS 2U +#define TRNG_CR_TRNGSEL_MSK BIT(TRNG_CR_TRNGSEL_POS) + +#define TRNG_CR_ADJM_POS 1U +#define TRNG_CR_ADJM_MSK BIT(TRNG_CR_ADJM_POS) + +#define TRNG_CR_TRNGEN_POS 0U +#define TRNG_CR_TRNGEN_MSK BIT(TRNG_CR_TRNGEN_POS) + +/****************** Bit definition for TRNG_SR register ************************/ + +#define TRNG_SR_OVER_POS 3U +#define TRNG_SR_OVER_MSK BIT(TRNG_SR_OVER_POS) + +#define TRNG_SR_SERR_POS 2U +#define TRNG_SR_SERR_MSK BIT(TRNG_SR_SERR_POS) + +#define TRNG_SR_DAVLD_POS 1U +#define TRNG_SR_DAVLD_MSK BIT(TRNG_SR_DAVLD_POS) + +#define TRNG_SR_START_POS 0U +#define TRNG_SR_START_MSK BIT(TRNG_SR_START_POS) + +/****************** Bit definition for TRNG_DR register ************************/ + +#define TRNG_DR_DATA_POSS 0U +#define TRNG_DR_DATA_POSE 31U +#define TRNG_DR_DATA_MSK BITS(TRNG_DR_DATA_POSS,TRNG_DR_DATA_POSE) + +/****************** Bit definition for TRNG_SEED register ************************/ + +#define TRNG_SEED_SEED_POSS 0U +#define TRNG_SEED_SEED_POSE 31U +#define TRNG_SEED_SEED_MSK BITS(TRNG_SEED_SEED_POSS,TRNG_SEED_SEED_POSE) + +/****************** Bit definition for TRNG_CFGR register ************************/ + +#define TRNG_CFGR_TOPLMT_POSS 16U +#define TRNG_CFGR_TOPLMT_POSE 24U +#define TRNG_CFGR_TOPLMT_MSK BITS(TRNG_CFGR_TOPLMT_POSS,TRNG_CFGR_TOPLMT_POSE) + +#define TRNG_CFGR_CKDIV_POSS 8U +#define TRNG_CFGR_CKDIV_POSE 11U +#define TRNG_CFGR_CKDIV_MSK BITS(TRNG_CFGR_CKDIV_POSS,TRNG_CFGR_CKDIV_POSE) + +#define TRNG_CFGR_TSTART_POSS 0U +#define TRNG_CFGR_TSTART_POSE 2U +#define TRNG_CFGR_TSTART_MSK BITS(TRNG_CFGR_TSTART_POSS,TRNG_CFGR_TSTART_POSE) + +/****************** Bit definition for TRNG_IER register ************************/ + +#define TRNG_IER_SERR_POS 2U +#define TRNG_IER_SERR_MSK BIT(TRNG_IER_SERR_POS) + +#define TRNG_IER_DAVLD_POS 1U +#define TRNG_IER_DAVLD_MSK BIT(TRNG_IER_DAVLD_POS) + +#define TRNG_IER_START_POS 0U +#define TRNG_IER_START_MSK BIT(TRNG_IER_START_POS) + +/****************** Bit definition for TRNG_IFR register ************************/ + +#define TRNG_IFR_SERR_POS 2U +#define TRNG_IFR_SERR_MSK BIT(TRNG_IFR_SERR_POS) + +#define TRNG_IFR_DAVLD_POS 1U +#define TRNG_IFR_DAVLD_MSK BIT(TRNG_IFR_DAVLD_POS) + +#define TRNG_IFR_START_POS 0U +#define TRNG_IFR_START_MSK BIT(TRNG_IFR_START_POS) + +/****************** Bit definition for TRNG_IFCR register ************************/ + +#define TRNG_IFCR_SERRC_POS 2U +#define TRNG_IFCR_SERRC_MSK BIT(TRNG_IFCR_SERRC_POS) + +#define TRNG_IFCR_DAVLDC_POS 1U +#define TRNG_IFCR_DAVLDC_MSK BIT(TRNG_IFCR_DAVLDC_POS) + +#define TRNG_IFCR_STARTC_POS 0U +#define TRNG_IFCR_STARTC_MSK BIT(TRNG_IFCR_STARTC_POS) + +/****************** Bit definition for TRNG_ISR register ************************/ + +#define TRNG_ISR_SERR_POS 2U +#define TRNG_ISR_SERR_MSK BIT(TRNG_ISR_SERR_POS) + +#define TRNG_ISR_DAVLD_POS 1U +#define TRNG_ISR_DAVLD_MSK BIT(TRNG_ISR_DAVLD_POS) + +#define TRNG_ISR_START_POS 0U +#define TRNG_ISR_START_MSK BIT(TRNG_ISR_START_POS) + +typedef struct +{ + __IO uint32_t CR; + __I uint32_t SR; + __I uint32_t DR; + __IO uint32_t SEED; + __IO uint32_t CFGR; + __IO uint32_t IER; + __I uint32_t IFR; + __O uint32_t IFCR; + __I uint32_t ISR; +} TRNG_TypeDef; + +/****************** Bit definition for TEMP_WPR register ************************/ + +#define TEMP_WPR_WP_POS 0U +#define TEMP_WPR_WP_MSK BIT(TEMP_WPR_WP_POS) + +/****************** Bit definition for TEMP_CR register ************************/ + +#define TEMP_CR_TSU_POSS 12U +#define TEMP_CR_TSU_POSE 14U +#define TEMP_CR_TSU_MSK BITS(TEMP_CR_TSU_POSS,TEMP_CR_TSU_POSE) + +#define TEMP_CR_TOM_POSS 8U +#define TEMP_CR_TOM_POSE 10U +#define TEMP_CR_TOM_MSK BITS(TEMP_CR_TOM_POSS,TEMP_CR_TOM_POSE) + +#define TEMP_CR_CTN_POS 4U +#define TEMP_CR_CTN_MSK BIT(TEMP_CR_CTN_POS) + +#define TEMP_CR_RST_POS 3U +#define TEMP_CR_RST_MSK BIT(TEMP_CR_RST_POS) + +#define TEMP_CR_ENS_POS 2U +#define TEMP_CR_ENS_MSK BIT(TEMP_CR_ENS_POS) + +#define TEMP_CR_REQEN_POS 1U +#define TEMP_CR_REQEN_MSK BIT(TEMP_CR_REQEN_POS) + +#define TEMP_CR_EN_POS 0U +#define TEMP_CR_EN_MSK BIT(TEMP_CR_EN_POS) + +/****************** Bit definition for TEMP_DR register ************************/ + +#define TEMP_DR_ERR_POS 31U +#define TEMP_DR_ERR_MSK BIT(TEMP_DR_ERR_POS) + +#define TEMP_DR_DATA_POSS 0U +#define TEMP_DR_DATA_POSE 15U +#define TEMP_DR_DATA_MSK BITS(TEMP_DR_DATA_POSS,TEMP_DR_DATA_POSE) + +/****************** Bit definition for TEMP_PSR register ************************/ + +#define TEMP_PSR_PRS_POSS 0U +#define TEMP_PSR_PRS_POSE 7U +#define TEMP_PSR_PRS_MSK BITS(TEMP_PSR_PRS_POSS,TEMP_PSR_PRS_POSE) + +/****************** Bit definition for TEMP_IE register ************************/ + +#define TEMP_IE_TEMP_POS 0U +#define TEMP_IE_TEMP_MSK BIT(TEMP_IE_TEMP_POS) + +/****************** Bit definition for TEMP_IF register ************************/ + +#define TEMP_IF_TEMP_POS 0U +#define TEMP_IF_TEMP_MSK BIT(TEMP_IF_TEMP_POS) + +/****************** Bit definition for TEMP_IFCR register ************************/ + +#define TEMP_IFCR_TEMP_POS 0U +#define TEMP_IFCR_TEMP_MSK BIT(TEMP_IFCR_TEMP_POS) + +/****************** Bit definition for TEMP_LTGR register ************************/ + +#define TEMP_LTGR_LTG_POSS 0U +#define TEMP_LTGR_LTG_POSE 20U +#define TEMP_LTGR_LTG_MSK BITS(TEMP_LTGR_LTG_POSS,TEMP_LTGR_LTG_POSE) + +/****************** Bit definition for TEMP_HTGR register ************************/ + +#define TEMP_HTGR_HTG_POSS 0U +#define TEMP_HTGR_HTG_POSE 20U +#define TEMP_HTGR_HTG_MSK BITS(TEMP_HTGR_HTG_POSS,TEMP_HTGR_HTG_POSE) + +/****************** Bit definition for TEMP_TBDR register ************************/ + +#define TEMP_TBDR_TBD_POSS 0U +#define TEMP_TBDR_TBD_POSE 15U +#define TEMP_TBDR_TBD_MSK BITS(TEMP_TBDR_TBD_POSS,TEMP_TBDR_TBD_POSE) + +/****************** Bit definition for TEMP_TCALBDR register ************************/ + +#define TEMP_TCALBDR_TCAL_POSS 0U +#define TEMP_TCALBDR_TCAL_POSE 16U +#define TEMP_TCALBDR_TCAL_MSK BITS(TEMP_TCALBDR_TCAL_POSS,TEMP_TCALBDR_TCAL_POSE) + +/****************** Bit definition for TEMP_SR register ************************/ + +#define TEMP_SR_TSOUT_POS 31U +#define TEMP_SR_TSOUT_MSK BIT(TEMP_SR_TSOUT_POS) + +#define TEMP_SR_NVLD_POS 25U +#define TEMP_SR_NVLD_MSK BIT(TEMP_SR_NVLD_POS) + +#define TEMP_SR_TCAL_POSS 0U +#define TEMP_SR_TCAL_POSE 24U +#define TEMP_SR_TCAL_MSK BITS(TEMP_SR_TCAL_POSS,TEMP_SR_TCAL_POSE) + +typedef struct +{ + __IO uint32_t WPR; + __IO uint32_t CR; + __I uint32_t DR; + __IO uint32_t PSR; + __IO uint32_t IE; + __I uint32_t IF; + __IO uint32_t IFCR; + __IO uint32_t LTGR; + __IO uint32_t HTGR; + __IO uint32_t TBDR; + __IO uint32_t TCALBDR; + __I uint32_t SR; +} TEMP_TypeDef; + +/****************** Bit definition for IWDT_LOAD register ************************/ + +#define IWDT_LOAD_LOAD_POSS 0U +#define IWDT_LOAD_LOAD_POSE 31U +#define IWDT_LOAD_LOAD_MSK BITS(IWDT_LOAD_LOAD_POSS,IWDT_LOAD_LOAD_POSE) + +/****************** Bit definition for IWDT_VALUE register ************************/ + +#define IWDT_VALUE_VALUE_POSS 0U +#define IWDT_VALUE_VALUE_POSE 31U +#define IWDT_VALUE_VALUE_MSK BITS(IWDT_VALUE_VALUE_POSS,IWDT_VALUE_VALUE_POSE) + +/****************** Bit definition for IWDT_CON register ************************/ + +#define IWDT_CON_CLKS_POS 3U +#define IWDT_CON_CLKS_MSK BIT(IWDT_CON_CLKS_POS) + +#define IWDT_CON_RSTEN_POS 2U +#define IWDT_CON_RSTEN_MSK BIT(IWDT_CON_RSTEN_POS) + +#define IWDT_CON_IE_POS 1U +#define IWDT_CON_IE_MSK BIT(IWDT_CON_IE_POS) + +#define IWDT_CON_EN_POS 0U +#define IWDT_CON_EN_MSK BIT(IWDT_CON_EN_POS) + +/****************** Bit definition for IWDT_INTCLR register ************************/ + +#define IWDT_INTCLR_INTCLR_POSS 0U +#define IWDT_INTCLR_INTCLR_POSE 31U +#define IWDT_INTCLR_INTCLR_MSK BITS(IWDT_INTCLR_INTCLR_POSS,IWDT_INTCLR_INTCLR_POSE) + +/****************** Bit definition for IWDT_RIS register ************************/ + +#define IWDT_RIS_WDTIF_POS 0U +#define IWDT_RIS_WDTIF_MSK BIT(IWDT_RIS_WDTIF_POS) + +/****************** Bit definition for IWDT_LOCK register ************************/ + +#define IWDT_LOCK_LOCK_POS 0U +#define IWDT_LOCK_LOCK_MSK BIT(IWDT_LOCK_LOCK_POS) + +typedef struct +{ + __O uint32_t LOAD; + __I uint32_t VALUE; + __IO uint32_t CON; + __O uint32_t INTCLR; + __I uint32_t RIS; + uint32_t RESERVED0[59] ; + __IO uint32_t LOCK; +} IWDT_TypeDef; + +/****************** Bit definition for WWDT_LOAD register ************************/ + +#define WWDT_LOAD_LOAD_POSS 0U +#define WWDT_LOAD_LOAD_POSE 31U +#define WWDT_LOAD_LOAD_MSK BITS(WWDT_LOAD_LOAD_POSS,WWDT_LOAD_LOAD_POSE) + +/****************** Bit definition for WWDT_VALUE register ************************/ + +#define WWDT_VALUE_VALUE_POSS 0U +#define WWDT_VALUE_VALUE_POSE 31U +#define WWDT_VALUE_VALUE_MSK BITS(WWDT_VALUE_VALUE_POSS,WWDT_VALUE_VALUE_POSE) + +/****************** Bit definition for WWDT_CON register ************************/ + +#define WWDT_CON_WWDTWIN_POSS 4U +#define WWDT_CON_WWDTWIN_POSE 5U +#define WWDT_CON_WWDTWIN_MSK BITS(WWDT_CON_WWDTWIN_POSS,WWDT_CON_WWDTWIN_POSE) + +#define WWDT_CON_CLKS_POS 3U +#define WWDT_CON_CLKS_MSK BIT(WWDT_CON_CLKS_POS) + +#define WWDT_CON_RSTEN_POS 2U +#define WWDT_CON_RSTEN_MSK BIT(WWDT_CON_RSTEN_POS) + +#define WWDT_CON_IE_POS 1U +#define WWDT_CON_IE_MSK BIT(WWDT_CON_IE_POS) + +#define WWDT_CON_EN_POS 0U +#define WWDT_CON_EN_MSK BIT(WWDT_CON_EN_POS) + +/****************** Bit definition for WWDT_INTCLR register ************************/ + +#define WWDT_INTCLR_INTCLR_POSS 0U +#define WWDT_INTCLR_INTCLR_POSE 31U +#define WWDT_INTCLR_INTCLR_MSK BITS(WWDT_INTCLR_INTCLR_POSS,WWDT_INTCLR_INTCLR_POSE) + +/****************** Bit definition for WWDT_RIS register ************************/ + +#define WWDT_RIS_WWDTIF_POS 0U +#define WWDT_RIS_WWDTIF_MSK BIT(WWDT_RIS_WWDTIF_POS) + +/****************** Bit definition for WWDT_LOCK register ************************/ + +#define WWDT_LOCK_LOCK_POS 0U +#define WWDT_LOCK_LOCK_MSK BIT(WWDT_LOCK_LOCK_POS) + +typedef struct +{ + __O uint32_t LOAD; + __I uint32_t VALUE; + __IO uint32_t CON; + __O uint32_t INTCLR; + __I uint32_t RIS; + uint32_t RESERVED0[59]; + __IO uint32_t LOCK; +} WWDT_TypeDef; + +/****************** Bit definition for LP16T_CON0 register ************************/ + +#define LP16T_CON0_PRELOAD_POS 22U +#define LP16T_CON0_PRELOAD_MSK BIT(LP16T_CON0_PRELOAD_POS) + +#define LP16T_CON0_WAVEPOL_POS 21U +#define LP16T_CON0_WAVEPOL_MSK BIT(LP16T_CON0_WAVEPOL_POS) + +#define LP16T_CON0_WAVE_POSS 19U +#define LP16T_CON0_WAVE_POSE 20U +#define LP16T_CON0_WAVE_MSK BITS(LP16T_CON0_WAVE_POSS,LP16T_CON0_WAVE_POSE) + +#define LP16T_CON0_TRIGEN_POSS 17U +#define LP16T_CON0_TRIGEN_POSE 18U +#define LP16T_CON0_TRIGEN_MSK BITS(LP16T_CON0_TRIGEN_POSS,LP16T_CON0_TRIGEN_POSE) + +#define LP16T_CON0_TRIGSEL_POSS 13U +#define LP16T_CON0_TRIGSEL_POSE 15U +#define LP16T_CON0_TRIGSEL_MSK BITS(LP16T_CON0_TRIGSEL_POSS,LP16T_CON0_TRIGSEL_POSE) + +#define LP16T_CON0_PRESC_POSS 9U +#define LP16T_CON0_PRESC_POSE 11U +#define LP16T_CON0_PRESC_MSK BITS(LP16T_CON0_PRESC_POSS,LP16T_CON0_PRESC_POSE) + +#define LP16T_CON0_TRGFLT_POSS 6U +#define LP16T_CON0_TRGFLT_POSE 7U +#define LP16T_CON0_TRGFLT_MSK BITS(LP16T_CON0_TRGFLT_POSS,LP16T_CON0_TRGFLT_POSE) + +#define LP16T_CON0_CKFLT_POSS 3U +#define LP16T_CON0_CKFLT_POSE 4U +#define LP16T_CON0_CKFLT_MSK BITS(LP16T_CON0_CKFLT_POSS,LP16T_CON0_CKFLT_POSE) + +#define LP16T_CON0_CKPOL_POS 1U +#define LP16T_CON0_CKPOL_MSK BIT(LP16T_CON0_CKPOL_POS) + +#define LP16T_CON0_CKSEL_POS 0U +#define LP16T_CON0_CKSEL_MSK BIT(LP16T_CON0_CKSEL_POS) + +/****************** Bit definition for LP16T_CON1 register ************************/ + +#define LP16T_CON1_CNTSTRT_POS 2U +#define LP16T_CON1_CNTSTRT_MSK BIT(LP16T_CON1_CNTSTRT_POS) + +#define LP16T_CON1_SNGSTRT_POS 1U +#define LP16T_CON1_SNGSTRT_MSK BIT(LP16T_CON1_SNGSTRT_POS) + +#define LP16T_CON1_ENABLE_POS 0U +#define LP16T_CON1_ENABLE_MSK BIT(LP16T_CON1_ENABLE_POS) + +/****************** Bit definition for LP16T_ARR register ************************/ + +#define LP16T_ARR_ARR_POSS 0U +#define LP16T_ARR_ARR_POSE 15U +#define LP16T_ARR_ARR_MSK BITS(LP16T_ARR_ARR_POSS,LP16T_ARR_ARR_POSE) + +/****************** Bit definition for LP16T_CNT register ************************/ + +#define LP16T_CNT_CNT_POSS 0U +#define LP16T_CNT_CNT_POSE 15U +#define LP16T_CNT_CNT_MSK BITS(LP16T_CNT_CNT_POSS,LP16T_CNT_CNT_POSE) + +/****************** Bit definition for LP16T_CMP register ************************/ + +#define LP16T_CMP_CMP_POSS 0U +#define LP16T_CMP_CMP_POSE 15U +#define LP16T_CMP_CMP_MSK BITS(LP16T_CMP_CMP_POSS,LP16T_CMP_CMP_POSE) + +/****************** Bit definition for LP16T_IER register ************************/ + +#define LP16T_IER_EXTTRIGIE_POS 2U +#define LP16T_IER_EXTTRIGIE_MSK BIT(LP16T_IER_EXTTRIGIE_POS) + +#define LP16T_IER_ARRMIE_POS 1U +#define LP16T_IER_ARRMIE_MSK BIT(LP16T_IER_ARRMIE_POS) + +#define LP16T_IER_CMPMIE_POS 0U +#define LP16T_IER_CMPMIE_MSK BIT(LP16T_IER_CMPMIE_POS) + +/****************** Bit definition for LP16T_ISR register ************************/ + +#define LP16T_ISR_EXTTRIG_POS 2U +#define LP16T_ISR_EXTTRIG_MSK BIT(LP16T_ISR_EXTTRIG_POS) + +#define LP16T_ISR_ARRM_POS 1U +#define LP16T_ISR_ARRM_MSK BIT(LP16T_ISR_ARRM_POS) + +#define LP16T_ISR_CMPM_POS 0U +#define LP16T_ISR_CMPM_MSK BIT(LP16T_ISR_CMPM_POS) + +/****************** Bit definition for LP16T_IFC register ************************/ + +#define LP16T_IFC_EXTTRIG_POS 2U +#define LP16T_IFC_EXTTRIG_MSK BIT(LP16T_IFC_EXTTRIG_POS) + +#define LP16T_IFC_ARRM_POS 1U +#define LP16T_IFC_ARRM_MSK BIT(LP16T_IFC_ARRM_POS) + +#define LP16T_IFC_CMPM_POS 0U +#define LP16T_IFC_CMPM_MSK BIT(LP16T_IFC_CMPM_POS) + +/****************** Bit definition for LP16T_UPDATE register ************************/ + +#define LP16T_UPDATE_UDIS_POS 0U +#define LP16T_UPDATE_UDIS_MSK BIT(LP16T_UPDATE_UDIS_POS) + +/****************** Bit definition for LP16T_SYNCSTAT register ************************/ + +#define LP16T_SYNCSTAT_CMPWBSY_POS 3U +#define LP16T_SYNCSTAT_CMPWBSY_MSK BIT(LP16T_SYNCSTAT_CMPWBSY_POS) + +#define LP16T_SYNCSTAT_ARRWBSY_POS 2U +#define LP16T_SYNCSTAT_ARRWBSY_MSK BIT(LP16T_SYNCSTAT_ARRWBSY_POS) + +#define LP16T_SYNCSTAT_CON1WBSY_POS 1U +#define LP16T_SYNCSTAT_CON1WBSY_MSK BIT(LP16T_SYNCSTAT_CON1WBSY_POS) + +typedef struct +{ + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t ARR; + __I uint32_t CNT; + __IO uint32_t CMP; + uint32_t RESERVED0 ; + __IO uint32_t IER; + __I uint32_t ISR; + __O uint32_t IFC; + uint32_t RESERVED1[3] ; + __IO uint32_t UPDATE; + __I uint32_t SYNCSTAT; +} LPTIM_TypeDef; + +/****************** Bit definition for DBGC_IDCODE register ************************/ + +#define DBGC_IDCODE_REV_ID_POSS 16U +#define DBGC_IDCODE_REV_ID_POSE 31U +#define DBGC_IDCODE_REV_ID_MSK BITS(DBGC_IDCODE_REV_ID_POSS,DBGC_IDCODE_REV_ID_POSE) + +#define DBGC_IDCODE_CORE_ID_POSS 12U +#define DBGC_IDCODE_CORE_ID_POSE 15U +#define DBGC_IDCODE_CORE_ID_MSK BITS(DBGC_IDCODE_CORE_ID_POSS,DBGC_IDCODE_CORE_ID_POSE) + +#define DBGC_IDCODE_DEV_ID_POSS 0U +#define DBGC_IDCODE_DEV_ID_POSE 11U +#define DBGC_IDCODE_DEV_ID_MSK BITS(DBGC_IDCODE_DEV_ID_POSS,DBGC_IDCODE_DEV_ID_POSE) + +/****************** Bit definition for DBGC_CR register ************************/ + +#define DBGC_CR_DBG_STANDBY_POS 3U +#define DBGC_CR_DBG_STANDBY_MSK BIT(DBGC_CR_DBG_STANDBY_POS) + +#define DBGC_CR_DBG_STOP2_POS 2U +#define DBGC_CR_DBG_STOP2_MSK BIT(DBGC_CR_DBG_STOP2_POS) + +#define DBGC_CR_DBG_STOP1_POS 1U +#define DBGC_CR_DBG_STOP1_MSK BIT(DBGC_CR_DBG_STOP1_POS) + +#define DBGC_CR_DBG_SLEEP_POS 0U +#define DBGC_CR_DBG_SLEEP_MSK BIT(DBGC_CR_DBG_SLEEP_POS) + +/****************** Bit definition for DBGC_APB1FZ register ************************/ + +#define DBGC_APB1FZ_CAN_STOP_POS 12U +#define DBGC_APB1FZ_CAN_STOP_MSK BIT(DBGC_APB1FZ_CAN_STOP_POS) + +#define DBGC_APB1FZ_I2C1_SMBUS_TO_POS 9U +#define DBGC_APB1FZ_I2C1_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C1_SMBUS_TO_POS) + +#define DBGC_APB1FZ_I2C0_SMBUS_TO_POS 8U +#define DBGC_APB1FZ_I2C0_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C0_SMBUS_TO_POS) + +#define DBGC_APB1FZ_TIM7_STOP_POS 7U +#define DBGC_APB1FZ_TIM7_STOP_MSK BIT(DBGC_APB1FZ_TIM7_STOP_POS) + +#define DBGC_APB1FZ_TIM6_STOP_POS 6U +#define DBGC_APB1FZ_TIM6_STOP_MSK BIT(DBGC_APB1FZ_TIM6_STOP_POS) + +#define DBGC_APB1FZ_TIM5_STOP_POS 5U +#define DBGC_APB1FZ_TIM5_STOP_MSK BIT(DBGC_APB1FZ_TIM5_STOP_POS) + +#define DBGC_APB1FZ_TIM4_STOP_POS 4U +#define DBGC_APB1FZ_TIM4_STOP_MSK BIT(DBGC_APB1FZ_TIM4_STOP_POS) + +#define DBGC_APB1FZ_TIM3_STOP_POS 3U +#define DBGC_APB1FZ_TIM3_STOP_MSK BIT(DBGC_APB1FZ_TIM3_STOP_POS) + +#define DBGC_APB1FZ_TIM2_STOP_POS 2U +#define DBGC_APB1FZ_TIM2_STOP_MSK BIT(DBGC_APB1FZ_TIM2_STOP_POS) + +#define DBGC_APB1FZ_TIM1_STOP_POS 1U +#define DBGC_APB1FZ_TIM1_STOP_MSK BIT(DBGC_APB1FZ_TIM1_STOP_POS) + +#define DBGC_APB1FZ_TIM0_STOP_POS 0U +#define DBGC_APB1FZ_TIM0_STOP_MSK BIT(DBGC_APB1FZ_TIM0_STOP_POS) + +/****************** Bit definition for DBGC_APB2FZ register ************************/ + +#define DBGC_APB2FZ_RTC_STOP_POS 10U +#define DBGC_APB2FZ_RTC_STOP_MSK BIT(DBGC_APB2FZ_RTC_STOP_POS) + +#define DBGC_APB2FZ_WWDT_STOP_POS 9U +#define DBGC_APB2FZ_WWDT_STOP_MSK BIT(DBGC_APB2FZ_WWDT_STOP_POS) + +#define DBGC_APB2FZ_IWDT_STOP_POS 8U +#define DBGC_APB2FZ_IWDT_STOP_MSK BIT(DBGC_APB2FZ_IWDT_STOP_POS) + +#define DBGC_APB2FZ_LPTIM0_STOP_POS 0U +#define DBGC_APB2FZ_LPTIM0_STOP_MSK BIT(DBGC_APB2FZ_LPTIM0_STOP_POS) + +typedef struct +{ + __I uint32_t IDCODE; + __IO uint32_t CR; + __IO uint32_t APB1FZ; + __IO uint32_t APB2FZ; +} DBGC_TypeDef; + + +/* Base addresses */ +#define SRAM_BASE (0x20000000UL) +#define APB1_BASE (0x40000000UL) +#define APB2_BASE (0x40040000UL) +#define AHB_BASE (0x40080000UL) + +/* Timer memory map */ +#define TIMER0_BASE (APB1_BASE + 0x0000) +#define TIMER1_BASE (APB1_BASE + 0x0400) +#define TIMER2_BASE (APB1_BASE + 0x0800) +#define TIMER3_BASE (APB1_BASE + 0x0C00) +#define TIMER4_BASE (APB1_BASE + 0x1000) +#define TIMER5_BASE (APB1_BASE + 0x1400) +#define TIMER6_BASE (APB1_BASE + 0x1800) +#define TIMER7_BASE (APB1_BASE + 0x1C00) + +/* SPI memory map */ +#define SPI0_BASE (APB1_BASE + 0x6000) +#define SPI1_BASE (APB1_BASE + 0x6400) +#define SPI2_BASE (APB1_BASE + 0x6800) + +/* I2C memory map */ +#define I2C0_BASE (APB1_BASE + 0x8000) +#define I2C1_BASE (APB1_BASE + 0x8400) + +/* AHB peripherals */ +#define SYSTEM_BASE (AHB_BASE + 0x0000) +#define GPIOA_BASE (AHB_BASE + 0x4000) +#define GPIOB_BASE (AHB_BASE + 0x4040) +#define GPIOC_BASE (AHB_BASE + 0x4080) +#define GPIOD_BASE (AHB_BASE + 0x40C0) +#define GPIOE_BASE (AHB_BASE + 0x4100) +#define GPIOF_BASE (AHB_BASE + 0x4140) +#define GPIOG_BASE (AHB_BASE + 0x4180) +#define GPIOH_BASE (AHB_BASE + 0x41C0) +#define EXTI_BASE (AHB_BASE + 0x4300) +#define CRC_BASE (AHB_BASE + 0x5000) +#define CALC_BASE (AHB_BASE + 0x5400) +#define TRNG_BASE (AHB_BASE + 0x5C00) +#define CRYPT_BASE (AHB_BASE + 0x5800) + +#define SYSCFG_BASE (SYSTEM_BASE + 0x0000) +#define CMU_BASE (SYSTEM_BASE + 0x0400) +#define RMU_BASE (SYSTEM_BASE + 0x0800) +#define PMU_BASE (SYSTEM_BASE + 0x0C00) +#define MSC_BASE (SYSTEM_BASE + 0x1000) +#define PIS_BASE (SYSTEM_BASE + 0x6000) + +/* APB1 peripherals */ +#define CAN0_BASE (APB1_BASE + 0xB000) +#define USART0_BASE (APB1_BASE + 0x5000) +#define USART1_BASE (APB1_BASE + 0x5400) +#define UART0_BASE (APB1_BASE + 0x4000) +#define UART1_BASE (APB1_BASE + 0x4400) +#define UART2_BASE (APB1_BASE + 0x4800) +#define UART3_BASE (APB1_BASE + 0x4C00) +#define DMA0_BASE (APB1_BASE + 0xC000) + +/* APB2 peripherals */ +#define LPTIM0_BASE (APB2_BASE + 0x0000) +#define LPUART0_BASE (APB2_BASE + 0x1000) +#define DBGC_BASE (APB2_BASE + 0xA000) +#define WWDT_BASE (APB2_BASE + 0x6000) +#define IWDT_BASE (APB2_BASE + 0x6400) +#define RTC_BASE (APB2_BASE + 0x8400) +#define LCD_BASE (APB2_BASE + 0x7000) +#define ADC0_BASE (APB2_BASE + 0x2000) +#define ADC1_BASE (APB2_BASE + 0x2400) +#define ACMP0_BASE (APB2_BASE + 0x3000) +#define ACMP1_BASE (APB2_BASE + 0x3400) +#define OPAMP_BASE (APB2_BASE + 0x4000) +#define DAC0_BASE (APB2_BASE + 0x5000) +#define BKPC_BASE (APB2_BASE + 0x8000) +#define TEMP_BASE (APB2_BASE + 0x8800) + +/* RTC Peripheral declaration */ +#define RTC ((RTC_TypeDef *)RTC_BASE) + +/* GPIO Peripheral_declaration */ +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *)GPIOH_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) + +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define TRNG ((TRNG_TypeDef *)TRNG_BASE) +#define CALC ((CALC_TypeDef *)CALC_BASE) +#define CRYPT ((CRYPT_TypeDef *)CRYPT_BASE) +#define PIS ((PIS_TypeDef *)PIS_BASE) + +/* LCD Peripheral declaration */ +#define LCD ((LCD_TypeDef *)LCD_BASE) +/* ADC Peripheral declaration */ +#define ADC0 ((ADC_TypeDef *)ADC0_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +/* ACMP Peripheral declaration */ +#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) +#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) +/* OPAMP Peripheral declaration */ +#define OPAMP ((OPAMP_TypeDef *)OPAMP_BASE) +/* DAC Peripheral declaration */ +#define DAC0 ((DAC_TypeDef *)DAC0_BASE) +/* TEMP Peripheral declaration */ +#define TEMP ((TEMP_TypeDef *)TEMP_BASE) +/* BKPC Peripheral declaration */ +#define BKPC ((BKPC_TypeDef *)BKPC_BASE) + +/* Timer Peripheral_declaration */ +#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) +#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) +#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) +#define TIMER3 ((TIMER_TypeDef *)TIMER3_BASE) +#define TIMER4 ((TIMER_TypeDef *)TIMER4_BASE) +#define TIMER5 ((TIMER_TypeDef *)TIMER5_BASE) +#define TIMER6 ((TIMER_TypeDef *)TIMER6_BASE) +#define TIMER7 ((TIMER_TypeDef *)TIMER7_BASE) + +#define AD16C4T0 TIMER0 +#define GP16C4T0 TIMER6 +#define GP16C2T0 TIMER2 +#define GP16C2T1 TIMER3 +#define BS16T0 TIMER1 +#define BS16T1 TIMER4 +#define BS16T2 TIMER5 +#define BS16T3 TIMER7 + +/* SPI Peripheral_declaration */ +#define SPI0 ((SPI_TypeDef *)SPI0_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) + +/* I2C Peripheral_declaration */ +#define I2C0 ((I2C_TypeDef *)I2C0_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) + +/* CAN Peripheral_declaration */ +#define CAN0 ((CAN_TypeDef *)CAN0_BASE) + +/* DMA Peripheral_declaration */ +#define DMA0 ((DMA_TypeDef *)DMA0_BASE) + +/* UART Peripheral_declaration */ +#define USART0 ((USART_TypeDef *)USART0_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define UART0 ((UART_TypeDef *)UART0_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define UART3 ((UART_TypeDef *)UART3_BASE) +#define LPTIM0 ((LPTIM_TypeDef *)LPTIM0_BASE) +#define LPUART0 ((LPUART_TypeDef *)LPUART0_BASE) +#define DBGC ((DBGC_TypeDef *)DBGC_BASE) +#define WWDT ((WWDT_TypeDef *)WWDT_BASE) +#define IWDT ((IWDT_TypeDef *)IWDT_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *)SYSCFG_BASE) +#define CMU ((CMU_TypeDef *)CMU_BASE) +#define RMU ((RMU_TypeDef *)RMU_BASE) +#define PMU ((PMU_TypeDef *)PMU_BASE) +#define MSC ((MSC_TypeDef *)MSC_BASE) + +#endif diff --git a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s b/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s new file mode 100644 index 0000000000..265c345fb1 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s @@ -0,0 +1,266 @@ +;******************************************************************************* +; file : startup_es32f065x.s +; description: es32f065x Device Startup File +; author : AE Team +; data : 10 Dec 2018 +; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. +;******************************************************************************* + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ;0, load top of stack + DCD Reset_Handler ;1, reset handler + DCD NMI_Handler ;2, nmi handler + DCD HardFault_Handler ;3, hard fault handler + DCD 0 ;4, MPU Fault Handler + DCD 0 ;5, Bus Fault Handler + DCD 0 ;6, Usage Fault Handler + DCD 0 ;7, Reserved + DCD 0 ;8, Reserved + DCD 0 ;9, Reserved + DCD 0 ;10, Reserved + DCD SVC_Handler ;11, svcall handler + DCD DebugMon_Handler ;12, Debug Monitor Handler + DCD 0 ;13, Reserved + DCD PendSV_Handler ;14, pendsv handler + DCD SysTick_Handler ;15, systick handler + DCD WWDG_IWDG_Handler ;16, irq0 WWDG_IWDG handler + DCD LVD_Handler ;17, irq1 LVD handler + DCD RTC_TEMP_Handler ;18, irq2 RTC handler + DCD CRYPT_TRNG_Handler ;19, irq3 CRYPT handler + DCD CMU_Handler ;20, irq4 CMU handler + DCD EXTI0_3_Handler ;21, irq5 EXTI0_3 handler + DCD EXTI4_7_Handler ;22, irq6 EXTI4_7 handler + DCD EXTI8_11_Handler ;23, irq7 EXTI8_11 handler + DCD EXTI12_15_Handler ;24, irq8 EXTI12_15 handler + DCD DMA_Handler ;25, irq9 DMA handler + DCD CAN0_Handler ;26, irq10 CAN0_CRYPT_TRNG handler + DCD LPTIM0_SPI2_Handler ;27, irq11 LPTIM0_SPI2 handler + DCD ADC_ACMP_Handler ;28, irq12 ADC_ACMP handler + DCD AD16C4T0_BRK_UP_TRIG_COM_Handler ;29, irq13 AD16C4T0_BRK_UP_TRIG_COM handler + DCD AD16C4T0_CC_Handler ;30, irq14 AD16C4T0_CC handler + DCD BS16T0_Handler ;31, irq15 BS16T0 handler + DCD 0 ;32, irq16 Reserved + DCD GP16C2T0_Handler ;33, irq17 GP16C2T0 handler + DCD GP16C2T1_Handler ;34, irq18 GP16C2T1 handler + DCD BS16T1_UART2_Handler ;35, irq19 BS16T1_UART2 handler + DCD BS16T2_UART3_Handler ;36, irq20 BS16T2_UART3 handler + DCD GP16C4T0_LCD_Handler ;37, irq21 GP16C4T0_LCD handler + DCD BS16T3_DAC0_Handler ;38, irq22 BS16T3_DAC0 handler + DCD I2C0_Handler ;39, irq23 I2C0 handler + DCD I2C1_Handler ;40, irq24 I2C1 handler + DCD SPI0_Handler ;41, irq25 SPI0 handler + DCD SPI1_Handler ;42, irq26 SPI1 handler + DCD UART0_Handler ;43, irq27 UART0 handler + DCD UART1_Handler ;44, irq28 UART1 handler + DCD USART0_Handler ;45, irq29 USART0 handler + DCD USART1_Handler ;46, irq30 USART1 handler + DCD LPUART0_Handler ;47, irq31 LPUART0 handler + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IWDG_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IWDG_Handler + B WWDG_IWDG_Handler + + PUBWEAK LVD_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_Handler + B LVD_Handler + + PUBWEAK RTC_TEMP_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_TEMP_Handler + B RTC_TEMP_Handler + + PUBWEAK CRYPT_TRNG_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYPT_TRNG_Handler + B CRYPT_TRNG_Handler + + PUBWEAK CMU_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CMU_Handler + B CMU_Handler + + PUBWEAK EXTI0_3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_3_Handler + B EXTI0_3_Handler + + PUBWEAK EXTI4_7_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_7_Handler + B EXTI4_7_Handler + + PUBWEAK EXTI8_11_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI8_11_Handler + B EXTI8_11_Handler + + PUBWEAK EXTI12_15_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI12_15_Handler + B EXTI12_15_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_Handler + B DMA_Handler + + PUBWEAK CAN0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_Handler + B CAN0_Handler + + PUBWEAK LPTIM0_SPI2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM0_SPI2_Handler + B LPTIM0_SPI2_Handler + + PUBWEAK ADC_ACMP_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_ACMP_Handler + B ADC_ACMP_Handler + + PUBWEAK AD16C4T0_BRK_UP_TRIG_COM_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T0_BRK_UP_TRIG_COM_Handler + B AD16C4T0_BRK_UP_TRIG_COM_Handler + + PUBWEAK AD16C4T0_CC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T0_CC_Handler + B AD16C4T0_CC_Handler + + PUBWEAK BS16T0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BS16T0_Handler + B BS16T0_Handler + + PUBWEAK GP16C2T0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C2T0_Handler + B GP16C2T0_Handler + + PUBWEAK GP16C2T1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C2T1_Handler + B GP16C2T1_Handler + + PUBWEAK BS16T1_UART2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BS16T1_UART2_Handler + B BS16T1_UART2_Handler + + PUBWEAK BS16T2_UART3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BS16T2_UART3_Handler + B BS16T2_UART3_Handler + + PUBWEAK GP16C4T0_LCD_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C4T0_LCD_Handler + B GP16C4T0_LCD_Handler + + PUBWEAK BS16T3_DAC0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BS16T3_DAC0_Handler + B BS16T3_DAC0_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK SPI0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_Handler + B SPI0_Handler + + PUBWEAK SPI1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_Handler + B SPI1_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_Handler + B UART1_Handler + + PUBWEAK USART0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_Handler + B USART0_Handler + + PUBWEAK USART1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_Handler + B USART1_Handler + + PUBWEAK LPUART0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART0_Handler + B LPUART0_Handler + + END diff --git a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s b/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s new file mode 100644 index 0000000000..6bf19bc877 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s @@ -0,0 +1,335 @@ +;******************************************************************************* +; file : startup_es32f065x.s +; description: es32f065x Device Startup File +; author : AE Team +; data : 29 Aug 2017 +; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. +;******************************************************************************* + +;Stack Configuration------------------------------------------------------------ +Stack_Size EQU 0x00000400 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp +;------------------------------------------------------------------------------- + +;Heap Configuration------------------------------------------------------------- +Heap_Size EQU 0x00000000 + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit +;------------------------------------------------------------------------------- + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset------------------------------------- + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ;0, load top of stack + DCD Reset_Handler ;1, reset handler + DCD NMI_Handler ;2, nmi handler + DCD HardFault_Handler ;3, hard fault handler + DCD 0 ;4, MPU Fault Handler + DCD 0 ;5, Bus Fault Handler + DCD 0 ;6, Usage Fault Handler + DCD 0 ;7, Reserved + DCD 0 ;8, Reserved + DCD 0 ;9, Reserved + DCD 0 ;10, Reserved + DCD SVC_Handler ;11, svcall handler + DCD DebugMon_Handler ;12, Debug Monitor Handler + DCD 0 ;13, Reserved + DCD PendSV_Handler ;14, pendsv handler + DCD SysTick_Handler ;15, systick handler + DCD WWDG_IWDG_Handler ;16, irq0 WWDG_IWDG handler + DCD LVD_Handler ;17, irq1 LVD handler + DCD RTC_TEMP_Handler ;18, irq2 RTC handler + DCD CRYPT_TRNG_Handler ;19, irq3 CRYPT handler + DCD CMU_Handler ;20, irq4 CMU handler + DCD EXTI0_3_Handler ;21, irq5 EXTI0_3 handler + DCD EXTI4_7_Handler ;22, irq6 EXTI4_7 handler + DCD EXTI8_11_Handler ;23, irq7 EXTI8_11 handler + DCD EXTI12_15_Handler ;24, irq8 EXTI12_15 handler + DCD DMA_Handler ;25, irq9 DMA handler + DCD CAN0_Handler ;26, irq10 CAN0_CRYPT_TRNG handler + DCD LPTIM0_SPI2_Handler ;27, irq11 LPTIM0_SPI2 handler + DCD ADC_ACMP_Handler ;28, irq12 ADC_ACMP handler + DCD AD16C4T0_BRK_UP_TRIG_COM_Handler ;29, irq13 AD16C4T0_BRK_UP_TRIG_COM handler + DCD AD16C4T0_CC_Handler ;30, irq14 AD16C4T0_CC handler + DCD BS16T0_Handler ;31, irq15 BS16T0 handler + DCD 0 ;32, irq16 Reserved + DCD GP16C2T0_Handler ;33, irq17 GP16C2T0 handler + DCD GP16C2T1_Handler ;34, irq18 GP16C2T1 handler + DCD BS16T1_UART2_Handler ;35, irq19 BS16T1_UART2 handler + DCD BS16T2_UART3_Handler ;36, irq20 BS16T2_UART3 handler + DCD GP16C4T0_LCD_Handler ;37, irq21 GP16C4T0_LCD handler + DCD BS16T3_DAC0_Handler ;38, irq22 BS16T3_DAC0 handler + DCD I2C0_Handler ;39, irq23 I2C0 handler + DCD I2C1_Handler ;40, irq24 I2C1 handler + DCD SPI0_Handler ;41, irq25 SPI0 handler + DCD SPI1_Handler ;42, irq26 SPI1 handler + DCD UART0_Handler ;43, irq27 UART0 handler + DCD UART1_Handler ;44, irq28 UART1 handler + DCD USART0_Handler ;45, irq29 USART0 handler + DCD USART1_Handler ;46, irq30 USART1 handler + DCD LPUART0_Handler ;47, irq31 LPUART0 handler + +;------------------------------------------------------------------------------- + AREA INT, CODE, READONLY ;code begin + +;Reset Handler---------------------------------------------- +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + LDR R0, =__main + BX R0 + NOP + ALIGN + ENDP + +;system int------------------------------------------------- +NMI_Handler PROC ;int 2 + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler \ + PROC ;int3 + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler \ + PROC ;int11 + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler \ + PROC ;int12 + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC ;int14 + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler \ + PROC ;int15 + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +;peripheral module int ----------------------------------------------- +WWDG_IWDG_Handler \ + PROC ;int16 + EXPORT WWDG_IWDG_Handler [WEAK] + B . + ENDP + +LVD_Handler \ + PROC ;int17 + EXPORT LVD_Handler [WEAK] + B . + ENDP + +RTC_TEMP_Handler \ + PROC ;int18 + EXPORT RTC_TEMP_Handler [WEAK] + B . + ENDP + +CRYPT_TRNG_Handler \ + PROC ;int19 + EXPORT CRYPT_TRNG_Handler [WEAK] + B . + ENDP + +CMU_Handler \ + PROC ;int20 + EXPORT CMU_Handler [WEAK] + B . + ENDP + +EXTI0_3_Handler \ + PROC ;int21 + EXPORT EXTI0_3_Handler [WEAK] + B . + ENDP + +EXTI4_7_Handler \ + PROC ;int22 + EXPORT EXTI4_7_Handler [WEAK] + B . + ENDP + +EXTI8_11_Handler \ + PROC ;int23 + EXPORT EXTI8_11_Handler [WEAK] + B . + ENDP + +EXTI12_15_Handler \ + PROC ;int24 + EXPORT EXTI12_15_Handler [WEAK] + B . + ENDP + +DMA_Handler \ + PROC ;int25 + EXPORT DMA_Handler [WEAK] + B . + ENDP + +CAN0_Handler \ + PROC ;int26 + EXPORT CAN0_Handler [WEAK] + B . + ENDP + +LPTIM0_SPI2_Handler \ + PROC ;int27 + EXPORT LPTIM0_SPI2_Handler [WEAK] + B . + ENDP + +ADC_ACMP_Handler \ + PROC ;int28 + EXPORT ADC_ACMP_Handler [WEAK] + B . + ENDP + +AD16C4T0_BRK_UP_TRIG_COM_Handler \ + PROC ;int29 + EXPORT AD16C4T0_BRK_UP_TRIG_COM_Handler [WEAK] + B . + ENDP + +AD16C4T0_CC_Handler \ + PROC ;int30 + EXPORT AD16C4T0_CC_Handler [WEAK] + B . + ENDP + +BS16T0_Handler \ + PROC ;int31 + EXPORT BS16T0_Handler [WEAK] + B . + ENDP + +GP16C2T0_Handler PROC ;int33 + EXPORT GP16C2T0_Handler [WEAK] + B . + ENDP + +GP16C2T1_Handler PROC ;int34 + EXPORT GP16C2T1_Handler [WEAK] + B . + ENDP + +BS16T1_UART2_Handler \ + PROC ;int35 + EXPORT BS16T1_UART2_Handler [WEAK] + B . + ENDP + +BS16T2_UART3_Handler \ + PROC ;int36 + EXPORT BS16T2_UART3_Handler [WEAK] + B . + ENDP + +GP16C4T0_LCD_Handler \ + PROC ;int37 + EXPORT GP16C4T0_LCD_Handler [WEAK] + B . + ENDP + +BS16T3_DAC0_Handler \ + PROC ;int38 + EXPORT BS16T3_DAC0_Handler [WEAK] + B . + ENDP + +I2C0_Handler \ + PROC ;int39 + EXPORT I2C0_Handler [WEAK] + B . + ENDP + +I2C1_Handler \ + PROC ;int40 + EXPORT I2C1_Handler [WEAK] + B . + ENDP + +SPI0_Handler \ + PROC ;int41 + EXPORT SPI0_Handler [WEAK] + B . + ENDP + +SPI1_Handler \ + PROC ;int42 + EXPORT SPI1_Handler [WEAK] + B . + ENDP + +UART0_Handler \ + PROC ;int43 + EXPORT UART0_Handler [WEAK] + B . + ENDP + +UART1_Handler \ + PROC ;int44 + EXPORT UART1_Handler [WEAK] + B . + ENDP + +USART0_Handler \ + PROC ;int45 + EXPORT USART0_Handler [WEAK] + B . + ENDP + +USART1_Handler \ + PROC ;int46 + EXPORT USART1_Handler [WEAK] + B . + ENDP + +LPUART0_Handler \ + PROC ;int47 + EXPORT LPUART0_Handler [WEAK] + B . + ENDP + +; User Initial Stack & Heap----------------------------------------------------- + ALIGN + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/System/system_es32f065x.c b/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/System/system_es32f065x.c new file mode 100644 index 0000000000..a8208bb3ab --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/System/system_es32f065x.c @@ -0,0 +1,28 @@ +/** + ********************************************************************************* + * + * @file system_es32f065x.c + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer + * + * @version V1.0 + * @date 6 Dec 2018 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "utils.h" + + +/** + * @brief Configuring system clock before startup. + * @note This function must be used after reset. + * @retval None + */ +void system_init (void) +{ + /* do nothing */ +} \ No newline at end of file diff --git a/bsp/es32f0654/libraries/CMSIS/Include/arm_common_tables.h b/bsp/es32f0654/libraries/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000000..8742a56991 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. October 2015 +* $Revision: V.1.4.5 a +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +/* extern const q31_t realCoefAQ31[1024]; */ +/* extern const q31_t realCoefBQ31[1024]; */ +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/arm_const_structs.h b/bsp/es32f0654/libraries/CMSIS/Include/arm_const_structs.h new file mode 100644 index 0000000000..726d06eb69 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. March 2015 +* $Revision: V.1.4.5 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/es32f0654/libraries/CMSIS/Include/arm_math.h b/bsp/es32f0654/libraries/CMSIS/Include/arm_math.h new file mode 100644 index 0000000000..d33f8a9b3b --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/arm_math.h @@ -0,0 +1,7154 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2015 ARM Limited. All rights reserved. +* +* $Date: 20. October 2015 +* $Revision: V1.4.5 b +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *

+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __GNUC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __ICCARM__ + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + +#elif defined __CSMC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + +#elif defined __TASKING__ + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) + static __INLINE uint32_t __CLZ( + q31_t data); + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + } +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + } +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc.h b/bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000..74c49c67de --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc_V6.h b/bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc_V6.h new file mode 100644 index 0000000000..cd13240ce3 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc_V6.h @@ -0,0 +1,1800 @@ +/**************************************************************************//** + * @file cmsis_armcc_V6.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_V6_H +#define __CMSIS_ARMCC_V6_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get IPSR Register (non-secure) + \details Returns the content of the non-secure IPSR Register when in secure state. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get APSR Register (non-secure) + \details Returns the content of the non-secure APSR Register when in secure state. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get xPSR Register (non-secure) + \details Returns the content of the non-secure xPSR Register when in secure state. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority with condition (non_secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + + +#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ + +/** + \brief Get FPSCR + \details eturns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get FPSCR (non-secure) + \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set FPSCR (non-secure) + \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +/*#define __SSAT __builtin_arm_ssat*/ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat +#if 0 +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) +#endif + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1U) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/cmsis_gcc.h b/bsp/es32f0654/libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000..bb89fbba9e --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm0.h b/bsp/es32f0654/libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000..a2c7335f68 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,668 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.02 + * @date 16. July 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#endif /* __CORE_CM0_H_GENERIC */ + + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm0plus.h b/bsp/es32f0654/libraries/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000..b04aa39053 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,914 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm3.h b/bsp/es32f0654/libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..b4ac4c7b05 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1763 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm4.h b/bsp/es32f0654/libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000..dc840ebf22 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm7.h b/bsp/es32f0654/libraries/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000000..3b7530ad50 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/core_cm7.h @@ -0,0 +1,2512 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + { + return 2UL; /* Double + Single precision FPU */ + } + else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + { + return 1UL; /* Single precision FPU */ + } + else + { + return 0UL; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cmFunc.h b/bsp/es32f0654/libraries/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000000..0a18fafc30 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,636 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cmInstr.h b/bsp/es32f0654/libraries/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000000..d213f0eed7 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,688 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.20 + * @date 05. March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cmSimd.h b/bsp/es32f0654/libraries/CMSIS/Include/core_cmSimd.h new file mode 100644 index 0000000000..66bf5c2a72 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_sc000.h b/bsp/es32f0654/libraries/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000..514dbd81b9 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/core_sc000.h @@ -0,0 +1,926 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_sc300.h b/bsp/es32f0654/libraries/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000..8bd18aa318 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/Include/core_sc300.h @@ -0,0 +1,1745 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/es32f0654/libraries/CMSIS/RTOS/Template/cmsis_os.h b/bsp/es32f0654/libraries/CMSIS/RTOS/Template/cmsis_os.h new file mode 100644 index 0000000000..02930af3e6 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/RTOS/Template/cmsis_os.h @@ -0,0 +1,707 @@ +/* ---------------------------------------------------------------------- + * $Date: 5. February 2013 + * $Revision: V1.02 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h template header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedef's + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + *---------------------------------------------------------------------------- + * + * Copyright (c) 2013 ARM LIMITED + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + + +#ifndef _CMSIS_OS_H +#define _CMSIS_OS_H + +/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) + +/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. +#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string + +/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. +#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 30 ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumeration, structures, defines ==== + +/// Priority used for thread control. +/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. +typedef enum { + osPriorityIdle = -3, ///< priority: idle (lowest) + osPriorityLow = -2, ///< priority: low + osPriorityBelowNormal = -1, ///< priority: below normal + osPriorityNormal = 0, ///< priority: normal (default) + osPriorityAboveNormal = +1, ///< priority: above normal + osPriorityHigh = +2, ///< priority: high + osPriorityRealtime = +3, ///< priority: realtime (highest) + osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority +} osPriority; + +/// Timeout value. +/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. +#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value + +/// Status code values returned by CMSIS-RTOS functions. +/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. +typedef enum { + osOK = 0, ///< function completed; no error or event occurred. + osEventSignal = 0x08, ///< function completed; signal event occurred. + osEventMessage = 0x10, ///< function completed; message event occurred. + osEventMail = 0x20, ///< function completed; mail event occurred. + osEventTimeout = 0x40, ///< function completed; timeout occurred. + osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< value of a parameter is out of range. + osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. + os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. +} osStatus; + + +/// Timer type value for the timer definition. +/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. +typedef enum { + osTimerOnce = 0, ///< one-shot timer + osTimerPeriodic = 1 ///< repeating timer +} os_timer_type; + +/// Entry point of a thread. +/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. +typedef void (*os_ptimer) (void const *argument); + +// >>> the following data type definitions may shall adapted towards a specific RTOS + +/// Thread ID identifies the thread (pointer to a thread control block). +/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_cb *osThreadId; + +/// Timer ID identifies the timer (pointer to a timer control block). +/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_cb *osTimerId; + +/// Mutex ID identifies the mutex (pointer to a mutex control block). +/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_cb *osMutexId; + +/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). +/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_cb *osSemaphoreId; + +/// Pool ID identifies the memory pool (pointer to a memory pool control block). +/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_cb *osPoolId; + +/// Message ID identifies the message queue (pointer to a message queue control block). +/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_cb *osMessageQId; + +/// Mail ID identifies the mail queue (pointer to a mail queue control block). +/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_cb *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value. +} osMutexDef_t; + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value. +} osSemaphoreDef_t; + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for messages +} osMessageQDef_t; + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; + +/// Event structure contains detailed information about an event. +/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. +/// However the struct may be extended at the end. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Control Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. +osStatus osKernelInitialize (void); + +/// Start the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +osStatus osKernelStart (void); + +/// Check if the RTOS kernel is already started. +/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +/// \return 0 RTOS is not started, 1 RTOS is started. +int32_t osKernelRunning(void); + +#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter +/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. +/// \return RTOS kernel system timer as 32-bit value +uint32_t osKernelSysTick (void); + +/// The RTOS kernel system timer frequency in Hz +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#define osKernelSysTickFrequency 100000000 + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) + +#endif // System Timer available + +// ==== Thread Management ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), (instances), (stacksz) } +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +osThreadId osThreadGetId (void); + +/// Terminate execution of a thread and remove it from Active Threads. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +osStatus osThreadTerminate (osThreadId thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +osStatus osThreadYield (void); + +/// Change priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); + +/// Get current priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the thread function. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +osPriority osThreadGetPriority (osThreadId thread_id); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec time delay value +/// \return status code that indicates the execution status of the function. +osStatus osDelay (uint32_t millisec); + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function) } +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec time delay value of the timer. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); + +/// Stop the timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +osStatus osTimerStop (osTimerId timer_id); + +/// Delete a timer that was created by \ref osTimerCreate. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. +osStatus osTimerDelete (osTimerId timer_id); + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. +/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event flag information or error code. +/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Mutex Management ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0 } +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +osStatus osMutexRelease (osMutexId mutex_id); + +/// Delete a Mutex that was created by \ref osMutexCreate. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. +osStatus osMutexDelete (osMutexId mutex_id); + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object used for managing resources. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count number of available resources. +/// \return semaphore ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); + +/// Delete a Semaphore that was created by \ref osSemaphoreCreate. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a memory pool. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a memory pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a specific memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block that is returned to the memory pool. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool Management available + + +// ==== Message Queue Management Functions ==== + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue. +/// \param[in] queue_def queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message or Wait for a Message from a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event information that includes status code. +/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queues available + + +// ==== Mail Queue Management Functions ==== + +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue +/// \param queue_sz maximum number of messages in queue +/// \param type data type of a single message element +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern const osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize mail queue. +/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block from a mail and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a mail to a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +osStatus osMailPut (osMailQId queue_id, void *mail); + +/// Get a mail from a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queues available + + +#ifdef __cplusplus +} +#endif + +#endif // _CMSIS_OS_H diff --git a/bsp/es32f0654/libraries/CMSIS/index.html b/bsp/es32f0654/libraries/CMSIS/index.html new file mode 100644 index 0000000000..c6da0802b4 --- /dev/null +++ b/bsp/es32f0654/libraries/CMSIS/index.html @@ -0,0 +1,14 @@ + + + +Redirect to the CMSIS main page after 0 seconds + + + + + + +If the automatic redirection is failing, click open CMSIS Documentation. + + + diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h new file mode 100644 index 0000000000..8c39f28af2 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h @@ -0,0 +1,374 @@ +/** + ********************************************************************************* + * + * @file ald_acmp.h + * @brief Header file of ACMP module driver. + * + * @version V1.0 + * @date 13 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_ACMP_H__ +#define __ALD_ACMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup ACMP + * @{ + */ + +/** @defgroup ACMP_Public_Types ACMP Public Types + * @{ + */ + +/** + * @brief Acmp interrupt + */ +typedef enum +{ + ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */ + ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */ +} acmp_it_t; + +/** + * @brief Acmp interrupt + */ +typedef enum +{ + ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */ + ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */ +} acmp_flag_t; + +/** + * @brief Acmp interrupt flag + */ +typedef enum +{ + ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */ + ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */ +} acmp_status_t; + +/** + * @brief Acmp positive input + */ +typedef enum +{ + ACMP_POS_CH0 = 0, /**< Channel 0 as positive input */ + ACMP_POS_CH1 = 1, /**< Channel 1 as positive input */ + ACMP_POS_CH2 = 2, /**< Channel 2 as positive input */ + ACMP_POS_CH3 = 3, /**< Channel 3 as positive input */ + ACMP_POS_CH4 = 4, /**< Channel 4 as positive input */ + ACMP_POS_CH5 = 5, /**< Channel 5 as positive input */ + ACMP_POS_CH6 = 6, /**< Channel 6 as positive input */ + ACMP_POS_CH7 = 7, /**< Channel 7 as positive input */ +} acmp_pos_input_t; + +/** + * @brief Acmp negative input + */ +typedef enum +{ + ACMP_NEG_CH0 = 0, /**< Channel 0 as negative input */ + ACMP_NEG_CH1 = 1, /**< Channel 1 as negative input */ + ACMP_NEG_CH2 = 2, /**< Channel 2 as negative input */ + ACMP_NEG_CH3 = 3, /**< Channel 3 as negative input */ + ACMP_NEG_CH4 = 4, /**< Channel 4 as negative input */ + ACMP_NEG_CH5 = 5, /**< Channel 5 as negative input */ + ACMP_NEG_CH6 = 6, /**< Channel 6 as negative input */ + ACMP_NEG_CH7 = 7, /**< Channel 7 as negative input */ + ACMP_NEG_1V25 = 8, /**< 1.25v as negative input */ + ACMP_NEG_2V5 = 9, /**< 2.5v as negative input */ + ACMP_NEG_VDD = 10, /**< VDD as negative input */ + ACMP_NEG_CAP = 11, /**< Capacitive as negative input */ + ACMP_NEG_DAC0_CH0 = 12, /**< DAC0 channel 0 as negative input */ + ACMP_NEG_DAC0_CH1 = 13, /**< DAC0 channel 1 as negative input */ +} acmp_neg_input_t; + +/** + * @brief Acmp mode + */ +typedef enum +{ + ACMP_ULTRA_LOW_POWER = 0, /**< Ultra low power mode */ + ACMP_LOW_POWER = 1, /**< Low power mode */ + ACMP_MIDDLE_POWER = 2, /**< Middle power mode */ + ACMP_HIGH_POWER = 3, /**< High power mode */ +} acmp_mode_t; + +/** + * @brief Acmp warm-up time + */ +typedef enum +{ + ACMP_4_PCLK = 0, /**< 4 hfperclk cycles */ + ACMP_8_PCLK = 1, /**< 4 hfperclk cycles */ + ACMP_16_PCLK = 2, /**< 4 hfperclk cycles */ + ACMP_32_PCLK = 3, /**< 4 hfperclk cycles */ + ACMP_64_PCLK = 4, /**< 4 hfperclk cycles */ + ACMP_128_PCLK = 5, /**< 4 hfperclk cycles */ + ACMP_256_PCLK = 6, /**< 4 hfperclk cycles */ + ACMP_512_PCLK = 7, /**< 4 hfperclk cycles */ +} acmp_warm_time_t; + +/** + * @brief Acmp hysteresis level + */ +typedef enum +{ + ACMP_HYST_0 = 0, /**< No hysteresis */ + ACMP_HYST_15 = 1, /**< 15mV hysteresis */ + ACMP_HYST_22 = 2, /**< 22mV hysteresis */ + ACMP_HYST_29 = 3, /**< 29mV hysteresis */ + ACMP_HYST_36 = 4, /**< 36mV hysteresis */ + ACMP_HYST_43 = 5, /**< 43mV hysteresis */ + ACMP_HYST_50 = 6, /**< 50mV hysteresis */ + ACMP_HYST_57 = 7, /**< 57mV hysteresis */ +} acmp_hystsel_t; + +/** + * @brief Acmp inactive state + */ +typedef enum +{ + ACMP_INACTVAL_LOW = 0, /**< The inactive value is 0 */ + ACMP_INACTVAL_HIGH = 1, /**< The inactive value is 1 */ +} acmp_inactval_t; + +/** + * @brief which edges set up interrupt + */ +typedef enum +{ + ACMP_EDGE_NONE = 0, /**< Disable EDGE interrupt */ + ACMP_EDGE_FALL = 1, /**< Falling edges set EDGE interrupt */ + ACMP_EDGE_RISE = 2, /**< rise edges set EDGE interrupt */ + ACMP_EDGE_ALL = 3, /**< Falling edges and rise edges set EDGE interrupt */ +} acmp_edge_t; + +/** + * @brief Acmp output function + */ +typedef enum +{ + ACMP_OUT_DISABLE = 0, /**< Disable acmp output */ + ACMP_OUT_ENABLE = 1, /**< Enable acmp output */ +} acmp_out_func_t; + +/** + * @brief Acmp warm-up interrupt function + */ +typedef enum +{ + ACMP_WARM_DISABLE = 0, /**< Disable acmp warm-up interrupt */ + ACMP_WARM_ENABLE = 1, /**< Enable acmp warm-up interrupt */ +} acmp_warm_it_func; + +/** + * @brief Acmp gpio output invert + */ +typedef enum +{ + ACMP_GPIO_NO_INV = 0, /**< Acmp output to gpio is not inverted */ + ACMP_GPIO_INV = 1, /**< Acmp output to gpio is inverted */ +} acmp_invert_t; + +/** + * @brief The location of the acmp i/o pin + */ +typedef enum +{ + ACMP_LOCATION_O = 0, /**< Location 0 */ + ACMP_LOCATION_1 = 1, /**< Location 1 */ + ACMP_LOCATION_2 = 2, /**< Location 2 */ +} acmp_location_t; + +/** + * @brief Acmp output config structure definition + */ +typedef struct +{ + acmp_out_func_t out_func; /**< Acmp output function */ + acmp_invert_t gpio_inv; /**< If invert gpio output */ + acmp_location_t location; /**< The location of acmp I/0 pin */ +} acmp_output_config_t; + +/** + * @brief Acmp init structure definition + */ +typedef struct +{ + acmp_mode_t mode; /**< Acmp operation mode */ + acmp_warm_time_t warm_time; /**< Acmp warm up time */ + acmp_hystsel_t hystsel; /**< Acmp hysteresis level */ + acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */ + acmp_pos_input_t pos_port; /**< Acmp positive port select */ + acmp_neg_input_t neg_port; /**< Acmp negative port select */ + acmp_inactval_t inactval; /**< Acmp inavtive output value */ + acmp_edge_t edge; /** Select edges to set interrupt flag */ + uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */ +} acmp_init_t; + +/** + * @brief ACMP Handle Structure definition + */ +typedef struct acmp_handle_s +{ + ACMP_TypeDef *perh; /**< Register base address */ + acmp_init_t init; /**< ACMP required parameters */ + lock_state_t lock; /**< Locking object */ + + void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */ + void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */ +} acmp_handle_t; +/** + * @} + */ + +/** @defgroup ACMP_Public_Macros ACMP Public Macros + * @{ + */ +#define ACMP_ENABLE(handle) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) +#define ACMP_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) +/** + * @} + */ + +/** @defgroup ACMP_Private_Macros ACMP Private Macros + * @{ + */ +#define IS_ACMP_TYPE(x) (((x) == ACMP0) || \ + ((x) == ACMP1)) +#define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \ + ((x) == ACMP_LOW_POWER) || \ + ((x) == ACMP_MIDDLE_POWER) || \ + ((x) == ACMP_HIGH_POWER)) +#define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \ + ((x) == ACMP_IT_WARMUP)) +#define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \ + ((x) == ACMP_FLAG_WARMUP)) +#define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_EDGE) || \ + ((x) == ACMP_STATUS_WARMUP)) +#define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \ + ((x) == ACMP_POS_CH1) || \ + ((x) == ACMP_POS_CH2) || \ + ((x) == ACMP_POS_CH3) || \ + ((x) == ACMP_POS_CH4) || \ + ((x) == ACMP_POS_CH5) || \ + ((x) == ACMP_POS_CH6) || \ + ((x) == ACMP_POS_CH7)) +#define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \ + ((x) == ACMP_NEG_CH1) || \ + ((x) == ACMP_NEG_CH2) || \ + ((x) == ACMP_NEG_CH3) || \ + ((x) == ACMP_NEG_CH4) || \ + ((x) == ACMP_NEG_CH5) || \ + ((x) == ACMP_NEG_CH6) || \ + ((x) == ACMP_NEG_CH7) || \ + ((x) == ACMP_NEG_1V25) || \ + ((x) == ACMP_NEG_2V5) || \ + ((x) == ACMP_NEG_VDD) || \ + ((x) == ACMP_NEG_CAP) || \ + ((x) == ACMP_NEG_DAC0_CH0) || \ + ((x) == ACMP_NEG_DAC0_CH1)) +#define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \ + ((x) == ACMP_8_PCLK) || \ + ((x) == ACMP_16_PCLK) || \ + ((x) == ACMP_32_PCLK) || \ + ((x) == ACMP_64_PCLK) || \ + ((x) == ACMP_128_PCLK) || \ + ((x) == ACMP_256_PCLK) || \ + ((x) == ACMP_512_PCLK)) +#define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \ + ((x) == ACMP_HYST_15) || \ + ((x) == ACMP_HYST_22) || \ + ((x) == ACMP_HYST_29) || \ + ((x) == ACMP_HYST_36) || \ + ((x) == ACMP_HYST_43) || \ + ((x) == ACMP_HYST_50) || \ + ((x) == ACMP_HYST_57)) +#define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \ + ((x) == ACMP_INACTVAL_HIGH)) +#define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \ + ((x) == ACMP_EDGE_FALL) || \ + ((x) == ACMP_EDGE_RISE) || \ + ((x) == ACMP_EDGE_ALL)) +#define IS_ACMP_OUT_FUNC_TYPE(x) (((x) == ACMP_OUT_DISABLE) || \ + ((x) == ACMP_OUT_ENABLE)) +#define IS_ACMP_INVERT_TYPE(x) (((x) == ACMP_GPIO_NO_INV) || \ + ((x) == ACMP_GPIO_INV)) +#define IS_ACMP_LOCATION_TYPE(x) (((x) == ACMP_LOCATION_O) || \ + ((x) == ACMP_LOCATION_1) || \ + ((x) == ACMP_LOCATION_2)) +#define IS_ACMP_WARM_FUNC_TYPE(x) (((x) == ACMP_WARM_DISABLE) || \ + ((x) == ACMP_WARM_ENABLE)) +/** + * @} + */ + +/** @addtogroup ACMP_Public_Functions + * @{ + */ + +/** @addtogroup ACMP_Public_Functions_Group1 + * @{ + */ +ald_status_t acmp_init(acmp_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup ACMP_Public_Functions_Group2 + * @{ + */ +ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state); +ald_status_t acmp_set_interrupt_mask(acmp_handle_t *hperh, acmp_it_t it); +it_status_t acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t it); +ald_status_t acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t it); +flag_status_t acmp_get_status(acmp_handle_t *hperh, acmp_status_t flag); + +/** + * @} + */ + +/** @addtogroup ACMP_Public_Functions_Group3 + * @{ + */ +void acmp_irq_handle(acmp_handle_t *hperh); +ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config); +uint8_t acmp_out_result(acmp_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +extern "C" +} +#endif + +#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h new file mode 100644 index 0000000000..b4f4f029d1 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h @@ -0,0 +1,585 @@ +/** + ****************************************************************************** + * @file ald_adc.h + * @brief Header file of ADC Module library. + * + * @version V1.0 + * @date 15 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ****************************************************************************** + */ + +#ifndef __ALD_ADC_H__ +#define __ALD_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" +#include "ald_pis.h" +#include "ald_timer.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Pubulic_Types ADC Pubulic Types + * @{ + */ + +/** + * @brief ADC State structures definition + */ +typedef enum +{ + ADC_STATE_RESET = 0x0, /**< ADC not yet initialized or disabled */ + ADC_STATE_READY = 0x1, /**< ADC peripheral ready for use */ + ADC_STATE_BUSY_INTERNAL = 0x2, /**< ADC is busy to internal process */ + ADC_STATE_TIMEOUT = 0x4, /**< TimeOut occurrence */ + ADC_STATE_ERROR = 0x10, /**< Internal error occurrence */ + ADC_STATE_NM_BUSY = 0x100, /**< Conversion on group normal is ongoing or can occur */ + ADC_STATE_NM_EOC = 0x200, /**< Conversion data available on group normal */ + ADC_STATE_IST_BUSY = 0x1000, /**< Conversion on group insert is ongoing or can occur */ + ADC_STATE_IST_EOC = 0x2000, /**< Conversion data available on group insert */ + ADC_STATE_AWD = 0x10000, /**< Out-of-window occurrence of analog watchdog */ +} adc_state_t; + +/** + *@brief ADC Error Code + */ +typedef enum +{ + ADC_ERROR_NONE = 0x0, /**< No error */ + ADC_ERROR_INTERNAL = 0x1, /**< ADC IP internal error*/ + ADC_ERROR_OVR = 0x2, /**< Overrun error */ + ADC_ERROR_DMA = 0x4, /**< DMA transfer error */ +} adc_error_t; + +/** + *@brief ADC data alignment + */ +typedef enum +{ + ADC_DATAALIGN_RIGHT = 0x0, /**< ADC data alignment right */ + ADC_DATAALIGN_LEFT = 0x1, /**< ADC data alignment left */ +} adc_align_t; + +/** + *@brief ADC scan mode + */ +typedef enum +{ + ADC_SCAN_DISABLE = 0x0, /**< ADC scan disable */ + ADC_SCAN_ENABLE = 0x1, /**< ADC scan enable */ +} adc_scan_t; + +/** + *@brief ADC config hannal trigger the EOC IT mode + */ +typedef enum +{ + ADC_NCHESEL_MODE_ALL = 0x0, /**< ADC set RCHE after convert sequence finish */ + ADC_NCHESEL_MODE_ONE = 0x1, /**< ADC set RCHE after one convert finish */ +} adc_nchesel_t; + +/** + *@brief ADC channels + */ +typedef enum +{ + ADC_CHANNEL_0 = 0x0, /**< ADC channel 0 */ + ADC_CHANNEL_1 = 0x1, /**< ADC channel 1 */ + ADC_CHANNEL_2 = 0x2, /**< ADC channel 2 */ + ADC_CHANNEL_3 = 0x3, /**< ADC channel 3 */ + ADC_CHANNEL_4 = 0x4, /**< ADC channel 4 */ + ADC_CHANNEL_5 = 0x5, /**< ADC channel 5 */ + ADC_CHANNEL_6 = 0x6, /**< ADC channel 6 */ + ADC_CHANNEL_7 = 0x7, /**< ADC channel 7 */ + ADC_CHANNEL_8 = 0x8, /**< ADC channel 8 */ + ADC_CHANNEL_9 = 0x9, /**< ADC channel 9 */ + ADC_CHANNEL_10 = 0xA, /**< ADC channel 10 */ + ADC_CHANNEL_11 = 0xB, /**< ADC channel 11 */ + ADC_CHANNEL_12 = 0xC, /**< ADC channel 12 */ + ADC_CHANNEL_13 = 0xD, /**< ADC channel 13 */ + ADC_CHANNEL_14 = 0xE, /**< ADC channel 14 */ + ADC_CHANNEL_15 = 0xF, /**< ADC channel 15 */ + ADC_CHANNEL_16 = 0x10, /**< ADC channel 16 */ + ADC_CHANNEL_17 = 0x11, /**< ADC channel 17 */ + ADC_CHANNEL_18 = 0x12, /**< ADC channel 18 */ + ADC_CHANNEL_19 = 0x13, /**< ADC channel 19 */ +} adc_channel_t; + +/** + *@brief ADC sampling times + */ +typedef enum +{ + ADC_SAMPLETIME_1 = 0x0, /**< ADC sampling times 1 clk */ + ADC_SAMPLETIME_2 = 0x1, /**< ADC sampling times 2 clk */ + ADC_SAMPLETIME_4 = 0x2, /**< ADC sampling times 4 clk */ + ADC_SAMPLETIME_15 = 0x3, /**< ADC sampling times 15 clk */ +} adc_samp_t; + +/** + *@brief ADC rank into normal group + */ +typedef enum +{ + ADC_NC_RANK_1 = 0x1, /**< ADC normal channel rank 1 */ + ADC_NC_RANK_2 = 0x2, /**< ADC normal channel rank 2 */ + ADC_NC_RANK_3 = 0x3, /**< ADC normal channel rank 3 */ + ADC_NC_RANK_4 = 0x4, /**< ADC normal channel rank 4 */ + ADC_NC_RANK_5 = 0x5, /**< ADC normal channel rank 5 */ + ADC_NC_RANK_6 = 0x6, /**< ADC normal channel rank 6 */ + ADC_NC_RANK_7 = 0x7, /**< ADC normal channel rank 7 */ + ADC_NC_RANK_8 = 0x8, /**< ADC normal channel rank 8 */ + ADC_NC_RANK_9 = 0x9, /**< ADC normal channel rank 9 */ + ADC_NC_RANK_10 = 0xA, /**< ADC normal channel rank 10 */ + ADC_NC_RANK_11 = 0xB, /**< ADC normal channel rank 11 */ + ADC_NC_RANK_12 = 0xC, /**< ADC normal channel rank 12 */ + ADC_NC_RANK_13 = 0xD, /**< ADC normal channel rank 13 */ + ADC_NC_RANK_14 = 0xE, /**< ADC normal channel rank 14 */ + ADC_NC_RANK_15 = 0xF, /**< ADC normal channel rank 15 */ + ADC_NC_RANK_16 = 0x10, /**< ADC normal channel rank 16 */ +} adc_nc_rank_t; + +/** + * @brief ADC rank into insert group + */ +typedef enum +{ + ADC_IH_RANK_1 = 0x1, /**< ADC insert channel rank 1 */ + ADC_IH_RANK_2 = 0x2, /**< ADC insert channel rank 2 */ + ADC_IH_RANK_3 = 0x3, /**< ADC insert channel rank 3 */ + ADC_IH_RANK_4 = 0x4, /**< ADC insert channel rank 4 */ +} adc_ih_rank_t; + +/** + * @brief ADC analog watchdog mode + */ +typedef enum +{ + ADC_ANAWTD_NONE = 0x0, /**< No watch dog */ + ADC_ANAWTD_SING_NM = 0x800200, /**< One normal channel watch dog */ + ADC_ANAWTD_SING_IST = 0x400200, /**< One inset channel Injec watch dog */ + ADC_ANAWTD_SING_NMIST = 0xC00200, /**< One normal and inset channel watch dog */ + ADC_ANAWTD_ALL_NM = 0x800000, /**< All normal channel watch dog */ + ADC_ANAWTD_ALL_IST = 0x400000, /**< All inset channel watch dog */ + ADC_ANAWTD_ALL_NMIST = 0xC00000, /**< All normal and inset channel watch dog */ +} adc_ana_wtd_t; + +/** + * @brief ADC Event type + */ +typedef enum +{ + ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ +} adc_event_type_t; + +/** + * @brief ADC interrupts definition + */ +typedef enum +{ + ADC_IT_NH = (1U << 5), /**< ADC it normal */ + ADC_IT_AWD = (1U << 6), /**< ADC it awd */ + ADC_IT_IH = (1U << 7), /**< ADC it insert */ + ADC_IT_OVR = (1U << 26), /**< ADC it overring */ +} adc_it_t; + +/** + * @brief ADC flags definition + */ +typedef enum +{ + ADC_FLAG_AWD = (1U << 0), /**perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) +#define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) +#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) +#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +/** + * @} + */ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +#define IS_ADC_IH_RANK_TYPE(x) ((x) <= ADC_IH_RANK_4) +#define IS_ADC_NC_RANK_TYPE(x) ((x) <= ADC_NC_RANK_16) +#define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ADC_SAMPLETIME_1) || \ + ((x) == ADC_SAMPLETIME_2) || \ + ((x) == ADC_SAMPLETIME_4) || \ + ((x) == ADC_SAMPLETIME_15)) +#define IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_19) +#define IS_ADC_SCAN_MODE_TYPE(x) (((x) == ADC_SCAN_DISABLE) || \ + ((x) == ADC_SCAN_ENABLE) ) +#define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ADC_DATAALIGN_RIGHT) || \ + ((x) == ADC_DATAALIGN_LEFT)) +#define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ADC_ANAWTD_NONE) || \ + ((x) == ADC_ANAWTD_SING_NM) || \ + ((x) == ADC_ANAWTD_SING_IST) || \ + ((x) == ADC_ANAWTD_SING_NMIST) || \ + ((x) == ADC_ANAWTD_ALL_NM) || \ + ((x) == ADC_ANAWTD_ALL_IST) || \ + ((x) == ADC_ANAWTD_ALL_NMIST)) +#define IS_ADC_IT_TYPE(x) (((x) == ADC_IT_NH) || \ + ((x) == ADC_IT_AWD) || \ + ((x) == ADC_IT_IH) || \ + ((x) == ADC_IT_OVR )) +#define IS_ADC_FLAGS_TYPE(x) (((x) == ADC_FLAG_AWD) || \ + ((x) == ADC_FLAG_NH) || \ + ((x) == ADC_FLAG_IH) || \ + ((x) == ADC_FLAG_OVR) || \ + ((x) == ADC_FLAG_NHS) || \ + ((x) == ADC_FLAG_IHS)) +#define IS_ADC_CLK_DIV_TYPE(x) (((x) == ADC_CKDIV_1) || \ + ((x) == ADC_CKDIV_2) || \ + ((x) == ADC_CKDIV_4) || \ + ((x) == ADC_CKDIV_8) || \ + ((x) == ADC_CKDIV_16) || \ + ((x) == ADC_CKDIV_32) || \ + ((x) == ADC_CKDIV_64) || \ + ((x) == ADC_CKDIV_128)) +#define IS_ADC_NEG_REF_VOLTAGE_TYPE(x) (((x) == ADC_NEG_REF_VSS ) || \ + ((x) == ADC_NEG_REF_VREFN )) +#define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ADC_POS_REF_VDD) || \ + ((x) == ADC_POS_REF_2V) || \ + ((x) == ADC_POS_REF_VREEFP) || \ + ((x) == ADC_POS_REF_VREEFP_BUF)) +#define IS_ADC_NBR_OF_NM_TYPE(x) ((x) <= ADC_NM_NBR_16) +#define IS_ADC_NBR_OF_IST_TYPE(x) ((x) <= ADC_IST_NBR_4) +#define IS_ADC_DISC_NBR_TYPE(x) ((x) <= ADC_DISC_NBR_8) +#define IS_ADC_CONV_RES_TYPE(x) (((x) == ADC_CONV_RES_12) || \ + ((x) == ADC_CONV_RES_6) || \ + ((x) == ADC_CONV_RES_8) || \ + ((x) == ADC_CONV_RES_10)) +#define IS_ADC_TRIG_MODE_TYPE(x) (((x) == ADC_TRIG_SOFT) || \ + ((x) == ADC_TRIG_PIS) || \ + ((x) == ADC_TRIG_PIS_SOFT)) +#define IS_ADC_TYPE(x) (((x) == ADC0) || \ + ((x) == ADC1)) +#define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ADC_NCHESEL_MODE_ALL) || \ + ((x) == ADC_NCHESEL_MODE_ONE)) +#define IS_ADC_EVENT_TYPE(x) ((x) == ADC_AWD_EVENT) +#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff) +#define IS_HTR_TYPE(x) ((x) <= 0xfff) +#define IS_LTR_TYPE(x) ((x) <= 0xfff) +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions + * @{ + */ + +/** @addtogroup ADC_Public_Functions_Group1 + * @{ + */ +ald_status_t adc_init(adc_handle_t *hperh); +ald_status_t adc_reset(adc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group2 + * @{ + */ +ald_status_t adc_normal_start(adc_handle_t *hperh); +ald_status_t adc_normal_stop(adc_handle_t *hperh); +ald_status_t adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); +ald_status_t adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout); +ald_status_t adc_normal_start_by_it(adc_handle_t *hperh); +ald_status_t adc_normal_stop_by_it(adc_handle_t *hperh); +#ifdef ALD_DMA +ald_status_t adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); +ald_status_t adc_stop_by_dma(adc_handle_t *hperh); +ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config); +#endif +uint32_t adc_normal_get_value(adc_handle_t *hperh); +ald_status_t adc_insert_start(adc_handle_t *hperh); +ald_status_t adc_insert_stop(adc_handle_t *hperh); +ald_status_t adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); +ald_status_t adc_insert_start_by_it(adc_handle_t *hperh); +ald_status_t adc_insert_stop_by_it(adc_handle_t *hperh); +uint32_t adc_insert_get_value(adc_handle_t *hperh, adc_ih_rank_t ih_rank); +void adc_irq_handler(adc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group3 + * @{ + */ +ald_status_t adc_normal_channel_config(adc_handle_t *hperh, adc_channel_conf_t *config); +ald_status_t adc_insert_channel_config(adc_handle_t *hperh, adc_ih_conf_t *config); +ald_status_t adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config); +void adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state); +it_status_t adc_get_it_status(adc_handle_t *hperh, adc_it_t it); +flag_status_t adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag); +void adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group4 + * @{ + */ +uint32_t adc_get_state(adc_handle_t *hperh); +uint32_t adc_get_error(adc_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +extern "C" +} +#endif + +#endif /* __ALD_ADC_H */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h new file mode 100644 index 0000000000..67923d9a3a --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h @@ -0,0 +1,186 @@ +/** + ********************************************************************************* + * + * @file ald_bkpc.h + * @brief Header file of BKPC module driver. + * + * @version V1.0 + * @date 15 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_BKPC_H__ +#define __ALD_BKPC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup BKPC + * @{ + */ + +/** @defgroup BKPC_Public_Macros BKPC Public Macros + * @{ + */ +#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0)) +#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55)) +#define BKPC_LRC_ENABLE() \ +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LRC_DISABLE() \ +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LOSM_ENABLE() \ +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LOSM_DISABLE() \ +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LOSC_ENABLE() \ +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LOSC_DISABLE() \ +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\ + BKPC_LOCK(); \ +} while (0) +/** + * @} + */ + +/** @defgroup BKPC_Public_Types BKPC Public Types + * @{ + */ +/** + * @brief BKPC ldo output select + */ +typedef enum +{ + BKPC_LDO_OUTPUT_1_6 = 0x0, /**< 1.6V */ + BKPC_LDO_OUTPUT_1_3 = 0x1, /**< 1.3V */ + BKPC_LDO_OUTPUT_1_4 = 0x2, /**< 1.4V */ + BKPC_LDO_OUTPUT_1_5 = 0x4, /**< 1.5V */ +} bkpc_ldo_output_t; + +/** + * @brief BKPC BOR voltage select + */ +typedef enum +{ + BKPC_BOR_VOL_1_7 = 0x0, /**< 1.7V */ + BKPC_BOR_VOL_2_0 = 0x1, /**< 2.0V */ + BKPC_BOR_VOL_2_1 = 0x2, /**< 2.1V */ + BKPC_BOR_VOL_2_2 = 0x3, /**< 2.2V */ + BKPC_BOR_VOL_2_3 = 0x4, /**< 2.3V */ + BKPC_BOR_VOL_2_4 = 0x5, /**< 2.4V */ + BKPC_BOR_VOL_2_5 = 0x6, /**< 2.5V */ + BKPC_BOR_VOL_2_6 = 0x7, /**< 2.6V */ + BKPC_BOR_VOL_2_8 = 0x8, /**< 2.8V */ + BKPC_BOR_VOL_3_0 = 0x9, /**< 3.0V */ + BKPC_BOR_VOL_3_1 = 0xA, /**< 3.1V */ + BKPC_BOR_VOL_3_3 = 0xB, /**< 3.3V */ + BKPC_BOR_VOL_3_6 = 0xC, /**< 3.6V */ + BKPC_BOR_VOL_3_7 = 0xD, /**< 3.7V */ + BKPC_BOR_VOL_4_0 = 0xE, /**< 4.0V */ + BKPC_BOR_VOL_4_3 = 0xF, /**< 4.3V */ +} bkpc_bor_vol_t; + +/** + * @} + */ + +/** + * @defgroup BKPC_Private_Macros BKPC Private Macros + * @{ + */ +#define IS_BKPC_LDO_OUTPUT(x) (((x) == BKPC_LDO_OUTPUT_1_6) || \ + ((x) == BKPC_LDO_OUTPUT_1_3) || \ + ((x) == BKPC_LDO_OUTPUT_1_4) || \ + ((x) == BKPC_LDO_OUTPUT_1_5)) +#define IS_BKPC_BOR_VOL(x) (((x) == BKPC_BOR_VOL_1_7) || \ + ((x) == BKPC_BOR_VOL_2_0) || \ + ((x) == BKPC_BOR_VOL_2_1) || \ + ((x) == BKPC_BOR_VOL_2_2) || \ + ((x) == BKPC_BOR_VOL_2_3) || \ + ((x) == BKPC_BOR_VOL_2_4) || \ + ((x) == BKPC_BOR_VOL_2_5) || \ + ((x) == BKPC_BOR_VOL_2_6) || \ + ((x) == BKPC_BOR_VOL_2_8) || \ + ((x) == BKPC_BOR_VOL_3_0) || \ + ((x) == BKPC_BOR_VOL_3_1) || \ + ((x) == BKPC_BOR_VOL_3_3) || \ + ((x) == BKPC_BOR_VOL_3_6) || \ + ((x) == BKPC_BOR_VOL_3_7) || \ + ((x) == BKPC_BOR_VOL_4_0) || \ + ((x) == BKPC_BOR_VOL_4_3)) +#define IS_BKPC_RAM_IDX(x) ((x) < 32) +/** + * @} + */ + +/** @addtogroup BKPC_Public_Functions + * @{ + */ +/** @addtogroup BKPC_Public_Functions_Group1 + * @{ + */ +/* control functions */ +extern void bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state); +extern void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state); +/** + * @} + */ +/** @addtogroup BKPC_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +extern void bkpc_write_ram(uint8_t idx, uint32_t value); +extern uint32_t bkpc_read_ram(uint8_t idx); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_BKPC_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h new file mode 100644 index 0000000000..896522b861 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h @@ -0,0 +1,57 @@ +/** + ********************************************************************************* + * + * @file ald_calc.h + * @brief Header file of CALC module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_CALC_H__ +#define __ALD_CALC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CALC + * @{ + */ + +/** @addtogroup CALC_Public_Functions + * @{ + */ +extern uint32_t calc_sqrt(uint32_t data); +extern uint32_t calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder); +extern int32_t calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder); +extern flag_status_t calc_get_dz_status(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CALC_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h new file mode 100644 index 0000000000..ebe2e2a479 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h @@ -0,0 +1,485 @@ +/** + ****************************************************************************** + * @file ald_can.h + * @brief Header file of CAN Module driver. + * + * @version V1.0 + * @date 16 Apr 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ****************************************************************************** + */ + +#ifndef __ALD_CAN_H +#define __ALD_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @defgroup CAN_Public_Types CAN Public Types + * @{ + */ +/** + * @brief ALD State structures definition + */ +typedef enum +{ + CAN_STATE_RESET = 0x00, /**< CAN not yet initialized or disabled */ + CAN_STATE_READY = 0x01, /**< CAN initialized and ready for use */ + CAN_STATE_BUSY = 0x02, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX = 0x11, /**< CAN process is ongoing */ + CAN_STATE_BUSY_RX = 0x21, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX_RX = 0x31, /**< CAN process is ongoing */ + CAN_STATE_TIMEOUT = 0x03, /**< CAN in Timeout state */ + CAN_STATE_ERROR = 0x04, /**< CAN error state */ +} can_state_t; + +/** + * @brief CAN Error Code + */ +typedef enum +{ + CAN_ERROR_NONE = 0x00, /**< No error */ + CAN_ERROR_EWG = 0x01, /**< EWG error */ + CAN_ERROR_EPV = 0x02, /**< EPV error */ + CAN_ERROR_BOF = 0x04, /**< BOF error */ + CAN_ERROR_STF = 0x08, /**< Stuff error */ + CAN_ERROR_FOR = 0x10, /**< Form error */ + CAN_ERROR_ACK = 0x20, /**< Acknowledgment error */ + CAN_ERROR_BR = 0x40, /**< Bit recessive */ + CAN_ERROR_BD = 0x80, /**< LEC dominant */ + CAN_ERROR_CRC = 0x100, /**< LEC transfer error */ +} can_error_t; + +/** + * @brief CAN Operating Mode + */ +typedef enum +{ + CAN_MODE_NORMAL = 0x00, /**< Normal mode */ + CAN_MODE_LOOPBACK = 0x01, /**< Loopback mode */ + CAN_MODE_SILENT = 0x02, /**< Silent mode */ + CAN_MODE_SILENT_LOOPBACK = 0x03, /**< Loopback combined with silent mode */ +} can_operate_mode_t; + +/** + * @brief CAN Synchronization Jump Width + */ +typedef enum +{ + CAN_SJW_1 = 0x0, /**< 1 time quantum */ + CAN_SJW_2 = 0x1, /**< 2 time quantum */ + CAN_SJW_3 = 0x2, /**< 3 time quantum */ + CAN_SJW_4 = 0x3, /**< 4 time quantum */ +} can_sjw_t; + +/** + * @brief CAN Time Quantum in Bit Segment 1 + */ +typedef enum +{ + CAN_SEG1_1 = 0x0, /**< 1 time quantum */ + CAN_SEG1_2 = 0x1, /**< 2 time quantum */ + CAN_SEG1_3 = 0x2, /**< 3 time quantum */ + CAN_SEG1_4 = 0x3, /**< 4 time quantum */ + CAN_SEG1_5 = 0x4, /**< 5 time quantum */ + CAN_SEG1_6 = 0x5, /**< 6 time quantum */ + CAN_SEG1_7 = 0x6, /**< 7 time quantum */ + CAN_SEG1_8 = 0x7, /**< 8 time quantum */ + CAN_SEG1_9 = 0x8, /**< 9 time quantum */ + CAN_SEG1_10 = 0x9, /**< 10 time quantum */ + CAN_SEG1_11 = 0xA, /**< 11 time quantum */ + CAN_SEG1_12 = 0xB, /**< 12 time quantum */ + CAN_SEG1_13 = 0xC, /**< 13 time quantum */ + CAN_SEG1_14 = 0xD, /**< 14 time quantum */ + CAN_SEG1_15 = 0xE, /**< 15 time quantum */ + CAN_SEG1_16 = 0xF, /**< 16 time quantum */ +} can_seg1_t; + +/** + * @brief CAN Time Quantum in Bit Segment 2 + */ +typedef enum +{ + CAN_SEG2_1 = 0x0, /**< 1 time quantum */ + CAN_SEG2_2 = 0x1, /**< 2 time quantum */ + CAN_SEG2_3 = 0x2, /**< 3 time quantum */ + CAN_SEG2_4 = 0x3, /**< 4 time quantum */ + CAN_SEG2_5 = 0x4, /**< 5 time quantum */ + CAN_SEG2_6 = 0x5, /**< 6 time quantum */ + CAN_SEG2_7 = 0x6, /**< 7 time quantum */ + CAN_SEG2_8 = 0x7, /**< 8 time quantum */ +} can_seg2_t; + +/** + * @brief CAN Filter Mode + */ +typedef enum +{ + CAN_FILTER_MODE_MASK = 0x0, /**< Identifier mask mode */ + CAN_FILTER_MODE_LIST = 0x1, /**< Identifier list mode */ +} can_filter_mode_t; + +/** + * @brief CAN Filter Scale + */ +typedef enum +{ + CAN_FILTER_SCALE_16 = 0x0, /**< Two 16-bit filters */ + CAN_FILTER_SCALE_32 = 0x1, /**< One 32-bit filter */ +} can_filter_scale_t; + +/** + * @brief CAN Filter fifo + */ +typedef enum +{ + CAN_FILTER_FIFO0 = 0x0, /**< FIFO 0 assignment for filter */ + CAN_FILTER_FIFO1 = 0x1, /**< FIFO 1 assignment for filter */ +} can_filter_fifo_t; + +/** + * @brief CAN Identifier Type + */ +typedef enum +{ + CAN_ID_STD = 0x0, /**< Standard Id */ + CAN_ID_EXT = 0x1, /**< Extended Id */ +} can_id_type_t; + +/** + * @brief CAN Remote Transmission Request + */ +typedef enum +{ + CAN_RTR_DATA = 0x0, /**< Data frame */ + CAN_RTR_REMOTE = 0x1, /**< Remote frame */ +} can_remote_req_t; + +/** + * @brief CAN Transmit Constants + */ +typedef enum +{ + CAN_TX_MAILBOX_0 = 0x0, /**< TX mailbox index 0 */ + CAN_TX_MAILBOX_1 = 0x1, /**< TX mailbox index 1 */ + CAN_TX_MAILBOX_2 = 0x2, /**< TX mailbox index 2 */ + CAN_TX_MAILBOX_NONE = 0x3, /**< MailBox can't be used */ +} can_tx_mailbox_t; + +/** + * @brief CAN Receive fifo Number + */ +typedef enum +{ + CAN_RX_FIFO0 = 0x0, /**< CAN fifo 0 used to receive */ + CAN_RX_FIFO1 = 0x1, /**< CAN fifo 1 used to receive */ +} can_rx_fifo_t; + +/** + * @brief CAN Flags + */ +typedef enum +{ + CAN_FLAG_SLAK = (1U << 1), /**< Sleep acknowledge flag */ + CAN_FLAG_WKU = (1U << 3), /**< Wake up flag */ + CAN_FLAG_SLAKI = (1U << 4), /**< Sleep acknowledge flag */ + CAN_FLAG_RQCP0 = (1U << 20) | (1U << 0), /**< Request MailBox0 flag */ + CAN_FLAG_TXOK0 = (1U << 20) | (1U << 1), /**< Transmission OK MailBox0 flag */ + CAN_FLAG_RQCP1 = (1U << 20) | (1U << 8), /**< Request MailBox1 flag */ + CAN_FLAG_TXOK1 = (1U << 20) | (1U << 9), /**< Transmission OK MailBox1 flag */ + CAN_FLAG_RQCP2 = (1U << 20) | (1U << 16), /**< Request MailBox2 flag */ + CAN_FLAG_TXOK2 = (1U << 20) | (1U << 17), /**< Transmission OK MailBox2 flag */ + CAN_FLAG_TME0 = (1U << 20) | (1U << 26), /**< Transmit mailbox 0 empty flag */ + CAN_FLAG_TME1 = (1U << 20) | (1U << 27), /**< Transmit mailbox 1 empty flag */ + CAN_FLAG_TME2 = (1U << 20) | (1U << 28), /**< Transmit mailbox 2 empty flag */ + CAN_FLAG_FF0 = (2U << 20) | (1U << 3), /**< FIFO 0 Full flag */ + CAN_FLAG_FOV0 = (2U << 20) | (1U << 4), /**< FIFO 0 Overrun flag */ + CAN_FLAG_FF1 = (3U << 20) | (1U << 3), /**< FIFO 1 Full flag */ + CAN_FLAG_FOV1 = (3U << 20) | (1U << 4), /**< FIFO 1 Overrun flag */ + CAN_FLAG_EWG = (4U << 20) | (1U << 0), /**< Error warning flag */ + CAN_FLAG_EPV = (4U << 20) | (1U << 1), /**< Error passive flag */ + CAN_FLAG_BOF = (4U << 20) | (1U << 2), /**< Bus-Off flag */ +} can_flag_t; + +/** + * @brief CAN Interrupts + */ +typedef enum +{ + CAN_IT_TME = (1U << 0), /**< Transmit mailbox empty interrupt bit */ + CAN_IT_FMP0 = (1U << 1), /**< FIFO0 message pending interrupt bit */ + CAN_IT_FF0 = (1U << 2), /**< FIFO0 full interrupt bit */ + CAN_IT_FOV0 = (1U << 3), /**< FIFO0 overrun interrupt bit */ + CAN_IT_FMP1 = (1U << 4), /**< FIFO1 message pending interrupt bit */ + CAN_IT_FF1 = (1U << 5), /**< FIFO1 full interrupt bit */ + CAN_IT_FOV1 = (1U << 6), /**< FIFO1 overrun interrupt bit */ + CAN_IT_EWG = (1U << 8), /**< Error warning interrupt bit */ + CAN_IT_EPV = (1U << 9), /**< Error passive interrupt bit */ + CAN_IT_BOF = (1U << 10), /**< Bus-off interrupt bit */ + CAN_IT_LEC = (1U << 11), /**< Last error code interrupt bit */ + CAN_IT_ERR = (1U << 15), /**< Error interrupt bit */ + CAN_IT_WKU = (1U << 16), /**< wake-up interrupt bit */ + CAN_IT_SLK = (1U << 17), /**< sleep interrupt bit */ +} can_it_t; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t id_high; /**< Specifies the filter identification number */ + uint32_t id_low; /**< Specifies the filter identification number */ + uint32_t mask_id_high; /**< Specifies the filter mask number or identification number */ + uint32_t mask_id_low; /**< Specifies the filter mask number or identification number */ + can_filter_fifo_t fifo; /**< Specifies the fifo (0 or 1) which will be assigned to the filter. */ + uint32_t number; /**< Specifies the filter which will be initialized. */ + can_filter_mode_t mode; /**< Specifies the filter mode to be initialized. */ + can_filter_scale_t scale; /**< Specifies the filter scale. */ + type_func_t active; /**< Enable or disable the filter. */ + uint32_t bank_number; /**< Select the start slave bank filter. */ +} can_filter_t; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t psc; /**< Specifies the length of a time quantum. */ + can_operate_mode_t mode; /**< Specifies the CAN operating mode. */ + can_sjw_t sjw; /**< Specifies the maximum number of time quanta the CAN hardware is + allowed to lengthen or shorten a bit to perform resynchronization. */ + can_seg1_t seg1; /**< Specifies the number of time quanta in Bit Segment 1. */ + can_seg2_t seg2; /**< Specifies the number of time quanta in Bit Segment 2. */ + type_func_t ttcm; /**< Enable or disable the time triggered communication mode. */ + type_func_t abom; /**< Enable or disable the automatic bus-off management. */ + type_func_t awk; /**< Enable or disable the automatic wake-up mode. */ + type_func_t artx; /**< Enable or disable the non-automatic retransmission mode. */ + type_func_t rfom; /**< Enable or disable the Receive fifo Locked mode. */ + type_func_t txmp; /**< Enable or disable the transmit fifo priority. */ +} can_init_t; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t std; /**< Specifies the standard identifier. */ + uint32_t ext; /**< Specifies the extended identifier. */ + can_id_type_t type; /**< Specifies the type of identifier for the message that will be transmitted. */ + can_remote_req_t rtr; /**< Specifies the type of frame for the message that will be transmitted. */ + uint32_t len; /**< Specifies the length of the frame that will be transmitted. */ + uint8_t data[8]; /**< Contains the data to be transmitted. */ +} can_tx_msg_t; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t std; /**< Specifies the standard identifier. */ + uint32_t ext; /**< Specifies the extended identifier. */ + can_id_type_t type; /**< Specifies the type of identifier for the message that will be received. */ + can_remote_req_t rtr; /**< Specifies the type of frame for the received message. */ + uint32_t len; /**< Specifies the length of the frame that will be received. */ + uint8_t data[8]; /**< Contains the data to be received. */ + uint32_t fmi; /**< Specifies the index of the filter the message stored in the mailbox passes through. */ + can_rx_fifo_t num; /**< Specifies the receive fifo number. */ +} can_rx_msg_t; + +/** + * @brief CAN handle Structure definition + */ +typedef struct can_handle_s +{ + CAN_TypeDef *perh; /**< Register base address */ + can_init_t init; /**< CAN required parameters */ + can_rx_msg_t *rx_msg; /**< Pointer to receive message */ + lock_state_t lock; /**< CAN locking object */ + can_state_t state; /**< CAN communication state */ + can_error_t err; /**< CAN Error code */ + + void (*tx_cplt_cbk)(struct can_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct can_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct can_handle_s *arg); /**< error callback */ +} can_handle_t; +/** + * @} + */ + +/** @defgroup CAN_Public_Macro CAN Public Macros + * @{ + */ +#define CAN_RESET_HANDLE_STATE(x) ((x)->state = CAN_STATE_RESET) +#define CAN_RX_MSG_PENDING(x, y) (((y) == CAN_RX_FIFO0) ? \ + (READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK))) +#define CAN_DBG_FREEZE(x, y) (MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS)) +/** + * @} + */ + +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ +#define IS_CAN_ALL(x) ((x) == CAN0) +#define IS_CAN_FILTER_NUMBER(x) ((x) <= 13) +#define IS_CAN_MODE(x) (((x) == CAN_MODE_NORMAL) || \ + ((x) == CAN_MODE_LOOPBACK) || \ + ((x) == CAN_MODE_SILENT) || \ + ((x) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(x) (((x) == CAN_SJW_1) || \ + ((x) == CAN_SJW_2) || \ + ((x) == CAN_SJW_3) || \ + ((x) == CAN_SJW_4)) +#define IS_CAN_BS1(x) ((x) <= CAN_SEG1_16) +#define IS_CAN_BS2(x) ((x) <= CAN_SEG2_8) +#define IS_CAN_FILTER_MODE(x) (((x) == CAN_FILTER_MODE_MASK) || \ + ((x) == CAN_FILTER_MODE_LIST)) +#define IS_CAN_FILTER_SCALE(x) (((x) == CAN_FILTER_SCALE_16) || \ + ((x) == CAN_FILTER_SCALE_32)) +#define IS_CAN_FILTER_FIFO(x) (((x) == CAN_FILTER_FIFO0) || \ + ((x) == CAN_FILTER_FIFO1)) +#define IS_CAN_IDTYPE(x) (((x) == CAN_ID_STD) || \ + ((x) == CAN_ID_EXT)) +#define IS_CAN_RTR(x) (((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE)) +#define IS_CAN_FIFO(x) (((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1)) +#define IS_CAN_BANKNUMBER(x) ((x) <= 28) +#define IS_CAN_TX_MAILBOX(x) ((x) <= CAN_TX_MAILBOX_NONE) +#define IS_CAN_STDID(x) ((x) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(x) ((x) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DATA_LEN(x) ((x) <= ((uint8_t)0x08)) +#define IS_CAN_PRESCALER(x) (((x) >= 1) && ((x) <= 1024)) +#define IS_CAN_GET_FLAG(x) (((x) == CAN_FLAG_SLAK) || \ + ((x) == CAN_FLAG_WKU) || \ + ((x) == CAN_FLAG_SLAKI) || \ + ((x) == CAN_FLAG_RQCP0) || \ + ((x) == CAN_FLAG_TXOK0) || \ + ((x) == CAN_FLAG_RQCP1) || \ + ((x) == CAN_FLAG_TXOK1) || \ + ((x) == CAN_FLAG_RQCP2) || \ + ((x) == CAN_FLAG_TXOK2) || \ + ((x) == CAN_FLAG_TME0) || \ + ((x) == CAN_FLAG_TME1) || \ + ((x) == CAN_FLAG_TME2) || \ + ((x) == CAN_FLAG_FF0) || \ + ((x) == CAN_FLAG_FOV0) || \ + ((x) == CAN_FLAG_FF1) || \ + ((x) == CAN_FLAG_FOV1) || \ + ((x) == CAN_FLAG_EWG) || \ + ((x) == CAN_FLAG_EPV) || \ + ((x) == CAN_FLAG_BOF)) +#define IS_CAN_CLEAR_FLAG(x) (((x) == CAN_FLAG_WKU) || \ + ((x) == CAN_FLAG_SLAKI) || \ + ((x) == CAN_FLAG_RQCP0) || \ + ((x) == CAN_FLAG_RQCP1) || \ + ((x) == CAN_FLAG_RQCP2) || \ + ((x) == CAN_FLAG_FF0) || \ + ((x) == CAN_FLAG_FOV0) || \ + ((x) == CAN_FLAG_FF1) || \ + ((x) == CAN_FLAG_FOV1)) +#define IS_CAN_IT(x) (((x) == CAN_IT_TME) || \ + ((x) == CAN_IT_FMP0) || \ + ((x) == CAN_IT_FF0) || \ + ((x) == CAN_IT_FOV0) || \ + ((x) == CAN_IT_FMP1) || \ + ((x) == CAN_IT_FF1) || \ + ((x) == CAN_IT_FOV1) || \ + ((x) == CAN_IT_EWG) || \ + ((x) == CAN_IT_EPV) || \ + ((x) == CAN_IT_BOF) || \ + ((x) == CAN_IT_LEC) || \ + ((x) == CAN_IT_ERR) || \ + ((x) == CAN_IT_WKU) || \ + ((x) == CAN_IT_SLK)) +#define CAN_TIMEOUT_VALUE 100 +#define CAN_STATE_TX_MASK (1U << 4) +#define CAN_STATE_RX_MASK (1U << 5) +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions + * @{ + */ + +/** @addtogroup CAN_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void can_reset(can_handle_t *hperh); +ald_status_t can_init(can_handle_t *hperh); +ald_status_t can_filter_config(can_handle_t *hperh, can_filter_t *config); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout); +ald_status_t can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg); +ald_status_t can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout); +ald_status_t can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group3 + * @{ + */ +/* Control function */ +ald_status_t can_sleep(can_handle_t *hperh); +ald_status_t can_wake_up(can_handle_t *hperh); +void can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box); +void can_irq_handler(can_handle_t *hperh); +type_bool_t can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box); +void can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state); +it_status_t can_get_it_status(can_handle_t *hperh, can_it_t it); +flag_status_t can_get_flag_status(can_handle_t *hperh, can_flag_t flag); +void can_clear_flag_status(can_handle_t *hperh, can_flag_t flag); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group4 + * @{ + */ +/* State and Error functions */ +can_state_t can_get_state(can_handle_t *hperh); +can_error_t can_get_error(can_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CAN_H */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h new file mode 100644 index 0000000000..ced2976ea8 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h @@ -0,0 +1,632 @@ +/** + ********************************************************************************* + * + * @file ald_cmu.h + * @brief Header file of CMU module driver. + * + * @version V1.0 + * @date 22 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_CMU_H__ +#define __ALD_CMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_syscfg.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CMU + * @{ + */ + +/** @defgroup CMU_Public_Macros CMU Public Macros + * @{ + */ +#define CMU_LOSC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LOSC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LRC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LRC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_ULRC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_ULRC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) + +/* Low power mode control */ +#define CMU_LP_LRC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LP_LRC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LP_LOSC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LP_LOSC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LP_HRC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LP_HRC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LP_HOSC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LP_HOSC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +/** + * @} + */ + + +/** @defgroup CMU_Public_Types CMU Public Types + * @{ + */ +/** + * @brief CMU state structure definition + */ +typedef enum +{ + CMU_CLOCK_HRC = 0x1, /**< HRC */ + CMU_CLOCK_LRC = 0x2, /**< LRC */ + CMU_CLOCK_LOSC = 0x3, /**< LOSC */ + CMU_CLOCK_PLL1 = 0x4, /**< PLL1 */ + CMU_CLOCK_HOSC = 0x5, /**< HOSC */ +} cmu_clock_t; + +/** + * @brief PLL1 output clock + */ +typedef enum +{ + CMU_PLL1_OUTPUT_32M = 0x0, /**< x8 (32MHz) */ + CMU_PLL1_OUTPUT_48M = 0x1, /**< x12 (48MHz) */ +} cmu_pll1_output_t; + +/** + * @brief PLL1 referance clock + */ +typedef enum +{ + CMU_PLL1_INPUT_HRC_6 = 0x0, /**< HRC / 6 */ + CMU_PLL1_INPUT_PLL2 = 0x1, /**< PLL2 */ + CMU_PLL1_INPUT_HOSC = 0x2, /**< HOSC / 1 */ + CMU_PLL1_INPUT_HOSC_2 = 0x3, /**< HOSC / 2 */ + CMU_PLL1_INPUT_HOSC_3 = 0x4, /**< HOSC / 3 */ + CMU_PLL1_INPUT_HOSC_4 = 0x5, /**< HOSC / 4 */ + CMU_PLL1_INPUT_HOSC_5 = 0x6, /**< HOSC / 5 */ + CMU_PLL1_INPUT_HOSC_6 = 0x7, /**< HOSC / 6 */ +} cmu_pll1_input_t; + +/** + * @brief HOSC range + */ +typedef enum +{ + CMU_HOSC_2M = 0x0, + CMU_HOSC_4M = 0x1, + CMU_HOSC_8M = 0x2, + CMU_HOSC_16M = 0x3, + CMU_HOSC_24M = 0x4, +} cmu_hosc_range_t; + +/** + * @brief Auto-calibrate input + */ +typedef enum +{ + CMU_AUTO_CALIB_INPUT_LOSE = 0x0, + CMU_AUTO_CALIB_INPUT_HOSE = 0x1, +} cmu_auto_calib_input_t; + +/** + * @brief Auto-calibrate output + */ +typedef enum +{ + CMU_AUTO_CALIB_OUTPUT_24M = 0x0, + CMU_AUTO_CALIB_OUTPUT_2M = 0x1, +} cmu_auto_calib_output_t; + +/** + * @brief Frequency division select bit + */ +typedef enum +{ + CMU_DIV_1 = 0x0, /**< Division by 1 */ + CMU_DIV_2 = 0x1, /**< Division by 2 */ + CMU_DIV_4 = 0x2, /**< Division by 4 */ + CMU_DIV_8 = 0x3, /**< Division by 8 */ + CMU_DIV_16 = 0x4, /**< Division by 16 */ + CMU_DIV_32 = 0x5, /**< Division by 32 */ + CMU_DIV_64 = 0x6, /**< Division by 64 */ + CMU_DIV_128 = 0x7, /**< Division by 128 */ + CMU_DIV_256 = 0x8, /**< Division by 256 */ + CMU_DIV_512 = 0x9, /**< Division by 512 */ + CMU_DIV_1024 = 0xA, /**< Division by 1024 */ + CMU_DIV_2048 = 0xB, /**< Division by 2048 */ + CMU_DIV_4096 = 0xC, /**< Division by 4096 */ +} cmu_div_t; + +/** + * @brief Bus type + */ +typedef enum +{ + CMU_HCLK_1 = 0x0, /**< AHB1 bus */ + CMU_SYS = 0x1, /**< SYS bus */ + CMU_PCLK_1 = 0x2, /**< APB1 bus */ + CMU_PCLK_2 = 0x3, /**< APB2 bus */ +} cmu_bus_t; + +/** + * @brief Output high clock select + */ +typedef enum +{ + CMU_OUTPUT_HIGH_SEL_HOSC = 0x0, /**< Select HOSC */ + CMU_OUTPUT_HIGH_SEL_LOSC = 0x1, /**< Select LOSC */ + CMU_OUTPUT_HIGH_SEL_HRC = 0x2, /**< Select HRC */ + CMU_OUTPUT_HIGH_SEL_LRC = 0x3, /**< Select LRC */ + CMU_OUTPUT_HIGH_SEL_HOSM = 0x4, /**< Select HOSM */ + CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5, /**< Select PLL1 */ + CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6, /**< Select PLL2 */ + CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7, /**< Select SYSCLK */ +} cmu_output_high_sel_t; + +/** + * @brief Output frequency division + */ +typedef enum +{ + CMU_OUTPUT_DIV_1 = 0x0, /**< Division by 1 */ + CMU_OUTPUT_DIV_2 = 0x1, /**< Division by 2 */ + CMU_OUTPUT_DIV_4 = 0x2, /**< Division by 4 */ + CMU_OUTPUT_DIV_8 = 0x3, /**< Division by 8 */ + CMU_OUTPUT_DIV_16 = 0x4, /**< Division by 16 */ + CMU_OUTPUT_DIV_32 = 0x5, /**< Division by 32 */ + CMU_OUTPUT_DIV_64 = 0x6, /**< Division by 64 */ + CMU_OUTPUT_DIV_128 = 0x7, /**< Division by 128 */ +} cmu_output_high_div_t; + +/** + * @brief Output low clock select + */ +typedef enum +{ + CMU_OUTPUT_LOW_SEL_LOSC = 0x0, /**< Select LOSC */ + CMU_OUTPUT_LOW_SEL_LRC = 0x1, /**< Select LRC */ + CMU_OUTPUT_LOW_SEL_LOSM = 0x2, /**< Select LOSM */ + CMU_OUTPUT_LOW_SEL_BUZZ = 0x3, /**< Select BUZZ */ + CMU_OUTPUT_LOW_SEL_ULRC = 0x4, /**< Select ULRC */ +} cmu_output_low_sel_t; + +/** + * @brief BUZZ frequency division + */ +typedef enum +{ + CMU_BUZZ_DIV_2 = 0x0, /**< Division by 2 */ + CMU_BUZZ_DIV_4 = 0x1, /**< Division by 4 */ + CMU_BUZZ_DIV_8 = 0x2, /**< Division by 8 */ + CMU_BUZZ_DIV_16 = 0x3, /**< Division by 16 */ + CMU_BUZZ_DIV_32 = 0x4, /**< Division by 32 */ + CMU_BUZZ_DIV_64 = 0x5, /**< Division by 64 */ + CMU_BUZZ_DIV_128 = 0x6, /**< Division by 128 */ + CMU_BUZZ_DIV_256 = 0x7, /**< Division by 256 */ +} cmu_buzz_div_t; + +/** + * @brief Low power peripheral clock select + */ +typedef enum +{ + CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0, /**< Select PCLK2 */ + CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1, /**< Select PLL1 */ + CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2, /**< Select PLL2 */ + CMU_LP_PERH_CLOCK_SEL_HRC = 0x3, /**< Select HRC */ + CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4, /**< Select HOSC */ + CMU_LP_PERH_CLOCK_SEL_LRC = 0x5, /**< Select LRC */ + CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6, /**< Select LOSC */ + CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7, /**< Select ULRC */ + CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8, /**< Select HRC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9, /**< Select HOSC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_LOSM = 0xA, /**< Select LOSM */ + CMU_LP_PERH_CLOCK_SEL_HOSM = 0xB, /**< Select HOSM */ +} cmu_lp_perh_clock_sel_t; + +/** + * @brief LCD clock select + */ +typedef enum +{ + CMU_LCD_SEL_LOSM = 0x0, /**< Select LOSM */ + CMU_LCD_SEL_LOSC = 0x1, /**< Select LOSC */ + CMU_LCD_SEL_LRC = 0x2, /**< Select LRC */ + CMU_LCD_SEL_ULRC = 0x3, /**< Select ULRC */ + CMU_LCD_SEL_HRC_1M = 0x4, /**< Select HRC down to 1MHz */ + CMU_LCD_SEL_HOSC_1M = 0x5, /**< Select HOSC down to 1MHz */ +} cmu_lcd_clock_sel_t; + +/** + * @brief Peripheral clock enable/disable + */ +typedef enum +{ + CMU_PERH_GPIO = (1U << 0), /**< GPIO */ + CMU_PERH_CRC = (1U << 1), /**< CRC */ + CMU_PERH_CALC = (1U << 2), /**< CALC */ + CMU_PERH_CRYPT = (1U << 3), /**< CRYPT */ + CMU_PERH_TRNG = (1U << 4), /**< TRNG */ + CMU_PERH_PIS = (1U << 5), /**< PIS */ + CMU_PERH_TIM0 = (1U << 0) | (1U << 27), /**< TIM0 */ + CMU_PERH_TIM1 = (1U << 1) | (1U << 27), /**< TIM1 */ + CMU_PERH_TIM2 = (1U << 2) | (1U << 27), /**< TIM2 */ + CMU_PERH_TIM3 = (1U << 3) | (1U << 27), /**< TIM3 */ + CMU_PERH_TIM4 = (1U << 4) | (1U << 27), /**< TIM4 */ + CMU_PERH_TIM5 = (1U << 5) | (1U << 27), /**< TIM5 */ + CMU_PERH_TIM6 = (1U << 6) | (1U << 27), /**< TIM6 */ + CMU_PERH_TIM7 = (1U << 7) | (1U << 27), /**< TIM7 */ + CMU_PERH_UART0 = (1U << 8) | (1U << 27), /**< UART0 */ + CMU_PERH_UART1 = (1U << 9) | (1U << 27), /**< UART1 */ + CMU_PERH_UART2 = (1U << 10) | (1U << 27), /**< UART2 */ + CMU_PERH_UART3 = (1U << 11) | (1U << 27), /**< UART3 */ + CMU_PERH_USART0 = (1U << 12) | (1U << 27), /**< USART0 */ + CMU_PERH_USART1 = (1U << 13) | (1U << 27), /**< USART1 */ + CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ + CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ + CMU_PERH_SPI2 = (1U << 18) | (1U << 27), /**< SPI2 */ + CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ + CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ + CMU_PERH_CAN = (1U << 24) | (1U << 27), /**< CAN */ + CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), /**< LPTIM0 */ + CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), /**< LPUART0 */ + CMU_PERH_ADC0 = (1U << 4) | (1U << 28), /**< ADC0 */ + CMU_PERH_ADC1 = (1U << 5) | (1U << 28), /**< ADC1 */ + CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), /**< ACMP0 */ + CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), /**< ACMP1 */ + CMU_PERH_OPAMP = (1U << 8) | (1U << 28), /**< OPAMP */ + CMU_PERH_DAC0 = (1U << 9) | (1U << 28), /**< DAC0 */ + CMU_PERH_WWDT = (1U << 12) | (1U << 28), /**< WWDT */ + CMU_PERH_LCD = (1U << 13) | (1U << 28), /**< LCD */ + CMU_PERH_IWDT = (1U << 14) | (1U << 28), /**< IWDT */ + CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */ + CMU_PERH_TEMP = (1U << 16) | (1U << 28), /**< TEMP */ + CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */ + CMU_PERH_BKRPAM = (1U << 18) | (1U << 28), /**< BKPRAM */ + CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */ + CMU_PERH_ALL = (0x7FFFFFFF), /**< ALL */ +} cmu_perh_t; + +/** + * @brief CMU interrupt type + */ +typedef enum +{ + CMU_LOSC_STOP = 0x0, /**< LOSC STOP INTERRUPT */ + CMU_HOSC_STOP = 0x1, /**< HOSC STOP INTERRUPT */ + CMU_PLL1_UNLOCK = 0x2, /**< PLL1 UNLOCK INTERRUPT */ + CMU_LOSC_START = 0x3, /**< LOSC START INTERRUPT */ + CMU_HOSC_START = 0x4, /**< HOSC START INTERRUPT */ +} cmu_security_t; + +/** + * @brief CMU clock state type + */ +typedef enum +{ + CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ + CMU_CLOCK_STATE_LOSCACT = (1U << 1), /**< LOSC active */ + CMU_CLOCK_STATE_HRCACT = (1U << 2), /**< HRC active */ + CMU_CLOCK_STATE_LRCACT = (1U << 3), /**< LRC active */ + CMU_CLOCK_STATE_ULRCACT = (1U << 4), /**< ULRC active */ + CMU_CLOCK_STATE_PLLACT = (1U << 8), /**< PLL active */ + CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ + CMU_CLOCK_STATE_LOSCRDY = (1U << 17), /**< LOSC ready */ + CMU_CLOCK_STATE_HRCRDY = (1U << 18), /**< HRC ready */ + CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ + CMU_CLOCK_STATE_PLLRDY = (1U << 24), /**< PLL ready */ +} cmu_clock_state_t; +/** + * @} + */ + +/** + * @defgroup CMU_Private_Macros CMU Private Macros + * @{ + */ +#define IS_CMU_CLOCK(x) (((x) == CMU_CLOCK_HRC) || \ + ((x) == CMU_CLOCK_LRC) || \ + ((x) == CMU_CLOCK_LOSC) || \ + ((x) == CMU_CLOCK_PLL1) || \ + ((x) == CMU_CLOCK_HOSC)) +#define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_32M) || \ + ((x) == CMU_PLL1_OUTPUT_48M)) +#define IS_CMU_PLL1_INPUT(x) (((x) == CMU_PLL1_INPUT_HRC_6) || \ + ((x) == CMU_PLL1_INPUT_PLL2) || \ + ((x) == CMU_PLL1_INPUT_HOSC) || \ + ((x) == CMU_PLL1_INPUT_HOSC_2) || \ + ((x) == CMU_PLL1_INPUT_HOSC_3) || \ + ((x) == CMU_PLL1_INPUT_HOSC_4) || \ + ((x) == CMU_PLL1_INPUT_HOSC_5) || \ + ((x) == CMU_PLL1_INPUT_HOSC_6)) +#define IS_CMU_HOSC_RANGE(x) (((x) == CMU_HOSC_2M) || \ + ((x) == CMU_HOSC_4M) || \ + ((x) == CMU_HOSC_8M) || \ + ((x) == CMU_HOSC_16M) || \ + ((x) == CMU_HOSC_24M)) +#define IS_CMU_DIV(x) (((x) == CMU_DIV_1) || \ + ((x) == CMU_DIV_2) || \ + ((x) == CMU_DIV_4) || \ + ((x) == CMU_DIV_8) || \ + ((x) == CMU_DIV_16) || \ + ((x) == CMU_DIV_32) || \ + ((x) == CMU_DIV_64) || \ + ((x) == CMU_DIV_128) || \ + ((x) == CMU_DIV_256) || \ + ((x) == CMU_DIV_512) || \ + ((x) == CMU_DIV_1024) || \ + ((x) == CMU_DIV_2048) || \ + ((x) == CMU_DIV_4096)) +#define IS_CMU_BUS(x) (((x) == CMU_HCLK_1) || \ + ((x) == CMU_SYS) || \ + ((x) == CMU_PCLK_1) || \ + ((x) == CMU_PCLK_2)) +#define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_HRC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_LRC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK)) +#define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == CMU_OUTPUT_DIV_1) || \ + ((x) == CMU_OUTPUT_DIV_2) || \ + ((x) == CMU_OUTPUT_DIV_4) || \ + ((x) == CMU_OUTPUT_DIV_8) || \ + ((x) == CMU_OUTPUT_DIV_16) || \ + ((x) == CMU_OUTPUT_DIV_32) || \ + ((x) == CMU_OUTPUT_DIV_64) || \ + ((x) == CMU_OUTPUT_DIV_128)) +#define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \ + ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \ + ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \ + ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \ + ((x) == CMU_OUTPUT_LOW_SEL_ULRC)) +#define IS_CMU_AUTO_CALIB_INPUT(x) (((x) == CMU_AUTO_CALIB_INPUT_LOSE) || \ + ((x) == CMU_AUTO_CALIB_INPUT_HOSE)) +#define IS_CMU_AUTO_CALIB_OUTPUT(x) (((x) == CMU_AUTO_CALIB_OUTPUT_24M) || \ + ((x) == CMU_AUTO_CALIB_OUTPUT_2M)) +#define IS_CMU_BUZZ_DIV(x) (((x) == CMU_BUZZ_DIV_2) || \ + ((x) == CMU_BUZZ_DIV_4) || \ + ((x) == CMU_BUZZ_DIV_8) || \ + ((x) == CMU_BUZZ_DIV_16) || \ + ((x) == CMU_BUZZ_DIV_32) || \ + ((x) == CMU_BUZZ_DIV_64) || \ + ((x) == CMU_BUZZ_DIV_128) || \ + ((x) == CMU_BUZZ_DIV_256)) +#define IS_CMU_LP_PERH_CLOCK_SEL(x) (((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM)) +#define IS_CMU_LCD_CLOCK_SEL(x) (((x) == CMU_LCD_SEL_LOSM) || \ + ((x) == CMU_LCD_SEL_LOSC) || \ + ((x) == CMU_LCD_SEL_LRC) || \ + ((x) == CMU_LCD_SEL_ULRC) || \ + ((x) == CMU_LCD_SEL_HRC_1M) || \ + ((x) == CMU_LCD_SEL_HOSC_1M)) +#define IS_CMU_PERH(x) (((x) == CMU_PERH_GPIO) || \ + ((x) == CMU_PERH_CRC) || \ + ((x) == CMU_PERH_CALC) || \ + ((x) == CMU_PERH_CRYPT) || \ + ((x) == CMU_PERH_TRNG) || \ + ((x) == CMU_PERH_PIS) || \ + ((x) == CMU_PERH_TIM0) || \ + ((x) == CMU_PERH_TIM1) || \ + ((x) == CMU_PERH_TIM2) || \ + ((x) == CMU_PERH_TIM3) || \ + ((x) == CMU_PERH_TIM4) || \ + ((x) == CMU_PERH_TIM5) || \ + ((x) == CMU_PERH_TIM6) || \ + ((x) == CMU_PERH_TIM7) || \ + ((x) == CMU_PERH_UART0) || \ + ((x) == CMU_PERH_UART1) || \ + ((x) == CMU_PERH_UART2) || \ + ((x) == CMU_PERH_UART3) || \ + ((x) == CMU_PERH_USART0) || \ + ((x) == CMU_PERH_USART1) || \ + ((x) == CMU_PERH_SPI0) || \ + ((x) == CMU_PERH_SPI1) || \ + ((x) == CMU_PERH_SPI2) || \ + ((x) == CMU_PERH_I2C0) || \ + ((x) == CMU_PERH_I2C1) || \ + ((x) == CMU_PERH_CAN) || \ + ((x) == CMU_PERH_LPTIM0) || \ + ((x) == CMU_PERH_LPUART0) || \ + ((x) == CMU_PERH_ADC0) || \ + ((x) == CMU_PERH_ADC1) || \ + ((x) == CMU_PERH_ACMP0) || \ + ((x) == CMU_PERH_ACMP1) || \ + ((x) == CMU_PERH_OPAMP) || \ + ((x) == CMU_PERH_DAC0) || \ + ((x) == CMU_PERH_WWDT) || \ + ((x) == CMU_PERH_LCD) || \ + ((x) == CMU_PERH_IWDT) || \ + ((x) == CMU_PERH_RTC) || \ + ((x) == CMU_PERH_TEMP) || \ + ((x) == CMU_PERH_BKPC) || \ + ((x) == CMU_PERH_BKRPAM ) || \ + ((x) == CMU_PERH_DBGC) || \ + ((x) == CMU_PERH_ALL)) +#define IS_CMU_CLOCK_STATE(x) (((x) == CMU_CLOCK_STATE_HOSCACT) || \ + ((x) == CMU_CLOCK_STATE_LOSCACT) || \ + ((x) == CMU_CLOCK_STATE_HRCACT) || \ + ((x) == CMU_CLOCK_STATE_LRCACT) || \ + ((x) == CMU_CLOCK_STATE_ULRCACT) || \ + ((x) == CMU_CLOCK_STATE_PLLACT) || \ + ((x) == CMU_CLOCK_STATE_HOSCRDY) || \ + ((x) == CMU_CLOCK_STATE_LOSCRDY) || \ + ((x) == CMU_CLOCK_STATE_HRCRDY) || \ + ((x) == CMU_CLOCK_STATE_LRCRDY) || \ + ((x) == CMU_CLOCK_STATE_PLLRDY)) +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions + * @{ + */ +/** @addtogroup CMU_Public_Functions_Group1 + * @{ + */ +/* System clock configure */ +ald_status_t cmu_clock_config_default(void); +ald_status_t cmu_clock_config(cmu_clock_t clk, uint32_t clock); +void cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output); +uint32_t cmu_get_clock(void); +int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group2 + * @{ + */ +/* BUS division control */ +void cmu_div_config(cmu_bus_t bus, cmu_div_t div); +uint32_t cmu_get_hclk1_clock(void); +uint32_t cmu_get_sys_clock(void); +uint32_t cmu_get_pclk1_clock(void); +uint32_t cmu_get_pclk2_clock(void); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group3 + * @{ + */ +/* Clock safe configure */ +void cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status); +void cmu_losc_safe_config(type_func_t status); +void cmu_pll_safe_config(type_func_t status); +flag_status_t cmu_get_clock_state(cmu_clock_state_t sr); +void cmu_irq_cbk(cmu_security_t se); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group4 + * @{ + */ +/* Clock output configure */ +void cmu_output_high_clock_config(cmu_output_high_sel_t sel, + cmu_output_high_div_t div, type_func_t status); +void cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group5 + * @{ + */ +/* Peripheral Clock configure */ +void cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status); +void cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock); +void cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock); +void cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock); +void cmu_perh_clock_config(cmu_perh_t perh, type_func_t status); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CMU_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h new file mode 100644 index 0000000000..2a91282ab6 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h @@ -0,0 +1,55 @@ +/** + ********************************************************************************* + * + * @file ald_conf.h + * @brief Enable/Disable the peripheral module. + * + * @version V1.0 + * @date 18 Apr 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + + +#ifndef __ALD_CONF_H__ +#define __ALD_CONF_H__ + + +#define ALD_DMA +#define ALD_GPIO +#define ALD_UART +#define ALD_LPUART +#define ALD_USART +#define ALD_SMARTCARD /* The ALD_SMARTCARD depend on ALD_USART */ +#define ALD_I2C +#define ALD_CMU +#define ALD_RMU +#define ALD_PMU +#define ALD_WDT +#define ALD_LCD +#define ALD_RTC +#define ALD_CAN +#define ALD_FLASH +#define ALD_ADC +#define ALD_CRC +#define ALD_CRYPT +#define ALD_TIMER +#define ALD_LPTIM +#define ALD_PIS +#define ALD_SPI +#define ALD_CALC +#define ALD_ACMP +#define ALD_OPAMP +#define ALD_TRNG +#define ALD_TEMP +#define ALD_BKPC +#define ALD_DAC +#define ALD_IAP + +#define TICK_INT_PRIORITY 3 + +#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h new file mode 100644 index 0000000000..5562db71f4 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h @@ -0,0 +1,197 @@ +/** + ********************************************************************************* + * + * @file ald_crc.h + * @brief Header file of CRC module driver. + * + * @version V1.0 + * @date 6 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_CRC_H__ +#define __ALD_CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Public_Types CRC Public Types + * @{ + */ + +/** + * @brief CRC mode + */ +typedef enum +{ + CRC_MODE_CCITT = 0, /**< Ccitt */ + CRC_MODE_8 = 1, /**< Crc8 */ + CRC_MODE_16 = 2, /**< Crc16 */ + CRC_MODE_32 = 3, /**< Crc32 */ +} crc_mode_t; + +/** + * @brief CRC input length + */ +typedef enum +{ + CRC_LEN_AUTO = 0, /**< Auto */ + CRC_DATASIZE_8 = 1, /**< Byte */ + CRC_DATASIZE_16 = 2, /**< Half word */ + CRC_DATASIZE_32 = 3, /**< Word */ +} crc_datasize_t; + +/** + * @brief CRC whether write error or no + */ +typedef enum +{ + CRC_WERR_NO = 0, /**< No error */ + CRC_WERR_ERR = 1, /**< Error */ +} crc_werr_t; + +/** + * @brief CRC state structures definition + */ +typedef enum +{ + CRC_STATE_RESET = 0x0, /**< Peripheral is not initialized */ + CRC_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ + CRC_STATE_BUSY = 0x2, /**< An internal process is ongoing */ + CRC_STATE_ERROR = 0x4, /**< Error */ +} crc_state_t; + +/** + * @brief CRC init structure definition + */ +typedef struct +{ + crc_mode_t mode; /**< CRC mode */ + type_func_t data_rev; /**< CRC data reverse or no */ + type_func_t data_inv; /**< CRC data inverse or no */ + type_func_t chs_rev; /**< CRC check sum reverse or no */ + type_func_t chs_inv; /**< CRC check sum inverse or no */ + uint32_t seed; /**< CRC seed */ +} crc_init_t; + +/** + * @brief CRC Handle Structure definition + */ +typedef struct crc_handle_s +{ + CRC_TypeDef *perh; /**< Register base address */ + crc_init_t init; /**< CRC required parameters */ + uint8_t *cal_buf; /**< The pointer of preparing buffer */ + uint32_t *cal_res; /**< The pointer of result */ +#ifdef ALD_DMA + dma_handle_t hdma; /**< CRC DMA handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + crc_state_t state; /**< CRC operation state */ + + void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */ + void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */ +} crc_handle_t; +/** + * @} + */ + +/** @defgroup CRC_Public_Macros CRC Public Macros + * @{ + */ +#define CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) +#define CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) +#define CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK)) +#define CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) +#define CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) +#define CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK)) +/** + * @} + */ + +/** @defgroup CRC_Private_Macros CRC Private Macros + * @{ + */ +#define IS_CRC(x) ((x) == CRC) +#define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \ + ((x) == CRC_MODE_8) || \ + ((x) == CRC_MODE_16) || \ + ((x) == CRC_MODE_32)) +/** + * @} + */ + +/** @addtogroup CRC_Public_Functions + * @{ + */ + +/** @addtogroup CRC_Public_Functions_Group1 + * @{ + */ +ald_status_t crc_init(crc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup CRC_Public_Functions_Group2 + * @{ + */ +uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size); +/** + * @} + */ + +#ifdef ALD_DMA +/** @addtogroup CRC_Public_Functions_Group3 + * @{ + */ +ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t crc_dma_pause(crc_handle_t *hperh); +ald_status_t crc_dma_resume(crc_handle_t *hperh); +ald_status_t crc_dma_stop(crc_handle_t *hperh); +/** + * @} + */ +#endif +/** @addtogroup CRC_Public_Functions_Group4 + * @{ + */ +crc_state_t crc_get_state(crc_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CRC_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h new file mode 100644 index 0000000000..f3a5ebaeb5 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h @@ -0,0 +1,264 @@ +/** + ********************************************************************************* + * + * @file ald_crypt.h + * @brief Header file of CRYPT module driver. + * + * @version V1.0 + * @date 7 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_CRYPT_H__ +#define __ALD_CRYPT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CRYPT + * @{ + */ + +/** @defgroup CRYPT_Public_Types CRYPT Public Types + * @{ + */ + +/** + * @brief CRYPT encrypt or decrypt select + */ +typedef enum +{ + CRYPT_DECRYPT = 0, /**< Decrypt */ + CRYPT_ENCRYPT = 1, /**< Encrypt */ +} crypt_encs_t; + +/** + * @brief CRYPT mode select + */ +typedef enum +{ + CRYPT_MODE_ECB = 0, /**< ECB */ + CRYPT_MODE_CBC = 1, /**< CBC */ + CRYPT_MODE_CTR = 2, /**< CTR */ +} crypt_mode_t; + +/** + * @brief CRYPT data type + */ +typedef enum +{ + CRYPT_DATA_CHANGE_NO = 0, /**< No exchange */ + CRYPT_DATA_CHANGE_16 = 1, /**< 16bit exchange */ + CRYPT_DATA_CHANGE_8 = 2, /**< 8bit exchange */ + CRYPT_DATA_CHANGE_1 = 3, /**< 1bit exchange */ +} crypt_datatype_t; + +/** + * @brief CRYPT interrupt + */ +typedef enum +{ + CRYPT_IT_IT = 0x80, /**< Interrupt */ +} crypt_it_t; + +/** + * @brief CRYPT interrupt flag + */ +typedef enum +{ + CRYPT_FLAG_AESIF = 0x1, /**< Aes flag */ + CRYPT_FLAG_DONE = 0x100, /**< Complete flag */ +} crypt_flag_t; + +/** + * @brief CRYPT state structures definition + */ +typedef enum +{ + CRYPT_STATE_RESET = 0x0, /**< Peripheral is not initialized */ + CRYPT_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ + CRYPT_STATE_BUSY = 0x2, /**< An internal process is ongoing */ + CRYPT_STATE_ERROR = 0x4, /**< Error */ +} crypt_state_t; + +/** + * @brief CRYPT data type + */ +typedef enum +{ + DATA_32_BIT = 0, /**< 32 bit data,don't swap */ + DATA_16_BIT = 1, /**< 16 bit data,swap */ + DATA_8_BIT = 2, /**< 8 bit data,swap */ + DATA_1_BIT = 3, /**< 1 bit data, swap */ +} crypt_data_t; + +/** + * @brief CRYPT init structure definition + */ +typedef struct +{ + crypt_mode_t mode; /**< Crypt mode */ + crypt_data_t type; /**< Data type select */ +} crypt_init_t; + +/** + * @brief CRYPT Handle Structure definition + */ +typedef struct crypt_handle_s +{ + CRYPT_TypeDef *perh; /**< Register base address */ + crypt_init_t init; /**< CRYPT required parameters */ +#ifdef ALD_DMA + dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */ + dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */ +#endif + uint8_t *plain_text; /**< Pointer to plain text */ + uint8_t *cipher_text; /**< Pointer to cipher text */ + uint32_t size; /**< The size of crypt data buf */ + uint32_t count; /**< The count of crypt data buf */ + uint32_t step; /**< The step of once crypt 4(aes) */ + uint32_t dir; /**< ENCRYPT or DECRYPT */ + uint32_t iv[4]; /**< The iv of crypt */ + uint32_t key[4]; /**< The key of crypt */ + lock_state_t lock; /**< Locking object */ + crypt_state_t state; /**< CRYPT operation state */ + + void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */ + void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */ +} crypt_handle_t; +/** + * @} + */ + +/** @defgroup CRYPT_Public_Macros CRYPT Public Macros + * @{ + */ +#define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK)) +#define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) +#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) +#define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) +#define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) +#define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) +#define CRYPT_IE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) +#define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) +#define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) +#define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \ + (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0) +#define CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data)) +#define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO) +/** + * @} + */ + +/** @defgroup CRYPT_Private_Macros CRYPT Private Macros + * @{ + */ +#define IS_CRYPT(x) ((x) == CRYPT) +#define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \ + ((x) == CRYPT_MODE_CBC) || \ + ((x) == CRYPT_MODE_CTR)) +#define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT) +#define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \ + ((x) == CRYPT_FLAG_DONE)) +#define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \ + ((x) == IV_4_LEN)) +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions + * @{ + */ + +/** @addtogroup CRYPT_Public_Functions_Group1 + * @{ + */ +ald_status_t crypt_init(crypt_handle_t *hperh); +ald_status_t crypt_write_key(crypt_handle_t *hperh, uint32_t *key); +ald_status_t crypt_read_key(crypt_handle_t *hperh, uint32_t *key); +ald_status_t crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv); +ald_status_t crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv); +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group2 + * @{ + */ +ald_status_t crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size); +ald_status_t crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); +ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag); +ald_status_t crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size); +ald_status_t crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); +#ifdef ALD_DMA +ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, + uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); +ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, + uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); +#endif +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group3 + * @{ + */ +#ifdef ALD_DMA +ald_status_t crypt_dma_pause(crypt_handle_t *hperh); +ald_status_t crypt_dma_resume(crypt_handle_t *hperh); +ald_status_t crypt_dma_stop(crypt_handle_t *hperh); +#endif +void crypt_irq_handle(crypt_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group4 + * @{ + */ +void crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state); +flag_status_t crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); +void crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); +it_status_t crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it); +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group5 + * @{ + */ +crypt_state_t crypt_get_state(crypt_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h new file mode 100644 index 0000000000..293997c04e --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h @@ -0,0 +1,160 @@ +/** + ********************************************************************************* + * + * @file ald_dbgc.h + * @brief DEBUGCON module driver. + * + * @version V1.0 + * @date 04 Jun 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_DBGC_H__ +#define __ALD_DBGC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup DBGC DBGC + * @brief DBGC module driver + * @{ + */ + + + +/** @defgroup DBGC_Public_Types DBGC Public Types + * @{ + */ +/** + * @brief Debug mode select + */ +typedef enum +{ + DEBC_MODE_SLEEP = (1u << 0), /**< Sleep mode */ + DEBC_MODE_STOP1 = (1u << 1), /**< STOP1 mode */ + DEBC_MODE_STOP2 = (1u << 2), /**< STOP2 mode */ + DEBC_MODE_STANDBY = (1u << 3), /**< Standby mode */ +} dbgc_mode_t; + +/** + * @brief Debug peripheral select + */ +typedef enum +{ + DEBC_PERH_TIMER0 = (1u << 0), /**< AD16C4T0 */ + DEBC_PERH_TIMER1 = (1u << 1), /**< BS16T0 */ + DEBC_PERH_TIMER2 = (1u << 2), /**< GP16C2T0 */ + DEBC_PERH_TIMER3 = (1u << 3), /**< GP16C2T1 */ + DEBC_PERH_TIMER4 = (1u << 4), /**< BS16T1 */ + DEBC_PERH_TIMER5 = (1u << 5), /**< BS16T2 */ + DEBC_PERH_TIMER6 = (1u << 6), /**< GP16C4T0 */ + DEBC_PERH_TIMER7 = (1u << 7), /**< BS16T3 */ + DEBC_PERH_I2C0 = (1u << 8), /**< I2C0 SMBUS */ + DEBC_PERH_I2C1 = (1u << 9), /**< I2C1 SMBUS */ + DEBC_PERH_CAN = (1u << 12), /**< CAN */ + DEBC_PERH_LPTIM0 = (1u << 0) | (1u << 16), /**< LPTIM0 */ + DEBC_PERH_IWDT = (1u << 8) | (1u << 16), /**< IWDT */ + DEBC_PERH_WWDT = (1u << 9) | (1u << 16), /**< WWDT */ + DEBC_PERH_RTC = (1u << 10) | (1u << 16), /**< RTC */ +} dbgc_perh_t; +/** + * @} + */ + +/** @defgroup DBGC_Public_Functions DBGC Public Functions + * @{ + */ +/** + * @brief Gets version. + * @retval Version + */ +__INLINE uint32_t dbgc_get_rev_id(void) +{ + return (DBGC->IDCODE >> 16); +} + +/** + * @brief Gets core id. + * @retval Core id + */ +__INLINE uint32_t dbgc_get_core_id(void) +{ + return (DBGC->IDCODE >> 12) & 0xF; +} + +/** + * @brief Gets device id + * @retval device id + */ +__INLINE uint32_t dbgc_get_device_id(void) +{ + return DBGC->IDCODE & 0xFFF; +} + +/** + * @brief Configures low power debug mode + * @param mode: The mode of low power. + * @param state: ENABLE/DISABLE + * @retval None + */ +__INLINE void dbgc_mode_config(dbgc_mode_t mode, type_func_t state) +{ + if (state) + SET_BIT(DBGC->CR, mode); + else + CLEAR_BIT(DBGC->CR, mode); +} + +/** + * @brief Configures peripheral debug mode + * @param perh: The peripheral. + * @param state: ENABLE/DISABLE + * @retval None + */ +__INLINE void dbgc_perh_config(dbgc_perh_t perh, type_func_t state) +{ + if ((perh >> 16) & 0x1) + { + if (state) + SET_BIT(DBGC->APB2FZ, perh); + else + CLEAR_BIT(DBGC->APB2FZ, perh); + } + else + { + if (state) + SET_BIT(DBGC->APB1FZ, perh); + else + CLEAR_BIT(DBGC->APB1FZ, perh); + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h new file mode 100644 index 0000000000..646ae02a67 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h @@ -0,0 +1,389 @@ +/** + ********************************************************************************* + * + * @file ald_dma.h + * @brief DMA module Library. + * + * @version V1.0 + * @date 09 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_DMA_H__ +#define __ALD_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** + * @defgroup DMA_Public_Macros DMA Public Macros + * @{ + */ +#define DMA_CH_COUNT 6 +#define DMA_ERR 31 +/** + * @} + */ + +/** + * @defgroup DMA_Public_Types DMA Public Types + * @{ + */ + +/** + * @brief Input source to DMA channel + */ +typedef enum +{ + DMA_MSEL_NONE = 0x0, /**< NONE */ + DMA_MSEL_GPIO = 0x1, /**< GPIO */ + DMA_MSEL_CRYPT = 0x2, /**< CRYPT */ + DMA_MSEL_ACMP = 0x3, /**< ACMP */ + DMA_MSEL_DAC0 = 0x4, /**< DAC0 */ + DMA_MSEL_ADC0 = 0x6, /**< ADC0 */ + DMA_MSEL_CRC = 0x7, /**< CRC */ + DMA_MSEL_UART0 = 0x8, /**< UART0 */ + DMA_MSEL_UART1 = 0x9, /**< UART1 */ + DMA_MSEL_UART2 = 0xA, /**< UART2 */ + DMA_MSEL_UART3 = 0xB, /**< UART3 */ + DMA_MSEL_USART0 = 0xC, /**< USART0 */ + DMA_MSEL_USART1 = 0xD, /**< USART1 */ + DMA_MSEL_SPI0 = 0xE, /**< SPI0 */ + DMA_MSEL_SPI1 = 0xF, /**< SPI1 */ + DMA_MSEL_I2C0 = 0x10, /**< I2C0 */ + DMA_MSEL_I2C1 = 0x11, /**< I2C1 */ + DMA_MSEL_TIMER0 = 0x12, /**< TIMER0 */ + DMA_MSEL_TIMER1 = 0x13, /**< TIMER1 */ + DMA_MSEL_TIMER2 = 0x14, /**< TIMER2 */ + DMA_MSEL_TIMER3 = 0x15, /**< TIMER3 */ + DMA_MSEL_RTC = 0x16, /**< RTC */ + DMA_MSEL_LPTIM0 = 0x17, /**< LPTIM0 */ + DMA_MSEL_LPUART0 = 0x18, /**< LPUART0 */ + DMA_MSEL_DMA = 0x19, /**< DMA */ + DMA_MSEL_SPI2 = 0x1A, /**< SPI2 */ + DMA_MSEL_TIMER4 = 0x1B, /**< TIMER4 */ + DMA_MSEL_TIMER5 = 0x1C, /**< TIMER5 */ + DMA_MSEL_TIMER6 = 0x1D, /**< TIMER6 */ + DMA_MSEL_TIMER7 = 0x1E, /**< TIMER7 */ + DMA_MSEL_ADC1 = 0x1F, /**< ADC1 */ + DMA_MSEL_PIS = 0x20, /**< PIS */ + DMA_MSEL_TRNG = 0x21, /**< TRNG */ +} dma_msel_t; + +/** + * @brief Input signal to DMA channel + */ +typedef enum +{ + DMA_MSIGSEL_NONE = 0x0, /**< NONE */ + DMA_MSIGSEL_EXTI_0 = 0x0, /**< External interrupt 0 */ + DMA_MSIGSEL_EXTI_1 = 0x1, /**< External interrupt 1 */ + DMA_MSIGSEL_EXTI_2 = 0x2, /**< External interrupt 2 */ + DMA_MSIGSEL_EXTI_3 = 0x3, /**< External interrupt 3 */ + DMA_MSIGSEL_EXTI_4 = 0x4, /**< External interrupt 4 */ + DMA_MSIGSEL_EXTI_5 = 0x5, /**< External interrupt 5 */ + DMA_MSIGSEL_EXTI_6 = 0x6, /**< External interrupt 6 */ + DMA_MSIGSEL_EXTI_7 = 0x7, /**< External interrupt 7 */ + DMA_MSIGSEL_EXTI_8 = 0x8, /**< External interrupt 8 */ + DMA_MSIGSEL_EXTI_9 = 0x9, /**< External interrupt 9 */ + DMA_MSIGSEL_EXTI_10 = 0xA, /**< External interrupt 10 */ + DMA_MSIGSEL_EXTI_11 = 0xB, /**< External interrupt 11 */ + DMA_MSIGSEL_EXTI_12 = 0xC, /**< External interrupt 12 */ + DMA_MSIGSEL_EXTI_13 = 0xD, /**< External interrupt 13 */ + DMA_MSIGSEL_EXTI_14 = 0xE, /**< External interrupt 14 */ + DMA_MSIGSEL_EXTI_15 = 0xF, /**< External interrupt 15 */ + DMA_MSIGSEL_CRYPT_WRITE = 0x0, /**< CRYPT write mode */ + DMA_MSIGSEL_CRYPT_READ = 0x1, /**< CRYPT read mode */ + DMA_MSIGSEL_CALC_WRITE = 0x0, /**< CALC write mode */ + DMA_MSIGSEL_CALC_READ = 0x1, /**< CALC read mode */ + DMA_MSIGSEL_DAC0_CH0 = 0x0, /**< DAC0 channel 0 complete */ + DMA_MSIGSEL_DAC0_CH1 = 0x1, /**< DAC0 channel 1 complete */ + DMA_MSIGSEL_ADC = 0x0, /**< ADC mode */ + DMA_MSIGSEL_UART_TXEMPTY = 0x0, /**< UART transmit */ + DMA_MSIGSEL_UART_RNR = 0x1, /**< UART receive */ + DMA_MSIGSEL_USART_RNR = 0x0, /**< USART reveive */ + DMA_MSIGSEL_USART_TXEMPTY = 0x1, /**< USART transmit */ + DMA_MSIGSEL_SPI_RNR = 0x0, /**< SPI receive */ + DMA_MSIGSEL_SPI_TXEMPTY = 0x1, /**< SPI transmit */ + DMA_MSIGSEL_I2C_RNR = 0x0, /**< I2C receive */ + DMA_MSIGSEL_I2C_TXEMPTY = 0x1, /**< I2C transmit */ + DMA_MSIGSEL_TIMER_CH1 = 0x0, /**< TIM channal 1 */ + DMA_MSIGSEL_TIMER_CH2 = 0x1, /**< TIM channal 2 */ + DMA_MSIGSEL_TIMER_CH3 = 0x2, /**< TIM channal 3 */ + DMA_MSIGSEL_TIMER_CH4 = 0x3, /**< TIM channal 4 */ + DMA_MSIGSEL_TIMER_TRI = 0x4, /**< TIM trigger */ + DMA_MSIGSEL_TIMER_COMP = 0x5, /**< TIM compare */ + DMA_MSIGSEL_TIMER_UPDATE = 0x6, /**< TIM update */ + DMA_MSIGSEL_LPUART_RNR = 0x0, /**< LPUART receive */ + DMA_MSIGSEL_LPUART_TXEMPTY = 0x1, /**< LPUART transmit */ + DMA_MSIGSEL_PIS_CH0 = 0x0, /**< PIS channal 0 */ + DMA_MSIGSEL_PIS_CH1 = 0x1, /**< PIS channal 1 */ + DMA_MSIGSEL_PIS_CH2 = 0x2, /**< PIS channal 2 */ + DMA_MSIGSEL_PIS_CH3 = 0x3, /**< PIS channal 3 */ + DMA_MSIGSEL_PIS_CH4 = 0x4, /**< PIS channal 4 */ + DMA_MSIGSEL_PIS_CH5 = 0x5, /**< PIS channal 5 */ + DMA_MSIGSEL_PIS_CH6 = 0x6, /**< PIS channal 6 */ + DMA_MSIGSEL_PIS_CH7 = 0x7, /**< PIS channal 7 */ + DMA_MSIGSEL_PIS_CH8 = 0x8, /**< PIS channal 8 */ + DMA_MSIGSEL_PIS_CH9 = 0x9, /**< PIS channal 9 */ + DMA_MSIGSEL_PIS_CH10 = 0xA, /**< PIS channal 10 */ + DMA_MSIGSEL_PIS_CH11 = 0xB, /**< PIS channal 11 */ + DMA_MSIGSEL_PIS_CH12 = 0xC, /**< PIS channal 12 */ + DMA_MSIGSEL_PIS_CH13 = 0xD, /**< PIS channal 13 */ + DMA_MSIGSEL_PIS_CH14 = 0xE, /**< PIS channal 14 */ + DMA_MSIGSEL_PIS_CH15 = 0xF, /**< PIS channal 15 */ +} dma_msigsel_t; + +/** + * @brief DMA Descriptor control type + */ +typedef union +{ + struct + { + uint32_t cycle_ctrl : 3; /**< DMA operating mode @ref dma_cycle_ctrl_t */ + uint32_t next_useburst : 1; /**< Uses the alternate data structure when complete a DMA cycle */ + uint32_t n_minus_1 : 10; /**< Represent the total number of DMA transfers that DMA cycle contains. */ + uint32_t R_power : 4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ + uint32_t src_prot_ctrl : 3; /**< Control the state of HPROT when reads the source data. */ + uint32_t dst_prot_ctrl : 3; /**< Control the state of HPROT when writes the destination data */ + uint32_t src_size : 2; /**< Source data size @ref dma_data_size_t */ + uint32_t src_inc : 2; /**< Control the source address increment. @ref dma_data_inc_t */ + uint32_t dst_size : 2; /**< Destination data size. @ref dma_data_size_t */ + uint32_t dst_inc : 2; /**< Destination address increment. @ref dma_data_inc_t */ + }; + uint32_t word; +} dma_ctrl_t; + +/** + * @brief Channel control data structure + */ +typedef struct +{ + void *src; /**< Source data end pointer */ + void *dst; /**< Destination data end pointer */ + dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */ + uint32_t use; /**< Reserve for user */ +} dma_descriptor_t; + +/** + * @brief data increment + */ +typedef enum +{ + DMA_DATA_INC_BYTE = 0x0, /**< Address increment by byte */ + DMA_DATA_INC_HALFWORD = 0x1, /**< Address increment by halfword */ + DMA_DATA_INC_WORD = 0x2, /**< Address increment by word */ + DMA_DATA_INC_NONE = 0x3, /**< No increment */ +} dma_data_inc_t; + +/** + * @brief Data size + */ +typedef enum +{ + DMA_DATA_SIZE_BYTE = 0x0, /**< Byte */ + DMA_DATA_SIZE_HALFWORD = 0x1, /**< Halfword */ + DMA_DATA_SIZE_WORD = 0x2, /**< Word */ +} dma_data_size_t; + +/** + * @brief The operating mode of the DMA cycle + */ +typedef enum +{ + DMA_CYCLE_CTRL_NONE = 0x0, /**< Stop */ + DMA_CYCLE_CTRL_BASIC = 0x1, /**< Basic */ + DMA_CYCLE_CTRL_AUTO = 0x2, /**< Auto-request */ + DMA_CYCLE_CTRL_PINGPONG = 0x3, /**< Ping-pong */ + DMA_CYCLE_CTRL_MEM_SCATTER_GATHER = 0x4, /**< Memory scatter/gather */ + DMA_CYCLE_CTRL_PER_SCATTER_GATHER = 0x6, /**< Peripheral scatter/gather */ +} dma_cycle_ctrl_t; + +/** + * @brief Control how many DMA transfers can occur + * before the controller re-arbitrates + */ +typedef enum +{ + DMA_R_POWER_1 = 0x0, /**< Arbitrates after each DMA transfer */ + DMA_R_POWER_2 = 0x1, /**< Arbitrates after 2 DMA transfer */ + DMA_R_POWER_4 = 0x2, /**< Arbitrates after 4 DMA transfer */ + DMA_R_POWER_8 = 0x3, /**< Arbitrates after 8 DMA transfer */ + DMA_R_POWER_16 = 0x4, /**< Arbitrates after 16 DMA transfer */ + DMA_R_POWER_32 = 0x5, /**< Arbitrates after 32 DMA transfer */ + DMA_R_POWER_64 = 0x6, /**< Arbitrates after 64 DMA transfer */ + DMA_R_POWER_128 = 0x7, /**< Arbitrates after 128 DMA transfer */ + DMA_R_POWER_256 = 0x8, /**< Arbitrates after 256 DMA transfer */ + DMA_R_POWER_512 = 0x9, /**< Arbitrates after 512 DMA transfer */ + DMA_R_POWER_1024 = 0xA, /**< Arbitrates after 1024 DMA transfer */ +} dma_arbiter_config_t; + +/** + * @brief Callback function pointer and param + */ +typedef struct +{ + void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*err_cbk)(void *arg); /**< DMA occurs error callback */ + void *cplt_arg; /**< The parameter of cplt_cbk() */ + void *err_arg; /**< The parameter of err_cbk() */ +} dma_call_back_t; + +/** + * @brief DMA channal configure structure + */ +typedef struct +{ + void *src; /**< Source data begin pointer */ + void *dst; /**< Destination data begin pointer */ + uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ + dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */ + dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */ + dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */ + dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ + type_func_t primary; /**< Use primary descriptor or alternate descriptor */ + type_func_t burst; /**< Uses the alternate data structure when complete a DMA cycle */ + type_func_t high_prio; /**< High priority or default priority */ + type_func_t iterrupt; /**< Enable/disable interrupt */ + dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */ + dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */ + uint8_t channel; /**< Channel index */ +} dma_config_t; + +/** + * @brief DMA handle structure definition + */ +typedef struct +{ + DMA_TypeDef *perh; /**< DMA registers base address */ + dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ + void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */ + void *cplt_arg; /**< The parameter of cplt_cbk() */ + void *err_arg; /**< The parameter of err_cbk() */ +} dma_handle_t; +/** + * @} + */ + +/** + * @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ +#define IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_TRNG) +#define IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF) +#define IS_DMA_DATAINC_TYPE(x) (((x) == DMA_DATA_INC_BYTE) || \ + ((x) == DMA_DATA_INC_HALFWORD) || \ + ((x) == DMA_DATA_INC_WORD) || \ + ((x) == DMA_DATA_INC_NONE)) +#define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \ + ((x) == DMA_DATA_SIZE_HALFWORD) || \ + ((x) == DMA_DATA_SIZE_WORD)) +#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ + ((x) == DMA_CYCLE_CTRL_BASIC) || \ + ((x) == DMA_CYCLE_CTRL_AUTO) || \ + ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ + ((x) == DMA_CYCLE_CTRL_MEM_SCATTER_GATHER) || \ + ((x) == DMA_CYCLE_CTRL_PER_SCATTER_GATHER)) +#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \ + ((x) == DMA_R_POWER_2) || \ + ((x) == DMA_R_POWER_4) || \ + ((x) == DMA_R_POWER_8) || \ + ((x) == DMA_R_POWER_16) || \ + ((x) == DMA_R_POWER_32) || \ + ((x) == DMA_R_POWER_64) || \ + ((x) == DMA_R_POWER_128) || \ + ((x) == DMA_R_POWER_256) || \ + ((x) == DMA_R_POWER_512) || \ + ((x) == DMA_R_POWER_1024)) +#define IS_DMA(x) ((x) == DMA0) +#define IS_DMA_CHANNEL(x) ((x) <= 5) +#define IS_DMA_DATA_SIZE(x) ((x) <= 1024) +#define IS_DMA_IT_TYPE(x) (((x) <= 5) || ((x) == 31)) +/** + * @} + */ + +/** + * @addtogroup DMA_Public_Functions + * @{ + */ + +/** @addtogroup DMA_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern void dma_reset(DMA_TypeDef *DMAx); +extern void dma_init(DMA_TypeDef *DMAx); +extern void dma_config_struct(dma_config_t *p); +/** + * @} + */ + + +/** @addtogroup DMA_Public_Functions_Group2 + * @{ + */ +/* Configure DMA channel functions */ +extern void dma_config_auto(dma_handle_t *hperh); +extern void dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size); +extern void dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, + uint16_t size, uint8_t channel, void (*cbk)(void *arg)); +extern void dma_config_basic(dma_handle_t *hperh); +extern void dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size); +extern void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, + dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); +/** + * @} + */ + +/** @addtogroup DMA_Public_Functions_Group3 + * @{ + */ +/* DMA control functions */ +extern void dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); +extern void dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); +extern it_status_t dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel); +extern flag_status_t dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel); +extern void dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel); +void dma0_irq_cbk(void); +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__ALD_DMA_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h new file mode 100644 index 0000000000..71449f946b --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h @@ -0,0 +1,122 @@ +/** + ********************************************************************************* + * + * @file ald_flash.h + * @brief Header file of FLASH driver + * + * @version V1.0 + * @date 20 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_FLASH_H__ +#define __ALD_FLASH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** + * @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ +#define FLASH_REG_UNLOCK() \ +do { \ + if (op_cmd == OP_FLASH) { \ + WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \ + WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \ + } \ + else { \ + WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \ + WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \ + } \ +} while (0) +#define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) +#define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) +#define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) +#define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) +#define FLASH_BASE_ADDR 0x00000000 +#define FLASH_PAGE_SIZE 1024UL +#define FLASH_WORD_SIZE 8UL +#define FLASH_TOTAL_SIZE 256UL +#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) +#define FLASH_WORD_MASK (FLASH_WORD_SIZE - 1) +#define IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE)) +#define IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0) +#define FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK)) +#define FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK) +#define FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK)) +#define FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK) +#define INFO_PAGE_SIZE 1024UL +#define INFO_PAGE_MASK (INFO_PAGE_SIZE - 1) +#define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK)) + +#ifdef USE_FLASH_FIFO +#define FLASH_FIFO 1 +#else +#define FLASH_FIFO 0 +#endif +/** + * @} + */ + +/** @defgroup FLASH_Private_Types FLASH Private Types + * @{ + */ +typedef enum +{ + FLASH_CMD_AE = 0x000051AE, /**< Program area erase all */ + FLASH_CMD_PE = 0x00005EA1, /**< Page erase */ + FLASH_CMD_WP = 0x00005DA2, /**< Word program */ + FLASH_CMD_DATAPE = 0x00005BA4, /**< Data flash page page erase */ + FLASH_CMD_DATAWP = 0x00005AA5, /**< Data flash word program */ +} flash_cmd_type; + +typedef enum +{ + OP_FLASH = 0, /**< Operate Pragram area */ + OP_INFO = 1, /**< Operate info area */ +} op_cmd_type; + +/** + * @} + */ + +/** @addtogroup Flash_Public_Functions + * @{ + */ +ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len); +ald_status_t flash_erase(uint32_t addr, uint16_t len); +ald_status_t flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_FLASH_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h new file mode 100644 index 0000000000..7e93a95751 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h @@ -0,0 +1,288 @@ +/** + ********************************************************************************* + * + * @file ald_gpio.h + * @brief Header file of GPIO module driver + * + * @version V1.0 + * @date 07 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_GPIO_H__ +#define __ALD_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** + * @defgroup GPIO_Public_Macros GPIO Public Macros + * @{ + */ +#define GPIO_PIN_0 (1U << 0) +#define GPIO_PIN_1 (1U << 1) +#define GPIO_PIN_2 (1U << 2) +#define GPIO_PIN_3 (1U << 3) +#define GPIO_PIN_4 (1U << 4) +#define GPIO_PIN_5 (1U << 5) +#define GPIO_PIN_6 (1U << 6) +#define GPIO_PIN_7 (1U << 7) +#define GPIO_PIN_8 (1U << 8) +#define GPIO_PIN_9 (1U << 9) +#define GPIO_PIN_10 (1U << 10) +#define GPIO_PIN_11 (1U << 11) +#define GPIO_PIN_12 (1U << 12) +#define GPIO_PIN_13 (1U << 13) +#define GPIO_PIN_14 (1U << 14) +#define GPIO_PIN_15 (1U << 15) +#define GPIO_PIN_ALL (0xFFFF) +/** + * @} + */ + +/** + * @defgroup GPIO_Public_Types GPIO Public Types + * @{ + */ + +/** + * @brief GPIO mode + */ +typedef enum +{ + GPIO_MODE_CLOSE = 0x0, /**< Digital close Analog open */ + GPIO_MODE_INPUT = 0x1, /**< Input */ + GPIO_MODE_OUTPUT = 0x2, /**< Output */ +} gpio_mode_t; + +/** + * @brief GPIO open-drain or push-pull + */ +typedef enum +{ + GPIO_PUSH_PULL = 0x0, /**< Push-Pull */ + GPIO_OPEN_DRAIN = 0x2, /**< Open-Drain */ + GPIO_OPEN_SOURCE = 0x3, /**< Open-Source */ +} gpio_odos_t; + +/** + * @brief GPIO push-up or push-down + */ +typedef enum +{ + GPIO_FLOATING = 0x0,/**< Floating */ + GPIO_PUSH_UP = 0x1,/**< Push-Up */ + GPIO_PUSH_DOWN = 0x2,/**< Push-Down */ + GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */ +} gpio_push_t; + +/** + * @brief GPIO output drive + */ +typedef enum +{ + GPIO_OUT_DRIVE_NORMAL = 0x0, /**< Normal current flow */ + GPIO_OUT_DRIVE_STRONG = 0x1, /**< Strong current flow */ +} gpio_out_drive_t; + +/** + * @brief GPIO filter + */ +typedef enum +{ + GPIO_FILTER_DISABLE = 0x0, /**< Disable filter */ + GPIO_FILTER_ENABLE = 0x1, /**< Enable filter */ +} gpio_filter_t; + +/** + * @brief GPIO type + */ +typedef enum +{ + GPIO_TYPE_CMOS = 0x0, /**< CMOS Type */ + GPIO_TYPE_TTL = 0x1, /**< TTL Type */ +} gpio_type_t; + +/** + * @brief GPIO functions + */ +typedef enum +{ + GPIO_FUNC_0 = 0, /**< function #0 */ + GPIO_FUNC_1 = 1, /**< function #1 */ + GPIO_FUNC_2 = 2, /**< function #2 */ + GPIO_FUNC_3 = 3, /**< function #3 */ + GPIO_FUNC_4 = 4, /**< function #4 */ + GPIO_FUNC_5 = 5, /**< function #5 */ + GPIO_FUNC_6 = 6, /**< function #6 */ + GPIO_FUNC_7 = 7, /**< function #7 */ +} gpio_func_t; + + +/** + * @brief GPIO Init Structure definition + */ +typedef struct +{ + gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. + This parameter can be any value of @ref gpio_mode_t */ + gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins. + This parameter can be a value of @ref gpio_odos_t */ + gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. + This parameter can be a value of @ref gpio_push_t */ + gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins. + This parameter can be a value of @ref gpio_out_drive_t */ + gpio_filter_t flt; /**< Specifies the input filter for the selected pins. + This parameter can be a value of @ref gpio_filter_t */ + gpio_type_t type; /**< Specifies the type for the selected pins. + This parameter can be a value of @ref gpio_type_t */ + gpio_func_t func; /**< Specifies the function for the selected pins. + This parameter can be a value of @ref gpio_func_t */ +} gpio_init_t; + +/** + * @brief EXTI trigger style + */ +typedef enum +{ + EXTI_TRIGGER_RISING_EDGE = 0, /**< Rising edge trigger */ + EXTI_TRIGGER_TRAILING_EDGE = 1, /**< Trailing edge trigger */ + EXTI_TRIGGER_BOTH_EDGE = 2, /**< Rising and trailing edge trigger */ +} exti_trigger_style_t; + +/** + * @brief EXTI filter clock select + */ +typedef enum +{ + EXTI_FILTER_CLOCK_10K = 0, /**< cks = 10KHz */ + EXTI_FILTER_CLOCK_32K = 1, /**< cks = 32KHz */ +} exti_filter_clock_t; + +/** + * @brief EXTI Init Structure definition + */ +typedef struct +{ + type_func_t filter; /**< Enable filter. */ + exti_filter_clock_t cks; /**< Filter clock select. */ + uint8_t filter_time; /**< Filter duration */ +} exti_init_t; +/** + * @} + */ + +/** + * @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define PIN_MASK 0xFFFF +#define UNLOCK_KEY 0x55AA + +#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0)) +#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \ + (GPIOx == GPIOB) || \ + (GPIOx == GPIOC) || \ + (GPIOx == GPIOD) || \ + (GPIOx == GPIOE) || \ + (GPIOx == GPIOF) || \ + (GPIOx == GPIOG) || \ + (GPIOx == GPIOH)) +#define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \ + ((x) == GPIO_MODE_INPUT) || \ + ((x) == GPIO_MODE_OUTPUT)) +#define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \ + ((x) == GPIO_OPEN_DRAIN) || \ + ((x) == GPIO_OPEN_SOURCE)) +#define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \ + ((x) == GPIO_PUSH_UP) || \ + ((x) == GPIO_PUSH_DOWN) || \ + ((x) == GPIO_PUSH_UP_DOWN)) +#define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_NORMAL) || \ + ((x) == GPIO_OUT_DRIVE_STRONG)) +#define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \ + ((x) == GPIO_FILTER_ENABLE)) +#define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \ + ((x) == GPIO_TYPE_CMOS)) +#define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \ + ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \ + ((x) == EXTI_TRIGGER_BOTH_EDGE)) +#define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \ + ((x) == EXTI_FILTER_CLOCK_32K)) +#define IS_GPIO_FUNC(x) ((x) <= 7) +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions + * @{ + */ + +/** @addtogroup GPIO_Public_Functions_Group1 + * @{ + */ +void gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init); +void gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin); +void gpio_func_default(GPIO_TypeDef *GPIOx); +void gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init); +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions_Group2 + * @{ + */ +uint8_t gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +void gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val); +void gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +void gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin); +void gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +uint16_t gpio_read_port(GPIO_TypeDef *GPIOx); +void gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val); +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions_Group3 + * @{ + */ +void gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status); +flag_status_t gpio_exti_get_flag_status(uint16_t pin); +void gpio_exti_clear_flag_status(uint16_t pin); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_GPIO_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h new file mode 100644 index 0000000000..f20384d7e1 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h @@ -0,0 +1,534 @@ +/** + ********************************************************************************* + * + * @file ald_i2c.h + * @brief Header file of I2C driver + * + * @version V1.0 + * @date 15 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_I2C_H__ +#define __ALD_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" +#include "ald_cmu.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Public_Types I2C Public Types + * @{ + */ +/** + * @brief I2C Error Code + */ +typedef enum +{ + I2C_ERROR_NONE = 0x0, /**< No error */ + I2C_ERROR_BERR = 0x1, /**< Berr error */ + I2C_ERROR_ARLO = 0x2, /**< Arlo error */ + I2C_ERROR_AF = 0x4, /**< Af error */ + I2C_ERROR_OVR = 0x8, /**< Ovr error */ + I2C_ERROR_DMA = 0x10, /**< Dma error */ + I2C_ERROR_TIMEOUT = 0x20, /**< Timeout error */ +} i2c_error_t; + +/** + * @brief I2C state structure definition + */ +typedef enum +{ + I2C_STATE_RESET = 0x0, /**< Peripheral is not yet Initialized */ + I2C_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ + I2C_STATE_BUSY = 0x2, /**< An internal process is ongoing */ + I2C_STATE_BUSY_TX = 0x3, /**< Data Transmission process is ongoing */ + I2C_STATE_BUSY_RX = 0x4, /**< Data Reception process is ongoing */ + I2C_STATE_TIMEOUT = 0x5, /**< timeout state */ + I2C_STATE_ERROR = 0x6, /**< Error */ +} i2c_state_t; + +/** + * @brief I2C Duty Cycle + */ +typedef enum +{ + I2C_DUTYCYCLE_2 = 0x0, /**< duty cycle is 2 */ + I2C_DUTYCYCLE_16_9 = 0x4000, /**< duty cycle is 16/9 */ +} i2c_duty_t; + +/** + * @brief I2C Addressing Mode + */ +typedef enum +{ + I2C_ADDR_7BIT = 0x1, /**< 7 bit address */ + I2C_ADDR_10BIT = 0x2, /**< 10 bit address */ +} i2c_addr_t; + +/** + * @brief I2C Dual Addressing Mode + */ +typedef enum +{ + I2C_DUALADDR_DISABLE = 0x0, /**< dual address is disable */ + I2C_DUALADDR_ENABLE = 0x1, /**< dual address is enable */ +} i2c_dual_addr_t; + +/** + * @brief I2C General Call Addressing mode + */ +typedef enum +{ + I2C_GENERALCALL_DISABLE = 0x0, /**< feneral call address is disable */ + I2C_GENERALCALL_ENABLE = 0x40, /**< feneral call address is enable */ +} i2c_general_addr_t; + +/** + * @brief I2C Nostretch Mode + */ +typedef enum +{ + I2C_NOSTRETCH_DISABLE = 0x0, /**< Nostretch disable */ + I2C_NOSTRETCH_ENABLE = 0x80, /**< Nostretch enable */ +} i2c_nostretch_t; + +/** + * @brief I2C Memory Address Size + */ +typedef enum +{ + I2C_MEMADD_SIZE_8BIT = 0x1, /**< 8 bit memory address size */ + I2C_MEMADD_SIZE_16BIT = 0x10 /**< 10 bit memory address size */ +} i2c_addr_size_t; + +/** + * @brief I2C Flag Definition + */ +typedef enum +{ + I2C_FLAG_SB = (1U << 0), + I2C_FLAG_ADDR = (1U << 1), + I2C_FLAG_BTF = (1U << 2), + I2C_FLAG_ADD10 = (1U << 3), + I2C_FLAG_STOPF = (1U << 4), + I2C_FLAG_RXNE = (1U << 6), + I2C_FLAG_TXE = (1U << 7), + I2C_FLAG_BERR = (1U << 8), + I2C_FLAG_ARLO = (1U << 9), + I2C_FLAG_AF = (1U << 10), + I2C_FLAG_OVR = (1U << 11), + I2C_FLAG_PECERR = (1U << 12), + I2C_FLAG_TIMEOUT = (1U << 14), + I2C_FLAG_SMBALERT = (1U << 15), + I2C_FLAG_MSL = (1U << 16), + I2C_FLAG_BUSY = (1U << 17), + I2C_FLAG_TRA = (1U << 18), + I2C_FLAG_GENCALL = (1U << 20), + I2C_FLAG_SMBDEFAULT = (1U << 21), + I2C_FLAG_SMBHOST = (1U << 22), + I2C_FLAG_DUALF = (1U << 23), +} i2c_flag_t; + +/** + * @brief I2C mode structure definition + */ +typedef enum +{ + I2C_MODE_NONE = 0x0, /**< No I2C communication on going */ + I2C_MODE_MASTER = 0x10, /**< I2C communication is in Master mode */ + I2C_MODE_SLAVE = 0x20, /**< I2C communication is in Slave mode */ + I2C_MODE_MEM = 0x40, /**< I2C communication is in Memory mode */ +} i2c_mode_t; + +/** + * @brief I2C Clock + */ +typedef enum +{ + I2C_STANDARD_MODE_MAX_CLK = 100000, /**< Standard mode clock */ + I2C_FAST_MODE_MAX_CLK = 400000, /**< Fast mode clock */ +} i2c_clock_t; + +/** + * @brief Interrupt Configuration Definition + */ +typedef enum +{ + I2C_IT_BUF = (1U << 10), /**< Buffer interrupt */ + I2C_IT_EVT = (1U << 9), /**< Event interrupt */ + I2C_IT_ERR = (1U << 8), /**< Error interrupt */ +} i2c_interrupt_t; + +/** + * @brief I2C CON1 Register + */ +typedef enum +{ + I2C_CON1_PEN = (1U << 0), /**< PEN BIT */ + I2C_CON1_PMOD = (1U << 1), /**< PMOD BIT */ + I2C_CON1_SMBMOD = (1U << 3), /**< SMBMOD BIT */ + I2C_CON1_ARPEN = (1U << 4), /**< ARPEN BIT */ + I2C_CON1_PECEN = (1U << 5), /**< PECEN BIT */ + I2C_CON1_GCEN = (1U << 6), /**< GCEN BIT */ + I2C_CON1_DISCS = (1U << 7), /**< DISCS BIT */ + I2C_CON1_START = (1U << 8), /**< START BIT */ + I2C_CON1_STOP = (1U << 9), /**< STOP BIT */ + I2C_CON1_ACKEN = (1U << 10), /**< ACKEN BIT */ + I2C_CON1_POSAP = (1U << 11), /**< POSAP BIT */ + I2C_CON1_TRPEC = (1U << 12), /**< TRPEC BIT */ + I2C_CON1_ALARM = (1U << 13), /**< ALARM BIT */ + I2C_CON1_SRST = (1U << 15), /**< SRST BIT */ +} i2c_con1_t; + +/** + * @brief I2C CON2 Register + */ +typedef enum +{ + I2C_CON2_CLKF = 0x3F, /**< CLKF BITS */ + I2C_CON2_CLKF_0 = (1U << 0), /**< CLKF_0 BIT */ + I2C_CON2_CLKF_1 = (1U << 1), /**< CLKF_1 BIT */ + I2C_CON2_CLKF_2 = (1U << 2), /**< CLKF_2 BIT */ + I2C_CON2_CLKF_3 = (1U << 3), /**< CLKF_3 BIT */ + I2C_CON2_CLKF_4 = (1U << 4), /**< CLKF_4 BIT */ + I2C_CON2_CLKF_5 = (1U << 5), /**< CLKF_5 BIT */ + I2C_CON2_ERRIE = (1U << 8), /**< ERRIE BIT */ + I2C_CON2_EVTIE = (1U << 9), /**< EVTIE BIT */ + I2C_CON2_BUFIE = (1U << 10), /**< BUFIE BIT */ + I2C_CON2_DMAEN = (1U << 11), /**< DMAEN BIT */ + I2C_CON2_LDMA = (1U << 12), /**< LDMA BIT */ +} i2c_con2_t; + +/** + * @brief I2C ADDR1 Register + */ +typedef enum +{ + I2C_ADDR1_ADDH0 = (1U << 0), /**< ADDH0 BIT */ + I2C_ADDR1_ADDH1 = (1U << 1), /**< ADDH1 BIT */ + I2C_ADDR1_ADDH2 = (1U << 2), /**< ADDH2 BIT */ + I2C_ADDR1_ADDH3 = (1U << 3), /**< ADDH3 BIT */ + I2C_ADDR1_ADDH4 = (1U << 4), /**< ADDH4 BIT */ + I2C_ADDR1_ADDH5 = (1U << 5), /**< ADDH5 BIT */ + I2C_ADDR1_ADDH6 = (1U << 6), /**< ADDH6 BIT */ + I2C_ADDR1_ADDH7 = (1U << 7), /**< ADDH7 BIT */ + I2C_ADDR1_ADDH8 = (1U << 8), /**< ADDH8 BIT */ + I2C_ADDR1_ADDH9 = (1U << 9), /**< ADDH9 BIT */ + I2C_ADDR1_ADDTYPE = (1U << 15), /**< ADDTYPE BIT */ +} i2c_addr1_t; + +/** + * @brief I2C ADDR2 Register + */ +typedef enum +{ + I2C_ADDR2_DUALEN = (1U << 0), /**< DUALEN BIT */ + I2C_ADDR2_ADD = (1U << 1), /**< ADD BIT */ +} i2c_addr2_t; + +/** + * @brief I2C STAT1 Register + */ +typedef enum +{ + I2C_STAT1_SB = (1U << 0), /**< SB BIT */ + I2C_STAT1_ADDR = (1U << 1), /**< ADDR BIT */ + I2C_STAT1_BTC = (1U << 2), /**< BTC BIT */ + I2C_STAT1_SENDADD10 = (1U << 3), /**< SENDADD10 BIT */ + I2C_STAT1_DETSTP = (1U << 4), /**< DETSTP BIT */ + I2C_STAT1_RXBNE = (1U << 6), /**< RXBNE BIT */ + I2C_STAT1_TXBE = (1U << 7), /**< TXBE BIT */ + I2C_STAT1_BUSERR = (1U << 8), /**< BUSERR BIT */ + I2C_STAT1_LARB = (1U << 9), /**< LARB BIT */ + I2C_STAT1_ACKERR = (1U << 10), /**< ACKERR BIT */ + I2C_STAT1_ROUERR = (1U << 11), /**< ROUERR BIT */ + I2C_STAT1_PECERR = (1U << 12), /**< PECERR BIT */ + I2C_STAT1_SMBTO = (1U << 14), /**< SMBTO BIT */ + I2C_STAT1_SMBALARM = (1U << 15), /**< SMBALARM BIT */ +} i2c_stat1_t; + +/** + * @brief I2C STAT2 Register + */ +typedef enum +{ + I2C_STAT2_MASTER = (1U << 0), /**< MASTER BIT */ + I2C_STAT2_BSYF = (1U << 1), /**< BSYF BIT */ + I2C_STAT2_TRF = (1U << 2), /**< TRF BIT */ + I2C_STAT2_RXGCF = (1U << 4), /**< RXGCF BIT */ + I2C_STAT2_SMBDEF = (1U << 5), /**< SMBDEF BIT */ + I2C_STAT2_SMBHH = (1U << 6), /**< SMBHH BIT */ + I2C_STAT2_DUALF = (1U << 7), /**< DMF BIT */ + I2C_STAT2_PECV = (1U << 8), /**< PECV BIT */ +} i2c_stat2_t; + +/** + * @brief I2C CKCFG Register + */ +typedef enum +{ + I2C_CKCFG_CLKSET = 0xFFF, /**< CLKSET BITS */ + I2C_CKCFG_DUTY = (1U << 14), /**< DUTY BIT */ + I2C_CKCFG_CLKMOD = (1U << 15), /**< CLKMOD BIT */ +} i2c_ckcfg_t; + +/** + * @brief I2C RT Register + */ +typedef enum +{ + I2C_RT_RISET = 0x3F, /**< RISET BITS */ +} i2c_trise_t; + +/** + * @brief I2C Configuration Structure definition + */ +typedef struct +{ + uint32_t clk_speed; /**< Specifies the clock frequency */ + i2c_duty_t duty; /**< Specifies the I2C fast mode duty cycle */ + uint32_t own_addr1; /**< Specifies the first device own address */ + i2c_addr_t addr_mode; /**< Specifies addressing mode */ + i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ + uint32_t own_addr2; /**< Specifies the second device own address */ + i2c_general_addr_t general_call; /**< Specifies if general call mode is selected */ + i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ +} i2c_init_t; + +/** + * @brief I2C handle Structure definition + */ +typedef struct i2c_handle_s +{ + I2C_TypeDef *perh; /**< I2C registers base address */ + i2c_init_t init; /**< I2C communication parameters */ + uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ + uint16_t xfer_size; /**< I2C transfer size */ + __IO uint16_t xfer_count; /**< I2C transfer counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ +#endif + lock_state_t lock; /**< I2C locking object */ + __IO i2c_state_t state; /**< I2C communication state */ + __IO i2c_mode_t mode; /**< I2C communication mode */ + __IO uint32_t error_code; /**< I2C Error code */ + + void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */ + void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */ + void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Tx completed callback */ + void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Rx completed callback */ + void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Tx to Memory completed callback */ + void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Rx from Memory completed callback */ + void (*error_callback)(struct i2c_handle_s *arg); /**< Error callback */ +} i2c_handle_t; + +/** + * @} + */ + +/** @defgroup I2C_Public_Macro I2C Public Macros + * @{ + */ +#define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET) +#define I2C_CLEAR_ADDRFLAG(x) \ +do { \ + __IO uint32_t tmpreg; \ + tmpreg = (x)->perh->STAT1; \ + tmpreg = (x)->perh->STAT2; \ + UNUSED(tmpreg); \ +} while (0) +#define __I2C_CLEAR_STOPFLAG(x) \ +do { \ + __IO uint32_t tmpreg; \ + tmpreg = (x)->perh->STAT1; \ + tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN); \ + UNUSED(tmpreg); \ +} while (0) +#define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) +#define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) +/** + * @} + */ + +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ +#define IS_I2C_TYPE(x) (((x) == I2C0) || \ + ((x) == I2C1)) +#define IS_I2C_ADDRESSING_MODE(x) (((x) == I2C_ADDR_7BIT) || \ + ((x) == I2C_ADDR_10BIT)) +#define IS_I2C_DUAL_ADDRESS(x) (((x) == I2C_DUALADDR_DISABLE) || \ + ((x) == I2C_DUALADDR_ENABLE)) +#define IS_I2C_GENERAL_CALL(x) (((x) == I2C_GENERALCALL_DISABLE) || \ + ((x) == I2C_GENERALCALL_ENABLE)) +#define IS_I2C_MEMADD_size(x) (((x) == I2C_MEMADD_SIZE_8BIT) || \ + ((x) == I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_NO_STRETCH(x) (((x) == I2C_NOSTRETCH_DISABLE) || \ + ((x) == I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_OWN_ADDRESS1(x) (((x) & (uint32_t)(0xFFFFFC00)) == 0) +#define IS_I2C_OWN_ADDRESS2(x) (((x) & (uint32_t)(0xFFFFFF01)) == 0) +#define IS_I2C_CLOCK_SPEED(x) (((x) > 0) && ((x) <= I2C_FAST_MODE_MAX_CLK)) +#define IS_I2C_DUTY_CYCLE(x) (((x) == I2C_DUTYCYCLE_2) || \ + ((x) == I2C_DUTYCYCLE_16_9)) +#define IS_I2C_IT_TYPE(x) (((x) == I2C_IT_BUF) || \ + ((x) == I2C_IT_EVT) || \ + ((x) == I2C_IT_ERR)) +#define IS_I2C_FLAG(x) (((x) == I2C_FLAG_SB) || \ + ((x) == I2C_FLAG_ADDR) || \ + ((x) == I2C_FLAG_BTF) || \ + ((x) == I2C_FLAG_ADD10) || \ + ((x) == I2C_FLAG_STOPF) || \ + ((x) == I2C_FLAG_RXNE) || \ + ((x) == I2C_FLAG_TXE) || \ + ((x) == I2C_FLAG_BERR) || \ + ((x) == I2C_FLAG_ARLO) || \ + ((x) == I2C_FLAG_AF) || \ + ((x) == I2C_FLAG_OVR) || \ + ((x) == I2C_FLAG_PECERR) || \ + ((x) == I2C_FLAG_TIMEOUT) || \ + ((x) == I2C_FLAG_SMBALERT) || \ + ((x) == I2C_FLAG_MSL) || \ + ((x) == I2C_FLAG_BUSY) || \ + ((x) == I2C_FLAG_TRA) || \ + ((x) == I2C_FLAG_GENCALL) || \ + ((x) == I2C_FLAG_SMBDEFAULT) || \ + ((x) == I2C_FLAG_SMBHOST) || \ + ((x) == I2C_FLAG_DUALF)) + +#define I2C_FREQ_RANGE(x) ((x) / 1000000) +#define I2C_RISE_TIME(x, u) (((u) <= I2C_STANDARD_MODE_MAX_CLK) ? ((x) + 1) :\ + ((((x) * 300) / 1000) + 1)) +#define I2C_SPEED_STANDARD(x, y) (((((x) / ((y) << 1)) & I2C_CKCFG_CLKSET) < 4) ? 4:\ + ((x) / ((y) << 1))) +#define I2C_SPEED_FAST(x, y, z) (((z) == I2C_DUTYCYCLE_2) ? ((x) / ((y) * 3)) :\ + (((x) / ((y) * 25)) | I2C_DUTYCYCLE_16_9)) +#define I2C_SPEED(x, y, z) (((y) <= 100000) ? (I2C_SPEED_STANDARD((x), (y))) :\ + ((I2C_SPEED_FAST((x), (y), (z)) & I2C_CKCFG_CLKSET) == 0) ? 1 : \ + ((I2C_SPEED_FAST((x), (y), (z))) | I2C_CKCFG_CLKMOD)) +#define I2C_MEM_ADD_MSB(x) ((uint8_t)((uint16_t)(((uint16_t)((x) &\ + (uint16_t)(0xFF00))) >> 8))) +#define I2C_MEM_ADD_LSB(x) ((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF)))) +#define I2C_7BIT_ADD_WRITE(x) ((uint8_t)((x) & (~I2C_ADDR1_ADDH0))) +#define I2C_7BIT_ADD_READ(x) ((uint8_t)((x) | I2C_ADDR1_ADDH0)) +#define I2C_10BIT_ADDRESS(x) ((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF)))) +#define I2C_10BIT_HEADER_WRITE(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ + (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) +#define I2C_10BIT_HEADER_READ(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ + (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions + * @{ + */ + +/** @addtogroup I2C_Public_Functions_Group1 + * @{ + */ +ald_status_t i2c_init(i2c_handle_t *hperh); +ald_status_t i2c_reset(i2c_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group2 + * @{ + */ +/** Blocking mode: Polling */ +ald_status_t i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout); + +/** Non-Blocking mode: Interrupt */ +ald_status_t i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); +ald_status_t i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); +ald_status_t i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); +ald_status_t i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); + +#ifdef ALD_DMA +/** Non-Blocking mode: DMA */ +ald_status_t i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel); +#endif +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group3 + * @{ + */ +i2c_state_t i2c_get_state(i2c_handle_t *hperh); +uint32_t i2c_get_error(i2c_handle_t *hperh); +flag_status_t i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag); +flag_status_t i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it); +void i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag); +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group4 + * @{ + */ +void i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state); +void i2c_ev_irq_handler(i2c_handle_t *hperh); +void i2c_er_irq_handler(i2c_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_I2C_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h new file mode 100644 index 0000000000..4109bed4b1 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h @@ -0,0 +1,80 @@ +/** + ********************************************************************************* + * + * @file ald_iap.h + * @brief Header file of IAP module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_IAP_H__ +#define __ALD_IAP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup IAP + * @{ + */ + +/** + * @defgroup IAP_Private_Macros IAP Private Macros + * @{ + */ +#define IAP_WSP_ADDR 0x10000000 +#define IAP_PE_ADDR 0x10000004 +#define IAP_WP_ADDR 0x10000008 +#define IAP_DWP_ADDR 0x1000000c +/** + * @} + */ + +/** @defgroup IAP_Private_Types IAP Private Types + * @{ + */ +typedef uint32_t (*IAP_PE)(uint32_t addr); +typedef uint32_t (*IAP_WP)(uint32_t addr, uint32_t data); +typedef uint32_t (*IAP_DWP)(uint32_t addr, uint32_t data_l, uint32_t data_h); +typedef uint32_t (*IAP_WSP)(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); +/** + * @} + */ + +/** @addtogroup IAP_Public_Functions + * @{ + */ +uint32_t iap_erase_page(uint32_t addr); +uint32_t iap_program_word(uint32_t addr, uint32_t data); +uint32_t iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h); +uint32_t iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_IAP_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h new file mode 100644 index 0000000000..3b7c12cf0f --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h @@ -0,0 +1,633 @@ +/** + ********************************************************************************* + * + * @file ald_pis.h + * @brief Header file of PIS driver. + * + * @version V1.0 + * @date 27 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_PIS_H__ +#define __ALD_PIS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup PIS + * @{ + */ + +/** @defgroup PIS_Public_Types PIS Public Types + * @{ + */ + +/** + * @brief Producer entry + */ +typedef enum +{ + PIS_NON = 0x0, /**< No async */ + PIS_GPIO_PIN0 = 0x10, /**< Pin0, level,support async */ + PIS_GPIO_PIN1 = 0x11, /**< Pin1, level,support async */ + PIS_GPIO_PIN2 = 0x12, /**< Pin2, level,support async */ + PIS_GPIO_PIN3 = 0x13, /**< Pin3, level,support async */ + PIS_GPIO_PIN4 = 0x14, /**< Pin4, level,support async */ + PIS_GPIO_PIN5 = 0x15, /**< Pin5, level,support async */ + PIS_GPIO_PIN6 = 0x16, /**< Pin6, level,support async */ + PIS_GPIO_PIN7 = 0x17, /**< Pin7, level,support async */ + PIS_GPIO_PIN8 = 0x18, /**< Pin8, level,support async */ + PIS_GPIO_PIN9 = 0x19, /**< Pin9, level,support async */ + PIS_GPIO_PIN10 = 0x1a, /**< Pin10, level,support async */ + PIS_GPIO_PIN11 = 0x1b, /**< Pin11, level,support async */ + PIS_GPIO_PIN12 = 0x1c, /**< Pin12, level,support async */ + PIS_GPIO_PIN13 = 0x1d, /**< Pin13, level,support async */ + PIS_GPIO_PIN14 = 0x1e, /**< Pin14, level,support async */ + PIS_GPIO_PIN15 = 0x1f, /**< Pin15, level,support async */ + PIS_ACMP_OUT0 = 0x30, /**< Acmp0 output, level,support async */ + PIS_ACMP_OUT1 = 0x31, /**< Acmp1 output, level,support async */ + PIS_DAC0_CH0 = 0x40, /**< Dac0 channel 0, pclk2 pulse,support async */ + PIS_DAC0_CH1 = 0x41, /**< Dac0 channel 1, pclk2 pulse,support async */ + PIS_ADC0_INJECT = 0x60, /**< Adc0 inject, pclk2 pulse,support async */ + PIS_ADC0_REGULAT = 0x61, /**< Adc0 regulat, pclk2 pulse,support async */ + PIS_ADC0_WINDOW = 0x62, /**< Adc0 window, no have */ + PIS_LVD = 0x70, /**< Lvd, level,support async */ + PIS_UART0_ASY_SEND = 0x80, /**< Uart0 asy send, pulse,support async */ + PIS_UART0_ASY_RECV = 0x81, /**< Uart0 asy recv, pulse,support async */ + PIS_UART0_IRDAOUT = 0x82, /**< Uart0 irdaout, level,support async */ + PIS_UART0_RTSOUT = 0x83, /**< Uart0 rtsout, level,support async */ + PIS_UART0_TXOUT = 0x84, /**< Uart0 txout, level,support async */ + PIS_UART0_SYN_SEND = 0x85, /**< Uart0 syn send, pulse,support async */ + PIS_UART0_SYN_RECV = 0x86, /**< Uart0 syn recv, pulse,support async */ + PIS_UART1_ASY_SEND = 0x90, /**< Uart1 asy send, pulse,support async */ + PIS_UART1_ASY_RECV = 0x91, /**< Uart1 asy recv, pulse,support async */ + PIS_UART1_IRDA = 0x92, /**< Uart1 irdaout, level,support async */ + PIS_UART1_RTS = 0x93, /**< Uart1 rtsout, level,support async */ + PIS_UART1_TXOUT = 0x94, /**< Uart1 txout, level,support async */ + PIS_UART1_SYN_SEND = 0x95, /**< Uart1 syn send, pulse,support async */ + PIS_UART1_SYN_RECV = 0x96, /**< Uart1 syn recv, pulse,support async */ + PIS_UART2_ASY_SEND = 0xa0, /**< Uart2 asy send, pulse,support async */ + PIS_UART2_ASY_RECV = 0xa1, /**< Uart2 asy recv, pulse,support async */ + PIS_UART2_IRDA = 0xa2, /**< Uart2 irdaout, level,support async */ + PIS_UART2_RTS = 0xa3, /**< Uart2 rtsout, level,support async */ + PIS_UART2_TXOUT = 0xa4, /**< Uart2 txout, level,support async */ + PIS_UART2_SYN_SEND = 0xa5, /**< Uart2 syn send, pulse,support async */ + PIS_UART2_SYN_RECV = 0xa6, /**< Uart2 syn recv, pulse,support async */ + PIS_UART3_ASY_SEND = 0xb1, /**< Uart3 asy send, pulse,support async */ + PIS_UART3_ASY_RECV = 0xb2, /**< Uart3 asy recv, pulse,support async */ + PIS_UART3_IRDA = 0xb3, /**< Uart3 irdaout, level,support async */ + PIS_UART3_RTS = 0xb4, /**< Uart3 rtsout, level,support async */ + PIS_UART3_TXOUT = 0xb5, /**< Uart3 txout, level,support async */ + PIS_UART3_SYN_SEND = 0xb6, /**< Uart3 syn send, pulse,support async */ + PIS_UART3_SYN_RECV = 0xb7, /**< Uart3 syn recv, pulse,support async */ + PIS_EUART0_RECV = 0xc0, /**< Euart0 recv, plck1 pulse */ + PIS_EUART0_SEND = 0xc1, /**< Euart0 send, plck1 pulse */ + PIS_EUART0_TXOUT = 0xc2, /**< Euart0 txout, plck1 level */ + PIS_EUART1_RECV = 0xd0, /**< Euart1 recv, plck1 pulse */ + PIS_EUART1_SEND = 0xd1, /**< Euart1 send, plck1 pulse */ + PIS_EUART1_TXOUT = 0xd2, /**< Euart1 txout, plck1 level */ + PIS_SPI0_RECV = 0xe0, /**< Spi0 recv, plck1 pulse */ + PIS_SPI0_SEND = 0xe1, /**< Spi0 send, plck1 pulse */ + PIS_SPI0_NE = 0xe2, /**< Spi0 ne, plck1 level */ + PIS_SPI1_RECV = 0xf0, /**< Spi1 recv, plck1 pulse */ + PIS_SPI1_SEND = 0xf1, /**< Spi1 send, plck1 pulse */ + PIS_SPI1_NE = 0xf2, /**< Spi1 ne, plck1 level */ + PIS_I2C0_RECV = 0x100, /**< I2c0 recv, plck1 level */ + PIS_I2C0_SEND = 0x101, /**< I2c0 send, plck1 level */ + PIS_I2C1_RECV = 0x110, /**< I2c1 recv, plck1 level */ + PIS_I2C1_SEND = 0x111, /**< I2c1 send, plck1 level */ + PIS_TIMER0_UPDATA = 0x120, /**< Timer0 updata, plck1 pulse */ + PIS_TIMER0_TRIG = 0x121, /**< Timer0 trig, plck1 pulse */ + PIS_TIMER0_INPUT = 0x122, /**< Timer0 input, plck1 pulse */ + PIS_TIMER0_OUTPUT = 0x123, /**< Timer0 output, plck1 pulse */ + PIS_TIMER1_UPDATA = 0x130, /**< Timer1 updata, plck1 pulse */ + PIS_TIMER1_TRIG = 0x131, /**< Timer1 trig, plck1 pulse */ + PIS_TIMER1_INPUT = 0x132, /**< Timer1 input, plck1 pulse */ + PIS_TIMER1_OUTPUT = 0x133, /**< Timer1 output, plck1 pulse */ + PIS_TIMER2_UPDATA = 0x140, /**< Timer2 updata, plck1 pulse */ + PIS_TIMER2_TRIG = 0x141, /**< Timer2 trig, plck1 pulse */ + PIS_TIMER2_INPUT = 0x142, /**< Timer2 input, plck1 pulse */ + PIS_TIMER2_OUTPUT = 0x143, /**< Timer2 output, plck1 pulse */ + PIS_TIMER3_UPDATA = 0x150, /**< Timer0 updata, plck1 pulse */ + PIS_TIMER3_TRIG = 0x151, /**< Timer0 trig, plck1 pulse */ + PIS_TIMER3_INPUT = 0x152, /**< Timer0 input, plck1 pulse */ + PIS_TIMER3_OUTPUT = 0x153, /**< Timer0 output, plck1 pulse */ + PIS_RTC_CLOCK = 0x160, /**< Rtc clock, pulse,support async */ + PIS_RTC_ALARM = 0x161, /**< Rtc alarm, pulse,support async */ + PIS_LPTIM0_SYN_UPDATA = 0x170, /**< Lptimer0 syn updata, pulse,support async */ + PIS_LPTIM0_ASY_UPDATA = 0x171, /**< Lptimer0 asy updata, pulse,support async */ + PIS_LPUART0_ASY_RECV = 0x180, /**< Lpuart0 asy recv, pulse,support async */ + PIS_LPUART0_ASY_SEND = 0x181, /**< Lpuart0 asy send, pulse,support async */ + PIS_LPUART0_SYN_RECV = 0x182, /**< Lpuart0 syn recv, pulse,support async */ + PIS_LPUART0_SYN_SEND = 0x183, /**< Lpuart0 syn recv, pulse,support async */ + PIS_DMA = 0x190, /**< Dma, pulse,support async */ + PIS_ADC1_INJECT = 0x1a0, /**< Adc1 inject, pclk2 pulse,support async */ + PIS_ADC1_REGULAT = 0x1a1, /**< Adc1 regulat, pclk2 pulse,support async */ + PIS_ADC1_WINDOW = 0x1a2, /**< Adc1 window, no have */ +} pis_src_t; + +/** + * @brief Consumer entry + */ +typedef enum +{ + PIS_CH0_TIMER0_BRKIN = 0x4000, /**< Timer0 brkin */ + PIS_CH0_SPI1_CLK = 0xF010, /**< Spi1 clk */ + PIS_CH0_LPTIM0_EXT0 = 0x0030, /**< Lptimer0 ext0 */ + PIS_CH0_ADC1_NORMAL = 0x0030, /**< Adc1 normal */ + PIS_CH1_TIMER0_CH1IN = 0x0001, /**< Timer0 ch1in */ + PIS_CH1_TIMER2_CH1IN = 0x0101, /**< Timer2 ch1in */ + PIS_CH1_TIMER3_CH1IN = 0x8101, /**< Timer3 ch1in */ + PIS_CH1_LPTIM0_EXT1 = 0x0031, /**< Lptime0 ext1 */ + PIS_CH1_UART0_RX_IRDA = 0x0011, /**< Uart0 rx irda */ + PIS_CH1_ADC1_INSERT = 0x0031, /**< Adc1 insert */ + PIS_CH2_TIMER0_CH2IN = 0x1002, /**< Timer0 ch2in */ + PIS_CH2_TIMER2_CH2IN = 0x1102, /**< Timer2 ch2in */ + PIS_CH2_TIMER3_CH2IN = 0x9102, /**< Timer3 ch2in */ + PIS_CH2_LPTIM0_EXT2 = 0x0032, /**< Lptime0 ext2 */ + PIS_CH2_UART1_RX_IRDA = 0x1012, /**< Uart1 rx irda */ + PIS_CH3_TIMER0_CH3IN = 0x2003, /**< Timer0 ch3in */ + PIS_CH3_LPTIM0_EXT3 = 0x0033, /**< Lptime0 ext3 */ + PIS_CH3_UART2_RX_IRDA = 0x2013, /**< Uart2 rx irda */ + PIS_CH4_TIMER0_CH4IN = 0x0004, /**< Timer0 ch4in */ + PIS_CH4_TIMER0_ITR0 = 0x0034, /**< Timer0 itr0 */ + PIS_CH4_TIMER2_ITR0 = 0x0034, /**< Timer2 itr0 */ + PIS_CH4_TIMER3_ITR0 = 0x0034, /**< Timer3 itr0 */ + PIS_CH4_LPTIM0_EXT4 = 0x4034, /**< Lptime0 ext4 */ + PIS_CH4_UART3_RX_IRDA = 0x3014, /**< Uart3 rx irda */ + PIS_CH5_SPI0_RX = 0xC015, /**< Spi0 rx */ + PIS_CH5_LPTIM0_EXT5 = 0x0035, /**< Lptime0 ext5 */ + PIS_CH5_EUART0_RX = 0x6015, /**< Euart0 rx */ + PIS_CH5_TIMER0_ITR1 = 0x0035, /**< Timer0 itr1 */ + PIS_CH5_TIMER2_ITR1 = 0x0035, /**< Timer2 itr1 */ + PIS_CH5_TIMER3_ITR1 = 0x0035, /**< Timer3 itr1 */ + PIS_CH6_SPI0_CLK = 0xD016, /**< Spi0 clk */ + PIS_CH6_ADC0_NORMAL = 0x0036, /**< Adc0 normal */ + PIS_CH6_LPTIM0_EXT6 = 0x0036, /**< Lptime0 ext6 */ + PIS_CH6_EUART1_RX = 0x7016, /**< Euart1 rx */ + PIS_CH6_TIMER0_ITR2 = 0x0036, /**< Timer0 itr2 */ + PIS_CH6_TIMER2_ITR2 = 0x0036, /**< Timer2 itr2 */ + PIS_CH6_TIMER3_ITR2 = 0x0036, /**< Timer3 itr2 */ + PIS_CH6_DAC_CH1 = 0x0036, /**< Dac channel 1 */ + PIS_CH7_SPI1_RX = 0xE017, /**< Spi1 rx */ + PIS_CH7_ADC0_INSERT = 0x0037, /**< Adc0 insert */ + PIS_CH7_LPTIM0_EXT7 = 0x0037, /**< Lptime0 ext7 */ + PIS_CH7_DMA = 0x0037, /**< Dma */ + PIS_CH7_TIMER0_ITR3 = 0x0037, /**< Timer0 itr3 */ + PIS_CH7_TIMER2_ITR3 = 0x0037, /**< Timer2 itr3 */ + PIS_CH7_TIMER3_ITR3 = 0x0037, /**< Timer3 itr3 */ + PIS_CH7_LPUART_RX = 0x8017, /**< Lpuart rx */ + PIS_CH7_DAC_CH0 = 0x0037, /**< Dac channel 0 */ +} pis_trig_t; + +/** + * @brief Clock select + */ +typedef enum +{ + PIS_CLK_PCLK1 = 0, /**< Pclock1 */ + PIS_CLK_PCLK2 = 1, /**< Pclock2 */ + PIS_CLK_SYS = 2, /**< Sys clock */ + PIS_CLK_LP = 3, /**< Low power clock */ +} pis_clock_t; + +/** + * @brief Level select + */ +typedef enum +{ + PIS_EDGE_NONE = 0, /**< None edge */ + PIS_EDGE_UP = 1, /**< Up edge */ + PIS_EDGE_DOWN = 2, /**< Down edge */ + PIS_EDGE_UP_DOWN = 3, /**< Up and down edge */ +} pis_edge_t; + +/** + * @brief Output style + */ +typedef enum +{ + PIS_OUT_LEVEL = 0, /**< Level */ + PIS_OUT_PULSE = 1, /**< Pulse */ +} pis_output_t; +/** + * @brief Sync select + */ +typedef enum +{ + PIS_SYN_DIRECT = 0, /**< Direct */ + PIS_SYN_ASY_PCLK1 = 1, /**< Asy pclk1 */ + PIS_SYN_ASY_PCLK2 = 2, /**< Asy pclk2 */ + PIS_SYN_ASY_PCLK = 3, /**< Asy pclk */ + PIS_SYN_PCLK2_PCLK1 = 4, /**< Pclk2 to pclk1 */ + PIS_SYN_PCLK1_PCLK2 = 5, /**< Pclk1 to pclk2 */ + PIS_SYN_PCLK12_SYS = 6, /**< Pclk1 or pclk2 to sysclk */ +} pis_syncsel_t; + +/** + * @brief Pis channel + */ +typedef enum +{ + PIS_CH_0 = 0, /**< Channel 0 */ + PIS_CH_1 = 1, /**< Channel 1 */ + PIS_CH_2 = 2, /**< Channel 2 */ + PIS_CH_3 = 3, /**< Channel 3 */ + PIS_CH_4 = 4, /**< Channel 4 */ + PIS_CH_5 = 5, /**< Channel 5 */ + PIS_CH_6 = 6, /**< Channel 6 */ + PIS_CH_7 = 7, /**< Channel 7 */ +} pis_ch_t; + +/** + * @brief Pis output channel + */ +typedef enum +{ + PIS_OUT_CH_0 = 0, /**< Channel 0 */ + PIS_OUT_CH_1 = 1, /**< Channel 1 */ + PIS_OUT_CH_2 = 2, /**< Channel 2 */ + PIS_OUT_CH_3 = 3, /**< Channel 3 */ +} pis_out_ch_t; + +/** + * @brief Indirect value,no care of it. + */ +typedef enum +{ + PIS_CON_0 = 0, /**< Con 0 */ + PIS_CON_1 = 1, /**< Con 1 */ + PIS_CON_NONE = 2, /**< None */ +} pis_con_t; + +/** + * @brief Indirect value,no care of it. + */ +typedef union +{ + struct + { + uint8_t ch : 4; /**< Channel */ + uint8_t con : 4; /**< Contorl */ + uint8_t shift : 8; /**< Shift */ + }; + uint16_t HalfWord; +} pis_divide_t; + +/** + * @brief PIS state structures definition + */ +typedef enum +{ + PIS_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + PIS_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + PIS_STATE_BUSY = 0x02, /**< An internal process is ongoing */ + PIS_STATE_TIMEOUT = 0x03, /**< Timeout state */ + PIS_STATE_ERROR = 0x04, /**< Error */ +} pis_state_t; + +/** + * @brief PIS modulate target + */ +typedef enum +{ + PIS_UART0_TX = 0, /**< Modulate uart0 tx */ + PIS_UART1_TX = 1, /**< Modulate uart1 tx */ + PIS_UART2_TX = 2, /**< Modulate uart2 tx */ + PIS_UART3_TX = 3, /**< Modulate uart3 tx */ + PIS_LPUART0_TX = 4, /**< Modulate lpuart0 tx */ +} pis_modu_targ_t; + +/** + * @brief PIS modulate level + */ +typedef enum +{ + PIS_LOW_LEVEL = 0, /**< Modulate low level */ + PIS_HIGH_LEVEL = 1, /**< Modulate high level */ +} pis_modu_level_t; + +/** + * @brief PIS modulate source + */ +typedef enum +{ + PIS_SRC_NONE = 0, /**< Stop modulate */ + PIS_SRC_TIMER0 = 1, /**< Modulate source is TIMER0 */ + PIS_SRC_TIMER1 = 2, /**< Modulate source is TIMER1 */ + PIS_SRC_TIMER2 = 3, /**< Modulate source is TIMER2 */ + PIS_SRC_TIMER3 = 4, /**< Modulate source is TIMER3 */ + PIS_SRC_TIMER6 = 5, /**< Modulate source is TIMER6 */ + PIS_SRC_TIMER7 = 6, /**< Modulate source is TIMER7 */ + PIS_SRC_LPTIM0 = 7, /**< Modulate source is LPTIM0 */ + PIS_SRC_BUZ = 8, /**< Modulate source is buz */ +} pis_modu_src_t; + +/** + * @brief PIS modulate channel + */ +typedef enum +{ + PIS_TIMER_CH1 = 0, /**< Src is TIMERx and choose channel 1 */ + PIS_TIMER_CH2 = 1, /**< Src is TIMERx and choose channel 2 */ + PIS_TIMER_CH3 = 2, /**< Src is TIMERx and choose channel 3 */ + PIS_TIMER_CH4 = 3, /**< Src is TIMERx and choose channel 4 */ +} pis_modu_channel_t; + +/** + * @brief PIS init structure definition + */ +typedef struct +{ + pis_src_t producer_src; /**< Producer entry */ + pis_clock_t producer_clk; /**< Producer module clock */ + pis_edge_t producer_edge; /**< Producer module pin output edge */ + pis_trig_t consumer_trig; /**< Consumer entry */ + pis_clock_t consumer_clk; /**< Consumer clock */ +} pis_init_t; + +/** + * @brief PIS modulate config structure definition + */ +typedef struct +{ + pis_modu_targ_t target; /**< Modulate target */ + pis_modu_level_t level; /**< Modulate level */ + pis_modu_src_t src; /**< Modulate src */ + pis_modu_channel_t channel; /**< Modulate channel */ +} pis_modulate_config_t; + +/** + * @brief PIS Handle Structure definition + */ +typedef struct pis_handle_s +{ + PIS_TypeDef *perh; /**< Register base address */ + pis_init_t init; /**< PIS required parameters */ + pis_ch_t consumer_ch; /**< Indirect value, no care of it */ + pis_con_t consumer_con; /**< Indirect value, no care of it */ + uint8_t consumer_pos; /**< Indirect value, no care of it */ + uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ + lock_state_t lock; /**< Locking object */ + pis_state_t state; /**< PIS operation state */ +} pis_handle_t; +/** + * @} + */ + + +/** @defgroup PIS_Private_Macros PIS Private Macros + * @{ + */ +#define IS_PIS(x) (((x) == PIS)) +#define IS_PIS_SRC(x) (((x) == PIS_NON) || \ + ((x) == PIS_GPIO_PIN0) || \ + ((x) == PIS_GPIO_PIN1) || \ + ((x) == PIS_GPIO_PIN2) || \ + ((x) == PIS_GPIO_PIN3) || \ + ((x) == PIS_GPIO_PIN4) || \ + ((x) == PIS_GPIO_PIN5) || \ + ((x) == PIS_GPIO_PIN6) || \ + ((x) == PIS_GPIO_PIN7) || \ + ((x) == PIS_GPIO_PIN8) || \ + ((x) == PIS_GPIO_PIN9) || \ + ((x) == PIS_GPIO_PIN10) || \ + ((x) == PIS_GPIO_PIN11) || \ + ((x) == PIS_GPIO_PIN12) || \ + ((x) == PIS_GPIO_PIN13) || \ + ((x) == PIS_GPIO_PIN14) || \ + ((x) == PIS_GPIO_PIN15) || \ + ((x) == PIS_ACMP_OUT0) || \ + ((x) == PIS_ACMP_OUT1) || \ + ((x) == PIS_DAC0_CH1) || \ + ((x) == PIS_ACMP_OUT1) || \ + ((x) == PIS_ADC0_INJECT) || \ + ((x) == PIS_ADC0_REGULAT) || \ + ((x) == PIS_ADC0_WINDOW) || \ + ((x) == PIS_LVD) || \ + ((x) == PIS_UART0_ASY_SEND) || \ + ((x) == PIS_UART0_ASY_RECV) || \ + ((x) == PIS_UART0_IRDAOUT) || \ + ((x) == PIS_UART0_RTSOUT) || \ + ((x) == PIS_UART0_TXOUT) || \ + ((x) == PIS_UART0_SYN_SEND) || \ + ((x) == PIS_UART0_SYN_RECV) || \ + ((x) == PIS_UART1_ASY_SEND) || \ + ((x) == PIS_UART1_ASY_RECV) || \ + ((x) == PIS_UART1_IRDA) || \ + ((x) == PIS_UART1_RTS) || \ + ((x) == PIS_UART1_TXOUT) || \ + ((x) == PIS_UART1_SYN_SEND) || \ + ((x) == PIS_UART1_SYN_RECV) || \ + ((x) == PIS_UART2_ASY_SEND) || \ + ((x) == PIS_UART2_ASY_RECV) || \ + ((x) == PIS_UART2_IRDA) || \ + ((x) == PIS_UART2_RTS) || \ + ((x) == PIS_UART2_TXOUT) || \ + ((x) == PIS_UART2_SYN_SEND) || \ + ((x) == PIS_UART2_SYN_RECV) || \ + ((x) == PIS_UART3_ASY_SEND) || \ + ((x) == PIS_UART3_ASY_RECV) || \ + ((x) == PIS_UART3_IRDA) || \ + ((x) == PIS_UART3_RTS) || \ + ((x) == PIS_UART3_TXOUT) || \ + ((x) == PIS_UART3_SYN_SEND) || \ + ((x) == PIS_UART3_SYN_RECV) || \ + ((x) == PIS_EUART0_RECV) || \ + ((x) == PIS_EUART0_SEND) || \ + ((x) == PIS_EUART0_TXOUT) || \ + ((x) == PIS_EUART1_RECV) || \ + ((x) == PIS_EUART1_SEND) || \ + ((x) == PIS_EUART1_TXOUT) || \ + ((x) == PIS_SPI0_RECV) || \ + ((x) == PIS_SPI0_SEND) || \ + ((x) == PIS_SPI0_NE) || \ + ((x) == PIS_SPI1_RECV) || \ + ((x) == PIS_SPI1_SEND) || \ + ((x) == PIS_SPI1_NE) || \ + ((x) == PIS_I2C0_RECV) || \ + ((x) == PIS_I2C0_SEND) || \ + ((x) == PIS_I2C1_RECV) || \ + ((x) == PIS_I2C1_SEND) || \ + ((x) == PIS_TIMER0_UPDATA) || \ + ((x) == PIS_TIMER0_TRIG) || \ + ((x) == PIS_TIMER0_INPUT) || \ + ((x) == PIS_TIMER0_OUTPUT) || \ + ((x) == PIS_TIMER1_UPDATA) || \ + ((x) == PIS_TIMER1_TRIG) || \ + ((x) == PIS_TIMER1_INPUT) || \ + ((x) == PIS_TIMER1_OUTPUT) || \ + ((x) == PIS_TIMER2_UPDATA) || \ + ((x) == PIS_TIMER2_TRIG) || \ + ((x) == PIS_TIMER2_INPUT) || \ + ((x) == PIS_TIMER2_OUTPUT) || \ + ((x) == PIS_TIMER3_UPDATA) || \ + ((x) == PIS_TIMER3_TRIG) || \ + ((x) == PIS_TIMER3_INPUT) || \ + ((x) == PIS_TIMER3_OUTPUT) || \ + ((x) == PIS_RTC_CLOCK) || \ + ((x) == PIS_RTC_ALARM) || \ + ((x) == PIS_LPTIM0_SYN_UPDATA) || \ + ((x) == PIS_LPTIM0_ASY_UPDATA) || \ + ((x) == PIS_LPUART0_ASY_RECV) || \ + ((x) == PIS_LPUART0_ASY_SEND) || \ + ((x) == PIS_LPUART0_SYN_RECV) || \ + ((x) == PIS_LPUART0_SYN_SEND) || \ + ((x) == PIS_DMA) || \ + ((x) == PIS_ADC1_INJECT) || \ + ((x) == PIS_ADC1_REGULAT) || \ + ((x) == PIS_ADC1_WINDOW)) +#define IS_PIS_TRIG(x) (((x) == PIS_CH0_TIMER0_BRKIN) || \ + ((x) == PIS_CH0_SPI1_CLK) || \ + ((x) == PIS_CH0_LPTIM0_EXT0) || \ + ((x) == PIS_CH0_ADC1_NORMAL) || \ + ((x) == PIS_CH1_TIMER0_CH1IN) || \ + ((x) == PIS_CH1_TIMER2_CH1IN) || \ + ((x) == PIS_CH1_TIMER3_CH1IN) || \ + ((x) == PIS_CH1_UART0_RX_IRDA) || \ + ((x) == PIS_CH1_LPTIM0_EXT1) || \ + ((x) == PIS_CH1_ADC1_INSERT) || \ + ((x) == PIS_CH2_TIMER0_CH2IN) || \ + ((x) == PIS_CH2_TIMER2_CH2IN) || \ + ((x) == PIS_CH2_TIMER3_CH2IN) || \ + ((x) == PIS_CH2_LPTIM0_EXT2) || \ + ((x) == PIS_CH2_UART1_RX_IRDA) || \ + ((x) == PIS_CH3_TIMER0_CH3IN) || \ + ((x) == PIS_CH3_LPTIM0_EXT3) || \ + ((x) == PIS_CH3_UART2_RX_IRDA) || \ + ((x) == PIS_CH4_TIMER0_CH4IN) || \ + ((x) == PIS_CH4_TIMER0_ITR0) || \ + ((x) == PIS_CH4_TIMER2_ITR0) || \ + ((x) == PIS_CH4_TIMER3_ITR0) || \ + ((x) == PIS_CH4_LPTIM0_EXT4) || \ + ((x) == PIS_CH4_UART3_RX_IRDA) || \ + ((x) == PIS_CH5_SPI0_RX) || \ + ((x) == PIS_CH5_LPTIM0_EXT5) || \ + ((x) == PIS_CH5_EUART0_RX) || \ + ((x) == PIS_CH5_TIMER0_ITR1) || \ + ((x) == PIS_CH5_TIMER2_ITR1) || \ + ((x) == PIS_CH5_TIMER3_ITR1) || \ + ((x) == PIS_CH6_SPI0_CLK) || \ + ((x) == PIS_CH6_ADC0_NORMAL) || \ + ((x) == PIS_CH6_LPTIM0_EXT6) || \ + ((x) == PIS_CH6_EUART1_RX) || \ + ((x) == PIS_CH6_TIMER0_ITR2) || \ + ((x) == PIS_CH6_TIMER2_ITR2) || \ + ((x) == PIS_CH6_TIMER3_ITR2) || \ + ((x) == PIS_CH6_DAC_CH1) || \ + ((x) == PIS_CH7_SPI1_RX) || \ + ((x) == PIS_CH7_ADC0_INSERT) || \ + ((x) == PIS_CH7_LPTIM0_EXT7) || \ + ((x) == PIS_CH7_DMA) || \ + ((x) == PIS_CH7_TIMER0_ITR3) || \ + ((x) == PIS_CH7_TIMER2_ITR3) || \ + ((x) == PIS_CH7_TIMER3_ITR3) || \ + ((x) == PIS_CH7_DAC_CH0) || \ + ((x) == PIS_CH7_LPUART_RX)) +#define IS_PIS_CLOCK(x) (((x) == PIS_CLK_PCLK1) || \ + ((x) == PIS_CLK_PCLK2) || \ + ((x) == PIS_CLK_SYS) || \ + ((x) == PIS_CLK_LP)) +#define IS_PIS_EDGE(x) (((x) == PIS_EDGE_NONE) || \ + ((x) == PIS_EDGE_UP) || \ + ((x) == PIS_EDGE_DOWN) || \ + ((x) == PIS_EDGE_UP_DOWN)) +#define IS_PIS_OUTPUT(x) (((x) == PIS_OUT_LEVEL) || \ + ((x) == PIS_OUT_PULSE)) +#define IS_PIS_OUPUT_CH(x) (((x) == PIS_OUT_CH_0) || \ + ((x) == PIS_OUT_CH_1) || \ + ((x) == PIS_OUT_CH_2) || \ + ((x) == PIS_OUT_CH_3)) +#define IS_PIS_MODU_TARGET(x) (((x) == PIS_UART0_TX) || \ + ((x) == PIS_UART1_TX) || \ + ((x) == PIS_UART2_TX) || \ + ((x) == PIS_UART3_TX) || \ + ((x) == PIS_LPUART0_TX)) +#define IS_PIS_MODU_LEVEL(x) (((x) == PIS_LOW_LEVEL) || \ + ((x) == PIS_HIGH_LEVEL)) +#define IS_PIS_MODU_SRC(x) (((x) == PIS_SRC_NONE) || \ + ((x) == PIS_SRC_TIMER0) || \ + ((x) == PIS_SRC_TIMER1) || \ + ((x) == PIS_SRC_TIMER2) || \ + ((x) == PIS_SRC_TIMER3) || \ + ((x) == PIS_SRC_TIMER6) || \ + ((x) == PIS_SRC_TIMER7) || \ + ((x) == PIS_SRC_LPTIM0) || \ + ((x) == PIS_SRC_BUZ)) +#define IS_PIS_MODU_CHANNEL(x) (((x) == PIS_TIMER_CH1) || \ + ((x) == PIS_TIMER_CH2) || \ + ((x) == PIS_TIMER_CH3) || \ + ((x) == PIS_TIMER_CH4)) +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions + * @{ + */ + +/** @addtogroup PIS_Public_Functions_Group1 + * @{ + */ +ald_status_t pis_create(pis_handle_t *hperh); +ald_status_t pis_destroy(pis_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group2 + * @{ + */ +ald_status_t pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch); +ald_status_t pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group3 + * @{ + */ +pis_state_t pis_get_state(pis_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group4 + * @{ + */ +ald_status_t pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_PIS_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h new file mode 100644 index 0000000000..c7e3327e59 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h @@ -0,0 +1,241 @@ +/** + ********************************************************************************* + * + * @file ald_pmu.h + * @brief Header file of PMU module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_PMU_H__ +#define __ALD_PMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_syscfg.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup PMU + * @{ + */ + +/** @defgroup PMU_Public_Macros PMU Public Macros + * @{ + */ +#define PMU_SRAM0_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \ + SYSCFG_LOCK(); \ +} while (0) +#define PMU_SRAM0_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\ + SYSCFG_LOCK(); \ +} while (0) +#define PMU_SRAM1_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \ + SYSCFG_LOCK(); \ +} while (0) +#define PMU_SRAM1_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\ + SYSCFG_LOCK(); \ +} while (0) +#define PMU_BXCAN_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define PMU_BXCAN_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) + +#define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS)) +/** + * @} + */ + + +/** @defgroup PMU_Public_Types PMU Public Types + * @{ + */ +/** + * @brief Standby wakeup port select + */ +typedef enum +{ + PMU_STANDBY_PORT_SEL_PA0 = 0x0, /**< PA0 */ + PMU_STANDBY_PORT_SEL_PA1 = 0x1, /**< PA1 */ + PMU_STANDBY_PORT_SEL_PA2 = 0x2, /**< PA2 */ + PMU_STANDBY_PORT_SEL_PA3 = 0x3, /**< PA3 */ + PMU_STANDBY_PORT_SEL_PA4 = 0x4, /**< PA4 */ + PMU_STANDBY_PORT_SEL_PA5 = 0x5, /**< PA5 */ + PMU_STANDBY_PORT_SEL_PA6 = 0x6, /**< PA6 */ + PMU_STANDBY_PORT_SEL_PA7 = 0x7, /**< PA7 */ + PMU_STANDBY_PORT_NONE = 0xF, /**< NONE */ +} pmu_standby_wakeup_sel_t; + +/** + * @brief Low power mode + */ +typedef enum +{ + PMU_LP_STOP1 = 0x0, /**< Stop1 */ + PMU_LP_STOP2 = 0x1, /**< Stop2 */ + PMU_LP_STANDBY = 0x2, /**< Standby */ +} pmu_lp_mode_t; + +typedef enum +{ + PMU_SR_WUF = (1U << 0), + PMU_SR_STANDBYF = (1U << 1), +} pmu_status_t; + +/** + * @brief LVD voltage select + */ +typedef enum +{ + PMU_LVD_VOL_SEL_2_0 = 0x0, /**< 2.0V ~ 2.05V */ + PMU_LVD_VOL_SEL_2_1 = 0x1, /**< 2.1V ~ 2.15V */ + PMU_LVD_VOL_SEL_2_2 = 0x2, /**< 2.2V ~ 2.25V */ + PMU_LVD_VOL_SEL_2_4 = 0x3, /**< 2.4V ~ 2.45V */ + PMU_LVD_VOL_SEL_2_6 = 0x4, /**< 2.6V ~ 2.65V */ + PMU_LVD_VOL_SEL_2_8 = 0x5, /**< 2.8V ~ 2.85V */ + PMU_LVD_VOL_SEL_3_0 = 0x6, /**< 3.0V ~ 3.05V */ + PMU_LVD_VOL_SEL_3_6 = 0x7, /**< 3.6V ~ 3.65V */ + PMU_LVD_VOL_SEL_4_0 = 0x8, /**< 4.0V ~ 4.05V */ + PMU_LVD_VOL_SEL_4_6 = 0x9, /**< 4.6V ~ 4.65V */ + PMU_LVD_VOL_SEL_2_3 = 0xA, /**< 2.3V ~ 2.35V */ + PMU_LVD_VOL_SEL_EXT = 0xF, /**< Select external input. It must be 1.2V */ +} pmu_lvd_voltage_sel_t; + +/** + * @brief LVD trigger mode + */ +typedef enum +{ + PMU_LVD_TRIGGER_RISING_EDGE = 0x0, /**< Rising edge */ + PMU_LVD_TRIGGER_FALLING_EDGE = 0x1, /**< Falling edge */ + PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2, /**< High level */ + PMU_LVD_TRIGGER_LOW_LEVEL = 0x3, /**< Low level */ + PMU_LVD_TRIGGER_RISING_FALLING = 0x4, /**< Rising and falling edge */ +} pmu_lvd_trigger_mode_t; + +/** + * @} + */ + +/** + * @defgroup PMU_Private_Macros PMU Private Macros + * @{ + */ +#define IS_PMU_STANDBY_PORT_SEL(x) (((x) == PMU_STANDBY_PORT_SEL_PA0) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA1) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA2) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA3) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA4) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA5) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA6) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA7) || \ + ((x) == PMU_STANDBY_PORT_NONE)) +#define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \ + ((x) == PMU_LP_STOP2) || \ + ((x) == PMU_LP_STANDBY)) +#define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || \ + ((x) == PMU_SR_STANDBYF)) +#define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_0) || \ + ((x) == PMU_LVD_VOL_SEL_2_1) || \ + ((x) == PMU_LVD_VOL_SEL_2_2) || \ + ((x) == PMU_LVD_VOL_SEL_2_4) || \ + ((x) == PMU_LVD_VOL_SEL_2_6) || \ + ((x) == PMU_LVD_VOL_SEL_2_8) || \ + ((x) == PMU_LVD_VOL_SEL_3_0) || \ + ((x) == PMU_LVD_VOL_SEL_3_6) || \ + ((x) == PMU_LVD_VOL_SEL_4_0) || \ + ((x) == PMU_LVD_VOL_SEL_4_6) || \ + ((x) == PMU_LVD_VOL_SEL_2_3) || \ + ((x) == PMU_LVD_VOL_SEL_EXT)) +#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \ + ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \ + ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \ + ((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \ + ((x) == PMU_LVD_TRIGGER_RISING_FALLING)) +/** + * @} + */ + +/** @addtogroup PMU_Public_Functions + * @{ + */ +/** @addtogroup PMU_Public_Functions_Group1 + * @{ + */ +/* Low power mode select */ +__STATIC_INLINE__ void __sleep() +{ + __WFI(); +} + +__STATIC_INLINE__ void __sleep_deep() +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); +} + +void pmu_stop1_enter(void); +void pmu_stop2_enter(void); +void pmu_standby_enter(pmu_standby_wakeup_sel_t port); +flag_status_t pmu_get_status(pmu_status_t sr); +void pmu_clear_status(pmu_status_t sr); +/** + * @} + */ +/** @addtogroup PMU_Public_Functions_Group2 + * @{ + */ +/* LVD configure */ +void pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state); +void lvd_irq_cbk(void); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_PMU_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h new file mode 100644 index 0000000000..22b8fd21a1 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h @@ -0,0 +1,265 @@ +/** + ********************************************************************************* + * + * @file ald_rmu.h + * @brief Header file of RMU module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_RMU_H__ +#define __ALD_RMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup RMU + * @{ + */ + +/** @defgroup RMU_Public_Types RMU Public Types + * @{ + */ +/** + * @brief RMU BOR fliter + */ +typedef enum +{ + RMU_BORFLT_1 = 0x1, /**< 1 cycle */ + RMU_BORFLT_2 = 0x2, /**< 2 cycles */ + RMU_BORFLT_3 = 0x3, /**< 3 cycles */ + RMU_BORFLT_4 = 0x4, /**< 4 cycles */ + RMU_BORFLT_5 = 0x5, /**< 5 cycles */ + RMU_BORFLT_6 = 0x6, /**< 6 cycles */ + RMU_BORFLT_7 = 0x7, /**< 7 cycles */ +} rmu_bor_filter_t; + +/** + * @brief RMU BOR voltage + */ +typedef enum +{ + RMU_VOL_1_7 = 0x0, /**< 1.7V */ + RMU_VOL_2_0 = 0x1, /**< 2.0V */ + RMU_VOL_2_1 = 0x2, /**< 2.1V */ + RMU_VOL_2_2 = 0x3, /**< 2.2V */ + RMU_VOL_2_3 = 0x4, /**< 2.3V */ + RMU_VOL_2_4 = 0x5, /**< 2.4V */ + RMU_VOL_2_5 = 0x6, /**< 2.5V */ + RMU_VOL_2_6 = 0x7, /**< 2.6V */ + RMU_VOL_2_8 = 0x8, /**< 2.8V */ + RMU_VOL_3_0 = 0x9, /**< 3.0V */ + RMU_VOL_3_1 = 0xA, /**< 3.1V */ + RMU_VOL_3_3 = 0xB, /**< 3.3V */ + RMU_VOL_3_6 = 0xC, /**< 3.6V */ + RMU_VOL_3_7 = 0xD, /**< 3.7V */ + RMU_VOL_4_0 = 0xE, /**< 4.0V */ + RMU_VOL_4_3 = 0xF, /**< 4.3V */ +} rmu_bor_vol_t; + +/** + * @brief RMU reset status + */ +typedef enum +{ + RMU_RST_POR = (1U << 0), /**< POR */ + RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ + RMU_RST_BOR = (1U << 2), /**< BOR */ + RMU_RST_NMRST = (1U << 3), /**< NMRST */ + RMU_RST_IWDT = (1U << 4), /**< IWDT */ + RMU_RST_WWDT = (1U << 5), /**< WWDT */ + RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ + RMU_RST_CHIP = (1U << 7), /**< CHIP */ + RMU_RST_MCU = (1U << 8), /**< MCU */ + RMU_RST_CPU = (1U << 9), /**< CPU */ + RMU_RST_CFG = (1U << 10), /**< CFG */ + RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ +} rmu_state_t; + +/** + * @brief RMU periperal select bit + */ +typedef enum +{ + RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ + RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ + RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */ + RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */ + RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */ + RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ + RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ + RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ + RMU_PERH_TIM0 = (1U << 0) | (1U << 28), /**< APB1: TIM0 */ + RMU_PERH_TIM1 = (1U << 1) | (1U << 28), /**< APB1: TIM1 */ + RMU_PERH_TIM2 = (1U << 2) | (1U << 28), /**< APB1: TIM2 */ + RMU_PERH_TIM3 = (1U << 3) | (1U << 28), /**< APB1: TIM3 */ + RMU_PERH_TIM4 = (1U << 4) | (1U << 28), /**< APB1: TIM4 */ + RMU_PERH_TIM5 = (1U << 5) | (1U << 28), /**< APB1: TIM5 */ + RMU_PERH_TIM6 = (1U << 6) | (1U << 28), /**< APB1: TIM6 */ + RMU_PERH_TIM7 = (1U << 7) | (1U << 28), /**< APB1: TIM7 */ + RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */ + RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */ + RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */ + RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */ + RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */ + RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */ + RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */ + RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */ + RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */ + RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */ + RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */ + RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */ + RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */ + RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */ + RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */ + RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */ + RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */ + RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */ + RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */ + RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */ + RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */ + RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */ + RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */ + RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */ + RMU_PERH_TEMP = (1U << 16) | (1U << 29), /**< APB2: TEMP */ + RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */ + RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */ +} rmu_peripheral_t; +/** + * @} + */ + +/** + * @defgroup RMU_Private_Macros RMU Private Macros + * @{ + */ +#define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \ + ((x) == RMU_BORFLT_2) || \ + ((x) == RMU_BORFLT_3) || \ + ((x) == RMU_BORFLT_4) || \ + ((x) == RMU_BORFLT_5) || \ + ((x) == RMU_BORFLT_6) || \ + ((x) == RMU_BORFLT_7)) +#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_7) || \ + ((x) == RMU_VOL_2_0) || \ + ((x) == RMU_VOL_2_1) || \ + ((x) == RMU_VOL_2_2) || \ + ((x) == RMU_VOL_2_3) || \ + ((x) == RMU_VOL_2_4) || \ + ((x) == RMU_VOL_2_5) || \ + ((x) == RMU_VOL_2_6) || \ + ((x) == RMU_VOL_2_8) || \ + ((x) == RMU_VOL_3_0) || \ + ((x) == RMU_VOL_3_1) || \ + ((x) == RMU_VOL_3_3) || \ + ((x) == RMU_VOL_3_6) || \ + ((x) == RMU_VOL_3_7) || \ + ((x) == RMU_VOL_4_0) || \ + ((x) == RMU_VOL_4_3)) +#define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \ + ((x) == RMU_RST_WAKEUP) || \ + ((x) == RMU_RST_BOR) || \ + ((x) == RMU_RST_NMRST) || \ + ((x) == RMU_RST_IWDT) || \ + ((x) == RMU_RST_WWDT) || \ + ((x) == RMU_RST_LOCKUP) || \ + ((x) == RMU_RST_CHIP) || \ + ((x) == RMU_RST_MCU) || \ + ((x) == RMU_RST_CPU) || \ + ((x) == RMU_RST_CFG) || \ + ((x) == RMU_RST_CFGERR)) +#define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \ + ((x) == RMU_RST_WAKEUP) || \ + ((x) == RMU_RST_BOR) || \ + ((x) == RMU_RST_NMRST) || \ + ((x) == RMU_RST_IWDT) || \ + ((x) == RMU_RST_WWDT) || \ + ((x) == RMU_RST_LOCKUP) || \ + ((x) == RMU_RST_CHIP) || \ + ((x) == RMU_RST_MCU) || \ + ((x) == RMU_RST_CPU) || \ + ((x) == RMU_RST_CFG)) +#define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \ + ((x) == RMU_PERH_CRC) || \ + ((x) == RMU_PERH_CALC) || \ + ((x) == RMU_PERH_CRYPT) || \ + ((x) == RMU_PERH_TRNG) || \ + ((x) == RMU_PERH_PIS) || \ + ((x) == RMU_PERH_CHIP) || \ + ((x) == RMU_PERH_CPU) || \ + ((x) == RMU_PERH_TIM0) || \ + ((x) == RMU_PERH_TIM1) || \ + ((x) == RMU_PERH_TIM2) || \ + ((x) == RMU_PERH_TIM3) || \ + ((x) == RMU_PERH_TIM4) || \ + ((x) == RMU_PERH_TIM5) || \ + ((x) == RMU_PERH_TIM6) || \ + ((x) == RMU_PERH_TIM7) || \ + ((x) == RMU_PERH_UART0) || \ + ((x) == RMU_PERH_UART1) || \ + ((x) == RMU_PERH_UART2) || \ + ((x) == RMU_PERH_UART3) || \ + ((x) == RMU_PERH_USART0) || \ + ((x) == RMU_PERH_USART1) || \ + ((x) == RMU_PERH_SPI0) || \ + ((x) == RMU_PERH_SPI1) || \ + ((x) == RMU_PERH_SPI2) || \ + ((x) == RMU_PERH_I2C0) || \ + ((x) == RMU_PERH_I2C1) || \ + ((x) == RMU_PERH_CAN0) || \ + ((x) == RMU_PERH_LPTIM0) || \ + ((x) == RMU_PERH_LPUART0) || \ + ((x) == RMU_PERH_ADC0) || \ + ((x) == RMU_PERH_ADC1) || \ + ((x) == RMU_PERH_ACMP0) || \ + ((x) == RMU_PERH_ACMP1) || \ + ((x) == RMU_PERH_OPAMP) || \ + ((x) == RMU_PERH_DAC0) || \ + ((x) == RMU_PERH_WWDT) || \ + ((x) == RMU_PERH_LCD) || \ + ((x) == RMU_PERH_IWDT) || \ + ((x) == RMU_PERH_RTC) || \ + ((x) == RMU_PERH_TEMP) || \ + ((x) == RMU_PERH_BKPC) || \ + ((x) == RMU_PERH_BKPRAM)) +/** + * @} + */ + +/** @addtogroup RMU_Public_Functions + * @{ + */ +void rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state); +flag_status_t rmu_get_reset_status(rmu_state_t state); +void rmu_clear_reset_status(rmu_state_t state); +void rmu_reset_periperal(rmu_peripheral_t perh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_RMU_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h new file mode 100644 index 0000000000..9d0bce383f --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h @@ -0,0 +1,699 @@ +/** + ****************************************************************************** + * @file ald_rtc.h + * @brief Header file of RTC Module driver. + * + * @version V1.0 + * @date 16 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************* + */ + +#ifndef __ALD_RTC_H__ +#define __ALD_RTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** @defgroup RTC_Public_Types RTC Public Types + * @{ + */ + +/** + * @brief Hours format + */ +typedef enum +{ + RTC_HOUR_FORMAT_24 = 0x0, /**< 24-hours format */ + RTC_HOUR_FORMAT_12 = 0x1, /**< 12-hours format */ +} rtc_hour_format_t; + +/** + * @brief Output mode + */ +typedef enum +{ + RTC_OUTPUT_DISABLE = 0x0, /**< Disable output */ + RTC_OUTPUT_ALARM_A = 0x1, /**< Output alarm_a signal */ + RTC_OUTPUT_ALARM_B = 0x2, /**< Output alarm_b signal */ + RTC_OUTPUT_WAKEUP = 0x3, /**< Output wakeup signal */ +} rtc_output_select_t; + +/** + * @brief Output polarity + */ +typedef enum +{ + RTC_OUTPUT_POLARITY_HIGH = 0x0, /**< Polarity is high */ + RTC_OUTPUT_POLARITY_LOW = 0x0, /**< Polarity is low */ +} rtc_output_polarity_t; + +/** + * @brief Initialization structure + */ +typedef struct +{ + rtc_hour_format_t hour_format; /**< Hours format */ + uint32_t asynch_pre_div; /**< Asynchronous predivider value */ + uint32_t synch_pre_div; /**< Synchronous predivider value */ + rtc_output_select_t output; /**< Output signal type */ + rtc_output_polarity_t output_polarity; /**< Output polarity */ +} rtc_init_t; + +/** + * @brief Source select + */ +typedef enum +{ + RTC_SOURCE_LOSC = 0x0, /**< LOSC */ + RTC_SOURCE_LRC = 0x1, /**< LRC */ + RTC_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ + RTC_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ +} rtc_source_sel_t; + +/** + * @brief Time structure + */ +typedef struct +{ + uint8_t hour; /**< Hours */ + uint8_t minute; /**< Minutes */ + uint8_t second; /**< Seconds */ + uint16_t sub_sec; /**< Sub-seconds */ +} rtc_time_t; + +/** + * @brief Date structure + */ +typedef struct +{ + uint8_t week; /**< Weeks */ + uint8_t day; /**< days */ + uint8_t month; /**< months */ + uint8_t year; /**< years */ +} rtc_date_t; + +/** + * @brief Data format + */ +typedef enum +{ + RTC_FORMAT_DEC = 0, + RTC_FORMAT_BCD = 1, +} rtc_format_t; + +/** + * @brief Index of alarm + */ +typedef enum +{ + RTC_ALARM_A = 0x0, /**< Alarm-A */ + RTC_ALARM_B = 0x1, /**< Alarm-B */ +} rtc_alarm_idx_t; + +/** + * @brief Alarm mask + */ +typedef enum +{ + RTC_ALARM_MASK_NONE = 0x0, /**< Mask is disable */ + RTC_ALARM_MASK_WEEK_DAY = (1U << 30), /**< Mask week or day */ + RTC_ALARM_MASK_HOUR = (1U << 23), /**< Mask hour */ + RTC_ALARM_MASK_MINUTE = (1U << 15), /**< Mask minute */ + RTC_ALARM_MASK_SECOND = (1U << 7), /**< Mask second */ + RTC_ALARM_MASK_ALL = 0x40808080, /**< Mask all */ +} rtc_alarm_mask_t; + +/** + * @brief Alarm sub-second mask + */ +typedef enum +{ + RTC_ALARM_SS_MASK_NONE = 0xF, /**< Mask is disable */ + RTC_ALARM_SS_MASK_14_1 = 0x1, /**< Mask bit(1-14) */ + RTC_ALARM_SS_MASK_14_2 = 0x2, /**< Mask bit(2-14) */ + RTC_ALARM_SS_MASK_14_3 = 0x3, /**< Mask bit(3-14) */ + RTC_ALARM_SS_MASK_14_4 = 0x4, /**< Mask bit(4-14) */ + RTC_ALARM_SS_MASK_14_5 = 0x5, /**< Mask bit(5-14) */ + RTC_ALARM_SS_MASK_14_6 = 0x6, /**< Mask bit(6-14) */ + RTC_ALARM_SS_MASK_14_7 = 0x7, /**< Mask bit(7-14) */ + RTC_ALARM_SS_MASK_14_8 = 0x8, /**< Mask bit(8-14) */ + RTC_ALARM_SS_MASK_14_9 = 0x9, /**< Mask bit(9-14) */ + RTC_ALARM_SS_MASK_14_10 = 0xA, /**< Mask bit(10-14) */ + RTC_ALARM_SS_MASK_14_11 = 0xB, /**< Mask bit(11-14) */ + RTC_ALARM_SS_MASK_14_12 = 0xC, /**< Mask bit(12-14) */ + RTC_ALARM_SS_MASK_14_13 = 0xD, /**< Mask bit(13-14) */ + RTC_ALARM_SS_MASK_14 = 0xE, /**< Mask bit14 */ + RTC_ALARM_SS_MASK_ALL = 0x0, /**< Mask bit(0-14) */ +} rtc_sub_second_mask_t; + +/** + * @brief Alarm select week or day */ +typedef enum +{ + RTC_SELECT_DAY = 0x0, /**< Alarm select day */ + RTC_SELECT_WEEK = 0x1, /**< Alarm select week */ +} rtc_week_day_sel_t; + +/** + * @brief Alarm structure + */ +typedef struct +{ + rtc_alarm_idx_t idx; /**< Index of alarm */ + rtc_time_t time; /**< Time structure */ + uint32_t mask; /**< Alarm mask */ + rtc_sub_second_mask_t ss_mask; /**< Alarm sub-second mask */ + rtc_week_day_sel_t sel; /**< Select week or day */ + + union + { + uint8_t week; /**< Alarm select week */ + uint8_t day; /**< Alarm select day */ + }; +} rtc_alarm_t; + +/** + * @brief Time stamp signel select + */ +typedef enum +{ + RTC_TS_SIGNAL_SEL_TAMPER0 = 0, /**< Select tamper0 */ + RTC_TS_SIGNAL_SEL_TAMPER1 = 1, /**< Select tamper1 */ +} rtc_ts_signal_sel_t; + +/** + * @brief Time stamp trigger style + */ +typedef enum +{ + RTC_TS_RISING_EDGE = 0, /**< Rising edge */ + RTC_TS_FALLING_EDGE = 1, /**< Falling edge */ +} rtc_ts_trigger_style_t; + +/** + * @brief Index of tamper + */ +typedef enum +{ + RTC_TAMPER_0 = 0, /**< Tamper0 */ + RTC_TAMPER_1 = 1, /**< Tamper1 */ +} rtc_tamper_idx_t; + +/** + * @brief Tamper trigger type + */ +typedef enum +{ + RTC_TAMPER_TRIGGER_LOW = 0, /**< High trigger */ + RTC_TAMPER_TRIGGER_HIGH = 1, /**< Low trigger */ +} rtc_tamper_trigger_t; + +/** + * @brief Tamper sampling frequency + */ +typedef enum +{ + RTC_TAMPER_SAMPLING_FREQ_32768 = 0, /**< RTCCLK / 32768 */ + RTC_TAMPER_SAMPLING_FREQ_16384 = 1, /**< RTCCLK / 16384 */ + RTC_TAMPER_SAMPLING_FREQ_8192 = 2, /**< RTCCLK / 8192 */ + RTC_TAMPER_SAMPLING_FREQ_4096 = 3, /**< RTCCLK / 4096 */ + RTC_TAMPER_SAMPLING_FREQ_2048 = 4, /**< RTCCLK / 2048 */ + RTC_TAMPER_SAMPLING_FREQ_1024 = 5, /**< RTCCLK / 1024 */ + RTC_TAMPER_SAMPLING_FREQ_512 = 6, /**< RTCCLK / 512 */ + RTC_TAMPER_SAMPLING_FREQ_256 = 7, /**< RTCCLK / 256 */ +} rtc_tamper_sampling_freq_t; + +/** + * @brief Tamper filter time + */ +typedef enum +{ + RTC_TAMPER_DURATION_1 = 0, /**< Duration 1 sampling */ + RTC_TAMPER_DURATION_2 = 1, /**< Duration 2 sampling */ + RTC_TAMPER_DURATION_4 = 2, /**< Duration 4 sampling */ + RTC_TAMPER_DURATION_8 = 3, /**< Duration 8 sampling */ +} rtc_tamper_duration_t; + +/** + * @brief Tamper structure + */ +typedef struct +{ + rtc_tamper_idx_t idx; /**< Index of tamper */ + rtc_tamper_trigger_t trig; /**< Trigger type */ + rtc_tamper_sampling_freq_t freq; /**< Sampling frequency */ + rtc_tamper_duration_t dur; /**< Filter time */ + type_func_t ts; /**< Enable/Disable trigger time stamp event */ +} rtc_tamper_t; + +/** + * @brief Wake-up clock + */ +typedef enum +{ + RTC_WAKEUP_CLOCK_DIV_16 = 0, /**< RTCCLK / 16 */ + RTC_WAKEUP_CLOCK_DIV_8 = 1, /**< RTCCLK / 8 */ + RTC_WAKEUP_CLOCK_DIV_4 = 2, /**< RTCCLK / 4 */ + RTC_WAKEUP_CLOCK_DIV_2 = 3, /**< RTCCLK / 2 */ + RTC_WAKEUP_CLOCK_1HZ = 4, /**< 1Hz */ + RTC_WAKEUP_CLOCK_1HZ_PULS = 6, /**< 1Hz and WUT + 65536 */ +} rtc_wakeup_clock_t; + +/** + * @brief RTC clock output type + */ +typedef enum +{ + RTC_CLOCK_OUTPUT_32768 = 0, /**< 32768Hz */ + RTC_CLOCK_OUTPUT_1024 = 1, /**< 1024Hz */ + RTC_CLOCK_OUTPUT_32 = 2, /**< 32Hz */ + RTC_CLOCK_OUTPUT_1 = 3, /**< 1Hz */ + RTC_CLOCK_OUTPUT_CAL_1 = 4, /**< 1Hz after calibration */ + RTC_CLOCK_OUTPUT_EXA_1 = 5, /**< Exact 1Hz */ +} rtc_clock_output_t; + +/** + * @ Calibration frequency + */ +typedef enum +{ + RTC_CALI_FREQ_10_SEC = 0, /**< Calibrate every 10 seconds */ + RTC_CALI_FREQ_20_SEC = 1, /**< Calibrate every 20 seconds */ + RTC_CALI_FREQ_1_MIN = 2, /**< Calibrate every 1 minute */ + RTC_CALI_FREQ_2_MIN = 3, /**< Calibrate every 2 minutes */ + RTC_CALI_FREQ_5_MIN = 4, /**< Calibrate every 5 minutes */ + RTC_CALI_FREQ_10_MIN = 5, /**< Calibrate every 10 minutes */ + RTC_CALI_FREQ_20_MIN = 6, /**< Calibrate every 20 minutes */ + RTC_CALI_FREQ_1_SEC = 7, /**< Calibrate every 1 second */ +} rtc_cali_freq_t; + +/** + * @brief Temperature compensate type + */ +typedef enum +{ + RTC_CALI_TC_NONE = 0, /**< Temperature compensate disable */ + RTC_CALI_TC_AUTO_BY_HW = 1, /**< Temperature compensate by hardware */ + RTC_CALI_TC_AUTO_BY_SF = 2, /**< Temperature compensate by software */ + RTC_CALI_TC_AUTO_BY_HW_SF = 3, /**< Temperature compensate by hardware, trigger by software */ +} rtc_cali_tc_t; + +/** + * @ Calculate frequency + */ +typedef enum +{ + RTC_CALI_CALC_FREQ_10_SEC = 0, /**< Calculate every 10 seconds */ + RTC_CALI_CALC_FREQ_20_SEC = 1, /**< Calculate every 20 seconds */ + RTC_CALI_CALC_FREQ_1_MIN = 2, /**< Calculate every 1 minute */ + RTC_CALI_CALC_FREQ_2_MIN = 3, /**< Calculate every 2 minutes */ + RTC_CALI_CALC_FREQ_5_MIN = 4, /**< Calculate every 5 minutes */ + RTC_CALI_CALC_FREQ_10_MIN = 5, /**< Calculate every 10 minutes */ + RTC_CALI_CALC_FREQ_20_MIN = 6, /**< Calculate every 20 minutes */ + RTC_CALI_CALC_FREQ_1_HOUR = 7, /**< Calculate every 1 hour */ +} rtc_cali_calc_freq_t; + +/** + * @brief Calibration algorithm + */ +typedef enum +{ + RTC_CALI_CALC_4 = 0, /**< 4-polynomial */ + RTC_CALI_CALC_2 = 1, /**< 2-parabola */ +} rtc_cali_calc_t; + +/** + * @brief Calibration structure + */ +typedef struct +{ + rtc_cali_freq_t cali_freq; /**< calibrate frequency */ + rtc_cali_tc_t tc; /**< Temperature compensate type */ + rtc_cali_calc_freq_t calc_freq; /**< Calculate frequency */ + rtc_cali_calc_t calc; /**< algorithm */ + type_func_t acc; /**< Enable/Disable decimal accumulate */ +} rtc_cali_t; + +/** + * @brief Interrupt type + */ +typedef enum +{ + RTC_IT_SEC = (1U << 0), /**< Second */ + RTC_IT_MIN = (1U << 1), /**< Minute */ + RTC_IT_HR = (1U << 2), /**< Hour */ + RTC_IT_DAY = (1U << 3), /**< Day */ + RTC_IT_MON = (1U << 4), /**< Month */ + RTC_IT_YR = (1U << 5), /**< Year */ + RTC_IT_ALMA = (1U << 8), /**< Alarm-A */ + RTC_IT_ALMB = (1U << 9), /**< Alarm-B */ + RTC_IT_TS = (1U << 10), /**< Time stamp */ + RTC_IT_TSOV = (1U << 11), /**< Time stamp overflow */ + RTC_IT_TP0 = (1U << 12), /**< Tamper-0 */ + RTC_IT_TP1 = (1U << 13), /**< Tamper-1 */ + RTC_IT_RSC = (1U << 16), /**< Synchronous complete */ + RTC_IT_SFC = (1U << 17), /**< Shift complete */ + RTC_IT_WU = (1U << 18), /**< Wake-up */ + RTC_IT_TCC = (1U << 24), /**< Temperature compensate complete */ + RTC_IT_TCE = (1U << 25), /**< Temperature compensate error */ +} rtc_it_t; + +/** + * @brief Interrupt flag + */ +typedef enum +{ + RTC_IF_SEC = (1U << 0), /**< Second */ + RTC_IF_MIN = (1U << 1), /**< Minute */ + RTC_IF_HR = (1U << 2), /**< Hour */ + RTC_IF_DAY = (1U << 3), /**< Day */ + RTC_IF_MON = (1U << 4), /**< Month */ + RTC_IF_YR = (1U << 5), /**< Year */ + RTC_IF_ALMA = (1U << 8), /**< Alarm-A */ + RTC_IF_ALMB = (1U << 9), /**< Alarm-B */ + RTC_IF_TS = (1U << 10), /**< Time stamp */ + RTC_IF_TSOV = (1U << 11), /**< Time stamp overflow */ + RTC_IF_TP0 = (1U << 12), /**< Tamper-0 */ + RTC_IF_TP1 = (1U << 13), /**< Tamper-1 */ + RTC_IF_RSC = (1U << 16), /**< Synchronous complete */ + RTC_IF_SFC = (1U << 17), /**< Shift complete */ + RTC_IF_WU = (1U << 18), /**< Wake-up */ + RTC_IF_TCC = (1U << 24), /**< Temperature compensate complete */ + RTC_IF_TCE = (1U << 25), /**< Temperature compensate error */ +} rtc_flag_t; +/** + * @} + */ + +/** @defgroup RTC_Public_Macro RTC Public Macros + * @{ + */ +#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55)) +#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0)) +#define RTC_BY_PASS_ENABLE() \ +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ + RTC_LOCK(); \ +} while (0) +#define RTC_BY_PASS_DISABLE() \ +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ + RTC_LOCK(); \ +} while (0) +#define RTC_SUMMER_TIME_ENABLE() \ +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ + RTC_LOCK(); \ +} while (0) +#define RTC_SUMMER_TIME_DISABLE() \ +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ + RTC_LOCK(); \ +} while (0) +#define RTC_WINTER_TIME_ENABLE() \ +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ + RTC_LOCK(); \ +} while (0) +#define RTC_WINTER_TIME_DISABLE() \ +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ + RTC_LOCK(); \ +} while (0) +/** + * @} + */ + +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ +#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AA)) +#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0)) +#define ALARM_MASK_ALL 0x40808080 +#define RTC_TIMEOUT_VALUE 100 + +#define IS_SHIFT_SUB_SS(x) ((x) < (1U << 15)) +#define IS_RTC_HOUR_FORMAT(x) (((x) == RTC_HOUR_FORMAT_24) || \ + ((x) == RTC_HOUR_FORMAT_12)) +#define IS_RTC_OUTPUT_SEL(x) (((x) == RTC_OUTPUT_DISABLE) || \ + ((x) == RTC_OUTPUT_ALARM_A) || \ + ((x) == RTC_OUTPUT_ALARM_B) || \ + ((x) == RTC_OUTPUT_WAKEUP)) +#define IS_RTC_OUTPUT_POLARITY(x) (((x) == RTC_OUTPUT_POLARITY_HIGH) || \ + ((x) == RTC_OUTPUT_POLARITY_LOW)) +#define IS_RTC_SOURCE_SEL(x) (((x) == RTC_SOURCE_LOSC) || \ + ((x) == RTC_SOURCE_LRC) || \ + ((x) == RTC_SOURCE_HRC_DIV_1M ) || \ + ((x) == RTC_SOURCE_HOSC_DIV_1M)) +#define IS_RTC_ALARM(x) (((x) == RTC_ALARM_A) || \ + ((x) == RTC_ALARM_B)) +#define IS_RTC_ALARM_SEL(x) (((x) == RTC_SELECT_DAY) || \ + ((x) == RTC_SELECT_WEEK)) +#define IS_RTC_ALARM_MASK(x) (((x) == RTC_ALARM_MASK_NONE) || \ + ((x) == RTC_ALARM_MASK_WEEK_DAY) || \ + ((x) == RTC_ALARM_MASK_HOUR) || \ + ((x) == RTC_ALARM_MASK_MINUTE) || \ + ((x) == RTC_ALARM_MASK_SECOND) || \ + ((x) == RTC_ALARM_MASK_ALL)) +#define IS_RTC_ALARM_SS_MASK(x) (((x) == RTC_ALARM_SS_MASK_NONE) || \ + ((x) == RTC_ALARM_SS_MASK_14_1) || \ + ((x) == RTC_ALARM_SS_MASK_14_2) || \ + ((x) == RTC_ALARM_SS_MASK_14_3) || \ + ((x) == RTC_ALARM_SS_MASK_14_4) || \ + ((x) == RTC_ALARM_SS_MASK_14_5) || \ + ((x) == RTC_ALARM_SS_MASK_14_6) || \ + ((x) == RTC_ALARM_SS_MASK_14_7) || \ + ((x) == RTC_ALARM_SS_MASK_14_8) || \ + ((x) == RTC_ALARM_SS_MASK_14_9) || \ + ((x) == RTC_ALARM_SS_MASK_14_10) || \ + ((x) == RTC_ALARM_SS_MASK_14_11) || \ + ((x) == RTC_ALARM_SS_MASK_14_12) || \ + ((x) == RTC_ALARM_SS_MASK_14_13) || \ + ((x) == RTC_ALARM_SS_MASK_14) || \ + ((x) == RTC_ALARM_SS_MASK_ALL)) +#define IS_RTC_TS_SIGNAL(x) (((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \ + ((x) == RTC_TS_SIGNAL_SEL_TAMPER1)) +#define IS_RTC_TS_STYLE(x) (((x) == RTC_TS_RISING_EDGE) || \ + ((x) == RTC_TS_FALLING_EDGE)) +#define IS_RTC_FORMAT(x) (((x) == RTC_FORMAT_DEC) || \ + ((x) == RTC_FORMAT_BCD)) +#define IS_RTC_TAMPER(x) (((x) == RTC_TAMPER_0) || \ + ((x) == RTC_TAMPER_1)) +#define IS_RTC_TAMPER_TRIGGER(x) (((x) == RTC_TAMPER_TRIGGER_LOW) || \ + ((x) == RTC_TAMPER_TRIGGER_HIGH)) +#define IS_RTC_TAMPER_SAMPLING_FREQ(x) (((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_8192) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_4096) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_2048) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_1024) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_512) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_256)) +#define IS_RTC_TAMPER_DURATION(x) (((x) == RTC_TAMPER_DURATION_1) || \ + ((x) == RTC_TAMPER_DURATION_2) || \ + ((x) == RTC_TAMPER_DURATION_4) || \ + ((x) == RTC_TAMPER_DURATION_8)) +#define IS_RTC_WAKEUP_CLOCK(x) (((x) == RTC_WAKEUP_CLOCK_DIV_16) || \ + ((x) == RTC_WAKEUP_CLOCK_DIV_8) || \ + ((x) == RTC_WAKEUP_CLOCK_DIV_4) || \ + ((x) == RTC_WAKEUP_CLOCK_DIV_2) || \ + ((x) == RTC_WAKEUP_CLOCK_1HZ) || \ + ((x) == RTC_WAKEUP_CLOCK_1HZ_PULS)) +#define IS_RTC_CLOCK_OUTPUT(x) (((x) == RTC_CLOCK_OUTPUT_32768) || \ + ((x) == RTC_CLOCK_OUTPUT_1024) || \ + ((x) == RTC_CLOCK_OUTPUT_32) || \ + ((x) == RTC_CLOCK_OUTPUT_1) || \ + ((x) == RTC_CLOCK_OUTPUT_CAL_1) || \ + ((x) == RTC_CLOCK_OUTPUT_EXA_1)) +#define IS_RTC_CALI_FREQ(x) (((x) == RTC_CALI_FREQ_10_SEC) || \ + ((x) == RTC_CALI_FREQ_20_SEC) || \ + ((x) == RTC_CALI_FREQ_1_MIN) || \ + ((x) == RTC_CALI_FREQ_2_MIN) || \ + ((x) == RTC_CALI_FREQ_5_MIN) || \ + ((x) == RTC_CALI_FREQ_10_MIN) || \ + ((x) == RTC_CALI_FREQ_20_MIN) || \ + ((x) == RTC_CALI_FREQ_1_SEC)) +#define IS_RTC_CALI_TC(x) (((x) == RTC_CALI_TC_NONE) || \ + ((x) == RTC_CALI_TC_AUTO_BY_HW) || \ + ((x) == RTC_CALI_TC_AUTO_BY_SF) || \ + ((x) == RTC_CALI_TC_AUTO_BY_HW_SF)) +#define IS_RTC_CALC_FREQ(x) (((x) == RTC_CALI_CALC_FREQ_10_SEC) || \ + ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \ + ((x) == RTC_CALI_CALC_FREQ_1_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_2_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_5_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_1_HOUR)) +#define IS_RTC_CALI_CALC(x) (((x) == RTC_CALI_CALC_4) || \ + ((x) == RTC_CALI_CALC_2)) +#define IS_RTC_IT(x) (((x) == RTC_IT_SEC) || \ + ((x) == RTC_IT_MIN) || \ + ((x) == RTC_IT_HR) || \ + ((x) == RTC_IT_DAY) || \ + ((x) == RTC_IT_MON) || \ + ((x) == RTC_IT_YR) || \ + ((x) == RTC_IT_ALMA) || \ + ((x) == RTC_IT_ALMB) || \ + ((x) == RTC_IT_TS) || \ + ((x) == RTC_IT_TSOV) || \ + ((x) == RTC_IT_TP0) || \ + ((x) == RTC_IT_TP1) || \ + ((x) == RTC_IT_RSC) || \ + ((x) == RTC_IT_SFC) || \ + ((x) == RTC_IT_WU) || \ + ((x) == RTC_IT_TCC) || \ + ((x) == RTC_IT_TCE)) +#define IS_RTC_IF(x) (((x) == RTC_IF_SEC) || \ + ((x) == RTC_IF_MIN) || \ + ((x) == RTC_IF_HR) || \ + ((x) == RTC_IF_DAY) || \ + ((x) == RTC_IF_MON) || \ + ((x) == RTC_IF_YR) || \ + ((x) == RTC_IF_ALMA) || \ + ((x) == RTC_IF_ALMB) || \ + ((x) == RTC_IF_TS) || \ + ((x) == RTC_IF_TSOV) || \ + ((x) == RTC_IF_TP0) || \ + ((x) == RTC_IF_TP1) || \ + ((x) == RTC_IF_RSC) || \ + ((x) == RTC_IF_SFC) || \ + ((x) == RTC_IF_WU) || \ + ((x) == RTC_IF_TCC) || \ + ((x) == RTC_IF_TCE)) +#define IS_RTC_SECOND(x) ((x) < 60) +#define IS_RTC_MINUTE(x) ((x) < 60) +#define IS_RTC_HOUR(x) ((x) < 24) +#define IS_RTC_DAY(x) (((x) > 0) && ((x) < 32)) +#define IS_RTC_MONTH(x) (((x) > 0) && ((x) < 13)) +#define IS_RTC_YEAR(x) ((x) < 100) +/** + * @} + */ + +/** @addtogroup RTC_Public_Functions + * @{ + */ + +/** @addtogroup RTC_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void rtc_reset(void); +void rtc_init(rtc_init_t *init); +void rtc_source_selcet(rtc_source_sel_t sel); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group2 + * @{ + */ +/* Time and date operation functions */ +ald_status_t rtc_set_time(rtc_time_t *time, rtc_format_t format); +ald_status_t rtc_set_date(rtc_date_t *date, rtc_format_t format); +void rtc_get_time(rtc_time_t *time, rtc_format_t format); +void rtc_get_date(rtc_date_t *date, rtc_format_t format); +int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group3 + * @{ + */ +/* Alarm functions */ +void rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format); +void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group4 + * @{ + */ +/* Time stamp functions */ +void rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style); +void rtc_cancel_time_stamp(void); +void rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group5 + * @{ + */ +/* Tamper functions */ +void rtc_set_tamper(rtc_tamper_t *tamper); +void rtc_cancel_tamper(rtc_tamper_idx_t idx); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group6 + * @{ + */ +/* Wakeup functions */ +void rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value); +void rtc_cancel_wakeup(void); +uint16_t rtc_get_wakeup_timer_value(void); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group7 + * @{ + */ +/* Clock output functions */ +ald_status_t rtc_set_clock_output(rtc_clock_output_t clock); +void rtc_cancel_clock_output(void); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group8 + * @{ + */ +/* Control functions */ +void rtc_interrupt_config(rtc_it_t it, type_func_t state); +void rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state); +ald_status_t rtc_set_shift(type_func_t add_1s, uint16_t sub_ss); +void rtc_set_cali(rtc_cali_t *config); +void rtc_cancel_cali(void); +ald_status_t rtc_get_cali_status(void); +void rtc_write_temp(uint16_t temp); +it_status_t rtc_get_it_status(rtc_it_t it); +flag_status_t rtc_get_flag_status(rtc_flag_t flag); +void rtc_clear_flag_status(rtc_flag_t flag); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h new file mode 100644 index 0000000000..1d5564bd76 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h @@ -0,0 +1,279 @@ +/** + ********************************************************************************* + * + * @file ald_usart.h + * @brief Header file of SMARTCARD driver module. + * + * @version V1.0 + * @date 25 Apr 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_SMARTCARD_H__ +#define __ALD_SMARTCARD_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" +#include "ald_usart.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup SMARTCARD + * @{ + */ + +/** @defgroup SMARTCARD_Public_Constants SMARTCARD Public constants + * @{ + */ + +/** + * @brief SMARTCARD error codes + */ +typedef enum +{ + SMARTCARD_ERROR_NONE = ((uint32_t)0x00), /**< No error */ + SMARTCARD_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ + SMARTCARD_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ + SMARTCARD_ERROR_FE = ((uint32_t)0x04), /**< frame error */ + SMARTCARD_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ + SMARTCARD_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +} smartcard_error_t; + +/** + * @brief SMARTCARD Prescaler + */ +typedef enum +{ + SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1), /**< SYSCLK divided by 2 */ + SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2), /**< SYSCLK divided by 4 */ + SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3), /**< SYSCLK divided by 6 */ + SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4), /**< SYSCLK divided by 8 */ + SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5), /**< SYSCLK divided by 10 */ + SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6), /**< SYSCLK divided by 12 */ + SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7), /**< SYSCLK divided by 14 */ + SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8), /**< SYSCLK divided by 16 */ + SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9), /**< SYSCLK divided by 18 */ + SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xA), /**< SYSCLK divided by 20 */ + SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xB), /**< SYSCLK divided by 22 */ + SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xC), /**< SYSCLK divided by 24 */ + SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xD), /**< SYSCLK divided by 26 */ + SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xE), /**< SYSCLK divided by 28 */ + SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xF), /**< SYSCLK divided by 30 */ + SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10), /**< SYSCLK divided by 32 */ + SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11), /**< SYSCLK divided by 34 */ + SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12), /**< SYSCLK divided by 36 */ + SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13), /**< SYSCLK divided by 38 */ + SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14), /**< SYSCLK divided by 40 */ + SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15), /**< SYSCLK divided by 42 */ + SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16), /**< SYSCLK divided by 44 */ + SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17), /**< SYSCLK divided by 46 */ + SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18), /**< SYSCLK divided by 48 */ + SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19), /**< SYSCLK divided by 50 */ + SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1A), /**< SYSCLK divided by 52 */ + SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1B), /**< SYSCLK divided by 54 */ + SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1C), /**< SYSCLK divided by 56 */ + SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1D), /**< SYSCLK divided by 58 */ + SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1E), /**< SYSCLK divided by 60 */ + SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1F), /**< SYSCLK divided by 62 */ +} smartcard_prescaler_t; + +/** + * @} + */ + +/** @defgroup SMARTCARD_Public_Types SMARTCARD Public Types + * @{ + */ + +/** + * @brief SMARTCARD Init Structure definition + */ +typedef struct +{ + uint32_t baud; /**< This member configures the SmartCard communication baud rate. */ + usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ + usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ + usart_parity_t parity; /**< Specifies the parity mode. + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits).*/ + usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */ + usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ + usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/ + usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref usart_last_bit_t */ + smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock + to provide the smartcard clock. The value given in the register (5 significant bits) + is multiplied by 2 to give the division factor of the source clock frequency. */ + uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */ + type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */ +} smartcard_init_t; + +/** + * @brief ALD state structures definition + */ +typedef enum +{ + SMARTCARD_STATE_RESET = 0x00, /**< Peripheral is not yet Initialized */ + SMARTCARD_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + SMARTCARD_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + SMARTCARD_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ + SMARTCARD_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ + SMARTCARD_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission and Reception process is ongoing */ + SMARTCARD_STATE_TIMEOUT = 0x03, /**< Timeout state */ + SMARTCARD_STATE_ERROR = 0x04 /**< Error */ +} smartcard_state_t; + + +/** + * @brief SMARTCARD handle structure definition + */ +typedef struct smartcard_handle_s +{ + USART_TypeDef *perh; /**< USART registers base address */ + smartcard_init_t init; /**< SmartCard communication parameters */ + uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */ + uint16_t tx_size; /**< SmartCard Tx Transfer size */ + uint16_t tx_count; /**< SmartCard Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */ + uint16_t rx_size; /**< SmartCard Rx Transfer size */ + uint16_t rx_count; /**< SmartCard Rx Transfer Counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */ + dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + smartcard_state_t state; /**< SmartCard communication state */ + uint32_t err_code; /**< SmartCard Error code */ + + void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */ +} smartcard_handle_t; + +/** + * @} + */ + +/** @defgroup SMARTCARD_Public_Macros SMARTCARD Public Macros + * @{ + */ + +/** @defgroup SMARTCARD_Public_Macros_1 SMARTCARD handle reset + * @{ + */ +#define SMARTCARD_RESET_HANDLE_STATE(handle) ((handle)->state = SMARTCARD_STATE_RESET) +/** + * @} + */ + +/** @defgroup SMARTCARD_Public_Macros_2 SMARTCARD flush data + * @{ + */ +#define SMARTCARD_FLUSH_DRREGISTER(handle) ((handle)->perh->DATA) +/** + * @} + */ + +/** @defgroup SMARTCARD_Public_Macros_3 SMARTCARD enable + * @{ + */ +#define SMARTCARD_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Public_Macros_4 SMARTCARD disable + * @{ + */ +#define SMARTCARD_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros + * @{ + */ + +#define IS_SMARTCARD_PRESCALER(x) (((x) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \ + ((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62)) +/** + * @} + */ + +/** @addtogroup SMARTCARD_Public_Functions + * @{ + */ + +/** @addtogroup SMARTCARD_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +ald_status_t smartcard_init(smartcard_handle_t *hperh); +ald_status_t smartcard_reset(smartcard_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup SMARTCARD_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size); +#ifdef ALD_DMA +ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +#endif +void smartcard_irq_handle(smartcard_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup SMARTCARD_Public_Functions_Group3 + * @{ + */ +/* Peripheral State and Errors functions functions */ +smartcard_state_t smartcard_get_state(smartcard_handle_t *hperh); +uint32_t smartcard_get_error(smartcard_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_SMARTCARD_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h new file mode 100644 index 0000000000..467e92b07f --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h @@ -0,0 +1,377 @@ +/** + ********************************************************************************* + * + * @file ald_spi.c + * @brief Header file of SPI module driver. + * + * @version V1.0 + * @date 13 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_SPI_H__ +#define __ALD_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Public_Types SPI Public Types + * @{ + */ + +/** + * @brief clock phase + */ +typedef enum +{ + SPI_CPHA_FIRST = 0, /**< Transiting data in the first edge */ + SPI_CPHA_SECOND = 1, /**< Transiting data in the seconde edge */ +} spi_cpha_t; + +/** + * @brief clock polarity + */ +typedef enum +{ + SPI_CPOL_LOW = 0, /**< Polarity hold low when spi-bus is idle */ + SPI_CPOL_HIGH = 1, /**< Polarity hold high when spi-bus is idle */ +} spi_cpol_t; + +/** + * @brief master selection + */ +typedef enum +{ + SPI_MODE_SLAVER = 0, /**< Slave mode */ + SPI_MODE_MASTER = 1, /**< Master mode */ +} spi_mode_t; + +/** + * @brief baud rate control + */ +typedef enum +{ + SPI_BAUD_2 = 0, /**< fpclk/2 */ + SPI_BAUD_4 = 1, /**< fpclk/4 */ + SPI_BAUD_8 = 2, /**< fpclk/8 */ + SPI_BAUD_16 = 3, /**< fpclk/16 */ + SPI_BAUD_32 = 4, /**< fpclk/32 */ + SPI_BAUD_64 = 5, /**< fpclk/64 */ + SPI_BAUD_128 = 6, /**< fpclk/128 */ + SPI_BAUD_256 = 7, /**< fpclk/256 */ +} spi_baud_t; + +/** + * @brief frame format + */ +typedef enum +{ + SPI_FIRSTBIT_MSB = 0, /**< MSB transmitted first */ + SPI_FIRSTBIT_LSB = 1, /**< LSB transmitted first */ +} spi_firstbit_t; + +/** + * @brief data frame format + */ +typedef enum +{ + SPI_DATA_SIZE_8 = 0, /**< 8-bit data frame format is selected for transmission/reception */ + SPI_DATA_SIZE_16 = 1, /**< 16-bit data frame format is selected for transmission/reception */ +} spi_datasize_t; + +/** + * @brief interrupt control + */ +typedef enum +{ + SPI_IT_ERR = (1U << 5), /**< error interrupt */ + SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */ + SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */ +} spi_it_t; + +/** + * @brief interrupt flag + */ +typedef enum +{ + SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */ + SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */ + SPI_IF_CRCERR = (1U << 4), /**< crc error flag */ + SPI_IF_MODF = (1U << 5), /**< mode fault */ + SPI_IF_OVE = (1U << 6), /**< overrun flag */ + SPI_IF_BUSY = (1U << 7), /**< busy flag */ +} spi_flag_t; + +/** + * @brief SPI error status + */ +typedef enum +{ + SPI_ERROR_NONE = 0, /**< none */ + SPI_ERROR_MODF = 1, /**< mode fault */ + SPI_ERROR_CRC = 2, /**< crc error */ + SPI_ERROR_OVE = 4, /**< overrun error */ + SPI_ERROR_DMA = 8, /**< dma error */ + SPI_ERROR_FLAG = 0x10, /**< interrupt flag error */ +} spi_error_t; + + + +/** + * @brief SPI state structures definition + */ +typedef enum +{ + SPI_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + SPI_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + SPI_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + SPI_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */ + SPI_STATE_BUSY_RX = 0x21, /**< receive is ongoing */ + SPI_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */ + SPI_STATE_TIMEOUT = 0x03, /**< Timeout state */ + SPI_STATE_ERROR = 0x04, /**< Error */ +} spi_state_t; + + +/** + * @brief SPI direction definition + */ +typedef enum +{ + SPI_DIRECTION_2LINES = 0, /**< 2 lines */ + SPI_DIRECTION_2LINES_RXONLY = 1, /**< 2 lines only rx */ + SPI_DIRECTION_1LINE = 2, /**< 1 line */ + SPI_DIRECTION_1LINE_RX = 3, /**< 1 line only rx */ +} spi_direction_t; + +/** + * @brief SPI dma request definition + */ +typedef enum +{ + SPI_DMA_REQ_TX = 0, /**< TX dma request */ + SPI_DMA_REQ_RX = 1, /**< RX dma request */ +} spi_dma_req_t; + +/** + * @brief SPI TXE/RXNE status definition + */ +typedef enum +{ + SPI_SR_TXBE = 0, /**< SR.TXE set */ + SPI_SR_RXBNE = 1, /**< SR.RXNE set */ + SPI_SR_TXBE_RXBNE = 2, /**< SR.TXE and SR.RXNE set */ +} spi_sr_status_t; + +/** + * @brief SPI init structure definition + */ +typedef struct +{ + spi_mode_t mode; /**< SPI mode */ + spi_direction_t dir; /**< SPI direction */ + spi_datasize_t data_size; /**< SPI data size */ + spi_baud_t baud; /**< SPI baudrate prescaler */ + spi_cpha_t phase; /**< SPI clock phase */ + spi_cpol_t polarity; /**< SPI clock polarity */ + spi_firstbit_t first_bit; /**< SPI first bit */ + type_func_t ss_en; /**< SPI ssm enable or disable */ + type_func_t crc_calc; /**< SPI crc calculation */ + uint16_t crc_poly; /**< SPI crc polynomial */ +} spi_init_t; + +/** + * @brief SPI handle structure definition + */ +typedef struct spi_handle_s +{ + SPI_TypeDef *perh; /**< SPI registers base address */ + spi_init_t init; /**< SPI communication parameters */ + uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */ + uint16_t tx_size; /**< SPI Tx transfer size */ + uint16_t tx_count; /**< SPI Tx transfer counter */ + uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */ + uint16_t rx_size; /**< SPI Rx Transfer size */ + uint16_t rx_count; /**< SPI Rx Transfer Counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + spi_state_t state; /**< SPI communication state */ + uint32_t err_code; /**< SPI error code */ + + void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */ + void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */ + void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */ +} spi_handle_t; +/** + * @} + */ + +/** @defgroup SPI_Public_Macros SPI Public Macros + * @{ + */ +#define SPI_RESET_HANDLE_STATE(x) ((x)->state = SPI_STATE_RESET) +#define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS)) +#define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS)) +#define SPI_CRC_RESET(x) \ +do { \ + CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ + SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ +} while (0) +#define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) +#define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) +#define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) +#define SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) +#define SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) +#define SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) +#define SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) +#define SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) +#define SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) +#define SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) +/** + * @} + */ + +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ +#define IS_SPI(x) (((x) == SPI0) || \ + ((x) == SPI1) || \ + ((x) == SPI2)) +#define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \ + ((x) == SPI_CPHA_SECOND)) +#define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \ + ((x) == SPI_CPOL_HIGH)) +#define IS_SPI_MODE(x) (((x) == SPI_MODE_SLAVER) || \ + ((x) == SPI_MODE_MASTER)) +#define IS_SPI_BAUD(x) (((x) == SPI_BAUD_2) || \ + ((x) == SPI_BAUD_4) || \ + ((x) == SPI_BAUD_8) || \ + ((x) == SPI_BAUD_16) || \ + ((x) == SPI_BAUD_32) || \ + ((x) == SPI_BAUD_64) || \ + ((x) == SPI_BAUD_128) || \ + ((x) == SPI_BAUD_256)) +#define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \ + ((x) == SPI_DATA_SIZE_16)) +#define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \ + ((x) == SPI_BID_TX)) +#define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \ + ((x) == SPI_BIDMODE_SOLE)) +#define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \ + ((x) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((x) == SPI_DIRECTION_1LINE) || \ + ((x) == SPI_DIRECTION_1LINE_RX)) +#define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \ + ((x) == SPI_DMA_REQ_RX)) +#define IS_SPI_SR_STATUS(x) (((x) == SPI_SR_TXBE) || \ + ((x) == SPI_SR_RXBNE) || \ + ((x) == SPI_SR_TXBE_RXBNE)) +#define IS_SPI_IT(x) (((x) == SPI_IT_ERR) || \ + ((x) == SPI_IT_RXBNE) || \ + ((x) == SPI_IT_TXBE)) +#define IS_SPI_IF(x) (((x) == SPI_IF_RXBNE) || \ + ((x) == SPI_IF_TXBE) || \ + ((x) == SPI_IF_CRCERR) || \ + ((x) == SPI_IF_MODF) || \ + ((x) == SPI_IF_OVE) || \ + ((x) == SPI_IF_BUSY)) +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions + * @{ + */ + +/** @addtogroup SPI_Public_Functions_Group1 + * @{ + */ + +ald_status_t spi_init(spi_handle_t *hperh); +void spi_reset(spi_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions_Group2 + * @{ + */ +int32_t spi_send_byte_fast(spi_handle_t *hperh, uint8_t data); +uint8_t spi_recv_byte_fast(spi_handle_t *hperh); +ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); +ald_status_t spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); +#ifdef ALD_DMA +ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); +ald_status_t spi_dma_pause(spi_handle_t *hperh); +ald_status_t spi_dma_resume(spi_handle_t *hperh); +ald_status_t spi_dma_stop(spi_handle_t *hperh); +#endif +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions_Group3 + * @{ + */ +void spi_irq_handle(spi_handle_t *hperh); +void spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state); +void spi_speed_config(spi_handle_t *hperh, spi_baud_t speed); +void spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state); +it_status_t spi_get_it_status(spi_handle_t *hperh, spi_it_t it); +flag_status_t spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag); +void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag); +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions_Group4 + * @{ + */ +spi_state_t spi_get_state(spi_handle_t *hperh); +uint32_t spi_get_error(spi_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h new file mode 100644 index 0000000000..22ef750f70 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h @@ -0,0 +1,107 @@ +/** + ********************************************************************************* + * + * @file ald_syscfg.h + * @brief SYSCFG module driver. + * + * @version V1.0 + * @date 04 Jun 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_SYSCFG_H__ +#define __ALD_SYSCFG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup SYSCFG SYSCFG + * @brief SYSCFG module driver + * @{ + */ + +/** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros + * @{ + */ +#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0) +#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996) +#define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK) + +#define BOOT_FROM_BOOT_ROM() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) + +#define BOOT_FROM_BOOT_FLASH() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) + +#define BOOT_FROM_FLASH() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +/** + * @} + */ + + +/** @defgroup SYSCFG_Public_Functions SYSCFG Public Functions + * @{ + */ +__STATIC_INLINE__ void vtor_config(uint32_t offset, type_func_t status) +{ + SYSCFG_UNLOCK(); + + if (status) + { + MODIFY_REG(SYSCFG->VTOR, SYSCFG_VTOR_VTO_MSK, (offset & ~0x3F)); + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK); + } + else + { + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK); + } + + SYSCFG_LOCK(); + return; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_temp.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_temp.h new file mode 100644 index 0000000000..b9d5c15d15 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_temp.h @@ -0,0 +1,203 @@ +/** + ********************************************************************************* + * + * @file ald_temp.h + * @brief Header file of TEMP module driver. + * + * @version V1.0 + * @date 15 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_TEMP_H__ +#define __ALD_TEMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup TEMP + * @{ + */ + +/** @defgroup TEMP_Public_Macros TEMP Public Macros + * @{ + */ +#define TEMP_LOCK() (WRITE_REG(TEMP->WPR, 0x0)) +#define TEMP_UNLOCK() (WRITE_REG(TEMP->WPR, 0xA55A9669)) +#define TEMP_ENABLE() \ +do { \ + TEMP_UNLOCK(); \ + SET_BIT(TEMP->CR, TEMP_CR_EN_MSK); \ + TEMP_LOCK(); \ +} while (0) +#define TEMP_DISABLE() \ +do { \ + TEMP_UNLOCK(); \ + CLEAR_BIT(TEMP->CR, TEMP_CR_EN_MSK); \ + TEMP_LOCK(); \ +} while (0) +#define TEMP_REQ_ENABLE() \ +do { \ + TEMP_UNLOCK(); \ + SET_BIT(TEMP->CR, TEMP_CR_REQEN_MSK); \ + TEMP_LOCK(); \ +} while (0) +#define TEMP_REQ_DISABLE() \ +do { \ + TEMP_UNLOCK(); \ + CLEAR_BIT(TEMP->CR, TEMP_CR_REQEN_MSK); \ + TEMP_LOCK(); \ +} while (0) +#define TEMP_CTN_ENABLE() \ +do { \ + TEMP_UNLOCK(); \ + SET_BIT(TEMP->CR, TEMP_CR_CTN_MSK); \ + TEMP_LOCK(); \ +} while (0) +#define TEMP_CTN_DISABLE() \ +do { \ + TEMP_UNLOCK(); \ + CLEAR_BIT(TEMP->CR, TEMP_CR_CTN_MSK); \ + TEMP_LOCK(); \ +} while (0) +#define TEMP_RESET() \ +do { \ + TEMP_UNLOCK(); \ + SET_BIT(TEMP->CR, TEMP_CR_RST_MSK); \ + TEMP_LOCK(); \ +} while (0) +/** + * @} + */ + +/** @defgroup TEMP_Public_Types TEMP Public Types + * @{ + */ +/** + * @brief Temperature update time + */ +typedef enum +{ + TEMP_UPDATE_CYCLE_3 = 0x3, /**< 3 Cycles */ + TEMP_UPDATE_CYCLE_4 = 0x4, /**< 4 Cycles */ + TEMP_UPDATE_CYCLE_5 = 0x5, /**< 5 Cycles */ + TEMP_UPDATE_CYCLE_6 = 0x6, /**< 6 Cycles */ + TEMP_UPDATE_CYCLE_7 = 0x7, /**< 7 Cycles */ +} temp_update_cycle_t; + +/** + * @brief Temperature output mode + */ +typedef enum +{ + TEMP_OUTPUT_MODE_200 = 0x0, /**< 200 cycles update one temperature */ + TEMP_OUTPUT_MODE_400 = 0x1, /**< 400 cycles update one temperature */ + TEMP_OUTPUT_MODE_800 = 0x2, /**< 800 cycles update one temperature */ + TEMP_OUTPUT_MODE_1600 = 0x3, /**< 1600 cycles update one temperature */ + TEMP_OUTPUT_MODE_3200 = 0x4, /**< 3200 cycles update one temperature */ +} temp_output_mode_t; + +/** + * @brief Source select + */ +typedef enum +{ + TEMP_SOURCE_LOSC = 0x0, /**< LOSC */ + TEMP_SOURCE_LRC = 0x1, /**< LRC */ + TEMP_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ + TEMP_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ +} temp_source_sel_t; + + +/** + * @brief TEMP init structure definition + */ +typedef struct +{ + temp_update_cycle_t cycle; /**< Temperature update time */ + temp_output_mode_t mode; /**< Temperature output mode */ + uint8_t ctn; /**< Continue mode */ + uint8_t psc; /**< Perscaler */ +} temp_init_t; + +/** + * @brief Define callback function type + */ +typedef void (*temp_cbk)(uint16_t value, ald_status_t status); +/** + * @} + */ + +/** + * @defgroup TEMP_Private_Macros TEMP Private Macros + * @{ + */ +#define IS_TEMP_UPDATE_CYCLE(x) (((x) == TEMP_UPDATE_CYCLE_3) || \ + ((x) == TEMP_UPDATE_CYCLE_4) || \ + ((x) == TEMP_UPDATE_CYCLE_5) || \ + ((x) == TEMP_UPDATE_CYCLE_6) || \ + ((x) == TEMP_UPDATE_CYCLE_7)) +#define IS_TEMP_OUTPUT_MODE(x) (((x) == TEMP_OUTPUT_MODE_200) || \ + ((x) == TEMP_OUTPUT_MODE_400) || \ + ((x) == TEMP_OUTPUT_MODE_800) || \ + ((x) == TEMP_OUTPUT_MODE_1600) || \ + ((x) == TEMP_OUTPUT_MODE_3200)) +#define IS_TEMP_SOURCE_SEL(x) (((x) == TEMP_SOURCE_LOSC) || \ + ((x) == TEMP_SOURCE_LRC) || \ + ((x) == TEMP_SOURCE_HRC_DIV_1M ) || \ + ((x) == TEMP_SOURCE_HOSC_DIV_1M)) +/** + * @} + */ + +/** @addtogroup TEMP_Public_Functions + * @{ + */ +/** @addtogroup TEMP_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern void temp_init(temp_init_t *init); +extern void temp_source_selcet(temp_source_sel_t sel); +/** + * @} + */ +/** @addtogroup TEMP_Public_Functions_Group2 + * @{ + */ +/* Control functions */ +extern ald_status_t temp_get_value(uint16_t *temp); +extern void temp_get_value_by_it(temp_cbk cbk); +void temp_irq_handle(void); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_TEMP_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h new file mode 100644 index 0000000000..6eaf44da44 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h @@ -0,0 +1,1130 @@ +/** + ********************************************************************************* + * + * @file ald_timer.h + * @brief TIMER module driver. + * This is the common part of the TIMER initialization + * + * @version V1.0 + * @date 06 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_TIMER_H__ +#define __ALD_TIMER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/** @defgroup TIMER_Public_Types TIMER Public Types + * @{ + */ + +/** + * @brief TIMER counter mode + */ +typedef enum +{ + TIMER_CNT_MODE_UP = 0, /**< Counter mode up */ + TIMER_CNT_MODE_DOWN = 1, /**< Counter mode down */ + TIMER_CNT_MODE_CENTER1 = 2, /**< Counter mode center1 */ + TIMER_CNT_MODE_CENTER2 = 3, /**< Counter mode center2 */ + TIMER_CNT_MODE_CENTER3 = 4, /**< Counter mode center3 */ +} timer_cnt_mode_t; + +/** + * @brief TIMER clock division + */ +typedef enum +{ + TIMER_CLOCK_DIV1 = 0, /**< No prescaler is used */ + TIMER_CLOCK_DIV2 = 1, /** Clock is divided by 2 */ + TIMER_CLOCK_DIV4 = 2, /** Clock is divided by 4 */ +} timer_clock_division_t; + +/** + * @brief TIMER output compare and PWM modes + */ +typedef enum +{ + TIMER_OC_MODE_TIMERING = 0, /**< Output compare mode is timering */ + TIMER_OC_MODE_ACTIVE = 1, /**< Output compare mode is active */ + TIMER_OC_MODE_INACTIVE = 2, /**< Output compare mode is inactive */ + TIMER_OC_MODE_TOGGLE = 3, /**< Output compare mode is toggle */ + TIMER_OC_MODE_FORCE_INACTIVE = 4, /**< Output compare mode is force inactive */ + TIMER_OC_MODE_FORCE_ACTIVE = 5, /**< Output compare mode is force active */ + TIMER_OC_MODE_PWM1 = 6, /**< Output compare mode is pwm1 */ + TIMER_OC_MODE_PWM2 = 7, /**< Output compare mode is pwm2 */ +} timer_oc_mode_t; + +/** + * @brief TIMER output compare polarity + */ +typedef enum +{ + TIMER_OC_POLARITY_HIGH = 0, /**< Output compare polarity is high */ + TIMER_OC_POLARITY_LOW = 1, /**< Output compare polarity is low */ +} timer_oc_polarity_t; + +/** + * @brief TIMER complementary output compare polarity + */ +typedef enum +{ + TIMER_OCN_POLARITY_HIGH = 0, /**< Complementary output compare polarity is high */ + TIMER_OCN_POLARITY_LOW = 1, /**< Complementary output compare polarity is low */ +} timer_ocn_polarity_t; + +/** + * @brief TIMER output compare idle state + */ +typedef enum +{ + TIMER_OC_IDLE_RESET = 0, /**< Output compare idle state is reset */ + TIMER_OC_IDLE_SET = 1, /**< Output compare idle state is set */ +} timer_oc_idle_t; + +/** + * @brief TIMER complementary output compare idle state + */ +typedef enum +{ + TIMER_OCN_IDLE_RESET = 0, /**< Complementary output compare idle state is reset */ + TIMER_OCN_IDLE_SET = 1, /**< Complementary output compare idle state is set */ +} timer_ocn_idle_t; + +/** + * @brief TIMER channel + */ +typedef enum +{ + TIMER_CHANNEL_1 = 0, /**< Channel 1 */ + TIMER_CHANNEL_2 = 1, /**< Channel 2 */ + TIMER_CHANNEL_3 = 2, /**< Channel 3 */ + TIMER_CHANNEL_4 = 4, /**< Channel 4 */ + TIMER_CHANNEL_ALL = 0xF, /**< All channel */ +} timer_channel_t; + +/** + * @brief TIMER one pulse mode + */ +typedef enum +{ + TIMER_OP_MODE_REPEAT = 0, /**< Repetitive */ + TIMER_OP_MODE_SINGLE = 1, /**< single */ +} timer_op_mode_t; + +/** + * @brief TIMER one pulse output channel + */ +typedef enum +{ + TIMER_OP_OUTPUT_CHANNEL_1 = 0, /**< One pulse output channal 1 */ + TIMER_OP_OUTPUT_CHANNEL_2 = 1, /**< One pulse output channal 2 */ +} timer_op_output_channel_t; + +/** + * @brief TIMER time base configuration structure definition + */ +typedef struct +{ + uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ + timer_cnt_mode_t mode; /**< Specifies the counter mode. */ + uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ + timer_clock_division_t clk_div; /**< Specifies the clock division.*/ + uint32_t re_cnt; /**< Specifies the repetition counter value. */ +} timer_base_init_t; + +/** + * @brief TIMER output compare configuration structure definition + */ +typedef struct +{ + timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ + uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ + timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ + timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ + type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ + timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ + timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ +} timer_oc_init_t; + +/** + * @brief State structures definition + */ +typedef enum +{ + TIMER_STATE_RESET = 0x00, /**< Peripheral not yet initialized or disabled */ + TIMER_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + TIMER_STATE_BUSY = 0x02, /**< An internal process is ongoing */ + TIMER_STATE_TIMEREOUT = 0x03, /**< Timeout state */ + TIMER_STATE_ERROR = 0x04, /**< Reception process is ongoing */ +} timer_state_t; + +/** + * @brief Active channel structures definition + */ +typedef enum +{ + TIMER_ACTIVE_CHANNEL_1 = 0x01, /**< The active channel is 1 */ + TIMER_ACTIVE_CHANNEL_2 = 0x02, /**< The active channel is 2 */ + TIMER_ACTIVE_CHANNEL_3 = 0x04, /**< The active channel is 3 */ + TIMER_ACTIVE_CHANNEL_4 = 0x08, /**< The active channel is 4 */ + TIMER_ACTIVE_CHANNEL_CLEARED = 0x00, /**< All active channels cleared */ +} timer_active_channel_t; + +/** + * @brief TIMER time base handle structure definition + */ +typedef struct timer_handle_s +{ + TIMER_TypeDef *perh; /**< Register base address */ + timer_base_init_t init; /**< TIMER Time Base required parameters */ + timer_active_channel_t ch; /**< Active channel */ + lock_state_t lock; /**< Locking object */ + timer_state_t state; /**< TIMER operation state */ + + void (*period_elapse_cbk)(struct timer_handle_s *arg); /**< Period elapse callback */ + void (*delay_elapse_cbk)(struct timer_handle_s *arg); /**< Delay_elapse callback */ + void (*capture_cbk)(struct timer_handle_s *arg); /**< Capture callback */ + void (*pwm_pulse_finish_cbk)(struct timer_handle_s *arg); /**< PWM_pulse_finish callback */ + void (*trigger_cbk)(struct timer_handle_s *arg); /**< Trigger callback */ + void (*break_cbk)(struct timer_handle_s *arg); /**< Break callback */ + void (*com_cbk)(struct timer_handle_s *arg); /**< commutation callback */ + void (*error_cbk)(struct timer_handle_s *arg); /**< Error callback */ +} timer_handle_t; + + +/** + * @brief TIMER encoder mode + */ +typedef enum +{ + TIMER_ENC_MODE_TI1 = 1, /**< encoder mode 1 */ + TIMER_ENC_MODE_TI2 = 2, /**< encoder mode 2 */ + TIMER_ENC_MODE_TI12 = 3, /**< encoder mode 3 */ +} timer_encoder_mode_t; + +/** + * @brief TIMER input capture polarity + */ +typedef enum +{ + TIMER_IC_POLARITY_RISE = 0, /**< Input capture polarity rising */ + TIMER_IC_POLARITY_FALL = 1, /**< Input capture polarity falling */ + TIMER_IC_POLARITY_BOTH = 3, /**< Input capture polarity rising and falling */ +} timer_ic_polarity_t; + +/** + *@brief TIMER input capture selection + */ +typedef enum +{ + TIMER_IC_SEL_DIRECT = 1, /**< IC1 -- TI1 */ + TIMER_IC_SEL_INDIRECT = 2, /**< IC1 -- TI2 */ + TIMER_IC_SEL_TRC = 3, /**< IC1 -- TRC */ +} timer_ic_select_t; + +/** + * @brief TIMER input capture prescaler + */ +typedef enum +{ + TIMER_IC_PSC_DIV1 = 0, /**< Capture performed once every 1 events */ + TIMER_IC_PSC_DIV2 = 1, /**< Capture performed once every 2 events */ + TIMER_IC_PSC_DIV4 = 2, /**< Capture performed once every 4 events */ + TIMER_IC_PSC_DIV8 = 3, /**< Capture performed once every 4 events */ +} timer_ic_prescaler_t; + +/** + * @brief TIMER encoder configuration structure definition + */ +typedef struct +{ + timer_encoder_mode_t mode; /**< Specifies the encoder mode */ + timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t ic1_sel; /**< Specifies the input */ + timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic1_filter; /**< Specifies the input capture filter */ + timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t ic2_sel; /**< Specifies the input */ + timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic2_filter; /**< Specifies the input capture filter */ +} timer_encoder_init_t; + +/** + * @brief TIMER input capture configuration structure definition + */ +typedef struct +{ + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t sel; /**< Specifies the input */ + timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter */ +} timer_ic_init_t; + +/** + * @brief TIMER one pulse mode configuration structure definition + */ +typedef struct +{ + timer_oc_mode_t mode; /**< Specifies the TIMER mode */ + uint16_t pulse; /**< Specifies the pulse value */ + timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ + timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ + timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t sel; /**< Specifies the input */ + uint32_t filter; /**< Specifies the input capture filter */ +} timer_one_pulse_init_t; + +/** @brief TIMER clear input source + */ +typedef enum +{ + TIMER_INPUT_NONE = 0, /**< Clear input none */ + TIMER_INPUT_ETR = 1, /**< Clear input etr */ +} timer_clear_input_source_t; + +/** @brief TIMER clear input polarity + */ +typedef enum +{ + TIMER_POLARITY_NO_INV = 0, /**< Polarity for ETRx pin */ + TIMER_POLARITY_INV = 1, /**< Polarity for ETRx pin */ +} timer_clear_input_polarity_t; + +/** @brief TIMER clear input polarity + */ +typedef enum +{ + TIMER_ETR_PSC_DIV1 = 0, /**< No prescaler is used */ + TIMER_ETR_PSC_DIV2 = 1, /**< ETR input source is divided by 2 */ + TIMER_ETR_PSC_DIV4 = 2, /**< ETR input source is divided by 4 */ + TIMER_ETR_PSC_DIV8 = 3, /**< ETR input source is divided by 8 */ +} timer_etr_psc_t; + +/** + * @brief TIMER clear input configuration handle structure definition + */ +typedef struct +{ + type_func_t state; /**< TIMER clear Input state */ + timer_clear_input_source_t source; /**< TIMER clear Input sources */ + timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ + timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ + uint32_t filter; /**< TIMER Clear Input filter */ +} timer_clear_input_config_t; + +/** @brief TIMER clock source + */ +typedef enum +{ + TIMER_SRC_ETRMODE2 = 0, /**< Clock source is etr mode2 */ + TIMER_SRC_INTER = 1, /**< Clock source is etr internal */ + TIMER_SRC_ITR0 = 2, /**< Clock source is etr itr0 */ + TIMER_SRC_ITR1 = 3, /**< Clock source is etr itr1 */ + TIMER_SRC_ITR2 = 4, /**< Clock source is etr itr2 */ + TIMER_SRC_ITR3 = 5, /**< Clock source is etr itr3 */ + TIMER_SRC_TI1ED = 6, /**< Clock source is etr ti1ed */ + TIMER_SRC_TI1 = 7, /**< Clock source is etr ti1 */ + TIMER_SRC_TI2 = 8, /**< Clock source is etr ti2 */ + TIMER_SRC_ETRMODE1 = 9, /**< Clock source is etr mode1 */ +} timer_clock_source_t; + +/** @brief TIMER clock polarity + */ +typedef enum +{ + TIMER_CLK_POLARITY_INV = 1, /**< Polarity for ETRx clock sources */ + TIMER_CLK_POLARITY_NO_INV = 0, /**< Polarity for ETRx clock sources */ + TIMER_CLK_POLARITY_RISE = 0, /**< Polarity for TIx clock sources */ + TIMER_CLK_POLARITY_FALL = 1, /**< Polarity for TIx clock sources */ + TIMER_CLK_POLARITY_BOTH = 3, /**< Polarity for TIx clock sources */ +} timer_clock_polarity_t; + +/** + * @brief TIMER clock config structure definition + */ +typedef struct +{ + timer_clock_source_t source; /**< TIMER clock sources */ + timer_clock_polarity_t polarity; /**< TIMER clock polarity */ + timer_etr_psc_t psc; /**< TIMER clock prescaler */ + uint32_t filter; /**< TIMER clock filter */ +} timer_clock_config_t; + +/** + * @brief TIMER slave mode + */ +typedef enum +{ + TIMER_MODE_DISABLE = 0, /**< Slave mode is disable */ + TIMER_MODE_ENC1 = 1, /**< Slave mode is encoder1 */ + TIMER_MODE_ENC2 = 2, /**< Slave mode is encoder2 */ + TIMER_MODE_ENC3 = 3, /**< Slave mode is encoder3 */ + TIMER_MODE_RESET = 4, /**< Slave mode is reset */ + TIMER_MODE_GATED = 5, /**< Slave mode is gated */ + TIMER_MODE_TRIG = 6, /**< Slave mode is trigger */ + TIMER_MODE_EXTERNAL1 = 7, /**< Slave mode is external1 */ +} timer_slave_mode_t; + +/** + * @brief TIMER ts definition + */ +typedef enum +{ + TIMER_TS_ITR0 = 0, /**< ITR0 */ + TIMER_TS_ITR1 = 1, /**< ITR1 */ + TIMER_TS_ITR2 = 2, /**< ITR2 */ + TIMER_TS_ITR3 = 3, /**< ITR3 */ + TIMER_TS_TI1F_ED = 4, /**< TI1F_ED */ + TIMER_TS_TI1FP1 = 5, /**< TI1FP1 */ + TIMER_TS_TI2FP2 = 6, /**< TI2FP2 */ + TIMER_TS_ETRF = 7, /**< ETRF */ +} timer_ts_t; + +/** + * @brief TIMER slave configuration structure definition + */ +typedef struct +{ + timer_slave_mode_t mode; /**< Slave mode selection */ + timer_ts_t input; /**< Input Trigger source */ + timer_clock_polarity_t polarity; /**< Input Trigger polarity */ + timer_etr_psc_t psc; /**< Input trigger prescaler */ + uint32_t filter; /**< Input trigger filter */ +} timer_slave_config_t; + +/** + * @brief TIMER hall sensor configuretion structure definition + */ +typedef struct +{ + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter [0x0, 0xF] */ + uint32_t delay; /**< Specifies the pulse value to be loaded into the register [0x0, 0xFFFF] */ +} timer_hall_sensor_init_t; + +/** + * @brief TIMER lock level + */ +typedef enum +{ + TIMER_LOCK_LEVEL_OFF = 0, /**< Lock off */ + TIMER_LOCK_LEVEL_1 = 1, /**< Lock level 1 */ + TIMER_LOCK_LEVEL_2 = 2, /**< Lock level 2 */ + TIMER_LOCK_LEVEL_3 = 3, /**< Lock level 3 */ +} timer_lock_level_t; + +/** + * @brief TIMER break polarity + */ +typedef enum +{ + TIMER_BREAK_POLARITY_LOW = 0, /**< LOW */ + TIMER_BREAK_POLARITY_HIGH = 1, /**< HIGH */ +} timer_break_polarity_t; + +/** + * @brief TIMER break and dead time configuretion structure definition + */ +typedef struct +{ + type_func_t off_run; /**< Enalbe/Disable off state in run mode */ + type_func_t off_idle; /**< Enalbe/Disable off state in idle mode */ + timer_lock_level_t lock_level; /**< Lock level */ + uint32_t dead_time; /**< Dead time, [0x0, 0xFF] */ + type_func_t break_state; /**< Break state */ + timer_break_polarity_t polarity; /**< Break input polarity */ + type_func_t auto_out; /**< Enalbe/Disable automatic output */ +} timer_break_dead_time_t; + +/** + * @brief TIMER commutation event channel configuretion structure definition + */ +typedef struct +{ + type_func_t en; /**< Enalbe/Disable the channel */ + type_func_t n_en; /**< Enalbe/Disable the complementary channel */ + timer_oc_mode_t mode; /**< Mode of the channel */ +} timer_channel_config_t; + +/** + * @brief TIMER commutation event configuretion structure definition + */ +typedef struct +{ + timer_channel_config_t ch[3]; /**< Configure of channel */ +} timer_com_channel_config_t; + +/** + * @brief TIMER master mode selection + */ +typedef enum +{ + TIMER_TRGO_RESET = 0, /**< RESET */ + TIMER_TRGO_ENABLE = 1, /**< ENABLE */ + TIMER_TRGO_UPDATE = 2, /**< UPDATE */ + TIMER_TRGO_OC1 = 3, /**< OC1 */ + TIMER_TRGO_OC1REF = 4, /**< OC1REF */ + TIMER_TRGO_OC2REF = 5, /**< OC2REF */ + TIMER_TRGO_OC3REF = 6, /**< OC3REF */ + TIMER_TRGO_OC4REF = 7, /**< OC4REF */ +} timer_master_mode_sel_t; + +/** + * @brief TIMER master configuretion structure definition + */ +typedef struct +{ + timer_master_mode_sel_t sel; /**< Specifies the active edge of the input signal */ + type_func_t master_en; /**< Master/Slave mode selection */ +} timer_master_config_t; + +/** + * @brief Specifies the event source + */ +typedef enum +{ + TIMER_SRC_UPDATE = (1U << 0), /**< Event source is update */ + TIMER_SRC_CC1 = (1U << 1), /**< Event source is channel1 */ + TIMER_SRC_CC2 = (1U << 2), /**< Event source is channel2 */ + TIMER_SRC_CC3 = (1U << 3), /**< Event source is channel3 */ + TIMER_SRC_CC4 = (1U << 4), /**< Event source is channel4 */ + TIMER_SRC_COM = (1U << 5), /**< Event source is compare */ + TIMER_SRC_TRIG = (1U << 6), /**< Event source is trigger */ + TIMER_SRC_BREAK = (1U << 7), /**< Event source is break */ +} timer_event_source_t; + +/** + * @brief TIMER interrupt definition + */ +typedef enum +{ + TIMER_IT_UPDATE = (1U << 0), /**< Update interrupt bit */ + TIMER_IT_CC1 = (1U << 1), /**< Channel1 interrupt bit */ + TIMER_IT_CC2 = (1U << 2), /**< Channel2 interrupt bit */ + TIMER_IT_CC3 = (1U << 3), /**< Channel3 interrupt bit */ + TIMER_IT_CC4 = (1U << 4), /**< Channel4 interrupt bit */ + TIMER_IT_COM = (1U << 5), /**< compare interrupt bit */ + TIMER_IT_TRIGGER = (1U << 6), /**< Trigger interrupt bit */ + TIMER_IT_BREAK = (1U << 7), /**< Break interrupt bit */ +} timer_it_t; + +/** + * @brief TIMER DMA request + */ +typedef enum +{ + TIMER_DMA_UPDATE = (1U << 8), /**< DMA request from update */ + TIMER_DMA_CC1 = (1U << 9), /**< DMA request from channel1 */ + TIMER_DMA_CC2 = (1U << 10), /**< DMA request from channel2 */ + TIMER_DMA_CC3 = (1U << 11), /**< DMA request from channel3 */ + TIMER_DMA_CC4 = (1U << 12), /**< DMA request from channel4 */ + TIMER_DMA_COM = (1U << 13), /**< DMA request from compare */ + TIMER_DMA_TRIGGER = (1U << 14), /**< DMA request from trigger */ +} timer_dma_req_t; + +/** + * @brief TIMER flag definition + */ +typedef enum +{ + TIMER_FLAG_UPDATE = (1U << 0), /**< Update interrupt flag */ + TIMER_FLAG_CC1 = (1U << 1), /**< Channel1 interrupt flag */ + TIMER_FLAG_CC2 = (1U << 2), /**< Channel2 interrupt flag */ + TIMER_FLAG_CC3 = (1U << 3), /**< Channel3 interrupt flag */ + TIMER_FLAG_CC4 = (1U << 4), /**< Channel4 interrupt flag */ + TIMER_FLAG_COM = (1U << 5), /**< Compare interrupt flag */ + TIMER_FLAG_TRIGGER = (1U << 6), /**< Trigger interrupt flag */ + TIMER_FLAG_BREAK = (1U << 7), /**< Break interrupt flag */ + TIMER_FLAG_CC1OF = (1U << 9), /**< Channel1 override state flag */ + TIMER_FLAG_CC2OF = (1U << 10), /**< Channel2 override state flag */ + TIMER_FLAG_CC3OF = (1U << 11), /**< Channel3 override state flag */ + TIMER_FLAG_CC4OF = (1U << 12), /**< Channel4 override state flag */ +} timer_flag_t; +/** + * @} + */ + +/** @defgroup TIMER_Public_Macros TIMER Public Macros + * @{ + */ +#define CCER_CCxE_MASK ((1U << 0) | (1U << 4) | (1U << 8) | (1U << 12)) +#define CCER_CCxNE_MASK ((1U << 2) | (1U << 6) | (1U << 10)) + +/** + * @brief Reset TIMER handle state + */ +#define TIMER_RESET_HANDLE_STATE(hperh) ((hperh)->state = TIMER_STATE_RESET) + +/** + * @brief Enable the TIMER peripheral. + */ +#define TIMER_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK)) + +/** + * @brief Enable the TIMER main output. + */ +#define TIMER_MOE_ENABLE(hperh) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK)) + +/** + * @brief Disable the TIMER peripheral. + */ +#define TIMER_DISABLE(hperh) \ +do { \ + if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ +} while (0) + +/** + * @brief Disable the TIMER main output. + * @note The Main Output Enable of a timer instance is disabled only if + * all the CCx and CCxN channels have been disabled + */ +#define TIMER_MOE_DISABLE(hperh) \ +do { \ + if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ +} while (0) + +/** + * @brief Sets the TIMER autoreload register value on runtime without calling + * another time any Init function. + */ +#define TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \ +do { \ + (handle)->perh->AR = (AUTORELOAD); \ + (handle)->init.period = (AUTORELOAD); \ +} while (0) + +/** + * @brief Gets the TIMER autoreload register value on runtime + */ +#define TIMER_GET_AUTORELOAD(handle) ((handle)->perh->AR) + +/** + * @brief Gets the TIMER count register value on runtime + */ +#define TIMER_GET_CNT(handle) ((handle)->perh->COUNT) + +/** + * @brief Gets the TIMER count direction value on runtime + */ +#define TIMER_GET_DIR(handle) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS)) + +/** + * @brief CCx DMA request sent when CCx event occurs + */ +#define TIMER_CCx_DMA_REQ_CCx(handle) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) + +/** + * @brief CCx DMA request sent when update event occurs + */ +#define TIMER_CCx_DMA_REQ_UPDATE(handle) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) + +/** + * @brief Enable channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + * TIMER_CHANNEL_4 + */ +#define TIMER_CCx_ENABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ +(SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2)))))) + +/** + * @brief Disable channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + * TIMER_CHANNEL_4 + */ +#define TIMER_CCx_DISABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ +(CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2)))) + +/** + * @brief Enable complementary channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + */ +#define TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2))) + +/** + * @brief Disable complementary channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + */ +#define TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2))) +/** + * @} + */ + +/** @defgroup TIMER_Private_Macros TIMER Private Macros + * @{ + */ +#define IS_TIMER_INSTANCE(x) (((x) == TIMER0) || \ + ((x) == TIMER1) || \ + ((x) == TIMER2) || \ + ((x) == TIMER3) || \ + ((x) == TIMER4) || \ + ((x) == TIMER5) || \ + ((x) == TIMER6) || \ + ((x) == TIMER7)) +#define IS_ADTIMER_INSTANCE(x) ((x) == TIMER0) +#define IS_TIMER_XOR_INSTANCE(x) (((x) == TIMER0) || ((x) == TIMER6)) +#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == TIMER0) || \ + ((x) == TIMER2) || \ + ((x) == TIMER3)) +#define IS_TIMER_CC2_INSTANCE(x) (((x) == TIMER0) || \ + ((x) == TIMER2) || \ + ((x) == TIMER3) || \ + ((x) == TIMER6)) +#define IS_TIMER_CC4_INSTANCE(x) (((x) == TIMER0) || \ + ((x) == TIMER6)) +#define IS_TIMER_BREAK_INSTANCE(x) (((x) == TIMER0) || \ + ((x) == TIMER2) || \ + ((x) == TIMER3)) +#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == TIMER0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == TIMER2) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == TIMER3) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == TIMER6) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2)))) +#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == TIMER0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == TIMER2) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == TIMER3) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == TIMER6) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4)))) +#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == TIMER0) || \ + ((x) == TIMER2) || \ + ((x) == TIMER3)) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) +#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == TIMER0) || \ + ((x) == TIMER2) || \ + ((x) == TIMER3)) +#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) +#define IS_TIMER_COUNTER_MODE(x) (((x) == TIMER_CNT_MODE_UP) || \ + ((x) == TIMER_CNT_MODE_DOWN) || \ + ((x) == TIMER_CNT_MODE_CENTER1) || \ + ((x) == TIMER_CNT_MODE_CENTER2) || \ + ((x) == TIMER_CNT_MODE_CENTER3)) +#define IS_TIMER_CLOCK_DIVISION(x) (((x) == TIMER_CLOCK_DIV1) || \ + ((x) == TIMER_CLOCK_DIV2) || \ + ((x) == TIMER_CLOCK_DIV4)) +#define IS_TIMER_PWM_MODE(x) (((x) == TIMER_OC_MODE_PWM1) || \ + ((x) == TIMER_OC_MODE_PWM2)) +#define IS_TIMER_OC_MODE(x) (((x) == TIMER_OC_MODE_TIMERING) || \ + ((x) == TIMER_OC_MODE_ACTIVE) || \ + ((x) == TIMER_OC_MODE_INACTIVE) || \ + ((x) == TIMER_OC_MODE_TOGGLE) || \ + ((x) == TIMER_OC_MODE_FORCE_ACTIVE) || \ + ((x) == TIMER_OC_MODE_FORCE_INACTIVE) || \ + ((x) == TIMER_OC_MODE_PWM1) || \ + ((x) == TIMER_OC_MODE_PWM2)) +#define IS_TIMER_OC_POLARITY(x) (((x) == TIMER_OC_POLARITY_HIGH) || \ + ((x) == TIMER_OC_POLARITY_LOW)) +#define IS_TIMER_OCN_POLARITY(x) (((x) == TIMER_OCN_POLARITY_HIGH) || \ + ((x) == TIMER_OCN_POLARITY_LOW)) +#define IS_TIMER_OCIDLE_STATE(x) (((x) == TIMER_OC_IDLE_RESET) || \ + ((x) == TIMER_OC_IDLE_SET)) +#define IS_TIMER_OCNIDLE_STATE(x) (((x) == TIMER_OCN_IDLE_RESET) || \ + ((x) == TIMER_OCN_IDLE_SET)) +#define IS_TIMER_CHANNELS(x) (((x) == TIMER_CHANNEL_1) || \ + ((x) == TIMER_CHANNEL_2) || \ + ((x) == TIMER_CHANNEL_3) || \ + ((x) == TIMER_CHANNEL_4) || \ + ((x) == TIMER_CHANNEL_ALL)) +#define IS_TIMER_OP_MODE(x) (((x) == TIMER_OP_MODE_REPEAT) || \ + ((x) == TIMER_OP_MODE_SINGLE)) +#define IS_TIMER_OP_OUTPUT_CH(x) (((x) == TIMER_OP_OUTPUT_CHANNEL_1) || \ + ((x) == TIMER_OP_OUTPUT_CHANNEL_2)) +#define IS_TIMER_ENCODER_MODE(x) (((x) == TIMER_ENC_MODE_TI1) || \ + ((x) == TIMER_ENC_MODE_TI2) || \ + ((x) == TIMER_ENC_MODE_TI12)) +#define IS_TIMER_IC_POLARITY(x) (((x) == TIMER_IC_POLARITY_RISE) || \ + ((x) == TIMER_IC_POLARITY_FALL) || \ + ((x) == TIMER_IC_POLARITY_BOTH)) +#define IS_TIMER_IC_SELECT(x) (((x) == TIMER_IC_SEL_DIRECT) || \ + ((x) == TIMER_IC_SEL_INDIRECT) || \ + ((x) == TIMER_IC_SEL_TRC)) +#define IS_TIMER_IC_PSC(x) (((x) == TIMER_IC_PSC_DIV1) || \ + ((x) == TIMER_IC_PSC_DIV2) || \ + ((x) == TIMER_IC_PSC_DIV4) || \ + ((x) == TIMER_IC_PSC_DIV8)) +#define IS_TIMER_IC_FILTER(x) ((x) <= 0xF) +#define IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF) +#define IS_TIMER_CLEAR_INPUT_SOURCE(x) (((x) == TIMER_INPUT_NONE) || \ + ((x) == TIMER_INPUT_ETR)) +#define IS_TIMER_CLEAR_INPUT_POLARITY(x) (((x) == TIMER_POLARITY_NO_INV) || \ + ((x) == TIMER_POLARITY_INV)) +#define IS_TIMER_ETR_PSC(x) (((x) == TIMER_ETR_PSC_DIV1) || \ + ((x) == TIMER_ETR_PSC_DIV2) || \ + ((x) == TIMER_ETR_PSC_DIV4) || \ + ((x) == TIMER_ETR_PSC_DIV8)) +#define IS_TIMER_CLOCK_SOURCE(x) (((x) == TIMER_SRC_ETRMODE2) || \ + ((x) == TIMER_SRC_INTER) || \ + ((x) == TIMER_SRC_ITR0) || \ + ((x) == TIMER_SRC_ITR1) || \ + ((x) == TIMER_SRC_ITR2) || \ + ((x) == TIMER_SRC_ITR3) || \ + ((x) == TIMER_SRC_TI1ED) || \ + ((x) == TIMER_SRC_TI1) || \ + ((x) == TIMER_SRC_TI2) || \ + ((x) == TIMER_SRC_ETRMODE1)) +#define IS_TIMER_CLOCK_POLARITY(x) (((x) == TIMER_CLK_POLARITY_INV) || \ + ((x) == TIMER_CLK_POLARITY_NO_INV) || \ + ((x) == TIMER_CLK_POLARITY_RISE) || \ + ((x) == TIMER_CLK_POLARITY_FALL) || \ + ((x) == TIMER_CLK_POLARITY_BOTH)) +#define IS_TIMER_SLAVE_MODE(x) (((x) == TIMER_MODE_DISABLE) || \ + ((x) == TIMER_MODE_ENC1) || \ + ((x) == TIMER_MODE_ENC2) || \ + ((x) == TIMER_MODE_ENC3) || \ + ((x) == TIMER_MODE_RESET) || \ + ((x) == TIMER_MODE_GATED) || \ + ((x) == TIMER_MODE_TRIG) || \ + ((x) == TIMER_MODE_EXTERNAL1)) +#define IS_TIMER_EVENT_SOURCE(x) (((x) == TIMER_SRC_UPDATE) || \ + ((x) == TIMER_SRC_CC1) || \ + ((x) == TIMER_SRC_CC2) || \ + ((x) == TIMER_SRC_CC3) || \ + ((x) == TIMER_SRC_CC4) || \ + ((x) == TIMER_SRC_COM) || \ + ((x) == TIMER_SRC_TRIG) || \ + ((x) == TIMER_SRC_BREAK)) +#define IS_TIMER_TS(x) (((x) == TIMER_TS_ITR0) || \ + ((x) == TIMER_TS_ITR1) || \ + ((x) == TIMER_TS_ITR2) || \ + ((x) == TIMER_TS_ITR3) || \ + ((x) == TIMER_TS_TI1F_ED) || \ + ((x) == TIMER_TS_TI1FP1) || \ + ((x) == TIMER_TS_TI2FP2) || \ + ((x) == TIMER_TS_ETRF)) +#define IS_TIMER_CLOCK_LEVEL(x) (((x) == TIMER_LOCK_LEVEL_OFF) || \ + ((x) == TIMER_LOCK_LEVEL_1) || \ + ((x) == TIMER_LOCK_LEVEL_2) || \ + ((x) == TIMER_LOCK_LEVEL_3)) +#define IS_TIMER_BREAK_POLARITY(x) (((x) == TIMER_BREAK_POLARITY_LOW) || \ + ((x) == TIMER_BREAK_POLARITY_HIGH)) +#define IS_TIMER_MASTER_MODE_SEL(x) (((x) == TIMER_TRGO_RESET) || \ + ((x) == TIMER_TRGO_ENABLE) || \ + ((x) == TIMER_TRGO_UPDATE) || \ + ((x) == TIMER_TRGO_OC1) || \ + ((x) == TIMER_TRGO_OC1REF) || \ + ((x) == TIMER_TRGO_OC2REF) || \ + ((x) == TIMER_TRGO_OC3REF) || \ + ((x) == TIMER_TRGO_OC4REF)) +#define IS_TIMER_IT(x) (((x) == TIMER_IT_UPDATE) || \ + ((x) == TIMER_IT_CC1) || \ + ((x) == TIMER_IT_CC2) || \ + ((x) == TIMER_IT_CC3) || \ + ((x) == TIMER_IT_CC4) || \ + ((x) == TIMER_IT_COM) || \ + ((x) == TIMER_IT_TRIGGER) || \ + ((x) == TIMER_IT_BREAK)) +#define IS_TIMER_DMA_REQ(x) (((x) == TIMER_DMA_UPDATE) || \ + ((x) == TIMER_DMA_CC1) || \ + ((x) == TIMER_DMA_CC2) || \ + ((x) == TIMER_DMA_CC3) || \ + ((x) == TIMER_DMA_CC4) || \ + ((x) == TIMER_DMA_COM) || \ + ((x) == TIMER_DMA_TRIGGER)) +#define IS_TIMER_FLAG(x) (((x) == TIMER_FLAG_UPDATE) || \ + ((x) == TIMER_FLAG_CC1) || \ + ((x) == TIMER_FLAG_CC2) || \ + ((x) == TIMER_FLAG_CC3) || \ + ((x) == TIMER_FLAG_CC4) || \ + ((x) == TIMER_FLAG_COM) || \ + ((x) == TIMER_FLAG_TRIGGER) || \ + ((x) == TIMER_FLAG_BREAK) || \ + ((x) == TIMER_FLAG_CC1OF) || \ + ((x) == TIMER_FLAG_CC2OF) || \ + ((x) == TIMER_FLAG_CC3OF) || \ + ((x) == TIMER_FLAG_CC4OF)) +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions + * @{ + */ +/** @addtogroup TIMER_Public_Functions_Group1 + * @{ + */ +/* Time Base functions */ +ald_status_t timer_base_init(timer_handle_t *hperh); +void timer_base_reset(timer_handle_t *hperh); +void timer_base_start(timer_handle_t *hperh); +void timer_base_stop(timer_handle_t *hperh); +void timer_base_start_by_it(timer_handle_t *hperh); +void timer_base_stop_by_it(timer_handle_t *hperh); +#ifdef ALD_DMA +ald_status_t timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void timer_base_stop_by_dma(timer_handle_t *hperh); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group2 + * @{ + */ +/* Timer Output Compare functions */ +ald_status_t timer_oc_init(timer_handle_t *hperh); +void timer_oc_start(timer_handle_t *hperh, timer_channel_t ch); +void timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch); +void timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group3 + * @{ + */ +/* Timer PWM functions */ +ald_status_t timer_pwm_init(timer_handle_t *hperh); +void timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch); +void timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch); +void timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +void timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq); +void timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty); +void timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group4 + * @{ + */ +/* Timer Input Capture functions */ +ald_status_t timer_ic_init(timer_handle_t *hperh); +void timer_ic_start(timer_handle_t *hperh, timer_channel_t ch); +void timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch); +void timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group5 + * @{ + */ +/* Timer One Pulse functions */ +ald_status_t timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode); +void timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch); +void timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch); +void timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); +void timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group6 + * @{ + */ +/* Timer encoder functions */ +ald_status_t timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config); +void timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch); +void timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch); +void timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, + uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2); +void timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group7 + * @{ + */ +/* Timer hall sensor functions */ +ald_status_t timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config); +void timer_hall_sensor_start(timer_handle_t *hperh); +void timer_hall_sensor_stop(timer_handle_t *hperh); +void timer_hall_sensor_start_by_it(timer_handle_t *hperh); +void timer_hall_sensor_stop_by_it(timer_handle_t *hperh); +#ifdef ALD_DMA +ald_status_t timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void timer_hall_sensor_stop_by_dma(timer_handle_t *hperh); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group8 + * @{ + */ +/* Timer complementary output compare functions */ +void timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch); +void timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch); +void timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group9 + * @{ + */ +/* Timer complementary PWM functions */ +void timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch); +void timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch); +void timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group10 + * @{ + */ +/* Timer complementary one pulse functions */ +void timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch); +void timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch); +void timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group11 + * @{ + */ +/* Control functions */ +ald_status_t timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch); +ald_status_t timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch); +ald_status_t timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, + timer_channel_t ch_out, timer_channel_t ch_in); +ald_status_t timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch); +ald_status_t timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config); +ald_status_t timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select); +ald_status_t timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config); +ald_status_t timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config); +ald_status_t timer_generate_event(timer_handle_t *hperh, timer_event_source_t event); +uint32_t timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch); +void timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch); +void timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config); +void timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); +void timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); +void timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config); +void timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config); +void timer_irq_handle(timer_handle_t *hperh); +void timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state); +void timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state); +it_status_t timer_get_it_status(timer_handle_t *hperh, timer_it_t it); +flag_status_t timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag); +void timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group12 + * @{ + */ +/* State functions */ +timer_state_t timer_get_state(timer_handle_t *hperh); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_TIMER_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h new file mode 100644 index 0000000000..072f892184 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h @@ -0,0 +1,182 @@ +/** + ********************************************************************************* + * + * @file ald_trng.h + * @brief Header file of TRNG module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_TRNG_H__ +#define __ALD_TRNG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup TRNG + * @{ + */ + +/** @defgroup TRNG_Public_Macros TRNG Public Macros + * @{ + */ +#define TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) +#define TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) +#define TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) +#define TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) +/** + * @} + */ + +/** @defgroup TRNG_Public_Types TRNG Public Types + * @{ + */ +/** + * @brief Data width + */ +typedef enum +{ + TRNG_DSEL_1B = 0x0, /**< 1-bit */ + TRNG_DSEL_8B = 0x1, /**< 8-bit */ + TRNG_DSEL_16B = 0x2, /**< 16-bit */ + TRNG_DSEL_32B = 0x3, /**< 32-bit */ +} trng_data_width_t; + +/** + * @brief seed type + */ +typedef enum +{ + TRNG_SEED_TYPE_0 = 0x0, /**< Using 0 as seed */ + TRNG_SEED_TYPE_1 = 0x1, /**< Using 1 as seed */ + TRNG_SEED_TYPE_LAST = 0x2, /**< Using last seed */ + TRNG_SEED_TYPE_SEED = 0x3, /**< Using value of register */ +} trng_seed_type_t; + +/** + * @brief TRNG init structure definition + */ +typedef struct +{ + trng_data_width_t data_width; /**< The width of data */ + trng_seed_type_t seed_type; /**< The seed type */ + uint32_t seed; /**< The value of seed */ + uint16_t t_start; /**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */ + uint8_t adjc; /**< Adjust parameter */ + uint8_t posten; +} trng_init_t; + +/** + * @brief State type + */ +typedef enum +{ + TRNG_STATUS_START = (1U << 0), /**< Start state */ + TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */ + TRNG_STATUS_SERR = (1U << 2), /**< Error state */ +} trng_status_t; + +/** + * @brief Interrupt type + */ +typedef enum +{ + TRNG_IT_START = (1U << 0), /**< Start */ + TRNG_IT_DAVLD = (1U << 1), /**< Data valid */ + TRNG_IT_SERR = (1U << 2), /**< Error */ +} trng_it_t; + +/** + * @brief Interrupt flag type + */ +typedef enum +{ + TRNG_IF_START = (1U << 0), /**< Start */ + TRNG_IF_DAVLD = (1U << 1), /**< Data valid */ + TRNG_IF_SERR = (1U << 2), /**< Error */ +} trng_flag_t; +/** + * @} + */ + +/** + * @defgroup TRNG_Private_Macros TRNG Private Macros + * @{ + */ +#define IS_TRNG_DATA_WIDTH(x) (((x) == TRNG_DSEL_1B) || \ + ((x) == TRNG_DSEL_8B) || \ + ((x) == TRNG_DSEL_16B) || \ + ((x) == TRNG_DSEL_32B)) +#define IS_TRNG_SEED_TYPE(x) (((x) == TRNG_SEED_TYPE_0) || \ + ((x) == TRNG_SEED_TYPE_1) || \ + ((x) == TRNG_SEED_TYPE_LAST) || \ + ((x) == TRNG_SEED_TYPE_SEED)) +#define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \ + ((x) == TRNG_STATUS_DAVLD) || \ + ((x) == TRNG_STATUS_SERR)) +#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \ + ((x) == TRNG_IT_DAVLD) || \ + ((x) == TRNG_IT_SERR)) +#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \ + ((x) == TRNG_IF_DAVLD) || \ + ((x) == TRNG_IF_SERR)) +#define IS_TRNG_ADJC(x) ((x) < 4) +/** + * @} + */ + +/** @addtogroup TRNG_Public_Functions + * @{ + */ +/** @addtogroup TRNG_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern void trng_init(trng_init_t *init); +/** + * @} + */ +/** @addtogroup TRNG_Public_Functions_Group2 + * @{ + */ +/* Control functions */ +extern uint32_t trng_get_result(void); +extern void trng_interrupt_config(trng_it_t it, type_func_t state); +extern flag_status_t trng_get_status(trng_status_t status); +extern it_status_t trng_get_it_status(trng_it_t it); +extern flag_status_t trng_get_flag_status(trng_flag_t flag); +extern void trng_clear_flag_status(trng_flag_t flag); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_TRNG_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h new file mode 100644 index 0000000000..0d8b189931 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h @@ -0,0 +1,478 @@ +/** + ********************************************************************************* + * + * @file ald_uart.h + * @brief Header file of UART module library. + * + * @version V1.0 + * @date 21 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_UART_H__ +#define __ALD_UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** + * @defgroup UART_Public_Macros UART Public Macros + * @{ + */ +#define UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK)) +#define UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK)) +#define UART_BRR_WRITE_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK)) +#define UART_BRR_WRITE_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK)) +#define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK)) +#define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK)) +#define UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK)) +#define UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK)) +#define UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK)) +#define UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK)) +#define UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK)) +#define UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK)) +#define UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK)) +#define UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK)) +#define UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK)) +#define UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK)) +#define UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK)) +#define UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK)) +#define UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_TFRST_MSK)) +#define UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_RFRST_MSK)) +#define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK)) +#define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK)) +#define UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK)) +#define UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK)) +#define UART_AUTOBR_RESTART(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABRRS_MSK)) +#define UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR)) +#define UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS)) +/** + * @} + */ + +/** @defgroup UART_Public_Types UART Public Types + * @{ + */ +/** + * @brief UART word length + */ +typedef enum +{ + UART_WORD_LENGTH_5B = 0x0, /**< 5-bits */ + UART_WORD_LENGTH_6B = 0x1, /**< 6-bits */ + UART_WORD_LENGTH_7B = 0x2, /**< 7-bits */ + UART_WORD_LENGTH_8B = 0x3, /**< 8-bits */ +} uart_word_length_t; + +/** + * @brief UART stop bits + */ +typedef enum +{ + UART_STOP_BITS_1 = 0x0, /**< 1-bits */ + UART_STOP_BITS_2 = 0x1, /**< 2-bits */ + UART_STOP_BITS_0_5 = 0x0, /**< 0.5-bits, using smartcard mode */ + UART_STOP_BITS_1_5 = 0x1, /**< 1.5-bits, using smartcard mode */ +} uart_stop_bits_t; + +/** + * @brief UART parity + */ +typedef enum +{ + UART_PARITY_NONE = 0x0, /**< Not parity */ + UART_PARITY_ODD = 0x1, /**< Odd parity */ + UART_PARITY_EVEN = 0x3, /**< Even parity */ +} uart_parity_t; + +/** + * @brief UART mode + */ +typedef enum +{ + UART_MODE_UART = 0x0, /**< UART */ + UART_MODE_LIN = 0x1, /**< LIN */ + UART_MODE_IrDA = 0x2, /**< IrDA */ + UART_MODE_RS485 = 0x3, /**< RS485 */ + UART_MODE_HDSEL = 0x4, /**< Single-wire half-duplex */ +} uart_mode_t; + +/** + * @brief UART hardware flow control + */ +typedef enum +{ + UART_HW_FLOW_CTL_DISABLE = 0x0, /**< Auto-flow-control disable */ + UART_HW_FLOW_CTL_ENABLE = 0x1, /**< Auto-flow-control enable */ +} uart_hw_flow_ctl_t; + +/** + * @brief ALD UART state + */ +typedef enum +{ + UART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + UART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + UART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + UART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ + UART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ + UART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ + UART_STATE_TIMEOUT = 0x03, /**< Timeout state */ + UART_STATE_ERROR = 0x04, /**< Error */ +} uart_state_t; + +/** + * @brief UART error codes + */ +typedef enum +{ + UART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ + UART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ + UART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ + UART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ + UART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ + UART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +} uart_error_t; + +/** + * @brief UART init structure definition + */ +typedef struct +{ + uint32_t baud; /**< Specifies the uart communication baud rate */ + uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ + uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ + uart_parity_t parity; /**< Specifies the parity mode */ + uart_mode_t mode; /**< Specifies uart mode */ + uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ +} uart_init_t; + +/** + * @brief UART handle structure definition + */ +typedef struct uart_handle_s +{ + UART_TypeDef *perh; /**< UART registers base address */ + uart_init_t init; /**< UART communication parameters */ + uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */ + uint16_t tx_size; /**< UART Tx Transfer size */ + uint16_t tx_count; /**< UART Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */ + uint16_t rx_size; /**< UART Rx Transfer size */ + uint16_t rx_count; /**< UART Rx Transfer Counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */ + dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + uart_state_t state; /**< UART communication state */ + uart_error_t err_code; /**< UART Error code */ + + void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */ +} uart_handle_t; + +/** + * @brief UART RS485 configure structure definition + */ +typedef struct +{ + type_func_t normal; /**< Normal mode */ + type_func_t dir; /**< Auto-direction mode */ + type_func_t invert; /**< Address detection invert */ + uint8_t addr; /**< Address for compare */ +} uart_rs485_config_t; + +/** + * @brief LIN detection break length + */ +typedef enum +{ + LIN_BREAK_LEN_10B = 0x0, /**< 10-bit break */ + LIN_BREAK_LEN_11B = 0x1, /**< 11-bit break */ +} uart_lin_break_len_t; + +/** + * @brief UART TXFIFO size + */ +typedef enum +{ + UART_TXFIFO_EMPTY = 0x0, /**< Empty */ + UART_TXFIFO_2BYTE = 0x1, /**< 2-Bytes */ + UART_TXFIFO_4BYTE = 0x2, /**< 4-Bytes */ + UART_TXFIFO_8BYTE = 0x3, /**< 8-Bytes */ +} uart_txfifo_t; + +/** + * @brief UART RXFIFO size + */ +typedef enum +{ + UART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */ + UART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */ + UART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */ + UART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */ +} uart_rxfifo_t; + +/** + * @brief UART auto-baud mode + */ +typedef enum +{ + UART_ABRMOD_1_TO_0 = 0x0, /**< Detect bit0:1, bit1:0 */ + UART_ABRMOD_1 = 0x1, /**< Detect bit0:1 */ + UART_ABRMOD_0_TO_1 = 0x2, /**< Detect bit0:0, bit1:1 */ +} uart_auto_baud_mode_t; + +/** + * @brief UART status types + */ +typedef enum +{ + UART_STATUS_DR = (1U << 0), /**< Data ready */ + UART_STATUS_OE = (1U << 1), /**< Overrun error */ + UART_STATUS_PE = (1U << 2), /**< Parity error */ + UART_STATUS_FE = (1U << 3), /**< Framing error */ + UART_STATUS_BI = (1U << 4), /**< Break interrupt */ + UART_STATUS_TBEM = (1U << 5), /**< Transmit buffer empty */ + UART_STATUS_TEM = (1U << 6), /**< Transmitter empty */ + UART_STATUS_RFE = (1U << 7), /**< Reveiver FIFO data error */ + UART_STATUS_BUSY = (1U << 8), /**< UART busy */ + UART_STATUS_TFNF = (1U << 9), /**< Transmit FIFO not full */ + UART_STATUS_TFEM = (1U << 10), /**< Transmit FIFO not empty */ + UART_STATUS_RFNE = (1U << 11), /**< Receive FIFO not empty */ + UART_STATUS_RFF = (1U << 12), /**< Receive FIFO full */ + UART_STATUS_DCTS = (1U << 14), /**< Delta clear to send */ + UART_STATUS_CTS = (1U << 15), /**< Clear to send */ +} uart_status_t; + +/** + * @brief UART interrupt types + */ +typedef enum +{ + UART_IT_RXRD = (1U << 0), /**< Receive data available */ + UART_IT_TXS = (1U << 1), /**< Tx empty status */ + UART_IT_RXS = (1U << 2), /**< Rx line status */ + UART_IT_MDS = (1U << 3), /**< Modem status */ + UART_IT_RTO = (1U << 4), /**< Receiver timeout */ + UART_IT_BZ = (1U << 5), /**< Busy status */ + UART_IT_ABE = (1U << 6), /**< Auto-baud rate detection end */ + UART_IT_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ + UART_IT_LINBK = (1U << 8), /**< Lin break detection */ + UART_IT_TC = (1U << 9), /**< Transmission complete */ + UART_IT_EOB = (1U << 10), /**< End of block */ + UART_IT_CM = (1U << 11), /**< Character match */ +} uart_it_t; + +/** + * @brief UART flags types + */ +typedef enum +{ + UART_IF_RXRD = (1U << 0), /**< Receive data available */ + UART_IF_TXS = (1U << 1), /**< Tx empty status */ + UART_IF_RXS = (1U << 2), /**< Rx line status */ + UART_IF_MDS = (1U << 3), /**< Modem status */ + UART_IF_RTO = (1U << 4), /**< Receiver timeout */ + UART_IF_BZ = (1U << 5), /**< Busy status */ + UART_IF_ABE = (1U << 6), /**< Auto-baud rate detection end */ + UART_IF_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ + UART_IF_LINBK = (1U << 8), /**< Lin break detection */ + UART_IF_TC = (1U << 9), /**< Transmission complete */ + UART_IF_EOB = (1U << 10), /**< End of block */ + UART_IF_CM = (1U << 11), /**< Character match */ +} uart_flag_t; +/** + * @} + */ + +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +#define IS_UART_ALL(x) (((x) == UART0) || \ + ((x) == UART1) || \ + ((x) == UART2) || \ + ((x) == UART3)) +#define IS_UART_WORD_LENGTH(x) (((x) == UART_WORD_LENGTH_5B) || \ + ((x) == UART_WORD_LENGTH_6B) || \ + ((x) == UART_WORD_LENGTH_7B) || \ + ((x) == UART_WORD_LENGTH_8B)) +#define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \ + ((x) == UART_STOP_BITS_2) || \ + ((x) == UART_STOP_BITS_0_5) || \ + ((x) == UART_STOP_BITS_1_5)) +#define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \ + ((x) == UART_PARITY_ODD) || \ + ((x) == UART_PARITY_EVEN)) +#define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \ + ((x) == UART_MODE_LIN) || \ + ((x) == UART_MODE_IrDA) || \ + ((x) == UART_MODE_RS485) || \ + ((x) == UART_MODE_HDSEL)) +#define IS_UART_HARDWARE_FLOW_CONTROL(x) \ + (((x) == UART_HW_FLOW_CTL_DISABLE) || \ + ((x) == UART_HW_FLOW_CTL_ENABLE)) +#define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \ + ((x) == LIN_BREAK_LEN_11B)) +#define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \ + ((x) == UART_TXFIFO_2BYTE) || \ + ((x) == UART_TXFIFO_4BYTE) || \ + ((x) == UART_TXFIFO_8BYTE)) +#define IS_UART_RXFIFO_TYPE(x) (((x) == UART_RXFIFO_1BYTE) || \ + ((x) == UART_RXFIFO_4BYTE) || \ + ((x) == UART_RXFIFO_8BYTE) || \ + ((x) == UART_RXFIFO_14BYTE)) +#define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \ + ((x) == UART_ABRMOD_1) || \ + ((x) == UART_ABRMOD_0_TO_1)) +#define IS_UART_STATUS(x) (((x) == UART_STATUS_DR) || \ + ((x) == UART_STATUS_OE) || \ + ((x) == UART_STATUS_PE) || \ + ((x) == UART_STATUS_FE) || \ + ((x) == UART_STATUS_BI) || \ + ((x) == UART_STATUS_TBEM) || \ + ((x) == UART_STATUS_TEM) || \ + ((x) == UART_STATUS_RFE) || \ + ((x) == UART_STATUS_BUSY) || \ + ((x) == UART_STATUS_TFNF) || \ + ((x) == UART_STATUS_TFEM) || \ + ((x) == UART_STATUS_RFNE) || \ + ((x) == UART_STATUS_RFF) || \ + ((x) == UART_STATUS_DCTS) || \ + ((x) == UART_STATUS_CTS)) +#define IS_UART_IT(x) (((x) == UART_IT_RXRD) || \ + ((x) == UART_IT_TXS) || \ + ((x) == UART_IT_RXS) || \ + ((x) == UART_IT_MDS) || \ + ((x) == UART_IT_RTO) || \ + ((x) == UART_IT_BZ) || \ + ((x) == UART_IT_ABE) || \ + ((x) == UART_IT_ABTO) || \ + ((x) == UART_IT_LINBK) || \ + ((x) == UART_IT_TC) || \ + ((x) == UART_IT_EOB) || \ + ((x) == UART_IT_CM)) +#define IS_UART_IF(x) (((x) == UART_IF_RXRD) || \ + ((x) == UART_IF_TXS) || \ + ((x) == UART_IF_RXS) || \ + ((x) == UART_IF_MDS) || \ + ((x) == UART_IF_RTO) || \ + ((x) == UART_IF_BZ) || \ + ((x) == UART_IF_ABE) || \ + ((x) == UART_IF_ABTO) || \ + ((x) == UART_IF_LINBK) || \ + ((x) == UART_IF_TC) || \ + ((x) == UART_IF_EOB) || \ + ((x) == UART_IF_CM)) +#define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21)) +#define IS_UART_DATA(x) ((x) <= 0x1FF) + +#define UART_STATE_TX_MASK (1U << 4) +#define UART_STATE_RX_MASK (1U << 5) +/** + * @} + */ + +/** @addtogroup UART_Public_Functions + * @{ + */ + +/** @addtogroup UART_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void uart_init(uart_handle_t *hperh); +void uart_reset(uart_handle_t *hperh); +void uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); +#ifdef ALD_DMA +ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t uart_dma_pause(uart_handle_t *hperh); +ald_status_t uart_dma_resume(uart_handle_t *hperh); +ald_status_t uart_dma_stop(uart_handle_t *hperh); +#endif +void uart_irq_handle(uart_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group3 + * @{ + */ +/* Peripheral Control functions */ +void uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state); +void uart_dma_req_config(uart_handle_t *hperh, type_func_t state); +void uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); +void uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); +void uart_lin_send_break(uart_handle_t *hperh); +void uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len); +void uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode); +ald_status_t uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout); +it_status_t uart_get_it_status(uart_handle_t *hperh, uart_it_t it); +flag_status_t uart_get_status(uart_handle_t *hperh, uart_status_t status); +flag_status_t uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag); +flag_status_t uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag); +void uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group4 + * @{ + */ +/* Peripheral State and Errors functions */ +uart_state_t uart_get_state(uart_handle_t *hperh); +uint32_t uart_get_error(uart_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_UART_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h new file mode 100644 index 0000000000..07aac584f1 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h @@ -0,0 +1,580 @@ +/** + ********************************************************************************* + * + * @file ald_usart.h + * @brief Header file of USART module library. + * + * @version V1.0 + * @date 16 Apr 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_USART_H__ +#define __ALD_USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/** @defgroup USART_Public_Types USART Public Types + * @{ + */ + +/** + * @brief usart_word_length + */ +typedef enum +{ + USART_WORD_LENGTH_8B = 0x0, /**< Word length is 8-bits */ + USART_WORD_LENGTH_9B = 0x1, /**< Word length is 9-bits */ +} usart_word_length_t; + +/** + * @brief usart_stop_bits + */ +typedef enum +{ + USART_STOP_BITS_1 = 0x0, /**< Stop bits is 1-bits */ + USART_STOP_BITS_0_5 = 0x1, /**< Stop bits is 0.5-bits */ + USART_STOP_BITS_2 = 0x2, /**< Stop bits is 2-bits */ + USART_STOP_BITS_1_5 = 0x3, /**< Stop bits is 1.5-bits */ +} usart_stop_bits_t; + +/** + * @brief usart_parity + */ +typedef enum +{ + USART_PARITY_NONE = 0x0, /**< Not parity */ + USART_PARITY_EVEN = 0x2, /**< Even parity */ + USART_PARITY_ODD = 0x3, /**< Odd parity */ +} usart_parity_t; + +/** + * @brief usart_mode + */ +typedef enum +{ + USART_MODE_RX = 0x1, /**< TX mode */ + USART_MODE_TX = 0x2, /**< RX mode */ + USART_MODE_TX_RX = 0x3, /**< TX & RX mode */ +} usart_mode_t; + +/** + * @brief usart_hardware_flow_control + */ +typedef enum +{ + USART_HW_FLOW_CTL_NONE = 0x0, /**< Not flow control */ + USART_HW_FLOW_CTL_RTS = 0x1, /**< RTS flow control */ + USART_HW_FLOW_CTL_CTS = 0x2, /**< CTS flow control */ + USART_HW_FLOW_CTL_RTS_CTS = 0x3, /**< RTS & CTS flow control */ +} usart_hw_flow_ctl_t; + +/** + * @brief usart_clock + */ +typedef enum +{ + USART_CLOCK_DISABLE = 0x0, /**< Disable clock output */ + USART_CLOCK_ENABLE = 0x1, /**< Enable clock output */ +} usart_clock_t; + +/** + * @brief usart_clock_polarity + */ +typedef enum +{ + USART_CPOL_LOW = 0x0, /**< Clock polarity low */ + USART_CPOL_HIGH = 0x1, /**< Clock polarity high */ +} usart_cpol_t; + +/** + * @brief usart_clock_phase + */ +typedef enum +{ + USART_CPHA_1EDGE = 0x0, /**< Clock phase first edge */ + USART_CPHA_2EDGE = 0x1, /**< Clock phase second edge */ +} usart_cpha_t; + +/** + * @brief usart_last_bit + */ +typedef enum +{ + USART_LAST_BIT_DISABLE = 0x0, /**< Disable last bit clock output */ + USART_LAST_BIT_ENABLE = 0x1, /**< Enable last bit clock output */ +} usart_last_bit_t; + +/** + * @brief usart state structures definition + */ +typedef enum +{ + USART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + USART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + USART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + USART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ + USART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ + USART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ + USART_STATE_TIMEOUT = 0x03, /**< Timeout state */ + USART_STATE_ERROR = 0x04, /**< Error */ +} usart_state_t; + +/** + * @brief usart error codes + */ +typedef enum +{ + USART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ + USART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ + USART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ + USART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ + USART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ + USART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +} usart_error_t; + + +/** + * @brief usart init structure definition + */ +typedef struct +{ + uint32_t baud; /**< This member configures the Usart communication baud rate. */ + usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ + usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ + usart_parity_t parity; /**< Specifies the parity mode. + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + usart_mode_t mode; /**< Specifies wether the Receive or Transmit mode is enabled or disabled. */ + usart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled. */ + type_func_t over_sampling; /**< Specifies whether the Over sampling 8 is enabled or disabled. */ +} usart_init_t; + +/** + * @brief USART handle structure definition + */ +typedef struct usart_handle_s +{ + USART_TypeDef *perh; /**< USART registers base address */ + usart_init_t init; /**< USART communication parameters */ + uint8_t *tx_buf; /**< Pointer to USART Tx transfer buffer */ + uint16_t tx_size; /**< USART Tx transfer size */ + uint16_t tx_count; /**< USART Tx transfer counter */ + uint8_t *rx_buf; /**< Pointer to USART Rx transfer buffer */ + uint16_t rx_size; /**< USART Rx Transfer size */ + uint16_t rx_count; /**< USART Rx Transfer Counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< USART Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< USART Rx DMA handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + usart_state_t state; /**< USART communication state */ + uint32_t err_code; /**< USART error code */ + + void (*tx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct usart_handle_s *arg); /**< Rx completed callback */ + void (*tx_rx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx & Rx completed callback */ + void (*error_cbk)(struct usart_handle_s *arg); /**< error callback */ +} usart_handle_t; + + +/** + * @brief USART clock init structure definition + */ +typedef struct +{ + usart_clock_t clk; /**< Pecifies whether the USART clock is enable or disable. */ + usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ + usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made. */ + usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. */ +} usart_clock_init_t; + + +/** + * @brief usart_dma_request + */ +typedef enum +{ + USART_DMA_REQ_TX = (1U << 7), /**< TX dma bit */ + USART_DMA_REQ_RX = (1U << 6), /**< RX dma bit */ +} usart_dma_req_t; + +/** + * @brief usart_wakeup_methods + */ +typedef enum +{ + USART_WAKEUP_IDLE = 0x0, /**< Wake up the machine when bus-line is idle */ + USART_WAKEUP_ADDR = 0x1, /**< Wake up the machine when match the address */ +} usart_wakeup_t; + +/** + * @brief usart_IrDA_low_power + */ +typedef enum +{ + USART_IrDA_MODE_NORMAL = 0x0, /**< Normal IrDA mode */ + USART_IrDA_MODE_LOW_POWER = 0x1, /**< Low-power IrDA mode */ +} usart_IrDA_mode_t; + +/** + * @brief USART interrupts definition + */ +typedef enum +{ + USART_IT_PE = ((1U << 8) | (1U << 16)), /**< Parity error */ + USART_IT_TXE = ((1U << 7) | (1U << 16)), /**< Tx empty */ + USART_IT_TC = ((1U << 6) | (1U << 16)), /**< Tx complete */ + USART_IT_RXNE = ((1U << 5) | (1U << 16)), /**< Rx not empty */ + USART_IT_IDLE = ((1U << 4) | (1U << 16)), /**< Idle */ + USART_IT_CTS = ((1U << 10) | (1U << 18)), /**< CTS */ + USART_IT_ERR = ((1U << 0) | (1U << 18)), /**< Error */ + USART_IT_ORE = (1U << 3), /**< Overrun error */ + USART_IT_NE = (1U << 2), /**< Noise error */ + USART_IT_FE = (1U << 0), /**< Frame error */ +} usart_it_t; + +/** + * @brief USART flags + */ +typedef enum +{ + USART_FLAG_CTS = (1U << 9), /**< CTS */ + USART_FLAG_TXE = (1U << 7), /**< Tx empty */ + USART_FLAG_TC = (1U << 6), /**< Tx complete */ + USART_FLAG_RXNE = (1U << 5), /**< Rx not empty */ + USART_FLAG_IDLE = (1U << 4), /**< Idle */ + USART_FLAG_ORE = (1U << 3), /**< Overrun error */ + USART_FLAG_NE = (1U << 2), /**< Noise error */ + USART_FLAG_FE = (1U << 1), /**< Frame error */ + USART_FLAG_PE = (1U << 0), /**< Parity error */ +} usart_flag_t; + +/** + * @} + */ + + +/** @defgroup USART_Public_Macros USART Public Macros + * @{ + */ + +/** @defgroup USART_Public_Macros_1 USART handle reset + * @{ + */ +#define USART_RESET_HANDLE_STATE(handle) ((handle)->state = USART_STATE_RESET) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_2 USART clear PE flag + * @{ + */ +#define USART_CLEAR_PEFLAG(handle) \ +do { \ + __IO uint32_t tmpreg; \ + tmpreg = (handle)->perh->STAT; \ + tmpreg = (handle)->perh->DATA; \ + UNUSED(tmpreg); \ +} while (0) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_3 USART clear FE flag + * @{ + */ +#define USART_CLEAR_FEFLAG(handle) USART_CLEAR_PEFLAG(handle) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_4 USART clear NE flag + * @{ + */ +#define USART_CLEAR_NEFLAG(handle) USART_CLEAR_PEFLAG(handle) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_5 USART clear ORE flag + * @{ + */ +#define USART_CLEAR_OREFLAG(handle) USART_CLEAR_PEFLAG(handle) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_6 USART clear IDLE flag + * @{ + */ +#define USART_CLEAR_IDLEFLAG(handle) USART_CLEAR_PEFLAG(handle) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_7 USART enable CTS flow control + * @{ + */ +#define USART_HWCONTROL_CTS_ENABLE(handle) \ + (SET_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_8 USART disable CTS flow control + * @{ + */ +#define USART_HWCONTROL_CTS_DISABLE(handle) \ + (CLEAR_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_9 USART enable RTS flow control + * @{ + */ +#define USART_HWCONTROL_RTS_ENABLE(handle) \ + (SET_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_10 USART disable RTS flow control + * @{ + */ +#define USART_HWCONTROL_RTS_DISABLE(handle) \ + (CLEAR_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_11 USART enable + * @{ + */ +#define USART_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) +/** + * @} + */ + +/** @defgroup USART_Public_Macros_12 USART disable + * @{ + */ +#define USART_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Macros USART Private Macros + * @{ + */ + +#define IS_USART(x) (((x) == USART0) || ((x) == USART1)) +#define IS_USART_WORD_LENGTH(x) (((x) == USART_WORD_LENGTH_8B) || \ + ((x) == USART_WORD_LENGTH_9B)) +#define IS_USART_STOPBITS(x) (((x) == USART_STOP_BITS_1) || \ + ((x) == USART_STOP_BITS_0_5) || \ + ((x) == USART_STOP_BITS_2) || \ + ((x) == USART_STOP_BITS_1_5)) +#define IS_USART_PARITY(x) (((x) == USART_PARITY_NONE) || \ + ((x) == USART_PARITY_EVEN) || \ + ((x) == USART_PARITY_ODD)) +#define IS_USART_MODE(x) (((x) == USART_MODE_RX) || \ + ((x) == USART_MODE_TX) || \ + ((x) == USART_MODE_TX_RX)) +#define IS_USART_HARDWARE_FLOW_CONTROL(x)\ + (((x) == USART_HW_FLOW_CTL_NONE) || \ + ((x) == USART_HW_FLOW_CTL_RTS) || \ + ((x) == USART_HW_FLOW_CTL_CTS) || \ + ((x) == USART_HW_FLOW_CTL_RTS_CTS)) +#define IS_USART_CLOCK(x) (((x) == USART_CLOCK_DISABLE) || \ + ((x) == USART_CLOCK_ENABLE)) +#define IS_USART_CPOL(x) (((x) == USART_CPOL_LOW) || ((x) == USART_CPOL_HIGH)) +#define IS_USART_CPHA(x) (((x) == USART_CPHA_1EDGE) || ((x) == USART_CPHA_2EDGE)) +#define IS_USART_LASTBIT(x) (((x) == USART_LAST_BIT_DISABLE) || \ + ((x) == USART_LAST_BIT_ENABLE)) +#define IS_USART_DMAREQ(x) (((x) == USART_DMA_REQ_TX) || \ + ((x) == USART_DMA_REQ_RX)) +#define IS_USART_WAKEUP(x) (((x) == USART_WAKEUP_IDLE) || \ + ((x) == USART_WAKEUP_ADDR)) +#define IS_USART_IRDA_MODE(x) (((x) == USART_IrDA_MODE_NORMAL) || \ + ((x) == USART_IrDA_MODE_LOW_POWER)) +#define IS_USART_CONFIG_IT(x) (((x) == USART_IT_PE) || ((x) == USART_IT_TXE) || \ + ((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ + ((x) == USART_IT_IDLE) || \ + ((x) == USART_IT_CTS) || ((x) == USART_IT_ERR)) +#define IS_USART_GET_IT(x) (((x) == USART_IT_PE) || ((x) == USART_IT_TXE) || \ + ((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ + ((x) == USART_IT_IDLE) || \ + ((x) == USART_IT_CTS) || ((x) == USART_IT_ORE) || \ + ((x) == USART_IT_NE) || ((x) == USART_IT_FE) || \ + ((x) == USART_IT_ERR)) +#define IS_USART_CLEAR_IT(x) (((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ + ((x) == USART_IT_CTS)) + +#define IS_USART_FLAG(x) (((x) == USART_FLAG_PE) || ((x) == USART_FLAG_TXE) || \ + ((x) == USART_FLAG_TC) || ((x) == USART_FLAG_RXNE) || \ + ((x) == USART_FLAG_IDLE) || \ + ((x) == USART_FLAG_CTS) || ((x) == USART_FLAG_ORE) || \ + ((x) == USART_FLAG_NE) || ((x) == USART_FLAG_FE)) +#define IS_USART_CLEAR_FLAG(x) (((x) == USART_FLAG_CTS) || \ + ((x) == USART_FLAG_TC) || \ + ((x) == USART_FLAG_RXNE)) +#define IS_USART_BAUDRATE(x) (((x) > 0) && ((x) < 0x0044AA21)) +#define IS_USART_ADDRESS(x) ((x) <= 0xF) +#define IS_USART_DATA(x) ((x) <= 0x1FF) +#define DUMMY_DATA 0xFFFF +#define USART_STATE_TX_MASK (1 << 4) +#define USART_STATE_RX_MASK (1 << 5) + +/** + * @} + */ + +/** @addtogroup USART_Public_Functions + * @{ + */ + +/** @addtogroup USART_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void usart_reset(usart_handle_t *hperh); +ald_status_t usart_init(usart_handle_t *hperh); +ald_status_t usart_half_duplex_init(usart_handle_t *hperh); +ald_status_t usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup); +ald_status_t usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init); +/** + * @} + */ + +/** @addtogroup USART_Public_Functions_Group2 + * @{ + */ + +/** @addtogroup USART_Public_Functions_Group2_1 + * @{ + */ +/* Asynchronization IO operation functions */ +ald_status_t usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +#ifdef ALD_DMA +ald_status_t usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +#endif +/** + * @} + */ + +/** @addtogroup USART_Public_Functions_Group2_2 + * @{ + */ +/* Synchronization IO operation functions */ +ald_status_t usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); +ald_status_t usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); +#ifdef ALD_DMA +ald_status_t usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); +ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, + uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); +#endif +/** + * @} + */ + +/** @addtogroup USART_Public_Functions_Group2_3 + * @{ + */ +/* Utilities functions */ +#ifdef ALD_DMA +ald_status_t usart_dma_pause(usart_handle_t *hperh); +ald_status_t usart_dma_resume(usart_handle_t *hperh); +ald_status_t usart_dma_stop(usart_handle_t *hperh); +#endif +void usart_irq_handle(usart_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USART_Public_Functions_Group3 + * @{ + */ +/* Peripheral control functions */ +ald_status_t usart_multi_processor_enter_mute_mode(usart_handle_t *hperh); +ald_status_t usart_multi_processor_exit_mute_mode(usart_handle_t *hperh); +ald_status_t usart_half_duplex_enable_send(usart_handle_t *hperh); +ald_status_t usart_half_duplex_enable_recv(usart_handle_t *hperh); +void usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state); +void usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state); +flag_status_t usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag); +void usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag); +it_status_t usart_get_it_status(usart_handle_t *hperh, usart_it_t it); +/** + * @} + */ + +/** @addtogroup USART_Public_Functions_Group4 + * @{ + */ + +/* Peripheral state and error functions */ +usart_state_t usart_get_state(usart_handle_t *hperh); +uint32_t usart_get_error(usart_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_USART_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h new file mode 100644 index 0000000000..ee181e3da7 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h @@ -0,0 +1,117 @@ +/** + ********************************************************************************* + * + * @file ald_wdt.h + * @brief Header file of WDT module driver. + * + * @version V1.0 + * @date 18 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_WDT_H__ +#define __ALD_WDT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup WDT + * @{ + */ + +/** @defgroup WDT_Public_Types WDT Public Types + * @{ + */ + +/** + * @brief Wwdt no dog window + */ +typedef enum +{ + WWDT_WIN_25 = 0x0, /**< No dog window size: 25% */ + WWDT_WIN_50 = 0x1, /**< No dog window size: 50% */ + WWDT_WIN_75 = 0x2, /**< No dog window size: 75% */ + WWDT_WIN_00 = 0x3, /**< No dog window size: 0% */ +} wwdt_win_t; + +/** + * @} + */ + +/** + * @defgroup WDT_Private_Macros WDT Private Macros + * @{ + */ +#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551);} +#define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFF);} +#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551);} +#define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFF);} + +/** + * @} + */ + +/** + * @addtogroup WDT_Private_Macros WDT Private Macros + * @{ + */ +#define IS_WWDT_WIN_TYPE(x) ((x == WWDT_WIN_25) || \ + (x == WWDT_WIN_50) || \ + (x == WWDT_WIN_75) || \ + (x == WWDT_WIN_00)) +#define IS_FUNC_STATE(x) (((x) == DISABLE) || \ + ((x) == ENABLE)) +/** + * @} + */ + +/** @addtogroup WWDT_Public_Functions + * @{ + */ +void wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt); +void wwdt_start(void); +uint32_t wwdt_get_value(void); +it_status_t wwdt_get_flag_status(void); +void wwdt_clear_flag_status(void); +void wwdt_feed_dog(void); +/** + * @} + */ + +/** @addtogroup IWDT_Public_Functions + * @{ + */ +void iwdt_init(uint32_t load, type_func_t interrupt); +void iwdt_start(void); +uint32_t iwdt_get_value(void); +it_status_t iwdt_get_flag_status(void); +void iwdt_clear_flag_status(void); +void iwdt_feed_dog(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_WDT_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h new file mode 100644 index 0000000000..34303037d9 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h @@ -0,0 +1,127 @@ +/** + ********************************************************************************* + * + * @file type.h + * @brief define type + * + * @version V1.0 + * @date 17 Apr 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __TYPE_H__ +#define __TYPE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#if defined (__CC_ARM) +#define __INLINE__ __inline +#define __STATIC_INLINE__ static __inline +#else +#define __INLINE__ inline +#define __STATIC_INLINE__ static inline +#endif + +#define __isr__ + +typedef enum +{ + RESET = 0x0, + SET = 0x1, +} flag_status_t, it_status_t; + +typedef enum +{ + BIT_RESET = 0x0, + BIT_SET = 0x1, +} bit_status_t; + +typedef enum +{ + DISABLE = 0x0, + ENABLE = 0x1, +} type_func_t; +#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) + +typedef enum +{ + FALSE = 0x0, + TRUE = 0x1, +} type_bool_t; + +typedef enum +{ + UNLOCK = 0x0, + LOCK = 0x1, +} lock_state_t; +#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) + + +#define BIT(x) ((1U << (x))) +#define BITS(s, e) ((0xffffffff << (s)) & (0xffffffff >> (31 - (e)))) +#define SET_BIT(reg, bit) ((reg) |= (bit)) +#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) +#define READ_BIT(reg, bit) ((reg) & (bit)) +#define READ_BITS(reg, msk, s) (((reg) & (msk)) >> (s)) +#define CLEAR_REG(reg) ((reg) = (0x0)) +#define WRITE_REG(reg, val) ((reg) = (val)) +#define READ_REG(reg) ((reg)) +#define MODIFY_REG(reg, clearmask, setmask) \ + WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask))) +#define UNUSED(x) ((void)(x)) + +#ifdef USE_ASSERT +#define assert_param(x) \ +do { \ + if (!(x)) { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ +} while (0) +#else +#define assert_param(x) +#endif + + +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */ + +__STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val) +{ + uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; +} + +__STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val) +{ + uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; +} + +#if defined ( __GNUC__ ) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __TYPE_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h new file mode 100644 index 0000000000..b80d155790 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h @@ -0,0 +1,163 @@ +/** + ********************************************************************************* + * + * @file utils.h + * @brief This file contains the Utilities functions/types for the driver. + * + * @version V1.0 + * @date 07 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __UTILS_H__ +#define __UTILS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "ald_conf.h" +#include "type.h" +#include "es32f065x.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup UTILS + * @{ + */ + +/** @defgroup ALD_Public_Types Public Types + * @{ + */ +/** + * @brief SysTick interval + */ +extern uint32_t __systick_interval; + +/** + * @brief ALD Status structures definition + */ +typedef enum +{ + OK = 0x0, + ERROR = 0x1, + BUSY = 0x2, + TIMEOUT = 0x3 +} ald_status_t; + +/** + * @brief SysTick interval definition + */ +typedef enum +{ + SYSTICK_INTERVAL_1MS = 1000, /**< Interval is 1ms */ + SYSTICK_INTERVAL_10MS = 100, /**< Interval is 10ms */ + SYSTICK_INTERVAL_100MS = 10, /**< Interval is 100ms */ + SYSTICK_INTERVAL_1000MS = 1, /**< Interval is 1s */ +} systick_interval_t; +/** + * @} + */ + +/** @defgroup ALD_Public_Macros Public Macros + * @{ + */ +#define ALD_MAX_DELAY 0xFFFFFFFF + +#define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET) +#define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET) +#define RESET_HANDLE_STATE(x) ((x)->state = 0) +#define __LOCK(x) \ + do { \ + if ((x)->lock == LOCK) { \ + return BUSY; \ + } \ + else { \ + (x)->lock = LOCK; \ + } \ + } while (0) + +#define __UNLOCK(x) \ + do { \ + (x)->lock = UNLOCK; \ + } while (0) + +/** + * @} + */ + +/** @defgroup ALD_Private_Macros Private Macros + * @{ + */ +#define IS_PRIO(x) ((x) < 4) +#define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \ + ((x) == SYSTICK_INTERVAL_10MS) || \ + ((x) == SYSTICK_INTERVAL_100MS) || \ + ((x) == SYSTICK_INTERVAL_1000MS)) +/** + * @} + */ + +/** @addtogroup ALD_Public_Functions + * @{ + */ + +/** @addtogroup ALD_Public_Functions_Group1 + * @{ + */ + +/* Initialization functions */ +void mcu_ald_init(void); +void __init_tick(uint32_t prio); +void systick_interval_select(systick_interval_t value); + +/** + * @} + */ + +/** @addtogroup ALD_Public_Functions_Group2 + * @{ + */ +/* Peripheral Control functions */ +void __inc_tick(void); +void __delay_ms(__IO uint32_t delay); +uint32_t __get_tick(void); +void __suspend_tick(void); +void __resume_tick(void); +void systick_irq_cbk(void); +uint32_t get_ald_version(void); +ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout); +void mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status); +uint32_t mcu_get_tick(void); +uint32_t mcu_get_cpu_id(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __UTILS_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/ReleaseNote.html b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/ReleaseNote.html new file mode 100644 index 0000000000..a57c58046d --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/ReleaseNote.html @@ -0,0 +1,14 @@ + + + + +ReleaseNote +

ES32F065x MD Release Note

+

V1.00 2018-12-26

+
    +
  1. First release
    2. + +
+

 

+ + \ No newline at end of file diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c new file mode 100644 index 0000000000..0ea7a7c0eb --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c @@ -0,0 +1,331 @@ +/** + ********************************************************************************* + * + * @file ald_acmp.c + * @brief ACMP module driver. + * + * @version V1.0 + * @date 13 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_acmp.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup ACMP ACMP + * @brief ACMP module driver + * @{ + */ +#ifdef ALD_ACMP + +/** @defgroup ACMP_Public_Functions ACMP Public Functions + * @{ + */ + +/** @defgroup ACMP_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the ACMP mode according to the specified parameters in + * the acmp_init_t and create the associated handle. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t acmp_init(acmp_handle_t *hperh) +{ + uint32_t tmp = 0; + + if (hperh == NULL) + return ERROR; + + if (hperh->init.vdd_level > 63) + return ERROR; + + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode)); + assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time)); + assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel)); + assert_param(IS_ACMP_WARM_FUNC_TYPE(hperh->init.warm_func)); + assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.pos_port)); + assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.neg_port)); + assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval)); + assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge)); + + __LOCK(hperh); + + tmp = hperh->perh->CON; + + tmp |= ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) | + (hperh->init.inactval << ACMP_CON_INACTV_POS)); + + hperh->perh->CON = tmp; + + tmp = hperh->perh->INPUTSEL; + + tmp |= ((hperh->init.pos_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.neg_port << ACMP_INPUTSEL_NSEL_POSS) | + (hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS)); + + hperh->perh->INPUTSEL = tmp; + + if (hperh->init.warm_func == ACMP_WARM_DISABLE) + CLEAR_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK); + else + SET_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK); + + switch (hperh->init.edge) + { + case ACMP_EDGE_NONE: + CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_FALL: + SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_RISE: + CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_ALL: + SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + default: + break; + } + + SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK); + + while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0); + + __UNLOCK(hperh); + return OK; +} +/** + * @} + */ + +/** @defgroup ACMP_Public_Functions_Group2 Interrupt operation functions + * @brief ACMP Interrupt operation functions + * @{ + */ + +/** + * @brief Enables or disables the specified ACMP interrupts. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param it: Specifies the ACMP interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref acmp_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval Status, see @ref ald_status_t. + */ +ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); + + __LOCK(hperh); + + if (state) + hperh->perh->IES |= it; + else + hperh->perh->IEC |= it; + + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Checks whether the specified ACMP interrupt has occurred or not. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param flag: Specifies the ACMP interrupt source to check. + * This parameter can be one of the @ref acmp_it_t. + * @retval it_status_t + * - SET + * - RESET + */ +it_status_t acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_FLAG_TYPE(flag)); + + if (hperh->perh->RIF & flag) + { + __UNLOCK(hperh); + return SET; + } + + return RESET; +} + +/** @brief Clear the specified ACMP it flags. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param flag: specifies the it flag. + * This parameter can be one of the @ref acmp_it_t. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_FLAG_TYPE(flag)); + + __LOCK(hperh); + hperh->perh->IFC |= flag; + __UNLOCK(hperh); + + return OK; +} + +/** @brief Set the specified acmp it flags. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified acmp module. + * @param it: specifies the it flag. + * This parameter can be one of the @ref acmp_it_t. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t acmp_set_it_mask(acmp_handle_t *hperh, acmp_it_t it) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_IT_TYPE(it)); + + __LOCK(hperh); + hperh->perh->IFM |= it; + __UNLOCK(hperh); + + return OK; +} + +/** @brief Check whether the specified ACMP flag is set or not. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param status: specifies the status to check. + * This parameter can be one of the @ref acmp_status_t. + * @retval flag_status_t + * - SET + * - RESET + */ +flag_status_t acmp_get_status(acmp_handle_t *hperh, acmp_status_t status) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_STATUS_TYPE(status)); + + if (hperh->perh->STAT & status) + { + __UNLOCK(hperh); + return SET; + } + + return RESET; +} +/** + * @} + */ + +/** @defgroup ACMP_Public_Functions_Group3 Output value functions + * @brief ACMP Output value functions + * @{ + */ + +/** + * @brief This function handles ACMP interrupt request. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @retval None + */ +void acmp_irq_handle(acmp_handle_t *hperh) +{ + if (acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) + { + if (hperh->acmp_warmup_cplt_cbk) + hperh->acmp_warmup_cplt_cbk(hperh); + acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP); + } + + if (acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) + { + if (hperh->acmp_edge_cplt_cbk) + hperh->acmp_edge_cplt_cbk(hperh); + acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE); + } + + return; +} + +/** + * @brief This function config acmp output. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param config: Pointer to a acmp_output_config_t structure that contains + * the configutation information for acmp output. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config) +{ + if (hperh == NULL) + return ERROR; + + if (config == NULL) + return ERROR; + + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_INVERT_TYPE(config->gpio_inv)); + assert_param(IS_ACMP_LOCATION_TYPE(config->location)); + assert_param(IS_ACMP_OUT_FUNC_TYPE(config->out_func)); + + __LOCK(hperh); + hperh->perh->PORT = config->location; + hperh->perh->CON |= (config->gpio_inv << ACMP_CON_OUTINV_POS); + hperh->perh->PORT = config->out_func; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief This function output acmp result. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @retval output value. + */ +uint8_t acmp_out_result(acmp_handle_t *hperh) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + + return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS); +} +/** + * @} + */ + +/** + * @} + */ +#endif /* ALD_ACMP */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c new file mode 100644 index 0000000000..95d707dfda --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c @@ -0,0 +1,1345 @@ +/** + ****************************************************************************** + * @file ald_adc.c + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) + * peripheral: + * + Initialization functions + * ++ Initialization and Configuration of ADC + * + Operation functions + * ++ Start, stop, get result of conversions of normal + * group, using 3 possible modes: polling, interruption or DMA. + * + Control functions + * ++ Channels configuration on normal group + * ++ Channels configuration on insert group + * ++ Analog Watchdog configuration + * + State functions + * ++ ADC state machine management + * ++ Interrupts and flags management + * + * @version V1.0 + * @date 15 Dec 2017 + * @author AE Team. + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + + +#include "ald_cmu.h" +#include "ald_adc.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC module driver + * @{ + */ + +#ifdef ALD_ADC + +/** @addtogroup ADC_Private_Functions + * @{ + */ +#ifdef ALD_DMA + static void adc_dma_normal_conv_cplt(void *arg); + static void adc_dma_error(void *arg); +#endif +/** + * @} + */ + + +/** @defgroup ADC_Public_Functions ADC Public Functions + * @{ + */ + +/** @defgroup ADC_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the ADC peripheral and normal group according to + * parameters specified in structure "adc_handle_t". + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_init(adc_handle_t *hperh) +{ + ald_status_t tmp_status = OK; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.data_align)); + assert_param(IS_ADC_SCAN_MODE_TYPE(hperh->init.scan_mode)); + assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.clk_div)); + assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.neg_ref)); + assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.pos_ref)); + assert_param(IS_ADC_CONV_RES_TYPE(hperh->init.conv_res)); + assert_param(IS_ADC_NBR_OF_NM_TYPE(hperh->init.conv_nbr)); + assert_param(IS_ADC_DISC_NBR_TYPE(hperh->init.disc_nbr)); + assert_param(IS_FUNC_STATE(hperh->init.cont_mode)); + assert_param(IS_FUNC_STATE(hperh->init.disc_mode)); + assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_mode)); + assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode)); + + if (hperh->state == ADC_STATE_RESET) + { + hperh->error_code = ADC_ERROR_NONE; + hperh->lock = UNLOCK; + } + + ADC_DISABLE(hperh); + hperh->state = ADC_STATE_BUSY_INTERNAL; + MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.data_align << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont_mode << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan_mode << ADC_CON0_SCANEN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.conv_res << ADC_CON0_RSEL_POSS); + + /* Enable discontinuous mode only if continuous mode is enabled */ + if (hperh->init.disc_mode == ENABLE) + { + if (hperh->init.cont_mode == ENABLE) + { + SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nbr << ADC_CON0_ETRGN_POSS); + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.conv_nbr << ADC_CHSL_NSL_POSS); + } + else + { + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_INTERNAL; + tmp_status = ERROR; + } + } + else + { + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + } + + if (hperh->init.scan_mode == ADC_SCAN_ENABLE) + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.conv_nbr << ADC_CHSL_NSL_POSS); + + if (hperh->init.cont_mode == ENABLE) + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.conv_nbr << ADC_CHSL_NSL_POSS); + + MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS); + /* if the ADC CLK less than 1MHZ,PWRMOD should be Enable*/ + MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.clk_div << ADC_CCR_CKDIV_POSS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.neg_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.pos_ref << ADC_CCR_VRPSEL_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_mode << ADC_CON1_NCHESEL_POS); + + if (hperh->nm_trig_mode != ADC_TRIG_SOFT) + pis_create(&hperh->reg_pis_handle); + + if (tmp_status == OK) + { + hperh->error_code = ADC_ERROR_NONE; + hperh->state |= ADC_STATE_READY; + hperh->state &= ~(ADC_STATE_ERROR | ADC_STATE_NM_BUSY + | ADC_STATE_IST_BUSY | ADC_STATE_BUSY_INTERNAL); + } + + adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE); + return tmp_status; +} + +/** + * @brief Deinitialize the ADC peripheral registers to their default reset + * values. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_reset(adc_handle_t *hperh) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + ADC_DISABLE(hperh); + + adc_clear_flag_status(hperh, ADC_FLAG_AWD); + adc_clear_flag_status(hperh, ADC_FLAG_NH); + adc_clear_flag_status(hperh, ADC_FLAG_IH); + adc_clear_flag_status(hperh, ADC_FLAG_OVR); + adc_clear_flag_status(hperh, ADC_FLAG_NHS); + adc_clear_flag_status(hperh, ADC_FLAG_IHS); + + WRITE_REG(hperh->perh->CON0, 0x0); + WRITE_REG(hperh->perh->CON1, 0x0); + WRITE_REG(hperh->perh->CCR, 0x0); + WRITE_REG(hperh->perh->WDTH, 0xFFF); + WRITE_REG(hperh->perh->WDTL, 0x0); + WRITE_REG(hperh->perh->ICHOFF[0], 0x0); + WRITE_REG(hperh->perh->ICHOFF[1], 0x0); + WRITE_REG(hperh->perh->ICHOFF[2], 0x0); + WRITE_REG(hperh->perh->ICHOFF[3], 0x0); + WRITE_REG(hperh->perh->ICHS, 0x0); + WRITE_REG(hperh->perh->NCHS1, 0x0); + WRITE_REG(hperh->perh->NCHS2, 0x0); + WRITE_REG(hperh->perh->NCHS3, 0x0); + WRITE_REG(hperh->perh->NCHS4, 0x0); + WRITE_REG(hperh->perh->SMPT1, 0x0); + WRITE_REG(hperh->perh->SMPT2, 0x0); + WRITE_REG(hperh->perh->CHSL, 0x0); + + if (hperh->nm_trig_mode != ADC_TRIG_SOFT) + pis_destroy(&hperh->reg_pis_handle); + + if (hperh->ist_trig_mode != ADC_TRIG_SOFT) + pis_destroy(&hperh->inj_pis_handle); + + hperh->state = ADC_STATE_RESET; + hperh->error_code = ADC_ERROR_NONE; + return OK; +} +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group2 IO operation functions + * @brief Input and Output operation functions + * @{ + */ + +/** + * @brief Enables ADC, starts conversion of normal group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_normal_start(adc_handle_t *hperh) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode)); + assert_param(IS_ADC_TYPE(hperh->perh)); + + __LOCK(hperh); + ADC_ENABLE(hperh); + hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); + hperh->state |= ADC_STATE_NM_BUSY; + __UNLOCK(hperh); + adc_clear_flag_status(hperh, ADC_FLAG_NH); + + if (hperh->nm_trig_mode == ADC_TRIG_SOFT) + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert channels in + * case of auto_injection mode), disable ADC peripheral. + * @note: ADC peripheral disable is forcing stop of potential + * conversion on insert group. If insert group is under use, it + * should be preliminarily stopped using adc_insert_stop function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_normal_stop(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode)); + assert_param(IS_ADC_TYPE(hperh->perh)); + + __LOCK(hperh); + + ADC_DISABLE(hperh); + hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_NM_EOC); + hperh->state |= ADC_STATE_READY; + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Wait for normal group conversion to be completed. + * @note This function cannot be used in a particular setup: ADC configured in DMA mode. + * In this case, DMA resets the flag EOC and polling cannot be performed on each conversion. + * @note When use this function,you should be pay attention to the hperh->init.reocs_mode, + * if it is ADC_REOCS_MODE_ALL, it means the function will wait all normal rank conversion finished. + * if it is ADC_REOCS_MODE_ONE, it means the funcion will wait every normal rank conversion finished. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = 0; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + tickstart = __get_tick(); + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) + { + if (timeout != ALD_MAX_DELAY) + { + if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + { + hperh->state |= ADC_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + + adc_clear_flag_status(hperh, ADC_FLAG_NHS); + adc_clear_flag_status(hperh, ADC_FLAG_NH); + + hperh->state |= ADC_STATE_NM_EOC; + + if ((hperh->nm_trig_mode == ADC_TRIG_SOFT) + && (hperh->init.cont_mode == DISABLE) + && (hperh->init.scan_mode == ADC_SCAN_DISABLE)) + { + hperh->state &= ~ADC_STATE_NM_BUSY; + + if ((hperh->state & ADC_STATE_IST_BUSY) == 0) + hperh->state |= ADC_STATE_READY; + } + return OK; +} + +/** + * @brief Poll for conversion event. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param event_type: the ADC event type. + * This parameter can be one of the following values: + * ADC_awd_event: ADC Analog watchdog event. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout) +{ + uint32_t tickstart = 0; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_EVENT_TYPE(event_type)); + + tickstart = __get_tick(); + + while (adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) + { + if (timeout != ALD_MAX_DELAY) + { + if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + { + hperh->state |= ADC_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + + hperh->state |= ADC_STATE_AWD; + return OK; +} + +/** + * @brief Enables ADC, starts conversion of normal group with interruption. + * Interruptions enabled in this function: + * - REOC (end of conversion of normal group) + * Each of these interruptions has its dedicated callback function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_normal_start_by_it(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + __LOCK(hperh); + ADC_ENABLE(hperh); + hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); + hperh->state |= ADC_STATE_NM_BUSY; + hperh->error_code = ADC_ERROR_NONE; + + if (READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)) + { + hperh->state &= ~(ADC_STATE_IST_EOC); + hperh->state |= ADC_STATE_IST_BUSY; + } + + __UNLOCK(hperh); + adc_clear_flag_status(hperh, ADC_FLAG_NH); + adc_interrupt_config(hperh, ADC_IT_NH, ENABLE); + + if (hperh->nm_trig_mode == ADC_TRIG_SOFT) + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert group in + * case of auto_injection mode), disable interrution of + * end-of-conversion, disable ADC peripheral. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_normal_stop_by_it(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + __LOCK(hperh); + ADC_DISABLE(hperh); + adc_interrupt_config(hperh, ADC_IT_NH, DISABLE); + hperh->state |= ADC_STATE_READY; + hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); + + __UNLOCK(hperh); + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Enables ADC, starts conversion of normal group and transfers result + * through DMA. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param buf: The destination Buffer address. + * @param size: The length of data to be transferred from ADC peripheral to memory. + * @param channel: The DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) +{ + if ((hperh == NULL) || (buf == NULL) || (size == 0) || (channel > 5)) + return ERROR; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + __LOCK(hperh); + ADC_ENABLE(hperh); + hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); + hperh->state |= ADC_STATE_NM_BUSY; + + if (READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)) + { + hperh->state &= ~(ADC_STATE_IST_EOC); + hperh->state |= ADC_STATE_IST_BUSY; + } + + if ((hperh->state & ADC_STATE_IST_BUSY) != 0) + { + hperh->state &= ~(ADC_STATE_ERROR); + hperh->error_code &= ~(ADC_ERROR_OVR | ADC_ERROR_DMA); + } + else + { + hperh->state &= ~(ADC_STATE_ERROR); + hperh->error_code = ADC_ERROR_NONE; + } + __UNLOCK(hperh); + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_cbk = adc_dma_normal_conv_cplt; + hperh->hdma.cplt_arg = hperh; + hperh->hdma.err_cbk = adc_dma_error; + hperh->hdma.err_arg = hperh; + + dma_config_struct(&hperh->hdma.config); + hperh->hdma.config.src = (void *)&hperh->perh->NCHDR; + hperh->hdma.config.dst = (void *)buf; + hperh->hdma.config.size = size; + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.msel = DMA_MSEL_ADC0; + hperh->hdma.config.msigsel = DMA_MSIGSEL_ADC; + hperh->hdma.config.channel = channel; + dma_config_basic(&hperh->hdma); + + hperh->hpis.init.producer_src = PIS_ADC1_REGULAT; + hperh->hpis.init.producer_clk = PIS_CLK_PCLK2; + hperh->hpis.init.producer_edge = PIS_EDGE_NONE; + hperh->hpis.init.consumer_trig = PIS_CH7_DAC_CH0; + hperh->hpis.init.consumer_clk = PIS_CLK_PCLK1; + pis_create(&hperh->hpis); + + if (hperh->nm_trig_mode == ADC_TRIG_SOFT) + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert group in + * case of auto_insert mode), disable ADC DMA transfer, disable + * ADC peripheral. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_stop_dma(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + __LOCK(hperh); + + ADC_DISABLE(hperh); + pis_destroy(&hperh->hpis); + hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); + hperh->state |= ADC_STATE_READY; + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief DMA transfer complete callback. + * @param arg: argument of the call back. + * @retval None + */ +static void adc_dma_timer_trigger_cplt(void *arg) +{ + adc_timer_config_t *hperh = (adc_timer_config_t *)arg; + + ADC_DISABLE(&hperh->lh_adc); + timer_base_stop(&hperh->lh_timer); + + __UNLOCK(hperh); + if (hperh->lh_adc.adc_reg_cplt_cbk != NULL) + hperh->lh_adc.adc_reg_cplt_cbk(&hperh->lh_adc); + +} + + +/** + * @brief Config Timer trigger adc function + * @param config: Pointer to a adc_timer_config_t structure that + * contains the configuration information for the specified function. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) +{ + __LOCK(config); + + config->lh_pis.perh = PIS; + config->lh_pis.init.producer_clk = PIS_CLK_PCLK1; + config->lh_pis.init.producer_edge = PIS_EDGE_NONE; + config->lh_pis.init.consumer_clk = PIS_CLK_PCLK1; + + if (config->p_timer == TIMER0) + config->lh_pis.init.producer_src = PIS_TIMER0_UPDATA; + else if (config->p_timer == TIMER1) + config->lh_pis.init.producer_src = PIS_TIMER1_UPDATA; + else if (config->p_timer == TIMER2) + config->lh_pis.init.producer_src = PIS_TIMER2_UPDATA; + else if (config->p_timer == TIMER3) + config->lh_pis.init.producer_src = PIS_TIMER3_UPDATA; + else + return ERROR; + + if (config->p_adc == ADC0) + config->lh_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL; + else if (config->p_adc == ADC1) + config->lh_pis.init.consumer_trig = PIS_CH0_ADC1_NORMAL; + else + return ERROR; + + pis_create(&config->lh_pis); + + /* Initialize TIMER0 */ + config->lh_timer.perh = config->p_timer; + config->lh_timer.init.prescaler = 0; + config->lh_timer.init.mode = TIMER_CNT_MODE_UP; + config->lh_timer.init.period = ((cmu_get_pclk1_clock() / 1000000) * config->time); + config->lh_timer.init.clk_div = TIMER_CLOCK_DIV1; + config->lh_timer.init.re_cnt = 0; + timer_base_init(&config->lh_timer); + + config->lh_adc.perh = config->p_adc; + config->lh_adc.init.data_align = ADC_DATAALIGN_RIGHT; + config->lh_adc.init.scan_mode = ADC_SCAN_DISABLE; + config->lh_adc.init.cont_mode = DISABLE; + config->lh_adc.init.conv_nbr = ADC_NM_NBR_1; + config->lh_adc.init.disc_mode = DISABLE; + config->lh_adc.init.disc_nbr = ADC_DISC_NBR_1; + config->lh_adc.init.conv_res = ADC_CONV_RES_12; + config->lh_adc.init.clk_div = ADC_CKDIV_16; + config->lh_adc.init.nche_mode = ADC_NCHESEL_MODE_ONE; + config->lh_adc.init.neg_ref = config->n_ref; + config->lh_adc.init.pos_ref = config->p_ref; + config->lh_adc.adc_reg_cplt_cbk = config->adc_cplt_cbk; + config->lh_adc.adc_inj_cplt_cbk = NULL; + config->lh_adc.adc_out_of_win_cbk = NULL; + config->lh_adc.adc_error_cbk = NULL; + config->lh_adc.adc_ovr_cbk = NULL; + adc_init(&config->lh_adc); + + config->lnm_config.channel = config->adc_ch; + config->lnm_config.rank = ADC_NC_RANK_1; + config->lnm_config.sampling_time = ADC_SAMPLETIME_1; + adc_normal_channel_config(&config->lh_adc, &config->lnm_config); + + config->lh_dma.cplt_cbk = adc_dma_timer_trigger_cplt; + config->lh_dma.cplt_arg = config; + config->lh_dma.err_cbk = adc_dma_error; + config->lh_dma.err_arg = &config->lh_adc; + + dma_config_struct(&config->lh_dma.config); + config->lh_dma.perh = DMA0; + config->lh_dma.config.src = (void *)&config->lh_adc.perh->NCHDR; + config->lh_dma.config.dst = (void *)config->buf; + config->lh_dma.config.size = config->size; + config->lh_dma.config.data_width = DMA_DATA_SIZE_HALFWORD; + config->lh_dma.config.src_inc = DMA_DATA_INC_NONE; + config->lh_dma.config.dst_inc = DMA_DATA_INC_HALFWORD; + config->lh_dma.config.msel = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1; + config->lh_dma.config.msigsel = DMA_MSIGSEL_ADC; + config->lh_dma.config.channel = config->dma_ch; + dma_config_basic(&config->lh_dma); + + ADC_ENABLE(&config->lh_adc); + timer_base_start(&config->lh_timer); + + return OK; +} +#endif + +/** + * @brief Get ADC normal group conversion result. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval ADC group normal conversion data + */ +uint32_t adc_normal_get_value(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + hperh->state &= ~ADC_STATE_NM_EOC; + return hperh->perh->NCHDR; +} + +/** + * @brief Enables ADC, starts conversion of insert group. + * Interruptions enabled in this function: None. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_insert_start(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); + + __LOCK(hperh); + ADC_ENABLE(hperh); + hperh->state &= ~(ADC_STATE_READY | ADC_STATE_IST_EOC); + hperh->state |= ADC_STATE_IST_BUSY; + + if ((hperh->state & ADC_STATE_NM_BUSY) == 0) + hperh->error_code = ADC_ERROR_NONE; + + __UNLOCK(hperh); + adc_clear_flag_status(hperh, ADC_FLAG_IH); + + if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + { + if (hperh->ist_trig_mode == ADC_TRIG_SOFT) + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); + } + + return OK; +} + +/** + * @brief Stop conversion of insert channels. Disable ADC peripheral if + * no normal conversion is on going. + * @note If ADC must be disabled and if conversion is on going on + * normal group, function adc_normal_stop must be used to stop both + * insert and normal groups, and disable the ADC. + * @note If insert group mode auto-injection is enabled, + * function adc_normal_stop must be used. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_insert_stop(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); + + __LOCK(hperh); + + if (((hperh->state & ADC_STATE_NM_BUSY) == 0) + && (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))) + { + ADC_DISABLE(hperh); + hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY | ADC_STATE_IST_EOC); + hperh->state |= ADC_STATE_READY; + } + else + { + hperh->state |= ADC_STATE_ERROR; + __UNLOCK(hperh); + return ERROR; + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Wait for insert group conversion to be completed. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); + + tickstart = __get_tick(); + + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) + { + if (timeout != ALD_MAX_DELAY) + { + if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + { + hperh->state |= ADC_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + + adc_clear_flag_status(hperh, ADC_FLAG_IHS); + adc_clear_flag_status(hperh, ADC_FLAG_IH); + adc_clear_flag_status(hperh, ADC_FLAG_NH); + + hperh->state |= ADC_STATE_IST_EOC; + + if (hperh->ist_trig_mode == ADC_TRIG_SOFT) + { + hperh->state &= ~(ADC_STATE_IST_BUSY); + if ((hperh->state & ADC_STATE_NM_BUSY) == 0) + hperh->state |= ADC_STATE_READY; + } + + hperh->state &= ~(ADC_STATE_TIMEOUT); + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Enables ADC, starts conversion of insert group with interruption. + * - JEOC (end of conversion of insert group) + * Each of these interruptions has its dedicated callback function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t.. + */ +ald_status_t adc_insert_start_by_it(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); + + __LOCK(hperh); + ADC_ENABLE(hperh); + hperh->state &= ~(ADC_STATE_READY | ADC_STATE_IST_EOC); + hperh->state |= ADC_STATE_IST_BUSY; + + if ((hperh->state & ADC_STATE_NM_BUSY) == 0) + hperh->error_code = ADC_ERROR_NONE; + + __UNLOCK(hperh); + adc_clear_flag_status(hperh, ADC_FLAG_IH); + adc_interrupt_config(hperh, ADC_IT_IH, ENABLE); + + if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + { + if (hperh->ist_trig_mode == ADC_TRIG_SOFT) + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); + } + return OK; +} + +/** + * @brief Stop conversion of insert channels, disable interruption of + * end-of-conversion. Disable ADC peripheral if no normal conversion + * is on going. + * @note If ADC must be disabled and if conversion is on going on + * normal group, function adc_normal_stop must be used to stop both + * insert and normal groups, and disable the ADC. + * @note If insert group mode auto-injection is enabled, + * function adc_normal_stop must be used. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval None + */ +ald_status_t adc_insert_stop_by_it(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); + + __LOCK(hperh); + + if (((hperh->state & ADC_STATE_NM_BUSY) == 0) + && (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))) + { + ADC_DISABLE(hperh); + adc_interrupt_config(hperh, ADC_IT_IH, DISABLE); + hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); + hperh->state |= ADC_STATE_READY; + } + else + { + adc_interrupt_config(hperh, ADC_IT_IH, DISABLE); + hperh->state |= ADC_STATE_ERROR; + __UNLOCK(hperh); + return ERROR; + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Get ADC insert group conversion result. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param ih_rank: the converted ADC insert rank. + * This parameter can be one of the following values: + * @arg ADC_INJ_RANK_1: insert Channel1 selected + * @arg ADC_INJ_RANK_2: insert Channel2 selected + * @arg ADC_INJ_RANK_3: insert Channel3 selected + * @arg ADC_INJ_RANK_4: insert Channel4 selected + * @retval ADC group insert conversion data + */ +uint32_t adc_insert_get_value(adc_handle_t *hperh, adc_ih_rank_t ih_rank) +{ + uint32_t tmp; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IH_RANK_TYPE(ih_rank)); + + switch (ih_rank) + { + case ADC_IH_RANK_1: + tmp = hperh->perh->ICHDR[0]; + break; + case ADC_IH_RANK_2: + tmp = hperh->perh->ICHDR[1]; + break; + case ADC_IH_RANK_3: + tmp = hperh->perh->ICHDR[2]; + break; + case ADC_IH_RANK_4: + tmp = hperh->perh->ICHDR[3]; + break; + default: + break; + } + + return tmp; +} + +/** + * @brief Handles ADC interrupt request + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval None + */ +void adc_irq_handler(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); + assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode)); + + if (adc_get_it_status(hperh, ADC_IT_NH) && adc_get_flag_status(hperh, ADC_FLAG_NH)) + { + if ((hperh->state & ADC_STATE_ERROR) == 0) + hperh->state |= ADC_STATE_NM_EOC; + + if ((hperh->nm_trig_mode == ADC_TRIG_SOFT) + && (hperh->init.cont_mode == DISABLE)) + { + adc_interrupt_config(hperh, ADC_IT_NH, DISABLE); + hperh->state &= ~(ADC_STATE_NM_BUSY); + + if ((hperh->state & ADC_STATE_IST_BUSY) == 0) + hperh->state |= ADC_STATE_READY; + } + + if (hperh->adc_reg_cplt_cbk != NULL) + hperh->adc_reg_cplt_cbk(hperh); + + adc_clear_flag_status(hperh, ADC_FLAG_NHS); + adc_clear_flag_status(hperh, ADC_FLAG_NH); + } + + if (adc_get_it_status(hperh, ADC_IT_IH) && adc_get_flag_status(hperh, ADC_FLAG_IH)) + { + if ((hperh->state & ADC_STATE_ERROR) == 0) + hperh->state |= ADC_STATE_IST_EOC; + + if ((hperh->ist_trig_mode == ADC_TRIG_SOFT) + || ((!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + && (hperh->nm_trig_mode == ADC_TRIG_SOFT) + && (hperh->init.cont_mode == DISABLE))) + { + adc_interrupt_config(hperh, ADC_IT_IH, DISABLE); + hperh->state &= ~(ADC_STATE_IST_BUSY); + + if ((hperh->state & ADC_STATE_NM_BUSY) == 0) + hperh->state |= ADC_STATE_READY; + } + if (hperh->adc_inj_cplt_cbk != NULL) + hperh->adc_inj_cplt_cbk(hperh); + + adc_clear_flag_status(hperh, ADC_FLAG_IHS); + adc_clear_flag_status(hperh, ADC_FLAG_IH); + } + + if (adc_get_it_status(hperh, ADC_IT_AWD) && adc_get_flag_status(hperh, ADC_FLAG_AWD)) + { + hperh->state |= ADC_STATE_AWD; + + if (hperh->adc_out_of_win_cbk != NULL) + hperh->adc_out_of_win_cbk(hperh); + + adc_clear_flag_status(hperh, ADC_FLAG_AWD); + } + + if (adc_get_it_status(hperh, ADC_IT_OVR) && adc_get_flag_status(hperh, ADC_FLAG_OVR)) + { + adc_clear_flag_status(hperh, ADC_FLAG_OVR); + hperh->error_code |= ADC_ERROR_OVR; + hperh->state |= ADC_STATE_ERROR; + + if (hperh->adc_ovr_cbk != NULL) + hperh->adc_ovr_cbk(hperh); + } +} + +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ + +/** + * @brief Configures the the selected channel to be linked to the normal + * group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC channel for normal group. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_normal_channel_config(adc_handle_t *hperh, adc_channel_conf_t *config) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); + assert_param(IS_ADC_NC_RANK_TYPE(config->rank)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->sampling_time)); + + __LOCK(hperh); + + if (config->rank <= ADC_NC_RANK_4) + { + hperh->perh->NCHS1 &= ~(0x1f << ((config->rank - 1) << 3)); + hperh->perh->NCHS1 |= (config->channel << ((config->rank - 1) << 3)); + } + else if (config->rank <= ADC_NC_RANK_8) + { + hperh->perh->NCHS2 &= ~(0x1f << ((config->rank - 5) << 3)); + hperh->perh->NCHS2 |= (config->channel << ((config->rank - 5) << 3)); + } + else if (config->rank <= ADC_NC_RANK_12) + { + hperh->perh->NCHS3 &= ~(0x1f << ((config->rank - 9) << 3)); + hperh->perh->NCHS3 |= (config->channel << ((config->rank - 9) << 3)); + } + else + { + hperh->perh->NCHS4 &= ~(0x1f << ((config->rank - 13) << 3)); + hperh->perh->NCHS4 |= (config->channel << ((config->rank - 13) << 3)); + } + + if (config->channel <= 15) + { + hperh->perh->SMPT1 &= ~(0x03 << (config->channel << 1)); + hperh->perh->SMPT1 |= config->sampling_time << (config->channel << 1); + } + else + { + hperh->perh->SMPT2 &= ~(0x03 << ((config->channel - 16) << 1)); + hperh->perh->SMPT2 |= config->sampling_time << ((config->channel - 16) << 1); + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Configures the the selected channel to be linked to the insert + * group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC channel for insert group. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_insert_channel_config(adc_handle_t *hperh, adc_ih_conf_t *config) +{ + uint8_t tmp1, tmp2; + ald_status_t tmp_status = OK; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); + assert_param(IS_ADC_IH_RANK_TYPE(config->rank)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp_time)); + assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset)); + assert_param(IS_ADC_NBR_OF_IST_TYPE(config->nbr)); + assert_param(IS_FUNC_STATE(config->disc_mode)); + assert_param(IS_FUNC_STATE(config->auto_inj)); + assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); + + __LOCK(hperh); + + if (hperh->init.scan_mode == ADC_SCAN_DISABLE) + { + switch (config->rank) + { + case ADC_IH_RANK_1: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS1_MSK, config->channel << ADC_ICHS_IS1_POSS); + break; + case ADC_IH_RANK_2: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS2_MSK, config->channel << ADC_ICHS_IS1_POSS); + break; + case ADC_IH_RANK_3: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS3_MSK, config->channel << ADC_ICHS_IS1_POSS); + break; + case ADC_IH_RANK_4: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS4_MSK, config->channel << ADC_ICHS_IS1_POSS); + break; + default: + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_INTERNAL; + tmp_status = ERROR; + break; + } + } + else + { + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nbr << ADC_CHSL_ISL_POSS); + tmp1 = config->rank ; + tmp2 = config->nbr; + + if (tmp1 <= tmp2) + { + hperh->perh->ICHS &= ~(0x1f << ((tmp1 - 1) << 3)); + hperh->perh->ICHS |= config->channel + << ((tmp1 - 1) << 3); + } + else + { + hperh->perh->ICHS &= ~(0x1f << ((tmp1 - 1) << 3)); + } + } + + if (config->auto_inj == ENABLE) + { + if (hperh->ist_trig_mode == ADC_TRIG_SOFT) + { + SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); + } + else + { + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_INTERNAL; + tmp_status = ERROR; + } + } + + if (config->disc_mode == ENABLE) + { + if (config->auto_inj == DISABLE) + { + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nbr << ADC_CHSL_ISL_POSS); + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + } + else + { + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_INTERNAL; + tmp_status = ERROR; + } + } + + if (config->channel <= 15) + { + hperh->perh->SMPT1 &= ~(0x03 << (config->channel << 1)); + hperh->perh->SMPT1 |= config->samp_time << (config->channel << 1); + } + else + { + hperh->perh->SMPT2 &= ~(0x03 << ((config->channel - 16) << 1)); + hperh->perh->SMPT2 |= config->samp_time << ((config->channel - 16) << 1); + } + + switch (config->rank) + { + case ADC_IH_RANK_1: + hperh->perh->ICHOFF[0] = config->offset; + break; + case ADC_IH_RANK_2: + hperh->perh->ICHOFF[1] = config->offset; + break; + case ADC_IH_RANK_3: + hperh->perh->ICHOFF[2] = config->offset; + break; + case ADC_IH_RANK_4: + hperh->perh->ICHOFF[3] = config->offset; + break; + default: + break; + } + + if (hperh->ist_trig_mode != ADC_TRIG_SOFT) + pis_create(&hperh->inj_pis_handle); + + __UNLOCK(hperh); + return tmp_status; +} + +/** + * @brief Configures the analog watchdog. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC analog watchdog configuration + * @retval ALD status + */ +ald_status_t adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config) +{ + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->watchdog_mode)); + assert_param(IS_FUNC_STATE(config->it_mode)); + assert_param(IS_HTR_TYPE(config->high_threshold)); + assert_param(IS_LTR_TYPE(config->low_threshold)); + + __LOCK(hperh); + + if ((config->watchdog_mode == ADC_ANAWTD_SING_NM) + || (config->watchdog_mode == ADC_ANAWTD_SING_IST) + || (config->watchdog_mode == ADC_ANAWTD_SING_NMIST)) + assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); + + if (config->it_mode == DISABLE) + adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE); + else + adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE); + + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK); + hperh->perh->CON0 |= config->watchdog_mode; + + if (READ_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK)) + MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->channel << ADC_CON0_AWDCH_POSS); + + WRITE_REG(hperh->perh->WDTL, config->low_threshold); + WRITE_REG(hperh->perh->WDTH, config->high_threshold); + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param hperh: Pointer to a adc_handle_t structure. + * @param it: Specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref adc_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->CON0, it); + else + CLEAR_BIT(hperh->perh->CON0, it); + + return; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param hperh: Pointer to a adc_handle_t structure. + * @param it: Specifies the ADC interrupt source to check. + * This parameter can be one of the @ref adc_it_t. + * @retval Status + * - SET + * - RESET + */ +it_status_t adc_get_it_status(adc_handle_t *hperh, adc_it_t it) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IT_TYPE(it)); + + if (READ_BIT(hperh->perh->CON0, it)) + return SET; + + return RESET; +} + +/** @brief Check whether the specified ADC flag is set or not. + * @param hperh: Pointer to a adc_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref adc_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_FLAGS_TYPE(flag)); + + if (READ_BIT(hperh->perh->STAT, flag)) + return SET; + + return RESET; +} + +/** @brief Clear the specified ADC pending flags. + * @param hperh: Pointer to a adc_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref adc_flag_t. + * @retval None + */ +void adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_FLAGS_TYPE(flag)); + + WRITE_REG(hperh->perh->CLR, flag); + return; +} +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ + +/** + * @brief return the ADC state + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval state + */ +uint32_t adc_get_state(adc_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the ADC error code + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval ADC Error Code + */ +uint32_t adc_get_error(adc_handle_t *hperh) +{ + return hperh->error_code; +} + +/** + *@} + */ + +/** + *@} + */ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +#ifdef ALD_DMA +/** + * @brief DMA transfer complete callback. + * @param arg: argument of the call back. + * @retval None + */ +static void adc_dma_normal_conv_cplt(void *arg) +{ + adc_handle_t *hperh = (adc_handle_t *)arg; + + if (hperh->adc_reg_cplt_cbk != NULL) + hperh->adc_reg_cplt_cbk(hperh); + +} + +/** + * @brief DMA error callback + * @param arg: argument of the call back. + * @retval None + */ +static void adc_dma_error(void *arg) +{ + adc_handle_t *hperh = (adc_handle_t *)arg; + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_DMA; + + if (hperh->adc_error_cbk != NULL) + hperh->adc_error_cbk(hperh); +} +#endif +/** + *@} + */ + +#endif /* ALD_ADC */ + +/** + *@} + */ + +/** + *@} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c new file mode 100644 index 0000000000..0a6e766b6a --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c @@ -0,0 +1,154 @@ +/** + ********************************************************************************* + * + * @file ald_bkpc.c + * @brief BKPC module driver. + * + * @version V1.0 + * @date 15 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_bkpc.h" +#include "ald_rtc.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup BKPC BKPC + * @brief BKPC module driver + * @{ + */ +#ifdef ALD_BKPC + +/** @defgroup BKPC_Public_Functions BKPC Public Functions + * @{ + */ + +/** @addtogroup BKPC_Public_Functions_Group1 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) bkpc_ldo_config() API can configure LDO in backup field. + (+) bkpc_bor_config() API can configure BOR in backup field. + + @endverbatim + * @{ + */ + +/** + * @brief Configure ldo in backup field + * @param output: Output voltage select. + * @param state: DISABLE/ENABLE. + * @retval None + */ +void bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state) +{ + assert_param(IS_BKPC_LDO_OUTPUT(output)); + assert_param(IS_FUNC_STATE(state)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->CR, BKPC_CR_MT_STDB_MSK, state << BKPC_CR_MT_STDB_POS); + + if (state) + MODIFY_REG(BKPC->CR, BKPC_CR_LDO_VSEL_MSK, output << BKPC_CR_LDO_VSEL_POSS); + + BKPC_LOCK(); + return; +} + +/** + * @brief Configure bor voltage in backup field + * @param vol: Voltage select. + * @param state: DISABLE/ENABLE. + * @retval None + */ +void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state) +{ + assert_param(IS_BKPC_BOR_VOL(vol)); + assert_param(IS_FUNC_STATE(state)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCR, BKPC_PCR_BOREN_MSK, state << BKPC_PCR_BOREN_POS); + + if (state) + MODIFY_REG(BKPC->PCR, BKPC_PCR_BORS_MSK, vol << BKPC_PCR_BORS_POSS); + + BKPC_LOCK(); + return; + + +} +/** + * @} + */ + +/** @addtogroup BKPC_Public_Functions_Group2 IO operation functions + * @brief IO operation functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) bkpc_write_ram() API can write data in backup ram. + (+) bkpc_read_ram() API can read data from backup ram. + + @endverbatim + * @{ + */ + +/** + * @brief Write data into backup ram. + * @param idx: Index of backup word. + * @param value: Value which will be written to backup ram. + * @retval None + */ +void bkpc_write_ram(uint8_t idx, uint32_t value) +{ + assert_param(IS_BKPC_RAM_IDX(idx)); + + RTC_UNLOCK(); + WRITE_REG(RTC->BKPR[idx], value); + RTC_LOCK(); + + return; +} + +/** + * @brief Read data from backup ram. + * @param idx: Index of backup word. + * @retval The data. + */ +uint32_t bkpc_read_ram(uint8_t idx) +{ + assert_param(IS_BKPC_RAM_IDX(idx)); + + return READ_REG(RTC->BKPR[idx]); +} +/** + * @} + */ + +/** + * @} + */ +#endif /* ALD_BKPC */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c new file mode 100644 index 0000000000..4ddc9901f9 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c @@ -0,0 +1,121 @@ +/** + ********************************************************************************* + * + * @file ald_calc.c + * @brief CALC module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_calc.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CALC CALC + * @brief CALC module driver + * @{ + */ +#ifdef ALD_CALC + +/** @defgroup CALC_Public_Functions CALC Public Functions + * @brief Accelerating calculate functions + * + * @verbatim + ============================================================================== + ##### Accelerating calculate functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Square root operation. + (+) Division. + (+) Get DZ flag. + + @endverbatim + * @{ + */ + +/** + * @brief Square root operation. + * @param data: The data; + * @retval The value of square root. + */ +uint32_t calc_sqrt(uint32_t data) +{ + WRITE_REG(CALC->RDCND, data); + while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK)); + + return READ_REG(CALC->SQRTRES); +} + +/** + * @brief Calculating division. + * @param dividend: The value of the dividend. + * @param divisor: The value of the divisor. + * @param remainder: The value of the remainder. + * @retval The result of division. + */ +uint32_t calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder) +{ + CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); + SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); + WRITE_REG(CALC->DIVDR, dividend); + WRITE_REG(CALC->DIVSR, divisor); + + while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); + + *remainder = READ_REG(CALC->DIVRR); + return READ_REG(CALC->DIVQR); +} + +/** + * @brief Calculating division. + * @param dividend: The value of the dividend. + * @param divisor: The value of the divisor. + * @param remainder: The value of the remainder. + * @retval The result of division. + */ +int32_t calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder) +{ + SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); + SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); + WRITE_REG(CALC->DIVDR, dividend); + WRITE_REG(CALC->DIVSR, divisor); + + while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); + + *remainder = READ_REG(CALC->DIVRR); + return READ_REG(CALC->DIVQR); +} + +/** + * @brief Get the flag of divisor is zero. + * @retval The status, SET/RESET. + */ +flag_status_t calc_get_dz_status(void) +{ + if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK)) + return SET; + + return RESET; +} + +/** + * @} + */ +#endif /* ALD_CALC */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c new file mode 100644 index 0000000000..cb01604b87 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c @@ -0,0 +1,1049 @@ +/** + ****************************************************************************** + * @file ald_can.c + * @brief CAN module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * @version V1.0 + * @date 25 Apr 2017 + * @author AE Team + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the CAN controller interface clock. + (#) CAN pins configuration + (++) Enable the clock for the CAN GPIOs; + (++) Connect and configure the involved CAN pins using the + following function gpio_init(); + (#) Initialise and configure the CAN using can_init() function. + (#) Transmit the CAN frame using can_send()/can_send_by_it() function. + (#) Receive a CAN frame using can_recv()/can_recv_by_it function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the CAN peripheral transmission and wait the end of this operation + using can_send(), at this stage user can specify the value of timeout + according to his end application. + (+) Start the CAN peripheral reception and wait the end of this operation + using can_recv(), at this stage user can specify the value of timeout + according to his end application + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the CAN peripheral transmission using can_send_by_it() + (+) Start the CAN peripheral reception using can_recv_by_it() + (+) Use can_irq_handler() called under the used CAN Interrupt subroutine + (+) At CAN end of transmission pherh->tx_cplt_cbk() function is executed and user can + add his own code by customization of function pointer pherh->tx_cplt_cbk() + (+) In case of CAN Error, pherh->rx_cplt_cbk() function is executed and user can + add his own code by customization of function pointer pherh->rx_cplt_cbk() + + *** CAN ALD driver macros list *** + ============================================= + [..] + Below the list of most used macros in CAN driver. + + (+) CAN_RESET_HANDLE_STATE(): Reset CAN handle state. + (+) CAN_RX_MSG_PENDING(): Return the number of pending received messages. + (+) CAN_DBG_FREEZE(): Enable or disables the DBG Freeze for CAN. + + [..] + (@) You can refer to the CAN driver header file for used the macros + + @endverbatim + ****************************************************************************** + */ + +#include "ald_can.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CAN CAN + * @brief CAN module driver + * @{ + */ +#ifdef ALD_CAN + +/** @addtogroup CAN_Private_Functions CAN Private Functions + * @{ + */ +static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num); +static ald_status_t __can_send_by_it(can_handle_t *hperh); +static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num); +/** + * @} + */ + +/** @defgroup CAN_Public_Functions CAN Public Functions + * @{ + */ + +/** @defgroup CAN_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + * @verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the CAN. + (+) Configures the CAN reception filter. + (+) Reset the CAN. + + @endverbatim + * @{ + */ + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_init_t. + * @param hperh: pointer to a can_handle_t structure that contains + * the configuration information for the specified CAN. + * @retval Status, see ald_status_t. + */ +ald_status_t can_init(can_handle_t *hperh) +{ + uint32_t tickstart = 0; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_FUNC_STATE(hperh->init.ttcm)); + assert_param(IS_FUNC_STATE(hperh->init.abom)); + assert_param(IS_FUNC_STATE(hperh->init.awk)); + assert_param(IS_FUNC_STATE(hperh->init.abom)); + assert_param(IS_FUNC_STATE(hperh->init.rfom)); + assert_param(IS_FUNC_STATE(hperh->init.txmp)); + assert_param(IS_CAN_MODE(hperh->init.mode)); + assert_param(IS_CAN_SJW(hperh->init.sjw)); + assert_param(IS_CAN_BS1(hperh->init.seg1)); + assert_param(IS_CAN_BS2(hperh->init.seg2)); + assert_param(IS_CAN_PRESCALER(hperh->init.psc)); + + if (hperh->state == CAN_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = CAN_STATE_BUSY; + tickstart = __get_tick(); + + CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); + SET_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); + + while (!READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) + { + if ((__get_tick() - tickstart) > CAN_TIMEOUT_VALUE) + { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + + return TIMEOUT; + } + } + + MODIFY_REG(hperh->perh->CON, CAN_CON_TTCEN_MSK, hperh->init.ttcm << CAN_CON_TTCEN_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_ABOFFEN_MSK, hperh->init.abom << CAN_CON_ABOFFEN_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_AWKEN_MSK, hperh->init.awk << CAN_CON_AWKEN_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_ARTXDIS_MSK, hperh->init.artx << CAN_CON_ARTXDIS_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_RXFOPM_MSK, hperh->init.rfom << CAN_CON_RXFOPM_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_TXMP_MSK, hperh->init.txmp << CAN_CON_TXMP_POS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_LOOP_MSK, (hperh->init.mode & 0x1) << CAN_BTIME_LOOP_POS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SILENT_MSK, ((hperh->init.mode >> 1) & 0x1) << CAN_BTIME_SILENT_POS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_RESJW_MSK, hperh->init.sjw << CAN_BTIME_RESJW_POSS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SEG1_MSK, hperh->init.seg1 << CAN_BTIME_SEG1_POSS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SEG2_MSK, hperh->init.seg2 << CAN_BTIME_SEG2_POSS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_BPSC_MSK, (hperh->init.psc - 1) << CAN_BTIME_BPSC_POSS); + + CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); + tickstart = __get_tick(); + + while (READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) + { + if ((__get_tick() - tickstart) > CAN_TIMEOUT_VALUE) + { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + + return TIMEOUT; + } + } + + hperh->err = CAN_ERROR_NONE; + hperh->state = CAN_STATE_READY; + + return OK; +} + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the can_filter_t. + * @param hperh: pointer to a can_handle_t structure. + * @param config: pointer to a can_filter_t structure that + * contains the filter configuration information. + * @retval Status, see ald_status_t. + */ +ald_status_t can_filter_config(can_handle_t *hperh, can_filter_t *config) +{ + uint32_t pos; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_FILTER_NUMBER(config->number)); + assert_param(IS_CAN_FILTER_MODE(config->mode)); + assert_param(IS_CAN_FILTER_SCALE(config->scale)); + assert_param(IS_CAN_FILTER_FIFO(config->fifo)); + assert_param(IS_FUNC_STATE(config->active)); + assert_param(IS_CAN_BANKNUMBER(config->bank_number)); + + pos = 1 << config->number; + + SET_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK); + CLEAR_BIT(hperh->perh->FLTGO, pos); + + if (config->scale == CAN_FILTER_SCALE_16) + { + CLEAR_BIT(hperh->perh->FLTWS, pos); + hperh->perh->Filter[config->number].FLT1 = + ((0xFFFF & config->mask_id_low) << 16) | + (0xFFFF & config->id_low); + + hperh->perh->Filter[config->number].FLT2 = + ((0xFFFF & config->mask_id_high) << 16) | + (0xFFFF & config->id_high); + } + + if (config->scale == CAN_FILTER_SCALE_32) + { + SET_BIT(hperh->perh->FLTWS, pos); + hperh->perh->Filter[config->number].FLT1 = + ((0xFFFF & config->id_high) << 16) | + (0xFFFF & config->id_low); + hperh->perh->Filter[config->number].FLT2 = + ((0xFFFF & config->mask_id_high) << 16) | + (0xFFFF & config->mask_id_low); + } + + MODIFY_REG(hperh->perh->FLTM, pos, config->mode << config->number); + MODIFY_REG(hperh->perh->FLTAS, pos, config->fifo << config->number); + MODIFY_REG(hperh->perh->FLTGO, pos, config->active << config->number); + CLEAR_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK); + + return OK; +} + +/** + * @brief Reset the CAN peripheral. + * @param hperh: pointer to a can_handle_t structure. + * @retval None + */ +void can_reset(can_handle_t *hperh) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + + hperh->state = CAN_STATE_RESET; + __UNLOCK(hperh); + + return; +} + +/** + * @} + */ + +/** @defgroup CAN_Public_Functions_Group2 IO operation functions + * @brief I/O operation functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Send a CAN frame message. + (+) Send a CAN frame message using interrupt. + (+) Receive a CAN frame message. + (+) Receive a CAN frame message using interrupt. + + *@endverbatim + * @{ + */ + +/** + * @brief Send a CAN frame message. + * @param hperh: pointer to a can_handle_t structure. + * @param msg: message which will be snet. + * @param timeout: specify Timeout value + * @retval Status, see ald_status_t. + */ +ald_status_t can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout) +{ + uint32_t tick; + can_tx_mailbox_t idx; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IDTYPE(msg->type)); + assert_param(IS_CAN_RTR(msg->rtr)); + assert_param(IS_CAN_DATA_LEN(msg->len)); + + __LOCK(hperh); + SET_BIT(hperh->state, CAN_STATE_TX_MASK); + + if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) + idx = CAN_TX_MAILBOX_0; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) + idx = CAN_TX_MAILBOX_1; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) + idx = CAN_TX_MAILBOX_2; + else + idx = CAN_TX_MAILBOX_NONE; + + if (idx == CAN_TX_MAILBOX_NONE) + { + hperh->state = CAN_STATE_ERROR; + __UNLOCK(hperh); + return ERROR; + } + + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_IDE_MSK, msg->type << CAN_TXID0_IDE_POS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_RTR_MSK, msg->rtr << CAN_TXID0_RTR_POS); + + if (msg->type == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(msg->std)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, msg->std << CAN_TXID0_STDID_POSS); + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK); + } + else + { + assert_param(IS_CAN_EXTID(msg->ext)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS); + } + MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24)); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24)); + SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + tick = __get_tick(); + + while (!(can_get_tx_status(hperh, idx))) + { + if ((timeout == 0) || ((__get_tick() - tick) > timeout)) + { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + + CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK); + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Send a CAN frame message using interrupt. + * @param hperh: pointer to a can_handle_t structure. + * @param msg: message which will be snet. + * @retval Status, see ald_status_t. + */ +ald_status_t can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg) +{ + uint8_t idx = CAN_TX_MAILBOX_NONE; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IDTYPE(msg->type)); + assert_param(IS_CAN_RTR(msg->rtr)); + assert_param(IS_CAN_DATA_LEN(msg->len)); + + if ((hperh->state != CAN_STATE_READY) && (hperh->state != CAN_STATE_BUSY_RX)) + return BUSY; + + if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) + idx = CAN_TX_MAILBOX_0; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) + idx = CAN_TX_MAILBOX_1; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) + idx = CAN_TX_MAILBOX_2; + else + idx = CAN_TX_MAILBOX_NONE; + + if (idx == CAN_TX_MAILBOX_NONE) + return BUSY; + + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_IDE_MSK, msg->type << CAN_TXID0_IDE_POS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_RTR_MSK, msg->rtr << CAN_TXID0_RTR_POS); + + if (msg->type == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(msg->std)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, msg->std << CAN_TXID0_STDID_POSS); + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK); + } + else + { + assert_param(IS_CAN_EXTID(msg->ext)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS); + } + + MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24)); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24)); + + SET_BIT(hperh->state, CAN_STATE_TX_MASK); + + can_interrupt_config(hperh, CAN_IT_EWG, ENABLE); + can_interrupt_config(hperh, CAN_IT_EPV, ENABLE); + can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); + can_interrupt_config(hperh, CAN_IT_LEC, ENABLE); + can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); + can_interrupt_config(hperh, CAN_IT_TME, ENABLE); + + SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + return OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hperh: pointer to a can_handle_t structure. + * @param num: Receive fifo number, CAN_RX_FIFO0 or CAN_RX_FIFO1 + * @param msg: Storing message. + * @param timeout: Specify timeout value + * @retval Status, see ald_status_t. + */ +ald_status_t can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout) +{ + uint32_t tick, stid, exid; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_FIFO(num)); + + __LOCK(hperh); + SET_BIT(hperh->state, CAN_STATE_RX_MASK); + tick = __get_tick(); + + while (CAN_RX_MSG_PENDING(hperh, num) == 0) + { + if ((timeout == 0) || ((__get_tick() - tick) > timeout)) + { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + + stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS); + exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS); + msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS); + + if (msg->type == CAN_ID_STD) + msg->std = stid; + else + msg->ext = (stid << 18) | exid; + + msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS); + msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS); + msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS); + msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF; + msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF; + msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF; + msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF; + msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF; + msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF; + msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF; + msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF; + + can_rx_fifo_release(hperh, num); + CLEAR_BIT(hperh->state, CAN_STATE_RX_MASK); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receives a correct CAN frame using interrupt. + * @param hperh: pointer to a can_handle_t structure. + * @param num: Specify the FIFO number + * @param msg: Storing message. + * @retval Status, see ald_status_t. + */ +ald_status_t can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_FIFO(num)); + + if ((hperh->state != CAN_STATE_READY) && (hperh->state != CAN_STATE_BUSY_TX)) + return BUSY; + + SET_BIT(hperh->state, CAN_STATE_RX_MASK); + hperh->rx_msg = msg; + + can_interrupt_config(hperh, CAN_IT_EWG, ENABLE); + can_interrupt_config(hperh, CAN_IT_EPV, ENABLE); + can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); + can_interrupt_config(hperh, CAN_IT_LEC, ENABLE); + can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); + + if (num == CAN_RX_FIFO0) + can_interrupt_config(hperh, CAN_IT_FMP0, ENABLE); + else + can_interrupt_config(hperh, CAN_IT_FMP1, ENABLE); + + return OK; +} +/** + * @} + */ + +/** @defgroup CAN_Public_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure CAN sleep. + (+) Configure CAN wakeup. + (+) CAN cancel send message. + (+) Handle CAN interrupt. + (+) Get CAN transmit status. + (+) Configure CAN interrupt ENABLE/DISABLE. + (+) Get CAN interrupt source status. + (+) Get CAN interrupt flag status. + (+) Clear CAN interrupt flag. + + * @endverbatim + * @{ + */ + +/** + * @brief Enters the Sleep(low power) mode. + * @param hperh: pointer to a can_handle_t. + * @retval Status, see ald_status_t. + */ +ald_status_t can_sleep(can_handle_t *hperh) +{ + uint32_t tick; + + assert_param(IS_CAN_ALL(hperh->perh)); + + __LOCK(hperh); + hperh->state = CAN_STATE_BUSY; + + CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); + SET_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); + tick = __get_tick(); + + while ((!(READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK))) || READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) + { + if ((__get_tick() - tick) > CAN_TIMEOUT_VALUE) + { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->state = CAN_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral + * is in the normal mode. + * @param hperh: pointer to a can_handle_t structure. + * @retval Status, see ald_status_t. + */ +ald_status_t can_wake_up(can_handle_t *hperh) +{ + uint32_t tick; + + assert_param(IS_CAN_ALL(hperh->perh)); + + __LOCK(hperh); + hperh->state = CAN_STATE_BUSY; + + CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); + tick = __get_tick(); + + while (READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK)) + { + if ((__get_tick() - tick) > CAN_TIMEOUT_VALUE) + { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->state = CAN_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Handles CAN interrupt request + * @param hperh: pointer to a can_handle_t structure. + * @retval None + */ +void can_irq_handler(can_handle_t *hperh) +{ + if (can_get_it_status(hperh, CAN_IT_TME)) + { + if ((can_get_tx_status(hperh, CAN_TX_MAILBOX_0)) + || (can_get_tx_status(hperh, CAN_TX_MAILBOX_1)) + || (can_get_tx_status(hperh, CAN_TX_MAILBOX_2))) + __can_send_by_it(hperh); + } + + if ((can_get_it_status(hperh, CAN_IT_FMP0)) + && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO0) != 0)) + __can_recv_by_it(hperh, CAN_RX_FIFO0); + + if ((can_get_it_status(hperh, CAN_IT_FMP1)) + && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO1) != 0)) + __can_recv_by_it(hperh, CAN_RX_FIFO1); + + if ((can_get_flag_status(hperh, CAN_FLAG_EWG)) + && (can_get_it_status(hperh, CAN_IT_EWG)) + && (can_get_it_status(hperh, CAN_IT_ERR))) + hperh->err |= CAN_ERROR_EWG; + + if ((can_get_flag_status(hperh, CAN_FLAG_EPV)) + && (can_get_it_status(hperh, CAN_IT_EPV)) + && (can_get_it_status(hperh, CAN_IT_ERR))) + hperh->err |= CAN_ERROR_EPV; + + if ((can_get_flag_status(hperh, CAN_FLAG_BOF)) + && (can_get_it_status(hperh, CAN_IT_BOF)) + && (can_get_it_status(hperh, CAN_IT_ERR))) + hperh->err |= CAN_ERROR_BOF; + + if (READ_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK) + && (can_get_it_status(hperh, CAN_IT_LEC)) + && (can_get_it_status(hperh, CAN_IT_ERR))) + { + + switch (READ_BITS(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK, CAN_ERRSTAT_PRERRF_POSS)) + { + case (1): + hperh->err |= CAN_ERROR_STF; + break; + case (2): + hperh->err |= CAN_ERROR_FOR; + break; + case (3): + hperh->err |= CAN_ERROR_ACK; + break; + case (4): + hperh->err |= CAN_ERROR_BR; + break; + case (5): + hperh->err |= CAN_ERROR_BD; + break; + case (6): + hperh->err |= CAN_ERROR_CRC; + break; + default: + break; + } + + CLEAR_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK); + } + + if (hperh->err != CAN_ERROR_NONE) + { + SET_BIT(hperh->perh->IFC, CAN_IFC_ERRIFC_MSK); + hperh->state = CAN_STATE_READY; + + if (hperh->error_cbk != NULL) + hperh->error_cbk(hperh); + } +} + +/** + * @brief Check the transmission status of a CAN Frame. + * @param hperh: pointer to a can_handle_t structure. + * @param box: the index of the mailbox that is used for transmission. + * @retval The new status of transmission(TRUE or FALSE). + */ +type_bool_t can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_TX_MAILBOX(box)); + + switch (box) + { + case CAN_TX_MAILBOX_0: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0REQC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0TXC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) + return FALSE; + + return TRUE; + + case CAN_TX_MAILBOX_1: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1REQC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1TXC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) + return FALSE; + + return TRUE; + + case CAN_TX_MAILBOX_2: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2REQC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2TXC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) + return FALSE; + + return TRUE; + + default: + break; + } + + return FALSE; +} + +/** + * @brief Cancel transmission. + * @param hperh: pointer to a can_handle_t structure. + * @param box: the index of the mailbox that is used for transmission. + * @retval None + */ +void can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_TX_MAILBOX(box)); + + switch (box) + { + case CAN_TX_MAILBOX_0: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0STPREQ_MSK); + break; + case CAN_TX_MAILBOX_1: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1STPREQ_MSK); + break; + case CAN_TX_MAILBOX_2: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2STPREQ_MSK); + break; + default: + break; + } + + return; +} + +/** + * @brief Enable/disable the specified CAN interrupts. + * @param hperh: Pointer to a can_handle_t structure. + * @param it: Specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref can_it_t. + * @param state: New state of the specified CAN interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->IE, it); + else + CLEAR_BIT(hperh->perh->IE, it); + + return; +} + +/** + * @brief Get the status of CAN interrupt source. + * @param hperh: Pointer to a can_handle_t structure. + * @param it: Specifies the CAN interrupt source. + * This parameter can be one of the @ref can_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t can_get_it_status(can_handle_t *hperh, can_it_t it) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IT(it)); + + if (READ_BIT(hperh->perh->IE, it)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of CAN interrupt flag. + * @param hperh: Pointer to a can_handle_t structure. + * @param flag: Specifies the CAN interrupt flag. + * This parameter can be one of the @ref can_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t can_get_flag_status(can_handle_t *hperh, can_flag_t flag) +{ + uint32_t idx = (flag >> 20) & 0x7; + uint32_t _flag = flag & 0xFF8FFFFF; + + assert_param(IS_CAN_GET_FLAG(flag)); + + switch (idx) + { + case 0: + if (READ_BIT(hperh->perh->STAT, _flag)) + return SET; + + break; + case 1: + if (READ_BIT(hperh->perh->TXSTAT, _flag)) + return SET; + + break; + case 2: + if (READ_BIT(hperh->perh->RXF0, _flag)) + return SET; + + break; + case 3: + if (READ_BIT(hperh->perh->RXF1, _flag)) + return SET; + + break; + case 4: + if (READ_BIT(hperh->perh->ERRSTAT, _flag)) + return SET; + + break; + default: + break; + } + + return RESET; +} + +/** @brief Clear the specified CAN pending flag. + * @param hperh: pointer to a can_handle_t structure. + * @param flag: specifies the flag to check. + * @retval None. + */ +void can_clear_flag(can_handle_t *hperh, can_flag_t flag) +{ + uint32_t idx = (flag >> 20) & 0x7; + uint32_t _flag = flag & 0xFF8FFFFF; + + assert_param(IS_CAN_CLEAR_FLAG(flag)); + + switch (idx) + { + case 0: + WRITE_REG(hperh->perh->IFC, _flag); + break; + case 1: + WRITE_REG(hperh->perh->TXSTATC, _flag); + break; + case 2: + WRITE_REG(hperh->perh->RXF0C, _flag); + break; + case 3: + WRITE_REG(hperh->perh->RXF1C, _flag); + break; + default: + break; + } + + return; +} +/** + * @} + */ + +/** @defgroup CAN_Public_Functions_Group4 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * + * @verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to: + (+) Check the CAN state. + (+) Check CAN Errors detected during interrupt process + + * @endverbatim + * @{ + */ +/** + * @brief return the CAN state + * @param hperh: pointer to a can_handle_t structure. + * @retval Status, see can_state_t. + */ +can_state_t can_get_state(can_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the CAN error code + * @param hperh: pointer to a can_handle_t structure. + * @retval CAN Error Code + */ +can_error_t can_get_error(can_handle_t *hperh) +{ + return hperh->err; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ + +/** + * @brief Release rx FIFO + * @param hperh: pointer to a can_handle_t structure. + * @param num: Receive fifo number, CAN_RX_FIFO0 or CAN_RX_FIFO1 + * @retval None + */ +static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num) +{ + if (num == CAN_RX_FIFO0) + SET_BIT(hperh->perh->RXF0, CAN_RXF0_FREE_MSK); + else + SET_BIT(hperh->perh->RXF1, CAN_RXF1_FREE_MSK); +} + + +/** + * @brief transmits a CAN frame message using interrupt. + * @param hperh: pointer to a can_handle_t structure. + * @retval Status, see ald_status_t. + */ +static ald_status_t __can_send_by_it(can_handle_t *hperh) +{ + can_interrupt_config(hperh, CAN_IT_TME, DISABLE); + + if (hperh->state == CAN_STATE_BUSY_TX) + { + can_interrupt_config(hperh, CAN_IT_EWG, DISABLE); + can_interrupt_config(hperh, CAN_IT_EPV, DISABLE); + can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); + can_interrupt_config(hperh, CAN_IT_LEC, DISABLE); + can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); + } + + CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK); + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return OK; +} + +/** + * @brief Receives a correct CAN frame using interrupt. + * @param hperh: Pointer to a can_handle_t structure. + * @param num: Specify the FIFO number + * @retval Status, see ald_status_t. + */ +static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num) +{ + uint32_t stid, exid; + + stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS); + exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS); + hperh->rx_msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS); + + if (hperh->rx_msg->type == CAN_ID_STD) + hperh->rx_msg->std = stid; + else + hperh->rx_msg->ext = (stid << 18) | exid; + + hperh->rx_msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS); + hperh->rx_msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS); + hperh->rx_msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS); + hperh->rx_msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF; + hperh->rx_msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF; + hperh->rx_msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF; + hperh->rx_msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF; + hperh->rx_msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF; + hperh->rx_msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF; + hperh->rx_msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF; + hperh->rx_msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF; + + if (num == CAN_RX_FIFO0) + { + can_rx_fifo_release(hperh, CAN_RX_FIFO0); + can_interrupt_config(hperh, CAN_IT_FMP0, DISABLE); + } + else + { + can_rx_fifo_release(hperh, CAN_RX_FIFO1); + can_interrupt_config(hperh, CAN_IT_FMP1, DISABLE); + } + + if (hperh->state == CAN_STATE_BUSY_RX) + { + can_interrupt_config(hperh, CAN_IT_EWG, DISABLE); + can_interrupt_config(hperh, CAN_IT_EPV, DISABLE); + can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); + can_interrupt_config(hperh, CAN_IT_LEC, DISABLE); + can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); + } + + CLEAR_BIT(hperh->state, CAN_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + + return OK; +} +/** + * @} + */ + +#endif /* ALD_CAN */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c new file mode 100644 index 0000000000..88fc71952a --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c @@ -0,0 +1,1101 @@ +/** + ********************************************************************************* + * + * @file ald_cmu.c + * @brief CMU module driver. + * + * @version V1.0 + * @date 22 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** System clock configure *** + ================================= + [..] + (+) If you don't change system clock, you can using cmu_clock_config_default() API. + It will select HRC as system clock. The system clock is 24MHz. + (+) If you want to change system clock, you can using cmu_clock_config() API. + You can select one of the following as system clock: + @ref CMU_CLOCK_HRC 2MHz or 24MHz + @ref CMU_CLOCK_LRC 32768Hz + @ref CMU_CLOCK_LOSC 32768Hz + @ref CMU_CLOCK_PLL1 32MHz, 48MHz or (32768*1024)Hz + @ref CMU_CLOCK_HOSC 1MHz -- 24MHz + (+) If you select CMU_CLOCK_PLL1 as system clock, it must config the PLL1 + using cmu_pll1_config() API. The input of clock must be 4MHz or PLL2. + (+) If you get current clock, you can using cmu_get_clock() API. + + *** BUS division control *** + =================================== + + PLCK sys_clk hclk1 + -------DIV_SYS-----------+------DIV_AHB1------------Peripheral(GPIO, CRC, ... etc.) + | + | pclk1 + +------DIV_APB1------------Peripheral(TIM, UART, ... etc.) + | + | pclk2 + +------DIV_APB2------------Peripheral(ADC, WWDT, ... etc.) + + [..] + (+) Configure the division using cmu_div_config() API. + (+) Get sys_clk using cmu_get_sys_clock() API. + (+) Get hclk1 using cmu_get_hclk1_clock() API. + (+) Get pclk1 using cmu_get_pclk1_clock() API. + (+) Get pclk2 using cmu_get_pclk2_clock() API. + + *** Clock safe configure *** + =================================== + [..] + (+) If you select CMU_CLOCK_HOSC as system clock, you need enable + clock safe using cmu_hosc_safe_config() API. It will change + CMU_CLOCK_HRC as system clock, when the outer crystal stoped. + (+) If you select CMU_CLOCK_LOSC as system clock, you need enable + clock safe using cmu_losc_safe_config() API. It will change + CMU_CLOCK_LRC as system clock, when the outer crystal stoped. + (+) If you select CMU_CLOCK_PLL1 as system clock, you need enable + clock safe using cmu_pll_safe_config() API. It will change + CMU_CLOCK_HRC as system clock, when the pll1 is lose. + (+) The cmu_irq_cbk() will be invoked, when CMU interrupt has + been occurred. You can overwrite this function in application. + + *** Clock output configure *** + =================================== + [..] + (+) Output high-speed clock using cmu_output_high_clock_config() API. + (+) Output low-speed clock using cmu_output_low_clock_config() API. + + *** Peripheral clock configure *** + =================================== + [..] + (+) Configure buzz clock using cmu_buzz_config() API. + (+) Selected lptim0 clock using cmu_lptim0_clock_select() API. + (+) Selected lpuart clock using cmu_lpuart0_clock_select() API. + (+) Selected lcd clock using cmu_lcd_clock_select() API. + (+) Enable/Disable peripheral clock using cmu_perh_clock_config() API. + + *** CMU ALD driver macros list *** + ============================================= + [..] + Below the list of most used macros in CMU driver. + + (+) CMU_LOSC_ENABLE(): Enable outer low crystal(32768Hz). + (+) CMU_LOSC_DISABLE(): Disable outer low crystal(32768Hz). + (+) CMU_LRC_ENABLE(): Enable LRC(32768Hz). + (+) CMU_LRC_DISABLE(): Disable LRC(32768Hz). + (+) CMU_ULRC_ENABLE(): Enable ULRC(10KHz). + (+) CMU_ULRC_DISABLE(): Disable ULRC(10KHz). + (+) CMU_LP_LRC_ENABLE(): Enable low power LRC(32768Hz). + (+) CMU_LP_LRC_DISABLE(): Disable low power LRC(32768Hz). + (+) CMU_LP_LOSC_ENABLE(): Enable low power LOSC(32768Hz). + (+) CMU_LP_LOSC_DISABLE(): Disable low power LOSC(32768Hz). + (+) CMU_LP_HRC_ENABLE(): Enable low power HRC(2MHz or 24MHz). + (+) CMU_LP_HRC_DISABLE(): Disable low power HRC(2MHz OR 24MHz). + (+) CMU_LP_HOSC_ENABLE(): Enable low power HOSC(1MHz -- 24MHz). + (+) CMU_LP_HOSC_DISABLE(): Disable low power HOSC(1MHz -- 24MHz). + + [..] + (@) You can refer to the CMU driver header file for used the macros + + @endverbatim + ****************************************************************************** + */ + +#include "ald_cmu.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CMU CMU + * @brief CMU module driver + * @{ + */ + +/** + * @defgroup CMU_Private_Variables CMU Private Variables + * @{ + */ +uint32_t __system_clock = 24000000; +/** + * @} + */ + +/** @defgroup CMU_Private_Functions CMU Private Functions + * @{ + */ + +/** + * @brief Update the current system clock. This function + * will be invoked, when system clock has changed. + * @param clock: The new clock. + * @retval None + */ + +static void cmu_clock_update(uint32_t clock) +{ + __system_clock = clock; + + if (clock > 1000000) + __init_tick(TICK_INT_PRIORITY); + + return; +} + +/** + * @brief CMU module interrupt handler + * @retval None + */ +void CMU_Handler(void) +{ + /* HOSC stop */ + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) + { + SYSCFG_UNLOCK(); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); + SYSCFG_LOCK(); + + if ((READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) + || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) + cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); + cmu_irq_cbk(CMU_HOSC_STOP); + } + + /* HOSC start */ + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) + { + SYSCFG_UNLOCK(); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK); + SYSCFG_LOCK(); + + if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))) + cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000); + cmu_irq_cbk(CMU_HOSC_START); + } + + /* LOSC stop */ + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK)) + { + SYSCFG_UNLOCK(); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); + SYSCFG_LOCK(); + cmu_irq_cbk(CMU_LOSC_STOP); + } + + /* LOSC start */ + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIE_MSK)) + { + SYSCFG_UNLOCK(); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK); + SYSCFG_LOCK(); + cmu_irq_cbk(CMU_LOSC_START); + } + + /* PLL1 lose */ + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) + { + SYSCFG_UNLOCK(); + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); + SYSCFG_LOCK(); + + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_CLKS_MSK) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) + || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) + cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); + cmu_irq_cbk(CMU_PLL1_UNLOCK); + } + + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions CMU Public Functions + * @{ + */ + +/** @defgroup CMU_Public_Functions_Group1 System clock configuration + * @brief System clock configuration functions + * + * @verbatim + ============================================================================== + ##### System clock Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure system clock using default parameters. + (+) Configure system clock using specified parameters. + (+) Configure PLL1 using specified parameters. + (+) Get system clock. + + @endverbatim + * @{ + */ + +/** + * @brief Configure system clock using default. + * Select CMU_CLOCK_HRC(24MHz) as system clock and + * enable CMU_CLOCK_LRC(32768Hz). + * @retval The status of ALD. + */ +ald_status_t cmu_clock_config_default(void) +{ + uint32_t cnt = 4000, tmp; + + SYSCFG_UNLOCK(); + + /* Select HRC */ + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) + { + SYSCFG_LOCK(); + return ERROR; + } + + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); /* Select 24Mhz */ + + tmp = READ_REG(CMU->CLKENR); + /* Enable HRC/LRC/LOSC */ + SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK | CMU_CLKENR_LOSCEN_MSK); + WRITE_REG(CMU->CLKENR, tmp); + + SYSCFG_LOCK(); + return OK; +} + +/** + * @brief Configure system clock using specified parameters + * @param clk: The parameter can be one of the following: + * @arg @ref CMU_CLOCK_HRC 2MHz or 24MHz + * @arg @ref CMU_CLOCK_LRC 32768Hz + * @arg @ref CMU_CLOCK_LOSC 32768Hz + * @arg @ref CMU_CLOCK_PLL1 32MHz, 48MHz or (32768*1024)Hz + * @arg @ref CMU_CLOCK_HOSC 1MHz -- 24MHz + * @param clock: The clock which will be set. the value depends + * on the parameter of clk. + * @retval The status of ALD. + */ +ald_status_t cmu_clock_config(cmu_clock_t clk, uint32_t clock) +{ + uint32_t cnt = 4000; + + assert_param(IS_CMU_CLOCK(clk)); + SYSCFG_UNLOCK(); + + switch (clk) + { + case CMU_CLOCK_HRC: + assert_param(clock == 24000000 || clock == 2000000); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) + { + SYSCFG_LOCK(); + return ERROR; + } + + if (clock == 24000000) + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); + else + SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); + + for (cnt = 4000; cnt; --cnt); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt)); + + cmu_clock_update(clock); + break; + + case CMU_CLOCK_LRC: + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) + { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); + + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); + + cmu_clock_update(32768); + break; + + case CMU_CLOCK_LOSC: + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) + { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); + + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt)); + + cmu_clock_update(32768); + break; + + case CMU_CLOCK_PLL1: + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) + { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); + + for (cnt = 4000; cnt; --cnt); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); + + cmu_clock_update(clock); + break; + + case CMU_CLOCK_HOSC: + assert_param(clock <= 24000000); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) + { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1); + + for (cnt = 4000; cnt; --cnt); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + + cmu_clock_update(clock); + break; + + default: + break; + } + + SYSCFG_LOCK(); + return OK; +} + + + +/** + * @brief Configure PLL1 using specified parameters. + * @param input: The input clock type. + * @param output: The output clock which can be 32MHz or 48MHz. + * When input = CMU_PLL1_INPUT_PLL2; then output must be + * CMU_PLL1_OUTPUT_32M, and then the real clock is (32768x1024)Hz. + * @retval None + */ +void cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) +{ + uint32_t cnt = 4000; + + assert_param(IS_CMU_PLL1_INPUT(input)); + assert_param(IS_CMU_PLL1_OUTPUT(output)); + + SYSCFG_UNLOCK(); + + if (input == CMU_PLL1_INPUT_HRC_6) + { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); + } + else if (input == CMU_PLL1_INPUT_PLL2) + { + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); + CLEAR_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2RFS_MSK); + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + } + else + { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + } + + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1RFS_MSK, input << CMU_PLLCFG_PLL1RFS_POSS); + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1OS_MSK, output << CMU_PLLCFG_PLL1OS_POS); + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); + + while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL1LCKN_MSK)) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Gets current system clock. + * @retval The value of system clock. + */ +uint32_t cmu_get_clock(void) +{ + return __system_clock; +} + +/** + * @brief Automatic-calibrate internal clock. + * @param input: input type: HOSC or LOSC. + * @param freq: output frequency: 24MHz or 2MHz. + * @retval The result: + * - 0 Success + * - -1 Failed + */ +int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq) +{ + uint32_t cnt = 5000, tmp; + + assert_param(IS_CMU_AUTO_CALIB_INPUT(input)); + assert_param(IS_CMU_AUTO_CALIB_OUTPUT(freq)); + + SYSCFG_UNLOCK(); + + tmp = READ_REG(CMU->HRCACR); + + MODIFY_REG(tmp, CMU_HRCACR_AC_MSK, 1 << CMU_HRCACR_AC_POSS); + MODIFY_REG(tmp, CMU_HRCACR_RFSEL_MSK, input << CMU_HRCACR_RFSEL_POS); + MODIFY_REG(tmp, CMU_HRCACR_FREQ_MSK, freq << CMU_HRCACR_FREQ_POS); + SET_BIT(tmp, CMU_HRCACR_EN_MSK); + WRITE_REG(CMU->HRCACR, tmp); + + while (cnt--); + cnt = 30000; + while ((READ_BIT(CMU->HRCACR, CMU_HRCACR_BUSY_MSK)) && (--cnt)); + + if (READ_BITS(CMU->HRCACR, CMU_HRCACR_STA_MSK, CMU_HRCACR_STA_POSS) != 1) + { + CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK); + SYSCFG_LOCK(); + return -1; + } + + SET_BIT(CMU->HRCACR, CMU_HRCACR_WRTRG_MSK); + CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK); + SYSCFG_LOCK(); + + return 0; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group2 BUS division control + * @brief BUS division control functions + * + * @verbatim + ============================================================================== + ##### BUS division control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure the bus division. + (+) Get ahb1 clock. + (+) Get sys bus clock. + (+) Get apb1 clock. + (+) Get apb2 clock. + + @endverbatim + * @{ + */ + +/** + * @brief Configure the bus division. + * @param bus: The type of bus: + * @arg CMU_HCLK_1 + * @arg CMU_SYS + * @arg CMU_PCLK_1 + * @arg CMU_PCLK_2 + * @param div: The value of divider. + * @retval None + */ +void cmu_div_config(cmu_bus_t bus, cmu_div_t div) +{ + assert_param(IS_CMU_BUS(bus)); + assert_param(IS_CMU_DIV(div)); + + SYSCFG_UNLOCK(); + + switch (bus) + { + case CMU_HCLK_1: + MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS); + break; + + case CMU_SYS: + MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); + break; + + case CMU_PCLK_1: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS); + break; + + case CMU_PCLK_2: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS); + break; + + default: + break; + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Get AHB1 clock. + * @retval The value of AHB1 clock. + */ +uint32_t cmu_get_hclk1_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, CMU_CFGR_HCLK1DIV_POSS); + + return (__system_clock >> sys_div) >> ahb_div; +} + +/** + * @brief Get SYS clock + * @retval The value of SYS clock + */ +uint32_t cmu_get_sys_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + + return __system_clock >> sys_div; +} + +/** + * @brief Get APB1 clock. + * @retval The value of APB1 clock. + */ +uint32_t cmu_get_pclk1_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t apb1_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, CMU_CFGR_PCLK1DIV_POSS); + + return (__system_clock >> sys_div) >> apb1_div; +} + +/** + * @brief Get APB2 clock. + * @retval The value of APB2 clock. + */ +uint32_t cmu_get_pclk2_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t apb2_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, CMU_CFGR_PCLK2DIV_POSS); + + return (__system_clock >> sys_div) >> apb2_div; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group3 Clock safe configure + * @brief Clock safe configure functions + * + * @verbatim + ============================================================================== + ##### Clock safe configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable outer high crystal safe mode. + (+) Enable/Disable outer low crystal safe mode. + (+) Enable/Disable PLL1 safe mode. + (+) Interrupt callback function. + + @endverbatim + * @{ + */ + +/** + * @brief Enable/Disable outer high crystal safe mode. + * @param clock: the value of outer crystal frequency. + * @param status: The new status. + * @retval None + */ +void cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) +{ + assert_param(IS_CMU_HOSC_RANGE(clock)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) + { + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); + MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clock << CMU_HOSMCR_FRQS_POSS); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); + + mcu_irq_config(CMU_IRQn, 3, ENABLE); + } + else + { + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); + + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) + mcu_irq_config(CMU_IRQn, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Enable/Disable outer low crystal safe mode. + * @param status: The new status. + * @retval None + */ +void cmu_losc_safe_config(type_func_t status) +{ + assert_param(IS_FUNC_STATE(status)); + SYSCFG_UNLOCK(); + + if (status) + { + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); + + mcu_irq_config(CMU_IRQn, 3, ENABLE); + } + else + { + CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); + CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); + + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) + mcu_irq_config(CMU_IRQn, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Enable/Disable PLL1 safe mode. + * @param status: The new status. + * @retval None + */ +void cmu_pll_safe_config(type_func_t status) +{ + assert_param(IS_FUNC_STATE(status)); + SYSCFG_UNLOCK(); + + if (status) + { + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); + MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS); + SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); + + mcu_irq_config(CMU_IRQn, 3, ENABLE); + } + else + { + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); + + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0) + mcu_irq_config(CMU_IRQn, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Get clock state. + * @param sr: The state type, see @ref cmu_clock_state_t. + * @retval SET/RESET + */ +flag_status_t cmu_get_clock_state(cmu_clock_state_t sr) +{ + assert_param(IS_CMU_CLOCK_STATE(sr)); + + if (READ_BIT(CMU->CLKSR, sr)) + return SET; + + return RESET; +} + +/** + * @brief Interrupt callback function. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void cmu_irq_cbk(cmu_security_t se) +{ + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group4 Clock output configure + * @brief Clock output configure functions + * + * @verbatim + ============================================================================== + ##### Clock output configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure the high-speed clock output. + (+) Configure the low-speed clock output. + + @endverbatim + * @{ + */ + +/** + * @brief Configure the high-speed clock output. + * @param sel: Select the source: + * @arg CMU_OUTPUT_HIGH_SEL_HOSC + * @arg CMU_OUTPUT_HIGH_SEL_LOSC + * @arg CMU_OUTPUT_HIGH_SEL_HRC + * @arg CMU_OUTPUT_HIGH_SEL_LRC + * @arg CMU_OUTPUT_HIGH_SEL_HOSM + * @arg CMU_OUTPUT_HIGH_SEL_PLL1 + * @arg CMU_OUTPUT_HIGH_SEL_PLL2 + * @arg CMU_OUTPUT_HIGH_SEL_SYSCLK + * @param div: The value of divider: + * @arg CMU_OUTPUT_DIV_1 + * @arg CMU_OUTPUT_DIV_2 + * @arg CMU_OUTPUT_DIV_4 + * @arg CMU_OUTPUT_DIV_8 + * @arg CMU_OUTPUT_DIV_16 + * @arg CMU_OUTPUT_DIV_32 + * @arg CMU_OUTPUT_DIV_64 + * @arg CMU_OUTPUT_DIV_128 + * @param status: The new status. + * @retval None + */ +void cmu_output_high_clock_config(cmu_output_high_sel_t sel, + cmu_output_high_div_t div, type_func_t status) +{ + assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel)); + assert_param(IS_CMU_OUTPUT_HIGH_DIV(div)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) + { + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS); + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, div << CMU_CLKOCR_HSCODIV_POSS); + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); + } + else + { + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Configure the low-speed clock output. + * @param sel: Select the source: + * @arg CMU_OUTPUT_LOW_SEL_LOSC + * @arg CMU_OUTPUT_LOW_SEL_LRC + * @arg CMU_OUTPUT_LOW_SEL_LOSM + * @arg CMU_OUTPUT_LOW_SEL_BUZZ + * @arg CMU_OUTPUT_LOW_SEL_ULRC + * @param status: The new status. + * @retval None + */ +void cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status) +{ + assert_param(IS_CMU_OUTPUT_LOW_SEL(sel)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) + { + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS); + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); + } + else + { + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); + } + + SYSCFG_LOCK(); + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group5 Peripheral Clock configure + * @brief Peripheral clock configure functions + * + * @verbatim + ============================================================================== + ##### Peripheral clock configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure buzz clock. + (+) Select lptim0 clock source. + (+) Select lpuart0 clock source. + (+) Select lcd clock source. + (+) Enable/Disable peripheral clock. + + @endverbatim + * @{ + */ + +/** + * @brief Configure buzz clock. + * freq = sysclk / (2^(div + 1) * (dat + 1)) + * @param div: The value of divider. + * @param dat: The value of coefficient. + * @param status: The new status. + * @retval None + */ +void cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status) +{ + assert_param(IS_CMU_BUZZ_DIV(div)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) + { + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS); + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS); + SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); + } + else + { + CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Select lptim0 clock source. + * @param clock: The clock source: + * @arg CMU_LP_PERH_CLOCK_SEL_PCLK2 + * @arg CMU_LP_PERH_CLOCK_SEL_PLL1 + * @arg CMU_LP_PERH_CLOCK_SEL_PLL2 + * @arg CMU_LP_PERH_CLOCK_SEL_HRC + * @arg CMU_LP_PERH_CLOCK_SEL_HOSC + * @arg CMU_LP_PERH_CLOCK_SEL_LRC + * @arg CMU_LP_PERH_CLOCK_SEL_LOSC + * @arg CMU_LP_PERH_CLOCK_SEL_ULRC + * @arg CMU_LP_PERH_CLOCK_SEL_HRC_1M + * @arg CMU_LP_PERH_CLOCK_SEL_HOSC_1M + * @arg CMU_LP_PERH_CLOCK_SEL_LOSM + * @arg CMU_LP_PERH_CLOCK_SEL_HOSM + * @retval None + */ +void cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock) +{ + assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); + + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LPTIM0_MSK, clock << CMU_PERICR_LPTIM0_POSS); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Select lpuart0 clock source. + * @param clock: The clock source: + * @arg CMU_LP_PERH_CLOCK_SEL_PCLK2 + * @arg CMU_LP_PERH_CLOCK_SEL_PLL1 + * @arg CMU_LP_PERH_CLOCK_SEL_PLL2 + * @arg CMU_LP_PERH_CLOCK_SEL_HRC + * @arg CMU_LP_PERH_CLOCK_SEL_HOSC + * @arg CMU_LP_PERH_CLOCK_SEL_LRC + * @arg CMU_LP_PERH_CLOCK_SEL_LOSC + * @arg CMU_LP_PERH_CLOCK_SEL_ULRC + * @arg CMU_LP_PERH_CLOCK_SEL_HRC_1M + * @arg CMU_LP_PERH_CLOCK_SEL_HOSC_1M + * @arg CMU_LP_PERH_CLOCK_SEL_LOSM + * @arg CMU_LP_PERH_CLOCK_SEL_HOSM + * @retval None + */ +void cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock) +{ + assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); + + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LPUART0_MSK, clock << CMU_PERICR_LPUART0_POSS); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Select lcd clock source. + * @param clock: The clock source: + * @arg CMU_LCD_SEL_LOSM + * @arg CMU_LCD_SEL_LOSC + * @arg CMU_LCD_SEL_LRC + * @arg CMU_LCD_SEL_ULRC + * @arg CMU_LCD_SEL_HRC_1M + * @arg CMU_LCD_SEL_HOSC_1M + * @retval None + */ +void cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock) +{ + assert_param(IS_CMU_LCD_CLOCK_SEL(clock)); + + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LCD_MSK, clock << CMU_PERICR_LCD_POSS); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Enable/Disable peripheral clock. + * @param perh: The type of peripheral, you can see @ref cmu_perh_t + * @param status: The new status. + * @retval None + */ +void cmu_perh_clock_config(cmu_perh_t perh, type_func_t status) +{ + uint32_t idx, pos; + + assert_param(IS_CMU_PERH(perh)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (perh == CMU_PERH_ALL) + { + if (status) + { + WRITE_REG(CMU->AHB1ENR, ~0); + WRITE_REG(CMU->APB1ENR, ~0); + WRITE_REG(CMU->APB2ENR, ~0); + } + else + { + WRITE_REG(CMU->AHB1ENR, 0); + WRITE_REG(CMU->APB1ENR, 0); + WRITE_REG(CMU->APB2ENR, 0); + } + + SYSCFG_LOCK(); + return; + } + + idx = (perh >> 27) & 0x3; + pos = perh & ~(0x3 << 27); + + if (status) + { + switch (idx) + { + case 0: + SET_BIT(CMU->AHB1ENR, pos); + break; + + case 1: + SET_BIT(CMU->APB1ENR, pos); + break; + + case 2: + SET_BIT(CMU->APB2ENR, pos); + break; + + default: + break; + } + } + else + { + switch (idx) + { + case 0: + CLEAR_BIT(CMU->AHB1ENR, pos); + break; + + case 1: + CLEAR_BIT(CMU->APB1ENR, pos); + break; + + case 2: + CLEAR_BIT(CMU->APB2ENR, pos); + break; + + default: + break; + } + } + + SYSCFG_LOCK(); + return; +} + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c new file mode 100644 index 0000000000..d03a935835 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c @@ -0,0 +1,342 @@ +/** + ********************************************************************************* + * + * @file ald_crc.c + * @brief CRC module driver. + * + * @version V1.0 + * @date 6 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_crc.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC module driver + * @{ + */ +#ifdef ALD_CRC + +/** @addtogroup CRC_Private_Functions CRC Private Functions + * @{ + */ +void crc_reset(crc_handle_t *hperh); +#ifdef ALD_DMA + static void crc_dma_calculate_cplt(void *arg); + static void crc_dma_error(void *arg); +#endif +/** + * @} + */ + + +/** @defgroup CRC_Public_Functions CRC Public Functions + * @{ + */ + +/** @defgroup CRC_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the CRC mode according to the specified parameters in + * the crc_handle_t and create the associated handle. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t crc_init(crc_handle_t *hperh) +{ + uint32_t tmp = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC_MODE(hperh->init.mode)); + assert_param(IS_FUNC_STATE(hperh->init.chs_rev)); + assert_param(IS_FUNC_STATE(hperh->init.data_inv)); + assert_param(IS_FUNC_STATE(hperh->init.data_rev)); + assert_param(IS_FUNC_STATE(hperh->init.chs_inv)); + + crc_reset(hperh); + __LOCK(hperh); + + CRC_ENABLE(hperh); + + tmp = hperh->perh->CR; + + tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) | + (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) | + (CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) | + (1 << CRC_CR_BYTORD_POS)); + + hperh->perh->CR = tmp; + hperh->perh->SEED = hperh->init.seed; + CRC_RESET(hperh); + + hperh->state = CRC_STATE_READY; + + __UNLOCK(hperh); + return OK; +} + +/** + * @} + */ + +/** @defgroup CRC_Public_Functions_Group2 Calculate functions + * @brief Calculate functions + * @{ + */ + +/** + * @brief Calculate the crc value of data. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate + * @retval result, the result of a amount data + */ +uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + hperh->state = CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + CRC->DATA = buf[i]; + + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} +/** + * @} + */ + +#ifdef ALD_DMA +/** @defgroup CRC_Public_Functions_Group3 DMA operation functions + * @brief DMA operation functions + * @{ + */ + +/** + * @brief Calculate an amount of data used dma channel + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param res: Pointer to result + * @param size: Amount of data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != CRC_STATE_READY) + return BUSY; + + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + + hperh->state = CRC_STATE_BUSY; + + hperh->cal_buf = buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; + + dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + dma_config_basic(&(hperh->hdma)); + + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); + + return OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t crc_dma_pause(crc_handle_t *hperh) +{ + __LOCK(hperh); + CRC_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t crc_dma_resume(crc_handle_t *hperh) +{ + __LOCK(hperh); + CRC_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t crc_dma_stop(crc_handle_t *hperh) +{ + __LOCK(hperh); + CRC_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + hperh->state = CRC_STATE_READY; + return OK; +} + +/** + * @} + */ +#endif + +/** @defgroup CRC_Public_Functions_Group4 Peripheral State and Errors functions + * @brief CRC State and Errors functions + * @{ + */ + +/** + * @brief Returns the CRC state. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval CRC state + */ +crc_state_t crc_get_state(crc_handle_t *hperh) +{ + assert_param(IS_CRC(hperh->perh)); + + return hperh->state; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Functions CRC Private Functions + * @brief CRC Private functions + * @{ + */ + +/** + * @brief Reset the CRC peripheral. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval None + */ +void crc_reset(crc_handle_t *hperh) +{ + hperh->perh->DATA = 0x0; + hperh->perh->CR = 0x2; + hperh->perh->SEED = 0xFFFFFFFF; + + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + return; +} + +#ifdef ALD_DMA +/** + * @brief DMA CRC calculate process complete callback. + * @param arg: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval None + */ +static void crc_dma_calculate_cplt(void *arg) +{ + crc_handle_t *hperh = (crc_handle_t *)arg; + + *(hperh->cal_res) = CRC->CHECKSUM; + CRC_DMA_DISABLE(hperh); + + hperh->state = CRC_STATE_READY; + + if (hperh->cal_cplt_cbk) + hperh->cal_cplt_cbk(hperh); +} + +/** + * @brief DMA CRC communication error callback. + * @param arg: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval None + */ +static void crc_dma_error(void *arg) +{ + crc_handle_t *hperh = (crc_handle_t *)arg; + + CRC_CLEAR_ERROR_FLAG(hperh); + CRC_DMA_DISABLE(hperh); + + hperh->state = CRC_STATE_READY; + + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); +} +#endif +/** + * @} + */ + +/** + * @} + */ +#endif /* ALD_CRC */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c new file mode 100644 index 0000000000..4cf2f6e5a9 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c @@ -0,0 +1,1027 @@ +/** + ********************************************************************************* + * + * @file ald_crypt.c + * @brief CRYPT module driver. + * This is the common part of the CRYPT initialization + * + * @version V1.0 + * @date 7 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + + +#include "ald_crypt.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CRYPT CRYPT + * @brief CRYPT module driver + * @{ + */ +#ifdef ALD_CRYPT + +/** @addtogroup CRYPT_Private_Functions CRYPT Private Functions + * @{ + */ +void crypt_reset(crypt_handle_t *hperh); +#ifdef ALD_DMA + static void crypt_dma_crypt_cplt(void *arg); + static void crypt_dma_error(void *arg); +#endif +/** + * @} + */ + + +/** @defgroup CRYPT_Public_Functions CRYPT Public Functions + * @{ + */ + +/** @defgroup CRYPT_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the CRYPT mode according to the specified parameters in + * the crypt_init_t and create the associated handle. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t crypt_init(crypt_handle_t *hperh) +{ + uint32_t tmp = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_MODE(hperh->init.mode)); + + __LOCK(hperh); + crypt_reset(hperh); + + if (hperh->state == CRYPT_STATE_RESET) + __UNLOCK(hperh); + + tmp = hperh->perh->CON; + hperh->step = 4; + tmp |= ((1 << CRYPT_CON_FIFOODR_POS) | (hperh->init.mode << CRYPT_CON_MODE_POSS) | \ + (hperh->init.type << CRYPT_CON_TYPE_POSS) | (1 << CRYPT_CON_FIFOEN_POS)); + WRITE_REG(hperh->perh->CON, tmp); + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Write the Content of KEY. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param key: Pointer to key data buffer + * @retval Status, see @ref ald_status_t. + */ +ald_status_t crypt_write_key(crypt_handle_t *hperh, uint32_t *key) +{ + uint32_t *temp = key; + uint32_t i; + + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; + + if ((hperh == NULL) || (key == NULL)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + hperh->perh->KEY[3] = *temp++; + hperh->perh->KEY[2] = *temp++; + hperh->perh->KEY[1] = *temp++; + hperh->perh->KEY[0] = *temp; + + for (i = 0; i < 4; i++) + hperh->key[i] = *key++; + + return OK; +} + +/** + * @brief Read the Content of KEY. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param key: The pointer to the key + * @retval Status, see @ref ald_status_t. + */ +ald_status_t crypt_read_key(crypt_handle_t *hperh, uint32_t *key) +{ + uint32_t *temp = key; + + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; + + if ((hperh == NULL) || (key == NULL)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + *temp++ = hperh->perh->KEY[3]; + *temp++ = hperh->perh->KEY[2]; + *temp++ = hperh->perh->KEY[1]; + *temp = hperh->perh->KEY[0]; + + return OK; +} + +/** + * @brief Write the Content of IV if you use CBC mode + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param iv: Pointer to iv data buffer + * @retval Status, see @ref ald_status_t. + */ +ald_status_t crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv) +{ + uint32_t *temp = iv; + uint32_t i; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; + + if ((hperh == NULL) || (iv == NULL)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + hperh->perh->IV[3] = *temp++; + hperh->perh->IV[2] = *temp++; + hperh->perh->IV[1] = *temp++; + hperh->perh->IV[0] = *temp; + + for (i = 0; i < 4; i++) + hperh->iv[i] = *iv++; + + CRYPT_IVEN_ENABLE(hperh); + return OK; +} + +/** + * @brief Read the Content of IV. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param iv: Pointer to iv data buffer + * @retval Status, see @ref ald_status_t. + */ +ald_status_t crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv) +{ + uint32_t *temp = iv; + + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; + + if ((hperh == NULL) || (iv == NULL)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + *temp++ = hperh->perh->IV[3]; + *temp++ = hperh->perh->IV[2]; + *temp++ = hperh->perh->IV[1]; + *temp = hperh->perh->IV[0]; + + return OK; +} + +/** + * @} + */ + +/** @defgroup CRYPT_Public_Functions_Group2 Encrypt or Decrypt functions + * @brief Encrypt or Decrypt functions + * @{ + */ + +/** + * @brief Encrypt an amount of data in blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of plain data + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 16(ase) + */ +ald_status_t crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) +{ + uint32_t count = 0; + uint32_t i; + uint32_t *plain_buf = (uint32_t *)plain_text; + uint32_t *cipher_buf = (uint32_t *)cipher_text; + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + count = size / (4 * hperh->step); + + while (count--) + { + for (i = 0; i < hperh->step; i++) + { + CRYPT_WRITE_FIFO(hperh, *plain_buf); + plain_buf++; + } + + while (crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); + + for (i = 0; i < hperh->step; i++) + { + *cipher_buf = CRYPT_READ_FIFO(hperh); + cipher_buf++; + } + } + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Decrypt an amount of data in blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param cipher_text: Pointer to cipher data buffer + * @param plain_text: Pointer to plain data buffer + * @param size: Amount of cipher data + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 16(ase) + */ +ald_status_t crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) +{ + uint32_t count = 0; + uint32_t i; + uint32_t *plain_buf = (uint32_t *)plain_text; + uint32_t *cipher_buf = (uint32_t *)cipher_text; + + if (hperh->init.mode == CRYPT_MODE_CTR) + { + return crypt_encrypt(hperh, cipher_text, plain_text, size); + } + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + count = size / (4 * hperh->step); + + while (count--) + { + for (i = 0; i < hperh->step; i++) + { + CRYPT_WRITE_FIFO(hperh, *cipher_buf); + cipher_buf++; + } + + while (crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); + + for (i = 0; i < hperh->step; i++) + { + *plain_buf = CRYPT_READ_FIFO(hperh); + plain_buf++; + } + } + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +void gcm_mul(uint32_t *res, uint32_t *data, uint32_t *iv) +{ + CRYPT->CON = 0; + CRYPT->DATA[0] = data[3]; + CRYPT->DATA[1] = data[2]; + CRYPT->DATA[2] = data[1]; + CRYPT->DATA[3] = data[0]; + CRYPT->IV[0] = iv[3]; + CRYPT->IV[1] = iv[2]; + CRYPT->IV[2] = iv[1]; + CRYPT->IV[3] = iv[0]; + CRYPT->CON |= ((1 << CRYPT_CON_RESCLR_POS) | (3 << CRYPT_CON_MODE_POSS) | \ + (1 << CRYPT_CON_GO_POS)); + + while (READ_BIT(CRYPT->IF, CRYPT_IF_MULTHIF_MSK) == 0); + + res[3] = CRYPT->RES[0]; + res[2] = CRYPT->RES[1]; + res[1] = CRYPT->RES[2]; + res[0] = CRYPT->RES[3]; + + WRITE_REG(CRYPT->IFC, CRYPT_IFC_MULTHIFC_MSK); + return; +} + +/** + * @brief verify an amount of data in gcm mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of cipher data + * @param aadata: Pointer to additional authenticated data buffer + * @param alen: Amount of additional authenticated data + * @param tag: Pointer to authentication tag buffer + * @retval Status, see @ref ald_status_t. + */ +ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag) +{ + uint8_t GCM_HASH_in[0x60] = {0}; + uint8_t ecb[16] = {0}; + uint32_t x_temp[4]; + uint64_t u, v; + uint32_t len = 0; + uint32_t j, i, k; + uint32_t *tag_temp, *cipher_text_temp; + + /* calculate u and v */ + u = 128 * ((size % 16) ? (size / 16 + 1) : size / 16) - size * 8; + v = 128 * ((alen % 16) ? (alen / 16 + 1) : alen / 16) - alen * 8; + + /* get the input of GHASH algorithm,the input:A||0^v||C||0^u||[len(A)]_64||[len(C)]_64 */ + for (i = 0; i < alen; i++) + { + GCM_HASH_in [i] = * (aadata + i); + } + len += alen; + for (i = 0; i < v / 8; i++) + { + GCM_HASH_in[i + len] = 0; + } + len += v / 8; + for (i = 0; i < size; i++) + { + GCM_HASH_in[i + len] = * (cipher_text + i); + } + len += size; + for (i = 0; i < u / 8; i++) + { + GCM_HASH_in[i + len] = 0; + } + len += u / 8; + + for (i = 0; i < 4; i++) + { + GCM_HASH_in[i + len] = 0; + } + len += 4; + + for (i = 0; i < 4; i++) + { + GCM_HASH_in[i + len] = ((alen * 8) >> (8 * i)) & 0xFF; + } + len += 4; + + for (i = 0; i < 4; i++) + { + GCM_HASH_in[i + len] = 0; + } + len += 4; + + for (i = 0; i < 4; i++) + { + GCM_HASH_in[i + len] = ((size * 8) >> (8 * i)) & 0xFF; + } + len += 4; + + CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS); + CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS); + + crypt_encrypt(hperh, ecb, ecb, 16); + + k = len / 16; + for (i = 0; i < 16; i++) + { + tag[i] = 0; + } + + cipher_text_temp = (uint32_t *)GCM_HASH_in; + tag_temp = (uint32_t *)tag; + for (i = 0; i < k; i++) + { + for (j = 0; j < 4; j++) + { + x_temp[j] = (*cipher_text_temp) ^ tag_temp[j]; + ++cipher_text_temp; + } + + gcm_mul((uint32_t *)tag_temp, x_temp, (uint32_t *)ecb); + } + + /* calculate the authentication tag T, + * T = CIPH_K(J0)^S,J0=IV||0^31||1,CIPH_K is the algorithm of AES in ECB mode + */ + tag_temp = (uint32_t *)tag; + crypt_init(hperh); + CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS); + CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS); + crypt_write_key(hperh, hperh->key); + hperh->iv[3] = 1; + crypt_write_ivr(hperh, hperh->iv); + crypt_encrypt(hperh, tag, tag, 16); + + return OK; +} + +/** + * @brief Encrypt an amount of data in non-blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of plain data + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 16(ase) + */ +ald_status_t crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) +{ + uint32_t i; + uint32_t *plain_buf = (uint32_t *)plain_text; + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + hperh->count = hperh->step; + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); + + for (i = 0; i < hperh->step; i++) + { + CRYPT_WRITE_FIFO(hperh, *plain_buf); + ++plain_buf; + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Decrypt an amount of data in non-blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of cipher data + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 16(ase) + */ +ald_status_t crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) +{ + uint32_t i; + uint32_t *cipher_buf = (uint32_t *)cipher_text; + + if (hperh->init.mode == CRYPT_MODE_CTR) + { + return crypt_decrypt_by_it(hperh, cipher_text, plain_text, size); + } + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + hperh->count = hperh->step; + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); + + for (i = 0; i < hperh->step; i++) + { + CRYPT_WRITE_FIFO(hperh, *cipher_buf); + cipher_buf++; + } + + __UNLOCK(hperh); + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Encrypt an amount of data in non-blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of plain data + * @param channel_m2p: Memory to Crypt module DMA channel + * @param channel_p2m: Crypt module to Memory DMA channel + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 16(ase) + */ +ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, + uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) +{ + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if (plain_text == NULL || cipher_text == NULL || size == 0) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + hperh->count = size; + + if (hperh->hdma_m2p.perh == NULL) + hperh->hdma_m2p.perh = DMA0; + if (hperh->hdma_p2m.perh == NULL) + hperh->hdma_p2m.perh = DMA0; + + hperh->hdma_m2p.cplt_arg = NULL; + hperh->hdma_m2p.cplt_cbk = NULL; + hperh->hdma_m2p.err_arg = NULL; + hperh->hdma_m2p.err_cbk = NULL; + + hperh->hdma_p2m.cplt_arg = (void *)hperh; + hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; + hperh->hdma_p2m.err_arg = (void *)hperh; + hperh->hdma_p2m.err_cbk = &crypt_dma_error; + + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + + dma_config_struct(&hperh->hdma_m2p.config); + hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_m2p.config.src = (void *)hperh->plain_text; + hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; + hperh->hdma_m2p.config.size = size / 4; + hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; + hperh->hdma_m2p.config.channel = channel_m2p; + dma_config_basic(&(hperh->hdma_m2p)); + + dma_config_struct(&hperh->hdma_p2m.config); + hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; + hperh->hdma_p2m.config.dst = (void *)hperh->cipher_text; + hperh->hdma_p2m.config.size = size / 4; + hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; + hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; + hperh->hdma_p2m.config.channel = channel_p2m; + dma_config_basic(&(hperh->hdma_p2m)); + + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Decrypt an amount of data in non-blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of cipher data + * @param channel_m2p: Memory to Crypt module DMA channel + * @param channel_p2m: Crypt module to Memory DMA channel + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 16(ase) + */ +ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, + uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) +{ + if (hperh->init.mode == CRYPT_MODE_CTR) + return crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m); + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + if (plain_text == NULL || cipher_text == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + hperh->count = size; + + if (hperh->hdma_m2p.perh == NULL) + hperh->hdma_m2p.perh = DMA0; + if (hperh->hdma_p2m.perh == NULL) + hperh->hdma_p2m.perh = DMA0; + + + hperh->hdma_m2p.cplt_arg = NULL; + hperh->hdma_m2p.cplt_cbk = NULL; + hperh->hdma_m2p.err_arg = NULL; + hperh->hdma_m2p.err_cbk = NULL; + + hperh->hdma_p2m.cplt_arg = (void *)hperh; + hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; + hperh->hdma_p2m.err_arg = (void *)hperh; + hperh->hdma_p2m.err_cbk = &crypt_dma_error; + + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + + dma_config_struct(&hperh->hdma_m2p.config); + hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_m2p.config.src = (void *)hperh->cipher_text; + hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; + hperh->hdma_m2p.config.size = size / 4; + hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; + hperh->hdma_m2p.config.channel = channel_m2p; + dma_config_basic(&(hperh->hdma_m2p)); + + dma_config_struct(&hperh->hdma_p2m.config); + hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; + hperh->hdma_p2m.config.dst = (void *)hperh->plain_text; + hperh->hdma_p2m.config.size = size / 4; + hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; + hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; + hperh->hdma_p2m.config.channel = channel_p2m; + dma_config_basic(&(hperh->hdma_p2m)); + + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @} + */ + +/** @defgroup CRYPT_Public_Functions_Group3 DMA operation functions + * @brief DMA operation functions + * @{ + */ + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t crypt_dma_pause(crypt_handle_t *hperh) +{ + __LOCK(hperh); + CRYPT_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + return OK; + +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t crypt_dma_resume(crypt_handle_t *hperh) +{ + __LOCK(hperh); + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t crypt_dma_stop(crypt_handle_t *hperh) +{ + __LOCK(hperh); + CRYPT_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + hperh->state = CRYPT_STATE_READY; + return OK; +} +#endif + +/** + * @brief This function handles CRYPT interrupt request. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval None + */ +void crypt_irq_handle(crypt_handle_t *hperh) +{ + uint32_t i; + uint32_t *in_buf; + uint32_t *out_buf; + + if (READ_BIT(hperh->perh->CON, CRYPT_CON_ENCS_MSK)) + { + in_buf = (uint32_t *)hperh->plain_text + hperh->count; + out_buf = (uint32_t *)hperh->cipher_text + hperh->count - hperh->step; + } + else + { + in_buf = (uint32_t *)hperh->cipher_text + hperh->count; + out_buf = (uint32_t *)hperh->plain_text + hperh->count - hperh->step; + } + + if (crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) + { + crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF); + } + + for (i = 0; i < hperh->step; i++) + *out_buf++ = CRYPT_READ_FIFO(hperh); + + hperh->count += hperh->step; + if (hperh->count > (hperh->size / 4)) + { + hperh->count = 0; + hperh->state = CRYPT_STATE_READY; + + if (hperh->crypt_cplt_cbk) + hperh->crypt_cplt_cbk(hperh); + } + else + { + for (i = 0; i < hperh->step; i++) + { + CRYPT_WRITE_FIFO(hperh, *in_buf++); + } + } +} +/** + * @} + */ + +/** @defgroup CRYPT_Public_Functions_Group4 Peripheral Control functions + * @brief CRYPT control functions + * @{ + */ + +/** + * @brief Enables or disables the specified CRYPT interrupts. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param it: Specifies the CRYPT interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg crypt_it_t: CRYPT interrupt + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state) +{ + assert_param(IS_CRYPT(hperh->perh)); + + if (it == CRYPT_IT_IT) + { + CLEAR_BIT(CRYPT->CON, CRYPT_CON_IE_MSK); + CRYPT->CON |= (state << CRYPT_CON_IE_POS); + } + + return; +} + +/** @brief Check whether the specified CRYPT flag is set or not. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref crypt_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) +{ + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_FLAG(flag)); + + if (CRYPT->IF & flag) + return SET; + + return RESET; +} + +/** @brief Clear the specified CRYPT pending flags. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param flag: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg CRYPT_FLAG_AESIF: AES encrypt or decrypt Complete flag. + * @arg CRYPT_FLAG_DONE: encrypt or decrypt Complete flag. + * @retval None + */ +void crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) +{ + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_FLAG(flag)); + + WRITE_REG(CRYPT->IFC, flag); + return; +} + +/** + * @brief Checks whether the specified CRYPT interrupt has occurred or not. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param it: Specifies the CRYPT interrupt source to check. + * This parameter can be one of the following values: + * @arg crypt_it_t: CRYPT interrupt + * @retval Status + * - SET + * - RESET + */ +it_status_t crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it) +{ + assert_param(IS_CRYPT_IT(it)); + + if (READ_BIT(CRYPT->CON, CRYPT_CON_IE_MSK)) + return SET; + + return RESET; +} + + +/** + * @} + */ + +/** @defgroup CRYPT_Public_Functions_Group5 Peripheral State and Errors functions + * @brief State and Errors functions + * @{ + */ + +/** + * @brief Returns the CRYPT state. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval CRYPT state + */ +crypt_state_t crypt_get_state(crypt_handle_t *hperh) +{ + assert_param(IS_CRYPT(hperh->perh)); + + + return hperh->state; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CRYPT_Private_Functions CRYPT Private Functions + * @brief CRYPT Private functions + * @{ + */ + +/** + * @brief Reset the CRYPT peripheral. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval None + */ +void crypt_reset(crypt_handle_t *hperh) +{ + hperh->perh->DATA[0] = 0x0; + hperh->perh->DATA[1] = 0x0; + hperh->perh->DATA[2] = 0x0; + hperh->perh->DATA[3] = 0x0; + hperh->perh->KEY[0] = 0x0; + hperh->perh->KEY[1] = 0x0; + hperh->perh->KEY[2] = 0x0; + hperh->perh->KEY[3] = 0x0; + hperh->perh->KEY[4] = 0x0; + hperh->perh->KEY[5] = 0x0; + hperh->perh->KEY[6] = 0x0; + hperh->perh->KEY[7] = 0x0; + hperh->perh->IV[0] = 0x0; + hperh->perh->IV[1] = 0x0; + hperh->perh->IV[2] = 0x0; + hperh->perh->IV[3] = 0x0; + hperh->perh->CON = 0x0; + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); +} + +#ifdef ALD_DMA +/** + * @brief DMA CRYPT encrypt or decrypt process complete callback. + * @param arg: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval None + */ +static void crypt_dma_crypt_cplt(void *arg) +{ + crypt_handle_t *hperh = (crypt_handle_t *)arg; + + CRYPT_DMA_DISABLE(hperh); + hperh->count = 0; + hperh->plain_text = NULL; + hperh->cipher_text = NULL; + hperh->size = 0; + + hperh->state = CRYPT_STATE_READY; + + if (hperh->crypt_cplt_cbk) + hperh->crypt_cplt_cbk(hperh); +} + +/** + * @brief DMA CRYPT communication error callback. + * @param arg: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval None + */ +static void crypt_dma_error(void *arg) +{ + crypt_handle_t *hperh = (crypt_handle_t *)arg; + CRYPT_DMA_DISABLE(hperh); + + hperh->count = 0; + hperh->plain_text = NULL; + hperh->cipher_text = NULL; + hperh->size = 0; + + hperh->state = CRYPT_STATE_READY; + + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); +} +#endif +/** + * @} + */ + +/** + * @} + */ +#endif /* ALD_CRYPT */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c new file mode 100644 index 0000000000..9a7d04c392 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c @@ -0,0 +1,744 @@ +/** + ********************************************************************************* + * + * @file ald_dma.c + * @brief DMA module driver. + * + * @version V1.0 + * @date 09 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA driver can be used as follows: + + (#) System initialization invokes dma_init(), mcu_ald_init() --> dma_init(). + + (#) Declare a dma_handle_t handle structure. + + (#) Configure the dma_handle_t structure, you can configure the + dma_config_t structure with the help of dma_config_struct(). + + (#) Enable the DMA Configure: + (##) Memory -- memory: call dma_config_auto(). + (##) Peripheral -- memory: call dma_config_basic(). + (##) If you want use the dma easily, you can do this: + (+++) Memory -- memory: call dma_config_auto_easy(). + (+++) Peripheral -- memory: call dma_config_basic_easy(). + + (#) Enable the DMA request signal: + (##) Memory -- memory: the DMA request signal is request automatic. + (##) Peripheral -- memory: you need enable peripheral request signal. + + (#) If you enable DMA interrupt, the callback will be invoked: + (##) When DMA transfer is completed, the cplt_cbk() will be invoked. + (##) When DMA bus occurs error, the err_cbk() will be invoked. + + (#) If you don't enable the DMA interrupt, you need do this: + (##) Polling the dma_get_flag_status(), this function's parameter is channel + or DMA_ERR. + (+++) When the function's Parameter is channel, if retval is SET, it means + the DMA transfer is completed. at this moment, you can do something, + and then, you need invoke dma_clear_flag_status() to clear flag. + + (+++) When the function's Parameter is DMA_ERR, if retval is SET, it means + the DMA bus occurs error. at this moment, you can do something, + and then, you need invoke dma_clear_flag_status() to clear flag. + + @endverbatim + */ + +#include +#include "ald_conf.h" +#include "ald_dma.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA module driver + * @{ + */ + +#ifdef ALD_DMA +/** @defgroup DMA_Private_Variables DMA Private Variables + * @{ + */ +dma_descriptor_t dma0_ctrl_base[28] __attribute__((aligned(512))); +dma_call_back_t dma0_cbk[6]; +/** + * @} + */ + +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ + +/** + * @brief Configure DMA channel using dma_config_t structure + * @param DMAx: Pointer to DMA peripheral + * @param mode: DMA transfer mode. see @ref dma_cycle_ctrl_t + * @param p: Pointer to dma_cycle_ctrl_t which contains + * DMA channel parameter. see @ref dma_config_t + * @retval None + */ +static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config_t *p) +{ + dma_descriptor_t *descr; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_CYCLECTRL_TYPE(mode)); + assert_param(p->src != NULL); + assert_param(p->dst != NULL); + assert_param(IS_DMA_DATA_SIZE(p->size)); + assert_param(IS_DMA_DATASIZE_TYPE(p->data_width)); + assert_param(IS_DMA_DATAINC_TYPE(p->src_inc)); + assert_param(IS_DMA_DATAINC_TYPE(p->dst_inc)); + assert_param(IS_DMA_ARBITERCONFIG_TYPE(p->R_power)); + assert_param(IS_FUNC_STATE(p->primary)); + assert_param(IS_FUNC_STATE(p->burst)); + assert_param(IS_FUNC_STATE(p->high_prio)); + assert_param(IS_FUNC_STATE(p->iterrupt)); + assert_param(IS_DMA_MSEL_TYPE(p->msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel)); + assert_param(IS_DMA_CHANNEL(p->channel)); + + if (p->primary) + descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + p->channel; + else + descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + p->channel; + + if (p->src_inc == DMA_DATA_INC_NONE) + descr->src = p->src; + else + descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << p->data_width)); + + if (p->dst_inc == DMA_DATA_INC_NONE) + descr->dst = p->dst; + else + descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << p->data_width)); + + descr->ctrl.cycle_ctrl = mode; + descr->ctrl.next_useburst = 0; + descr->ctrl.n_minus_1 = p->size - 1; + descr->ctrl.R_power = p->R_power; + descr->ctrl.src_prot_ctrl = 0, + descr->ctrl.dst_prot_ctrl = 0, + descr->ctrl.src_size = p->data_width; + descr->ctrl.src_inc = p->src_inc; + descr->ctrl.dst_size = p->data_width; + descr->ctrl.dst_inc = p->dst_inc; + + if (p->primary) + WRITE_REG(DMAx->CHPRIALTCLR, (1 << p->channel)); + else + WRITE_REG(DMAx->CHPRIALTSET, (1 << p->channel)); + + if (p->burst) + WRITE_REG(DMAx->CHUSEBURSTSET, (1 << p->channel)); + else + WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << p->channel)); + + if (p->high_prio) + WRITE_REG(DMAx->CHPRSET, (1 << p->channel)); + else + WRITE_REG(DMAx->CHPRCLR, (1 << p->channel)); + + if (p->iterrupt) + SET_BIT(DMAx->IER, (1 << p->channel)); + else + CLEAR_BIT(DMAx->IER, (1 << p->channel)); + + MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSEL_MSK, p->msel << DMA_CH0_SELCON_MSEL_POSS); + MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSIGSEL_MSK, p->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); + return; +} + +/** + * @brief Handle DMA interrupt + * @retval None + */ +void DMA_Handler(void) +{ + uint32_t i, reg = DMA0->IFLAG; + + for (i = 0; i < DMA_CH_COUNT; ++i) + { + if (READ_BIT(reg, (1 << i))) + { + if (dma0_cbk[i].cplt_cbk != NULL) + dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg); + + dma_clear_flag_status(DMA0, i); + } + } + + if (READ_BIT(reg, (1U << DMA_ERR))) + { + dma_clear_flag_status(DMA0, DMA_ERR); + + for (i = 0; i < DMA_CH_COUNT; ++i) + { + if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL)) + dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg); + } + } + + dma0_irq_cbk(); + return; +} +/** + * @} + */ + +/** @defgroup DMA_Public_Functions DMA Public Functions + * @{ + */ + +/** @defgroup DMA_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @verbatim + =================================================================== + + #### Initialization functions #### + + =================================================================== + [..] + This subsection provides two functions to Initilizate DMA: + (+) dma_reset(): Reset the DMA register. + + (+) dma_init(): Initializate the DMA module. this function is + invoked by mcu_ald_init(). + this function do this: + (++) Initializte private variable dma_ctrl_base and dma_cbk. + (++) Reset DMA register. + (++) Set DMA interrupt priority: preempt_prio=1, sub_priority=1 + (++) Enable DMA interrupt. + (++) Enable DMA bus error interrupt. + (++) Configure CTRLBASE resigter. + (++) Enable DMA module. + + (+) dma_config_struct(): Configure dma_config_t + structure using default parameter. + + @endverbatim + * @{ + */ + +/** + * @brief Reset the DMA register + * @param DMAx: Pointer to DMA peripheral + * @retval None + */ +void dma_reset(DMA_TypeDef *DMAx) +{ + uint32_t i; + + assert_param(IS_DMA(DMAx)); + + WRITE_REG(DMAx->CFG, 0x0); + WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF); + WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF); + WRITE_REG(DMAx->CHENCLR, 0xFFF); + WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF); + WRITE_REG(DMAx->CHPRCLR, 0xFFF); + WRITE_REG(DMAx->ERRCLR, 0x1); + WRITE_REG(DMAx->IER, 0x0); + WRITE_REG(DMAx->ICFR, 0x80000FFF); + + for (i = 0; i < DMA_CH_COUNT; ++i) + WRITE_REG(DMAx->CH_SELCON[i], 0x0); + + return; +} + +/** + * @brief DMA module initialization, this function + * is invoked by mcu_ald_init(). + * @param DMAx: Pointer to DMA peripheral + * @retval None + */ +void dma_init(DMA_TypeDef *DMAx) +{ + assert_param(IS_DMA(DMAx)); + + memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base)); + memset(dma0_cbk, 0x0, sizeof(dma0_cbk)); + + dma_reset(DMAx); + NVIC_SetPriority(DMA_IRQn, 2); + NVIC_EnableIRQ(DMA_IRQn); + SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK); + + WRITE_REG(DMAx->CTRLBASE, (uint32_t)&dma0_ctrl_base); + SET_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE_MSK); + + return; +} + +/** + * @brief Configure dma_config_t structure using default parameter. + * User can invoked this function, before configure dma_config_t + * @param p: Pointer to dma_config_t structure, see @ref dma_config_t + * @retval None + */ +void dma_config_struct(dma_config_t *p) +{ + p->data_width = DMA_DATA_SIZE_BYTE; + p->src_inc = DMA_DATA_INC_BYTE; + p->dst_inc = DMA_DATA_INC_BYTE; + p->R_power = DMA_R_POWER_1; + p->primary = ENABLE; + p->burst = DISABLE; + p->high_prio = DISABLE; + p->iterrupt = ENABLE; + + return; +} + +/** + * @} + */ + +/** @defgroup DMA_Public_Functions_Group2 Configure DMA channel functions + * @brief Configure DMA channel functions + * + * @verbatim + =================================================================== + + #### Configure DMA channel functions #### + + =================================================================== + [..] + This subsection provides some functions allowing to configure + DMA channel. Include two type DMA transfer: + (+) Carry data from memory to memory, this mode APIs are: + (++) dma_config_auto(): Configure DMA channel according to + the specified parameter in the dma_handle_t structure. + (++) dma_restart_auto(): Restart DMA transmitted. + (++) dma_config_auto_easy(): Configure DMA channel according + to the specified parameter. If you want use the dma easily, + you can invoke this function. + (+) Carry data from peripheral to memory or from memory to peripheral, + this mode APIs are: + (++) dma_config_basic(): Configure DMA channel according to + the specified parameter in the dma_handle_t structure. + (++) dma_restart_basic(): Restart DMA transmitted. + (++) dma_config_basic_easy(): Configure DMA channel according + to the specified parameter. If you want use the dma easily, + you can invoke this function. + + @endverbatim + * @{ + */ + +/** + * @brief Configure DMA channel according to the specified parameter + * in the dma_handle_t structure. The DMA mode is automatic. + * This mode is used to carry data from memory to memory. + * @param hperh: Pointer to DMA_handle_t structure that contains + * configuration information for specified DMA channel. + * @retval None + */ +void dma_config_auto(dma_handle_t *hperh) +{ + dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; + dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; + dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; + dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; + dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config); + + dma_clear_flag_status(hperh->perh, hperh->config.channel); + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); + + return; +} + +/** + * @brief Restart DMA transmitted. The DMA mode is automatic. + * The other parameters have not changed except 'size' and 'addr'. + * @param hperh: Pointer to DMA_handle_t structure that contains + * configuration information for specified DMA channel. + * @param src: Source data begin pointer + * @param dst: Destination data begin pointer + * @param size: Size. + * @retval None + */ +void dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size) +{ + dma_descriptor_t *descr; + + if (hperh->config.primary) + descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; + else + descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; + + if (src) + { + if (hperh->config.src_inc == DMA_DATA_INC_NONE) + descr->src = src; + else + descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width)); + } + + if (dst) + { + if (hperh->config.dst_inc == DMA_DATA_INC_NONE) + descr->dst = dst; + else + descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width)); + } + + dma_clear_flag_status(hperh->perh, hperh->config.channel); + descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; + descr->ctrl.n_minus_1 = size - 1; + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); + return; +} + + + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is automatic. This mode is used to carry data + * from memory to memory. If User want use the dma easily, + * they can invoke this function. + * @param DMAx: Pointer to DMA peripheral + * @param src: Source data begin pointer + * @param dst: Destination data begin pointer + * @param size: The total number of DMA transfers that DMA cycle contains + * @param channel: Channel index which well be used. + * @param cbk: DMA complete callback function + * + * @retval None + */ +void dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, + uint16_t size, uint8_t channel, void (*cbk)(void *arg)) +{ + dma_handle_t hperh; + + assert_param(IS_DMA(DMAx)); + + dma_config_struct(&hperh.config); + hperh.config.src = src; + hperh.config.dst = dst; + hperh.config.size = size; + hperh.config.msel = DMA_MSEL_NONE; + hperh.config.msigsel = DMA_MSIGSEL_NONE; + hperh.config.channel = channel; + + hperh.perh = DMAx; + hperh.cplt_cbk = cbk; + hperh.cplt_arg = NULL; + hperh.err_cbk = NULL; + + dma_clear_flag_status(DMAx, channel); + dma_config_auto(&hperh); + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter + * in the dma_handle_t structure. The DMA mode is basic. + * This mode is used to carry data from peripheral to memory + * or from memory to peripheral. + * @param hperh: Pointer to dma_handle_t structure that contains + * configuration information for specified DMA channel. + * @retval None + */ +void dma_config_basic(dma_handle_t *hperh) +{ + dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; + dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; + dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; + dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; + + dma_clear_flag_status(hperh->perh, hperh->config.channel); + dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config); + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + + return; +} + +/** + * @brief Restart DMA transmitted. The DMA mode is basic. + * The other parameters have not changed except 'size' and 'addr'. + * @param hperh: Pointer to DMA_handle_t structure that contains + * configuration information for specified DMA channel. + * @param src: Source data begin pointer + * @param dst: Destination data begin pointer + * @param size: Size. + * @retval None + */ +void dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size) +{ + dma_descriptor_t *descr; + + if (hperh->config.primary) + descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; + else + descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; + + if (src) + { + if (hperh->config.src_inc == DMA_DATA_INC_NONE) + descr->src = src; + else + descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width)); + } + + if (dst) + { + if (hperh->config.dst_inc == DMA_DATA_INC_NONE) + descr->dst = dst; + else + descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width)); + } + + dma_clear_flag_status(hperh->perh, hperh->config.channel); + descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; + descr->ctrl.n_minus_1 = size - 1; + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is basic. This mode is used to carry data + * from peripheral to memory or negative direction. If user want + * use the dma easily, they can invoke this function. + * @param DMAx: Pointer to DMA peripheral + * @param src: Source data begin pointer + * @param dst: Destination data begin pointer + * @param size: The total number of DMA transfers that DMA cycle contains + * @param msel: Input source to DMA channel @ref dma_msel_t + * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t + * @param channel: Channel index which well be used + * @param cbk: DMA complete callback function + * + * @retval None + * + */ +void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, + dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) +{ + dma_handle_t hperh; + + assert_param(IS_DMA(DMAx)); + dma_config_struct(&hperh.config); + + if (((uint32_t)src) >= 0x40000000) + hperh.config.src_inc = DMA_DATA_INC_NONE; + + if (((uint32_t)dst) >= 0x40000000) + hperh.config.dst_inc = DMA_DATA_INC_NONE; + + hperh.config.src = src; + hperh.config.dst = dst; + hperh.config.size = size; + hperh.config.msel = msel; + hperh.config.msigsel = msigsel; + hperh.config.channel = channel; + + hperh.perh = DMAx; + hperh.cplt_cbk = cbk; + hperh.cplt_arg = NULL; + hperh.err_cbk = NULL; + + dma_clear_flag_status(DMAx, channel); + dma_config_basic(&hperh); + + return; +} + +/** + * @} + */ + +/** @defgroup DMA_Public_Functions_Group3 DMA Control functions + * @brief DMA control functions + * + * @verbatim + =================================================================== + + #### DMA control functions #### + + =================================================================== + [..] + This subsection provides some functions allowing to control DMA: + (+) dma_channel_config(): Control DMA channel ENABLE/DISABLE. + (+) dma_interrupt_config(): Control DMA channel interrupt ENABLE or + DISABLE. + (+) dma_get_it_status(): Check whether the specified channel + interrupt is SET or RESET. + (+) dma_get_flag_status(): Check whether the specified channel + flag is SET or RESET. + (+) dma_clear_flag_status(): Clear the specified channel + pending flag + + @endverbatim + * @{ + */ + +/** + * @brief Configure channel enable or disable. It will unbind descriptor with + * channel, when channel has been disable. + * @param DMAx: Pointer to DMA peripheral + * @param channel: channel index + * @param state: status of channel: + * @arg ENABLE: Enable the channel + * @arg DISABLE: Disable the channel + * @retval None + */ +void dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) +{ + dma_descriptor_t *descr, *alt_descr; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_FUNC_STATE(state)); + + descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + alt_descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + + if (state) + { + WRITE_REG(DMAx->CHENSET, (1 << channel)); + } + else + { + memset(descr, 0x00, sizeof(dma_descriptor_t)); + memset(alt_descr, 0x00, sizeof(dma_descriptor_t)); + WRITE_REG(DMAx->CH_SELCON[channel], 0x0); + WRITE_REG(DMAx->CHENCLR, (1 << channel)); + } + + return; +} + +/** + * @brief Configure the interrupt enable or disable + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index or DMA_ERR. + * @arg 0~5: Channel index + * @arg DMA_ERR: DMA bus error + * @param state: status of channel: + * @arg ENABLE: Enable the channel + * @arg DISABLE: Disable the channel + * + * @retval None + */ +void dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) +{ + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + SET_BIT(DMAx->IER, (1 << channel)); + else + CLEAR_BIT(DMAx->IER, (1 << channel)); + + return; +} + +/** + * @brief Check whether the specified channel interrupt + * is set or reset + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index or DMA_ERR + * @arg 0~5: Channel index + * @arg DMA_ERR: DMA bus error + * @retval Status: + * - SET: Channel interrupt is set + * - RESET: Channel interrupt is reset + */ +it_status_t dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel) +{ + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + if (READ_BIT(DMAx->IER, (1 << channel))) + return SET; + + return RESET; +} + +/** + * @brief Check whether the specified channel flag + * is set or reset + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index or DMA_ERR + * @arg 0~5: Channel index + * @arg DMA_ERR: DMA bus error + * @retval Status: + * - SET: Channel flag is set + * - RESET: Channel flag is reset + */ +flag_status_t dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel) +{ + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + if (READ_BIT(DMAx->IFLAG, (1 << channel))) + return SET; + + return RESET; +} + +/** + * @brief Clear the specified channel pending flag + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index or DMA_ERR + * @arg 0~5: Channel index + * @arg DMA_ERR: DMA bus error + * @retval None + */ +void dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel) +{ + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + WRITE_REG(DMAx->ICFR, (1 << channel)); + return; +} + +/** + * @brief Interrupt callback function. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void dma0_irq_cbk(void) +{ + return; +} +/** + * @} + */ + +/** + * @} + */ +#endif /* ALD_DMA */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c new file mode 100644 index 0000000000..0b15ad7ca8 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c @@ -0,0 +1,530 @@ +/** + ********************************************************************************* + * + * @file ald_flash.c + * @brief FLASH module driver. + * + * @version V1.0 + * @date 20 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + * + ********************************************************************************* + * @verbatim + ============================================================================== + ##### FLASH Peripheral features ##### + ============================================================================== + [..] + Base address is 0x00000000 + + [..] + FLASH have just one programme mode , word programme. + word programme can programme 8 bytes once ; + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) programme flash using flash_write(uint32_t addr, uint8_t *buf, uint16_t len) + (++) call the function and supply all the three paraments is needs, addr means + the first address to write in this operation, buf is a pointer to the data which + need writing to flash. + + (#) erase flash using flash_erase(uint32_t addr, uint16_t len) + (++) call the function and supply two paraments, addr is the first address to erase, + len is the length to erase + + (#) read flash using flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) + (++) read the flash and save to a buffer, ram_addr is the buffer's first address, + addr is the start reading address in flash, len is the length need read + + @endverbatim + */ + +#include "ald_flash.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH module driver + * @{ + */ + +#ifdef ALD_FLASH + +/** @addtogroup FLASH_Private_Types + * @{ + */ + +/* opration buffer, global variable*/ +static uint8_t write_buf[FLASH_PAGE_SIZE]; +static op_cmd_type OP_CMD = OP_FLASH; + +#if defined ( __ICCARM__ ) + #define __RAMFUNC __ramfunc +#else + #define __RAMFUNC +#endif + +/** + * @} + */ + +/** @defgroup Flash_Private_Functions Flash Private Functions + * @brief Flash Private functions + * @{ + */ + +/** + * @brief Unlock the flash. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC static ald_status_t flash_unlock(void) +{ + uint16_t i; + uint16_t op_cmd = OP_CMD; + + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + return ERROR; + + FLASH_REG_UNLOCK(); + FLASH_IAP_ENABLE(); + FLASH_REQ(); + + for (i = 0; i < 0xFFFF; i++) + { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)) + break; + } + + return i == 0xFFFF ? ERROR : OK; +} + +/** + * @brief Lock the flash. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC static ald_status_t flash_lock(void) +{ + uint16_t i; + uint16_t op_cmd = OP_CMD; + + FLASH_REG_UNLOCK(); + WRITE_REG(MSC->FLASHCR, 0x0); + + for (i = 0; i < 0xFFFF; i++) + { + if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))) + break; + } + + return i == 0xFFFF ? ERROR : OK; +} + +/** + * @brief Erase one page. + * @param addr: The erased page's address + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC static ald_status_t flash_page_erase(uint32_t addr) +{ + uint32_t i; + uint16_t op_cmd = OP_CMD; + + __disable_irq(); + if (flash_unlock() != OK) + goto end; + + if (op_cmd == OP_FLASH) + { + CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); + } + else + { + SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); + } + + WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE); + + for (i = 0; i < 0xFFFF; i++) + { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + continue; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK)) + goto end; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK)) + goto end; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK)) + break; + } + + if (i == 0xFFFF) + goto end; + + if (flash_lock() == ERROR) + goto end; + + __enable_irq(); + return OK; +end: + + if (flash_lock() == ERROR) + while (1); + + __enable_irq(); + return ERROR; +} + +/** + * @brief Programme a word. + * @param addr: The word's address, it is must word align. + * @param data: The 8 bytes data be write. + * @param len: The number of data be write. + * @param fifo: Choose if use fifo. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC static ald_status_t flash_word_program(uint32_t addr, uint32_t data[], uint32_t len, uint32_t fifo) +{ + uint16_t i; + uint16_t prog_len; + uint32_t *p_data = data; + uint16_t op_cmd = OP_CMD; + + __disable_irq(); + if (flash_unlock() != OK) + goto end; + + if (op_cmd == OP_FLASH) + CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + else + SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS); + MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS); + + for (prog_len = 0; prog_len < len; prog_len++) + { + if (fifo) + { + WRITE_REG(MSC->FLASHFIFO, p_data[0]); + WRITE_REG(MSC->FLASHFIFO, p_data[1]); + } + else + { + WRITE_REG(MSC->FLASHDL, p_data[0]); + WRITE_REG(MSC->FLASHDH, p_data[1]); + WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP); + } + + p_data += 2; + + for (i = 0; i < 0xFFFF; i++) + { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + continue; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK)) + break; + } + } + if (i == 0xFFFF) + goto end; + + if (flash_lock() == ERROR) + goto end; + + __enable_irq(); + return OK; +end: + if (flash_lock() == ERROR) + while (1); + + __enable_irq(); + return ERROR; +} + +/** + * @brief Read data from flash, and store in buffer. + * @param ram_addr: The stored buffer's address. + * @param addr: The start address in flash to read. + * @param len: The length of byte to read. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC static ald_status_t __flash_read(uint32_t ram_addr[], uint32_t addr, uint32_t len) +{ + uint32_t i; + + if (!len) + return ERROR; + + for (i = 0; i < len; i++) + { + ram_addr[i] = ((uint32_t *)addr)[i]; + } + + return OK; +} + +/** + * @brief Check whether the flash between the given address section + * have been writen, if it have been writen, return TRUE, else + * return FALSE. + * @param begin_addr: The begin address. + * @param end_addr: The end address. + * @retval The check result + * - TRUE + * - FALSE + */ +__RAMFUNC static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr) +{ + uint8_t *addr_to_read; + uint8_t value; + uint32_t index; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(begin_addr)); + assert_param(IS_FLASH_ADDRESS(end_addr)); + + addr_to_read = (uint8_t *)begin_addr; + index = begin_addr; + value = 0xFF; + + if (begin_addr > end_addr) + return FALSE; + + while (index++ <= end_addr) + { + value = *addr_to_read++; + + if (value != 0xFF) + break; + } + + return value == 0xFF ? FALSE : TRUE; +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @verbatim + =============================================================================== + ##### Flash oprate functions ##### + =============================================================================== + [..] + This section provides functions allowing to operate flash, such as read and write. + + @endverbatim + * @{ + */ + +/** + * @brief Write the give bytes to the given address section. + * @param addr: The start address to write. + * @param buf: The bytes' address. + * @param len: The length to write,and multiple of 2. + * @retval Status, see @ref ald_status_t. + */ + +__RAMFUNC ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len) +{ + uint32_t index = 0; + uint32_t para = 0; + uint32_t index2 = 0; + uint32_t start_write_addr; + uint32_t end_write_addr; + uint32_t start_word_addr; + uint32_t end_word_addr; + uint16_t len_to_write; + uint32_t len_index; + type_bool_t need_erase_page; + + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + len_to_write = len; + + while (len_to_write > 0) + { + need_erase_page = FALSE; + + for (index = 0; index < FLASH_PAGE_SIZE; index++) + write_buf[index] = 0xFF; + + start_write_addr = addr + (len - len_to_write); + end_write_addr = addr + len - 1; + end_write_addr = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr) + ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr); + need_erase_page = page_have_writen(FLASH_WORD_ADDR(start_write_addr), + FLASH_WORDEND_ADDR(end_write_addr)); + + if (need_erase_page) + { + if (ERROR == __flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr), + FLASH_PAGE_SIZE >> 2)) + return ERROR; + + if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) + return ERROR; + + para = end_write_addr & (FLASH_PAGE_SIZE - 1); + index = start_write_addr & (FLASH_PAGE_SIZE - 1); + index2 = len - len_to_write; + + while (index <= para) + write_buf[index++] = buf[index2++]; + + index2 = 0; + index = FLASH_PAGE_ADDR(start_write_addr); + para = FLASH_PAGE_ADDR(start_write_addr) + FLASH_PAGE_SIZE; + len_index = FLASH_PAGE_SIZE; + } + else + { + para = end_write_addr & (FLASH_PAGE_SIZE - 1); + index = start_write_addr & (FLASH_PAGE_SIZE - 1); + index2 = len - len_to_write; + + while (index <= para) + write_buf[index++] = buf[index2++]; + + start_word_addr = FLASH_WORD_ADDR(start_write_addr); + end_word_addr = FLASH_WORDEND_ADDR(end_write_addr); + index2 = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr)); + index = start_word_addr; + len_index = end_word_addr - start_word_addr + 1; + } + + if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) + return ERROR; + + len_to_write = len_to_write - (end_write_addr - start_write_addr + 1); + } + + return OK; +} + +/** + * @brief erase The flash between the given address section. + * @param addr: The start address to erase. + * @param len: The length to erase. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC ald_status_t flash_erase(uint32_t addr, uint16_t len) +{ + int32_t index; + int32_t para; + int32_t start_erase_addr; + int32_t end_erase_addr; + uint16_t len_not_erase; + uint32_t len_index; + type_bool_t page_need_save; + + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + len_not_erase = len; + + while (len_not_erase > 0) + { + page_need_save = FALSE; + + start_erase_addr = addr + len - len_not_erase; + end_erase_addr = addr + len - 1; + end_erase_addr = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr)) + ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr); + + if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) + { + if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1))) + page_need_save = TRUE; + } + if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) + { + if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr))) + page_need_save = TRUE; + } + + if (page_need_save) + { + if (ERROR == __flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr), + FLASH_PAGE_SIZE >> 2)) + { + __enable_irq(); + return ERROR; + } + } + + if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) + { + __enable_irq(); + return ERROR; + } + + if (page_need_save) + { + para = end_erase_addr & (FLASH_PAGE_SIZE - 1); + index = start_erase_addr & (FLASH_PAGE_SIZE - 1); + + while (index <= para) + write_buf[index++] = 0xFF; + + index = FLASH_PAGE_ADDR(start_erase_addr); + len_index = FLASH_PAGE_SIZE; + if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) + { + __enable_irq(); + return ERROR; + } + } + len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1); + } + + return OK; +} + +/** + * @brief read the specified length bytes from flash, and store to the specified area. + * @param ram_addr: the specified area to store the reading bytes. + * @param addr: the start address. + * @param len: the length to read. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC ald_status_t flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) +{ + uint32_t temp; + + assert_param(IS_4BYTES_ALIGN(ram_addr)); + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + temp = (uint32_t)ram_addr; + + if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0)) + return ERROR; + + return __flash_read(ram_addr, addr, len) == ERROR ? ERROR : OK; +} + +/** + * @} + */ + +#endif + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c new file mode 100644 index 0000000000..e1d95dca31 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c @@ -0,0 +1,645 @@ +/** + ********************************************************************************* + * + * @file ald_gpio.c + * @brief GPIO module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization functions + * + IO operation functions + * + Control functions + * + * @version V1.0 + * @date 07 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + * @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each + port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software + in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) External interrupt/event lines + + [..] + During and just after reset, the external interrupt lines are not active and + the I/O ports are configured Analog mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output mode, each IO can be configured on open-drain or push-pull + type and the Output driver can be selected depending on ODRV register. + + [..] + In Input mode, each IO can select filter function. + + [..] + Each IO can select TTL or SMIT type. + + [..] + Each IO have up to eight functions, user can configure the functions depend + on the user's environment. + + [..] + Each IO can be locked. Once locked, uesr can only change the output data. + Only when the CPU reset to unlock the GPIO port. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + Each input line can be independently configured to select the type (event or interrupt) and + the corresponding trigger event (rising or falling). Each line can also masked + independently. A pending register maintains the status line of the interrupt requests. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO clock. + + (#) Configure the GPIO pin(s) using gpio_init(). + (++) Configure the IO mode using "mode" member from gpio_init_t structure + (++) Activate Pull-up, Pull-down resistor using "pupd" member from gpio_init_t + structure. + (++) In Output mode, configured on open-drain or push-pull using "odos" + member from gpio_init_t structure. + (++) In Output mode, configured output driver using "odrv" member + from gpio_init_t structure. + (++) In Input mode, configured filter function using "flt" member + from gpio_init_t structure. + (++) Configured type using "type" member from gpio_init_t structure. + (++) Configured functions using "func" member from gpio_init_t structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + + (#) Configure the GPIO pin(s) using gpio_init_default(). + (++) Configure GPIO pin using default param: + init.mode = GPIO_MODE_OUTPUT; + init.odos = GPIO_PUSH_PULL; + init.pupd = GPIO_PUSH_UP; + init.odrv = GPIO_OUT_DRIVE_NORMAL; + init.flt = GPIO_FILTER_DISABLE; + init.type = GPIO_TYPE_TTL; + init.func = GPIO_FUNC_1; + + (#) In case of external interrupt/event mode selection, user need invoke + gpio_exti_init() to configure some param. And then invoke + gpio_exti_interrupt_config() to enable/disable external interrupt/event. + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using NVIC_SetPriority() and enable it using + NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use GPIO_read_pin(). + + (#) To set/reset the level of a pin configured in output mode use + gpio_write_pin()/gpio_toggle_pin(). + + (#) To lock pin configuration until next reset use gpio_lock_pin(). + + (#) Configure external interrupt mode and enable/disable using + gpio_exti_interrupt_config(). + + (#) Get external interrupt flag status using gpio_exti_get_flag_status(). + + (#) Clear pending external interrupt flag status using + gpio_exti_clear_flag_status(). + + @endverbatim + */ + +#include "ald_conf.h" +#include "ald_gpio.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO module driver + * @{ + */ + +#ifdef ALD_GPIO + +/** @defgroup GPIO_Public_Functions GPIO Public Functions + * @{ + */ + +/** @defgroup GPIO_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the GPIOs or external + interrupt to be ready for use. + + @endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified + * parameters in the gpio_init_t. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @param init: Pointer to a gpio_init_t structure that can contains + * the configuration information for the specified parameters. + * @retval None + */ +void gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) +{ + uint32_t i, pos, mask, tmp; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_MODE(init->mode)); + assert_param(IS_GPIO_ODOS(init->odos)); + assert_param(IS_GPIO_PUPD(init->pupd)); + assert_param(IS_GPIO_ODRV(init->odrv)); + assert_param(IS_GPIO_FLT(init->flt)); + assert_param(IS_GPIO_TYPE(init->type)); + assert_param(IS_GPIO_FUNC(init->func)); + + for (i = 0; i < 16; ++i) + { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Set PIN mode */ + tmp = READ_REG(GPIOx->MODE); + tmp &= ~mask; + tmp |= (init->mode << pos); + WRITE_REG(GPIOx->MODE, tmp); + + /* Set PIN open-drain or push-pull */ + tmp = READ_REG(GPIOx->ODOS); + tmp &= ~mask; + tmp |= (init->odos << pos); + WRITE_REG(GPIOx->ODOS, tmp); + + /* Set PIN push-up or/and push-down */ + tmp = READ_REG(GPIOx->PUPD); + tmp &= ~mask; + tmp |= (init->pupd << pos); + WRITE_REG(GPIOx->PUPD, tmp); + + /* Set PIN output driver */ + tmp = READ_REG(GPIOx->ODRV); + tmp &= ~mask; + tmp |= (init->odrv << pos); + WRITE_REG(GPIOx->ODRV, tmp); + + /* Get position and 1-bit mask */ + pos = i; + mask = 0x1 << pos; + + /* Set PIN filter enable or disable */ + tmp = READ_REG(GPIOx->FLT); + tmp &= ~mask; + tmp |= (init->flt << pos); + WRITE_REG(GPIOx->FLT, tmp); + + /* Set PIN type ttl or smit */ + tmp = READ_REG(GPIOx->TYPE); + tmp &= ~mask; + tmp |= (init->type << pos); + WRITE_REG(GPIOx->TYPE, tmp); + + /* Configure PIN function */ + pos = i < 8 ? (i << 2) : ((i - 8) << 2); + mask = 0xF << pos; + tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); + tmp &= ~mask; + tmp |= (init->func << pos); + i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); + } + + return; +} + +/** + * @brief Initialize the GPIOx peripheral using the default parameters. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @retval None + */ +void gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + gpio_init_t init; + + /* Fill GPIO_init_t structure with default parameter */ + init.mode = GPIO_MODE_OUTPUT; + init.odos = GPIO_PUSH_PULL; + init.pupd = GPIO_PUSH_UP; + init.odrv = GPIO_OUT_DRIVE_NORMAL; + init.flt = GPIO_FILTER_DISABLE; + init.type = GPIO_TYPE_CMOS; + init.func = GPIO_FUNC_1; + + gpio_init(GPIOx, pin, &init); + return; +} + +/** + * @brief Sets GPIO function to default(func0). + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @retval None + */ +void gpio_func_default(GPIO_TypeDef *GPIOx) +{ + WRITE_REG(GPIOx->FUNC0, 0x00); + WRITE_REG(GPIOx->FUNC1, 0x00); + + return; +} + +/** + * @brief Initialize the external interrupt according to the specified + * parameters in the exti_init_t. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @param init: Pointer to a exti_init_t structure that can contains + * the configuration information for the specified parameters. + * @retval None + */ +void gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) +{ + uint8_t i; + uint8_t port; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_FUNC_STATE(init->filter)); + assert_param(IS_EXTI_FLTCKS_TYPE(init->cks)); + + /* Get GPIO port */ + if (GPIOx == GPIOA) + port = 0x0; + else if (GPIOx == GPIOB) + port = 0x1; + else if (GPIOx == GPIOC) + port = 2; + else if (GPIOx == GPIOD) + port = 3; + else if (GPIOx == GPIOE) + port = 4; + else if (GPIOx == GPIOF) + port = 5; + else if (GPIOx == GPIOG) + port = 6; + else if (GPIOx == GPIOH) + port = 7; + else + port = 0; + + /* Get Pin index */ + for (i = 0; i < 16; ++i) + { + if (((pin >> i) & 0x1) == 0x1) + break; + } + + /* Select external interrupt line */ + if (i <= 7) + { + EXTI->EXTIPSR0 &= ~(0x7 << (i * 4)); + EXTI->EXTIPSR0 |= (port << (i * 4)); + } + else + { + i -= 8; + EXTI->EXTIPSR1 &= ~(0x7 << (i * 4)); + EXTI->EXTIPSR1 |= (port << (i * 4)); + } + + /* Configure filter parameter */ + if (init->filter == ENABLE) + { + SET_BIT(EXTI->EXTIFLTCR, pin); + MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS); + MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS); + } + else + { + CLEAR_BIT(EXTI->EXTIFLTCR, pin); + } + + return; +} +/** + * @} + */ + +/** @defgroup GPIO_Public_Functions_Group2 IO operation functions + * @brief GPIO Read and Write + * + @verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the GPIOs. + + @endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: Specifies the pin to read. + * @retval The input pin value + * - BIT_SET + * - BIT_RESET + */ +uint8_t gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + if (READ_BIT(GPIOx->DIN, pin)) + return BIT_SET; + + else + return BIT_RESET; +} + +/** + * @brief Set or clear the select Pin data. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The specified pin to be written. + * @param val: The specifies value to be written. + * @retval None + */ +void gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + if ((val & (0x01)) == 0x00) + CLEAR_BIT(GPIOx->DOUT, pin); + else + SET_BIT(GPIOx->DOUT, pin); + + return; +} + +/** + * @brief Turn over the select data. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: Specifies the pin to turn over. + * @retval None + */ +void gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + WRITE_REG(GPIOx->BIR, pin); + return; +} + +/** + * @brief Turn over the direction. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: Specifies the pin to turn over. + * @retval None + */ +void gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + uint32_t i, pos, mask, tmp, value; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + for (i = 0; i < 16; ++i) + { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Get the new direction */ + tmp = READ_REG(GPIOx->MODE); + value = (tmp >> pos) & 0x3; + + if ((value == 2) || (value == 3)) + value = 1; + else if (value == 1) + { + value = 2; + } + else + { + continue; /* do nothing */ + } + + /* Set PIN mode */ + tmp &= ~mask; + tmp |= (value << pos); + WRITE_REG(GPIOx->MODE, tmp); + } + + return; +} + +/** + * @brief Lock the GPIO prot. Once locked, can + * only change the output data. Only when the CPU + * reset to unlock the GPIO port. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The specified Pin to be written. + * @retval None + */ +void gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, UNLOCK_KEY << GPIO_LOCK_KEY_POSS); + WRITE_REG(GPIOx->LOCK, pin); + + return; +} + +/** + * @brief Read the specified input port pin. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @retval The value; + */ +uint16_t gpio_read_port(GPIO_TypeDef *GPIOx) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + + return READ_REG(GPIOx->DIN); +} + +/** + * @brief Set or clear the select Pin data. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param val: The specifies value to be written. + * @retval None + */ +void gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + + WRITE_REG(GPIOx->DOUT, val); + return; +} + + +/** + * @} + */ + +/** @defgroup GPIO_Public_Functions_Group3 Control functions + * @brief EXTI Control functions + * + @verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to + control external interrupt. + + @endverbatim + * @{ + */ + +/** + * @brief Configure the interrupt according to the specified parameter. + * @param pin: The Pin which need to configure. + * @param style: External interrupt trigger style. + * @param status: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status) +{ + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_TRIGGER_STYLE(style)); + assert_param(IS_FUNC_STATE(status)); + + if (status == ENABLE) + { + if (style == EXTI_TRIGGER_RISING_EDGE) + { + SET_BIT(EXTI->EXTIRER, pin); + } + else if (style == EXTI_TRIGGER_TRAILING_EDGE) + { + SET_BIT(EXTI->EXTIFER, pin); + } + else if (style == EXTI_TRIGGER_BOTH_EDGE) + { + SET_BIT(EXTI->EXTIRER, pin); + SET_BIT(EXTI->EXTIFER, pin); + } + else + { + ; /* do nothing */ + } + + WRITE_REG(EXTI->EXTICFR, 0xffff); + SET_BIT(EXTI->EXTIEN, pin); + } + else + { + if (style == EXTI_TRIGGER_RISING_EDGE) + { + CLEAR_BIT(EXTI->EXTIRER, pin); + } + else if (style == EXTI_TRIGGER_TRAILING_EDGE) + { + CLEAR_BIT(EXTI->EXTIFER, pin); + } + else if (style == EXTI_TRIGGER_BOTH_EDGE) + { + CLEAR_BIT(EXTI->EXTIRER, pin); + CLEAR_BIT(EXTI->EXTIFER, pin); + } + else + { + ; /* do nothing */ + } + + CLEAR_BIT(EXTI->EXTIEN, pin); + } + + return; +} + +/** + * @brief Get the Flag about external interrupt. + * @param pin: The pin which belong to external interrupt. + * @retval Flag status + * - SET + * - RESET + */ +flag_status_t gpio_exti_get_flag_status(uint16_t pin) +{ + assert_param(IS_GPIO_PIN(pin)); + + if (READ_BIT(EXTI->EXTIFLAG, pin)) + return SET; + + return RESET; +} + +/** + * @brief Clear the external interrupt flag. + * @param pin: The pin which belong to external interrupt. + * @retval None + */ +void gpio_exti_clear_flag_status(uint16_t pin) +{ + assert_param(IS_GPIO_PIN(pin)); + + WRITE_REG(EXTI->EXTICFR, pin); + return; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* ALD_GPIO */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c new file mode 100644 index 0000000000..e285872cf2 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c @@ -0,0 +1,3365 @@ +/** + ********************************************************************************* + * + * @file ald_i2c.c + * @brief I2C module driver. + * + * @version V1.0 + * @date 15 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C driver can be used as follows: + + (#) Declare a i2c_handle_t handle structure, for example: + i2c_handle_t hperh; + + (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, + Dual Addressing mode, Own Address2, General call and Nostretch mode in the hperh init structure. + + (#) Initialize the I2C registers by calling the i2c_init(). + (#) To check if target device is ready for communication, use the function i2c_is_device_ready() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using i2c_master_send() + (+) Receive in master mode an amount of data in blocking mode using i2c_master_recv() + (+) Transmit in slave mode an amount of data in blocking mode using i2c_slave_send() + (+) Receive in slave mode an amount of data in blocking mode using i2c_slave_recv() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using i2c_mem_write() + (+) Read an amount of data in blocking mode from a specific memory address using i2c_mem_read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) The I2C interrupts should have the highest priority in the application in order + to make them uninterruptible. + (+) Transmit in master mode an amount of data in non-blocking mode using i2c_master_send_by_it() + (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_tx_cplt_cbk() + (+) Receive in master mode an amount of data in non-blocking mode using i2c_master_recv_by_it() + (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_rx_cplt_cbk() + (+) Transmit in slave mode an amount of data in non-blocking mode using i2c_slave_send_by_it() + (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() + (+) Receive in slave mode an amount of data in non-blocking mode using i2c_slave_recv_by_it() + (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) The I2C interrupts should have the highest priority in the application in order + to make them uninterruptible. + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + i2c_mem_write_by_it() + (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + i2c_mem_read_by_it() + (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + i2c_master_send_by_dma() + (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_tx_cplt_cbk() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + i2c_master_recv_by_dma() + (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_rx_cplt_cbk() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + i2c_slave_send_by_dma() + (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + i2c_slave_recv_by_dma() + (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + i2c_mem_write_by_dma() + (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + i2c_mem_read_by_dma() + (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + + *** I2C ald_status_t driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C ald_status_t driver. + + (+) I2C_ENABLE: Enable the I2C peripheral + (+) I2C_DISABLE: Disable the I2C peripheral + (@) You can refer to the I2C ald_status_t driver header file for more useful macros + + + *** I2C Workarounds linked to Silicon Limitation *** + ==================================================== + [..] + Below the list of all silicon limitations implemented for library on our product. + (@) See ErrataSheet to know full silicon limitation list of your product. + + (#) Workarounds Implemented inside I2C library + (##) Wrong data read into data register (Polling and Interrupt mode) + (##) Start cannot be generated after a misplaced Stop + (##) Some software events must be managed before the current byte is being transferred: + Workaround: Use DMA in general, except when the Master is receiving a single byte. + For Interupt mode, I2C should have the highest priority in the application. + (##) Mismatch on the "Setup time for a repeated Start condition" timing parameter: + Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if + supported by the slave. + (##) Data valid time (tVD;DAT) violated without the OVR flag being set: + Workaround: If the slave device allows it, use the clock stretching mechanism + by programming no_stretch = I2C_NOSTRETCH_DISABLE in i2c_init. + + @endverbatim + ********************************************************************************* + */ + +#include "ald_i2c.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C module driver + * @{ + */ +#ifdef ALD_I2C + +/** @addtogroup I2C_Private_Constants I2C Private Constants + * @{ + */ +#define I2C_TIMEOUT_FLAG (__systick_interval / 20 + 1) +#define I2C_TIMEOUT_ADDR_SLAVE (__systick_interval * 10) +#define I2C_TIMEOUT_BUSY_FLAG (__systick_interval * 10) +#define I2C_MAX_DELAY 0xFFFFFFFF +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions I2C Private Functions + * @{ + */ +#ifdef ALD_DMA + static void i2c_dma_master_send_cplt(void *argv); + static void i2c_dma_master_recv_cplt(void *argv); + static void i2c_dma_slave_send_cplt(void *argv); + static void i2c_dma_slave_recv_cplt(void *argv); + static void i2c_dma_mem_send_cplt(void *argv); + static void i2c_dma_mem_recv_cplt(void *argv); + static void i2c_dma_error(void *argv); +#endif +static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); +static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); +static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + uint16_t add_size, uint32_t timeout); +static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + uint16_t add_size, uint32_t timeout); +static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, + flag_status_t status, uint32_t timeout); +static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, uint32_t timeout); +static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout); +static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeout); +static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout); +static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeout); +static ald_status_t i2c_is_ack_failed(i2c_handle_t *hperh); +static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh); +static ald_status_t i2c_master_send_btf(i2c_handle_t *hperh); +static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh); +static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh); +static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh); +static ald_status_t i2c_slave_send_btf(i2c_handle_t *hperh); +static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh); +static ald_status_t i2c_slave_recv_btf(i2c_handle_t *hperh); +static ald_status_t i2c_slave_addr(i2c_handle_t *hperh); +static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh); +static ald_status_t i2c_slave_af(i2c_handle_t *hperh); +static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk); +/** + * @} + */ + +/** @defgroup I2C_Public_Functions I2C Public functions + * @{ + */ + +/** @defgroup I2C_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the I2Cx peripheral: + + (+) Call the function i2c_init() to configure the selected device with + the selected configuration: + (++) Communication Speed + (++) Duty cycle + (++) Addressing mode + (++) Own Address 1 + (++) Dual Addressing mode + (++) Own Address 2 + (++) General call mode + (++) Nostretch mode + + (+) Call the function i2c_reset() to restore the default configuration + of the selected I2Cx periperal. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the i2c_init_t and initialize the associated handle. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_init(i2c_handle_t *hperh) +{ + uint32_t freqrange = 0; + uint32_t pclk1 = 0; + + if (hperh == NULL) + return ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_CLOCK_SPEED(hperh->init.clk_speed)); + assert_param(IS_I2C_DUTY_CYCLE(hperh->init.duty)); + assert_param(IS_I2C_OWN_ADDRESS1(hperh->init.own_addr1)); + assert_param(IS_I2C_ADDRESSING_MODE(hperh->init.addr_mode)); + assert_param(IS_I2C_GENERAL_CALL(hperh->init.general_call)); + assert_param(IS_I2C_NO_STRETCH(hperh->init.no_stretch)); + + if (hperh->init.dual_addr == I2C_DUALADDR_ENABLE) + assert_param(IS_I2C_OWN_ADDRESS2(hperh->init.own_addr2)); + + if (hperh->state == I2C_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = I2C_STATE_BUSY; + pclk1 = cmu_get_pclk1_clock(); + I2C_DISABLE(hperh); + + freqrange = I2C_FREQ_RANGE(pclk1); + WRITE_REG(hperh->perh->CON2, freqrange); + WRITE_REG(hperh->perh->RT, I2C_RISE_TIME(freqrange, hperh->init.clk_speed)); + WRITE_REG(hperh->perh->CKCFG, i2c_configure_speed(hperh, pclk1)); + WRITE_REG(hperh->perh->CON1, hperh->init.general_call); + SET_BIT(hperh->perh->CON1, hperh->init.no_stretch); + WRITE_REG(hperh->perh->ADDR1, (hperh->init.addr_mode | hperh->init.own_addr1)); + WRITE_REG(hperh->perh->ADDR2, (hperh->init.dual_addr | hperh->init.own_addr2)); + + I2C_ENABLE(hperh); + + hperh->error_code = I2C_ERROR_NONE; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + return OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_reset(i2c_handle_t *hperh) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + hperh->state = I2C_STATE_BUSY; + I2C_DISABLE(hperh); + + hperh->error_code = I2C_ERROR_NONE; + hperh->state = I2C_STATE_RESET; + hperh->mode = I2C_MODE_NONE; + + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) i2c_master_send() + (++) i2c_master_recv() + (++) i2c_slave_send() + (++) i2c_slave_recv() + (++) i2c_mem_write() + (++) i2c_mem_read() + (++) i2c_is_device_ready() + + (#) No-Blocking mode functions with Interrupt are : + (++) i2c_master_send_by_it() + (++) i2c_master_recv_by_it() + (++) i2c_slave_send_by_it() + (++) i2c_slave_recv_by_it() + (++) i2c_mem_write_by_it() + (++) i2c_mem_read_by_it() + + (#) No-Blocking mode functions with DMA are : + (++) i2c_master_send_by_dma() + (++) i2c_master_recv_by_dma() + (++) i2c_slave_send_by_dma() + (++) i2c_slave_recv_by_dma() + (++) i2c_mem_write_by_dma() + (++) i2c_mem_read_by_dma() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) hperh->mem_tx_cplt_cbk() + (++) hperh->mem_rx_cplt_cbk() + (++) hperh->master_tx_cplt_cbk() + (++) hperh->master_rx_cplt_cbk() + (++) hperh->slave_tx_cplt_cbk() + (++) hperh->slave_rx_cplt_cbk() + (++) hperh->error_callback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint32_t timeout) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + + if (i2c_master_req_write(hperh, dev_addr, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + I2C_CLEAR_ADDRFLAG(hperh); + + while (size > 0) + { + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->perh->DATA = (*buf++); + --size; + + if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) + { + hperh->perh->DATA = (*buf++); + --size; + } + } + + if (i2c_wait_btf_to_timeout(hperh, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return OK; + +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint32_t timeout) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + + if (i2c_master_req_read(hperh, dev_addr, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (size == 1) + { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __enable_irq(); + } + else if (size == 2) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + __disable_irq(); + I2C_CLEAR_ADDRFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __enable_irq(); + } + else + { + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + } + + while (size > 3) + { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_TIMEOUT) + { + __UNLOCK(hperh); + return TIMEOUT; + } + else + { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + --size; + + if (i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) + { + (*buf++) = hperh->perh->DATA; + --size; + } + } + + switch (size) + { + case 1: + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_TIMEOUT) + { + __UNLOCK(hperh); + return TIMEOUT; + } + else + { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + break; + + case 2: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } + + __disable_irq(); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; + + case 3: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + (*buf++) = hperh->perh->DATA; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + __enable_irq(); + return TIMEOUT; + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; + + default : + break; + } + + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + + if (hperh->init.addr_mode == I2C_ADDR_10BIT) + { + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + } + + while (size > 0) + { + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (hperh->error_code == I2C_ERROR_AF) + { + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->perh->DATA = (*buf++); + --size; + + if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) + { + hperh->perh->DATA = (*buf++); + --size; + } + } + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } + + i2c_clear_flag_status(hperh, I2C_FLAG_AF); + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + + while (size > 0) + { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) + { + hperh->perh->CON1 &= ~I2C_CON1_ACKEN; + + if (hperh->error_code == I2C_ERROR_TIMEOUT) + { + __UNLOCK(hperh); + return TIMEOUT; + } + else + { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + --size; + + if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) + { + (*buf++) = hperh->perh->DATA; + --size; + } + } + + if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) + { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + if (hperh->error_code == I2C_ERROR_AF) + { + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + __I2C_CLEAR_STOPFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + I2C_CLEAR_ADDRFLAG(hperh); + + __UNLOCK(hperh); + + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + return OK; +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (hperh->xfer_count == 1) + { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + } + else if (hperh->xfer_count == 2) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + I2C_CLEAR_ADDRFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + } + else + { + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + } + + __UNLOCK(hperh); + + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + return OK; +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __UNLOCK(hperh); + + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + + return OK; +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __UNLOCK(hperh); + + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_master_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + + dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + dma_config_basic(&hperh->hdmatx); + + if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + I2C_CLEAR_ADDRFLAG(hperh); + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_master_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + dma_config_basic(&hperh->hdmarx); + + if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (size == 1) + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + else + SET_BIT(hperh->perh->CON2, I2C_CON2_LDMA); + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + I2C_CLEAR_ADDRFLAG(hperh); + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C Transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_slave_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + + dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + dma_config_basic(&hperh->hdmatx); + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.addr_mode == I2C_ADDR_7BIT) + { + I2C_CLEAR_ADDRFLAG(hperh); + } + else + { + I2C_CLEAR_ADDRFLAG(hperh); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + } + + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_slave_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + dma_config_basic(&hperh->hdmarx); + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + __UNLOCK(hperh); + return OK; +} +#endif + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + while (size > 0) + { + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->perh->DATA = (*buf++); + --size; + + if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) + { + hperh->perh->DATA = (*buf++); + --size; + } + } + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __delay_ms(10); + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint32_t timeout) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + + if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (size == 1) + { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + __enable_irq(); + } + else if (size == 2) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + __disable_irq(); + I2C_CLEAR_ADDRFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __enable_irq(); + } + else + { + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + } + + while (size > 3) + { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_TIMEOUT) + { + __UNLOCK(hperh); + return TIMEOUT; + } + else + { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + --size; + + if (i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) + { + (*buf++) = hperh->perh->DATA; + --size; + } + } + + switch (size) + { + case 1: + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_TIMEOUT) + { + __UNLOCK(hperh); + return TIMEOUT; + } + else + { + __UNLOCK(hperh); + return ERROR; + } + } + + (*buf++) = hperh->perh->DATA; + break; + + case 2: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } + + __disable_irq(); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; + + case 3: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + (*buf++) = hperh->perh->DATA; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + __enable_irq(); + return TIMEOUT; + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; + + default: + break; + } + + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + __UNLOCK(hperh); + + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + + return OK; +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (hperh->xfer_count == 1) + { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + } + else if (hperh->xfer_count == 2) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + I2C_CLEAR_ADDRFLAG(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + } + else + { + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + I2C_CLEAR_ADDRFLAG(hperh); + } + + __UNLOCK(hperh); + + /* Note : The I2C interrupts must be enabled after unlocking current process + * to avoid the risk of I2C interrupt handle execution before current + * process unlock */ + i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_mem_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + dma_config_struct(&hperh->hdmatx.config); + + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + dma_config_basic(&hperh->hdmatx); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be read + * @param channel: DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_MEMADD_size(add_size)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_mem_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + dma_config_struct(&hperh->hdmarx.config); + + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + dma_config_basic(&hperh->hdmarx); + + if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + __UNLOCK(hperh); + return ERROR; + } + else + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (size == 1) + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + else + SET_BIT(hperh->perh->CON2, I2C_CON2_LDMA); + + SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + I2C_CLEAR_ADDRFLAG(hperh); + __UNLOCK(hperh); + return OK; +} +#endif + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param trials: Number of trials + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout) +{ + uint32_t tickstart = 0; + uint32_t tmp1 = 0; + uint32_t tmp2 = 0; + uint32_t tmp3 = 0; + uint32_t I2C_Trials = 1; + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + + __LOCK(hperh); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + + hperh->state = I2C_STATE_BUSY; + hperh->error_code = I2C_ERROR_NONE; + + do + { + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } + + hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); + tickstart = __get_tick(); + tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ADDR); + tmp2 = i2c_get_flag_status(hperh, I2C_FLAG_AF); + tmp3 = hperh->state; + + while ((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != I2C_STATE_TIMEOUT)) + { + if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + hperh->state = I2C_STATE_TIMEOUT; + + tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ADDR); + tmp2 = i2c_get_flag_status(hperh, I2C_FLAG_AF); + tmp3 = hperh->state; + } + hperh->state = I2C_STATE_READY; + + if (i2c_get_flag_status(hperh, I2C_FLAG_ADDR) == SET) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + I2C_CLEAR_ADDRFLAG(hperh); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, + I2C_TIMEOUT_BUSY_FLAG) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } + + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return OK; + } + else + { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + i2c_clear_flag_status(hperh, I2C_FLAG_AF); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, + I2C_TIMEOUT_BUSY_FLAG) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + while (I2C_Trials++ < trials); + + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return OK; +} +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group3 Peripheral Control functions + * @brief Peripheral state and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Enable/disable the specified i2c interrupts. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param it: Specifies the i2c interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref i2c_interrupt_t. + * @param state: New state of the specified i2c interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT((hperh)->perh->CON2, (it)); + else + CLEAR_BIT((hperh)->perh->CON2, (it)); + + return; +} + +/** + * @brief Get the status of I2C_SR register. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param flag: Specifies the I2C status type. + * This parameter can be one of the @ref i2c_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) +{ + flag_status_t state = RESET; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_FLAG(flag)); + + if ((flag & 0xFF0000) == 0) + { + if ((hperh->perh->STAT1 & flag) == flag) + state = SET; + } + else + { + if ((hperh->perh->STAT2 & (flag >> 16)) == (flag >> 16)) + state = SET; + } + + return state; +} + +/** + * @brief Get the status of interrupt. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param it: Specifies the i2c interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref i2c_interrupt_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT_TYPE(it)); + + if ((hperh->perh->CON2 & it) == it) + return SET; + else + return RESET; +} + +/** + * @brief Clear the UART interrupt flag. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval None + */ +void i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_FLAG(flag)); + + if (flag > 65535) + return; + + hperh->perh->STAT1 = (hperh->perh->STAT1 & (~flag)); + + return; + +} + +/** + * @brief Return the I2C handle state. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval ald_status_t state + */ +i2c_state_t i2c_get_state(i2c_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the I2C error code. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t i2c_get_error(i2c_handle_t *hperh) +{ + return hperh->error_code; +} +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group4 IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void i2c_ev_irq_handler(i2c_handle_t *hperh) +{ + uint32_t tmp1 = 0; + uint32_t tmp2 = 0; + uint32_t tmp3 = 0; + uint32_t tmp4 = 0; + + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) + { + if (i2c_get_flag_status(hperh, I2C_FLAG_TRA) == SET) + { + tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_TXE); + tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF); + tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF); + tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT); + + if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) + i2c_master_send_txe(hperh); + else if ((tmp3 == SET) && (tmp4 == SET)) + i2c_master_send_btf(hperh); + } + + /* I2C in mode Receiver */ + else + { + tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_RXNE); + tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF); + tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF); + tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT); + + if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) + i2c_master_recv_rxne(hperh); + else if ((tmp3 == SET) && (tmp4 == SET)) + i2c_master_recv_btf(hperh); + } + } + + /* Slave mode selected */ + else + { + tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ADDR); + tmp2 = i2c_get_it_status(hperh, (I2C_IT_EVT)); + tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_STOPF); + tmp4 = i2c_get_flag_status(hperh, I2C_FLAG_TRA); + + if ((tmp1 == SET) && (tmp2 == SET)) + { + i2c_slave_addr(hperh); + } + else if ((tmp3 == SET) && (tmp2 == SET)) + { + i2c_slave_stopf(hperh); + } + + /* I2C in mode Transmitter */ + else if (tmp4 == SET) + { + tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_TXE); + tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF); + tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF); + tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT); + + if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) + i2c_slave_send_txe(hperh); + else if ((tmp3 == SET) && (tmp4 == SET)) + i2c_slave_send_btf(hperh); + } + + /* I2C in mode Receiver */ + else + { + tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_RXNE); + tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF); + tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF); + tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT); + + if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) + i2c_slave_recv_rxne(hperh); + else if ((tmp3 == SET) && (tmp4 == SET)) + i2c_slave_recv_btf(hperh); + } + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hperh: pointer to a i2c_handle_t structure that contains + * the configuration information for I2C module + * @retval NONE + */ +void i2c_er_irq_handler(i2c_handle_t *hperh) +{ + uint32_t tmp1 = 0; + uint32_t tmp2 = 0; + uint32_t tmp3 = 0; + + tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_BERR); + tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR); + + /* I2C Bus error interrupt occurred */ + if ((tmp1 == SET) && (tmp2 == SET)) + { + hperh->error_code |= I2C_ERROR_BERR; + i2c_clear_flag_status(hperh, I2C_FLAG_BERR); + SET_BIT(hperh->perh->CON1, I2C_CON1_SRST); + } + + tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ARLO); + tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR); + + /* I2C Arbitration Loss error interrupt occurred */ + if ((tmp1 == SET) && (tmp2 == SET)) + { + hperh->error_code |= I2C_ERROR_ARLO; + i2c_clear_flag_status(hperh, I2C_FLAG_ARLO); + } + + tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_AF); + tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR); + + /* I2C Acknowledge failure error interrupt occurred */ + if ((tmp1 == SET) && (tmp2 == SET)) + { + tmp1 = hperh->mode; + tmp2 = hperh->xfer_count; + tmp3 = hperh->state; + if ((tmp1 == I2C_MODE_SLAVE) && (tmp2 == 0) && \ + (tmp3 == I2C_STATE_BUSY_TX)) + { + i2c_slave_af(hperh); + } + else + { + hperh->error_code |= I2C_ERROR_AF; + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + i2c_clear_flag_status(hperh, I2C_FLAG_AF); + } + } + + tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_OVR); + tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR); + + /* I2C Over-Run/Under-Run interrupt occurred */ + if ((tmp1 == SET) && (tmp2 == SET)) + { + hperh->error_code |= I2C_ERROR_OVR; + i2c_clear_flag_status(hperh, I2C_FLAG_OVR); + } + + if (hperh->error_code != I2C_ERROR_NONE) + { + hperh->state = I2C_STATE_READY; + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + if (hperh->error_callback) + hperh->error_callback(hperh); + } +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Handle TXE flag for Master Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh) +{ + if (hperh->xfer_count == 0) + { + i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + } + else + { + hperh->perh->DATA = (*hperh->p_buff++); + hperh->xfer_count--; + } + + return OK; +} + +/** + * @brief Handle BTF flag for Master Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_send_btf(i2c_handle_t *hperh) +{ + if (hperh->xfer_count != 0) + { + hperh->perh->DATA = (*hperh->p_buff++); + hperh->xfer_count--; + } + else + { + i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + if (hperh->mode == I2C_MODE_MEM) + { + hperh->state = I2C_STATE_READY; + if (hperh->mem_tx_cplt_cbk) + hperh->mem_tx_cplt_cbk(hperh); + } + else + { + hperh->state = I2C_STATE_READY; + if (hperh->master_tx_cplt_cbk) + hperh->master_tx_cplt_cbk(hperh); + } + } + return OK; +} + +/** + * @brief Handle RXNE flag for Master Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh) +{ + uint32_t tmp = 0; + + tmp = hperh->xfer_count; + if (tmp > 3) + { + (*hperh->p_buff++) = hperh->perh->DATA; + hperh->xfer_count--; + } + else if ((tmp == 2) || (tmp == 3)) + { + i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + } + else + { + i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + (*hperh->p_buff++) = hperh->perh->DATA; + hperh->xfer_count--; + + if (hperh->mode == I2C_MODE_MEM) + { + hperh->state = I2C_STATE_READY; + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } + else + { + hperh->state = I2C_STATE_READY; + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } + } + return OK; +} + +/** + * @brief Handle BTF flag for Master Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh) +{ + if (hperh->xfer_count == 3) + { + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } + else if (hperh->xfer_count == 2) + { + i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + + if (hperh->mode == I2C_MODE_MEM) + { + hperh->state = I2C_STATE_READY; + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } + else + { + hperh->state = I2C_STATE_READY; + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } + } + else + { + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } + return OK; +} + +/** + * @brief Handle TXE flag for Slave Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh) +{ + if (hperh->xfer_count != 0) + { + hperh->perh->DATA = (*hperh->p_buff++); + --hperh->xfer_count; + } + return OK; +} + +/** + * @brief Handle BTF flag for Slave Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_send_btf(i2c_handle_t *hperh) +{ + if (hperh->xfer_count != 0) + { + hperh->perh->DATA = (*hperh->p_buff++); + --hperh->xfer_count; + } + return OK; +} + +/** + * @brief Handle RXNE flag for Slave Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh) +{ + if (hperh->xfer_count != 0) + { + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } + return OK; +} + +/** + * @brief Handle BTF flag for Slave Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_recv_btf(i2c_handle_t *hperh) +{ + if (hperh->xfer_count != 0) + { + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } + return OK; +} + +/** + * @brief Handle ADD flag for Slave + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_addr(i2c_handle_t *hperh) +{ + I2C_CLEAR_ADDRFLAG(hperh); + + return OK; +} + +/** + * @brief Handle STOPF flag for Slave mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh) +{ + if (hperh->xfer_count != 0) + { + (*hperh->p_buff++) = hperh->perh->DATA; + --hperh->xfer_count; + } + + i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + __I2C_CLEAR_STOPFLAG(hperh); + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + hperh->state = I2C_STATE_READY; + + if (hperh->slave_rx_cplt_cbk) + hperh->slave_rx_cplt_cbk(hperh); + + return OK; +} + +/** + * @brief Handle Acknowledge Failed for Slave mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_af(i2c_handle_t *hperh) +{ + i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + i2c_clear_flag_status(hperh, I2C_FLAG_AF); + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + hperh->state = I2C_STATE_READY; + + if (hperh->slave_tx_cplt_cbk) + hperh->slave_tx_cplt_cbk(hperh); + + return OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) +{ + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + if (hperh->init.addr_mode == I2C_ADDR_7BIT) + { + hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); + } + else + { + hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + return ERROR; + } + else + { + return TIMEOUT; + } + } + + hperh->perh->DATA = I2C_10BIT_ADDRESS(dev_addr); + } + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + return OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) +{ + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + if (hperh->init.addr_mode == I2C_ADDR_7BIT) + { + hperh->perh->DATA = I2C_7BIT_ADD_READ(dev_addr); + } + else + { + hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr); + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + hperh->perh->DATA = I2C_10BIT_ADDRESS(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + hperh->perh->DATA = I2C_10BIT_HEADER_READ(dev_addr); + } + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + return OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) +{ + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + { + return TIMEOUT; + } + + hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else + { + return TIMEOUT; + } + } + + if (add_size == I2C_MEMADD_SIZE_8BIT) + { + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); + } + else + { + hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr); + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else + { + return TIMEOUT; + } + } + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); + } + + return OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) +{ + SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + I2C_CLEAR_ADDRFLAG(hperh); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else + { + return TIMEOUT; + } + } + + if (add_size == I2C_MEMADD_SIZE_8BIT) + { + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); + } + else + { + hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else + { + return TIMEOUT; + } + } + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); + } + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + return ERROR; + } + else + { + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_START); + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) + return TIMEOUT; + + hperh->perh->DATA = I2C_7BIT_ADD_READ(dev_addr); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + return ERROR; + else + return TIMEOUT; + } + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief DMA I2C master transmit process complete callback. + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_master_send_cplt(void *argv) +{ + i2c_handle_t *hperh = (i2c_handle_t *)argv; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != OK) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->master_tx_cplt_cbk) + hperh->master_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_slave_send_cplt(void *argv) +{ + i2c_handle_t *hperh = (i2c_handle_t *)argv; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != OK) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + i2c_clear_flag_status(hperh, I2C_FLAG_AF); + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->slave_tx_cplt_cbk) + hperh->slave_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C master receive process complete callback + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_master_recv_cplt(void *argv) +{ + i2c_handle_t *hperh = (i2c_handle_t *)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_LDMA); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_slave_recv_cplt(void *argv) +{ + i2c_handle_t *hperh = (i2c_handle_t *)argv; + + if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) + { + if (hperh->error_code == I2C_ERROR_AF) + hperh->error_code |= I2C_ERROR_AF; + else + hperh->error_code |= I2C_ERROR_TIMEOUT; + } + + __I2C_CLEAR_STOPFLAG(hperh); + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->slave_rx_cplt_cbk) + hperh->slave_rx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C Memory Write process complete callback + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_mem_send_cplt(void *argv) +{ + i2c_handle_t *hperh = (i2c_handle_t *)argv; + + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != OK) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->mem_tx_cplt_cbk) + hperh->mem_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C Memory Read process complete callback + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_mem_recv_cplt(void *argv) +{ + i2c_handle_t *hperh = (i2c_handle_t *)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_LDMA); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + if (hperh->error_code != I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } +} +#endif + +/** + * @brief I2C Configuration Speed function + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param i2c_clk: PCLK frequency from RCC. + * @retval CCR Speed: Speed to set in I2C CCR Register + */ +static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk) +{ + uint32_t tmp1 = 0; + + if (hperh->init.clk_speed <= I2C_STANDARD_MODE_MAX_CLK) + { + tmp1 = (i2c_clk / (hperh->init.clk_speed << 1)); + if ((tmp1 & I2C_CKCFG_CLKSET) < 4) + return 4; + else + return tmp1; + } + else + { + tmp1 = I2C_CKCFG_CLKMOD; + + if (hperh->init.duty == I2C_DUTYCYCLE_2) + tmp1 |= (i2c_clk / (hperh->init.clk_speed * 3)) | I2C_DUTYCYCLE_2; + else + tmp1 |= (i2c_clk / (hperh->init.clk_speed * 25)) | I2C_DUTYCYCLE_16_9; + + if ((tmp1 & I2C_CKCFG_CLKSET) < 1) + return 1; + else + return tmp1; + } +} + +#ifdef ALD_DMA +/** + * @brief DMA I2C communication error callback. + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_error(void *argv) +{ + i2c_handle_t *hperh = (i2c_handle_t *)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + hperh->error_code |= I2C_ERROR_DMA; + + if (hperh->error_callback) + hperh->error_callback(hperh); +} +#endif + +/** + * @brief This function handles I2C Communication timeout. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param flag: specifies the I2C flag to check. + * @param status: The new flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tickstart = 0; + + tickstart = __get_tick(); + + if (status == RESET) + { + while (i2c_get_flag_status(hperh, flag) == RESET) + { + if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + { + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + else + { + while (i2c_get_flag_status(hperh, flag) != RESET) + { + if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + { + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + return OK; +} + +/** + * @brief This function handles I2C Communication timeout for Master addressing phase. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param flag: specifies the I2C flag to check. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, uint32_t timeout) +{ + uint32_t tickstart = 0; + + tickstart = __get_tick(); + while (i2c_get_flag_status(hperh, flag) == RESET) + { + if (i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) + { + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + i2c_clear_flag_status(hperh, I2C_FLAG_AF); + + hperh->error_code = I2C_ERROR_AF; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return ERROR; + } + + if (timeout != I2C_MAX_DELAY) + { + if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + { + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + return OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of TXE flag. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = __get_tick(); + + while (i2c_get_flag_status(hperh, I2C_FLAG_TXE) == RESET) + { + if (i2c_is_ack_failed(hperh) != OK) + return ERROR; + + if (timeout != I2C_MAX_DELAY) + { + if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + { + hperh->error_code |= I2C_ERROR_TIMEOUT; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + return OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of BTF flag. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = __get_tick(); + + while (i2c_get_flag_status(hperh, I2C_FLAG_BTF) == RESET) + { + if (i2c_is_ack_failed(hperh) != OK) + { + return ERROR; + } + + if (timeout != I2C_MAX_DELAY) + { + if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + { + hperh->error_code |= I2C_ERROR_TIMEOUT; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + return OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of STOP flag. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = 0x00; + tickstart = __get_tick(); + + while (i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == RESET) + { + if (i2c_is_ack_failed(hperh) != OK) + return ERROR; + + if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + { + hperh->error_code |= I2C_ERROR_TIMEOUT; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + return OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of RXNE flag. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = 0x00; + tickstart = __get_tick(); + + while (i2c_get_flag_status(hperh, I2C_FLAG_RXNE) == RESET) + { + if (i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == SET) + { + i2c_clear_flag_status(hperh, I2C_FLAG_STOPF); + hperh->error_code = I2C_ERROR_NONE; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return ERROR; + } + + if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + { + hperh->error_code |= I2C_ERROR_TIMEOUT; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + } + return OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_is_ack_failed(i2c_handle_t *hperh) +{ + if (i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) + { + i2c_clear_flag_status(hperh, I2C_FLAG_AF); + hperh->error_code = I2C_ERROR_AF; + hperh->state = I2C_STATE_READY; + __UNLOCK(hperh); + + return ERROR; + } + + return OK; +} +/** + * @} + */ + +#endif /* ALD_I2C */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c new file mode 100644 index 0000000000..842e40938f --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c @@ -0,0 +1,149 @@ +/** + ********************************************************************************* + * + * @file ald_iap.c + * @brief IAP module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_iap.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup IAP IAP + * @brief IAP module driver + * @{ + */ +#ifdef ALD_IAP + + +/** @defgroup IAP_Public_Functions IAP Public Functions + * + * @verbatim + ============================================================================== + ##### Erase and Program flash functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Erase flash. + (+) Program flash. + + @endverbatim + * @{ + */ + +/** + * @brief Erases a specified page. + * @param addr: The beginning address of the page to be erased. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t iap_erase_page(uint32_t addr) +{ + uint32_t status; + IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR); + + __disable_irq(); + status = (*iap_pe)(addr); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs a word at a specified address. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data: Specifies the data to be programmed. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t iap_program_word(uint32_t addr, uint32_t data) +{ + uint32_t status; + IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR); + + if (addr & 0x3) + return 1; + + __disable_irq(); + status = (*iap_wp)(addr, data); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs double words at a specified address. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data_l: Specifies the LSB data to be programmed. + * @param data_h: Specifies the MSB data to be programmed. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h) +{ + uint32_t status; + IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR); + + if (addr & 0x3) + return 1; + + __disable_irq(); + status = (*iap_dwp)(addr, data_l, data_h); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs datas at a specified address. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data: Specifies the data to be programmed. + * @param len: Specifies the data length to be programmed. + * Bit0-1 must be zero. + * @param erase: Erase page flag before programming. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase) +{ + uint32_t status; + IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR); + + if ((addr & 0x3) || (len & 0x3)) + return 1; + + __disable_irq(); + status = (*iap_wsp)(addr, data, len, erase); + __enable_irq(); + + return !status; +} +/** + * @} + */ +#endif /* ALD_IAP */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c new file mode 100644 index 0000000000..f15053cd6d --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c @@ -0,0 +1,322 @@ +/** + ********************************************************************************* + * + * @file ald_pis.c + * @brief PIS module driver. + * + * @version V1.0 + * @date 27 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_pis.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup PIS PIS + * @brief PIS module driver + * @{ + */ +#ifdef ALD_PIS + +/** @defgroup PIS_Public_Functions PIS Public Functions + * @{ + */ + +/** @defgroup PIS_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Create the PIS mode according to the specified parameters in + * the pis_handle_t and create the associated handle. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t pis_create(pis_handle_t *hperh) +{ + pis_divide_t temp; + uint8_t clock_menu = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_PIS_SRC(hperh->init.producer_src)); + assert_param(IS_PIS_TRIG(hperh->init.consumer_trig)); + assert_param(IS_PIS_CLOCK(hperh->init.producer_clk)); + assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk)); + assert_param(IS_PIS_EDGE(hperh->init.producer_edge)); + + __LOCK(hperh); + hperh->perh = PIS; + + /* get location of consumer in channel and position of con0/con1 + * accord to comsumer_trig information */ + temp.HalfWord = (hperh->init.consumer_trig); + hperh->consumer_ch = (pis_ch_t)(temp.ch); + hperh->consumer_con = (pis_con_t)(temp.con); + hperh->consumer_pos = (1 << temp.shift); + + /* union producer clock and consumer clock */ + clock_menu = (hperh->init.producer_clk << 4) | (hperh->init.consumer_clk); + + if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) + { + __UNLOCK(hperh); + return BUSY; + } + + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS); + + /* configure sync clock, judging by producer clock with consumer clock */ + switch (clock_menu) + { + case 0x00: + case 0x11: + case 0x22: + case 0x33: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x01: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x02: + case 0x12: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x21: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x30: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x31: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS); + break; + case 0x32: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS); + default: + break; + } + + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS); + hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch]; + + /* enable consumer bit, switch pin of consumer */ + switch (hperh->consumer_con) + { + case PIS_CON_0: + PIS->TAR_CON0 |= hperh->consumer_pos; + break; + case PIS_CON_1: + PIS->TAR_CON1 |= hperh->consumer_pos; + break; + default: + break; + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Destroy the PIS mode according to the specified parameters in + * the pis_init_t and create the associated handle. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t pis_destroy(pis_handle_t *hperh) +{ + assert_param(IS_PIS(hperh->perh)); + + if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch]) + return ERROR; + + __LOCK(hperh); + + CLEAR_BIT(PIS->CH_OER, (1 << hperh->consumer_ch)); + WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0); + + switch (hperh->consumer_con) + { + case PIS_CON_0: + PIS->TAR_CON0 &= ~(hperh->consumer_pos); + break; + case PIS_CON_1: + PIS->TAR_CON1 &= ~(hperh->consumer_pos); + break; + default: + break; + } + + hperh->state = PIS_STATE_RESET; + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group2 Operation functions + * @brief PIS output enable or disable functions + * @{ + */ + +/** + * @brief Start the PIS output function. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param ch: The PIS channel enable output + * This parameter can be one of the following values: + * @arg PIS_OUT_CH_0 + * @arg PIS_OUT_CH_1 + * @arg PIS_OUT_CH_2 + * @arg PIS_OUT_CH_3 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_OUPUT_CH(ch)); + __LOCK(hperh); + SET_BIT(PIS->CH_OER, (1 << ch)); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Stop the PIS output function. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param ch: The PIS channel disable output + * This parameter can be one of the following values: + * @arg PIS_OUT_CH_0 + * @arg PIS_OUT_CH_1 + * @arg PIS_OUT_CH_2 + * @arg PIS_OUT_CH_3 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_OUPUT_CH(ch)); + __LOCK(hperh); + CLEAR_BIT(PIS->CH_OER, (1 << ch)); + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group3 Peripheral State and Errors functions + * @brief PIS State and Errors functions + * @{ + */ + +/** + * @brief Returns the PIS state. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval ALD state + */ +pis_state_t pis_get_state(pis_handle_t *hperh) +{ + assert_param(IS_PIS(hperh->perh)); + return hperh->state; +} + +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group4 modulate output functions + * @brief PIS modulate output signal functions + * @{ + */ + +/** + * @brief Config the PIS modulate signal function + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param config: Pointer to a pis_modulate_config_t structure that + * contains the selected target (UART0,UART1,UART2,UART3 or + * LPUART0) how to modulate the target output signal. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_MODU_TARGET(config->target)); + assert_param(IS_PIS_MODU_LEVEL(config->level)); + assert_param(IS_PIS_MODU_SRC(config->src)); + assert_param(IS_PIS_MODU_CHANNEL(config->channel)); + __LOCK(hperh); + + switch (config->target) + { + case PIS_UART0_TX: + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART1_TX: + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART2_TX: + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART3_TX: + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_LPUART0_TX: + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + default: + break; + } + + __UNLOCK(hperh); + return OK; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_PIS */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c new file mode 100644 index 0000000000..f959aa3001 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c @@ -0,0 +1,257 @@ +/** + ********************************************************************************* + * + * @file ald_pmu.c + * @brief PMU module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_pmu.h" +#include "ald_bkpc.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup PMU PMU + * @brief PMU module driver + * @{ + */ +#ifdef ALD_PMU + + +/** @defgroup PMU_Private_Functions PMU Private Functions + * @{ + */ + +/** + * @brief PMU module interrupt handler + * @retval None + */ +void LVD_Handler(void) +{ + SYSCFG_UNLOCK(); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + SYSCFG_LOCK(); + + lvd_irq_cbk(); + return; +} +/** + * @} + */ + +/** @defgroup PMU_Public_Functions PMU Public Functions + * @{ + */ + +/** @addtogroup PMU_Public_Functions_Group1 Low Power Mode + * @brief Low power mode select functions + * + * @verbatim + ============================================================================== + ##### Low power mode select functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Enter stop1 mode. + (+) Enter stop2 mode. + (+) Enter standby mode. + (+) Get wakeup status. + (+) Clear wakeup status. + + @endverbatim + * @{ + */ + +/** + * @brief Enter stop1 mode + * @retval None + */ +void pmu_stop1_enter(void) +{ + SYSCFG_UNLOCK(); + MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP1 << PMU_CR_LPM_POSS); + SYSCFG_LOCK(); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + + return; +} + +/** + * @brief Enter stop2 mode + * @retval None + */ +void pmu_stop2_enter(void) +{ + SYSCFG_UNLOCK(); + MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP2 << PMU_CR_LPM_POSS); + SYSCFG_LOCK(); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + + return; + +} + +/** + * @brief Enter standby mode + * @param port: The port whick wake up the standby mode. + * @retval None + */ +void pmu_standby_enter(pmu_standby_wakeup_sel_t port) +{ + assert_param(IS_PMU_STANDBY_PORT_SEL(port)); + + if (port != PMU_STANDBY_PORT_NONE) + { + BKPC_UNLOCK(); + MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS); + SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK); + BKPC_LOCK(); + + SYSCFG_UNLOCK(); + MODIFY_REG(PMU->CR, PMU_CR_WKPS_MSK, port << PMU_CR_WKPS_POSS); + SET_BIT(PMU->CR, PMU_CR_WKPEN_MSK); + MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STANDBY << PMU_CR_LPM_POSS); + SYSCFG_LOCK(); + } + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + + return; +} + +/** + * @brief Get wakup status. + * @param sr: Status bit. + * @retval Status. + */ +flag_status_t pmu_get_status(pmu_status_t sr) +{ + assert_param(IS_PMU_STATUS(sr)); + + if (READ_BIT(PMU->SR, sr)) + return SET; + + return RESET; +} + +/** + * @brief Clear wakup status. + * @param sr: Status bit. + * @retval None + */ +void pmu_clear_status(pmu_status_t sr) +{ + assert_param(IS_PMU_STATUS(sr)); + SYSCFG_UNLOCK(); + + if (sr == PMU_SR_WUF) + SET_BIT(PMU->CR, PMU_CR_CWUF_MSK); + else + SET_BIT(PMU->CR, PMU_CR_CSTANDBYF_MSK); + + SYSCFG_LOCK(); + return; +} + + +/** + * @} + */ + +/** @addtogroup PMU_Public_Functions_Group2 LVD Configure + * @brief LVD configure functions + * + * @verbatim + ============================================================================== + ##### LVD configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure lvd parameters. + (+) Interrupt callback function. + + @endverbatim + * @{ + */ + +/** + * @brief Configure lvd using specified parameters. + * @param sel: LVD threshold voltage. + * @param mode: LVD trigger mode. + * @param state: New state, ENABLE/DISABLE; + * @retval None + */ +void pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state) +{ + assert_param(IS_FUNC_STATE(state)); + SYSCFG_UNLOCK(); + + if (state) + { + assert_param(IS_PMU_LVD_VOL_SEL(sel)); + assert_param(IS_PMU_LVD_TRIGGER_MODE(mode)); + + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS); + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + else + { + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Interrupt callback function. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void lvd_irq_cbk(void) +{ + return; +} +/** + * @} + */ + + +/** + * @} + */ +#endif /* ALD_PMU */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c new file mode 100644 index 0000000000..5b8efcad02 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c @@ -0,0 +1,146 @@ +/** + ********************************************************************************* + * + * @file ald_rmu.c + * @brief RMU module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_rmu.h" +#include "ald_syscfg.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup RMU RMU + * @brief RMU module driver + * @{ + */ +#ifdef ALD_RMU + +/** @defgroup RMU_Public_Functions RMU Public Functions + * @{ + */ + +/** + * @brief Configure BOR parameters. + * @param flt: filter time. + * @param vol: The voltage. + * @param state: The new status: ENABLE/DISABLE. + * @retval None + */ +void rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state) +{ + assert_param(IS_FUNC_STATE(state)); + + SYSCFG_UNLOCK(); + + if (state) + { + assert_param(IS_RMU_BORFLT(flt)); + assert_param(IS_RMU_BORVOL(vol)); + + MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS); + MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS); + SET_BIT(RMU->CR, RMU_CR_BOREN_MSK); + } + else + { + CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Get specified reset status + * @param state: Speicifies the type of the reset, + * @retval The status: SET/RESET. + */ +flag_status_t rmu_get_reset_status(rmu_state_t state) +{ + assert_param(IS_RMU_STATE(state)); + + if (READ_BIT(RMU->RSTSR, state)) + return SET; + + return RESET; +} + +/** + * @brief Clear the specified reset status + * @param state: Specifies the type of the reset, + * @retval None + */ +void rmu_clear_reset_status(rmu_state_t state) +{ + assert_param(IS_RMU_STATE_CLEAR(state)); + + SYSCFG_UNLOCK(); + WRITE_REG(RMU->CRSTSR, state); + SYSCFG_LOCK(); + + return; +} +/** + * @brief Reset peripheral device + * @param perh: The peripheral device, + * @retval None + */ +void rmu_reset_periperal(rmu_peripheral_t perh) +{ + uint32_t idx, pos; + + assert_param(IS_RMU_PERH(perh)); + + idx = (perh >> 27) & 0x7; + pos = perh & ~(0x7 << 27); + SYSCFG_UNLOCK(); + + switch (idx) + { + case 0: + WRITE_REG(RMU->AHB1RSTR, pos); + break; + + case 1: + WRITE_REG(RMU->AHB2RSTR, pos); + break; + + case 2: + WRITE_REG(RMU->APB1RSTR, pos); + break; + + case 4: + WRITE_REG(RMU->APB2RSTR, pos); + break; + + default: + break; + } + + SYSCFG_LOCK(); + return; +} + +/** + * @} + */ +#endif /* ALD_RMU */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c new file mode 100644 index 0000000000..913a095bd2 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c @@ -0,0 +1,1229 @@ +/** + ****************************************************************************** + * @file ald_rtc.c + * @brief RTC module driver. + * This file provides firmware functions to manage the following + * functionalities of the RTC peripheral: + * + Initialization functions + * + Time and date functions + * + Alarm functions + * + Time stamp functions + * + Tamper functions + * + Wake-up functions + * + Clock output functions + * + Peripheral Control functions + * @version V1.0 + * @date 25 Apr 2017 + * @author AE Team + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) Enable the RTC controller interface clock. + (+) Select the RTC source clock(default LOSC). + (+) Configure the RTC asynchronous prescaler, synchronous prescaler and hour + format using the rtc_init() function. + + *** Time and date operation *** + ================================= + [..] + (+) To configure the time use the rtc_set_time() function. + (+) To configure the date use the rtc_set_date() function. + (+) To read the time use the rtc_get_time() function. + (+) To read the date use the rtc_get_date() function. + + *** Alarm operation *** + =================================== + [..] + (+) To configure the alarm use rtc_set_alarm() function + (+) To read the alarm use rtc_get_alarm() function + (+) To cancel the alarm use rtc_alarm_cmd() function + + *** Time stamp operation *** + =================================== + [..] + (+) To configure the time stamp use rtc_set_time_stamp() function + (+) To read the time stamp use rtc_get_time_stamp() function + (+) To cancel the time stamp use rtc_cancel_time_stamp() function + + *** Tamper operation *** + =================================== + [..] + (+) To configure the tamper use rtc_set_tamper() function + (+) To cancel the tamper use rtc_alarm_cmd() function + + *** Wake-up operation *** + =================================== + [..] + (+) To configure the wake-up parameters use rtc_set_wakeup() function + (+) To read the re-load register value use rtc_get_wakeup_timer_value() function + (+) To cancel the wake-up use rtc_cancel_wakeup() function + + *** Output clock operation *** + =================================== + [..] + (+) To configure the clock output type use rtc_set_clock_output() function + (+) To cancel the clock output use rtc_cancel_clock_output() function + + *** Control functions *** + =================================== + [..] + (+) Configure interrupt enable/disable. + (+) Enable/disable alarm. + (+) Configure rtc shift. + (+) Calibrate time. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag. + + ================================================================== + ##### RTC and low power modes ##### + ================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate function. + [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), + RTC wake-up, RTC tamper event detection and RTC time stamp event detection. + These RTC alternate functions can wake up the system from the Stop and + Standby low power modes. + [..] The system can also wake up from low power modes without depending + on an external interrupt (Auto-wake-up mode), by using the RTC alarm + or the RTC wake-up events. + [..] The RTC provides a programmable time base for waking up from the Stop or + Standby mode at regular intervals. Wake-up from STOP and STANDBY modes + is possible only when the RTC clock source is LSE or LSI. + + *** RTC driver macros list *** + ============================================= + [..] + Below the list of most used macros in RTC driver. + + (+) RTC_UNLOCK() Disable the protect. + (+) RTC_LOCK() Enable the protect. + (+) RTC_BY_PASS_ENABLE() Enable the by-pass shadow register. + (+) RTC_BY_PASS_DISABLE() Disable the by-pass shadow register. + (+) RTC_SUMMER_TIME_ENABLE() Enable summer time. + (+) RTC_SUMMER_TIME_DISABLE() Disable summer time. + (+) RTC_WINTER_TIME_ENABLE() Enable winter time. + (+) RTC_WINTER_TIME_DISABLE() Disable winter time. + [..] + (@) You can refer to the RTC driver header file for used the macros + + @endverbatim + ****************************************************************************** + */ + +#include "ald_rtc.h" +#include "ald_bkpc.h" +#include "ald_temp.h" +#include "ald_syscfg.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup RTC RTC + * @brief RTC module driver + * @{ + */ +#ifdef ALD_RTC + +/** @addtogroup RTC_Private_Functions RTC Private Functions + * @{ + */ +/** + * @brief Converts form 2 digit BCD to Binary. + * @param bcd: BCD value to be converted. + * @retval Converted word. + */ +static uint32_t bcd_to_dec(uint32_t bcd) +{ + return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10); +} + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param dec: Byte to be converted. + * @retval Converted byte. + */ +static uint32_t dec_to_bcd(uint32_t dec) +{ + return (((dec / 10) << 4) | (dec % 10)); +} + +/** + * @brief Time and Date consistency check. + * @param t_last: Last time. + * @param d_last: Last date. + * @param time: Current time. + * @param date: Current time. + * @retval status: + * 0 - Not consistency + * 1 - Consistency + */ +static int32_t rtc_consistency_check(rtc_time_t *t_last, + rtc_date_t *d_last, rtc_time_t *time, rtc_date_t *date) +{ + if (t_last->second != time->second) + return 0; + if (t_last->minute != time->minute) + return 0; + if (t_last->hour != time->hour) + return 0; + if (d_last->day != date->day) + return 0; + if (d_last->month != date->month) + return 0; + if (d_last->year != date->year) + return 0; + + return 1; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions RTC Public Functions + * @{ + */ + +/** @defgroup RTC_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @verbatim + =============================================================================== + ##### Initialization function ##### + =============================================================================== + [..] This section provides functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + RTC registers Write protection. + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize power consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register. + + @endverbatim + * @{ + */ + +/** + * @brief Reset RTC register. + * @retval None + */ +void rtc_reset(void) +{ + RTC_UNLOCK(); + + WRITE_REG(RTC->CON, 0x0); + WRITE_REG(RTC->TAMPCON, 0x0); + WRITE_REG(RTC->WUMAT, 0x0); + WRITE_REG(RTC->IER, 0x0); + WRITE_REG(RTC->IFCR, ~0x0); + + RTC_LOCK(); + return; +} + +/** + * @brief Initialize the RTC module. + * @param init: Pointer to rtc_init_t structure which contains + * the configuration parameters. + * @retval None + */ +void rtc_init(rtc_init_t *init) +{ + assert_param(IS_RTC_HOUR_FORMAT(init->hour_format)); + assert_param(IS_RTC_OUTPUT_SEL(init->output)); + assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); + + rtc_reset(); + RTC_UNLOCK(); + + MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); + MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS); + MODIFY_REG(RTC->CON, RTC_CON_POL_MSK, init->output_polarity << RTC_CON_POL_POS); + MODIFY_REG(RTC->PSR, RTC_PSR_SPRS_MSK, init->synch_pre_div << RTC_PSR_SPRS_POSS); + MODIFY_REG(RTC->PSR, RTC_PSR_APRS_MSK, init->asynch_pre_div << RTC_PSR_APRS_POSS); + SET_BIT(RTC->CON, RTC_CON_GO_MSK); + + RTC_LOCK(); + return; +} + +/** + * @brief Configure the RTC source. + * @param sel: RTC source type. + * @retval None + */ +void rtc_source_selcet(rtc_source_sel_t sel) +{ + assert_param(IS_RTC_SOURCE_SEL(sel)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, sel << BKPC_PCCR_RTCCS_POSS); + + if (sel == RTC_SOURCE_LOSC) + { + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); + } + else if (sel == RTC_SOURCE_LRC) + { + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); + } + else + { + ; /* do nothing */ + } + + BKPC_LOCK(); + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group2 Time and Date functions + * @brief RTC Time and Date functions + * + * @verbatim + =============================================================================== + ##### Time and Date functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the time use the rtc_set_time() function. + (+) To configure the date use the rtc_set_date() function. + (+) To read the time use the rtc_get_time() function. + (+) To read the date use the rtc_get_date() function. + + @endverbatim + * @{ + */ + +/** + * @brief Set specified time. + * @param time: pointer to a rtc_time_t structure. + * @param format: Data format. + * @retval ALD status. + */ +ald_status_t rtc_set_time(rtc_time_t *time, rtc_format_t format) +{ + uint32_t tmp; + + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) + { + assert_param(IS_RTC_SECOND(time->second)); + assert_param(IS_RTC_MINUTE(time->minute)); + assert_param(IS_RTC_HOUR(time->hour)); + + tmp = (dec_to_bcd(time->second)) | + (dec_to_bcd(time->minute) << 8) | + (dec_to_bcd(time->hour) << 16); + } + else + { + assert_param(IS_RTC_SECOND(bcd_to_dec(time->second))); + assert_param(IS_RTC_MINUTE(bcd_to_dec(time->minute))); + assert_param(IS_RTC_HOUR(bcd_to_dec(time->hour))); + + tmp = time->second | (time->minute << 8) | (time->hour << 16); + } + + RTC_UNLOCK(); + WRITE_REG(RTC->TIME, tmp); + WRITE_REG(RTC->SSEC, time->sub_sec); + RTC_LOCK(); + + tmp = __get_tick(); + + while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) + { + if ((__get_tick() - tmp) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } + + return OK; +} + +/** + * @brief Set specified date. + * @param date: pointer to a rtc_date_t structure. + * @param format: Data format. + * @retval ALD status. + */ +ald_status_t rtc_set_date(rtc_date_t *date, rtc_format_t format) +{ + uint32_t tmp; + + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) + { + assert_param(IS_RTC_DAY(date->day)); + assert_param(IS_RTC_MONTH(date->month)); + assert_param(IS_RTC_YEAR(date->year)); + + tmp = (dec_to_bcd(date->day)) | + (dec_to_bcd(date->month) << 8) | + (dec_to_bcd(date->year) << 16) | + (dec_to_bcd(date->week) << 24); + } + else + { + assert_param(IS_RTC_DAY(bcd_to_dec(date->day))); + assert_param(IS_RTC_MONTH(bcd_to_dec(date->month))); + assert_param(IS_RTC_YEAR(bcd_to_dec(date->year))); + + tmp = date->day | (date->month << 8) | + (date->year << 16) | (date->week << 24); + } + + RTC_UNLOCK(); + WRITE_REG(RTC->DATE, tmp); + RTC_LOCK(); + + tmp = __get_tick(); + + while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) + { + if ((__get_tick() - tmp) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } + + return OK; +} + +/** + * @brief Get current time. + * @param time: pointer to a rtc_time_t structure. + * @param format: Data format. + * @retval None + */ +void rtc_get_time(rtc_time_t *time, rtc_format_t format) +{ + uint32_t tmp; + + assert_param(time != NULL); + assert_param(IS_RTC_FORMAT(format)); + + time->sub_sec = RTC->SSEC & 0xFFFF; + tmp = RTC->TIME; + + if (format == RTC_FORMAT_DEC) + { + time->second = bcd_to_dec(tmp & 0x7F); + time->minute = bcd_to_dec((tmp >> 8) & 0x7F); + time->hour = bcd_to_dec((tmp >> 16) & 0x7F); + } + else + { + time->second = tmp & 0x7F; + time->minute = (tmp >> 8) & 0x7F; + time->hour = (tmp >> 16) & 0x7F; + } + + return; +} + +/** + * @brief Get current date. + * @param date: pointer to a rtc_date_t structure. + * @param format: Data format. + * @retval None + */ +void rtc_get_date(rtc_date_t *date, rtc_format_t format) +{ + uint32_t tmp = RTC->DATE; + + assert_param(date != NULL); + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) + { + date->day = bcd_to_dec(tmp & 0x3F); + date->month = bcd_to_dec((tmp >> 8) & 0x1F); + date->year = bcd_to_dec((tmp >> 16) & 0xFF); + date->week = bcd_to_dec((tmp >> 24) & 0x7); + } + else + { + date->day = tmp & 0x3F; + date->month = (tmp >> 8) & 0x1F; + date->year = (tmp >> 16) & 0xFF; + date->week = (tmp >> 24) & 0x7; + } + + return; +} + +/** + * @brief Get time and date consistency. + * @param date: pointer to a rtc_date_t structure. + * @param time: pointer to a rtc_time_t structure. + * @param format: Data format. + * @retval Status: + * 0 - Consistency + * -1 - Not consistency + */ +int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format) +{ + int32_t nr = 3; + rtc_date_t d_last; + rtc_time_t t_last; + + while (nr--) + { + rtc_get_time(&t_last, format); + rtc_get_date(&d_last, format); + rtc_get_time(time, format); + rtc_get_date(date, format); + + if (rtc_consistency_check(&t_last, &d_last, time, date)) + return 0; + } + + return -1; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group3 Alarm functions + * @brief RTC alarm functions + * + * @verbatim + =============================================================================== + ##### Alarm functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the alarm use rtc_set_alarm() function + (+) To read the alarm use rtc_get_alarm() function + + @endverbatim + * @{ + */ + +/** + * @brief Set alarm. + * @param alarm: pointer to rtc_alarm_t struct. + * @param format: Data format. + * @retval None + */ +void rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format) +{ + unsigned int tmp, ss_tmp; + + assert_param(IS_RTC_ALARM(alarm->idx)); + assert_param(IS_RTC_ALARM_SEL(alarm->sel)); + assert_param(IS_RTC_ALARM_SS_MASK(alarm->ss_mask)); + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) + { + assert_param(IS_RTC_SECOND(alarm->time.second)); + assert_param(IS_RTC_MINUTE(alarm->time.minute)); + assert_param(IS_RTC_HOUR(alarm->time.hour)); + + tmp = (dec_to_bcd(alarm->time.second)) | + (dec_to_bcd(alarm->time.minute) << 8) | + (dec_to_bcd(alarm->time.hour) << 16) | + alarm->mask; + + if (alarm->sel == RTC_SELECT_DAY) + { + assert_param(IS_RTC_DAY(alarm->day)); + + tmp |= (dec_to_bcd(alarm->day) << 24); + tmp &= 0x7FFFFFFF; /* Reset bit31 */ + } + else + { + tmp |= (1 << (alarm->week + 24)); + tmp |= 0x80000000; /* Set bit31 */ + } + } + else + { + assert_param(IS_RTC_SECOND(bcd_to_dec(alarm->time.second))); + assert_param(IS_RTC_MINUTE(bcd_to_dec(alarm->time.minute))); + assert_param(IS_RTC_HOUR(bcd_to_dec(alarm->time.hour))); + + tmp = alarm->time.second | + (alarm->time.minute << 8) | + (alarm->time.hour << 16) | + alarm->mask; + + if (alarm->sel == RTC_SELECT_DAY) + { + assert_param(IS_RTC_DAY(bcd_to_dec(alarm->day))); + + tmp |= (alarm->day << 24); + tmp &= 0x7FFFFFFF; /* Reset bit31 */ + } + else + { + tmp |= (1 << (alarm->week + 24)); + tmp |= 0x80000000; /* Set bit31 */ + } + } + + ss_tmp = (alarm->time.sub_sec & 0x7F) | + (alarm->ss_mask << 24); + + RTC_UNLOCK(); + + if (alarm->idx == RTC_ALARM_A) + { + WRITE_REG(RTC->ALMA, tmp); + WRITE_REG(RTC->ALMASSEC, ss_tmp); + SET_BIT(RTC->CON, RTC_CON_ALMAEN_MSK); + } + else + { + WRITE_REG(RTC->ALMB, tmp); + WRITE_REG(RTC->ALMBSSEC, ss_tmp); + SET_BIT(RTC->CON, RTC_CON_ALMBEN_MSK); + } + + RTC_LOCK(); + return; +} + +/** + * @brief Get alarm parameters. + * @param alarm: pointer to rtc_alarm_t struct. + * @param format: Data format. + * @retval None + */ +void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) +{ + uint8_t week; + uint32_t tmp, ss_tmp; + + assert_param(alarm != NULL); + assert_param(IS_RTC_FORMAT(format)); + + if (alarm->idx == RTC_ALARM_A) + { + tmp = RTC->ALMA; + ss_tmp = RTC->ALMASSEC; + } + else + { + tmp = RTC->ALMB; + ss_tmp = RTC->ALMBSSEC; + } + + if ((tmp >> 31) & 0x1) + { + alarm->sel = RTC_SELECT_WEEK; + week = ((tmp >> 24) & 0x7F); + + switch (week) + { + case 1: + alarm->week = 0; + break; + case 2: + alarm->week = 1; + break; + case 4: + alarm->week = 2; + break; + case 8: + alarm->week = 3; + break; + case 16: + alarm->week = 4; + break; + case 32: + alarm->week = 5; + break; + case 64: + alarm->week = 6; + break; + default: + break; + } + } + else + { + alarm->sel = RTC_SELECT_DAY; + + if (format == RTC_FORMAT_DEC) + alarm->day = bcd_to_dec((tmp >> 24) & 0x3F); + else + alarm->day = (tmp >> 24) & 0x3F; + } + + if (format == RTC_FORMAT_DEC) + { + alarm->time.second = bcd_to_dec(tmp & 0x7F); + alarm->time.minute = bcd_to_dec((tmp >> 8) & 0x7F); + alarm->time.hour = bcd_to_dec((tmp >> 16) & 0x3F); + } + else + { + alarm->time.second = tmp & 0x7F; + alarm->time.minute = (tmp >> 8) & 0x7F; + alarm->time.hour = (tmp >> 16) & 0x3F; + } + + alarm->time.sub_sec = ss_tmp & 0x7FFF; + alarm->ss_mask = (rtc_sub_second_mask_t)((ss_tmp >> 24) & 0xF); + alarm->mask = tmp & ALARM_MASK_ALL; + + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group4 Time stamp functions + * @brief RTC time stamp functions + * + * @verbatim + =============================================================================== + ##### Time stamp functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the time stamp use rtc_set_time_stamp() function + (+) To read the time stamp use rtc_get_time_stamp() function + (+) To cancel the time stamp use rtc_cancel_time_stamp() function + + @endverbatim + * @{ + */ + +/** + * @brief Set time stamp. + * @param sel: time stamp signal select: + * @arg RTC_TS_SIGNAL_SEL_TAMPER0 + * @arg RTC_TS_SIGNAL_SEL_TAMPER1 + * @param style: time stamp trigger style: + * @arg RTC_TS_RISING_EDGE + * @arg RTC_TS_FALLING_EDGE + * @retval None + */ +void rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style) +{ + assert_param(IS_RTC_TS_SIGNAL(sel)); + assert_param(IS_RTC_TS_STYLE(style)); + + RTC_UNLOCK(); + + CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); + MODIFY_REG(RTC->CON, RTC_CON_TSSEL_MSK, style << RTC_CON_TSSEL_POS); + MODIFY_REG(RTC->CON, RTC_CON_TSPIN_MSK, sel << RTC_CON_TSPIN_POS); + SET_BIT(RTC->CON, RTC_CON_TSEN_MSK); + + RTC_LOCK(); + return; +} + +/** + * @brief Cancel time stamp. + * @retval None + */ +void rtc_cancel_time_stamp(void) +{ + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); + RTC_LOCK(); + + return; +} + +/** + * @brief Get time stamp value. + * @param ts_time: pointer to rtc_time_t structure. + * @param ts_date: pointer to rtc_date_t structure. + * @param format: Data format. + * @retval None + */ +void rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format) +{ + uint32_t tmp0, tmp1; + + assert_param(ts_time != NULL); + assert_param(ts_date != NULL); + assert_param(IS_RTC_FORMAT(format)); + + ts_time->sub_sec = RTC->TSSSEC & 0xFFFF; + tmp0 = RTC->TSTIME; + tmp1 = RTC->TSDATE; + + if (format == RTC_FORMAT_DEC) + { + ts_time->second = bcd_to_dec(tmp0 & 0x7F); + ts_time->minute = bcd_to_dec((tmp0 >> 8) & 0x7F); + ts_time->hour = bcd_to_dec((tmp0 >> 16) & 0x3F); + ts_date->day = bcd_to_dec(tmp1 & 0x3F); + ts_date->month = bcd_to_dec((tmp1 >> 8) & 0x1F); + ts_date->year = bcd_to_dec((tmp1 >> 16) & 0xFF); + ts_date->week = bcd_to_dec((tmp1 >> 24) & 0x7); + } + else + { + ts_time->second = tmp0 & 0x7F; + ts_time->minute = (tmp0 >> 8) & 0x7F; + ts_time->hour = (tmp0 >> 16) & 0x3F; + ts_date->day = tmp1 & 0x3F; + ts_date->month = (tmp1 >> 8) & 0x1F; + ts_date->year = (tmp1 >> 16) & 0xFF; + ts_date->week = (tmp1 >> 24) & 0x7; + } + + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group5 Tamper functions + * @brief RTC tamper functions + * + * @verbatim + =============================================================================== + ##### Tamper functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the tamper use rtc_set_tamper() function + (+) To cancel the tamper use rtc_alarm_cmd() function + + @endverbatim + * @{ + */ +/** + * @brief Set tamper parameters. + * @param tamper: pointer to rtc_tamper_t structure. + * @retval None + */ +void rtc_set_tamper(rtc_tamper_t *tamper) +{ + assert_param(IS_RTC_TAMPER(tamper->idx)); + assert_param(IS_RTC_TAMPER_TRIGGER(tamper->trig)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(tamper->freq)); + assert_param(IS_RTC_TAMPER_DURATION(tamper->dur)); + assert_param(IS_FUNC_STATE(tamper->ts)); + + RTC_UNLOCK(); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPTS_MSK, tamper->ts << RTC_TAMPCON_TAMPTS_POS); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPCKS_MSK, tamper->freq << RTC_TAMPCON_TAMPCKS_POSS); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPFLT_MSK, tamper->dur << RTC_TAMPCON_TAMPFLT_POSS); + + if (tamper->idx == RTC_TAMPER_0) + { + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP1LV_MSK, tamper->trig << RTC_TAMPCON_TAMP1LV_POS); + SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); + } + else + { + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP2LV_MSK, tamper->trig << RTC_TAMPCON_TAMP2LV_POS); + SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK); + } + + RTC_LOCK(); + return; +} + +/** + * @brief Cancel tamper. + * @param idx: index of tamper: + * @arg RTC_TAMPER_0 + * @arg RTC_TAMPER_1 + * @retval None + */ +void rtc_cancel_tamper(rtc_tamper_idx_t idx) +{ + assert_param(IS_RTC_TAMPER(idx)); + + RTC_UNLOCK(); + + if (idx == RTC_TAMPER_0) + CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); + else + CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK); + + RTC_LOCK(); + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group6 Wake-up functions + * @brief RTC wake-up functions + * + * @verbatim + =============================================================================== + ##### Wake-up functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the wake-up parameters use rtc_set_wakeup() function + (+) To read the re-load register value use rtc_get_wakeup_timer_value() function + (+) To cancel the wake-up use rtc_cancel_wakeup() function + + @endverbatim + * @{ + */ +/** + * @brief Set wake-up parameters. + * @param clock: pointer to rtc_wakeup_clock_t structure. + * @param value: re-load value. + * @retval None + */ +void rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value) +{ + assert_param(IS_RTC_WAKEUP_CLOCK(clock)); + + RTC_UNLOCK(); + MODIFY_REG(RTC->CON, RTC_CON_WUCKS_MSK, clock << RTC_CON_WUCKS_POSS); + WRITE_REG(RTC->WUMAT, value & 0xFFFF); + SET_BIT(RTC->CON, RTC_CON_WUTE_MSK); + RTC_LOCK(); + + return; +} + +/** + * @brief Cancel wake-up. + * @retval None + */ +void rtc_cancel_wakeup(void) +{ + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_WUTE_MSK); + RTC_LOCK(); + + return; +} + +/** + * @brief Get wake-up re-load register value. + * @retval Value of re-load register. + */ +uint16_t rtc_get_wakeup_timer_value(void) +{ + return RTC->WUMAT & 0xFFFF; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group7 Clock output functions + * @brief RTC clock output functions + * + * @verbatim + =============================================================================== + ##### Clock output functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the clock output type use rtc_set_clock_output() function + (+) To cancel the clock output use rtc_cancel_clock_output() function + + @endverbatim + * @{ + */ +/** + * @brief Set clock output parameters. + * @param clock: pointer to rtc_clock_output_t structure. + * @retval ALD status. + */ +ald_status_t rtc_set_clock_output(rtc_clock_output_t clock) +{ + uint32_t cnt = 4000; + assert_param(IS_RTC_CLOCK_OUTPUT(clock)); + + SYSCFG_UNLOCK(); + + if (clock == RTC_CLOCK_OUTPUT_EXA_1) + { + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2LCKN_MSK)) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL2RDY_MSK))) && (--cnt)); + } + else + { + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + } + + SYSCFG_LOCK(); + RTC_UNLOCK(); + MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, clock << RTC_CON_CKOS_POSS); + SET_BIT(RTC->CON, RTC_CON_CKOE_MSK); + RTC_LOCK(); + + return OK; +} + +/** + * @brief Cancel clock output. + * @retval None + */ +void rtc_cancel_clock_output(void) +{ + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_CKOE_MSK); + RTC_LOCK(); + + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group8 Control functions + * @brief RTC control functions + * + * @verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) Configure interrupt enable/disable. + (+) Enable/disable alarm. + (+) Configure rtc shift. + (+) Calibrate time. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag. + + @endverbatim + * @{ + */ +/** + * @brief Enable/disable the specified RTC interrupts. + * @param it: Specifies the RTC interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref rtc_it_t. + * @param state: New state of the specified RTC interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void rtc_interrupt_config(rtc_it_t it, type_func_t state) +{ + assert_param(IS_RTC_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + RTC_UNLOCK(); + + if (state == ENABLE) + SET_BIT(RTC->IER, it); + else + CLEAR_BIT(RTC->IER, it); + + RTC_LOCK(); + return; +} + +/** + * @brief Enable/Disable alarm. + * @param idx: index of alarm: + * @arg RTC_ALARM_A + * @arg RTC_ALARM_B + * @param state: New status of the specified alarm: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state) +{ + assert_param(IS_RTC_ALARM(idx)); + assert_param(IS_FUNC_STATE(state)); + + RTC_UNLOCK(); + + if (idx == RTC_ALARM_A) + MODIFY_REG(RTC->CON, RTC_CON_ALMAEN_MSK, state << RTC_CON_ALMAEN_POS); + else + MODIFY_REG(RTC->CON, RTC_CON_ALMBEN_MSK, state << RTC_CON_ALMBEN_POS); + + RTC_LOCK(); + return; +} + +/** + * @brief Set shift parameters. + * @param add_1s: Enable/Disable added 1 second. + * @param sub_ss: value of sub-sconde. + * @retval ALD status. + */ +ald_status_t rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) +{ + uint32_t tick; + + assert_param(IS_FUNC_STATE(add_1s)); + assert_param(IS_SHIFT_SUB_SS(sub_ss)); + + RTC_UNLOCK(); + MODIFY_REG(RTC->SSECTR, RTC_SSECTR_TRIM_MSK, sub_ss << RTC_SSECTR_TRIM_POSS); + MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS); + RTC_LOCK(); + + tick = __get_tick(); + + while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK)) + { + if ((__get_tick() - tick) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } + + return OK; +} + +/** + * @brief Set calibation + * @param config: pointer to rtc_cali_t structure. + * @retval None + */ +void rtc_set_cali(rtc_cali_t *config) +{ + assert_param(IS_RTC_CALI_FREQ(config->cali_freq)); + assert_param(IS_RTC_CALI_TC(config->tc)); + assert_param(IS_RTC_CALC_FREQ(config->calc_freq)); + assert_param(IS_RTC_CALI_CALC(config->calc)); + assert_param(IS_FUNC_STATE(config->acc)); + + RTC_UNLOCK(); + RTC_CALI_UNLOCK(); + + MODIFY_REG(RTC->CALCON, RTC_CALCON_CALP_MSK, config->cali_freq << RTC_CALCON_CALP_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, config->tc << RTC_CALCON_TCM_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, config->calc_freq << RTC_CALCON_TCP_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_ALG_MSK, config->calc << RTC_CALCON_ALG_POS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_DCMACC_MSK, config->acc << RTC_CALCON_DCMACC_POS); + SET_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); + + RTC_CALI_LOCK(); + RTC_LOCK(); + + return; +} + +/** + * @brief Cancel calibration + * @retval None + */ +void rtc_cancel_cali(void) +{ + RTC_CALI_UNLOCK(); + CLEAR_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); + RTC_CALI_LOCK(); + + return; +} + +/** + * @brief Get calibration status. + * @retval ALD status. + */ +ald_status_t rtc_get_cali_status(void) +{ + if (READ_BIT(RTC->CALCON, RTC_CALCON_ERR_MSK)) + return ERROR; + else + return OK; +} + +/** + * @brief Write temperature value. + * @param temp: the value of temperature. + * @retval None + */ +void rtc_write_temp(uint16_t temp) +{ + RTC_CALI_UNLOCK(); + MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, temp << RTC_TEMPR_VAL_POSS); + RTC_CALI_LOCK(); + + return; +} + +/** + * @brief Get the status of RTC interrupt source. + * @param it: Specifies the RTC interrupt source. + * This parameter can be one of the @ref rtc_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t rtc_get_it_status(rtc_it_t it) +{ + assert_param(IS_RTC_IT(it)); + + if (READ_BIT(RTC->IER, it)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of RTC interrupt flag. + * @param flag: Specifies the RTC interrupt flag. + * This parameter can be one of the @ref rtc_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t rtc_get_flag_status(rtc_flag_t flag) +{ + assert_param(IS_RTC_IF(flag)); + + if (READ_BIT(RTC->IFR, flag)) + return SET; + + return RESET; +} + +/** @brief Clear the specified RTC pending flag. + * @param flag: specifies the flag to check. + * @retval None. + */ +void rtc_clear_flag_status(rtc_flag_t flag) +{ + assert_param(IS_RTC_IF(flag)); + + RTC_UNLOCK(); + WRITE_REG(RTC->IFCR, flag); + RTC_LOCK(); + + return; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_RTC */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c new file mode 100644 index 0000000000..79f2af9ac7 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c @@ -0,0 +1,937 @@ +/** + ********************************************************************************* + * + * @file ald_smartcard.c + * @brief SMARTCARD module driver. + * This file provides firmware functions to manage the following + * functionalities of the SMARTCARD peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + * @version V1.0 + * @date 25 Apr 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SMARTCARD driver can be used as follows: + + (#) Declare a smartcard_handle_t handle structure. + (##) Enable the interface clock of the USARTx associated to the SMARTCARD. + (##) SMARTCARD pins configuration: + (+++) Enable the clock for the SMARTCARD GPIOs. + (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). + (##) NVIC configuration if you need to use interrupt process (smartcard_send_by_it() + and smartcard_recv_by_it() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (##) DMA Configuration if you need to use DMA process (smartcard_send_by_dma() + and smartcard_recv_by_dma() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initilalized DMA handle to the SMARTCARD DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle + (used for last byte sending completion detection in DMA non circular mode) + + (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure. + + (#) Initialize the SMARTCARD registers by calling the smartcard_init() API. + + (#) Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using smartcard_send() + (+) Receive an amount of data in blocking mode using smartcard_recv() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using smartcard_send_by_it() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode using smartcard_recv_by_it() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using smartcard_send_by_dma() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode (DMA) using smartcard_recv_by_dma() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk()() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + + *** SMARTCARD ALD driver macros list *** + ======================================== + [..] + Below the list of most used macros in SMARTCARD ALD driver. + + (+) SMARTCARD_ENABLE: Enable the SmartCard peripheral. + (+) SMARTCARD_DISABLE: Disable the SmartCard peripheral. + (+) smartcard_reset_HANDLE_STATE : Reset SmartCard handle. + (+) SMARTCARD_FLUSH_DRREGISTER : Flush SmartCard data. + + [..] + (@) You can refer to the SMARTCARD library header file for more useful macros + + @endverbatim + ****************************************************************************** + */ + + +#include "ald_smartcard.h" +#include "ald_cmu.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup SMARTCARD SMARTCARD + * @brief SMARTCARD module driver + * @{ + */ + +#ifdef ALD_SMARTCARD + +/** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions + * @{ + */ +static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh); +static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hsmartcard); +static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh); +static void smartcard_set_config(smartcard_handle_t *hperh); +#ifdef ALD_DMA + static void smartcard_dma_send_cplt(void *arg); + static void smartcard_dma_recv_cplt(void *arg); + static void smartcard_dma_error(void *arg); +#endif +static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout); +/** + * @} + */ + +/** @defgroup SMARTCARD_Public_Functions SMARTCARD Public Functions + * @{ + */ + +/** @defgroup SMARTCARD_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + * @verbatim + + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USART + in Smartcard mode. + [..] + The Smartcard interface is designed to support asynchronous protocol Smartcards as + defined in the ISO 7816-3 standard. + [..] + The USART can provide a clock to the smartcard through the SCLK output. + In smartcard mode, SCLK is not associated to the communication but is simply derived + from the internal peripheral input clock through a 5-bit prescaler. + [..] + (+) For the Smartcard mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length => Should be 9 bits (8 bits + parity) + (++) Stop Bit + (++) Parity: => Should be enabled + (++) USART polarity + (++) USART phase + (++) USART LastBit + (++) Receiver/transmitter modes + (++) Prescaler + (++) GuardTime + (++) NACKState: The Smartcard NACK state + + (+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card: + (++) word Length = 9 Bits + (++) 1.5 Stop Bit + (++) Even parity + (++) BaudRate = 12096 baud + (++) Tx and Rx enabled + [..] + Please refer to the ISO 7816-3 specification for more details. + + (@) It is also possible to choose 0.5 stop bit for receiving but it is recommended + to use 1.5 stop bits for both transmitting and receiving to avoid switching + between the two configurations. + [..] + The smartcard_init() function follows the USART SmartCard configuration procedure. + + @endverbatim + * @{ + */ + +/* + Additionnal remark on the smartcard frame: + +-------------------------------------------------------------+ + | M bit | PCE bit | SMARTCARD frame | + |---------------------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ +*/ + +/** + * @brief Initializes the SmartCard mode according to the specified + * parameters in the smartcard_handle_t and create the associated handle. + * @param hperh: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t smartcard_init(smartcard_handle_t *hperh) +{ + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_USART_PARITY(hperh->init.parity)); + assert_param(IS_USART(hperh->perh)); + assert_param(IS_FUNC_STATE(hperh->init.nack)); + assert_param(IS_SMARTCARD_PRESCALER(hperh->init.prescaler)); + + if (hperh->state == SMARTCARD_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = SMARTCARD_STATE_BUSY; + SMARTCARD_DISABLE(hperh); + + MODIFY_REG(hperh->perh->GP, USART_GP_PSC_MSK, hperh->init.prescaler << USART_GP_PSC_POSS); + MODIFY_REG(hperh->perh->GP, USART_GP_GTVAL_MSK, hperh->init.guard_time << USART_GP_GTVAL_POSS); + smartcard_set_config(hperh); + + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + + SMARTCARD_ENABLE(hperh); + MODIFY_REG(hperh->perh->CON2, USART_CON2_NACK_MSK, hperh->init.nack << USART_CON2_NACK_POS); + SET_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + + hperh->err_code = SMARTCARD_ERROR_NONE; + hperh->state = SMARTCARD_STATE_READY; + return OK; +} + +/** + * @brief Reset SMARTCARD register. + * @param hperh: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t smartcard_reset(smartcard_handle_t *hperh) +{ + assert_param(IS_USART(hperh->perh)); + + hperh->state = SMARTCARD_STATE_BUSY; + SMARTCARD_DISABLE(hperh); + + WRITE_REG(hperh->perh->CON0, 0x0); + WRITE_REG(hperh->perh->CON1, 0x0); + WRITE_REG(hperh->perh->CON2, 0x0); + WRITE_REG(hperh->perh->BAUDCON, 0x0); + WRITE_REG(hperh->perh->GP, 0x0); + + hperh->err_code = SMARTCARD_ERROR_NONE; + hperh->state = SMARTCARD_STATE_RESET; + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup SMARTCARD_Public_Functions_Group2 IO operation functions + * @brief SMARTCARD Transmit and Receive functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SMARTCARD data transfers. + + [..] + (#) Smartcard is a single wire half duplex communication protocol. + The Smartcard interface is designed to support asynchronous protocol Smartcards as + defined in the ISO 7816-3 standard. + (#) The USART should be configured as: + (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register + (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The library status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, the relevant API's return the library status. + The end of the data processing will be indicated through the + dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks + will be executed respectively at the end of the Transmit or Receive process + The hperh->error_cbk() user callback will be executed when a communication + error is detected. + + (#) Blocking mode APIs are : + (++) smartcard_send() + (++) smartcard_recv() + + (#) Non Blocking mode APIs with Interrupt are : + (++) smartcard_send_by_it() + (++) smartcard_recv_by_it() + (++) smartcard_irq_handle() + + (#) Non Blocking mode functions with DMA are : + (++) smartcard_send_by_dma() + (++) smartcard_recv_by_dma() + + * @endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @param hperh: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Specify timeout value + * @retval Status, see @ref ald_status_t. + */ +ald_status_t smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = SMARTCARD_ERROR_NONE; + SET_BIT(hperh->state, USART_STATE_TX_MASK); + + hperh->tx_size = size; + hperh->tx_count = size; + + while (hperh->tx_count-- > 0) + { + if (smartcard_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) + { + hperh->state = SMARTCARD_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + WRITE_REG(hperh->perh->DATA, *buf++); + } + + if (smartcard_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) + { + hperh->state = SMARTCARD_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hperh: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Specify timeout value + * @retval Status, see @ref ald_status_t. + */ +ald_status_t smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = SMARTCARD_ERROR_NONE; + SET_BIT(hperh->state, USART_STATE_RX_MASK); + + hperh->rx_size = size; + hperh->rx_count = size; + + while (hperh->rx_count-- > 0) + { + if (smartcard_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) + { + hperh->state = SMARTCARD_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + + __UNLOCK(hperh); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + + return OK; +} + +/** + * @brief Sends an amount of data in non-blocking mode. + * @param hperh: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_TX_MASK); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = SMARTCARD_ERROR_NONE; + + __UNLOCK(hperh); + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, ENABLE); + + return OK; +} + +/** + * @brief Receives an amount of data in non-blocking mode. + * @param hperh: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @retval Status, see @ref ald_status_t. + */ +ald_status_t smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = SMARTCARD_ERROR_NONE; + + __UNLOCK(hperh); + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, ENABLE); + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, ENABLE); + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Sends an amount of data in non-blocking mode. + * @param hperh: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as USART transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_TX_MASK); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = SMARTCARD_ERROR_NONE; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = smartcard_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = smartcard_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = channel; + dma_config_basic(&hperh->hdmatx); + + usart_clear_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); + __UNLOCK(hperh); + usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, ENABLE); + + return OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode. + * @param hperh: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param channel: DMA channel as USART transmit + * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = SMARTCARD_ERROR_NONE; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = smartcard_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = smartcard_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; + hperh->hdmarx.config.channel = channel; + dma_config_basic(&hperh->hdmarx); + + __UNLOCK(hperh); + usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, ENABLE); + + return OK; +} +#endif + +/** + * @brief This function handles SMARTCARD interrupt request. + * @param hperh: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +void smartcard_irq_handle(smartcard_handle_t *hperh) +{ + uint32_t flag; + uint32_t source; + + /* Handle parity error */ + flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_PE); + source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_PE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= SMARTCARD_ERROR_PE; + + /* Handle frame error */ + flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_FE); + source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_ERR); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= SMARTCARD_ERROR_FE; + + /* Handle noise error */ + flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_NE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= SMARTCARD_ERROR_NE; + + /* Handle overrun error */ + flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_ORE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= SMARTCARD_ERROR_ORE; + + /* Handle receive */ + flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_RXNE); + source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) + __smartcard_recv_by_it(hperh); + + /* Handle transmit */ + flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TXE); + source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) + __smartcard_send_by_it(hperh); + + /* Handle transmit complete */ + flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); + source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_TC); + if ((flag != RESET) && (source != RESET)) + __smartcard_end_send_by_it(hperh); + + /* Handle error */ + if (hperh->err_code != SMARTCARD_ERROR_NONE) + { + USART_CLEAR_PEFLAG(hperh); + hperh->state = SMARTCARD_STATE_READY; + + if (hperh->error_cbk) + hperh->error_cbk(hperh); + } +} +/** + * @} + */ + +/** @defgroup SMARTCARD_Public_Functions_Group3 Peripheral State and Errors functions + * @brief SMARTCARD State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of SmartCard + communication process and also return Peripheral Errors occurred during communication process + (+) smartcard_get_state() API can be helpful to check in run-time the state + of the SMARTCARD peripheral. + (+) smartcard_get_error() check in run-time errors that could be occurred during + communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the SMARTCARD state. + * @param hperh: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval ALD state + */ +smartcard_state_t smartcard_get_state(smartcard_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the SMARTCARD error code + * @param hperh: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval SMARTCARD Error Code + */ +uint32_t smartcard_get_error(smartcard_handle_t *hperh) +{ + return hperh->err_code; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions + * @brief SMARTCARD Private functions + * @{ + */ + +#ifdef ALD_DMA +/** + * @brief DMA SMARTCARD transmit process complete callback. + * @param arg: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void smartcard_dma_send_cplt(void *arg) +{ + smartcard_handle_t *hperh = (smartcard_handle_t *)arg; + + hperh->tx_count = 0; + usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); + + return; +} + +/** + * @brief DMA SMARTCARD receive process complete callback. + * @param arg: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void smartcard_dma_recv_cplt(void *arg) +{ + smartcard_handle_t *hperh = (smartcard_handle_t *)arg; + + hperh->rx_count = 0; + usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + + return; +} + +/** + * @brief DMA SMARTCARD communication error callback. + * @param arg: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void smartcard_dma_error(void *arg) +{ + smartcard_handle_t *hperh = (smartcard_handle_t *)arg; + + hperh->rx_count = 0; + hperh->tx_count = 0; + hperh->err_code = SMARTCARD_ERROR_DMA; + hperh->state = SMARTCARD_STATE_READY; + + usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); + usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); + + if (hperh->error_cbk) + hperh->error_cbk(hperh); + + return; +} +#endif + +/** + * @brief This function handles USART Communication Timeout. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param flag: specifies the USART flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick; + + if (timeout == 0) + return OK; + + tick = __get_tick(); + + while ((usart_get_flag_status((usart_handle_t *)hperh, flag)) != status) + { + if (((__get_tick()) - tick) > timeout) + { + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + + return TIMEOUT; + } + } + + return OK; +} + +/** + * @brief Send an amount of data in non-blocking mode. + * @param hperh: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * Function called under interruption only, once + * interruptions have been enabled by smartcard_send_by_it() + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh) +{ + if ((hperh->state != SMARTCARD_STATE_BUSY_TX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX)) + return BUSY; + + WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); + + if (--hperh->tx_count == 0) + { + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); + } + + return OK; +} + + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hperh: pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hperh) +{ + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); + + if (hperh->state == SMARTCARD_STATE_READY) + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return OK; +} + + +/** + * @brief Receive an amount of data in non-blocking mode. + * @param hperh: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh) +{ + if ((hperh->state != SMARTCARD_STATE_BUSY_RX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX)) + return BUSY; + + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + + if (--hperh->rx_count == 0) + { + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); + usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return OK; +} + +/** + * @brief Configures the SMARTCARD peripheral. + * @param hperh: Pointer to a smartcard_handle_t structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void smartcard_set_config(smartcard_handle_t *hperh) +{ + uint32_t tmp; + uint32_t integer; + uint32_t fractional; + + /* Check the parameters */ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_BAUDRATE(hperh->init.baud)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_USART_PARITY(hperh->init.parity)); + assert_param(IS_USART_MODE(hperh->init.mode)); + + MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS); + tmp = READ_REG(hperh->perh->CON0); + MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS); + + if (hperh->init.parity == USART_PARITY_NONE) + CLEAR_BIT(tmp, USART_CON0_PEN_MSK); + else + SET_BIT(tmp, USART_CON0_PEN_MSK); + + if (hperh->init.parity == USART_PARITY_ODD) + SET_BIT(tmp, USART_CON0_PSEL_MSK); + else + CLEAR_BIT(tmp, USART_CON0_PSEL_MSK); + + WRITE_REG(hperh->perh->CON0, tmp); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RTSEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_CTSEN_MSK); + MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS); + MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS); + tmp = READ_REG(hperh->perh->CON1); + SET_BIT(tmp, USART_CON1_SCKEN_MSK); + MODIFY_REG(tmp, USART_CON1_SCKPOL_MSK, hperh->init.polarity << USART_CON1_SCKPOL_POS); + MODIFY_REG(tmp, USART_CON1_SCKPHA_MSK, hperh->init.phase << USART_CON1_SCKPHA_POS); + MODIFY_REG(tmp, USART_CON1_LBCP_MSK, hperh->init.last_bit << USART_CON1_LBCP_POS); + + /* Determine the integer part */ + if (READ_BIT(hperh->perh->CON0, (1 << 15))) + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integer = ((25 * cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); + } + else + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integer = ((25 * cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); + } + tmp = (integer / 100) << 4; + + /* Determine the fractional part */ + fractional = integer - (100 * (tmp >> 4)); + + /* Implement the fractional part in the register */ + if (READ_BIT(hperh->perh->CON0, (1 << 15))) + tmp |= ((((fractional * 8) + 50) / 100)) & ((uint8_t)0x07); + else + tmp |= ((((fractional * 16) + 50) / 100)) & ((uint8_t)0x0F); + + WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp); + return; +} + +/** + * @} + */ + +#endif /* ALD_SMARTCARD */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c new file mode 100644 index 0000000000..45e24960f8 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c @@ -0,0 +1,1840 @@ +/** + ********************************************************************************* + * + * @file ald_spi.c + * @brief SPI module driver. + * This file provides firmware functions to manage the following + * functionalities of SPI peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + * @version V1.0 + * @date 13 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI driver can be used as follows: + + (#) Declare a spi_handle_t structure, for example: + spi_handle_t hperh; + + (#) Initialize the SPI low level resources: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as push-pull + (##) NVIC configuration if you need to use interrupt process + by implementing the mcu_irq_config() API. + Invoked spi_irq_handle() function in SPI-IRQ function + (##) DMA Configuration if you need to use DMA process + (+++) Define ALD_DMA in ald_conf.h + (+++) Enable the DMAx clock + + (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI module by invoking the spi_init() API. + + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the spi_dma_pause()/ spi_dma_stop(). + + * @endverbatim + */ + +#include "ald_spi.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI module driver + * @{ + */ +#ifdef ALD_SPI + +/** @addtogroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static ald_status_t spi_wait_flag(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout); +static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout); +static void __spi_send_by_it(spi_handle_t *hperh); +static void __spi_recv_by_it(spi_handle_t *hperh); +static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); +#ifdef ALD_DMA + static void spi_dma_send_cplt(void *arg); + static void spi_dma_recv_cplt(void *arg); + static void spi_dma_send_recv_cplt(void *arg); + static void spi_dma_error(void *arg); +#endif +/** + * @} + */ + +/** @defgroup SPI_Public_Functions SPI Public Functions + * @{ + */ + +/** @defgroup SPI_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + * @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + reset the SPIx peripheral: + + (+) User must configure all related peripherals resources + (CLOCK, GPIO, DMA, NVIC). + + (+) Call the function spi_init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + + (+) Call the function spi_reset() to reset the selected SPIx periperal. + + @endverbatim + * @{ + */ + +/** + * @brief Reset the SPI peripheral. + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void spi_reset(spi_handle_t *hperh) +{ + hperh->perh->CON1 = 0x0; + hperh->perh->CON2 = 0x0; + hperh->perh->CRCPOLY = 0x00000007; + + SPI_RESET_HANDLE_STATE(hperh); + __UNLOCK(hperh); + + return; +} + +/** + * @brief Initializes the SPI mode according to the specified parameters in + * the SPI_init_t and create the associated handle. + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t spi_init(spi_handle_t *hperh) +{ + uint32_t tmp = 0; + + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_MODE(hperh->init.mode)); + assert_param(IS_SPI_DIRECTION(hperh->init.dir)); + assert_param(IS_SPI_BAUD(hperh->init.baud)); + assert_param(IS_FUNC_STATE(hperh->init.first_bit)); + assert_param(IS_FUNC_STATE(hperh->init.ss_en)); + assert_param(IS_FUNC_STATE(hperh->init.crc_calc)); + assert_param(IS_SPI_DATASIZE(hperh->init.data_size)); + assert_param(IS_SPI_CPHA(hperh->init.phase)); + assert_param(IS_SPI_CPOL(hperh->init.polarity)); + + if (hperh == NULL) + return ERROR; + + spi_reset(hperh); + + tmp = hperh->perh->CON1; + + if (hperh->init.mode == SPI_MODE_MASTER) + tmp |= 1 << SPI_CON1_SSOUT_POS; + + tmp |= ((hperh->init.phase << SPI_CON1_CPHA_POS) | (hperh->init.polarity << SPI_CON1_CPOL_POS) | + (hperh->init.baud << SPI_CON1_BAUD_POSS) | (hperh->init.data_size << SPI_CON1_FLEN_POS) | + (hperh->init.mode << SPI_CON1_MSTREN_POS) | (hperh->init.ss_en << SPI_CON1_SSEN_POS) | + (hperh->init.first_bit << SPI_CON1_LSBFST_POS)); + + hperh->perh->CON1 = tmp; + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + { + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); + } + else if (hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) + { + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + SET_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); + } + else + { + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + } + + /* configure CRC */ + hperh->perh->CON1 |= (hperh->init.crc_calc << SPI_CON1_CRCEN_POS); + hperh->perh->CRCPOLY = hperh->init.crc_poly; + + hperh->err_code = SPI_ERROR_NONE; + hperh->state = SPI_STATE_READY; + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + SPI_ENABLE(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group2 IO operation functions + * @brief SPI Transmit and Receive functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master or slave mode: + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The ALD status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the ALD status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The hperh->err_cbk() user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + + * @endverbatim + * @{ + */ + +/** + * @brief transmit one byte fast in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param data: Data to be sent + * @retval status: + * - 0 Success + * - -1 Failed + */ +int32_t spi_send_byte_fast(spi_handle_t *hperh, uint8_t data) +{ + uint16_t cnt = 2000, temp; + + hperh->perh->DATA = data; + while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); + + while ((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0); + temp = hperh->perh->DATA; + UNUSED(temp); + + return cnt == 0 ? -1 : 0; +} + +/** + * @brief Receive one byte fast in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Data. + */ +uint8_t spi_recv_byte_fast(spi_handle_t *hperh) +{ + uint16_t cnt = 2000; + + if (hperh->init.mode == SPI_MODE_MASTER) + { + hperh->perh->DATA = 0xFF; + while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); + } + + cnt = 2000; + while (((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0) && (--cnt)); + return (uint8_t)hperh->perh->DATA; +} + +/** + * @brief transmit an amount of data in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + + hperh->state = SPI_STATE_BUSY_TX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + if (hperh->init.dir == SPI_DIRECTION_1LINE) + SPI_1LINE_TX(hperh); + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + SPI_ENABLE(hperh); + + if ((hperh->init.mode == SPI_MODE_SLAVER) || (hperh->tx_count == 1)) + { + if (hperh->init.data_size == SPI_DATA_SIZE_8) + { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else + { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + } + + while (hperh->tx_count > 0) + { + if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) + { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) + { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else + { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + } + + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + + if ((spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) + || (spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) + { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + spi_clear_flag_status(hperh, SPI_IF_OVE); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + uint16_t temp; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) + SPI_1LINE_RX(hperh); + + if ((hperh->init.mode == SPI_MODE_MASTER) && (hperh->init.dir == SPI_DIRECTION_2LINES)) + { + __UNLOCK(hperh); + hperh->state = SPI_STATE_READY; + return spi_send_recv(hperh, buf, buf, size, timeout); + } + + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); + + while (hperh->rx_count > 1) + { + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) + { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) + { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else + { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) + { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) + { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else + { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + --hperh->rx_count; + } + + if (hperh->init.crc_calc) + { + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) + { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) + { + hperh->err_code |= SPI_ERROR_CRC; + SPI_CRC_RESET(hperh); + spi_clear_flag_status(hperh, SPI_IF_CRCERR); + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return ERROR; + } + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). + * @param hperh: Pointer to a spi_handle_t structure. + * @param tx_buf: Pointer to data transmitted buffer + * @param rx_buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) +{ + uint16_t temp; + + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (hperh->init.dir != SPI_DIRECTION_2LINES) + return ERROR; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if ((hperh->init.mode == SPI_MODE_SLAVER) || ((hperh->init.mode == SPI_MODE_SLAVER) && (hperh->tx_size == 1))) + { + if (hperh->init.data_size == SPI_DATA_SIZE_8) + { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else + { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + } + + if (hperh->tx_buf == 0) + { + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + + if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) + { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) + { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else + { + (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + while (hperh->tx_count > 0) + { + if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) + { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) + { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else + { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + + if ((hperh->tx_count == 0) && (hperh->init.crc_calc)) + SPI_CRCNEXT_ENABLE(hperh); + + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) + { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) + { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else + { + (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; + + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + if (hperh->init.mode == SPI_MODE_SLAVER) + { + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) + { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) + { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else + { + (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; + + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + if (hperh->init.crc_calc) + { + if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) + { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if ((spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) + { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) + { + hperh->err_code |= SPI_ERROR_CRC; + SPI_CRC_RESET(hperh); + spi_clear_flag_status(hperh, SPI_IF_CRCERR); + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return ERROR; + } + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hperh: pointer to a spi_handle_t structure. + * @param buf: Pointer to data transmitted buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + __UNLOCK(hperh); + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->init.dir == SPI_DIRECTION_1LINE) + SPI_1LINE_TX(hperh); + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + { + spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + } + else + { + spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); + } + + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + SPI_ENABLE(hperh); + + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) + return ERROR; /* Please call spi_send_recv_by_it() */ + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + __UNLOCK(hperh); + + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) + SPI_1LINE_RX(hperh); + + if (hperh->init.crc_calc == ENABLE) + SPI_CRC_RESET(hperh); + + spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); + spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); + + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); + + return OK; +} + +/** + * @brief Transmit and Receives an amount of data in non blocking mode + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @param tx_buf: Pointer to data transmitted buffer + * @param rx_buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + __UNLOCK(hperh); + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); + spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Transmit an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as SPI transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + if (hperh->init.dir == SPI_DIRECTION_1LINE) + SPI_1LINE_TX(hperh); + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.cplt_cbk = spi_dma_send_cplt; + hperh->hdmatx.err_arg = (void *)hperh; + hperh->hdmatx.err_cbk = spi_dma_error; + + /* Configure SPI DMA transmit */ + dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = channel; + dma_config_basic(&(hperh->hdmatx)); + + __UNLOCK(hperh); + spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + SPI_ENABLE(hperh); + + return OK; +} + +/** + * @brief Receive an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as SPI transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) + SPI_1LINE_RX(hperh); + if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) + { + __UNLOCK(hperh); + return ERROR; /* Please use spi_send_recv_by_dma() */ + } + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.cplt_cbk = spi_dma_recv_cplt; + hperh->hdmarx.err_arg = (void *)hperh; + hperh->hdmarx.err_cbk = spi_dma_error; + + /* Configure DMA Receive */ + dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; + hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.channel = channel; + dma_config_basic(&(hperh->hdmarx)); + + __UNLOCK(hperh); + spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); + + return OK; +} + +/** + * @brief Transmit and Receive an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param tx_buf: Pointer to data buffer + * @param rx_buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param tx_channel: DMA channel as SPI transmit + * @param rx_channel: DMA channel as SPI receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY && hperh->state != SPI_STATE_BUSY_RX) + return BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmatx.cplt_arg = NULL; + hperh->hdmatx.cplt_cbk = NULL; + hperh->hdmatx.err_arg = (void *)hperh; + hperh->hdmatx.err_cbk = spi_dma_error; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.cplt_cbk = spi_dma_send_recv_cplt; + hperh->hdmarx.err_arg = (void *)hperh; + hperh->hdmarx.err_cbk = spi_dma_error; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + /* Configure SPI DMA transmit */ + dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)tx_buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = tx_channel; + dma_config_basic(&(hperh->hdmatx)); + + /* Configure DMA Receive */ + dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)rx_buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; + hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.channel = rx_channel; + dma_config_basic(&(hperh->hdmarx)); + + __UNLOCK(hperh); + spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + + return OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t spi_dma_pause(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t spi_dma_resume(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t spi_dma_stop(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); + + hperh->state = SPI_STATE_READY; + return OK; +} +#endif +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group3 Control functions + * @brief SPI Control functions + * + * @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) Handle interrupt about SPI module. The spi_irq_handle() function must + be invoked by SPI-IRQ function. + (+) Configure the interrupt DISABLE/ENABLE. + (+) Configure the DMA request. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag + + @endverbatim + * @{ + */ + +/** + * @brief This function handles SPI interrupt request. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval None + */ +void spi_irq_handle(spi_handle_t *hperh) +{ + if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX)) + { + if ((spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) + __spi_recv_by_it(hperh); + + if ((spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) + __spi_send_by_it(hperh); + } + + else if (hperh->state == SPI_STATE_BUSY_TX_RX) + { + if (hperh->tx_size == hperh->tx_count) + { + if ((spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_TXBE); + } + else + { + if ((spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET) + && (spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_TXBE_RXBNE); + } + } + + if ((spi_get_it_status(hperh, SPI_IT_ERR) != RESET)) + { + if (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) + { + hperh->err_code |= SPI_ERROR_CRC; + spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + if (spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) + { + hperh->err_code |= SPI_ERROR_MODF; + spi_clear_flag_status(hperh, SPI_IF_MODF); + } + if (spi_get_flag_status(hperh, SPI_IF_OVE) != RESET) + { + if (hperh->state != SPI_STATE_BUSY_TX) + { + hperh->err_code |= SPI_ERROR_OVE; + spi_clear_flag_status(hperh, SPI_IF_OVE); + } + } + + if (hperh->err_code != SPI_ERROR_NONE) + { + spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + } + + return; +} + +/** + * @brief Enables or disables the specified SPI interrupts. + * @param hperh: Pointer to a spi_handle_t structure. + * @param it: Specifies the SPI interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref spi_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->CON2 |= (uint32_t)it; + else + hperh->perh->CON2 &= ~((uint32_t)it); + + return; +} + +/** + * @brief Configure the specified SPI speed. + * @param hperh: Pointer to a spi_handle_t structure. + * @param speed: Specifies the SPI speed. + * This parameter can be one of the @ref spi_baud_t. + * @retval None + */ +void spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) +{ + uint32_t tmp = 0; + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_BAUD(speed)); + + tmp = hperh->perh->CON1; + tmp &= ~(0x7 << SPI_CON1_BAUD_POSS); + tmp |= (speed << SPI_CON1_BAUD_POSS); + hperh->perh->CON1 = tmp; + return; +} + +/** + * @brief Enables or disables the dma request. + * @param hperh: Pointer to a spi_handle_t structure. + * @param req: Specifies the SPI dma request sources to be enabled or disabled. + * This parameter can be one of the @ref spi_dma_req_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + { + if (req == SPI_DMA_REQ_TX) + SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + else + { + if (req == SPI_DMA_REQ_TX) + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + + return; +} + +/** + * @brief Checks whether the specified SPI interrupt has occurred or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param it: Specifies the SPI interrupt source to check. + * This parameter can be one of the @ref spi_it_t. + * @retval Status + * - SET + * - RESET + */ +it_status_t spi_get_it_status(spi_handle_t *hperh, spi_it_t it) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IT(it)); + + if (hperh->perh->CON2 & it) + return SET; + + return RESET; +} + +/** @brief Check whether the specified SPI flag is set or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref spi_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IF(flag)); + + if (hperh->perh->STAT & flag) + return SET; + + return RESET; +} + +/** @brief Clear the specified SPI pending flags. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref spi_flag_t. + * @retval None + */ +void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) +{ + uint32_t temp; + + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IF(flag)); + + if (flag == SPI_IF_CRCERR) + { + SET_BIT(hperh->perh->STAT, SPI_STAT_CRCERR_MSK); + return; + } + if (flag == SPI_IF_OVE) + { + temp = hperh->perh->DATA; + temp = hperh->perh->STAT; + UNUSED(temp); + return; + } + if (flag == SPI_IF_MODF) + { + temp = hperh->perh->STAT; + UNUSED(temp); + hperh->perh->CON1 = hperh->perh->CON1; + return; + } + + return; +} + +/** + * @brief This function handles SPI communication timeout. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the SPI flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t spi_wait_flag(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick = __get_tick(); + + assert_param(timeout > 0); + + while ((spi_get_flag_status(hperh, flag)) != status) + { + if (((__get_tick()) - tick) > timeout) + { + spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + return TIMEOUT; + } + } + + return OK; +} + +/** + * @brief This function handles SPI communication timeout in interrupt function. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the SPI flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout) +{ + assert_param(timeout > 0); + + while (((spi_get_flag_status(hperh, flag)) != status) && (--timeout)); + + if (timeout) + return OK; + + spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + + return TIMEOUT; +} + +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group4 Peripheral State and Errors functions + * @brief SPI State and Errors functions + * + * @verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) spi_get_state() API can check in run-time the state of the SPI peripheral + (+) spi_get_error() check in run-time Errors occurring during communication + + @endverbatim + * @{ + */ + +/** + * @brief Returns the SPI state. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval ALD state + */ +spi_state_t spi_get_state(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + return hperh->state; +} + +/** + * @brief Return the SPI error code + * @param hperh: Pointer to a spi_handle_t structure. + * @retval SPI Error Code + */ +uint32_t spi_get_error(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + return hperh->err_code; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Functions SPI Private Functions + * @brief SPI Private functions + * @{ + */ + +/** + * @brief handle program when an tx empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_send_by_it(spi_handle_t *hperh) +{ + if (hperh->tx_count == 0) + { + spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + spi_clear_flag_status(hperh, SPI_IF_OVE); + + if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) + { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) + { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else + { + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + --hperh->tx_count; + + if (hperh->tx_count == 0) + { + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + } + + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_recv_by_it(spi_handle_t *hperh) +{ + uint16_t temp; + if (hperh->init.data_size == SPI_DATA_SIZE_8) + { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else + { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + --hperh->rx_count; + + if ((hperh->rx_count == 1) && (hperh->init.crc_calc)) + SPI_CRCNEXT_ENABLE(hperh); + + if (hperh->rx_count == 0) + { + spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + hperh->state = SPI_STATE_READY; + + if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) + { + hperh->err_code |= SPI_ERROR_CRC; + spi_clear_flag_status(hperh, SPI_IF_CRCERR); + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->init.crc_calc) + { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode(2 lines) + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: SR.TXE or SR.RXNE set. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) +{ + assert_param(IS_SPI_SR_STATUS(status)); + + if (hperh->rx_count != 0) + { + if ((status == SPI_SR_RXBNE) || (status == SPI_SR_TXBE_RXBNE)) + { + if (hperh->init.data_size == SPI_DATA_SIZE_8) + { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else + { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + + --hperh->rx_count; + } + } + + if (hperh->tx_count != 0) + { + if ((status == SPI_SR_TXBE) || (status == SPI_SR_TXBE_RXBNE)) + { + if (hperh->tx_count == 1) + { + if (hperh->init.data_size == SPI_DATA_SIZE_8) + { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else + { + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + + --hperh->tx_count; + + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + } + else + { + if (hperh->init.data_size == SPI_DATA_SIZE_8) + { + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else + { + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + + if (--hperh->tx_count == 0) + { + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + } + } + } + } + + if (hperh->rx_count == 0) + { + spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + hperh->state = SPI_STATE_READY; + + if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) + { + hperh->err_code |= SPI_ERROR_CRC; + spi_clear_flag_status(hperh, SPI_IF_CRCERR); + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->tx_rx_cplt_cbk) + hperh->tx_rx_cplt_cbk(hperh); + } + + return; +} + + +#ifdef ALD_DMA +/** + * @brief DMA SPI transmit process complete callback. + * @param arg: Pointer to a spi_handle_t structure. + * @retval None + */ +static void spi_dma_send_cplt(void *arg) +{ + uint16_t delay; + spi_handle_t *hperh = (spi_handle_t *)arg; + + hperh->tx_count = 0; + spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + spi_clear_flag_status(hperh, SPI_IF_OVE); + + if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + for (delay = 0; delay < 3000; delay++); + + if (hperh->err_code == SPI_ERROR_NONE) + { + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + else + { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA SPI receive process complete callback. + * @param arg: Pointer to a spi_handle_t structure. + * @retval None + */ +static void spi_dma_recv_cplt(void *arg) +{ + uint32_t tmp; + spi_handle_t *hperh = (spi_handle_t *)arg; + + hperh->rx_count = 0; + spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->init.crc_calc) + { + if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + tmp = hperh->perh->DATA; + UNUSED(tmp); + + if (spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) + { + SET_BIT(hperh->err_code, SPI_ERROR_CRC); + SPI_CRC_RESET(hperh); + spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + } + + if (hperh->err_code == SPI_ERROR_NONE) + { + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + else + { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA SPI transmit and receive process complete callback. + * @param arg: Pointer to a SPI_handle_t structure. + * @retval None + */ +static void spi_dma_send_recv_cplt(void *arg) +{ + uint32_t tmp; + uint16_t delay; + spi_handle_t *hperh = (spi_handle_t *)arg; + + if (hperh->init.crc_calc) + { + if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + tmp = hperh->perh->DATA; + UNUSED(tmp); + + if (spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) + { + SET_BIT(hperh->err_code, SPI_ERROR_CRC); + spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + } + + if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + for (delay = 0; delay < 3000; delay++); + + spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + hperh->tx_count = 0; + hperh->rx_count = 0; + hperh->state = SPI_STATE_READY; + + if (hperh->err_code == SPI_ERROR_NONE) + { + if (hperh->tx_rx_cplt_cbk) + hperh->tx_rx_cplt_cbk(hperh); + } + else + { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA SPI communication error callback. + * @param arg: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +static void spi_dma_error(void *arg) +{ + spi_handle_t *hperh = (spi_handle_t *)arg; + + spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + SET_BIT(hperh->err_code, SPI_ERROR_DMA); + + hperh->tx_count = 0; + hperh->rx_count = 0; + hperh->state = SPI_STATE_READY; + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; +} +#endif /* ALD_DMA */ +/** + * @} + */ +#endif /* ALD_SPI */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_temp.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_temp.c new file mode 100644 index 0000000000..4f311d1285 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_temp.c @@ -0,0 +1,213 @@ +/** + ********************************************************************************* + * + * @file ald_temp.c + * @brief TEMP module driver. + * + * @version V1.0 + * @date 15 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_temp.h" +#include "ald_bkpc.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup TEMP TEMP + * @brief TEMP module driver + * @{ + */ +#ifdef ALD_TEMP + + +/** @defgroup TEMP_Private_Variables TEMP Private Variables + * @{ + */ +temp_cbk __temp_cbk; +/** + * @} + */ + +/** @defgroup TEMP_Public_Functions TEMP Public Functions + * @{ + */ + +/** @addtogroup TEMP_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @verbatim + ============================================================================== + ##### Initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to initialize the TEMP: + (+) This parameters can be configured: + (++) Update Cycle + (++) Output Mode + (++) Perscaler + (+) Select TEMP source clock(default LOSC) + + @endverbatim + * @{ + */ + +/** + * @brief Initializes the TEMP according to the specified + * parameters in the temp_init_t. + * @param init: Pointer to a temp_init_t structure that contains + * the configuration information. + * @retval None + */ +void temp_init(temp_init_t *init) +{ + assert_param(IS_TEMP_UPDATE_CYCLE(init->cycle)); + assert_param(IS_TEMP_OUTPUT_MODE(init->mode)); + + TEMP_UNLOCK(); + MODIFY_REG(TEMP->CR, TEMP_CR_TSU_MSK, init->cycle << TEMP_CR_TSU_POSS); + MODIFY_REG(TEMP->CR, TEMP_CR_TOM_MSK, init->mode << TEMP_CR_TOM_POSS); + MODIFY_REG(TEMP->CR, TEMP_CR_CTN_MSK, init->ctn << TEMP_CR_CTN_POS); + MODIFY_REG(TEMP->PSR, TEMP_PSR_PRS_MSK, init->psc << TEMP_PSR_PRS_POSS); + TEMP_LOCK(); + + return; +} + +/** + * @brief Configure the TEMP source. + * @param sel: TEMP source type. + * @retval None + */ +void temp_source_selcet(temp_source_sel_t sel) +{ + assert_param(IS_TEMP_SOURCE_SEL(sel)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TEMPCS_MSK, sel << BKPC_PCCR_TEMPCS_POSS); + + if (sel == TEMP_SOURCE_LOSC) + { + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); + } + else if (sel == TEMP_SOURCE_LRC) + { + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); + } + else + { + ; /* do nothing */ + } + + BKPC_LOCK(); + return; +} +/** + * @} + */ + +/** @addtogroup TEMP_Public_Functions_Group2 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) temp_get_value() API can get the current temperature. + (+) temp_get_value_by_it() API can get the current temperature by interrupt. + (+) temp_irq_handle() API can handle the interrupt request. + + @endverbatim + * @{ + */ + +/** + * @brief Get the current temperature + * @param temp: The value of current temperature. + * @retval ALD status: + * @arg @ref OK The value is valid + * @arg @ref ERROR The value is invalid + */ +ald_status_t temp_get_value(uint16_t *temp) +{ + TEMP_UNLOCK(); + SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK); + SET_BIT(TEMP->CR, TEMP_CR_EN_MSK); + TEMP_LOCK(); + + while (!(READ_BIT(TEMP->IF, TEMP_IF_TEMP_MSK))); + + TEMP_UNLOCK(); + SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK); + TEMP_LOCK(); + + if (READ_BIT(TEMP->DR, TEMP_DR_ERR_MSK)) + return ERROR; + + *temp = READ_BITS(TEMP->DR, TEMP_DR_DATA_MSK, TEMP_DR_DATA_POSS); + return OK; +} + +/** + * @brief Get the current temperature by interrupt + * @param cbk: The callback function + * @retval None + */ +void temp_get_value_by_it(temp_cbk cbk) +{ + __temp_cbk = cbk; + + TEMP_UNLOCK(); + SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK); + SET_BIT(TEMP->IE, TEMP_IE_TEMP_MSK); + SET_BIT(TEMP->CR, TEMP_CR_EN_MSK); + TEMP_LOCK(); + + return; +} + +/** + * @brief This function handles TEMP interrupt request. + * @retval None + */ +void temp_irq_handle(void) +{ + TEMP_UNLOCK(); + SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK); + TEMP_LOCK(); + + if (__temp_cbk == NULL) + return; + + if (READ_BIT(TEMP->DR, TEMP_DR_ERR_MSK)) + { + __temp_cbk(0, ERROR); + return; + } + + __temp_cbk(READ_BITS(TEMP->DR, TEMP_DR_DATA_MSK, TEMP_DR_DATA_POSS), OK); + + return; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_TEMP */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c new file mode 100644 index 0000000000..d4419ebdec --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c @@ -0,0 +1,3774 @@ +/** + ********************************************************************************* + * + * @file ald_timer.c + * @brief TIMER module driver. + * This is the common part of the TIMER initialization + * + * @version V1.0 + * @date 06 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include +#include "ald_timer.h" +#include "ald_cmu.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup TIMER TIMER + * @brief TIMER module driver + * @{ + */ +#ifdef ALD_TIMER + +/** @defgroup TIMER_Private_Functions TIMER Private Functions + * @{ + */ +static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init); +static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); +static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); +static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); +static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); +static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state); +static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state); +static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter); +static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter); +static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter); +static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter); +static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter); +static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter); +static void timer_etr_set_config(TIMER_TypeDef *TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter); +static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config); +#ifdef ALD_DMA + static void timer_dma_oc_cplt(void *arg); + static void timer_dma_capture_cplt(void *arg); + static void timer_dma_period_elapse_cplt(void *arg); + static void timer_dma_error(void *arg); +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions TIMER Public Functions + * @{ + */ + +/** @defgroup TIMER_Public_Functions_Group1 TIMER Base functions + * @brief Time Base functions + * + * @verbatim + ============================================================================== + ##### Timer Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER base. + (+) Reset the TIMER base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Time base Unit according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER base handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_base_init(timer_handle_t *hperh) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = TIMER_STATE_BUSY; + timer_base_set_config(hperh->perh, &hperh->init); + hperh->state = TIMER_STATE_READY; + + return OK; +} + +/** + * @brief Reset the TIMER base peripheral + * @param hperh: TIMER base handle + * @retval Status, see @ref ald_status_t. + */ +void timer_base_reset(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = TIMER_STATE_BUSY; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_RESET; + __UNLOCK(hperh); + + return; +} + +/** + * @brief Starts the TIMER Base generation. + * @param hperh: TIMER handle + * @retval None + */ +void timer_base_start(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = TIMER_STATE_BUSY; + TIMER_ENABLE(hperh); + hperh->state = TIMER_STATE_READY; + + return; +} + +/** + * @brief Stops the TIMER Base generation. + * @param hperh: TIMER handle + * @retval None + */ +void timer_base_stop(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = TIMER_STATE_BUSY; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + + return; +} + +/** + * @brief Starts the TIMER Base generation in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void timer_base_start_by_it(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER Base generation in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void timer_base_stop_by_it(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE); + TIMER_DISABLE(hperh); + + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER Base generation in DMA mode. + * @param hperh: TIMER handle + * @param hdma: Pointer to dma_handle_t. + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. +*/ +ald_status_t timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) + { + if (((uint32_t)buf == 0) || (len == 0)) + return ERROR; + } + + hperh->state = TIMER_STATE_BUSY; + + if (hdma->perh == NULL) + hdma->perh = DMA0; + + hdma->cplt_cbk = timer_dma_period_elapse_cplt; + hdma->cplt_arg = (void *)hperh; + hdma->err_cbk = timer_dma_error; + hdma->err_arg = (void *)hperh; + + dma_config_struct(&hdma->config); + hdma->config.src = (void *)buf; + hdma->config.dst = (void *)&hperh->perh->AR; + hdma->config.size = len; + hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; + hdma->config.src_inc = DMA_DATA_INC_HALFWORD; + hdma->config.dst_inc = DMA_DATA_INC_NONE; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_UPDATE; + hdma->config.channel = dma_ch; + + if (hperh->perh == TIMER0) + hdma->config.msel = DMA_MSEL_TIMER0; + else if (hperh->perh == TIMER1) + hdma->config.msel = DMA_MSEL_TIMER1; + else if (hperh->perh == TIMER2) + hdma->config.msel = DMA_MSEL_TIMER2; + else if (hperh->perh == TIMER3) + hdma->config.msel = DMA_MSEL_TIMER3; + else if (hperh->perh == TIMER4) + hdma->config.msel = DMA_MSEL_TIMER4; + else if (hperh->perh == TIMER5) + hdma->config.msel = DMA_MSEL_TIMER5; + else if (hperh->perh == TIMER6) + hdma->config.msel = DMA_MSEL_TIMER6; + else if (hperh->perh == TIMER7) + hdma->config.msel = DMA_MSEL_TIMER7; + else + ; + + dma_config_basic(hdma); + timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE); + TIMER_ENABLE(hperh); + + return OK; +} + +/** + * @brief Stops the TIMER Base generation in DMA mode. + * @param hperh: TIMER handle + * @retval None +*/ +void timer_base_stop_by_dma(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE); + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group2 TIMER Output Compare functions + * @brief Time Output Compare functions + * + * @verbatim + ============================================================================== + ##### Time Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Output Compare. + (+) Start the Time Output Compare. + (+) Stop the Time Output Compare. + (+) Start the Time Output Compare and enable interrupt. + (+) Stop the Time Output Compare and disable interrupt. + (+) Start the Time Output Compare and enable DMA transfer. + (+) Stop the Time Output Compare and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Output Compare according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_oc_init(timer_handle_t *hperh) +{ + return timer_base_init(hperh); +} + +/** + * @brief Starts the TIMER Output Compare signal generation. + * @param hperh: TIMER handle + * @param ch : TIMER Channel to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void timer_oc_start(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Output Compare signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} + +/** + * @brief Starts the TIMER Output Compare signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + + case TIMER_CHANNEL_2: + timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + + case TIMER_CHANNEL_3: + timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + + case TIMER_CHANNEL_4: + timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Output Compare signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + + case TIMER_CHANNEL_4: + timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER Output Compare signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param hdma: Pointer to dma_handle_t. + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) + { + if (((uint32_t)buf == 0) || (len == 0)) + return ERROR; + } + + hperh->state = TIMER_STATE_BUSY; + + if (hdma->perh == NULL) + hdma->perh = DMA0; + + hdma->cplt_cbk = timer_dma_oc_cplt; + hdma->cplt_arg = (void *)hperh; + hdma->err_cbk = timer_dma_error; + hdma->err_arg = (void *)hperh; + + dma_config_struct(&hdma->config); + hdma->config.src = (void *)buf; + hdma->config.size = len; + hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; + hdma->config.src_inc = DMA_DATA_INC_HALFWORD; + hdma->config.dst_inc = DMA_DATA_INC_NONE; + hdma->config.channel = dma_ch; + + if (hperh->perh == TIMER0) + hdma->config.msel = DMA_MSEL_TIMER0; + else if (hperh->perh == TIMER1) + hdma->config.msel = DMA_MSEL_TIMER1; + else if (hperh->perh == TIMER2) + hdma->config.msel = DMA_MSEL_TIMER2; + else if (hperh->perh == TIMER3) + hdma->config.msel = DMA_MSEL_TIMER3; + else if (hperh->perh == TIMER4) + hdma->config.msel = DMA_MSEL_TIMER4; + else if (hperh->perh == TIMER5) + hdma->config.msel = DMA_MSEL_TIMER5; + else if (hperh->perh == TIMER6) + hdma->config.msel = DMA_MSEL_TIMER6; + else if (hperh->perh == TIMER7) + hdma->config.msel = DMA_MSEL_TIMER7; + else + ;//do nothing + + switch (ch) + { + case TIMER_CHANNEL_1: + hdma->config.dst = (void *)&hperh->perh->CCVAL1; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + dma_config_basic(hdma); + timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hdma->config.dst = (void *)&hperh->perh->CCVAL2; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + dma_config_basic(hdma); + timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hdma->config.dst = (void *)&hperh->perh->CCVAL3; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; + dma_config_basic(hdma); + timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + case TIMER_CHANNEL_4: + hdma->config.dst = (void *)&hperh->perh->CCVAL4; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; + dma_config_basic(hdma); + timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + TIMER_ENABLE(hperh); + return OK; +} + +/** + * @brief Stops the TIMER Output Compare signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None +*/ +void timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + + case TIMER_CHANNEL_4: + timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group3 TIMER PWM functions + * @brief TIMER PWM functions + * + * @verbatim + ============================================================================== + ##### Time PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER PWM. + (+) Start the Time PWM. + (+) Stop the Time PWM. + (+) Start the Time PWM and enable interrupt. + (+) Stop the Time PWM and disable interrupt. + (+) Start the Time PWM and enable DMA transfer. + (+) Stop the Time PWM and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER PWM Time Base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_pwm_init(timer_handle_t *hperh) +{ + return timer_base_init(hperh); +} + +/** + * @brief Starts the PWM signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch) +{ + timer_oc_start(hperh, ch); + return; +} + +/** + * @brief Stops the PWM signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + timer_oc_stop(hperh, ch); + return; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + timer_oc_start_by_it(hperh, ch); + return; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + timer_oc_stop_by_it(hperh, ch); + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER PWM signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param hdma: Pointer to dma_handle_t. + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + return timer_oc_start_by_dma(hperh, ch, hdma, buf, len, dma_ch); +} + +/** + * @brief Stops the TIMER PWM signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + timer_oc_stop_by_dma(hperh, ch); + return; +} +#endif +/** + * @brief Set the PWM freq. + * @param hperh: TIMER handle + * @param freq: PWM freq to set + * @retval None + */ +void timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) +{ + uint32_t _arr = cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1; + + WRITE_REG(hperh->perh->AR, _arr); + hperh->init.period = _arr; +} + +/** + * @brief Set the PWM duty. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param duty: PWM duty to set + * @retval None + */ +void timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty) +{ + uint32_t tmp = (hperh->init.period + 1) * duty / 100 - 1; + + if (ch == TIMER_CHANNEL_1) + WRITE_REG(hperh->perh->CCVAL1, tmp); + else if (ch == TIMER_CHANNEL_2) + WRITE_REG(hperh->perh->CCVAL2, tmp); + else if (ch == TIMER_CHANNEL_3) + WRITE_REG(hperh->perh->CCVAL3, tmp); + else if (ch == TIMER_CHANNEL_4) + WRITE_REG(hperh->perh->CCVAL4, tmp); + else + { + ;/* do nothing */ + } +} + +/** + * @brief Set capture the PWM. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be captured the PWM + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch)); + + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + switch (ch) + { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2EN_MSK); + + return; +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group4 TIMER Input Capture functions + * @brief Time Input Capture functions + * + * @verbatim + ============================================================================== + ##### Time Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Input Capture. + (+) Start the Time Input Capture. + (+) Stop the Time Input Capture. + (+) Start the Time Input Capture and enable interrupt. + (+) Stop the Time Input Capture and disable interrupt. + (+) Start the Time Input Capture and enable DMA transfer. + (+) Stop the Time Input Capture and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Input Capture Time base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_ic_init(timer_handle_t *hperh) +{ + return timer_base_init(hperh); +} + +/** + * @brief Starts the TIMER Input Capture measurement. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void timer_ic_start(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Input Capture measurement. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER Input Capture measurement in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + case TIMER_CHANNEL_2: + timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + case TIMER_CHANNEL_3: + timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + case TIMER_CHANNEL_4: + timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Input Capture measurement in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + case TIMER_CHANNEL_3: + timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + case TIMER_CHANNEL_4: + timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER Input Capture measurement in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param hdma: Pointer to dma_handle_t. + * @param buf: The destination Buffer address. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) + { + if (((uint32_t)buf == 0) || (len == 0)) + return ERROR; + } + + hperh->state = TIMER_STATE_BUSY; + + if (hdma->perh == NULL) + hdma->perh = DMA0; + + hdma->cplt_cbk = timer_dma_capture_cplt; + hdma->cplt_arg = (void *)hperh; + hdma->err_cbk = timer_dma_error; + hdma->err_arg = (void *)hperh; + + dma_config_struct(&hdma->config); + hdma->config.dst = (void *)buf; + hdma->config.size = len; + hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; + hdma->config.src_inc = DMA_DATA_INC_NONE; + hdma->config.dst_inc = DMA_DATA_INC_HALFWORD; + hdma->config.channel = dma_ch; + + if (hperh->perh == TIMER0) + hdma->config.msel = DMA_MSEL_TIMER0; + else if (hperh->perh == TIMER1) + hdma->config.msel = DMA_MSEL_TIMER1; + else if (hperh->perh == TIMER2) + hdma->config.msel = DMA_MSEL_TIMER2; + else if (hperh->perh == TIMER3) + hdma->config.msel = DMA_MSEL_TIMER3; + else if (hperh->perh == TIMER4) + hdma->config.msel = DMA_MSEL_TIMER4; + else if (hperh->perh == TIMER5) + hdma->config.msel = DMA_MSEL_TIMER5; + else if (hperh->perh == TIMER6) + hdma->config.msel = DMA_MSEL_TIMER6; + else if (hperh->perh == TIMER7) + hdma->config.msel = DMA_MSEL_TIMER7; + else + ;/* do nothing */ + + switch (ch) + { + case TIMER_CHANNEL_1: + hdma->config.src = (void *)&hperh->perh->CCVAL1; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + dma_config_basic(hdma); + timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hdma->config.src = (void *)&hperh->perh->CCVAL2; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + dma_config_basic(hdma); + timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hdma->config.src = (void *)&hperh->perh->CCVAL3; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; + dma_config_basic(hdma); + timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + case TIMER_CHANNEL_4: + hdma->config.src = (void *)&hperh->perh->CCVAL4; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; + dma_config_basic(hdma); + timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return OK; +} + +/** + * @brief Stops the TIMER Input Capture measurement in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + case TIMER_CHANNEL_3: + timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + case TIMER_CHANNEL_4: + timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group5 TIMER One Pulse functions + * @brief Time One Pulse functions + * + * @verbatim + ============================================================================== + ##### Time One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER One Pulse. + (+) Start the Time One Pulse. + (+) Stop the Time One Pulse. + (+) Start the Time One Pulse and enable interrupt. + (+) Stop the Time One Pulse and disable interrupt. + (+) Start the Time One Pulse and enable DMA transfer. + (+) Stop the Time One Pulse and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER One Pulse Time Base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @param mode: Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIMER_OP_MODE_SINGLE: Only one pulse will be generated. + * @arg TIMER_OP_MODE_REPEAT: Repetitive pulses wil be generated. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_OP_MODE(mode)); + + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = TIMER_STATE_BUSY; + timer_base_set_config(hperh->perh, &hperh->init); + MODIFY_REG(hperh->perh->CON1, TIMER_CON1_SPMEN_MSK, mode << TIMER_CON1_SPMEN_POS); + hperh->state = TIMER_STATE_READY; + + return OK; +} + +/** + * @brief Starts the TIMER One Pulse signal generation. + * @param hperh: TIMER One Pulse handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch) +{ + /* Enable the Capture compare and the Input Capture channels + * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) + * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and + * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output + * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together + */ + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER One Pulse signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch) +{ + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER One Pulse signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) +{ + /* Enable the Capture compare and the Input Capture channels + * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) + * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and + * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output + * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together + */ + timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER One Pulse signal generation in interrupt mode. + * @param hperh : TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) +{ + timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + return; +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group6 TIMER Encoder functions + * @brief TIMER Encoder functions + * + * @verbatim + ============================================================================== + ##### Time Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Encoder. + (+) Start the Time Encoder. + (+) Stop the Time Encoder. + (+) Start the Time Encoder and enable interrupt. + (+) Stop the Time Encoder and disable interrupt. + (+) Start the Time Encoder and enable DMA transfer. + (+) Stop the Time Encoder and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Encoder Interface and create the associated handle. + * @param hperh: TIMER handle + * @param config: TIMER Encoder Interface configuration structure + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_ENCODER_MODE(config->mode)); + assert_param(IS_TIMER_IC_POLARITY(config->ic1_polarity)); + assert_param(IS_TIMER_IC_POLARITY(config->ic2_polarity)); + assert_param(IS_TIMER_IC_SELECT(config->ic1_sel)); + assert_param(IS_TIMER_IC_SELECT(config->ic2_sel)); + assert_param(IS_TIMER_IC_PSC(config->ic1_psc)); + assert_param(IS_TIMER_IC_PSC(config->ic2_psc)); + assert_param(IS_TIMER_IC_FILTER(config->ic1_filter)); + assert_param(IS_TIMER_IC_FILTER(config->ic2_filter)); + + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = TIMER_STATE_BUSY; + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + timer_base_set_config(hperh->perh, &hperh->init); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, config->ic1_sel << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, config->ic2_sel << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->ic1_psc << TIMER_CHMR1_IC1PRES_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->ic2_psc << TIMER_CHMR1_IC2PRES_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->ic1_filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I2FLT_MSK, config->ic2_filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, (config->ic1_polarity & 0x1) << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((config->ic1_polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, (config->ic2_polarity & 0x1) << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((config->ic2_polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); + + hperh->state = TIMER_STATE_READY; + return OK; +} + +/** + * @brief Starts the TIMER Encoder Interface. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + break; + } + + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Encoder Interface. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + break; + } + + TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER Encoder Interface in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + } + + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Encoder Interface in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + } + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER Encoder Interface in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @param hdma1: Pointer to dma_handle_t. + * @param hdma2: Pointer to dma_handle_t. + * @param buf1: The destination Buffer address. Reading data from CCR1. + * @param buf2: The destination Buffer address. Reading data from CCR2. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch1: Channel of DMA. + * @param dma_ch2: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, + uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) + { + if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0)) + return ERROR; + } + + if (hdma1->perh == NULL) + hdma1->perh = DMA0; + if (hdma2->perh == NULL) + hdma2->perh = DMA0; + + hperh->state = TIMER_STATE_BUSY; + hdma1->cplt_cbk = timer_dma_capture_cplt; + hdma1->cplt_arg = (void *)hperh; + hdma1->err_cbk = timer_dma_error; + hdma1->err_arg = (void *)hperh; + + dma_config_struct(&hdma1->config); + hdma1->config.size = len; + hdma1->config.data_width = DMA_DATA_SIZE_HALFWORD; + hdma1->config.src_inc = DMA_DATA_INC_NONE; + hdma1->config.dst_inc = DMA_DATA_INC_HALFWORD; + + if (hperh->perh == TIMER0) + hdma1->config.msel = DMA_MSEL_TIMER0; + else if (hperh->perh == TIMER1) + hdma1->config.msel = DMA_MSEL_TIMER1; + else if (hperh->perh == TIMER2) + hdma1->config.msel = DMA_MSEL_TIMER2; + else if (hperh->perh == TIMER3) + hdma1->config.msel = DMA_MSEL_TIMER3; + else if (hperh->perh == TIMER4) + hdma1->config.msel = DMA_MSEL_TIMER4; + else if (hperh->perh == TIMER5) + hdma1->config.msel = DMA_MSEL_TIMER5; + else if (hperh->perh == TIMER6) + hdma1->config.msel = DMA_MSEL_TIMER6; + else if (hperh->perh == TIMER7) + hdma1->config.msel = DMA_MSEL_TIMER7; + else + ;/* do nothing */ + + switch (ch) + { + case TIMER_CHANNEL_1: + hdma1->config.src = (void *)&hperh->perh->CCVAL1; + hdma1->config.dst = (void *)buf1; + hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hdma1->config.channel = dma_ch1; + dma_config_basic(hdma1); + timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + break; + + case TIMER_CHANNEL_2: + hdma1->config.src = (void *)&hperh->perh->CCVAL2; + hdma1->config.dst = (void *)buf2; + hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hdma1->config.channel = dma_ch2; + dma_config_basic(hdma1); + timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + TIMER_ENABLE(hperh); + break; + + default: + hdma2->cplt_cbk = timer_dma_capture_cplt; + hdma2->cplt_arg = (void *)hperh; + hdma2->err_cbk = timer_dma_error; + hdma2->err_arg = (void *)hperh; + memcpy(&hdma2->config, &hdma1->config, sizeof(dma_config_t)); + + hdma1->config.src = (void *)&hperh->perh->CCVAL1; + hdma1->config.dst = (void *)buf1; + hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hdma1->config.channel = dma_ch1; + dma_config_basic(hdma1); + timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + + hdma2->config.src = (void *)&hperh->perh->CCVAL2; + hdma2->config.dst = (void *)buf2; + hdma2->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hdma2->config.channel = dma_ch2; + dma_config_basic(hdma2); + timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + TIMER_ENABLE(hperh); + break; + } + + return OK; +} + +/** + * @brief Stops the TIMER Encoder Interface in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + } + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group7 TIMER Hall Sensor functions + * @brief TIMER Hall Sensor functions + * + * @verbatim + ============================================================================== + ##### Time Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER hall sensor. + (+) Start the hall sensor. + (+) Stop the hall sensor. + (+) Start the hall sensor and enable interrupt. + (+) Stop the hall sensor and disable interrupt. + (+) Start the hall sensor and enable DMA transfer. + (+) Stop the hal sensor and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Encoder Interface and create the associated handle. + * @param hperh: TIMER handle + * @param config: TIMER Encoder Interface configuration structure + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config) +{ + timer_oc_init_t oc; + + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = TIMER_STATE_READY; + timer_base_set_config(hperh->perh, &hperh->init); + timer_ti1_set_config(hperh->perh, config->polarity, TIMER_IC_SEL_TRC, config->filter); + + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + SET_BIT(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + + oc.oc_mode = TIMER_OC_MODE_PWM2; + oc.pulse = config->delay; + oc.oc_polarity = TIMER_OC_POLARITY_HIGH; + oc.ocn_polarity = TIMER_OCN_POLARITY_HIGH; + oc.oc_fast_en = DISABLE; + oc.oc_idle = TIMER_OC_IDLE_RESET; + oc.ocn_idle = TIMER_OCN_IDLE_RESET; + timer_oc2_set_config(hperh->perh, &oc); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_TRGO_OC2REF << TIMER_SMCON_SMODS_POSS); + return OK; +} +/** + * @brief Starts the TIMER hall sensor interface. + * @param hperh: TIMER handle + * @retval None + */ +void timer_hall_sensor_start(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER hall sensor interface. + * @param hperh: TIMER handle + * @retval None + */ +void timer_hall_sensor_stop(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER hall sensor interface in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void timer_hall_sensor_start_by_it(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER hall sensor interface in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void timer_hall_sensor_stop_by_it(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + TIMER_DISABLE(hperh); + + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER hall sensor interface in DMA mode. + * @param hperh: TIMER handle + * @param hdma: Pointer to dma_handle_t. + * @param buf: The destination Buffer address. Reading data from CCR1. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) + { + if (((uint32_t)buf == 0) || (len == 0)) + return ERROR; + } + + if (hdma->perh == NULL) + hdma->perh = DMA0; + + hperh->state = TIMER_STATE_BUSY; + hdma->cplt_cbk = timer_dma_capture_cplt; + hdma->cplt_arg = (void *)hperh; + hdma->err_cbk = timer_dma_error; + hdma->err_arg = (void *)hperh; + + dma_config_struct(&hdma->config); + hdma->config.size = len; + hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; + hdma->config.src_inc = DMA_DATA_INC_NONE; + hdma->config.dst_inc = DMA_DATA_INC_HALFWORD; + + if (hperh->perh == TIMER0) + hdma->config.msel = DMA_MSEL_TIMER0; + else if (hperh->perh == TIMER6) + hdma->config.msel = DMA_MSEL_TIMER6; + else + ;/* do nothing */ + + hdma->config.src = (void *)&hperh->perh->CCVAL1; + hdma->config.dst = (void *)buf; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hdma->config.channel = dma_ch; + dma_config_basic(hdma); + timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + + return OK; +} +/** + * @brief Stops the TIMER hall sensor interface in DMA mode. + * @param hperh: TIMER handle + * @retval None + */ +void timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + TIMER_DISABLE(hperh); + + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group8 TIMER complementary output compare functions + * @brief TIMER complementary output compare functions + * + * @verbatim + ============================================================================== + ##### Time complementary output compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary output compare. + (+) Stop the Time complementary output compare. + (+) Start the Time complementary output compare and enable interrupt. + (+) Stop the Time complementary output compare and disable interrupt. + (+) Start the Time complementary output compare and enable DMA transfer. + (+) Stop the Time complementary output compare and disable DMA transfer. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER output compare signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + + case TIMER_CHANNEL_2: + timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + + case TIMER_CHANNEL_3: + timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + default: + break; + } + + timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE); + timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER output compare signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + default: + break; + } + + if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NEN_MSK))) + && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NEN_MSK))) + && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NEN_MSK)))) + { + timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE); + } + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); + + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @param hdma: Pointer to dma_handle_t. + * @param buf: The destination Buffer address. Reading data from CCRx. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval None + */ +ald_status_t timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) + { + if (((uint32_t)buf == 0) || (len == 0)) + return ERROR; + } + + hperh->state = TIMER_STATE_BUSY; + + if (hdma->perh == NULL) + hdma->perh = DMA0; + + hdma->cplt_cbk = timer_dma_oc_cplt; + hdma->cplt_arg = (void *)hperh; + hdma->err_cbk = timer_dma_error; + hdma->err_arg = (void *)hperh; + + dma_config_struct(&hdma->config); + hdma->config.src = (void *)buf; + hdma->config.size = len; + hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; + hdma->config.src_inc = DMA_DATA_INC_HALFWORD; + hdma->config.dst_inc = DMA_DATA_INC_NONE; + hdma->config.channel = dma_ch; + hdma->config.msel = DMA_MSEL_TIMER0; + + switch (ch) + { + case TIMER_CHANNEL_1: + hdma->config.dst = (void *)&hperh->perh->CCVAL1; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + dma_config_basic(hdma); + timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hdma->config.dst = (void *)&hperh->perh->CCVAL2; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + dma_config_basic(hdma); + timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hdma->config.dst = (void *)&hperh->perh->CCVAL3; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; + dma_config_basic(hdma); + timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); + + return OK; +} + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + default: + break; + } + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); + + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group9 TIMER complementary PWM functions + * @brief TIMER complementary PWM functions + * + * @verbatim + ============================================================================== + ##### Time complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary PWM. + (+) Stop the Time complementary PWM. + (+) Start the Time complementary PWM and enable interrupt. + (+) Stop the Time complementary PWM and disable interrupt. + (+) Start the Time complementary PWM and enable DMA transfer. + (+) Stop the Time complementary PWM and disable DMA transfer. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch) +{ + timer_ocn_start(hperh, ch); +} + +/** + * @brief Stops the TIMER PWM signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + timer_ocn_stop(hperh, ch); +} + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + timer_ocn_start_by_it(hperh, ch); +} + +/** + * @brief Stops the TIMER PWM signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + timer_ocn_stop_by_it(hperh, ch); +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @param hdma: Pointer to dma_handle_t. + * @param buf: The destination Buffer address. Reading data from CCRx. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval None + */ +ald_status_t timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + return timer_ocn_start_by_dma(hperh, hdma, ch, buf, len, dma_ch); +} + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + timer_ocn_stop_by_dma(hperh, ch); +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group10 TIMER complementary one pulse functions + * @brief TIMER complementary one pulse functions + * + * @verbatim + ============================================================================== + ##### Time complementary one pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary one pulse. + (+) Stop the Time complementary one pulse. + (+) Start the Time complementary one pulse and enable interrupt. + (+) Stop the Time complementary one pulse and disable interrupt. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER one pulse signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch) +{ + timer_ocn_start(hperh, ch); +} + +/** + * @brief Stops the TIMER one pulse signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + timer_ocn_stop(hperh, ch); +} + +/** + * @brief Starts the TIMER one pulse signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + timer_ocn_start_by_it(hperh, ch); +} + +/** + * @brief Stops the TIMER one pulse signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + timer_ocn_stop_by_it(hperh, ch); +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group11 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead timere. + (+) Configure Master and the Slave synchronization. + (+) Handle TIMER interrupt. + (+) Get TIMER compare register's vale. + (+) Configure TIMER interrupt ENABLE/DISABLE. + (+) Get TIMER interrupt source status. + (+) Get TIMER interrupt flag status. + (+) Clear TIMER interrupt flag. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Output Compare Channels according to the specified + * parameters in the timer_oc_init_t. + * @param hperh: TIMER handle + * @param config: TIMER Output Compare configuration structure + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_OC_MODE(config->oc_mode)); + assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, config); + break; + + case TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, config); + break; + + case TIMER_CHANNEL_3: + timer_oc3_set_config(hperh->perh, config); + break; + + case TIMER_CHANNEL_4: + timer_oc4_set_config(hperh->perh, config); + break; + + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Initializes the TIMER Input Capture Channels according to the specified + * parameters in the timer_ic_init_t. + * @param hperh: TIMER handle + * @param config: TIMER Input Capture configuration structure + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_SELECT(config->sel)); + assert_param(IS_TIMER_IC_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + switch (ch) + { + case TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + break; + + case TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS); + break; + + case TIMER_CHANNEL_3: + timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS); + break; + + case TIMER_CHANNEL_4: + timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS); + break; + + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Initializes the TIMER One Pulse Channels according to the specified + * parameters in the timer_one_pulse_init_t. + * @param hperh: TIMER handle + * @param config: TIMER One Pulse configuration structure + * @param ch_out: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @param ch_in: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, + timer_channel_t ch_out, timer_channel_t ch_in) +{ + timer_oc_init_t tmp; + + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_OC_MODE(config->mode)); + assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); + assert_param(IS_TIMER_OCN_POLARITY(config->ocn_polarity)); + assert_param(IS_TIMER_OCIDLE_STATE(config->oc_idle)); + assert_param(IS_TIMER_OCNIDLE_STATE(config->ocn_idle)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_SELECT(config->sel)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (ch_out == ch_in) + return ERROR; + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + tmp.oc_mode = config->mode; + tmp.pulse = config->pulse; + tmp.oc_polarity = config->oc_polarity; + tmp.ocn_polarity = config->ocn_polarity; + tmp.oc_idle = config->oc_idle; + tmp.ocn_idle = config->ocn_idle; + + switch (ch_out) + { + case TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, &tmp); + break; + case TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, &tmp); + break; + default: + break; + } + + switch (ch_in) + { + case TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param hperh: TIMER handle + * @param config: pointer to a TIMER_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIMER peripheral. + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @arg TIMER_CHANNEL_4: TIMER Channel 4 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->state)); + assert_param(IS_TIMER_CLEAR_INPUT_SOURCE(config->source)); + assert_param(IS_TIMER_CLEAR_INPUT_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (config->source == TIMER_INPUT_NONE) + { + timer_etr_set_config(hperh->perh, TIMER_ETR_PSC_DIV1, TIMER_CLK_POLARITY_NO_INV, 0); + } + else + { + timer_etr_set_config(hperh->perh, config->psc, + (timer_clock_polarity_t)config->polarity, config->filter); + } + + switch (ch) + { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS); + break; + + case TIMER_CHANNEL_3: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS); + break; + + case TIMER_CHANNEL_4: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS); + break; + + default: + break; + } + + return OK; +} + +/** + * @brief Configures the clock source to be used + * @param hperh: TIMER handle + * @param config: pointer to a timer_clock_config_t structure that + * contains the clock source information for the TIMER peripheral. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_CLOCK_SOURCE(config->source)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + WRITE_REG(hperh->perh->SMCON, 0x0); + + switch (config->source) + { + case TIMER_SRC_INTER: + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + break; + + case TIMER_SRC_ETRMODE1: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ETRMODE2: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK); + break; + + case TIMER_SRC_TI1: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_TI2: + timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_TI1ED: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR0: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR1: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR2: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR3: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param hperh: TIMER handle. + * @param ti1_select: Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg 0: The TIMERx_CH1 pin is connected to TI1 input + * @arg 1: The TIMERx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK, ti1_select << TIMER_CON2_I1FSEL_POS); + return OK; +} + +/** + * @brief Configures the TIMER in Slave mode + * @param hperh: TIMER handle. + * @param config: pointer to a timer_slave_config_t structure that + * contains the selected trigger (internal trigger input, filtered + * timerer input or external trigger input) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_SLAVE_MODE(config->mode)); + assert_param(IS_TIMER_TS(config->input)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + timer_slave_set_config(hperh, config); + timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE); + timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Configures the TIMER in Slave mode in interrupt mode + * @param hperh: TIMER handle. + * @param config: pointer to a timer_slave_config_t structure that + * contains the selected trigger (internal trigger input, filtered + * timerer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_SLAVE_MODE(config->mode)); + assert_param(IS_TIMER_TS(config->input)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + timer_slave_set_config(hperh, config); + timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE); + timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Generate a software event + * @param hperh: TIMER handle + * @param event: specifies the event source. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t timer_generate_event(timer_handle_t *hperh, timer_event_source_t event) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_EVENT_SOURCE(event)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + WRITE_REG(hperh->perh->SGE, event); + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param hperh: TIMER handle. + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1 : TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2 : TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3 : TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected + * @retval Captured value + */ +uint32_t timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) +{ + uint32_t tmp; + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + switch (ch) + { + case TIMER_CHANNEL_1: + tmp = hperh->perh->CCVAL1; + break; + case TIMER_CHANNEL_2: + tmp = hperh->perh->CCVAL2; + break; + case TIMER_CHANNEL_3: + tmp = hperh->perh->CCVAL3; + break; + case TIMER_CHANNEL_4: + tmp = hperh->perh->CCVAL4; + break; + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return tmp; +} + +/** + * @brief Sets TIMER output mode. + * @param hperh: TIMER handle. + * @param mode: TIMER output mode. + * @param ch: TIMER Channels. + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1 : TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2 : TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3 : TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected + * @retval None + */ +void timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_OC_MODE(mode)); + assert_param(IS_TIMER_CHANNELS(ch)); + + switch (ch) + { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS); + break; + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS); + break; + case TIMER_CHANNEL_3: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS); + break; + case TIMER_CHANNEL_4: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS); + break; + default: + break; + } + + return; +} + +/** + * @brief Configure the channel in commutation event. + * @param hperh: TIMER handel + * @param config: Parameters of the channel. + * @retval None + */ +void timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config) +{ + uint32_t cm1, cm2, cce; + + assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->ch[0].en)); + assert_param(IS_FUNC_STATE(config->ch[0].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[0].mode)); + assert_param(IS_FUNC_STATE(config->ch[1].en)); + assert_param(IS_FUNC_STATE(config->ch[1].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[1].mode)); + assert_param(IS_FUNC_STATE(config->ch[2].en)); + assert_param(IS_FUNC_STATE(config->ch[2].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[2].mode)); + + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); + + cm1 = hperh->perh->CHMR1; + cm2 = hperh->perh->CHMR2; + cce = hperh->perh->CCEP; + + MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4)); + MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12)); + MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4)); + MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0)); + MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2)); + MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4)); + MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6)); + MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8)); + MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10)); + + WRITE_REG(hperh->perh->CHMR1, cm1); + WRITE_REG(hperh->perh->CHMR2, cm2); + WRITE_REG(hperh->perh->CCEP, cce); + + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Configure the TIMER commutation event sequence. + * @param hperh: TIMER handel + * @param ts: the internal trigger corresponding to the timerer interfacing + * with the hall sensor. + * This parameter can be one of the following values: + * @arg TIMER_TS_ITR0 + * @arg TIMER_TS_ITR1 + * @arg TIMER_TS_ITR2 + * @arg TIMER_TS_ITR3 + * @param trgi: the commutation event source. + * This parameter can be one of the following values: + * @arg ENABLE: Commutation event source is TRGI + * @arg DISABLE: Commutation event source is set by software using the COMG bit + * @retval None + */ +void timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) +{ + assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_TS(ts)); + assert_param(IS_FUNC_STATE(trgi)); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ts << TIMER_SMCON_TSSEL_POSS); + SET_BIT(hperh->perh->CON2, TIMER_CON2_CCPCEN_MSK); + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_CCUSEL_MSK, trgi << TIMER_CON2_CCUSEL_POS); + + return; +} + +/** + * @brief Configure the TIMER commutation event sequence with interrupt. + * @param hperh: TIMER handel + * @param ts: the internal trigger corresponding to the timerer interfacing + * with the hall sensor. + * This parameter can be one of the following values: + * @arg TIMER_TS_ITR0 + * @arg TIMER_TS_ITR1 + * @arg TIMER_TS_ITR2 + * @arg TIMER_TS_ITR3 + * @param trgi: the commutation event source. + * This parameter can be one of the following values: + * @arg ENABLE: Commutation event source is TRGI + * @arg DISABLE: Commutation event source is set by software using the COMG bit + * @retval None + */ +void timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) +{ + timer_com_event_config(hperh, ts, trgi); + timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE); +} + +/** + * @brief Configure the break, dead timere, lock level state. + * @param hperh: TIMER handle + * @param config: Pointer to the timer_break_dead_timere_t structure. + * @retval None + */ +void timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config) +{ + uint32_t tmp; + + assert_param(IS_TIMER_BREAK_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->off_run)); + assert_param(IS_FUNC_STATE(config->off_idle)); + assert_param(IS_TIMER_CLOCK_LEVEL(config->lock_level)); + assert_param(IS_TIMER_DEAD_TIMERE(config->dead_time)); + assert_param(IS_FUNC_STATE(config->break_state)); + assert_param(IS_TIMER_BREAK_POLARITY(config->polarity)); + assert_param(IS_FUNC_STATE(config->auto_out)); + + tmp = READ_REG(hperh->perh->BDCFG); + MODIFY_REG(tmp, TIMER_BDCFG_OFFSSR_MSK, config->off_run << TIMER_BDCFG_OFFSSR_POS); + MODIFY_REG(tmp, TIMER_BDCFG_OFFSSI_MSK, config->off_idle << TIMER_BDCFG_OFFSSI_POS); + MODIFY_REG(tmp, TIMER_BDCFG_LOCKLVL_MSK, config->lock_level << TIMER_BDCFG_LOCKLVL_POSS); + MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS); + MODIFY_REG(tmp, TIMER_BDCFG_BRKEN_MSK, config->break_state << TIMER_BDCFG_BRKEN_POS); + MODIFY_REG(tmp, TIMER_BDCFG_BRKP_MSK, config->polarity << TIMER_BDCFG_BRKP_POS); + MODIFY_REG(tmp, TIMER_BDCFG_AOEN_MSK, config->auto_out << TIMER_BDCFG_AOEN_POS); + WRITE_REG(hperh->perh->BDCFG, tmp); + + hperh->state = TIMER_STATE_READY; + return; +} + +/** + * @brief Configure the master mode + * @param hperh: TIMER handle + * @param config: Pointer to the timer_master_config_t structure. + * @retval None + */ +void timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel)); + assert_param(IS_FUNC_STATE(config->master_en)); + + hperh->state = TIMER_STATE_BUSY; + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_TRGOSEL_MSK, config->sel << TIMER_CON2_TRGOSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_MSCFG_MSK, config->master_en << TIMER_SMCON_MSCFG_POS); + hperh->state = TIMER_STATE_READY; + + return; +} + +/** + * @brief This function handles TIMER interrupts requests. + * @param hperh: TIMER handle + * @retval None + */ +void timer_irq_handle(timer_handle_t *hperh) +{ + uint32_t reg = hperh->perh->IFM; + + /* Capture or compare 1 event */ + if (READ_BIT(reg, TIMER_FLAG_CC1)) + { + timer_clear_flag_status(hperh, TIMER_FLAG_CC1); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK)) + { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else /* Output compare event */ + { + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 2 event */ + if (READ_BIT(reg, TIMER_FLAG_CC2)) + { + timer_clear_flag_status(hperh, TIMER_FLAG_CC2); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK)) + { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else /* Output compare event */ + { + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 3 event */ + if (READ_BIT(reg, TIMER_FLAG_CC3)) + { + timer_clear_flag_status(hperh, TIMER_FLAG_CC3); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC3SSEL_MSK)) + { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else /* Output compare event */ + { + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 4 event */ + if (READ_BIT(reg, TIMER_FLAG_CC4)) + { + timer_clear_flag_status(hperh, TIMER_FLAG_CC4); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC4SSEL_MSK)) + { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else /* Output compare event */ + { + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + + /* TIMER Update event */ + if (READ_BIT(reg, TIMER_FLAG_UPDATE)) + { + timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE); + + if (hperh->period_elapse_cbk) + hperh->period_elapse_cbk(hperh); + } + + /* TIMER Break input event */ + if (READ_BIT(reg, TIMER_FLAG_BREAK)) + { + timer_clear_flag_status(hperh, TIMER_FLAG_BREAK); + + if (hperh->break_cbk) + hperh->break_cbk(hperh); + } + + /* TIMER Trigger detection event */ + if (READ_BIT(reg, TIMER_FLAG_TRIGGER)) + { + timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER); + + if (hperh->trigger_cbk) + hperh->trigger_cbk(hperh); + } + + /* TIMER commutation event */ + if (READ_BIT(reg, TIMER_FLAG_COM)) + { + timer_clear_flag_status(hperh, TIMER_FLAG_COM); + + if (hperh->com_cbk) + hperh->com_cbk(hperh); + } + + return; +} + +/** + * @brief Configure DMA request source. + * @param hperh: TIMER handle + * @param req: DMA request source. + * @param state: New state of the specified DMA request. + * @retval None + */ +void timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->DIER, req); + else + CLEAR_BIT(hperh->perh->DIER, req); + + return; +} + +/** + * @brief Enable/disable the specified TIMER interrupts. + * @param hperh: Pointer to a timer_handle_t structure. + * @param it: Specifies the timer interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref timer_it_t. + * @param state: New state of the specified TIMER interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->DIER, it); + else + CLEAR_BIT(hperh->perh->DIER, it); + + return; +} + +/** + * @brief Get the status of TIMER interrupt source. + * @param hperh: Pointer to a timer_handle_t structure. + * @param it: Specifies the TIMER interrupt source. + * This parameter can be one of the @ref timer_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t timer_get_it_status(timer_handle_t *hperh, timer_it_t it) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IT(it)); + + if (hperh->perh->DIVS & it) + return SET; + + return RESET; +} + +/** + * @brief Get the status of TIMER interrupt flag. + * @param hperh: Pointer to a timer_handle_t structure. + * @param flag: Specifies the TIMER interrupt flag. + * This parameter can be one of the @ref timer_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_FLAG(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the TIMER interrupt flag. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the TIMER interrupt flag. + * This parameter can be one of the @ref timer_flag_t. + * @retval None + */ +void timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_FLAG(flag)); + + hperh->perh->ICR = flag; + return; +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group12 Peripheral State functions + * @brief Peripheral State functions + * + * @verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permit to get in run-timere the status of the peripheral + and the data flow. + + @endverbatim + * @{ + */ + +/** + * @brief Return the TIMER Base state + * @param hperh: TIMER handle + * @retval TIMER peripheral state + */ +timer_state_t timer_get_state(timer_handle_t *hperh) +{ + return hperh->state; +} +/** + * @} + */ +/** + * @} + */ + +/** @addtogroup TIMER_Private_Functions + * @{ + */ + +#ifdef ALD_DMA +/** + * @brief TIMER DMA out compare complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_oc_cplt(void *arg) +{ + timer_handle_t *hperh = (timer_handle_t *)arg; + + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + return; +} + +/** + * @brief TIMER DMA Capture complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_capture_cplt(void *arg) +{ + timer_handle_t *hperh = (timer_handle_t *)arg; + + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + return; +} + +/** + * @brief TIMER DMA Period Elapse complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_period_elapse_cplt(void *arg) +{ + timer_handle_t *hperh = (timer_handle_t *)arg; + + if (hperh->period_elapse_cbk) + hperh->period_elapse_cbk(hperh); + + hperh->state = TIMER_STATE_READY; + return; +} + +/** + * @brief TIMER DMA error callback + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_error(void *arg) +{ + timer_handle_t *hperh = (timer_handle_t *)arg; + + hperh->state = TIMER_STATE_READY; + if (hperh->error_cbk) + hperh->error_cbk(hperh); + + return; +} +#endif + +/** + * @brief Time Base configuration + * @param TIMERx: TIMER periheral + * @param init: TIMER Base configuration structure + * @retval None + */ +static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init) +{ + assert_param(IS_TIMER_COUNTER_MODE(init->mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(init->clk_div)); + + if (init->mode == TIMER_CNT_MODE_UP || init->mode == TIMER_CNT_MODE_DOWN) + { + CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CMSEL_MSK); + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, init->mode << TIMER_CON1_DIRSEL_POS); + } + else + { + MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, (init->mode - 1) << TIMER_CON1_CMSEL_POSS); + } + + if (IS_TIMER_CLOCK_DIVISION_INSTANCE(TIMERx)) + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, init->clk_div << TIMER_CON1_DFCKSEL_POSS); + + WRITE_REG(TIMERx->AR, init->period); + WRITE_REG(TIMERx->PRES, init->prescaler); + + if (IS_TIMER_REPETITION_COUNTER_INSTANCE(TIMERx)) + WRITE_REG(TIMERx->REPAR, init->re_cnt); + + return; +} + +/** + * @brief Time Ouput Compare 1 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH1OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC1POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_1)) + { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC1NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) + { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1_MSK, oc_config->oc_idle << TIMER_CON2_OISS1_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS1N_POS); + } + + WRITE_REG(TIMERx->CCVAL1, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 2 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH2OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC2POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_2)) + { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC2NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) + { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2_MSK, oc_config->oc_idle << TIMER_CON2_OISS2_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS2N_POS); + } + + WRITE_REG(TIMERx->CCVAL2, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 3 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH3OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC3POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_3)) + { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC3NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) + { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3_MSK, oc_config->oc_idle << TIMER_CON2_OISS3_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS3N_POS); + } + + WRITE_REG(TIMERx->CCVAL3, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 4 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH4OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC4POL_POS); + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) + { + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS4_MSK, oc_config->oc_idle << TIMER_CON2_OISS4_POS); + } + + WRITE_REG(TIMERx->CCVAL4, oc_config->pulse); +} + +/** + * @brief Enables or disables the TIMER Capture Compare Channel x. + * @param TIMERx: Select the TIMER peripheral + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @arg TIMER_CHANNEL_4: TIMER Channel 4 + * @param state: specifies the TIMER Channel CCxE bit new state. + * @retval None + */ +static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state) +{ + assert_param(IS_TIMER_CC2_INSTANCE(TIMERx)); + assert_param(IS_TIMER_CHANNELS(ch)); + + switch (ch) + { + case TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS); + break; + + case TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS); + break; + + case TIMER_CHANNEL_4: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS); + break; + + default: + break; + } +} +/** + * @brief Enables or disables the TIMER Capture Compare Channel xN. + * @param TIMERx: Select the TIMER peripheral + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @param state: specifies the TIMER Channel CCxNE bit new state. + * @retval None + */ +static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state) +{ + switch (ch) + { + case TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS); + break; + + case TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS); + break; + + default: + break; + } + +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); + + return; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); + + return; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); + + return; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); + return; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC3POL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC3NPOL_POS); + + return; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC4POL_POS); + + return; +} + +/** + * @brief Configures the TIMERx External Trigger (ETR). + * @param TIMERx: Select the TIMER peripheral + * @param psc: The external Trigger Prescaler. + * @param polarity: The external Trigger Polarity. + * @param filter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +static void timer_etr_set_config(TIMER_TypeDef *TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETFLT_MSK, filter << TIMER_SMCON_ETFLT_POSS); + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, psc << TIMER_SMCON_ETPSEL_POSS); + CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK); + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, polarity << TIMER_SMCON_ETPOL_POS); + return; +} + +/** + * @brief Time Slave configuration + * @param hperh: pointer to a timer_handle_t structure that contains + * the configuration information for TIMER module. + * @param config: The slave configuration structure + * @retval None + */ +static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config) +{ + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, config->input << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); + + switch (config->input) + { + case TIMER_TS_ETRF: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + break; + + case TIMER_TS_TI1F_ED: + CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS); + break; + + case TIMER_TS_TI1FP1: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + break; + + case TIMER_TS_TI2FP2: + timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + break; + + default: + break; + } +} +/** + * @} + */ +#endif /* ALD_TIMER */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c new file mode 100644 index 0000000000..5a682f9195 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c @@ -0,0 +1,222 @@ +/** + ********************************************************************************* + * + * @file ald_trng.c + * @brief TRNG module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_trng.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup TRNG TRNG + * @brief TRNG module driver + * @{ + */ +#ifdef ALD_TRNG + +/** @defgroup TRNG_Public_Functions TRNG Public Functions + * @{ + */ + +/** @addtogroup TRNG_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @verbatim + ============================================================================== + ##### Initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to initialize the TRNG: + (+) This parameters can be configured: + (++) Word Width + (++) Seed Type + (++) Seed + (++) Start Time + (++) Adjust parameter + + @endverbatim + * @{ + */ + + +/** + * @brief Initializes the TRNG according to the specified + * parameters in the trng_init_t. + * @param init: Pointer to a trng_init_t structure that contains + * the configuration information. + * @retval None + */ +void trng_init(trng_init_t *init) +{ + assert_param(IS_TRNG_DATA_WIDTH(init->data_width)); + assert_param(IS_TRNG_SEED_TYPE(init->seed_type)); + assert_param(IS_TRNG_ADJC(init->adjc)); + + SET_BIT(TRNG->CR, TRNG_CR_TRNGSEL_MSK); + MODIFY_REG(TRNG->CR, TRNG_CR_DSEL_MSK, (init->data_width) << TRNG_CR_DSEL_POSS); + MODIFY_REG(TRNG->CR, TRNG_CR_SDSEL_MSK, (init->seed_type) << TRNG_CR_SDSEL_POSS); + MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (init->adjc) << TRNG_CR_ADJC_POSS); + + if (init->adjc == 0) + { + MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (0) << TRNG_CR_ADJC_POSS); + } + else + { + MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (1) << TRNG_CR_ADJC_POSS); + } + + WRITE_REG(TRNG->SEED, init->seed); + MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (init->t_start) << TRNG_CFGR_TSTART_POSS); + MODIFY_REG(TRNG->CR, TRNG_CR_POSTEN_MSK, (init->posten) << TRNG_CR_POSTEN_MSK); + + return; +} +/** + * @} + */ + +/** @addtogroup TRNG_Public_Functions_Group2 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) trng_get_result() API can Get the result. + (+) trng_interrupt_config() API can be helpful to configure TRNG interrupt source. + (+) trng_get_it_status() API can get the status of interrupt source. + (+) trng_get_status() API can get the status of SR register. + (+) trng_get_flag_status() API can get the status of interrupt flag. + (+) trng_clear_flag_status() API can clear interrupt flag. + + @endverbatim + * @{ + */ + +/** + * @brief Get the result. + * @retval The resultl + */ +uint32_t trng_get_result(void) +{ + return (uint32_t)TRNG->DR; +} + +/** + * @brief Enable/disable the specified interrupts. + * @param it: Specifies the interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref trng_it_t. + * @param state: New state of the specified interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void trng_interrupt_config(trng_it_t it, type_func_t state) +{ + assert_param(IS_TRNG_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + SET_BIT(TRNG->IER, it); + else + CLEAR_BIT(TRNG->IER, it); + + return; +} + +/** + * @brief Get the status of SR register. + * @param status: Specifies the TRNG status type. + * This parameter can be one of the @ref trng_status_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t trng_get_status(trng_status_t status) +{ + assert_param(IS_TRNG_STATUS(status)); + + if (READ_BIT(TRNG->SR, status)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt source. + * @param it: Specifies the interrupt source. + * This parameter can be one of the @ref trng_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t trng_get_it_status(trng_it_t it) +{ + assert_param(IS_TRNG_IT(it)); + + if (READ_BIT(TRNG->IER, it)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt flag. + * @param flag: Specifies the interrupt flag. + * This parameter can be one of the @ref trng_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t trng_get_flag_status(trng_flag_t flag) +{ + assert_param(IS_TRNG_FLAG(flag)); + + if (READ_BIT(TRNG->IFR, flag)) + return SET; + + return RESET; +} + +/** + * @brief Clear the interrupt flag. + * @param flag: Specifies the interrupt flag. + * This parameter can be one of the @ref trng_flag_t. + * @retval None + */ +void trng_clear_flag_status(trng_flag_t flag) +{ + assert_param(IS_TRNG_FLAG(flag)); + WRITE_REG(TRNG->IFCR, flag); + + return; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_TRNG */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c new file mode 100644 index 0000000000..32cdbe143f --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c @@ -0,0 +1,1200 @@ +/** + ********************************************************************************* + * + * @file ald_uart.c + * @brief UART module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + * + Initialization and Configuration functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + * @version V1.0 + * @date 21 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The UART driver can be used as follows: + + (#) Declare a uart_handle_t handle structure. + + (#) Initialize the UART low level resources: + (##) Enable the UARTx interface clock. + (##) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input). + (##) NVIC configuration if you need to use interrupt process (uart_send_by_it() + and uart_recv_by_it() APIs): + (+++) Configure the uart interrupt priority. + (+++) Enable the NVIC UART IRQ handle. + (##) DMA Configuration if you need to use DMA process (uart_send_by_dma() + and uart_recv_by_dma() APIs): + (+++) Select the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the hperh Init structure. + + (#) Initialize the UART registers by calling the uart_init() API. + + [..] + Three operation modes are available within this driver: + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using uart_send() + (+) Receive an amount of data in blocking mode using uart_recv() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using uart_send_by_it() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode using uart_recv_by_it() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using uart_send_by_dma() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode (DMA) using uart_recv_by_dma() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + (+) Pause the DMA Transfer using uart_dma_pause() + (+) Resume the DMA Transfer using uart_dma_resume() + (+) Stop the DMA Transfer using uart_dma_stop() + + @endverbatim + ****************************************************************************** + */ + +#include "ald_uart.h" +#include "ald_cmu.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup UART UART + * @brief UART module driver + * @{ + */ +#ifdef ALD_UART + +/** @defgroup UART_Private_Functions UART Private Functions + * @brief UART Private functions + * @{ + */ +#ifdef ALD_DMA +/** + * @brief DMA uart transmit process complete callback. + * @param arg: Pointer to a uart_handle_t structure. + * @retval None + */ +static void uart_dma_send_cplt(void *arg) +{ + uart_handle_t *hperh = (uart_handle_t *)arg; + + if (hperh->state == UART_STATE_BUSY_TX) + uart_dma_req_config(hperh, DISABLE); + + hperh->tx_count = 0; + uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + return; +} + +/** + * @brief DMA uart receive process complete callback. + * @param arg: Pointer to a uart_handle_t structure. + * @retval None + */ +static void uart_dma_recv_cplt(void *arg) +{ + uart_handle_t *hperh = (uart_handle_t *)arg; + + if (hperh->state == UART_STATE_BUSY_RX) + uart_dma_req_config(hperh, DISABLE); + + hperh->rx_count = 0; + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + + return; +} + +/** + * @brief DMA uart communication error callback. + * @param arg: Pointer to a uart_handle_t structure. + * @retval None + */ +static void uart_dma_error(void *arg) +{ + uart_handle_t *hperh = (uart_handle_t *)arg; + + hperh->rx_count = 0; + hperh->tx_count = 0; + hperh->state = UART_STATE_READY; + hperh->err_code |= UART_ERROR_DMA; + uart_dma_req_config(hperh, DISABLE); + + if (hperh->error_cbk) + hperh->error_cbk(hperh); + + return; +} +#endif + +/** + * @brief This function handles uart Communication Timeout. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: specifies the uart flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick; + + if (timeout == 0) + return ERROR; + + tick = __get_tick(); + + /* Waiting for flag */ + while ((uart_get_status(hperh, flag)) != status) + { + if (((__get_tick()) - tick) > timeout) + return TIMEOUT; + } + + return OK; +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_send_by_it(uart_handle_t *hperh) +{ + if ((hperh->state & UART_STATE_TX_MASK) == 0x0) + return BUSY; + + WRITE_REG(hperh->perh->TBR, (uint8_t)(*hperh->tx_buf++ & 0x00FF)); + + if (--hperh->tx_count == 0) + { + uart_clear_flag_status(hperh, UART_IF_TC); + uart_interrupt_config(hperh, UART_IT_TXS, DISABLE); + uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + } + + return OK; +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hperh: pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh) +{ + if (!(READ_BIT(hperh->perh->SR, UART_SR_TEM_MSK))) + return OK; + + uart_interrupt_config(hperh, UART_IT_TC, DISABLE); + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) +{ + if ((hperh->state & UART_STATE_RX_MASK) == 0x0) + return BUSY; + + *hperh->rx_buf++ = (uint8_t)(hperh->perh->RBR & 0xFF); + + if (--hperh->rx_count == 0) + { + uart_interrupt_config(hperh, UART_IT_RXRD, DISABLE); + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return OK; +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions UART Public Functions + * @{ + */ + +/** @defgroup UART_Public_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * + * @verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the UARTx + and configure UARTx param. + (+) For the UARTx only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity + (++) Hardware flow control + (+) For RS485 mode, user also need configure some parameters by + uart_rs485_config(): + (++) Enable/disable normal point mode + (++) Enable/disable auto-direction + (++) Enable/disable address detection invert + (++) Enable/disable address for compare + + @endverbatim + * @{ + */ + +/** + * @brief Reset UART peripheral + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified uart module. + * @retval None + */ +void uart_reset(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + WRITE_REG(hperh->perh->BRR, 0x0); + WRITE_REG(hperh->perh->LCR, 0x0); + WRITE_REG(hperh->perh->MCR, 0x0); + WRITE_REG(hperh->perh->CR, 0x0); + WRITE_REG(hperh->perh->RTOR, 0x0); + WRITE_REG(hperh->perh->FCR, 0x0); + WRITE_REG(hperh->perh->IDR, 0xFFF); + + hperh->err_code = UART_ERROR_NONE; + hperh->state = UART_STATE_RESET; + + __UNLOCK(hperh); + return; +} + +/** + * @brief Initializes the UARTx according to the specified + * parameters in the uart_handle_t. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void uart_init(uart_handle_t *hperh) +{ + uint32_t tmp; + + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_BAUDRATE(hperh->init.baud)); + assert_param(IS_UART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_UART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_UART_PARITY(hperh->init.parity)); + assert_param(IS_UART_MODE(hperh->init.mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); + + uart_reset(hperh); + + tmp = READ_REG(hperh->perh->LCR); + MODIFY_REG(tmp, UART_LCR_DLS_MSK, hperh->init.word_length << UART_LCR_DLS_POSS); + MODIFY_REG(tmp, UART_LCR_STOP_MSK, hperh->init.stop_bits << UART_LCR_STOP_POS); + MODIFY_REG(tmp, UART_LCR_PEN_MSK, (hperh->init.parity == UART_PARITY_NONE ? 0 : 1) << UART_LCR_PEN_POS); + MODIFY_REG(tmp, UART_LCR_PS_MSK, (hperh->init.parity == UART_PARITY_EVEN ? 1 : 0) << UART_LCR_PS_POS); + WRITE_REG(hperh->perh->LCR, tmp); + MODIFY_REG(hperh->perh->MCR, UART_MCR_AFCEN_MSK, hperh->init.fctl << UART_MCR_AFCEN_POS); + SET_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); + WRITE_REG(hperh->perh->BRR, cmu_get_pclk1_clock() / hperh->init.baud); + CLEAR_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); + SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); + SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); + SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK); + MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, 0 << UART_FCR_RXTL_POSS); + MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, 0 << UART_FCR_TXTL_POSS); + SET_BIT(hperh->perh->LCR, UART_LCR_RXEN_MSK); + + if (hperh->init.mode == UART_MODE_LIN) + SET_BIT(hperh->perh->MCR, UART_MCR_LINEN_MSK); + else if (hperh->init.mode == UART_MODE_IrDA) + SET_BIT(hperh->perh->MCR, UART_MCR_IREN_MSK); + else if (hperh->init.mode == UART_MODE_RS485) + SET_BIT(hperh->perh->MCR, UART_MCR_AADEN_MSK); + else if (hperh->init.mode == UART_MODE_HDSEL) + SET_BIT(hperh->perh->MCR, UART_MCR_HDSEL_MSK); + else + ;/* do nothing */ + + if (hperh->init.fctl) + SET_BIT(hperh->perh->MCR, UART_MCR_RTSCTRL_MSK); + if (hperh->init.mode == UART_MODE_IrDA) + SET_BIT(hperh->perh->LCR, UART_LCR_RXINV_MSK); + + hperh->state = UART_STATE_READY; + hperh->err_code = UART_ERROR_NONE; + return; +} + +/** + * @brief Configure the RS485 mode according to the specified + * parameters in the uart_rs485_config_t. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @param config: Specifies the RS485 parameters. + * @retval None + */ +void uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_FUNC_STATE(config->normal)); + assert_param(IS_FUNC_STATE(config->dir)); + assert_param(IS_FUNC_STATE(config->invert)); + + MODIFY_REG(hperh->perh->MCR, UART_MCR_AADNOR_MSK, config->normal << UART_MCR_AADNOR_POS); + MODIFY_REG(hperh->perh->MCR, UART_MCR_AADDIR_MSK, config->dir << UART_MCR_AADDIR_POS); + MODIFY_REG(hperh->perh->MCR, UART_MCR_AADINV_MSK, config->invert << UART_MCR_AADINV_POS); + MODIFY_REG(hperh->perh->CR, UART_CR_ADDR_MSK, config->addr << UART_CR_ADDR_POSS); + + return; +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group2 IO operation functions + * @brief UART Transmit and Receive functions + * @verbatim + ============================================================================== + # IO operation functions # + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the UART data transfers. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The Status of all data processing is returned by the same function + after finishing transfer. + (++) Non blocking mode: The communication is performed using Interrupts + or DMA, these APIs return the Status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks + will be executed respectively at the end of the transmit or receive process. + The hperh->error_cbk() user callback will be executed when + a communication error is detected. + + (#) Blocking mode APIs are: + (++) uart_send() + (++) uart_recv() + + (#) Non Blocking mode APIs with Interrupt are: + (++) uart_send_by_it() + (++) uart_recv_by_it() + (++) uart_irq_handle() + + (#) Non Blocking mode functions with DMA are: + (++) uart_send_by_dma() + (++) uart_recv_by_dma() + (++) uart_dma_pause() + (++) uart_dma_resume() + (++) uart_dma_stop() + + (#) A set of transfer complete callbacks are provided in non blocking mode: + (++) hperh->tx_cplt_cbk() + (++) hperh->rx_cplt_cbk() + (++) hperh->error_cbk() + + @endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + hperh->tx_size = size; + hperh->tx_count = size; + + while (hperh->tx_count-- > 0) + { + if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) + { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + WRITE_REG(hperh->perh->TBR, (*buf++ & 0xFF)); + } + + if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) + { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receives an amount of data in blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + hperh->rx_size = size; + hperh->rx_count = size; + + while (hperh->rx_count-- > 0) + { + if (uart_wait_flag(hperh, UART_STATUS_DR, SET, timeout) != OK) + { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + *buf++ = (uint8_t)(hperh->perh->RBR & 0xFF); + } + + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + __UNLOCK(hperh); + + if (((uart_get_status(hperh, UART_STATUS_TBEM)) == SET) + && ((uart_get_flag_status(hperh, UART_IF_TXS)) == RESET)) + { + WRITE_REG(hperh->perh->TBR, (*hperh->tx_buf++ & 0xFF)); + --hperh->tx_count; + } + + if (hperh->tx_count == 0) + { + uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + return OK; + } + + uart_interrupt_config(hperh, UART_IT_TXS, ENABLE); + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @retval Status, see @ref ald_status_t. + */ +ald_status_t uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + __UNLOCK(hperh); + + uart_interrupt_config(hperh, UART_IT_RXRD, ENABLE); + return OK; +} +#ifdef ALD_DMA +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as UART transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = uart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = uart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TBR; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART_TXEMPTY; + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.channel = channel; + + if (hperh->init.mode == UART_MODE_RS485) + { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + if (hperh->perh == UART0) + hperh->hdmatx.config.msel = DMA_MSEL_UART0; + else if (hperh->perh == UART1) + hperh->hdmatx.config.msel = DMA_MSEL_UART1; + else if (hperh->perh == UART2) + hperh->hdmatx.config.msel = DMA_MSEL_UART2; + else if (hperh->perh == UART3) + hperh->hdmatx.config.msel = DMA_MSEL_UART3; + else + ; /* do nothing */ + + dma_config_basic(&hperh->hdmatx); + + __UNLOCK(hperh); + uart_clear_flag_status(hperh, UART_IF_TC); + uart_dma_req_config(hperh, ENABLE); + + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param channel: DMA channel as UART receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = uart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = uart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RBR; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART_RNR; + hperh->hdmarx.config.burst = ENABLE; + hperh->hdmarx.config.channel = channel; + + if (hperh->init.mode == UART_MODE_RS485) + { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + if (hperh->perh == UART0) + hperh->hdmarx.config.msel = DMA_MSEL_UART0; + else if (hperh->perh == UART1) + hperh->hdmarx.config.msel = DMA_MSEL_UART1; + else if (hperh->perh == UART2) + hperh->hdmarx.config.msel = DMA_MSEL_UART2; + else if (hperh->perh == UART3) + hperh->hdmarx.config.msel = DMA_MSEL_UART3; + else + ; + + dma_config_basic(&hperh->hdmarx); + __UNLOCK(hperh); + uart_dma_req_config(hperh, ENABLE); + + return OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t uart_dma_pause(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + uart_dma_req_config(hperh, DISABLE); + return OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t uart_dma_resume(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + uart_dma_req_config(hperh, ENABLE); + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t uart_dma_stop(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + uart_dma_req_config(hperh, DISABLE); + hperh->state = UART_STATE_READY; + return OK; +} +#endif + +/** + * @brief This function handles UART interrupt request. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval None + */ +void uart_irq_handle(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + /* Handle parity error */ + if ((uart_get_status(hperh, UART_STATUS_PE)) != RESET) + hperh->err_code |= UART_ERROR_PE; + + /* Handle frame error */ + if ((uart_get_status(hperh, UART_STATUS_FE)) != RESET) + hperh->err_code |= UART_ERROR_FE; + + /* Handle overflow error */ + if ((uart_get_status(hperh, UART_STATUS_OE)) != RESET) + hperh->err_code |= UART_ERROR_ORE; + + /* Receive */ + if ((uart_get_mask_flag_status(hperh, UART_IF_RXRD)) != RESET) + { + uart_clear_flag_status(hperh, UART_IF_RXRD); + __uart_recv_by_it(hperh); + } + + /* Transmite */ + if ((uart_get_mask_flag_status(hperh, UART_IF_TXS)) != RESET) + { + uart_clear_flag_status(hperh, UART_IF_TXS); + __uart_send_by_it(hperh); + } + + /* End Transmite */ + if ((uart_get_mask_flag_status(hperh, UART_IF_TC)) != RESET) + { + uart_clear_flag_status(hperh, UART_IF_TC); + __uart_end_send_by_it(hperh); + } + + /* Handle error state */ + if (hperh->err_code != UART_ERROR_NONE) + { + hperh->state = UART_STATE_READY; + + if (hperh->error_cbk) + hperh->error_cbk(hperh); + } +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART: + (+) uart_interrupt_config() API can be helpful to configure UART interrupt source. + (+) uart_dma_req_config() API can be helpful to configure UART DMA request. + (+) uart_tx_fifo_config() API can be helpful to configure UART TX FIFO paramters. + (+) uart_rx_fifo_config() API can be helpful to configure UART RX FIFO paramters. + (+) uart_lin_send_break() API can send a frame of break in LIN mode. + (+) uart_lin_detect_break_len_config() API can be helpful to configure the length of break frame. + (+) uart_auto_baud_config() API can be helpful to configure detection data mode. + (+) uart_get_it_status() API can get the status of interrupt source. + (+) uart_get_status() API can get the status of UART_SR register. + (+) uart_get_flag_status() API can get the status of UART flag. + (+) uart_get_mask_flag_status() API can get status os flag and interrupt source. + (+) uart_clear_flag_status() API can clear UART flag. + + @endverbatim + * @{ + */ + +/** + * @brief Enable/disable the specified UART interrupts. + * @param hperh: Pointer to a uart_handle_t structure. + * @param it: Specifies the UART interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref uart_it_t. + * @param state: New state of the specified UART interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + WRITE_REG(hperh->perh->IER, it); + else + WRITE_REG(hperh->perh->IDR, it); + + return; +} + +/** + * @brief Configure UART DMA request. + * @param hperh: Pointer to a uart_handle_t structure. + * @param state: New state of the specified DMA request. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void uart_dma_req_config(uart_handle_t *hperh, type_func_t state) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->MCR, UART_MCR_DMAEN_MSK); + else + CLEAR_BIT(hperh->perh->MCR, UART_MCR_DMAEN_MSK); + + return; +} + +/** + * @brief Configure transmit fifo parameters. + * @param hperh: Pointer to a uart_handle_t structure. + * @param config: Transmit fifo trigger level. + * @param level: Transmit fifo level. + * @retval None + */ +void uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_TXFIFO_TYPE(config)); + + SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK); + MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, config << UART_FCR_TXTL_POSS); + MODIFY_REG(hperh->perh->FCR, UART_FCR_TXFL_MSK, level << UART_FCR_TXFL_POSS); + SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); + + return; +} + +/** + * @brief Configure receive fifo parameters. + * @param hperh: Pointer to a uart_handle_t structure. + * @param config: Receive fifo trigger level. + * @param level: Receive fifo level. + * @retval None + */ +void uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_RXFIFO_TYPE(config)); + + SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); + MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, config << UART_FCR_RXTL_POSS); + MODIFY_REG(hperh->perh->FCR, UART_FCR_RXFL_MSK, level << UART_FCR_RXFL_POSS); + SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); + + return; +} + +/** + * @brief request to send a frame of break. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval None + */ +void uart_lin_send_break(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + SET_BIT(hperh->perh->MCR, UART_MCR_BKREQ_MSK); + return; +} + +/** + * @brief Configure the length of break frame to be detect. + * @param hperh: Pointer to a uart_handle_t structure. + * @param len: Length of break frame. + * @arg LIN_BREAK_LEN_10B + * @arg LIN_BREAK_LEN_11B + * @retval None + */ +void uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_LIN_BREAK_LEN(len)); + + MODIFY_REG(hperh->perh->MCR, UART_MCR_LINBDL_MSK, len << UART_MCR_LINBDL_POS); + return; +} + +/** + * @brief Configure the mode of auto-baud-rate detect. + * @param hperh: Pointer to a uart_handle_t structure. + * @param mode: The mode of auto-baud-rate detect. + * @arg UART_ABRMOD_1_TO_0 + * @arg UART_ABRMOD_1 + * @arg UART_ABRMOD_0_TO_1 + * @retval None + */ +void uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_AUTO_BAUD_MODE(mode)); + + MODIFY_REG(hperh->perh->MCR, UART_MCR_ABRMOD_MSK, mode << UART_MCR_ABRMOD_POSS); + return; +} + +/** + * @brief Send address in RS485 mode. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @param addr: the address of RS485 device. + * @param timeout: Timeout duration + * @retval The ALD status. + */ +ald_status_t uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) + { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + WRITE_REG(hperh->perh->TBR, (addr | 0x100)); + + if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) + { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + + return OK; +} + +/** + * @brief Get the status of UART interrupt source. + * @param hperh: Pointer to a uart_handle_t structure. + * @param it: Specifies the UART interrupt source. + * This parameter can be one of the @ref uart_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t uart_get_it_status(uart_handle_t *hperh, uart_it_t it) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IT(it)); + + if (READ_BIT(hperh->perh->IVS, it)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of UART_SR register. + * @param hperh: Pointer to a uart_handle_t structure. + * @param status: Specifies the UART status type. + * This parameter can be one of the @ref uart_status_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t uart_get_status(uart_handle_t *hperh, uart_status_t status) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_STATUS(status)); + + if (READ_BIT(hperh->perh->SR, status)) + return SET; + + return RESET; +} + + +/** + * @brief Get the status of UART interrupt flag. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + if (READ_BIT(hperh->perh->RIF, flag)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt flag and interupt source. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + if (READ_BIT(hperh->perh->IFM, flag)) + return SET; + + return RESET; +} + +/** + * @brief Clear the UART interrupt flag. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval None + */ +void uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + WRITE_REG(hperh->perh->ICR, flag); + return; +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group4 Peripheral State and Errors functions + * @brief UART State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + UART communication process, return Peripheral Errors occurred during communication + process + (+) uart_get_state() API can be helpful to check in run-time the state of the UART peripheral. + (+) uart_get_error() check in run-time errors that could be occurred during communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the UART state. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval ALD state + */ +uart_state_t uart_get_state(uart_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the UART error code + * @param hperh: Pointer to a uart_handle_t structure. + * @retval UART Error Code + */ +uint32_t uart_get_error(uart_handle_t *hperh) +{ + return hperh->err_code; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* ALD_UART */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c new file mode 100644 index 0000000000..69641cb060 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c @@ -0,0 +1,2442 @@ +/** + ********************************************************************************* + * + * @file ald_usart.c + * @brief USART module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + * @version V1.0 + * @date 25 Apr 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The USART ALD driver can be used as follows: + + (#) Declare a usart_handle_t handle structure. + + (#) Initialize the USART handle: + (##) Enable the USARTx interface clock. + (##) USART pins configuration: + (+++) Enable the clock for the USART GPIOs. + (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). + (##) NVIC configuration if you need to use interrupt process (usart_send_by_it() + and usart_recv_by_it() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (##) DMA Configuration if you need to use DMA process (usart_send_by_dma() + and usart_recv_by_dma() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required + Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. + + (#) Program the baud rate, word length, stop bit, parity, hardware + flow control and mode(Receiver/Transmitter) in the hperh Init structure. + + (#) For the USART asynchronous mode, initialize the USART registers by calling + the usart_init() API. + + (#) For the USART Half duplex mode, initialize the USART registers by calling + the usart_half_duplex_init() API. + + (#) For the LIN mode, initialize the USART registers by calling the usart_lin_init() API. + + (#) For the Multi-Processor mode, initialize the USART registers by calling + the usart_multi_processor_init() API. + + [..] + (@) The specific USART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the function + usart_interrupt_config inside the transmit and receive process. + + [..] + Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] Asynchronous: + (+) Send an amount of data in blocking mode using usart_send() + (+) Receive an amount of data in blocking mode using usart_recv() + + [..] Synchronous: + (+) Send an amount of data in blocking mode using usart_send_sync() + (+) Receive an amount of data in blocking mode using usart_recv_sync() + + *** Interrupt mode IO operation *** + =================================== + [..] Asynchronous: + (+) Send an amount of data in non blocking mode using usart_send_by_it() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode using USART_recv_by_it() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + [..] Synchronous: + (+) Send an amount of data in non blocking mode using usart_send_by_it_sync() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode using USART_recv_by_it_sync() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + + *** DMA mode IO operation *** + ============================== + [..] Asynchronous: + (+) Send an amount of data in non blocking mode (DMA) using usart_send_by_dma() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode (DMA) using usart_recv_by_dma() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk()() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + [..] Synchronous: + (+) Send an amount of data in non blocking mode (DMA) using usart_send_by_dma_sync() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode (DMA) using usart_recv_by_dma_sync() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk()() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + [..] Utilities: + (+) Pause the DMA Transfer using usart_dma_pause() + (+) Resume the DMA Transfer using usart_dma_resume() + (+) Stop the DMA Transfer using usart_dma_stop() + + *** USART ALD driver macros list *** + ============================================= + [..] + Below the list of most used macros in USART ALD driver. + + (+) USART_ENABLE: Enable the USART peripheral + (+) USART_DISABLE: Disable the USART peripheral + (+) USART_RESET_HANDLE_STATE : Reset USART handle + (+) USART_CLEAR_PEFLAG : Clear PE flag + (+) USART_CLEAR_FEFLAG: Clear FE flag + (+) USART_CLEAR_NEFLAG: Clear NE flag + (+) USART_CLEAR_OREFLAG: Clear voerrun flag + (+) USART_CLEAR_IDLEFLAG : Clear IDLE flag + (+) USART_HWCONTROL_CTS_ENABLE: Enable CTS flow control + (+) USART_HWCONTROL_CTS_DISABLE: Disable CTS flow control + (+) USART_HWCONTROL_RTS_ENABLE: Enable RTS flow control + (+) USART_HWCONTROL_RTS_DISABLE: Disable RTS flow control + + [..] + (@) You can refer to the USART Library header file for more useful macros + + @endverbatim + ****************************************************************************** + */ + +#include "ald_usart.h" +#include "ald_cmu.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup USART USART + * @brief USART module driver + * @{ + */ +#ifdef ALD_USART + +/** @defgroup USART_Private_Variables USART Private Variables + * @{ + */ +uint8_t __frame_mode = 0; +/** + * @} + */ + +/** @addtogroup USART_Private_Functions USART Private Functions + * @{ + */ +static void usart_set_config(usart_handle_t *hperh); +static ald_status_t __usart_send_by_it(usart_handle_t *hperh); +static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh); +static ald_status_t __usart_recv_by_it(usart_handle_t *hperh); +static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh); +static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh); +static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh); +#ifdef ALD_DMA + static void usart_dma_send_cplt(void *arg); + static void usart_dma_recv_cplt(void *arg); + static void usart_dma_error(void *arg); +#endif +static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout); +/** + * @} + */ + +/** @defgroup USART_Public_Functions USART Public Functions + * @{ + */ + +/** @defgroup USART_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + * @verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the USARTy + in asynchronous or synchronous mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud rate + (++) Word length + (++) Stop bit + (++) Parity + (++) Hardware flow control + (++) Receiver/transmitter modes + [..] + The usart_init(), usart_half_duplex_init(), usart_lin_init(), usart_multi_processor_init() + and usart_clock_init() APIs follow respectively the USART asynchronous, USART Half duplex, + LIN, Multi-Processor and synchronous configuration procedures. + + @endverbatim + * @{ + */ + +/* + Additionnal remark: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible USART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | USART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ +*/ + + +/** + * @brief Reset the USART peripheral. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +void usart_reset(usart_handle_t *hperh) +{ + assert_param(IS_USART(hperh->perh)); + + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); + + WRITE_REG(hperh->perh->CON0, 0x0); + WRITE_REG(hperh->perh->CON1, 0x0); + WRITE_REG(hperh->perh->CON2, 0x0); + + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_RESET; + + __UNLOCK(hperh); + return; +} + +/** + * @brief Initializes the USART mode according to the specified parameters in + * the usart_init_t and create the associated handle. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_init(usart_handle_t *hperh) +{ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); + + usart_reset(hperh); + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); + usart_set_config(hperh); + + /* In asynchronous mode, the following bits must be kept cleared: + * - LINEN and CLKEN bits in the USART_CR2 register, + * - SCEN, HDSEL and IREN bits in the USART_CR3 register. + */ + CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_READY; + USART_ENABLE(hperh); + + return OK; +} + +/** + * @brief Initializes the half-duplex mode according to the specified + * parameters in the usart_init_t and create the associated handle. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_half_duplex_init(usart_handle_t *hperh) +{ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); + + usart_reset(hperh); + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); + usart_set_config(hperh); + + /* In half-duplex mode, the following bits must be kept cleared: + * - LINEN and CLKEN bits in the USART_CR2 register, + * - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + SET_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_READY; + USART_ENABLE(hperh); + + return OK; +} + +/** + * @brief Initializes the Multi-Processor mode according to the specified + * parameters in the usart_init_t and create the associated handle. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param addr: USART node address + * @param wakeup: specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WAKEUP_IDLE: Wakeup by an idle line detection + * @arg USART_WAKEUP_ADDR: Wakeup by an address mark + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup) +{ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_WAKEUP(wakeup)); + assert_param(IS_USART_ADDRESS(addr)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); + + usart_reset(hperh); + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); + usart_set_config(hperh); + + /* In Multi-Processor mode, the following bits must be kept cleared: + * - LINEN and CLKEN bits in the USART_CR2 register, + * - SCEN, HDSEL and IREN bits in the USART_CR3 register */ + CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + MODIFY_REG(hperh->perh->CON1, USART_CON1_ADDR_MSK, addr << USART_CON1_ADDR_POSS); + MODIFY_REG(hperh->perh->CON0, USART_CON0_WKMOD_MSK, wakeup << USART_CON0_WKMOD_POS); + + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_READY; + USART_ENABLE(hperh); + + return OK; +} + +/** + * @brief Initializes the synchronization mode according to the specified + * parameters in the usart_init_t and usart_clock_init_t. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param init: USART Clock Init Structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init) +{ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); + + usart_reset(hperh); + hperh->state = USART_STATE_BUSY; + USART_DISABLE(hperh); + usart_set_config(hperh); + + /* In Multi-Processor mode, the following bits must be kept cleared: + * - LINEN and CLKEN bits in the USART_CR2 register, + * - SCEN, HDSEL and IREN bits in the USART_CR3 register */ + CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); + MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKEN_MSK, init->clk << USART_CON1_SCKEN_POS); + MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKPOL_MSK, init->polarity << USART_CON1_SCKPOL_POS); + MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKPHA_MSK, init->phase << USART_CON1_SCKPHA_POS); + MODIFY_REG(hperh->perh->CON1, USART_CON1_LBCP_MSK, init->last_bit << USART_CON1_LBCP_POS); + + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_READY; + USART_ENABLE(hperh); + + return OK; +} + +/** + * @} + */ + +/** @defgroup USART_Public_Functions_Group2 IO operation functions + * @brief USART Transmit and Receive functions + * @{ + */ + +/** @defgroup USART_Public_Functions_Group2_1 Asynchronization IO operation functions + * @brief Asynchronization IO operation functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART asynchronous + and Half duplex data transfers. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The Status of all data processing is returned by the same function + after finishing transfer. + (++) Non blocking mode: The communication is performed using Interrupts + or DMA, these APIs return the Status. + The end of the data processing will be indicated through the + dedicated USART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks + will be executed respectively at the end of the transmit or receive process. + The hperh->error_cbk() user callback will be executed when + a communication error is detected. + + (#) Blocking mode APIs are: + (++) usart_send() + (++) usart_recv() + + (#) Non Blocking mode APIs with Interrupt are: + (++) usart_send_by_it() + (++) usart_recv_by_it() + (++) urart_irq_handle() + + (#) Non Blocking mode functions with DMA are: + (++) usart_send_by_dma() + (++) usart_recv_by_dma() + (++) usart_dma_pause() + (++) usart_dma_resume() + (++) usart_dma_stop() + + (#) A set of Transfer Complete Callbacks are provided in non blocking mode: + (++) hperh->tx_cplt_cbk() + (++) hperh->rx_cplt_cbk() + (++) hperh->error_cbk() + + [..] + (@) In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the USART state USART_STATE_BUSY_TX_RX + can't be useful. + + @endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = USART_ERROR_NONE; + SET_BIT(hperh->state, USART_STATE_TX_MASK); + + hperh->tx_size = size; + hperh->tx_count = size; + + while (hperh->tx_count-- > 0) + { + if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) + { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) + { + if (hperh->init.parity == USART_PARITY_NONE) + { + WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & (uint16_t)0x01FF)); + buf += 2; + } + else + { + WRITE_REG(hperh->perh->DATA, *buf++); + } + } + else + { + WRITE_REG(hperh->perh->DATA, *buf++); + } + } + + if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) + { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receives an amount of data in blocking mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = USART_ERROR_NONE; + SET_BIT(hperh->state, USART_STATE_RX_MASK); + + hperh->rx_size = size; + hperh->rx_count = size; + + while (hperh->rx_count-- > 0) + { + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) + { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) + { + if (hperh->init.parity == USART_PARITY_NONE) + { + *(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + buf += 2; + } + else + { + *buf = (uint8_t)(hperh->perh->DATA & 0xFF); + buf += 1; + } + } + else + { + if (hperh->init.parity == USART_PARITY_NONE) + *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + } + + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_TX_MASK); + + hperh->tx_buf = buf; + hperh->rx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + + __UNLOCK(hperh); + usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = USART_ERROR_NONE; + + __UNLOCK(hperh); + usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + + return OK; +} + +/** + * @brief Receives an frame in interrupt mode + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param buf: Pointer to data buffer + * @param size: Maximum amount of data to be received + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = USART_ERROR_NONE; + + __UNLOCK(hperh); + usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + __frame_mode = 1; + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as USART transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_TX_MASK); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + /* Configure callback function */ + hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = usart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + /* Configure USART DMA transmit */ + dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) + { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + dma_config_basic(&hperh->hdmatx); + + __UNLOCK(hperh); + usart_clear_flag_status(hperh, USART_FLAG_TC); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param channel: DMA channel as USART receive + * @note When the USART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position) + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + SET_BIT(hperh->state, USART_STATE_RX_MASK); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->err_code = USART_ERROR_NONE; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + /* Configure callback function */ + hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = usart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + /* Configure DMA Receive */ + dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; + hperh->hdmarx.config.channel = channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) + { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + dma_config_basic(&hperh->hdmarx); + + __UNLOCK(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + + return OK; +} +#endif +/** + * @} + */ + +/** @defgroup USART_Public_Functions_Group2_2 Synchronization IO operation functions + * @brief Synchronization IO operation functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART synchronous + data transfers. + + [..] + The USART supports master mode only: it cannot receive or send data related to an input + clock (SCLK is always an output). + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The Status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the Status. + The end of the data processing will be indicated through the + dedicated USART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk() + user callbacks will be executed respectively at the end of the transmit + or Receive process. The hperh->error_cbk() user callback will be + executed when a communication error is detected + + (#) Blocking mode APIs are : + (++) usart_send_sync() in simplex mode + (++) usart_recv_sync() in full duplex receive only + (++) usart_send_recv_sync() in full duplex mode + + (#) Non Blocking mode APIs with Interrupt are : + (++) usart_send_by_it_sync()in simplex mode + (++) usart_recv_by_it_sync() in full duplex receive only + (++) usart_send_recv_by_it_sync() in full duplex mode + (++) usart_irq_handle() + + (#) Non Blocking mode functions with DMA are : + (++) usart_send_by_dma_sync()in simplex mode + (++) usart_recv_by_dma_sync() in full duplex receive only + (++) usart_send_recv_by_dma_symc() in full duplex mode + (++) usart_dma_pause() + (++) usart_dma_resume() + (++) usart_dma_stop() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) hperh->tx_cplt_cbk() + (++) hperh->rx_cplt_cbk() + (++) hperh->tx_rx_cplt_cbk() + (++) hperh->error_cbk() + + @endverbatim + * @{ + */ + +/** + * @brief Simplex Send an amount of data in blocking mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX; + + while (hperh->tx_count-- > 0) + { + if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) + { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) + { + WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & 0x1FF)); + buf += 2; + } + else + { + WRITE_REG(hperh->perh->DATA, *buf++); + } + } + + if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) + { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + hperh->state = USART_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Full-Duplex Receive an amount of data in blocking mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_RX; + + while (hperh->rx_count-- > 0) + { + if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) + { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) + { + WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF)); + + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) + { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.parity == USART_PARITY_NONE) + { + *(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + buf += 2; + } + else + { + *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + } + else + { + WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0xFF)); + + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) + { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.parity == USART_PARITY_NONE) + *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + } + + hperh->state = USART_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param tx_buf: Pointer to data transmitted buffer + * @param rx_buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) +{ + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_RX; + + while (hperh->tx_count-- > 0) + { + --hperh->rx_count; + + if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) + { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) + { + if (hperh->init.parity == USART_PARITY_NONE) + { + WRITE_REG(hperh->perh->DATA, (*(uint16_t *)tx_buf & 0x1FF)); + tx_buf += 2; + } + else + { + WRITE_REG(hperh->perh->DATA, *tx_buf++); + } + + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) + { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.parity == USART_PARITY_NONE) + { + *(uint16_t *)rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + rx_buf += 2; + } + else + { + *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + } + else + { + WRITE_REG(hperh->perh->DATA, *tx_buf++); + + if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) + { + __UNLOCK(hperh); + hperh->state = USART_STATE_READY; + return TIMEOUT; + } + + if (hperh->init.parity == USART_PARITY_NONE) + *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + } + + hperh->state = USART_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Simplex Send an amount of data in non-blocking mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + * @note The USART errors are not managed to avoid the overrun error. + */ +ald_status_t usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX; + + /* The USART Error Interrupts: (Frame error, Noise error, Overrun error) + * are not managed by the USART transmit process to avoid the overrun interrupt + * when the USART mode is configured for transmit and receive "USART_MODE_TX_RX" + * to benefit for the frame error and noise interrupts the USART mode should be + * configured only for transmit "USART_MODE_TX" + * The __ALD_USART_ENABLE_IT(hperh, USART_IT_ERR) can be used to enable the Frame error, + * Noise error interrupt + */ + + __UNLOCK(hperh); + usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + + return OK; +} + +/** + * @brief Simplex Receive an amount of data in non-blocking mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_RX; + + __UNLOCK(hperh); + usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + + WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & (uint16_t)0x01FF)); + return OK; +} + +/** + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param tx_buf: Pointer to data transmitted buffer + * @param rx_buf: Pointer to data received buffer + * @param size: Amount of data to be received + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) +{ + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX_RX; + + __UNLOCK(hperh); + usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Simplex Send an amount of data in non-blocking mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as USART transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + /* Configure callback function */ + hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = usart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + /* Configure DMA transmit */ + dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) + { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + dma_config_basic(&hperh->hdmatx); + + __UNLOCK(hperh); + usart_clear_flag_status(hperh, USART_FLAG_TC); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + + return OK; +} + +/** + * @brief Full-Duplex Receive an amount of data in non-blocking mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param tx_channel: DMA channel as USART transmit + * @param rx_channel: DMA channel as USART receive + * @retval Status, see @ref ald_status_t. + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. + */ +ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) +{ + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_RX; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + /* Configure DMA callback function */ + hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = usart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + /* Configure DMA receive*/ + dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; + hperh->hdmarx.config.channel = rx_channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) + { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + dma_config_basic(&hperh->hdmarx); + + /* Enable the USART transmit DMA channel: the transmit channel is used in order + * to generate in the non-blocking mode the clock to the slave device, + * this mode isn't a simplex receive mode but a full-duplex receive one + */ + dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = tx_channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) + { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + dma_config_basic(&hperh->hdmatx); + + USART_CLEAR_OREFLAG(hperh); + __UNLOCK(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + + return OK; +} + +/** + * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param tx_buf: Pointer to data transmitted buffer + * @param rx_buf: Pointer to data received buffer + * @param size: Amount of data to be received + * @param tx_channel: DMA channel as USART transmit + * @param rx_channel: DMA channel as USART receive + * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, + uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) +{ + if (hperh->state != USART_STATE_READY) + return BUSY; + + if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->err_code = USART_ERROR_NONE; + hperh->state = USART_STATE_BUSY_TX_RX; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + /* Configure DMA callback function */ + hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = usart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + hperh->hdmarx.err_cbk = usart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + /* Configure DMA receive */ + dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)rx_buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; + hperh->hdmarx.config.channel = rx_channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) + { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + dma_config_basic(&hperh->hdmarx); + + /* Configure DMA transmit*/ + dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)tx_buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; + hperh->hdmatx.config.channel = tx_channel; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) + && (hperh->init.parity == USART_PARITY_NONE)) + { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + dma_config_basic(&hperh->hdmatx); + + usart_clear_flag_status(hperh, USART_FLAG_TC); + USART_CLEAR_OREFLAG(hperh); + __UNLOCK(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + + return OK; +} +#endif +/** + * @} + */ + +/** @defgroup USART_Public_Functions_Group2_3 Utilities functions + * @brief Utilities functions + * @{ + */ +#ifdef ALD_DMA +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_dma_pause(usart_handle_t *hperh) +{ + __LOCK(hperh); + + if (hperh->state == USART_STATE_BUSY_TX) + { + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + } + else if (hperh->state == USART_STATE_BUSY_RX) + { + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + } + else if (hperh->state == USART_STATE_BUSY_TX_RX) + { + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + } + else + { + __UNLOCK(hperh); + return ERROR; + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_dma_resume(usart_handle_t *hperh) +{ + __LOCK(hperh); + + if (hperh->state == USART_STATE_BUSY_TX) + { + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + } + else if (hperh->state == USART_STATE_BUSY_RX) + { + USART_CLEAR_OREFLAG(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + } + else if (hperh->state == USART_STATE_BUSY_TX_RX) + { + USART_CLEAR_OREFLAG(hperh); + SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + } + else + { + __UNLOCK(hperh); + return ERROR; + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_dma_stop(usart_handle_t *hperh) +{ + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + + hperh->state = USART_STATE_READY; + return OK; +} +#endif +/** + * @brief This function handles USART interrupt request. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +void usart_irq_handle(usart_handle_t *hperh) +{ + uint32_t flag; + uint32_t source; + + /* Handle parity error */ + flag = usart_get_flag_status(hperh, USART_FLAG_PE); + source = usart_get_it_status(hperh, USART_IT_PE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= USART_ERROR_PE; + + /* Handle frame error */ + flag = usart_get_flag_status(hperh, USART_FLAG_FE); + source = usart_get_it_status(hperh, USART_IT_ERR); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= USART_ERROR_FE; + + /* Handle noise error */ + flag = usart_get_flag_status(hperh, USART_FLAG_NE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= USART_ERROR_NE; + + /* Handle overrun error */ + flag = usart_get_flag_status(hperh, USART_FLAG_ORE); + if ((flag != RESET) && (source != RESET)) + hperh->err_code |= USART_ERROR_ORE; + + /* Handle idle error */ + flag = usart_get_flag_status(hperh, USART_FLAG_IDLE); + source = usart_get_it_status(hperh, USART_IT_IDLE); + if ((flag != RESET) && (source != RESET)) + __usart_recv_frame_cplt(hperh); + + /* Handle asynchronous */ + if (READ_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK) == 0) + { + /* Receiver */ + flag = usart_get_flag_status(hperh, USART_FLAG_RXNE); + source = usart_get_it_status(hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) + __usart_recv_by_it(hperh); + + /* Transmitter */ + flag = usart_get_flag_status(hperh, USART_FLAG_TXE); + source = usart_get_it_status(hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) + __usart_send_by_it(hperh); + } + else /* Handle synchronous */ + { + /* Receiver */ + flag = usart_get_flag_status(hperh, USART_FLAG_RXNE); + source = usart_get_it_status(hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) + { + if (hperh->state == USART_STATE_BUSY_RX) + __usart_recv_by_it_sync(hperh); + else + __usart_send_recv_by_it_sync(hperh); + } + + /* Transmitter */ + flag = usart_get_flag_status(hperh, USART_FLAG_TXE); + source = usart_get_it_status(hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) + { + if (hperh->state == USART_STATE_BUSY_TX) + __usart_send_by_it(hperh); + else + __usart_send_recv_by_it_sync(hperh); + } + } + + /* Handle transmitter end */ + flag = usart_get_flag_status(hperh, USART_FLAG_TC); + source = usart_get_it_status(hperh, USART_IT_TC); + if ((flag != RESET) && (source != RESET)) + __usart_end_send_by_it(hperh); + + /* Handle error */ + if (hperh->err_code != USART_ERROR_NONE) + { + USART_CLEAR_PEFLAG(hperh); + hperh->state = USART_STATE_READY; + + if (hperh->error_cbk != NULL) + hperh->error_cbk(hperh); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Public_Functions_Group3 Peripheral Control functions + * @brief USART control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the USART: + (+) usart_lin_send_break() API can be helpful to transmit the break character. + (+) usart_multi_processor_enter_mute_mode() API can be helpful to enter the USART in mute mode. + (+) usart_multi_processor_exit_mute_mode() API can be helpful to exit the USART mute mode by software. + (+) usart_half_duplex_enable_send() API to enable the USART transmitter and disables the USART receiver in Half Duplex mode + (+) usart_half_duplex_enable_recv() API to enable the USART receiver and disables the USART transmitter in Half Duplex mode + (+) usart_interrupt_config() API to Enables/Disables the specified USART interrupts + (+) usart_get_flag_status() API to get USART flag status + (+) usart_clear_flag_status() API to clear USART flag status + (+) usart_get_it_status() API to Checks whether the specified USART interrupt has occurred or not + + @endverbatim + * @{ + */ + +/** + * @brief Enters the USART in mute mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_multi_processor_enter_mute_mode(usart_handle_t *hperh) +{ + assert_param(IS_USART(hperh->perh)); + + __LOCK(hperh); + + hperh->state = USART_STATE_BUSY; + SET_BIT(hperh->perh->CON0, USART_CON0_RXWK_MSK); + hperh->state = USART_STATE_READY; + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Exits the USART mute mode: wake up software. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_multi_processor_exit_mute_mode(usart_handle_t *hperh) +{ + assert_param(IS_USART(hperh->perh)); + + __LOCK(hperh); + + hperh->state = USART_STATE_BUSY; + CLEAR_BIT(hperh->perh->CON0, USART_CON0_RXWK_MSK); + hperh->state = USART_STATE_READY; + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Enables the USART transmitter and disables the USART receiver. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_half_duplex_enable_send(usart_handle_t *hperh) +{ + __LOCK(hperh); + + hperh->state = USART_STATE_BUSY; + SET_BIT(hperh->perh->CON0, USART_CON0_RXEN_MSK); + SET_BIT(hperh->perh->CON0, USART_CON0_TXEN_MSK); + hperh->state = USART_STATE_READY; + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Enables the USART receiver and disables the USART transmitter. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t usart_half_duplex_enable_recv(usart_handle_t *hperh) +{ + __LOCK(hperh); + + hperh->state = USART_STATE_BUSY; + SET_BIT(hperh->perh->CON0, USART_CON0_RXEN_MSK); + SET_BIT(hperh->perh->CON0, USART_CON0_TXEN_MSK); + hperh->state = USART_STATE_READY; + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Enables or disables the USART's DMA request. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param req: specifies the DMA request. + * @arg USART_dma_req_tx: USART DMA transmit request + * @arg USART_dma_req_rx: USART DMA receive request + * @param state: New state of the DMA Request sources. + * @arg ENABLE + * @arg DISABLE + * @return: None + */ +void usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state) +{ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_DMAREQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state != DISABLE) + SET_BIT(hperh->perh->CON2, req); + else + CLEAR_BIT(hperh->perh->CON2, req); + + return; +} + +/** + * @brief Enables or disables the specified USART interrupts. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param it: Specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state) +{ + uint8_t idx; + + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_CONFIG_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + idx = (it >> 16) & 0x7; + it &= 0xFFFF; + + if (state) + { + if (idx == 1) + SET_BIT(hperh->perh->CON0, it); + else if (idx == 2) + SET_BIT(hperh->perh->CON1, it); + else if (idx == 4) + SET_BIT(hperh->perh->CON2, it); + else + ; + } + else + { + if (idx == 1) + CLEAR_BIT(hperh->perh->CON0, it); + else if (idx == 2) + CLEAR_BIT(hperh->perh->CON1, it); + else if (idx == 4) + CLEAR_BIT(hperh->perh->CON2, it); + else + ; + } + + return; +} + +/** @brief Check whether the specified USART flag is set or not. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref usart_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag) +{ + flag_status_t status = RESET; + + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_FLAG(flag)); + + if (READ_BIT(hperh->perh->STAT, flag)) + status = SET; + + return status; +} + +/** @brief Clear the specified USART pending flags. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param flag: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register followed by a read + * operation to USART_DR register. + * @note RXNE flag can be also cleared by a read to the USART_DR register. + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register followed by a write operation to USART_DR register. + * @note TXE flag is cleared only by a write to the USART_DR register. + * @retval None + */ +void usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag) +{ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_CLEAR_FLAG(flag)); + + CLEAR_BIT(hperh->perh->STAT, flag); +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param it: Specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ORE: OverRun Error interrupt + * @arg USART_IT_NE: Noise Error interrupt + * @arg USART_IT_FE: Framing Error interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @retval Status + * - SET + * - RESET + */ +it_status_t usart_get_it_status(usart_handle_t *hperh, usart_it_t it) +{ + uint8_t idx; + it_status_t status = RESET; + + /* Check the parameters */ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_GET_IT(it)); + + idx = (it >> 16) & 0x7; + it &= 0xFFFF; + + if (idx == 0) + { + if (READ_BIT(hperh->perh->STAT, it)) + status = SET; + } + else if (idx == 1) + { + if (READ_BIT(hperh->perh->CON0, it)) + status = SET; + } + else if (idx == 2) + { + if (READ_BIT(hperh->perh->CON1, it)) + status = SET; + } + else if (idx == 4) + { + if (READ_BIT(hperh->perh->CON2, it)) + status = SET; + } + else + { + /* do nothing */ + } + + return status; +} + +/** + * @} + */ + +/** @defgroup USART_Public_Functions_Group4 Peripheral State and Errors functions + * @brief USART State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + USART communication process, return Peripheral Errors occurred during communication + process + (+) usart_get_state() API can be helpful to check in run-time the state of the USART peripheral. + (+) usart_get_error() check in run-time errors that could be occurred during communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the USART state. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval USART state + */ +usart_state_t usart_get_state(usart_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the USART error code + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART. + * @retval USART Error Code + */ +uint32_t usart_get_error(usart_handle_t *hperh) +{ + return hperh->err_code; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions USART Private Functions + * @brief USART Private functions + * @{ + */ +#ifdef ALD_DMA +/** + * @brief DMA USART transmit process complete callback. + * @param arg: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +static void usart_dma_send_cplt(void *arg) +{ + usart_handle_t *hperh = (usart_handle_t *)arg; + + hperh->tx_count = 0; + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + usart_interrupt_config(hperh, USART_IT_TC, ENABLE); +} + +/** + * @brief DMA USART receive process complete callback. + * @param arg: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +static void usart_dma_recv_cplt(void *arg) +{ + usart_handle_t *hperh = (usart_handle_t *)arg; + + hperh->rx_count = 0; + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk != NULL) + hperh->rx_cplt_cbk(hperh); +} + +/** + * @brief DMA USART communication error callback. + * @param arg: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +static void usart_dma_error(void *arg) +{ + usart_handle_t *hperh = (usart_handle_t *)arg; + + hperh->rx_count = 0; + hperh->tx_count = 0; + hperh->state = USART_STATE_READY; + hperh->err_code |= USART_ERROR_DMA; + + CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); + CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); + + if (hperh->error_cbk != NULL) + hperh->error_cbk(hperh); +} +#endif +/** + * @brief This function handles USART Communication Timeout. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @param flag: specifies the USART flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick; + + if (timeout == 0) + return OK; + + tick = __get_tick(); + + while ((usart_get_flag_status(hperh, flag)) != status) + { + if (((__get_tick()) - tick) > timeout) + { + usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + + return TIMEOUT; + } + } + + return OK; +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __usart_send_by_it(usart_handle_t *hperh) +{ + if ((hperh->state != USART_STATE_BUSY_TX) && (hperh->state != USART_STATE_BUSY_TX_RX)) + return BUSY; + + if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) + { + WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & (uint16_t)0x01FF)); + hperh->tx_buf += 2; + } + else + { + WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); + } + + if (--hperh->tx_count == 0) + { + usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + usart_interrupt_config(hperh, USART_IT_TC, ENABLE); + } + + return OK; +} + + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hperh: pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh) +{ + usart_interrupt_config(hperh, USART_IT_TC, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); + + if (hperh->tx_cplt_cbk != NULL) + hperh->tx_cplt_cbk(hperh); + + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __usart_recv_by_it(usart_handle_t *hperh) +{ + if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX)) + return BUSY; + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) + { + if (hperh->init.parity == USART_PARITY_NONE) + { + *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & (uint16_t)0x01FF); + hperh->rx_buf += 2; + } + else + { + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + } + else + { + if (hperh->init.parity == USART_PARITY_NONE) + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + + if (__frame_mode && ((usart_get_it_status(hperh, USART_IT_IDLE)) == RESET)) + usart_interrupt_config(hperh, USART_IT_IDLE, ENABLE); + + if (--hperh->rx_count == 0) + { + usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + __frame_mode = 0; + + if (hperh->state == USART_STATE_READY) + { + usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + } + + if (hperh->rx_cplt_cbk != NULL) + hperh->rx_cplt_cbk(hperh); + } + + return OK; +} + +/** + * @brief Receives an frame complete in non blocking mode + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh) +{ + if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX)) + return BUSY; + + usart_interrupt_config(hperh, USART_IT_IDLE, DISABLE); + usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); + + __frame_mode = 0; + hperh->rx_size -= hperh->rx_count; + + if (hperh->state == USART_STATE_READY) + { + usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + } + + if (hperh->rx_cplt_cbk != NULL) + hperh->rx_cplt_cbk(hperh); + + return OK; +} + + + +/** + * @brief Simplex Receive an amount of data in non-blocking mode. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh) +{ + if (hperh->state != USART_STATE_BUSY_RX) + return BUSY; + + if (hperh->init.word_length == USART_WORD_LENGTH_9B) + { + + if (hperh->init.parity == USART_PARITY_NONE) + { + *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + hperh->rx_buf += 2; + } + else + { + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + + if (--hperh->rx_count != 0x00) + WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF)); + } + else + { + if (hperh->init.parity == USART_PARITY_NONE) + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + + if (--hperh->rx_count != 0x00) + hperh->perh->DATA = (DUMMY_DATA & 0xFF); + } + + if (hperh->rx_count == 0) + { + usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + hperh->state = USART_STATE_READY; + + if (hperh->rx_cplt_cbk != NULL) + hperh->rx_cplt_cbk(hperh); + } + + return OK; +} + +/** + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh) +{ + if (hperh->state != USART_STATE_BUSY_TX_RX) + return BUSY; + + if (hperh->tx_count != 0) + { + if (usart_get_flag_status(hperh, USART_FLAG_TXE) != RESET) + { + if (hperh->init.word_length == USART_WORD_LENGTH_9B) + { + if (hperh->init.parity == USART_PARITY_NONE) + { + WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & 0x1FF)); + hperh->tx_buf += 2; + } + else + { + WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); + } + } + else + { + WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); + } + + if (--hperh->tx_count == 0) + usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + } + } + + if (hperh->rx_count != 0) + { + if (usart_get_flag_status(hperh, USART_FLAG_RXNE) != RESET) + { + if (hperh->init.word_length == USART_WORD_LENGTH_9B) + { + if (hperh->init.parity == USART_PARITY_NONE) + { + *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); + hperh->rx_buf += 2; + } + else + { + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + } + } + else + { + if (hperh->init.parity == USART_PARITY_NONE) + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); + else + *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); + } + + --hperh->rx_count; + } + } + + if (hperh->rx_count == 0) + { + usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + + hperh->state = USART_STATE_READY; + + if (hperh->tx_rx_cplt_cbk != NULL) + hperh->tx_rx_cplt_cbk(hperh); + } + + return OK; +} + +/** + * @brief Configures the USART peripheral. + * @param hperh: Pointer to a usart_handle_t structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +static void usart_set_config(usart_handle_t *hperh) +{ + uint32_t tmp; + uint32_t integer; + uint32_t fractional; + + /* Check the parameters */ + assert_param(IS_USART(hperh->perh)); + assert_param(IS_USART_BAUDRATE(hperh->init.baud)); + assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_USART_PARITY(hperh->init.parity)); + assert_param(IS_USART_MODE(hperh->init.mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); + + MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS); + tmp = READ_REG(hperh->perh->CON0); + MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS); + + if (hperh->init.parity == USART_PARITY_NONE) + CLEAR_BIT(tmp, USART_CON0_PEN_MSK); + else + SET_BIT(tmp, USART_CON0_PEN_MSK); + + if (hperh->init.parity == USART_PARITY_ODD) + SET_BIT(tmp, USART_CON0_PSEL_MSK); + else + CLEAR_BIT(tmp, USART_CON0_PSEL_MSK); + + WRITE_REG(hperh->perh->CON0, tmp); + MODIFY_REG(hperh->perh->CON2, USART_CON2_RTSEN_MSK, (hperh->init.fctl & 0x1) << USART_CON2_RTSEN_POS); + MODIFY_REG(hperh->perh->CON2, USART_CON2_CTSEN_MSK, ((hperh->init.fctl >> 1) & 0x1) << USART_CON2_CTSEN_POS); + MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS); + MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS); + + if (hperh->init.over_sampling) + SET_BIT(hperh->perh->CON0, (1 << 15)); + + /* Determine the integer part */ + if (READ_BIT(hperh->perh->CON0, (1 << 15))) + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integer = ((25 * cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); + } + else + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integer = ((25 * cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); + } + tmp = (integer / 100) << 4; + + /* Determine the fractional part */ + fractional = integer - (100 * (tmp >> 4)); + + /* Implement the fractional part in the register */ + if (READ_BIT(hperh->perh->CON0, (1 << 15))) + tmp |= ((((fractional * 8) + 50) / 100) & ((uint8_t)0x07)); + else + tmp |= ((((fractional * 16) + 50) / 100) & ((uint8_t)0x0F)); + + WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp); + return; +} +/** + * @} + */ + +#endif /* ALD_USART */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c new file mode 100644 index 0000000000..cbe2921ee9 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c @@ -0,0 +1,214 @@ +/** + ********************************************************************************* + * + * @file ald_wdt.c + * @brief WDT module driver. + * + * @version V1.0 + * @date 18 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ +#include "ald_conf.h" +#include "ald_wdt.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup WDT WDT + * @brief WDT module driver + * @{ + */ +#ifdef ALD_WDT + + +/** @defgroup WWDT_Public_Functions WWDT Public Functions + * @brief Init and configure WWDT function + * @{ + */ +/** + * @brief Initializes the WWDT according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param win: specifics the no dog windows, + * the parameter can be one of the following values: + * @arg @ref WWDT_WIN_25 No dog window size: 25% + * @arg @ref WWDT_WIN_50 No dog window size: 50% + * @arg @ref WWDT_WIN_75 No dog window size: 75% + * @arg @ref WWDT_WIN_00 No dog window size: 0% + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt) +{ + assert_param(IS_WWDT_WIN_TYPE(win)); + assert_param(IS_FUNC_STATE(interrupt)); + + WWDT_UNLOCK(); + WRITE_REG(WWDT->LOAD, load); + MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS); + SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK); + SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK); + MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS); + WWDT_LOCK(); + + return; +} + +/** + * @brief Start the WWDT + * @retval None + */ +void wwdt_start(void) +{ + WWDT_UNLOCK(); + SET_BIT(WWDT->CON, WWDT_CON_EN_MSK); + WWDT_LOCK(); + + return; +} + +/** + * @brief Get the free-running downcounter value + * @retval Value + */ +uint32_t wwdt_get_value(void) +{ + return WWDT->VALUE; +} + +/** + * @brief Get interrupt state + * @retval Value + */ +it_status_t wwdt_get_flag_status(void) +{ + if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK)) + return SET; + + return RESET; +} + +/** + * @brief Clear interrupt state + * @retval None + */ +void wwdt_clear_flag_status(void) +{ + WRITE_REG(WWDT->INTCLR, 1); + return; +} + +/** + * @brief Refreshes the WWDT + * @retval None + */ +void wwdt_feed_dog(void) +{ + WWDT_UNLOCK(); + WRITE_REG(WWDT->INTCLR, 0x1); + WWDT_LOCK(); + + return; +} +/** + * @} + */ + +/** @defgroup IWDT_Public_Functions IWDT Public Functions + * @brief Init and configure IWDT function + * @{ + */ +/** + * @brief Initializes the IWDG according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void iwdt_init(uint32_t load, type_func_t interrupt) +{ + assert_param(IS_FUNC_STATE(interrupt)); + + IWDT_UNLOCK(); + WRITE_REG(IWDT->LOAD, load); + SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK); + SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK); + MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS); + IWDT_LOCK(); + + return; +} + +/** + * @brief Start the IWDT + * @retval None + */ +void iwdt_start(void) +{ + IWDT_UNLOCK(); + SET_BIT(IWDT->CON, IWDT_CON_EN_MSK); + IWDT_LOCK(); + + return; +} + +/** + * @brief Get the free-running downcounter value + * @retval Value + */ +uint32_t iwdt_get_value(void) +{ + return IWDT->VALUE; +} + +/** + * @brief Get interrupt state + * @retval Value + */ +it_status_t iwdt_get_flag_status(void) +{ + if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK)) + return SET; + + return RESET; +} + +/** + * @brief Clear interrupt state + * @retval None + */ +void iwdt_clear_flag_status(void) +{ + WRITE_REG(IWDT->INTCLR, 1); + return; +} + +/** + * @brief Refreshes the WWDT + * @retval None + */ +void iwdt_feed_dog(void) +{ + IWDT_UNLOCK(); + WRITE_REG(IWDT->INTCLR, 1); + IWDT_LOCK(); + + return; +} +/** + * @} + */ + +#endif /* ALD_WDT */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c new file mode 100644 index 0000000000..24c6bfdf45 --- /dev/null +++ b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c @@ -0,0 +1,421 @@ +/** + ********************************************************************************* + * + * @file utils.c + * @brief This file contains the Utilities functions/types for the driver. + * + * @version V1.0 + * @date 07 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "utils.h" +#include "ald_dma.h" +#include "ald_cmu.h" + + +/** @defgroup ES32FXXX_ALD EASTSOFT ES32F0xx ALD + * @brief Shanghai Eastsoft Microelectronics Cortex-M Chip Abstraction Layer Driver(ALD) + * @{ + */ + +/** @defgroup UTILS Utils + * @brief Utils module driver + * @{ + */ + +/** @defgroup ALD_Private_Constants Private Constants + * @brief ALD Private Constants + * @{ + */ + +/** + * @brief ALD version number + */ +#define __ALD_VERSION_MAIN (0x01) /**< [31:24] main version */ +#define __ALD_VERSION_SUB1 (0x00) /**< [23:16] sub1 version */ +#define __ALD_VERSION_SUB2 (0x00) /**< [15:8] sub2 version */ +#define __ALD_VERSION_RC (0x00) /**< [7:0] release candidate */ +#define __ALD_VERSION ((__ALD_VERSION_MAIN << 24) | \ + (__ALD_VERSION_SUB1 << 16) | \ + (__ALD_VERSION_SUB2 << 8 ) | \ + (__ALD_VERSION_RC)) +/** + * @} + */ + +/** @defgroup ALD_Private_Variables Private Variables + * @{ + */ +/** @brief lib_tick: Increase by one millisecond + */ +static __IO uint32_t lib_tick; +uint32_t __systick_interval = SYSTICK_INTERVAL_1MS; +/** + * @} + */ + + +/** @defgroup ALD_Public_Functions Public Functions + * @{ + */ + +/** @defgroup ALD_Public_Functions_Group1 Initialization Function + * @brief Initialization functions + * + * @verbatim + =============================================================================== + ##### Initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes interface, the NVIC allocation and initial clock + configuration. It initializes the source of time base also when timeout + is needed and the backup domain when enabled. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) Systick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms. + (++) Time base configuration function (__init_tick()) is called automatically + at the beginning of the program after reset by mcu_ald_init() or at + any time when clock is configured. + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if __delay_ms() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. + (+) Configure the interval of Systick interrupt. + + @endverbatim + * @{ + */ + +/** + * @brief This function Configures time base source, NVIC and DMA. + * @note This function is called at the beginning of program after reset and before + * the clock configuration. + * @note The time base configuration is based on MSI clock when exiting from Reset. + * Once done, time base tick start incrementing. + * In the default implementation, Systick is used as source of time base. + * The tick variable is incremented each 1ms in its ISR. + * @retval None + */ +void mcu_ald_init(void) +{ + cmu_clock_config_default(); + __init_tick(TICK_INT_PRIORITY); +#ifdef ALD_DMA + dma_init(DMA0); +#endif + return; +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if __delay_ms() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param prio: Tick interrupt priority. + * @retval None + */ +__weak void __init_tick(uint32_t prio) +{ + /* Configure the SysTick IRQ */ + SysTick_Config(cmu_get_clock() / SYSTICK_INTERVAL_1MS); + + if (prio != 3) + NVIC_SetPriority(SysTick_IRQn, prio); + + return; +} + +/** + * @brief Selects the interval of systick interrupt. + * @param value: The value of interval: + * @arg @ref SYSTICK_INTERVAL_1MS 1 millisecond + * @arg @ref SYSTICK_INTERVAL_10MS 10 milliseconds + * @arg @ref SYSTICK_INTERVAL_100MS 100 milliseconds + * @arg @ref SYSTICK_INTERVAL_1000MS 1 second + * @retval None + */ +void systick_interval_select(systick_interval_t value) +{ + assert_param(IS_SYSTICK_INTERVAL(value)); + + SysTick_Config(cmu_get_clock() / value); + __systick_interval = value; + + if (TICK_INT_PRIORITY != 3) + NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY); + + return; +} +/** + * @} + */ + +/** @defgroup ALD_Public_Functions_Group2 Control functions + * @brief Control functions + * + * @verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the ALD version + (+) Waiting for flag + (+) Configure the interrupt + (+) Provide system tick value + (+) Get CPU ID + @endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "lib_tick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void __inc_tick(void) +{ + ++lib_tick; +} + +/** + * @brief This function invoked by Systick ISR. + * @note This function is declared as __weak to be overwritten in case of + * other implementations in user file. + * @retval None + */ +__weak void systick_irq_cbk(void) +{ + /* do nothing */ + return; +} + +/** + * @brief This function invoked by Systick ISR each 1ms. + * @retval None + */ +__isr__ void SysTick_Handler(void) +{ + __inc_tick(); + systick_irq_cbk(); + + return; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t __get_tick(void) +{ + return lib_tick; +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where lib_tick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param delay: specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void __delay_ms(__IO uint32_t delay) +{ + uint32_t tick, __delay; + + switch (__systick_interval) + { + case SYSTICK_INTERVAL_1MS: + __delay = delay; + break; + + case SYSTICK_INTERVAL_10MS: + __delay = delay / 10; + break; + + case SYSTICK_INTERVAL_100MS: + __delay = delay / 100; + break; + + case SYSTICK_INTERVAL_1000MS: + __delay = delay / 1000; + break; + + default: + __delay = delay; + break; + } + + tick = __get_tick(); + __delay = __delay == 0 ? 1 : __delay; + + while ((__get_tick() - tick) < __delay) + ; +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Once __suspend_tick() is called, the the SysTick interrupt + * will be disabled and so Tick increment is suspended. + * @note This function is declared as __weak to be overwritten + * in case of other implementations in user file. + * @retval None + */ +__weak void __suspend_tick(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation, SysTick timer is the source of + * time base. It is used to generate interrupts at regular time + * intervals. Once __resume_tick() is called, the the SysTick + * interrupt will be enabled and so Tick increment is resumed. + * @note This function is declared as __weak to be overwritten + * in case of other implementations in user file. + * @retval None + */ +__weak void __resume_tick(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief This method returns the ALD revision + * @retval version: 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t get_ald_version(void) +{ + return __ALD_VERSION; +} + +/** + * @brief Waiting the specified bit in the register change to SET/RESET. + * @param reg: The register address. + * @param bit: The specified bit. + * @param status: The status for waiting. + * @param timeout: Timeout duration. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout) +{ + uint32_t tick = __get_tick(); + + assert_param(timeout > 0); + + if (status == SET) + { + while (!(IS_BIT_SET(*reg, bit))) + { + if (((__get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + else + { + while ((IS_BIT_SET(*reg, bit))) + { + if (((__get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + + return OK; +} + +/** + * @brief Configure interrupt. + * @param irq: Interrunpt type. + * @param prio: preempt priority(0-3). + * @param status: Status. + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) +{ + assert_param(IS_FUNC_STATE(status)); + assert_param(IS_PRIO(prio)); + + if (status == ENABLE) + { + NVIC_SetPriority(irq, prio); + NVIC_EnableIRQ(irq); + } + else + { + NVIC_DisableIRQ(irq); + } + + return; +} + +/** + * @brief Get the system tick. + * @retval The value of current tick. + */ +uint32_t mcu_get_tick(void) +{ + uint32_t load = SysTick->LOAD; + uint32_t val = SysTick->VAL; + + return (load - val); +} + +/** + * @brief Get the CPU ID. + * @retval CPU ID. + */ +uint32_t mcu_get_cpu_id(void) +{ + return SCB->CPUID; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/SConscript b/bsp/es32f0654/libraries/SConscript new file mode 100644 index 0000000000..bbc9d5d2e1 --- /dev/null +++ b/bsp/es32f0654/libraries/SConscript @@ -0,0 +1,28 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = [] + +src += Glob('ES32F065x_ALD_StdPeriph_Driver/Source/*.c') + + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['CMSIS/Device/EastSoft/ES32F065x/Startup/gcc/startup_es32f065x.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s'] + +path = [cwd + '/CMSIS/Device/EastSoft/ES32F065x/Include', + cwd + '/CMSIS/Include', + cwd + '/ES32F065x_ALD_StdPeriph_Driver/Include'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/es32f0654/project.uvoptx b/bsp/es32f0654/project.uvoptx new file mode 100644 index 0000000000..d3460f8030 --- /dev/null +++ b/bsp/es32f0654/project.uvoptx @@ -0,0 +1,176 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread_es32f065x + 0x4 + ARM-ADS + + 24000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 3 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0ES32F065x -FS00 -FL040000 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0es32f0xx -FL040000 -FS00 -FP0($$Device:ES32F0654LT$Flash\es32f0xx.FLM) + + + 0 + JL2CM3 + -U12345678 -O78 -S4 -ZTIFSpeedSel2000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0ES32F065x -FS00 -FL040000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + diff --git a/bsp/es32f0654/project.uvprojx b/bsp/es32f0654/project.uvprojx new file mode 100644 index 0000000000..fe59aa858b --- /dev/null +++ b/bsp/es32f0654/project.uvprojx @@ -0,0 +1,936 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread_es32f065x + 0x4 + ARM-ADS + + + ES32F0654LT + Eastsoft + Eastsoft.ES32_DFP.1.0.1 + http://www.essemi.com + IRAM(0x20000000,0x00008000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0es32f0xx -FS00 -FL040000 -FP0($$Device:ES32F0654LT$Flash\es32f0xx.FLM)) + 0 + $$Device:ES32F0654LT$Device\Include\es32f0xx.h + + + + + + + + + + $$Device:ES32F0654LT$SVD\es32f0xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\keil\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + -MPU + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + .;..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\ES32F065x\Include;libraries\CMSIS\Include;libraries\ES32F065x_ALD_StdPeriph_Driver\Include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + Kernel + + + clock.c + 1 + ..\..\src\clock.c + + + + + components.c + 1 + ..\..\src\components.c + + + + + cpu.c + 1 + ..\..\src\cpu.c + + + + + device.c + 1 + ..\..\src\device.c + + + + + idle.c + 1 + ..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\src\mempool.c + + + + + object.c + 1 + ..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\src\signal.c + + + + + thread.c + 1 + ..\..\src\thread.c + + + + + timer.c + 1 + ..\..\src\timer.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + + + drv_usart.c + 1 + drivers\drv_usart.c + + + + + Libraries + + + ald_acmp.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_acmp.c + + + + + ald_adc.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_adc.c + + + + + ald_bkpc.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_bkpc.c + + + + + ald_calc.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_calc.c + + + + + ald_can.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_can.c + + + + + ald_cmu.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_cmu.c + + + + + ald_crc.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crc.c + + + + + ald_crypt.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crypt.c + + + + + ald_dma.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_dma.c + + + + + ald_flash.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash.c + + + + + ald_gpio.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_gpio.c + + + + + ald_i2c.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_i2c.c + + + + + ald_iap.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_iap.c + + + + + ald_pis.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pis.c + + + + + ald_pmu.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pmu.c + + + + + ald_rmu.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rmu.c + + + + + ald_rtc.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rtc.c + + + + + ald_smartcard.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_smartcard.c + + + + + ald_spi.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_spi.c + + + + + ald_temp.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_temp.c + + + + + ald_timer.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c + + + + + ald_trng.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c + + + + + ald_uart.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_uart.c + + + + + ald_usart.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_usart.c + + + + + ald_wdt.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_wdt.c + + + + + utils.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\utils.c + + + + + startup_es32f065x.s + 2 + libraries\CMSIS\Device\EastSoft\ES32F065x\Startup\keil\startup_es32f065x.s + + + + + cpu + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m0\cpuport.c + + + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m0\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + + + symbol.c + 1 + ..\..\components\finsh\symbol.c + + + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + + + msh_cmd.c + 1 + ..\..\components\finsh\msh_cmd.c + + + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + + + + + + + + + + diff --git a/bsp/es32f0654/rtconfig.h b/bsp/es32f0654/rtconfig.h new file mode 100644 index 0000000000..a2217aa7be --- /dev/null +++ b/bsp/es32f0654/rtconfig.h @@ -0,0 +1,169 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_VER_NUM 0x40001 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* sample package */ + +/* samples: kernel and components samples */ + + +/* example package: hello */ + +#define SOC_ES32F0654LT + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO + +/* UART Drivers */ + +#define BSP_USING_UART2 + +/* Onboard Peripheral Drivers */ + +/* Offboard Peripheral Drivers */ + + +#endif diff --git a/bsp/es32f0654/rtconfig.py b/bsp/es32f0654/rtconfig.py new file mode 100644 index 0000000000..f8be824456 --- /dev/null +++ b/bsp/es32f0654/rtconfig.py @@ -0,0 +1,135 @@ +import os +import sys + +# toolchains options +CROSS_TOOL = 'keil' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# device options +ARCH = 'arm' +CPU = 'cortex-m0' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': # not support gcc yet + PLATFORM = 'gcc' + EXEC_PATH = 'C:/GCC' + +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil' + +elif CROSS_TOOL == 'iar': # not support iar yet + PLATFORM = 'iar' + EXEC_PATH = 'C:/IAR' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -std=c99' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMSTM' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + LFLAGS = ' --config "drivers\linker_scripts\link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS += ' --entry __iar_program_start' + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/es32f0654/template.uvoptx b/bsp/es32f0654/template.uvoptx new file mode 100644 index 0000000000..d3460f8030 --- /dev/null +++ b/bsp/es32f0654/template.uvoptx @@ -0,0 +1,176 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread_es32f065x + 0x4 + ARM-ADS + + 24000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 3 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0ES32F065x -FS00 -FL040000 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0es32f0xx -FL040000 -FS00 -FP0($$Device:ES32F0654LT$Flash\es32f0xx.FLM) + + + 0 + JL2CM3 + -U12345678 -O78 -S4 -ZTIFSpeedSel2000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0ES32F065x -FS00 -FL040000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + diff --git a/bsp/es32f0654/template.uvprojx b/bsp/es32f0654/template.uvprojx new file mode 100644 index 0000000000..be655d2f35 --- /dev/null +++ b/bsp/es32f0654/template.uvprojx @@ -0,0 +1,386 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread_es32f065x + 0x4 + ARM-ADS + + + ES32F0654LT + Eastsoft + Eastsoft.ES32_DFP.1.0.1 + http://www.essemi.com + IRAM(0x20000000,0x00008000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0es32f0xx -FS00 -FL040000 -FP0($$Device:ES32F0654LT$Flash\es32f0xx.FLM)) + 0 + $$Device:ES32F0654LT$Device\Include\es32f0xx.h + + + + + + + + + + $$Device:ES32F0654LT$SVD\es32f0xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\keil\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + -MPU + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + + + + + + + + -- GitLab