diff --git a/bsp/nuvoton/libraries/n9h30/Driver/Include/N9H30.h b/bsp/nuvoton/libraries/n9h30/Driver/Include/N9H30.h
new file mode 100644
index 0000000000000000000000000000000000000000..2bdc5ebddd03dd3c087664a248366cac8738399d
--- /dev/null
+++ b/bsp/nuvoton/libraries/n9h30/Driver/Include/N9H30.h
@@ -0,0 +1,2097 @@
+/**************************************************************************//**
+ * @file N9H30.h
+ * @version V1.00
+ * @brief N9H30 peripheral access layer header file.
+ * This file contains all the peripheral register's definitions
+ * and memory mapping for NuMicro N9H30 MCU.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+/**
+ \mainpage NuMicro N9H30 Family Driver Reference Guide
+ *
+ * Introduction
+ *
+ * This user manual describes the usage of N9H30 family device driver
+ *
+ * Disclaimer
+ *
+ * The Software is furnished "AS IS", without warranty as to performance or results, and
+ * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
+ * warranties, express, implied or otherwise, with regard to the Software, its use, or
+ * operation, including without limitation any and all warranties of merchantability, fitness
+ * for a particular purpose, and non-infringement of intellectual property rights.
+ *
+ * Important Notice
+ *
+ * Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
+ * any malfunction or failure of which may cause loss of human life, bodily injury or severe
+ * property damage. Such applications are deemed, "Insecure Usage".
+ *
+ * Insecure usage includes, but is not limited to: equipment for surgical implementation,
+ * atomic energy control instruments, airplane or spaceship instruments, the control or
+ * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
+ * instruments, all types of safety devices, and other applications intended to support or
+ * sustain life.
+ *
+ * All Insecure Usage shall be made at customer's risk, and in the event that third parties
+ * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
+ * the damages and liabilities thus incurred by Nuvoton.
+ *
+ * Please note that all data and specifications are subject to change without notice. All the
+ * trademarks of products and companies mentioned in this document belong to their respective
+ * owners.
+ *
+ * Copyright Notice
+ *
+ * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ */
+
+#ifndef __N9H30_H__
+ #define __N9H30_H__
+
+ #include
+
+ /** @addtogroup N9H30_PERIPHERAL_MEM_MAP N9H30 Peripheral Memory Base
+ Memory Mapped Structure for N9H30 Peripheral
+ @{
+ */
+
+ /*!< AHB peripherals */
+ #define SYS_BA 0xB0000000 /*!< System Global Control */
+ #define CLK_BA 0xB0000200 /*!< Clock Control */
+ #define EBI_BA 0xB0001000 /*!< EBI Control */
+ #define SDIC_BA 0xB0001800 /*!< SDRAM (SDR/DDR/DDR2) Control */
+ #define EMC0_BA 0xB0002000 /*!< Ethernet MAC 0 Control */
+ #define EMC1_BA 0xB0003000 /*!< Ethernet MAC 1 Control */
+ #define GDMA_BA 0xB0004000 /*!< GDMA control */
+ #define USBH_BA 0xB0005000 /*!< USB Host EHCI Control */
+ #define USBD_BA 0xB0006000 /*!< USB Device Control */
+ #define USBO_BA 0xB0007000 /*!< OHCI USB Host Control */
+ #define LCM_BA 0xB0008000 /*!< Display, LCM Interface */
+ #define ACTL_BA 0xB0009000 /*!< Audio Control */
+ #define JPEG_BA 0xB000A000 /*!< JPEG Engine Control */
+ #define GE_BA 0xB000B000 /*!< 2-D Graphic Engine */
+ #define SDH_BA 0xB000C000 /*!< SD/SDIO Host Controller */
+ #define FMI_BA 0xB000D000 /*!< Flash Memory Card Interface */
+ #define CAP_BA 0xB000E000 /*!< Sensor (Capture) Interface Control */
+ #define CRPT_BA 0xB000F000 /*!< Crypto Engine Control */
+
+ /*!< APB peripherals */
+ #define UART0_BA 0xB8000000 /*!< UART0 Control */
+ #define UART1_BA 0xB8000100 /*!< UART1 Control (High-Speed UART) */
+ #define UART2_BA 0xB8000200 /*!< UART2 Control (High-Speed UART) */
+ #define UART3_BA 0xB8000300 /*!< UART3 Control */
+ #define UART4_BA 0xB8000400 /*!< UART4 Control (High-Speed UART) */
+ #define UART5_BA 0xB8000500 /*!< UART5 Control */
+ #define UART6_BA 0xB8000600 /*!< UART6 Control (High-Speed UART) */
+ #define UART7_BA 0xB8000700 /*!< UART7 Control */
+ #define UART8_BA 0xB8000800 /*!< UART8 Control (High-Speed UART) */
+ #define UART9_BA 0xB8000900 /*!< UART9 Control */
+ #define UARTA_BA 0xB8000A00 /*!< UARTA Control (High-Speed UART) */
+ #define TMR0_BA 0xB8001000 /*!< Timer 0 */
+ #define TMR1_BA 0xB8001010 /*!< Timer 1 */
+ #define TMR2_BA 0xB8001020 /*!< Timer 2 */
+ #define TMR3_BA 0xB8001030 /*!< Timer 3 */
+ #define TMR4_BA 0xB8001040 /*!< Timer 4 */
+ #define ETMR0_BA 0xB8001400 /*!< Enhanced Timer 0 */
+ #define ETMR1_BA 0xB8001500 /*!< Enhanced Timer 1 */
+ #define ETMR2_BA 0xB8001600 /*!< Enhanced Timer 2 */
+ #define ETMR3_BA 0xB8001700 /*!< Enhanced Timer 3 */
+ #define WDT_BA 0xB8001800 /*!< Watch Dog Timer */
+ #define WWDT_BA 0xB8001900 /*!< Window Watch Dog Timer */
+ #define AIC_BA 0xB8002000 /*!< Interrupt Controller */
+ #define GPIO_BA 0xB8003000 /*!< GPIO Control */
+ #define RTC_BA 0xB8004000 /*!< Real Time Clock Control */
+ #define SC0_BA 0xB8005000 /*!< Smart Card 0 Control */
+ #define SC1_BA 0xB8005400 /*!< Smart Card 1 Control */
+ #define I2C0_BA 0xB8006000 /*!< I2C 0 Control */
+ #define I2C1_BA 0xB8006100 /*!< I2C 1 Control */
+ #define SPI0_BA 0xB8006200 /*!< Serial Peripheral Interface 0 */
+ #define SPI1_BA 0xB8006300 /*!< Serial Peripheral Interface 1 */
+ #define PWM_BA 0xB8007000 /*!< Pulse Width Modulation (PWM) Control */
+ #define ADC_BA 0xB800A000 /*!< ADC Control */
+ #define CAN0_BA 0xB800B000 /*!< CAN 0 Control */
+ #define CAN1_BA 0xB800B400 /*!< CAN 1 Control */
+ #define MTP_BA 0xB800C000 /*!< MTP Control */
+
+ /*@}*/ /* end of group N9H30_PERIPHERAL_MEM_MAP */
+
+ /******************************************************************************/
+ /* Device Specific Peripheral registers structures */
+ /******************************************************************************/
+ /** @addtogroup N9H30_Peripherals N9H30 Control Register
+ N9H30 Device Specific Peripheral registers structures
+ @{
+ */
+
+ /*---------------------- System Manger Controller -------------------------*/
+ /**
+ @addtogroup SYS System Manger Controller(SYS)
+ Memory Mapped Structure for SYS Controller
+ @{ */
+
+ #define REG_SYS_PDID (SYS_BA+0x000) /*!< Product Identifier Register */
+ #define REG_SYS_PWRON (SYS_BA+0x004) /*!< Power-On Setting Register */
+ #define REG_SYS_ARBCON (SYS_BA+0x008) /*!< Arbitration Control Register */
+ #define REG_SYS_LVRDCR (SYS_BA+0x020) /*!< Low Voltage Reset & Detect Control Register */
+ #define REG_SYS_MISCFCR (SYS_BA+0x030) /*!< Miscellaneous Function Control Register */
+ #define REG_SYS_MISCIER (SYS_BA+0x040) /*!< Miscellaneous Interrupt Enable Register */
+ #define REG_SYS_MISCISR (SYS_BA+0x044) /*!< Miscellaneous Interrupt Status Register */
+ #define REG_SYS_WKUPSER (SYS_BA+0x058) /*!< System Wakeup Source Enable Register */
+ #define REG_SYS_WKUPSSR (SYS_BA+0x05C) /*!< System Wakeup Source Status Register */
+ #define REG_SYS_AHBIPRST (SYS_BA+0x060) /*!< AHB IP Reset Control Register */
+ #define REG_SYS_APBIPRST0 (SYS_BA+0x064) /*!< APB IP Reset Control Register 0 */
+ #define REG_SYS_APBIPRST1 (SYS_BA+0x068) /*!< APB IP Reset Control Register 1 */
+ #define REG_SYS_RSTSTS (SYS_BA+0x06C) /*!< Reset Source Active Status Register */
+ #define REG_SYS_GPA_MFPL (SYS_BA+0x070) /*!< GPIOA Low Byte Multiple Function Control Register */
+ #define REG_SYS_GPA_MFPH (SYS_BA+0x074) /*!< GPIOA High Byte Multiple Function Control Register */
+ #define REG_SYS_GPB_MFPL (SYS_BA+0x078) /*!< GPIOB Low Byte Multiple Function Control Register */
+ #define REG_SYS_GPB_MFPH (SYS_BA+0x07C) /*!< GPIOB High Byte Multiple Function Control Register */
+ #define REG_SYS_GPC_MFPL (SYS_BA+0x080) /*!< GPIOC Low Byte Multiple Function Control Register */
+ #define REG_SYS_GPC_MFPH (SYS_BA+0x084) /*!< GPIOC High Byte Multiple Function Control Register */
+ #define REG_SYS_GPD_MFPL (SYS_BA+0x088) /*!< GPIOD Low Byte Multiple Function Control Register */
+ #define REG_SYS_GPD_MFPH (SYS_BA+0x08C) /*!< GPIOD High Byte Multiple Function Control Register */
+ #define REG_SYS_GPE_MFPL (SYS_BA+0x090) /*!< GPIOE Low Byte Multiple Function Control Register */
+ #define REG_SYS_GPE_MFPH (SYS_BA+0x094) /*!< GPIOE High Byte Multiple Function Control Register */
+ #define REG_SYS_GPF_MFPL (SYS_BA+0x098) /*!< GPIOF Low Byte Multiple Function Control Register */
+ #define REG_SYS_GPF_MFPH (SYS_BA+0x09C) /*!< GPIOF High Byte Multiple Function Control Register */
+ #define REG_SYS_GPG_MFPL (SYS_BA+0x0A0) /*!< GPIOG Low Byte Multiple Function Control Register */
+ #define REG_SYS_GPG_MFPH (SYS_BA+0x0A4) /*!< GPIOG High Byte Multiple Function Control Register */
+ #define REG_SYS_GPH_MFPL (SYS_BA+0x0A8) /*!< GPIOH Low Byte Multiple Function Control Register */
+ #define REG_SYS_GPH_MFPH (SYS_BA+0x0AC) /*!< GPIOH High Byte Multiple Function Control Register */
+ #define REG_SYS_GPI_MFPL (SYS_BA+0x0B0) /*!< GPIOI Low Byte Multiple Function Control Register */
+ #define REG_SYS_GPI_MFPH (SYS_BA+0x0B4) /*!< GPIOI High Byte Multiple Function Control Register */
+ #define REG_SYS_GPJ_MFPL (SYS_BA+0x0B8) /*!< GPIOJ Low Byte Multiple Function Control Register */
+ #define REG_SYS_DDR_DSCTL (SYS_BA+0x0F0) /*!< DDR I/O Driving Strength Control Register */
+ #define REG_SYS_PORDISCR (SYS_BA+0x100) /*!< Power-On-Reset Disable Control Register */
+ #define REG_SYS_ICEDBGCR (SYS_BA+0x104) /*!< ICE Debug Interface Control Register */
+ #define REG_SYS_ERRADDCR (SYS_BA+0x108) /*!< Error Response Address Control Regsiter */
+ #define REG_SYS_REGWPCTL (SYS_BA+0x1FC) /*!< Register Write-Protection Control Register */
+
+ /**@}*/ /* end of SYS register group */
+
+ /*---------------------- System Clock Controller -------------------------*/
+ /**
+ @addtogroup CLK System Clock Controller(CLK)
+ Memory Mapped Structure for CLK Controller
+ @{ */
+
+ #define REG_CLK_PMCON (CLK_BA+0x00) /*!< Power Management Control Register */
+ #define REG_CLK_HCLKEN (CLK_BA+0x10) /*!< AHB IP Clock Enable Control Register */
+ #define REG_CLK_PCLKEN0 (CLK_BA+0x18) /*!< APB IP Clock Enable Control Register 0 */
+ #define REG_CLK_PCLKEN1 (CLK_BA+0x1C) /*!< APB IP Clock Enable Control Register 1 */
+ #define REG_CLK_DIVCTL0 (CLK_BA+0x20) /*!< Clock Divider Control Register 0 */
+ #define REG_CLK_DIVCTL1 (CLK_BA+0x24) /*!< Clock Divider Control Register 1 */
+ #define REG_CLK_DIVCTL2 (CLK_BA+0x28) /*!< Clock Divider Control Register 2 */
+ #define REG_CLK_DIVCTL3 (CLK_BA+0x2C) /*!< Clock Divider Control Register 3 */
+ #define REG_CLK_DIVCTL4 (CLK_BA+0x30) /*!< Clock Divider Control Register 4 */
+ #define REG_CLK_DIVCTL5 (CLK_BA+0x34) /*!< Clock Divider Control Register 5 */
+ #define REG_CLK_DIVCTL6 (CLK_BA+0x38) /*!< Clock Divider Control Register 6 */
+ #define REG_CLK_DIVCTL7 (CLK_BA+0x3C) /*!< Clock Divider Control Register 7 */
+ #define REG_CLK_DIVCTL8 (CLK_BA+0x40) /*!< Clock Divider Control Register 8 */
+ #define REG_CLK_DIVCTL9 (CLK_BA+0x44) /*!< Clock Divider Control Register 9 */
+ #define REG_CLK_APLLCON (CLK_BA+0x60) /*!< APLL Control Register */
+ #define REG_CLK_UPLLCON (CLK_BA+0x64) /*!< UPLL Control Register */
+ #define REG_CLK_PLLSTBCNTR (CLK_BA+0x80) /*!< PLL Stable Counter and Test Clock Control Register */
+
+ /**@}*/ /* end of CLK register group */
+
+
+ /*---------------------- External Bus Interface Controller -------------------------*/
+ /**
+ @addtogroup EBI External Bus Interface Controller(EBI)
+ Memory Mapped Structure for EBI Controller
+ @{ */
+
+ #define REG_EBI_CTL (EBI_BA+0x000) /*!< EBI control register */
+ #define REG_EBI_BNKCTL0 (EBI_BA+0x018) /*!< External I/O 0 control register */
+ #define REG_EBI_BNKCTL1 (EBI_BA+0x01C) /*!< External I/O 1 control register */
+ #define REG_EBI_BNKCTL2 (EBI_BA+0x020) /*!< External I/O 2 control register */
+ #define REG_EBI_BNKCTL3 (EBI_BA+0x024) /*!< External I/O 3 control register */
+ #define REG_EBI_BNKCTL4 (EBI_BA+0x028) /*!< External I/O 4 control register */
+
+ /**@}*/ /* end of EBI register group */
+
+
+ /*---------------------- Ethernet MAC Controller -------------------------*/
+ /**
+ @addtogroup EMAC Ethernet MAC Controller(EMAC)
+ Memory Mapped Structure for EMAC Controller
+ @{ */
+
+ #define REG_EMAC0_CAMCMR (EMC0_BA+0x000) /*!< CAM Command Register */
+ #define REG_EMAC0_CAMEN (EMC0_BA+0x004) /*!< CAM Enable Register */
+ #define REG_EMAC0_CAM0M (EMC0_BA+0x008) /*!< CAM0 Most Significant Word Register */
+ #define REG_EMAC0_CAM0L (EMC0_BA+0x00c) /*!< CAM0 Least Significant Word Register */
+ #define REG_EMAC0_CAMxM_Reg(x)(REG_EMAC0_CAM0M+(x)*0x8) /*!< CAMx Most Significant Word Register */
+ #define REG_EMAC0_CAMxL_Reg(x)(REG_EMAC0_CAM0L+(x)*0x8) /*!< CAMx Least Significant Word Register */
+ #define REG_EMAC0_TXDLSA (EMC0_BA+0x088) /*!< Transmit Descriptor Link List Start Address Register */
+ #define REG_EMAC0_RXDLSA (EMC0_BA+0x08C) /*!< Receive Descriptor Link List Start Address Register */
+ #define REG_EMAC0_MCMDR (EMC0_BA+0x090) /*!< MAC Command Register */
+ #define REG_EMAC0_MIID (EMC0_BA+0x094) /*!< MII Management Data Register */
+ #define REG_EMAC0_MIIDA (EMC0_BA+0x098) /*!< MII Management Control and Address Register */
+ #define REG_EMAC0_FFTCR (EMC0_BA+0x09C) /*!< FIFO Threshold Control Register */
+ #define REG_EMAC0_TSDR (EMC0_BA+0x0a0) /*!< Transmit Start Demand Register */
+ #define REG_EMAC0_RSDR (EMC0_BA+0x0a4) /*!< Receive Start Demand Register */
+ #define REG_EMAC0_DMARFC (EMC0_BA+0x0a8) /*!< Maximum Receive Frame Control Register */
+ #define REG_EMAC0_MIEN (EMC0_BA+0x0ac) /*!< MAC Interrupt Enable Register */
+ #define REG_EMAC0_MISTA (EMC0_BA+0x0b0) /*!< MAC Interrupt Status Register */
+ #define REG_EMAC0_MGSTA (EMC0_BA+0x0b4) /*!< MAC General Status Register */
+ #define REG_EMAC0_MPCNT (EMC0_BA+0x0b8) /*!< Missed Packet Count Register */
+ #define REG_EMAC0_MRPC (EMC0_BA+0x0bc) /*!< MAC Receive Pause Count Register */
+ #define REG_EMAC0_DMARFS (EMC0_BA+0x0c8) /*!< DMA Receive Frame Status Register */
+ #define REG_EMAC0_CTXDSA (EMC0_BA+0x0cc) /*!< Current Transmit Descriptor Start Address Register */
+ #define REG_EMAC0_CTXBSA (EMC0_BA+0x0d0) /*!< Current Transmit Buffer Start Address Register */
+ #define REG_EMAC0_CRXDSA (EMC0_BA+0x0d4) /*!< Current Receive Descriptor Start Address Register */
+ #define REG_EMAC0_CRXBSA (EMC0_BA+0x0d8) /*!< Current Receive Buffer Start Address Register */
+ #define REG_EMAC0_TSCTL (EMC0_BA+0x100) /*!< Time Stamp Control Register */
+ #define REG_EMAC0_TSSEC (EMC0_BA+0x110) /*!< Time Stamp Counter Second Register */
+ #define REG_EMAC0_TSSUBSEC (EMC0_BA+0x114) /*!< Time Stamp Counter Sub Second Register */
+ #define REG_EMAC0_TSINC (EMC0_BA+0x118) /*!< Time Stamp Increment Register */
+ #define REG_EMAC0_TSADDEN (EMC0_BA+0x11c) /*!< Time Stamp Addend Register */
+ #define REG_EMAC0_TSUPDSEC (EMC0_BA+0x120) /*!< Time Stamp Update Second Register */
+ #define REG_EMAC0_TSUPDSUBSEC (EMC0_BA+0x124) /*!< Time Stamp Update Sub Second Register */
+ #define REG_EMAC0_TSALMSEC (EMC0_BA+0x128) /*!< Time Stamp Alarm Second Register */
+ #define REG_EMAC0_TSALMSUBSEC (EMC0_BA+0x12c) /*!< Time Stamp Alarm Sub Second Register */
+
+ #define REG_EMAC1_CAMCMR (EMC1_BA+0x000) /*!< CAM Command Register */
+ #define REG_EMAC1_CAMEN (EMC1_BA+0x004) /*!< CAM Enable Register */
+ #define REG_EMAC1_CAM0M (EMC1_BA+0x008) /*!< CAM0 Most Significant Word Register */
+ #define REG_EMAC1_CAM0L (EMC1_BA+0x00c) /*!< CAM0 Least Significant Word Register */
+ #define REG_EMAC1_CAMxM_Reg(x)(REG_EMAC1_CAM0M+(x)*0x8) /*!< CAMx Most Significant Word Register */
+ #define REG_EMAC1_CAMxL_Reg(x)(REG_EMAC1_CAM0L+(x)*0x8) /*!< CAMx Least Significant Word Register */
+ #define REG_EMAC1_TXDLSA (EMC1_BA+0x088) /*!< Transmit Descriptor Link List Start Address Register */
+ #define REG_EMAC1_RXDLSA (EMC1_BA+0x08C) /*!< Receive Descriptor Link List Start Address Register */
+ #define REG_EMAC1_MCMDR (EMC1_BA+0x090) /*!< MAC Command Register */
+ #define REG_EMAC1_MIID (EMC1_BA+0x094) /*!< MII Management Data Register */
+ #define REG_EMAC1_MIIDA (EMC1_BA+0x098) /*!< MII Management Control and Address Register */
+ #define REG_EMAC1_FFTCR (EMC1_BA+0x09C) /*!< FIFO Threshold Control Register */
+ #define REG_EMAC1_TSDR (EMC1_BA+0x0a0) /*!< Transmit Start Demand Register */
+ #define REG_EMAC1_RSDR (EMC1_BA+0x0a4) /*!< Receive Start Demand Register */
+ #define REG_EMAC1_DMARFC (EMC1_BA+0x0a8) /*!< Maximum Receive Frame Control Register */
+ #define REG_EMAC1_MIEN (EMC1_BA+0x0ac) /*!< MAC Interrupt Enable Register */
+ #define REG_EMAC1_MISTA (EMC1_BA+0x0b0) /*!< MAC Interrupt Status Register */
+ #define REG_EMAC1_MGSTA (EMC1_BA+0x0b4) /*!< MAC General Status Register */
+ #define REG_EMAC1_MPCNT (EMC1_BA+0x0b8) /*!< Missed Packet Count Register */
+ #define REG_EMAC1_MRPC (EMC1_BA+0x0bc) /*!< MAC Receive Pause Count Register */
+ #define REG_EMAC1_DMARFS (EMC1_BA+0x0c8) /*!< DMA Receive Frame Status Register */
+ #define REG_EMAC1_CTXDSA (EMC1_BA+0x0cc) /*!< Current Transmit Descriptor Start Address Register */
+ #define REG_EMAC1_CTXBSA (EMC1_BA+0x0d0) /*!< Current Transmit Buffer Start Address Register */
+ #define REG_EMAC1_CRXDSA (EMC1_BA+0x0d4) /*!< Current Receive Descriptor Start Address Register */
+ #define REG_EMAC1_CRXBSA (EMC1_BA+0x0d8) /*!< Current Receive Buffer Start Address Register */
+ #define REG_EMAC1_TSCTL (EMC1_BA+0x100) /*!< Time Stamp Control Register */
+ #define REG_EMAC1_TSSEC (EMC1_BA+0x110) /*!< Time Stamp Counter Second Register */
+ #define REG_EMAC1_TSSUBSEC (EMC1_BA+0x114) /*!< Time Stamp Counter Sub Second Register */
+ #define REG_EMAC1_TSINC (EMC1_BA+0x118) /*!< Time Stamp Increment Register */
+ #define REG_EMAC1_TSADDEN (EMC1_BA+0x11c) /*!< Time Stamp Addend Register */
+ #define REG_EMAC1_TSUPDSEC (EMC1_BA+0x120) /*!< Time Stamp Update Second Register */
+ #define REG_EMAC1_TSUPDSUBSEC (EMC1_BA+0x124) /*!< Time Stamp Update Sub Second Register */
+ #define REG_EMAC1_TSALMSEC (EMC1_BA+0x128) /*!< Time Stamp Alarm Second Register */
+ #define REG_EMAC1_TSALMSUBSEC (EMC1_BA+0x12c) /*!< Time Stamp Alarm Sub Second Register */
+
+ /**@}*/ /* end of EMAC register group */
+
+ /*---------------------- General Direct Memory Access Controller -------------------------*/
+ /**
+ @addtogroup GDMA General Direct Memory Access Controller(GDMA)
+ Memory Mapped Structure for GDMA Controller
+ @{ */
+
+ #define REG_GDMA_CTL0 (GDMA_BA+0x000) /*!< Channel 0 Control Register */
+ #define REG_GDMA_SRCB0 (GDMA_BA+0x004) /*!< Channel 0 Source Base Address Register */
+ #define REG_GDMA_DSTB0 (GDMA_BA+0x008) /*!< Channel 0 Destination Base Address Register */
+ #define REG_GDMA_TCNT0 (GDMA_BA+0x00C) /*!< Channel 0 Transfer Count Register */
+ #define REG_GDMA_CSRC0 (GDMA_BA+0x010) /*!< Channel 0 Current Source Address Register */
+ #define REG_GDMA_CDST0 (GDMA_BA+0x014) /*!< Channel 0 Current Destination Address Register */
+ #define REG_GDMA_CTCNT0 (GDMA_BA+0x018) /*!< Channel 0 Current Transfer Count Register */
+ #define REG_GDMA_DADR0 (GDMA_BA+0x01C) /*!< Channel 0 Descriptor Address Register */
+ #define REG_GDMA_CTL1 (GDMA_BA+0x020) /*!< Channel 1 Control Register */
+ #define REG_GDMA_SRCB1 (GDMA_BA+0x024) /*!< Channel 1 Source Base Address Register */
+ #define REG_GDMA_DSTB1 (GDMA_BA+0x028) /*!< Channel 1 Destination Base Address Register */
+ #define REG_GDMA_TCNT1 (GDMA_BA+0x02C) /*!< Channel 1 Transfer Count Register */
+ #define REG_GDMA_CSRC1 (GDMA_BA+0x030) /*!< Channel 1 Current Source Address Register */
+ #define REG_GDMA_CDST1 (GDMA_BA+0x034) /*!< Channel 1 Current Destination Address Register */
+ #define REG_GDMA_CTCNT1 (GDMA_BA+0x038) /*!< Channel 1 Current Transfer Count Register */
+ #define REG_GDMA_DADR1 (GDMA_BA+0x03C) /*!< Channel 1 Descriptor Address Register */
+ #define REG_GDMA_INTBUF0 (GDMA_BA+0x080) /*!< GDMA Internal Buffer Word 0 */
+ #define REG_GDMA_INTBUF1 (GDMA_BA+0x084) /*!< GDMA Internal Buffer Word 1 */
+ #define REG_GDMA_INTBUF2 (GDMA_BA+0x088) /*!< GDMA Internal Buffer Word 2 */
+ #define REG_GDMA_INTBUF3 (GDMA_BA+0x08C) /*!< GDMA Internal Buffer Word 3 */
+ #define REG_GDMA_INTBUF4 (GDMA_BA+0x090) /*!< GDMA Internal Buffer Word 4 */
+ #define REG_GDMA_INTBUF5 (GDMA_BA+0x094) /*!< GDMA Internal Buffer Word 5 */
+ #define REG_GDMA_INTBUF6 (GDMA_BA+0x098) /*!< GDMA Internal Buffer Word 6 */
+ #define REG_GDMA_INTBUF7 (GDMA_BA+0x09C) /*!< GDMA Internal Buffer Word 7 */
+ #define REG_GDMA_INTCS (GDMA_BA+0x0A0) /*!< Interrupt Control and Status Register */
+
+ /**@}*/ /* end of GDMA register group */
+
+
+
+ /*---------------------- USB Device Controller -------------------------*/
+ /**
+ @addtogroup USBD USB Device Controller(USBD)
+ Memory Mapped Structure for USBD Controller
+ @{ */
+ #define REG_USBD_GINTSTS (USBD_BA+0x00) /*!< Interrupt Status Low Register */
+ #define REG_USBD_GINTEN (USBD_BA+0x08) /*!< Interrupt Enable Low Register */
+ #define REG_USBD_BUSINTSTS (USBD_BA+0x10) /*!< USB Bus Interrupt Status Register */
+ #define REG_USBD_BUSINTEN (USBD_BA+0x14) /*!< USB Bus Interrupt Enable Register */
+ #define REG_USBD_OPER (USBD_BA+0x18) /*!< USB Operational Register */
+ #define REG_USBD_FRAMECNT (USBD_BA+0x1C) /*!< USB Frame Count Register */
+ #define REG_USBD_FADDR (USBD_BA+0x20) /*!< USB Function Address Register */
+ #define REG_USBD_TEST (USBD_BA+0x24) /*!< USB Test Mode Register */
+ #define REG_USBD_CEPDAT (USBD_BA+0x28) /*!< Control-ep data buffer register */
+ #define REG_USBD_CEPCTL (USBD_BA+0x2C) /*!< Control-ep control and status register */
+ #define REG_USBD_CEPINTEN (USBD_BA+0x30) /*!< Control-ep interrupt enable register */
+ #define REG_USBD_CEPINTSTS (USBD_BA+0x34) /*!< Control-ep interrupt status register */
+ #define REG_USBD_CEPTXCNT (USBD_BA+0x38) /*!< In-transfer data count register */
+ #define REG_USBD_CEPRXCNT (USBD_BA+0x3C) /*!< Out-transfer data count register */
+ #define REG_USBD_CEPDATCNT (USBD_BA+0x40) /*!< Control-ep data count register */
+ #define REG_USBD_SETUP1_0 (USBD_BA+0x44) /*!< Setup byte1 & byte0 register */
+ #define REG_USBD_SETUP3_2 (USBD_BA+0x48) /*!< Setup byte3 & byte2 register */
+ #define REG_USBD_SETUP5_4 (USBD_BA+0x4C) /*!< Setup byte5 & byte4 register */
+ #define REG_USBD_SETUP7_6 (USBD_BA+0x50) /*!< Setup byte7 & byte6 register */
+ #define REG_USBD_CEPBUFSTART (USBD_BA+0x54) /*!< Control-ep ram start address register */
+ #define REG_USBD_CEPBUFEND (USBD_BA+0x58) /*!< Control-ep ram end address register */
+ #define REG_USBD_DMACTL (USBD_BA+0x5C) /*!< Dma control and status register */
+ #define REG_USBD_DMACNT (USBD_BA+0x60) /*!< Dma count register */
+
+ #define REG_USBD_EPADAT (USBD_BA+0x64) /*!< Endpoint A data buffer register */
+ #define REG_USBD_EPAINTSTS (USBD_BA+0x68) /*!< Endpoint A interrupt status register */
+ #define REG_USBD_EPAINTEN (USBD_BA+0x6C) /*!< Endpoint A interrupt enable register */
+ #define REG_USBD_EPADATCNT (USBD_BA+0x70) /*!< Data count available in endpoint A buffer */
+ #define REG_USBD_EPARSPCTL (USBD_BA+0x74) /*!< Endpoint A response register set/clear */
+ #define REG_USBD_EPAMPS (USBD_BA+0x78) /*!< Endpoint A max packet size register */
+ #define REG_USBD_EPATXCNT (USBD_BA+0x7C) /*!< Endpoint A transfer count register */
+ #define REG_USBD_EPACFG (USBD_BA+0x80) /*!< Endpoint A configuration register */
+ #define REG_USBD_EPABUFSTART (USBD_BA+0x84) /*!< Endpoint A ram start address register */
+ #define REG_USBD_EPABUFEND (USBD_BA+0x88) /*!< Endpoint A ram end address register */
+
+ #define REG_USBD_EPBDAT (USBD_BA+0x8C) /*!< Endpoint B data buffer register */
+ #define REG_USBD_EPBINTSTS (USBD_BA+0x90) /*!< Endpoint B interrupt status register */
+ #define REG_USBD_EPBINTEN (USBD_BA+0x94) /*!< Endpoint B interrupt enable register */
+ #define REG_USBD_EPBDATCNT (USBD_BA+0x98) /*!< Data count available in endpoint B buffer */
+ #define REG_USBD_EPBRSPCTL (USBD_BA+0x9C) /*!< Endpoint B response register set/clear */
+ #define REG_USBD_EPBMPS (USBD_BA+0xA0) /*!< Endpoint B max packet size register */
+ #define REG_USBD_EPBTXCNT (USBD_BA+0xA4) /*!< Endpoint B transfer count register */
+ #define REG_USBD_EPBCFG (USBD_BA+0xA8) /*!< Endpoint B configuration register */
+ #define REG_USBD_EPBBUFSTART (USBD_BA+0xAC) /*!< Endpoint B ram start address register */
+ #define REG_USBD_EPBBUFEND (USBD_BA+0xB0) /*!< Endpoint B ram end address register */
+
+ #define REG_USBD_EPCDAT (USBD_BA+0xB4) /*!< Endpoint C data buffer register */
+ #define REG_USBD_EPCINTSTS (USBD_BA+0xB8) /*!< Endpoint C interrupt status register */
+ #define REG_USBD_EPCINTEN (USBD_BA+0xBC) /*!< Endpoint C interrupt enable register */
+ #define REG_USBD_EPCDATCNT (USBD_BA+0xC0) /*!< Data count available in endpoint C buffer */
+ #define REG_USBD_EPCRSPCTL (USBD_BA+0xC4) /*!< Endpoint C response register set/clear */
+ #define REG_USBD_EPCMPS (USBD_BA+0xC8) /*!< Endpoint C max packet size register */
+ #define REG_USBD_EPCTXCNT (USBD_BA+0xCC) /*!< Endpoint C transfer count register */
+ #define REG_USBD_EPCCFG (USBD_BA+0xD0) /*!< Endpoint C configuration register */
+ #define REG_USBD_EPCBUFSTART (USBD_BA+0xD4) /*!< Endpoint C ram start address register */
+ #define REG_USBD_EPCBUFEND (USBD_BA+0xD8) /*!< Endpoint C ram end address register */
+
+ #define REG_USBD_EPDDAT (USBD_BA+0xDC) /*!< Endpoint D data buffer register */
+ #define REG_USBD_EPDINTSTS (USBD_BA+0xE0) /*!< Endpoint D interrupt status register */
+ #define REG_USBD_EPDINTEN (USBD_BA+0xE4) /*!< Endpoint D interrupt enable register */
+ #define REG_USBD_EPDDATCNT (USBD_BA+0xE8) /*!< Data count available in endpoint D buffer */
+ #define REG_USBD_EPDRSPCTL (USBD_BA+0xEC) /*!< Endpoint D response register set/clear */
+ #define REG_USBD_EPDMPS (USBD_BA+0xF0) /*!< Endpoint D max packet size register */
+ #define REG_USBD_EPDTXCNT (USBD_BA+0xF4) /*!< Endpoint D transfer count register */
+ #define REG_USBD_EPDCFG (USBD_BA+0xF8) /*!< Endpoint D configuration register */
+ #define REG_USBD_EPDBUFSTART (USBD_BA+0xFC) /*!< Endpoint D ram start address register */
+ #define REG_USBD_EPDBUFEND (USBD_BA+0x100) /*!< Endpoint D ram end address register */
+
+ #define REG_USBD_EPEDAT (USBD_BA+0x104) /*!< Endpoint E data buffer register */
+ #define REG_USBD_EPEINTSTS (USBD_BA+0x108) /*!< Endpoint E interrupt status register */
+ #define REG_USBD_EPEINTEN (USBD_BA+0x10C) /*!< Endpoint E interrupt enable register */
+ #define REG_USBD_EPEDATCNT (USBD_BA+0x110) /*!< Data count available in endpoint E buffer */
+ #define REG_USBD_EPERSPCTL (USBD_BA+0x114) /*!< Endpoint E response register set/clear */
+ #define REG_USBD_EPEMPS (USBD_BA+0x118) /*!< Endpoint E max packet size register */
+ #define REG_USBD_EPETXCNT (USBD_BA+0x11C) /*!< Endpoint E transfer count register */
+ #define REG_USBD_EPECFG (USBD_BA+0x120) /*!< Endpoint E configuration register */
+ #define REG_USBD_EPEBUFSTART (USBD_BA+0x124) /*!< Endpoint E ram start address register */
+ #define REG_USBD_EPEBUFEND (USBD_BA+0x128) /*!< Endpoint E ram end address register */
+
+ #define REG_USBD_EPFDAT (USBD_BA+0x12C) /*!< Endpoint F data buffer register */
+ #define REG_USBD_EPFINTSTS (USBD_BA+0x130) /*!< Endpoint F interrupt status register */
+ #define REG_USBD_EPFINTEN (USBD_BA+0x134) /*!< Endpoint F interrupt enable register */
+ #define REG_USBD_EPFDATCNT (USBD_BA+0x138) /*!< Data count available in endpoint F buffer */
+ #define REG_USBD_EPFRSPCTL (USBD_BA+0x13C) /*!< Endpoint F response register set/clear */
+ #define REG_USBD_EPFMPS (USBD_BA+0x140) /*!< Endpoint F max packet size register */
+ #define REG_USBD_EPFTXCNT (USBD_BA+0x144) /*!< Endpoint F transfer count register */
+ #define REG_USBD_EPFCFG (USBD_BA+0x148) /*!< Endpoint F configuration register */
+ #define REG_USBD_EPFBUFSTART (USBD_BA+0x14C) /*!< Endpoint F ram start address register */
+ #define REG_USBD_EPFBUFEND (USBD_BA+0x150) /*!< Endpoint F ram end address register */
+
+ #define REG_USBD_EPGDAT (USBD_BA+0x154) /*!< Endpoint G data buffer register */
+ #define REG_USBD_EPGINTSTS (USBD_BA+0x158) /*!< Endpoint G interrupt status register */
+ #define REG_USBD_EPGINTEN (USBD_BA+0x15C) /*!< Endpoint G interrupt enable register */
+ #define REG_USBD_EPGDATCNT (USBD_BA+0x160) /*!< Data count available in endpoint G buffer */
+ #define REG_USBD_EPGRSPCTL (USBD_BA+0x164) /*!< Endpoint G response register set/clear */
+ #define REG_USBD_EPGMPS (USBD_BA+0x168) /*!< Endpoint G max packet size register */
+ #define REG_USBD_EPGTXCNT (USBD_BA+0x16C) /*!< Endpoint G transfer count register */
+ #define REG_USBD_EPGCFG (USBD_BA+0x170) /*!< Endpoint G configuration register */
+ #define REG_USBD_EPGBUFSTART (USBD_BA+0x174) /*!< Endpoint G ram start address register */
+ #define REG_USBD_EPGBUFEND (USBD_BA+0x178) /*!< Endpoint G ram end address register */
+
+ #define REG_USBD_EPHDAT (USBD_BA+0x17C) /*!< Endpoint H data buffer register */
+ #define REG_USBD_EPHINTSTS (USBD_BA+0x180) /*!< Endpoint H interrupt status register */
+ #define REG_USBD_EPHINTEN (USBD_BA+0x184) /*!< Endpoint H interrupt enable register */
+ #define REG_USBD_EPHDATCNT (USBD_BA+0x188) /*!< Data count available in endpoint H buffer */
+ #define REG_USBD_EPHRSPCTL (USBD_BA+0x18C) /*!< Endpoint H response register set/clear */
+ #define REG_USBD_EPHMPS (USBD_BA+0x190) /*!< Endpoint H max packet size register */
+ #define REG_USBD_EPHTXCNT (USBD_BA+0x194) /*!< Endpoint H transfer count register */
+ #define REG_USBD_EPHCFG (USBD_BA+0x198) /*!< Endpoint H configuration register */
+ #define REG_USBD_EPHBUFSTART (USBD_BA+0x19C) /*!< Endpoint H ram start address register */
+ #define REG_USBD_EPHBUFEND (USBD_BA+0x1A0) /*!< Endpoint H ram end address register */
+
+ #define REG_USBD_EPIDAT (USBD_BA+0x1A4) /*!< Endpoint I data buffer register */
+ #define REG_USBD_EPIINTSTS (USBD_BA+0x1A8) /*!< Endpoint I interrupt status register */
+ #define REG_USBD_EPIINTEN (USBD_BA+0x1AC) /*!< Endpoint I interrupt enable register */
+ #define REG_USBD_EPIDATCNT (USBD_BA+0x1B0) /*!< Data count available in endpoint I buffer */
+ #define REG_USBD_EPIRSPCTL (USBD_BA+0x1B4) /*!< Endpoint I response register set/clear */
+ #define REG_USBD_EPIMPS (USBD_BA+0x1B8) /*!< Endpoint I max packet size register */
+ #define REG_USBD_EPITXCNT (USBD_BA+0x1BC) /*!< Endpoint I transfer count register */
+ #define REG_USBD_EPICFG (USBD_BA+0x1C0) /*!< Endpoint I configuration register */
+ #define REG_USBD_EPIBUFSTART (USBD_BA+0x1C4) /*!< Endpoint I ram start address register */
+ #define REG_USBD_EPIBUFEND (USBD_BA+0x1C8) /*!< Endpoint I ram end address register */
+
+ #define REG_USBD_EPJDAT (USBD_BA+0x1CC) /*!< Endpoint J data buffer register */
+ #define REG_USBD_EPJINTSTS (USBD_BA+0x1D0) /*!< Endpoint J interrupt status register */
+ #define REG_USBD_EPJINTEN (USBD_BA+0x1D4) /*!< Endpoint J interrupt enable register */
+ #define REG_USBD_EPJDATCNT (USBD_BA+0x1D8) /*!< Data count available in endpoint J buffer */
+ #define REG_USBD_EPJRSPCTL (USBD_BA+0x1DC) /*!< Endpoint J response register set/clear */
+ #define REG_USBD_EPJMPS (USBD_BA+0x1E0) /*!< Endpoint J max packet size register */
+ #define REG_USBD_EPJTXCNT (USBD_BA+0x1E4) /*!< Endpoint J transfer count register */
+ #define REG_USBD_EPJCFG (USBD_BA+0x1E8) /*!< Endpoint J configuration register */
+ #define REG_USBD_EPJBUFSTART (USBD_BA+0x1EC) /*!< Endpoint J ram start address register */
+ #define REG_USBD_EPJBUFEND (USBD_BA+0x1F0) /*!< Endpoint J ram end address register */
+
+ #define REG_USBD_EPKDAT (USBD_BA+0x1F4) /*!< Endpoint K data buffer register */
+ #define REG_USBD_EPKINTSTS (USBD_BA+0x1F8) /*!< Endpoint K interrupt status register */
+ #define REG_USBD_EPKINTEN (USBD_BA+0x1FC) /*!< Endpoint K interrupt enable register */
+ #define REG_USBD_EPKDATCNT (USBD_BA+0x200) /*!< Data count available in endpoint K buffer */
+ #define REG_USBD_EPKRSPCTL (USBD_BA+0x204) /*!< Endpoint K response register set/clear */
+ #define REG_USBD_EPKMPS (USBD_BA+0x208) /*!< Endpoint K max packet size register */
+ #define REG_USBD_EPKTXCNT (USBD_BA+0x20C) /*!< Endpoint K transfer count register */
+ #define REG_USBD_EPKCFG (USBD_BA+0x210) /*!< Endpoint K configuration register */
+ #define REG_USBD_EPKBUFSTART (USBD_BA+0x214) /*!< Endpoint K ram start address register */
+ #define REG_USBD_EPKBUFEND (USBD_BA+0x218) /*!< Endpoint K ram end address register */
+
+ #define REG_USBD_EPLDAT (USBD_BA+0x21C) /*!< Endpoint L data buffer register */
+ #define REG_USBD_EPLINTSTS (USBD_BA+0x220) /*!< Endpoint L interrupt status register */
+ #define REG_USBD_EPLINTEN (USBD_BA+0x224) /*!< Endpoint L interrupt enable register */
+ #define REG_USBD_EPLDATCNT (USBD_BA+0x228) /*!< Data count available in endpoint L buffer */
+ #define REG_USBD_EPLRSPCTL (USBD_BA+0x22C) /*!< Endpoint L response register set/clear */
+ #define REG_USBD_EPLMPS (USBD_BA+0x230) /*!< Endpoint L max packet size register */
+ #define REG_USBD_EPLTXCNT (USBD_BA+0x234) /*!< Endpoint L transfer count register */
+ #define REG_USBD_EPLCFG (USBD_BA+0x238) /*!< Endpoint L configuration register */
+ #define REG_USBD_EPLBUFSTART (USBD_BA+0x23C) /*!< Endpoint L ram start address register */
+ #define REG_USBD_EPLBUFEND (USBD_BA+0x240) /*!< Endpoint L ram end address register */
+ #define REG_USBD_DMAADDR (USBD_BA+0x700) /*!< AHB_DMA address register */
+ #define REG_USBD_PHYCTL (USBD_BA+0x704) /*!< USB PHY control register */
+
+ /**@}*/ /* end of USBD register group */
+
+
+ /*---------------------- LCD Display Interface Controller -------------------------*/
+ /**
+ @addtogroup LCM LCD Display Interface Controller(LCM)
+ Memory Mapped Structure for LCM Controller
+ @{ */
+
+ #define REG_LCM_DCCS (LCM_BA+0x00) /*!< Display Controller Control/Status Register */
+ #define REG_LCM_DEV_CTRL (LCM_BA+0x04) /*!< Display Output Device Control Register */
+ #define REG_LCM_MPU_CMD (LCM_BA+0x08) /*!< MPU-Interface LCD Write Command */
+ #define REG_LCM_INT_CS (LCM_BA+0x0c) /*!< Interrupt Control/Status Register */
+ #define REG_LCM_CRTC_SIZE (LCM_BA+0x10) /*!< CRTC Display Size Control Register */
+ #define REG_LCM_CRTC_DEND (LCM_BA+0x14) /*!< CRTC Display Enable End */
+ #define REG_LCM_CRTC_HR (LCM_BA+0x18) /*!< CRTC Internal Horizontal Retrace Control Register */
+ #define REG_LCM_CRTC_HSYNC (LCM_BA+0x1C) /*!< CRTC Horizontal Sync Control Register */
+ #define REG_LCM_CRTC_VR (LCM_BA+0x20) /*!< CRTC Internal Vertical Retrace Control Register */
+ #define REG_LCM_VA_BADDR0 (LCM_BA+0x24) /*!< Video Stream Frame Buffer-0 Starting Address */
+ #define REG_LCM_VA_BADDR1 (LCM_BA+0x28) /*!< Video Stream Frame Buffer-1 Starting Address */
+ #define REG_LCM_VA_FBCTRL (LCM_BA+0x2C) /*!< Video Stream Frame Buffer Control Register */
+ #define REG_LCM_VA_SCALE (LCM_BA+0x30) /*!< Video Stream Scaling Control Register */
+ #define REG_LCM_VA_WIN (LCM_BA+0x38) /*!< Image Stream Active Window Coordinates */
+ #define REG_LCM_VA_STUFF (LCM_BA+0x3C) /*!< Image Stream Stuff Pixel */
+ #define REG_LCM_OSD_WINS (LCM_BA+0x40) /*!< OSD Window Starting Coordinates */
+ #define REG_LCM_OSD_WINE (LCM_BA+0x44) /*!< OSD Window Ending Coordinates */
+ #define REG_LCM_OSD_BADDR (LCM_BA+0x48) /*!< OSD Stream Frame Buffer Starting Address */
+ #define REG_LCM_OSD_FBCTRL (LCM_BA+0x4c) /*!< OSD Stream Frame Buffer Control Register */
+ #define REG_LCM_OSD_OVERLAY (LCM_BA+0x50) /*!< OSD Overlay Control Register */
+ #define REG_LCM_OSD_CKEY (LCM_BA+0x54) /*!< OSD Overlay Color-Key Pattern Register */
+ #define REG_LCM_OSD_CMASK (LCM_BA+0x58) /*!< OSD Overlay Color-Key Mask Register */
+ #define REG_LCM_OSD_SKIP1 (LCM_BA+0x5C) /*!< OSD Window Skip1 Register */
+ #define REG_LCM_OSD_SKIP2 (LCM_BA+0x60) /*!< OSD Window Skip2 Register */
+ #define REG_LCM_OSD_SCALE (LCM_BA+0x64) /*!< OSD horizontal up scaling control register */
+ #define REG_LCM_MPU_VSYNC (LCM_BA+0x68) /*!< MPU Vsync control register */
+ #define REG_LCM_HC_CTRL (LCM_BA+0x6C) /*!< Hardware cursor control Register */
+ #define REG_LCM_HC_POS (LCM_BA+0x70) /*!< Hardware cursot tip point potison on va picture */
+ #define REG_LCM_HC_WBCTRL (LCM_BA+0x74) /*!< Hardware Cursor Window Buffer Control Register */
+ #define REG_LCM_HC_BADDR (LCM_BA+0x78) /*!< Hardware cursor memory base address register */
+ #define REG_LCM_HC_COLOR0 (LCM_BA+0x7C) /*!< Hardware cursor color ram register mapped to bpp = 0 */
+ #define REG_LCM_HC_COLOR1 (LCM_BA+0x80) /*!< Hardware cursor color ram register mapped to bpp = 1 */
+ #define REG_LCM_HC_COLOR2 (LCM_BA+0x84) /*!< Hardware cursor color ram register mapped to bpp = 2 */
+ #define REG_LCM_HC_COLOR3 (LCM_BA+0x88) /*!< Hardware cursor color ram register mapped to bpp = 3 */
+
+ /**@}*/ /* end of LCM register group */
+
+
+ /*---------------------- I2S Interface Controller -------------------------*/
+ /**
+ @addtogroup I2S I2S Interface Controller(I2S)
+ Memory Mapped Structure for I2S Controller
+ @{ */
+
+ #define REG_ACTL_CON (ACTL_BA+0x00) /*!< Audio controller control register */
+ #define REG_ACTL_RESET (ACTL_BA+0x04) /*!< Sub block reset control register */
+ #define REG_ACTL_RDESB (ACTL_BA+0x08) /*!< DMA destination base address register for record */
+ #define REG_ACTL_RDES_LENGTH (ACTL_BA+0x0C) /*!< DMA destination length register for record */
+ #define REG_ACTL_RDESC (ACTL_BA+0x10) /*!< DMA destination current address for record */
+ #define REG_ACTL_PDESB (ACTL_BA+0x14) /*!< DMA destination current address for play */
+ #define REG_ACTL_PDES_LENGTH (ACTL_BA+0x18) /*!< DMA destination length register for play */
+ #define REG_ACTL_PDESC (ACTL_BA+0x1C) /*!< DMA destination current address register for play */
+ #define REG_ACTL_RSR (ACTL_BA+0x20) /*!< Record status register */
+ #define REG_ACTL_PSR (ACTL_BA+0x24) /*!< Play status register */
+ #define REG_ACTL_I2SCON (ACTL_BA+0x28) /*!< I2S control register */
+ #define REG_ACTL_COUNTER (ACTL_BA+0x2C) /*!< DMA count down values */
+ #define REG_ACTL_PCMCON (ACTL_BA+0x30) /*!< PCM interface control register */
+ #define REG_ACTL_PCMS1ST (ACTL_BA+0x34) /*!< PCM interface slot1 start register */
+ #define REG_ACTL_PCMS2ST (ACTL_BA+0x38) /*!< PCM interface slot2 start register */
+ #define REG_ACTL_RDESB2 (ACTL_BA+0x40) /*!< DMA destination base address register for record right channel */
+ #define REG_ACTL_PDESB2 (ACTL_BA+0x44) /*!< DMA destination base address register for play right channel */
+
+ /**@}*/ /* end of I2S register group */
+
+ /*---------------------- 2D Graphic Engine -------------------------*/
+ /**
+ @addtogroup GE2D 2D Graphic Engine(GE2D)
+ Memory Mapped Structure for GE2D Controller
+ @{ */
+
+ #define REG_GE2D_TRG (GE_BA+0x00) /*!< Graphic Engine Trigger Control Register */
+ #define REG_GE2D_XYSORG (GE_BA+0x04) /*!< Graphic Engine XY Mode Source Origin Starting Register */
+ #define REG_GE2D_TCNTVHSF (GE_BA+0x08) /*!< Graphic Engine Tile Width/Height or V/H Scale Factor N/M */
+ #define REG_GE2D_XYRRP (GE_BA+0x0C) /*!< Graphic Engine Rotate Reference Point XY Address */
+ #define REG_GE2D_INTSTS (GE_BA+0x10) /*!< Graphic Engine Interrupt Status Register */
+ #define REG_GE2D_PATSA (GE_BA+0x14) /*!< Graphic Engine Pattern Location Starting Address Register */
+ #define REG_GE2D_BETSC (GE_BA+0x18) /*!< GE Bresenham Error Term Stepping Constant Register */
+ #define REG_GE2D_BIEPC (GE_BA+0x1C) /*!< GE Bresenham Initial Error, Pixel Count Major M Register */
+ #define REG_GE2D_CTL (GE_BA+0x20) /*!< Graphic Engine Control Register */
+ #define REG_GE2D_BGCOLR (GE_BA+0x24) /*!< Graphic Engine Background Color Register */
+ #define REG_GE2D_FGCOLR (GE_BA+0x28) /*!< Graphic Engine Foreground Color Register */
+ #define REG_GE2D_TRNSCOLR (GE_BA+0x2C) /*!< Graphic Engine Transparency Color Register */
+ #define REG_GE2D_TCMSK (GE_BA+0x30) /*!< Graphic Engine Transparency Color Mask Register */
+ #define REG_GE2D_XYDORG (GE_BA+0x34) /*!< Graphic Engine XY Mode Display Origin Starting Register */
+ #define REG_GE2D_SDPITCH (GE_BA+0x38) /*!< Graphic Engine Source/Destination Pitch Register */
+ #define REG_GE2D_SRCSPA (GE_BA+0x3C) /*!< Graphic Engine Source Start XY/Linear Address Register */
+ #define REG_GE2D_DSTSPA (GE_BA+0x40) /*!< Graphic Engine Destination Start XY/Linear Register */
+ #define REG_GE2D_RTGLSZ (GE_BA+0x44) /*!< Graphic Engine Dimension XY/Linear Register */
+ #define REG_GE2D_CLPBTL (GE_BA+0x48) /*!< Graphic Engine Clipping Boundary Top/Left Register */
+ #define REG_GE2D_CLPBBR (GE_BA+0x4C) /*!< Graphic Engine Clipping Boundary Bottom/Right Register */
+ #define REG_GE2D_PTNA (GE_BA+0x50) /*!< Graphic Engine Pattern A Register */
+ #define REG_GE2D_PTNB (GE_BA+0x54) /*!< Graphic Engine Pattern B Register */
+ #define REG_GE2D_WRPLNMSK (GE_BA+0x58) /*!< Graphic Engine Write Plane Mask Register */
+ #define REG_GE2D_MISCTL (GE_BA+0x5C) /*!< Graphic Engine Miscellaneous Control Register */
+ #define REG_GE2D_GEHBDW0 (GE_BA+0x60) /*!< Graphic Engine HostBLT data Port 0 Register */
+ #define REG_GE2D_GEHBDW1 (GE_BA+0x64) /*!< Graphic Engine HostBLT data Port 1 Register */
+ #define REG_GE2D_GEHBDW2 (GE_BA+0x68) /*!< Graphic Engine HostBLT data Port 2 Register */
+ #define REG_GE2D_GEHBDW3 (GE_BA+0x6C) /*!< Graphic Engine HostBLT data Port 3 Register */
+ #define REG_GE2D_GEHBDW4 (GE_BA+0x70) /*!< Graphic Engine HostBLT data Port 4 Register */
+ #define REG_GE2D_GEHBDW5 (GE_BA+0x74) /*!< Graphic Engine HostBLT data Port 5 Register */
+ #define REG_GE2D_GEHBDW6 (GE_BA+0x78) /*!< Graphic Engine HostBLT data Port 6 Register */
+ #define REG_GE2D_GEHBDW7 (GE_BA+0x7C) /*!< Graphic Engine HostBLT data Port 7 Register */
+
+ /**@}*/ /* end of GE2D register group */
+
+ /*---------------------- Flash Memory Interface -------------------------*/
+ /**
+ @addtogroup FMI Flash Memory Interface(FMI)
+ Memory Mapped Structure for FMI Controller
+ @{ */
+
+ /* DMAC Control Registers*/
+ #define REG_FMI_BUFFER (FMI_BA+0x000) /*!< FMI Embedded Buffer Word */
+ #define REG_FMI_DMACTL (FMI_BA+0x400) /*!< FMI DMA Control Register */
+ #define REG_FMI_DMASA (FMI_BA+0x408) /*!< FMI DMA Transfer Starting Address Register */
+ #define REG_FMI_DMABCNT (FMI_BA+0x40C) /*!< FMI DMA Transfer Byte Count Register */
+ #define REG_FMI_DMAINTEN (FMI_BA+0x410) /*!< FMI DMA Interrupt Enable Register */
+ #define REG_FMI_DMAINTSTS (FMI_BA+0x414) /*!< FMI DMA Interrupt Status Register */
+
+ #define REG_FMI_CTL (FMI_BA+0x800) /*!< Global Control and Status Register */
+ #define REG_FMI_INTEN (FMI_BA+0x804) /*!< Global Interrupt Control Register */
+ #define REG_FMI_INTSTS (FMI_BA+0x808) /*!< Global Interrupt Status Register */
+
+ /* eMMC Registers */
+ #define REG_FMI_EMMCCTL (FMI_BA+0x820) /*!< eMMC control and status register */
+ #define REG_FMI_EMMCCMD (FMI_BA+0x824) /*!< eMMC command argument register */
+ #define REG_FMI_EMMCINTEN (FMI_BA+0x828) /*!< eMMC interrupt enable register */
+ #define REG_FMI_EMMCINTSTS (FMI_BA+0x82C) /*!< eMMC interrupt status register */
+ #define REG_FMI_EMMCRESP0 (FMI_BA+0x830) /*!< eMMC receive response token register 0 */
+ #define REG_FMI_EMMCRESP1 (FMI_BA+0x834) /*!< eMMC receive response token register 1 */
+ #define REG_FMI_EMMCBLEN (FMI_BA+0x838) /*!< eMMC block length register */
+ #define REG_FMI_EMMCTOUT (FMI_BA+0x83C) /*!< eMMC block length register */
+
+ /* NAND-type Flash Registers */
+ #define REG_NANDCTL (FMI_BA+0x8A0) /*!< NAND Flash Control and Status Register */
+ #define REG_NANDTMCTL (FMI_BA+0x8A4) /*!< NAND Flash Timing Control Register */
+ #define REG_NANDINTEN (FMI_BA+0x8A8) /*!< NAND Flash Interrupt Control Register */
+ #define REG_NANDINTSTS (FMI_BA+0x8AC) /*!< NAND Flash Interrupt Status Register */
+ #define REG_NANDCMD (FMI_BA+0x8B0) /*!< NAND Flash Command Port Register */
+ #define REG_NANDADDR (FMI_BA+0x8B4) /*!< NAND Flash Address Port Register */
+ #define REG_NANDDATA (FMI_BA+0x8B8) /*!< NAND Flash Data Port Register */
+ #define REG_NANDRACTL (FMI_BA+0x8BC) /*!< NAND Flash Redundant Area Control Register */
+ #define REG_NANDECTL (FMI_BA+0x8C0) /*!< NAND Flash Extend Control Regsiter */
+ #define REG_NANDECCES0 (FMI_BA+0x8D0) /*!< NAND Flash ECC Error Status 0 */
+ #define REG_NANDECCES1 (FMI_BA+0x8D4) /*!< NAND Flash ECC Error Status 1 */
+ #define REG_NANDECCES2 (FMI_BA+0x8D8) /*!< NAND Flash ECC Error Status 2 */
+ #define REG_NANDECCES3 (FMI_BA+0x8DC) /*!< NAND Flash ECC Error Status 3 */
+ #define REG_NANDPROTA0 (FMI_BA+0x8E0) /*!< NAND Flash Protect Region End Address 0 */
+ #define REG_NANDPROTA1 (FMI_BA+0x8E4) /*!< NAND Flash Protect Region End Address 1 */
+
+ /* NAND-type Flash BCH Error Address Registers */
+ #define REG_NANDECCEA0 (FMI_BA+0x900) /*!< NAND Flash ECC Error Byte Address 0 */
+ #define REG_NANDECCEA1 (FMI_BA+0x904) /*!< NAND Flash ECC Error Byte Address 1 */
+ #define REG_NANDECCEA2 (FMI_BA+0x908) /*!< NAND Flash ECC Error Byte Address 2 */
+ #define REG_NANDECCEA3 (FMI_BA+0x90C) /*!< NAND Flash ECC Error Byte Address 3 */
+ #define REG_NANDECCEA4 (FMI_BA+0x910) /*!< NAND Flash ECC Error Byte Address 4 */
+ #define REG_NANDECCEA5 (FMI_BA+0x914) /*!< NAND Flash ECC Error Byte Address 5 */
+ #define REG_NANDECCEA6 (FMI_BA+0x918) /*!< NAND Flash ECC Error Byte Address 6 */
+ #define REG_NANDECCEA7 (FMI_BA+0x91C) /*!< NAND Flash ECC Error Byte Address 7 */
+ #define REG_NANDECCEA8 (FMI_BA+0x920) /*!< NAND Flash ECC Error Byte Address 8 */
+ #define REG_NANDECCEA9 (FMI_BA+0x924) /*!< NAND Flash ECC Error Byte Address 9 */
+ #define REG_NANDECCEA10 (FMI_BA+0x928) /*!< NAND Flash ECC Error Byte Address 10 */
+ #define REG_NANDECCEA11 (FMI_BA+0x92C) /*!< NAND Flash ECC Error Byte Address 11 */
+
+ /* NAND-type Flash BCH Error Data Registers */
+ #define REG_NANDECCED0 (FMI_BA+0x960) /*!< NAND Flash ECC Error Data Register 0 */
+ #define REG_NANDECCED1 (FMI_BA+0x964) /*!< NAND Flash ECC Error Data Register 1 */
+ #define REG_NANDECCED2 (FMI_BA+0x968) /*!< NAND Flash ECC Error Data Register 2 */
+ #define REG_NANDECCED3 (FMI_BA+0x96C) /*!< NAND Flash ECC Error Data Register 3 */
+ #define REG_NANDECCED4 (FMI_BA+0x970) /*!< NAND Flash ECC Error Data Register 4 */
+ #define REG_NANDECCED5 (FMI_BA+0x974) /*!< NAND Flash ECC Error Data Register 5 */
+
+ /* NAND-type Flash Redundant Area Registers */
+ #define REG_NANDRA0 (FMI_BA+0xA00) /*!< NAND Flash Redundant Area Register */
+ #define REG_NANDRA1 (FMI_BA+0xA04) /*!< NAND Flash Redundant Area Register */
+
+ /**@}*/ /* end of FMI register group */
+
+
+ /*---------------------- SD/SDIO Host Controller -------------------------*/
+ /**
+ @addtogroup SDH SD/SDIO Host Controller(SDH)
+ Memory Mapped Structure for SDH Controller
+ @{ */
+
+ /* DMAC Control Registers*/
+ #define REG_SDH_FB0 (SDH_BA+0x000) /*!< SD Host Embedded Buffer Word */
+ #define REG_SDH_DMACTL (SDH_BA+0x400) /*!< SD Host DMA Control and Status Register */
+ #define REG_SDH_DMASA (SDH_BA+0x408) /*!< SD Host DMA Transfer Starting Address Register */
+ #define REG_SDH_DMABCNT (SDH_BA+0x40C) /*!< SD Host DMA Transfer Byte Count Register */
+ #define REG_SDH_DMAINTEN (SDH_BA+0x410) /*!< SD Host DMA Interrupt Enable Register */
+ #define REG_SDH_DMAINTSTS (SDH_BA+0x414) /*!< SD Host DMA Interrupt Status Register */
+
+ #define REG_SDH_GCTL (SDH_BA+0x800) /*!< SD Host Global Control and Status Register */
+ #define REG_SDH_GINTEN (SDH_BA+0x804) /*!< SD Host Global Interrupt Control Register */
+ #define REG_SDH_GINTSTS (SDH_BA+0x808) /*!< SD Host Global Interrupt Status Register */
+
+ /* Secure Digit Registers */
+ #define REG_SDH_CTL (SDH_BA+0x820) /*!< SD Host control and status register */
+ #define REG_SDH_CMD (SDH_BA+0x824) /*!< SD Host command argument register */
+ #define REG_SDH_INTEN (SDH_BA+0x828) /*!< SD Host interrupt enable register */
+ #define REG_SDH_INTSTS (SDH_BA+0x82C) /*!< SD Host interrupt status register */
+ #define REG_SDH_RESP0 (SDH_BA+0x830) /*!< SD Host receive response token register 0 */
+ #define REG_SDH_RESP1 (SDH_BA+0x834) /*!< SD Host receive response token register 1 */
+ #define REG_SDH_BLEN (SDH_BA+0x838) /*!< SD Host block length register */
+ #define REG_SDH_TMOUT (SDH_BA+0x83C) /*!< SD Host Response/Data-in Time-out register */
+ #define REG_SDH_ECTL (SDH_BA+0x840) /*!< SD Host Extend Control Register */
+
+ /**@}*/ /* end of SDH register group */
+
+
+ /*---------------------- Cryptographic Accelerator -------------------------*/
+ /**
+ @addtogroup CRYPTO Cryptographic Accelerator(CRYPTO)
+ Memory Mapped Structure for Cryptographic Accelerator registers
+ @{ */
+
+ /* Crypto Control Registers */
+ #define CRPT_INTEN (CRPT_BA+0x000) /*!< Crypto Interrupt Enable Control Register */
+ #define CRPT_INTSTS (CRPT_BA+0x004) /*!< Crypto Interrupt Flag */
+
+ /* PRNG Registers */
+ #define CRPT_PRNG_CTL (CRPT_BA+0x008) /*!< PRNG Control Register */
+ #define CRPT_PRNG_SEED (CRPT_BA+0x00C) /*!< Seed for PRNG */
+ #define CRPT_PRNG_KEY0 (CRPT_BA+0x010) /*!< PRNG Generated Key 0 */
+ #define CRPT_PRNG_KEY1 (CRPT_BA+0x014) /*!< PRNG Generated Key 1 */
+ #define CRPT_PRNG_KEY2 (CRPT_BA+0x018) /*!< PRNG Generated Key 2 */
+ #define CRPT_PRNG_KEY3 (CRPT_BA+0x01C) /*!< PRNG Generated Key 3 */
+ #define CRPT_PRNG_KEY4 (CRPT_BA+0x020) /*!< PRNG Generated Key 4 */
+ #define CRPT_PRNG_KEY5 (CRPT_BA+0x024) /*!< PRNG Generated Key 5 */
+ #define CRPT_PRNG_KEY6 (CRPT_BA+0x028) /*!< PRNG Generated Key 6 */
+ #define CRPT_PRNG_KEY7 (CRPT_BA+0x02C) /*!< PRNG Generated Key 7 */
+
+ /* AES/TDES feedback Registers */
+ #define CRPT_AES_FDBCK0 (CRPT_BA+0x050) /*!< AES Engine Output Feedback Data after Cryptographic Operation */
+ #define CRPT_AES_FDBCK1 (CRPT_BA+0x054) /*!< AES Engine Output Feedback Data after Cryptographic Operation */
+ #define CRPT_AES_FDBCK2 (CRPT_BA+0x058) /*!< AES Engine Output Feedback Data after Cryptographic Operation */
+ #define CRPT_AES_FDBCK3 (CRPT_BA+0x05C) /*!< AES Engine Output Feedback Data after Cryptographic Operation */
+ #define CRPT_TDES_FDBCKH (CRPT_BA+0x060) /*!< TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation */
+ #define CRPT_TDES_FDBCKL (CRPT_BA+0x064) /*!< TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation */
+
+ /* AES Control Registers */
+ #define CRPT_AES_CTL (CRPT_BA+0x100) /*!< AES Control Register */
+ #define CRPT_AES_STS (CRPT_BA+0x104) /*!< AES Engine Flag */
+ #define CRPT_AES_DATIN (CRPT_BA+0x108) /*!< AES Engine Data Input Port Register */
+ #define CRPT_AES_DATOUT (CRPT_BA+0x10C) /*!< AES Engine Data Output Port Register */
+ #define CRPT_AES0_KEY0 (CRPT_BA+0x110) /*!< AES Key Word 0 Register for Channel 0 */
+ #define CRPT_AES0_KEY1 (CRPT_BA+0x114) /*!< AES Key Word 1 Register for Channel 0 */
+ #define CRPT_AES0_KEY2 (CRPT_BA+0x118) /*!< AES Key Word 2 Register for Channel 0 */
+ #define CRPT_AES0_KEY3 (CRPT_BA+0x11C) /*!< AES Key Word 3 Register for Channel 0 */
+ #define CRPT_AES0_KEY4 (CRPT_BA+0x120) /*!< AES Key Word 4 Register for Channel 0 */
+ #define CRPT_AES0_KEY5 (CRPT_BA+0x124) /*!< AES Key Word 5 Register for Channel 0 */
+ #define CRPT_AES0_KEY6 (CRPT_BA+0x128) /*!< AES Key Word 6 Register for Channel 0 */
+ #define CRPT_AES0_KEY7 (CRPT_BA+0x12C) /*!< AES Key Word 7 Register for Channel 0 */
+ #define CRPT_AES0_IV0 (CRPT_BA+0x130) /*!< AES Initial Vector Word 0 Register for Channel 0 */
+ #define CRPT_AES0_IV1 (CRPT_BA+0x134) /*!< AES Initial Vector Word 1 Register for Channel 0 */
+ #define CRPT_AES0_IV2 (CRPT_BA+0x138) /*!< AES Initial Vector Word 2 Register for Channel 0 */
+ #define CRPT_AES0_IV3 (CRPT_BA+0x13C) /*!< AES Initial Vector Word 3 Register for Channel 0 */
+ #define CRPT_AES0_SADDR (CRPT_BA+0x140) /*!< AES DMA Source Address Register for Channel 0 */
+ #define CRPT_AES0_DADDR (CRPT_BA+0x144) /*!< AES DMA Destination Address Register for Channel 0 */
+ #define CRPT_AES0_CNT (CRPT_BA+0x148) /*!< AES Byte Count Register for Channel 0 */
+ #define CRPT_AES1_KEY0 (CRPT_BA+0x14C) /*!< AES Key Word 0 Register for Channel 1 */
+ #define CRPT_AES1_KEY1 (CRPT_BA+0x150) /*!< AES Key Word 1 Register for Channel 1 */
+ #define CRPT_AES1_KEY2 (CRPT_BA+0x154) /*!< AES Key Word 2 Register for Channel 1 */
+ #define CRPT_AES1_KEY3 (CRPT_BA+0x158) /*!< AES Key Word 3 Register for Channel 1 */
+ #define CRPT_AES1_KEY4 (CRPT_BA+0x15C) /*!< AES Key Word 4 Register for Channel 1 */
+ #define CRPT_AES1_KEY5 (CRPT_BA+0x160) /*!< AES Key Word 5 Register for Channel 1 */
+ #define CRPT_AES1_KEY6 (CRPT_BA+0x164) /*!< AES Key Word 6 Register for Channel 1 */
+ #define CRPT_AES1_KEY7 (CRPT_BA+0x168) /*!< AES Key Word 7 Register for Channel 1 */
+ #define CRPT_AES1_IV0 (CRPT_BA+0x16C) /*!< AES Initial Vector Word 0 Register for Channel 1 */
+ #define CRPT_AES1_IV1 (CRPT_BA+0x170) /*!< AES Initial Vector Word 1 Register for Channel 1 */
+ #define CRPT_AES1_IV2 (CRPT_BA+0x174) /*!< AES Initial Vector Word 2 Register for Channel 1 */
+ #define CRPT_AES1_IV3 (CRPT_BA+0x178) /*!< AES Initial Vector Word 3 Register for Channel 1 */
+ #define CRPT_AES1_SADDR (CRPT_BA+0x17C) /*!< AES DMA Source Address Register for Channel 1 */
+ #define CRPT_AES1_DADDR (CRPT_BA+0x180) /*!< AES DMA Destination Address Register for Channel 1 */
+ #define CRPT_AES1_CNT (CRPT_BA+0x184) /*!< AES Byte Count Register for Channel 1 */
+ #define CRPT_AES2_KEY0 (CRPT_BA+0x188) /*!< AES Key Word 0 Register for Channel 2 */
+ #define CRPT_AES2_KEY1 (CRPT_BA+0x18C) /*!< AES Key Word 1 Register for Channel 2 */
+ #define CRPT_AES2_KEY2 (CRPT_BA+0x190) /*!< AES Key Word 2 Register for Channel 2 */
+ #define CRPT_AES2_KEY3 (CRPT_BA+0x194) /*!< AES Key Word 3 Register for Channel 2 */
+ #define CRPT_AES2_KEY4 (CRPT_BA+0x198) /*!< AES Key Word 4 Register for Channel 2 */
+ #define CRPT_AES2_KEY5 (CRPT_BA+0x19C) /*!< AES Key Word 5 Register for Channel 2 */
+ #define CRPT_AES2_KEY6 (CRPT_BA+0x1A0) /*!< AES Key Word 6 Register for Channel 2 */
+ #define CRPT_AES2_KEY7 (CRPT_BA+0x1A4) /*!< AES Key Word 7 Register for Channel 2 */
+ #define CRPT_AES2_IV0 (CRPT_BA+0x1A8) /*!< AES Initial Vector Word 0 Register for Channel 2 */
+ #define CRPT_AES2_IV1 (CRPT_BA+0x1AC) /*!< AES Initial Vector Word 1 Register for Channel 2 */
+ #define CRPT_AES2_IV2 (CRPT_BA+0x1B0) /*!< AES Initial Vector Word 2 Register for Channel 2 */
+ #define CRPT_AES2_IV3 (CRPT_BA+0x1B4) /*!< AES Initial Vector Word 3 Register for Channel 2 */
+ #define CRPT_AES2_SADDR (CRPT_BA+0x1B8) /*!< AES DMA Source Address Register for Channel 2 */
+ #define CRPT_AES2_DADDR (CRPT_BA+0x1BC) /*!< AES DMA Destination Address Register for Channel 2 */
+ #define CRPT_AES2_CNT (CRPT_BA+0x1C0) /*!< AES Byte Count Register for Channel 2 */
+ #define CRPT_AES3_KEY0 (CRPT_BA+0x1C4) /*!< AES Key Word 0 Register for Channel 3 */
+ #define CRPT_AES3_KEY1 (CRPT_BA+0x1C8) /*!< AES Key Word 1 Register for Channel 3 */
+ #define CRPT_AES3_KEY2 (CRPT_BA+0x1CC) /*!< AES Key Word 2 Register for Channel 3 */
+ #define CRPT_AES3_KEY3 (CRPT_BA+0x1D0) /*!< AES Key Word 3 Register for Channel 3 */
+ #define CRPT_AES3_KEY4 (CRPT_BA+0x1D4) /*!< AES Key Word 4 Register for Channel 3 */
+ #define CRPT_AES3_KEY5 (CRPT_BA+0x1D8) /*!< AES Key Word 5 Register for Channel 3 */
+ #define CRPT_AES3_KEY6 (CRPT_BA+0x1DC) /*!< AES Key Word 6 Register for Channel 3 */
+ #define CRPT_AES3_KEY7 (CRPT_BA+0x1E0) /*!< AES Key Word 7 Register for Channel 3 */
+ #define CRPT_AES3_IV0 (CRPT_BA+0x1E4) /*!< AES Initial Vector Word 0 Register for Channel 3 */
+ #define CRPT_AES3_IV1 (CRPT_BA+0x1E8) /*!< AES Initial Vector Word 1 Register for Channel 3 */
+ #define CRPT_AES3_IV2 (CRPT_BA+0x1EC) /*!< AES Initial Vector Word 2 Register for Channel 3 */
+ #define CRPT_AES3_IV3 (CRPT_BA+0x1F0) /*!< AES Initial Vector Word 3 Register for Channel 3 */
+ #define CRPT_AES3_SADDR (CRPT_BA+0x1F4) /*!< AES DMA Source Address Register for Channel 3 */
+ #define CRPT_AES3_DADDR (CRPT_BA+0x1F8) /*!< AES DMA Destination Address Register for Channel 3 */
+ #define CRPT_AES3_CNT (CRPT_BA+0x1FC) /*!< AES Byte Count Register for Channel 3 */
+
+ /* DES/TDES Control Registers */
+ #define CRPT_TDES_CTL (CRPT_BA+0x200) /*!< TDES/DES Control Register */
+ #define CRPT_TDES_STS (CRPT_BA+0x204) /*!< TDES/DES Engine Flag */
+ #define CRPT_TDES0_KEY1H (CRPT_BA+0x208) /*!< TDES/DES Key 1 High Word Register for Channel 0 */
+ #define CRPT_TDES0_KEY1L (CRPT_BA+0x20C) /*!< TDES/DES Key 1 Low Word Register for Channel 0 */
+ #define CRPT_TDES0_KEY2H (CRPT_BA+0x210) /*!< TDES/DES Key 2 High Word Register for Channel 0 */
+ #define CRPT_TDES0_KEY2L (CRPT_BA+0x214) /*!< TDES/DES Key 2 Low Word Register for Channel 0 */
+ #define CRPT_TDES0_KEY3H (CRPT_BA+0x218) /*!< TDES/DES Key 3 High Word Register for Channel 0 */
+ #define CRPT_TDES0_KEY3L (CRPT_BA+0x21C) /*!< TDES/DES Key 3 Low Word Register for Channel 0 */
+ #define CRPT_TDES0_IVH (CRPT_BA+0x220) /*!< TDES/DES Initial Vector High Word Register for Channel 0 */
+ #define CRPT_TDES0_IVL (CRPT_BA+0x224) /*!< TDES/DES Initial Vector Low Word Register for Channel 0 */
+ #define CRPT_TDES0_SADDR (CRPT_BA+0x228) /*!< TDES/DES DMA Source Address Register for Channel 0 */
+ #define CRPT_TDES0_DADDR (CRPT_BA+0x22C) /*!< TDES/DES DMA Destination Address Register for Channel 0 */
+ #define CRPT_TDES0_CNT (CRPT_BA+0x230) /*!< TDES/DES Byte Count Register for Channel 0 */
+ #define CRPT_TDES_DATIN (CRPT_BA+0x234) /*!< TDES/DES Engine Input data Word Register */
+ #define CRPT_TDES_DATOUT (CRPT_BA+0x238) /*!< TDES/DES Engine Output data Word Register */
+ #define CRPT_TDES1_KEY1H (CRPT_BA+0x248) /*!< TDES/DES Key 1 High Word Register for Channel 1 */
+ #define CRPT_TDES1_KEY1L (CRPT_BA+0x24C) /*!< TDES/DES Key 1 Low Word Register for Channel 1 */
+ #define CRPT_TDES1_KEY2H (CRPT_BA+0x250) /*!< TDES/DES Key 2 High Word Register for Channel 1 */
+ #define CRPT_TDES1_KEY2L (CRPT_BA+0x254) /*!< TDES/DES Key 2 Low Word Register for Channel 1 */
+ #define CRPT_TDES1_KEY3H (CRPT_BA+0x258) /*!< TDES/DES Key 3 High Word Register for Channel 1 */
+ #define CRPT_TDES1_KEY3L (CRPT_BA+0x25C) /*!< TDES/DES Key 3 Low Word Register for Channel 1 */
+ #define CRPT_TDES1_IVH (CRPT_BA+0x260) /*!< TDES/DES Initial Vector High Word Register for Channel 1 */
+ #define CRPT_TDES1_IVL (CRPT_BA+0x264) /*!< TDES/DES Initial Vector Low Word Register for Channel 1 */
+ #define CRPT_TDES1_SADDR (CRPT_BA+0x268) /*!< TDES/DES DMA Source Address Register for Channel 1 */
+ #define CRPT_TDES1_DADDR (CRPT_BA+0x26C) /*!< TDES/DES DMA Destination Address Register for Channel 1 */
+ #define CRPT_TDES1_CNT (CRPT_BA+0x270) /*!< TDES/DES Byte Count Register for Channel 1 */
+ #define CRPT_TDES2_KEY1H (CRPT_BA+0x288) /*!< TDES/DES Key 1 High Word Register for Channel 2 */
+ #define CRPT_TDES2_KEY1L (CRPT_BA+0x28C) /*!< TDES/DES Key 1 Low Word Register for Channel 2 */
+ #define CRPT_TDES2_KEY2H (CRPT_BA+0x290) /*!< TDES/DES Key 2 High Word Register for Channel 2 */
+ #define CRPT_TDES2_KEY2L (CRPT_BA+0x294) /*!< TDES/DES Key 2 Low Word Register for Channel 2 */
+ #define CRPT_TDES2_KEY3H (CRPT_BA+0x298) /*!< TDES/DES Key 3 High Word Register for Channel 2 */
+ #define CRPT_TDES2_KEY3L (CRPT_BA+0x29C) /*!< TDES/DES Key 3 Low Word Register for Channel 2 */
+ #define CRPT_TDES2_IVH (CRPT_BA+0x2A0) /*!< TDES/DES Initial Vector High Word Register for Channel 2 */
+ #define CRPT_TDES2_IVL (CRPT_BA+0x2A4) /*!< TDES/DES Initial Vector Low Word Register for Channel 2 */
+ #define CRPT_TDES2_SADDR (CRPT_BA+0x2A8) /*!< TDES/DES DMA Source Address Register for Channel 2 */
+ #define CRPT_TDES2_DADDR (CRPT_BA+0x2AC) /*!< TDES/DES DMA Destination Address Register for Channel 2 */
+ #define CRPT_TDES2_CNT (CRPT_BA+0x2B0) /*!< TDES/DES Byte Count Register for Channel 3 */
+ #define CRPT_TDES3_KEY1H (CRPT_BA+0x2C8) /*!< TDES/DES Key 1 High Word Register for Channel 3 */
+ #define CRPT_TDES3_KEY1L (CRPT_BA+0x2CC) /*!< TDES/DES Key 1 Low Word Register for Channel 3 */
+ #define CRPT_TDES3_KEY2H (CRPT_BA+0x2D0) /*!< TDES/DES Key 2 High Word Register for Channel 3 */
+ #define CRPT_TDES3_KEY2L (CRPT_BA+0x2D4) /*!< TDES/DES Key 2 Low Word Register for Channel 3 */
+ #define CRPT_TDES3_KEY3H (CRPT_BA+0x2D8) /*!< TDES/DES Key 3 High Word Register for Channel 3 */
+ #define CRPT_TDES3_KEY3L (CRPT_BA+0x2DC) /*!< TDES/DES Key 3 Low Word Register for Channel 3 */
+ #define CRPT_TDES3_IVH (CRPT_BA+0x2E0) /*!< TDES/DES Initial Vector High Word Register for Channel 3 */
+ #define CRPT_TDES3_IVL (CRPT_BA+0x2E4) /*!< TDES/DES Initial Vector Low Word Register for Channel 3 */
+ #define CRPT_TDES3_SADDR (CRPT_BA+0x2E8) /*!< TDES/DES DMA Source Address Register for Channel 3 */
+ #define CRPT_TDES3_DADDR (CRPT_BA+0x2EC) /*!< TDES/DES DMA Destination Address Register for Channel 3 */
+ #define CRPT_TDES3_CNT (CRPT_BA+0x2F0) /*!< TDES/DES Byte Count Register for Channel 3 */
+
+ /* SHA/HMAC Control Registers */
+ #define CRPT_HMAC_CTL (CRPT_BA+0x300) /*!< SHA/HMAC Control Register */
+ #define CRPT_HMAC_STS (CRPT_BA+0x304) /*!< SHA/HMAC Status Flag */
+ #define CRPT_HMAC_DGST0 (CRPT_BA+0x308) /*!< SHA/HMAC Digest Message 0 */
+ #define CRPT_HMAC_DGST1 (CRPT_BA+0x30C) /*!< SHA/HMAC Digest Message 1 */
+ #define CRPT_HMAC_DGST2 (CRPT_BA+0x310) /*!< SHA/HMAC Digest Message 2 */
+ #define CRPT_HMAC_DGST3 (CRPT_BA+0x314) /*!< SHA/HMAC Digest Message 3 */
+ #define CRPT_HMAC_DGST4 (CRPT_BA+0x318) /*!< SHA/HMAC Digest Message 4 */
+ #define CRPT_HMAC_DGST5 (CRPT_BA+0x31C) /*!< SHA/HMAC Digest Message 5 */
+ #define CRPT_HMAC_DGST6 (CRPT_BA+0x320) /*!< SHA/HMAC Digest Message 6 */
+ #define CRPT_HMAC_DGST7 (CRPT_BA+0x324) /*!< SHA/HMAC Digest Message 7 */
+ #define CRPT_HMAC_DGST8 (CRPT_BA+0x328) /*!< SHA/HMAC Digest Message 8 */
+ #define CRPT_HMAC_DGST9 (CRPT_BA+0x32C) /*!< SHA/HMAC Digest Message 8 */
+ #define CRPT_HMAC_DGST10 (CRPT_BA+0x330) /*!< SHA/HMAC Digest Message 10 */
+ #define CRPT_HMAC_DGST11 (CRPT_BA+0x334) /*!< SHA/HMAC Digest Message 11 */
+ #define CRPT_HMAC_DGST12 (CRPT_BA+0x338) /*!< SHA/HMAC Digest Message 12 */
+ #define CRPT_HMAC_DGST13 (CRPT_BA+0x33C) /*!< SHA/HMAC Digest Message 13 */
+ #define CRPT_HMAC_DGST14 (CRPT_BA+0x340) /*!< SHA/HMAC Digest Message 14 */
+ #define CRPT_HMAC_DGST15 (CRPT_BA+0x344) /*!< SHA/HMAC Digest Message 15 */
+ #define CRPT_HMAC_KEYCNT (CRPT_BA+0x348) /*!< SHA/HMAC Key Byte Count */
+ #define CRPT_HMAC_SADDR (CRPT_BA+0x34C) /*!< SHA/HMAC Key Byte Count */
+ #define CRPT_HMAC_DMACNT (CRPT_BA+0x350) /*!< SHA/HMAC Byte Count Register */
+ #define CRPT_HMAC_DATIN (CRPT_BA+0x354) /*!< SHA/HMAC Engine Non-DMA Mode Data Input Port Register */
+
+ /**@}*/ /* end of Cryptographic Accelerator register group */
+
+
+
+
+ /*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
+ /**
+ @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
+ Memory Mapped Structure for UART Controller
+ @{ */
+
+ #define REG_UART0_RBR (UART0_BA+0x00) /*!< Receive Buffer Register */
+ #define REG_UART0_THR (UART0_BA+0x00) /*!< Transmit Holding Register */
+ #define REG_UART0_IER (UART0_BA+0x04) /*!< Interrupt Enable Register */
+ #define REG_UART0_FCR (UART0_BA+0x08) /*!< FIFO Control Register */
+ #define REG_UART0_LCR (UART0_BA+0x0C) /*!< Line Control Register */
+ #define REG_UART0_MCR (UART0_BA+0x10) /*!< Modem Control Register */
+ #define REG_UART0_MSR (UART0_BA+0x14) /*!< MODEM Status Register */
+ #define REG_UART0_FSR (UART0_BA+0x18) /*!< FIFO Status Register */
+ #define REG_UART0_ISR (UART0_BA+0x1C) /*!< Interrupt Status Control Register */
+ #define REG_UART0_TOR (UART0_BA+0x20) /*!< Time-out Register */
+ #define REG_UART0_BAUD (UART0_BA+0x24) /*!< Baud Rate Divider Register */
+ #define REG_UART0_IRCR (UART0_BA+0x28) /*!< IrDA Control Register */
+ #define REG_UART0_ALT_CSR (UART0_BA+0x2C) /*!< Alternate Control Register */
+ #define REG_UART0_FUN_SEL (UART0_BA+0x30) /*!< UART Function Select REgister */
+ #define REG_UART0_LIN_CTL (UART0_BA+0x34) /*!< UART LIN Control Register */
+ #define REG_UART0_LIN_SR (UART0_BA+0x38) /*!< LIN Status Register */
+
+
+
+
+ /*
+ UART1 Control Registers
+ */
+ #define REG_UART1_RBR (UART1_BA+0x00) /*!< Receive Buffer Register */
+ #define REG_UART1_THR (UART1_BA+0x00) /*!< Transmit Holding Register */
+ #define REG_UART1_IER (UART1_BA+0x04) /*!< Interrupt Enable Register */
+ #define REG_UART1_FCR (UART1_BA+0x08) /*!< FIFO Control Register */
+ #define REG_UART1_LCR (UART1_BA+0x0C) /*!< Line Control Register */
+ #define REG_UART1_MCR (UART1_BA+0x10) /*!< Modem Control Register */
+ #define REG_UART1_MSR (UART1_BA+0x14) /*!< MODEM Status Register */
+ #define REG_UART1_FSR (UART1_BA+0x18) /*!< FIFO Status Register */
+ #define REG_UART1_ISR (UART1_BA+0x1C) /*!< Interrupt Status Control Register */
+ #define REG_UART1_TOR (UART1_BA+0x20) /*!< Time-out Register */
+ #define REG_UART1_BAUD (UART1_BA+0x24) /*!< Baud Rate Divider Register */
+ #define REG_UART1_IRCR (UART1_BA+0x28) /*!< IrDA Control Register */
+ #define REG_UART1_ALT_CSR (UART1_BA+0x2C) /*!< Alternate Control Register */
+ #define REG_UART1_FUN_SEL (UART1_BA+0x30) /*!< UART Function Select REgister */
+ #define REG_UART1_LIN_CTL (UART1_BA+0x34) /*!< UART LIN Control Register */
+ #define REG_UART1_LIN_SR (UART1_BA+0x38) /*!< LIN Status Register */
+
+ /*
+ UART2 Control Registers
+ */
+ #define REG_UART2_RBR (UART2_BA+0x00) /*!< Receive Buffer Register */
+ #define REG_UART2_THR (UART2_BA+0x00) /*!< Transmit Holding Register */
+ #define REG_UART2_IER (UART2_BA+0x04) /*!< Interrupt Enable Register */
+ #define REG_UART2_FCR (UART2_BA+0x08) /*!< FIFO Control Register */
+ #define REG_UART2_LCR (UART2_BA+0x0C) /*!< Line Control Register */
+ #define REG_UART2_MCR (UART2_BA+0x10) /*!< Modem Control Register */
+ #define REG_UART2_MSR (UART2_BA+0x14) /*!< MODEM Status Register */
+ #define REG_UART2_FSR (UART2_BA+0x18) /*!< FIFO Status Register */
+ #define REG_UART2_ISR (UART2_BA+0x1C) /*!< Interrupt Status Control Register */
+ #define REG_UART2_TOR (UART2_BA+0x20) /*!< Time-out Register */
+ #define REG_UART2_BAUD (UART2_BA+0x24) /*!< Baud Rate Divider Register */
+ #define REG_UART2_IRCR (UART2_BA+0x28) /*!< IrDA Control Register */
+ #define REG_UART2_ALT_CSR (UART2_BA+0x2C) /*!< Alternate Control Register */
+ #define REG_UART2_FUN_SEL (UART2_BA+0x30) /*!< UART Function Select REgister */
+ #define REG_UART2_LIN_CTL (UART2_BA+0x34) /*!< UART LIN Control Register */
+ #define REG_UART2_LIN_SR (UART2_BA+0x38) /*!< LIN Status Register */
+
+ /*
+ UART3 Control Registers
+ */
+ #define REG_UART3_RBR (UART3_BA+0x00) /*!< Receive Buffer Register */
+ #define REG_UART3_THR (UART3_BA+0x00) /*!< Transmit Holding Register */
+ #define REG_UART3_IER (UART3_BA+0x04) /*!< Interrupt Enable Register */
+ #define REG_UART3_FCR (UART3_BA+0x08) /*!< FIFO Control Register */
+ #define REG_UART3_LCR (UART3_BA+0x0C) /*!< Line Control Register */
+ #define REG_UART3_MCR (UART3_BA+0x10) /*!< Modem Control Register */
+ #define REG_UART3_MSR (UART3_BA+0x14) /*!< MODEM Status Register */
+ #define REG_UART3_FSR (UART3_BA+0x18) /*!< FIFO Status Register */
+ #define REG_UART3_ISR (UART3_BA+0x1C) /*!< Interrupt Status Control Register */
+ #define REG_UART3_TOR (UART3_BA+0x20) /*!< Time-out Register */
+ #define REG_UART3_BAUD (UART3_BA+0x24) /*!< Baud Rate Divider Register */
+ #define REG_UART3_IRCR (UART3_BA+0x28) /*!< IrDA Control Register */
+ #define REG_UART3_ALT_CSR (UART3_BA+0x2C) /*!< Alternate Control Register */
+ #define REG_UART3_FUN_SEL (UART3_BA+0x30) /*!< UART Function Select REgister */
+ #define REG_UART3_LIN_CTL (UART3_BA+0x34) /*!< UART LIN Control Register */
+ #define REG_UART3_LIN_SR (UART3_BA+0x38) /*!< LIN Status Register */
+
+
+ /*
+ UART4 Control Registers
+ */
+ #define REG_UART4_RBR (UART4_BA+0x00) /*!< Receive Buffer Register */
+ #define REG_UART4_THR (UART4_BA+0x00) /*!< Transmit Holding Register */
+ #define REG_UART4_IER (UART4_BA+0x04) /*!< Interrupt Enable Register */
+ #define REG_UART4_FCR (UART4_BA+0x08) /*!< FIFO Control Register */
+ #define REG_UART4_LCR (UART4_BA+0x0C) /*!< Line Control Register */
+ #define REG_UART4_MCR (UART4_BA+0x10) /*!< Modem Control Register */
+ #define REG_UART4_MSR (UART4_BA+0x14) /*!< MODEM Status Register */
+ #define REG_UART4_FSR (UART4_BA+0x18) /*!< FIFO Status Register */
+ #define REG_UART4_ISR (UART4_BA+0x1C) /*!< Interrupt Status Control Register */
+ #define REG_UART4_TOR (UART4_BA+0x20) /*!< Time-out Register */
+ #define REG_UART4_BAUD (UART4_BA+0x24) /*!< Baud Rate Divider Register */
+ #define REG_UART4_IRCR (UART4_BA+0x28) /*!< IrDA Control Register */
+ #define REG_UART4_ALT_CSR (UART4_BA+0x2C) /*!< Alternate Control Register */
+ #define REG_UART4_FUN_SEL (UART4_BA+0x30) /*!< UART Function Select REgister */
+ #define REG_UART4_LIN_CTL (UART4_BA+0x34) /*!< UART LIN Control Register */
+ #define REG_UART4_LIN_SR (UART4_BA+0x38) /*!< LIN Status Register */
+
+ /*
+ UART5 Control Registers
+ */
+ #define REG_UART5_RBR (UART5_BA+0x00) /*!< Receive Buffer Register */
+ #define REG_UART5_THR (UART5_BA+0x00) /*!< Transmit Holding Register */
+ #define REG_UART5_IER (UART5_BA+0x04) /*!< Interrupt Enable Register */
+ #define REG_UART5_FCR (UART5_BA+0x08) /*!< FIFO Control Register */
+ #define REG_UART5_LCR (UART5_BA+0x0C) /*!< Line Control Register */
+ #define REG_UART5_MCR (UART5_BA+0x10) /*!< Modem Control Register */
+ #define REG_UART5_MSR (UART5_BA+0x14) /*!< MODEM Status Register */
+ #define REG_UART5_FSR (UART5_BA+0x18) /*!< FIFO Status Register */
+ #define REG_UART5_ISR (UART5_BA+0x1C) /*!< Interrupt Status Control Register */
+ #define REG_UART5_TOR (UART5_BA+0x20) /*!< Time-out Register */
+ #define REG_UART5_BAUD (UART5_BA+0x24) /*!< Baud Rate Divider Register */
+ #define REG_UART5_IRCR (UART5_BA+0x28) /*!< IrDA Control Register */
+ #define REG_UART5_ALT_CSR (UART5_BA+0x2C) /*!< Alternate Control Register */
+ #define REG_UART5_FUN_SEL (UART5_BA+0x30) /*!< UART Function Select REgister */
+ #define REG_UART5_LIN_CTL (UART5_BA+0x34) /*!< UART LIN Control Register */
+ #define REG_UART5_LIN_SR (UART5_BA+0x38) /*!< LIN Status Register */
+
+ /*
+ UART6 Control Registers
+ */
+ #define REG_UART6_RBR (UART6_BA+0x00) /*!< Receive Buffer Register */
+ #define REG_UART6_THR (UART6_BA+0x00) /*!< Transmit Holding Register */
+ #define REG_UART6_IER (UART6_BA+0x04) /*!< Interrupt Enable Register */
+ #define REG_UART6_FCR (UART6_BA+0x08) /*!< FIFO Control Register */
+ #define REG_UART6_LCR (UART6_BA+0x0C) /*!< Line Control Register */
+ #define REG_UART6_MCR (UART6_BA+0x10) /*!< Modem Control Register */
+ #define REG_UART6_MSR (UART6_BA+0x14) /*!< MODEM Status Register */
+ #define REG_UART6_FSR (UART6_BA+0x18) /*!< FIFO Status Register */
+ #define REG_UART6_ISR (UART6_BA+0x1C) /*!< Interrupt Status Control Register */
+ #define REG_UART6_TOR (UART6_BA+0x20) /*!< Time-out Register */
+ #define REG_UART6_BAUD (UART6_BA+0x24) /*!< Baud Rate Divider Register */
+ #define REG_UART6_IRCR (UART6_BA+0x28) /*!< IrDA Control Register */
+ #define REG_UART6_ALT_CSR (UART6_BA+0x2C) /*!< Alternate Control Register */
+ #define REG_UART6_FUN_SEL (UART6_BA+0x30) /*!< UART Function Select REgister */
+ #define REG_UART6_LIN_CTL (UART6_BA+0x34) /*!< UART LIN Control Register */
+ #define REG_UART6_LIN_SR (UART6_BA+0x38) /*!< LIN Status Register */
+
+ /*
+ UART7 Control Registers
+ */
+ #define REG_UART7_RBR (UART7_BA+0x00) /*!< Receive Buffer Register */
+ #define REG_UART7_THR (UART7_BA+0x00) /*!< Transmit Holding Register */
+ #define REG_UART7_IER (UART7_BA+0x04) /*!< Interrupt Enable Register */
+ #define REG_UART7_FCR (UART7_BA+0x08) /*!< FIFO Control Register */
+ #define REG_UART7_LCR (UART7_BA+0x0C) /*!< Line Control Register */
+ #define REG_UART7_MCR (UART7_BA+0x10) /*!< Modem Control Register */
+ #define REG_UART7_MSR (UART7_BA+0x14) /*!< MODEM Status Register */
+ #define REG_UART7_FSR (UART7_BA+0x18) /*!< FIFO Status Register */
+ #define REG_UART7_ISR (UART7_BA+0x1C) /*!< Interrupt Status Control Register */
+ #define REG_UART7_TOR (UART7_BA+0x20) /*!< Time-out Register */
+ #define REG_UART7_BAUD (UART7_BA+0x24) /*!< Baud Rate Divider Register */
+ #define REG_UART7_IRCR (UART7_BA+0x28) /*!< IrDA Control Register */
+ #define REG_UART7_ALT_CSR (UART7_BA+0x2C) /*!< Alternate Control Register */
+ #define REG_UART7_FUN_SEL (UART7_BA+0x30) /*!< UART Function Select REgister */
+ #define REG_UART7_LIN_CTL (UART7_BA+0x34) /*!< UART LIN Control Register */
+ #define REG_UART7_LIN_SR (UART7_BA+0x38) /*!< LIN Status Register */
+
+ /*
+ UART8 Control Registers
+ */
+ #define REG_UART8_RBR (UART8_BA+0x00) /*!< Receive Buffer Register */
+ #define REG_UART8_THR (UART8_BA+0x00) /*!< Transmit Holding Register */
+ #define REG_UART8_IER (UART8_BA+0x04) /*!< Interrupt Enable Register */
+ #define REG_UART8_FCR (UART8_BA+0x08) /*!< FIFO Control Register */
+ #define REG_UART8_LCR (UART8_BA+0x0C) /*!< Line Control Register */
+ #define REG_UART8_MCR (UART8_BA+0x10) /*!< Modem Control Register */
+ #define REG_UART8_MSR (UART8_BA+0x14) /*!< MODEM Status Register */
+ #define REG_UART8_FSR (UART8_BA+0x18) /*!< FIFO Status Register */
+ #define REG_UART8_ISR (UART8_BA+0x1C) /*!< Interrupt Status Control Register */
+ #define REG_UART8_TOR (UART8_BA+0x20) /*!< Time-out Register */
+ #define REG_UART8_BAUD (UART8_BA+0x24) /*!< Baud Rate Divider Register */
+ #define REG_UART8_IRCR (UART8_BA+0x28) /*!< IrDA Control Register */
+ #define REG_UART8_ALT_CSR (UART8_BA+0x2C) /*!< Alternate Control Register */
+ #define REG_UART8_FUN_SEL (UART8_BA+0x30) /*!< UART Function Select REgister */
+ #define REG_UART8_LIN_CTL (UART8_BA+0x34) /*!< UART LIN Control Register */
+ #define REG_UART8_LIN_SR (UART8_BA+0x38) /*!< LIN Status Register */
+
+ /*
+ UART9 Control Registers
+ */
+ #define REG_UART9_RBR (UART9_BA+0x00) /*!< Receive Buffer Register */
+ #define REG_UART9_THR (UART9_BA+0x00) /*!< Transmit Holding Register */
+ #define REG_UART9_IER (UART9_BA+0x04) /*!< Interrupt Enable Register */
+ #define REG_UART9_FCR (UART9_BA+0x08) /*!< FIFO Control Register */
+ #define REG_UART9_LCR (UART9_BA+0x0C) /*!< Line Control Register */
+ #define REG_UART9_MCR (UART9_BA+0x10) /*!< Modem Control Register */
+ #define REG_UART9_MSR (UART9_BA+0x14) /*!< MODEM Status Register */
+ #define REG_UART9_FSR (UART9_BA+0x18) /*!< FIFO Status Register */
+ #define REG_UART9_ISR (UART9_BA+0x1C) /*!< Interrupt Status Control Register */
+ #define REG_UART9_TOR (UART9_BA+0x20) /*!< Time-out Register */
+ #define REG_UART9_BAUD (UART9_BA+0x24) /*!< Baud Rate Divider Register */
+ #define REG_UART9_IRCR (UART9_BA+0x28) /*!< IrDA Control Register */
+ #define REG_UART9_ALT_CSR (UART9_BA+0x2C) /*!< Alternate Control Register */
+ #define REG_UART9_FUN_SEL (UART9_BA+0x30) /*!< UART Function Select REgister */
+ #define REG_UART9_LIN_CTL (UART9_BA+0x34) /*!< UART LIN Control Register */
+ #define REG_UART9_LIN_SR (UART9_BA+0x38) /*!< LIN Status Register */
+
+ /*
+ UARTA Control Registers
+ */
+ #define REG_UARTA_RBR (UARTA_BA+0x00) /*!< Receive Buffer Register */
+ #define REG_UARTA_THR (UARTA_BA+0x00) /*!< Transmit Holding Register */
+ #define REG_UARTA_IER (UARTA_BA+0x04) /*!< Interrupt Enable Register */
+ #define REG_UARTA_FCR (UARTA_BA+0x08) /*!< FIFO Control Register */
+ #define REG_UARTA_LCR (UARTA_BA+0x0C) /*!< Line Control Register */
+ #define REG_UARTA_MCR (UARTA_BA+0x10) /*!< Modem Control Register */
+ #define REG_UARTA_MSR (UARTA_BA+0x14) /*!< MODEM Status Register */
+ #define REG_UARTA_FSR (UARTA_BA+0x18) /*!< FIFO Status Register */
+ #define REG_UARTA_ISR (UARTA_BA+0x1C) /*!< Interrupt Status Control Register */
+ #define REG_UARTA_TOR (UARTA_BA+0x20) /*!< Time-out Register */
+ #define REG_UARTA_BAUD (UARTA_BA+0x24) /*!< Baud Rate Divider Register */
+ #define REG_UARTA_IRCR (UARTA_BA+0x28) /*!< IrDA Control Register */
+ #define REG_UARTA_ALT_CSR (UARTA_BA+0x2C) /*!< Alternate Control Register */
+ #define REG_UARTA_FUN_SEL (UARTA_BA+0x30) /*!< UART Function Select REgister */
+ #define REG_UARTA_LIN_CTL (UARTA_BA+0x34) /*!< UART LIN Control Register */
+ #define REG_UARTA_LIN_SR (UARTA_BA+0x38) /*!< LIN Status Register */
+
+
+ /**@}*/ /* end of UART register group */
+
+
+ /*---------------------- Timer Controller -------------------------*/
+ /**
+ @addtogroup TIMER Timer Controller(TIMER)
+ Memory Mapped Structure for TIMER Controller
+ @{ */
+
+ #define REG_TMR0_CSR (TMR0_BA+0x00) /*!< Timer Control and Status Register 0 */
+ #define REG_TMR0_CMPR (TMR0_BA+0x04) /*!< Timer Compare Register 0 */
+ #define REG_TMR0_DR (TMR0_BA+0x08) /*!< Timer Data Register 0 */
+
+ #define REG_TMR1_CSR (TMR1_BA+0x00) /*!< Timer Control and Status Register 1 */
+ #define REG_TMR1_CMPR (TMR1_BA+0x04) /*!< Timer Compare Register 1 */
+ #define REG_TMR1_TDR (TMR1_BA+0x08) /*!< Timer Data Register 1 */
+
+ #define REG_TMR2_CSR (TMR2_BA+0x00) /*!< Timer Control and Status Register 2 */
+ #define REG_TMR2_CMPR (TMR2_BA+0x04) /*!< Timer Compare Register 2 */
+ #define REG_TMR2_DR (TMR2_BA+0x08) /*!< Timer Data Register 2 */
+
+ #define REG_TMR3_CSR (TMR3_BA+0x00) /*!< Timer Control and Status Register 3 */
+ #define REG_TMR3_CMPR (TMR3_BA+0x04) /*!< Timer Compare Register 3 */
+ #define REG_TMR3_DR (TMR3_BA+0x08) /*!< Timer Data Register 3 */
+
+ #define REG_TMR4_CSR (TMR4_BA+0x00) /*!< Timer Control and Status Register 4 */
+ #define REG_TMR4_CMPR (TMR4_BA+0x04) /*!< Timer Compare Register 4 */
+ #define REG_TMR4_DR (TMR4_BA+0x08) /*!< Timer Data Register 4 */
+
+ #define REG_TMR_ISR (TMR0_BA+0x60) /*!< Timer Interrupt Status Register */
+
+ /**@}*/ /* end of TIMER register group */
+
+ /*---------------------- Enhance Timer Controller -------------------------*/
+ /**
+ @addtogroup ETIMER Enhance Timer Controller(ETIMER)
+ Memory Mapped Structure for TIMER Controller
+ @{ */
+
+ #define REG_ETMR0_CTL (ETMR0_BA+0x00) /*!< Enhance Timer 0 Control Register */
+ #define REG_ETMR0_PRECNT (ETMR0_BA+0x04) /*!< Enhance Timer 0 Pre-Scale Counter Register */
+ #define REG_ETMR0_CMPR (ETMR0_BA+0x08) /*!< Enhance Timer 0 Compare Register */
+ #define REG_ETMR0_IER (ETMR0_BA+0x0C) /*!< Enhance Timer 0 Interrupt Enable Register */
+ #define REG_ETMR0_ISR (ETMR0_BA+0x10) /*!< Enhance Timer 0 Interrupt Status Register */
+ #define REG_ETMR0_DR (ETMR0_BA+0x14) /*!< Enhance Timer 0 Data Register */
+ #define REG_ETMR0_TCAP (ETMR0_BA+0x18) /*!< Enhance Timer 0 Capture Data Register */
+
+ #define REG_ETMR1_CTL (ETMR1_BA+0x00) /*!< Enhance Timer 1 Control Register */
+ #define REG_ETMR1_PRECNT (ETMR1_BA+0x04) /*!< Enhance Timer 1 Pre-Scale Counter Register */
+ #define REG_ETMR1_CMPR (ETMR1_BA+0x08) /*!< Enhance Timer 1 Compare Register */
+ #define REG_ETMR1_IER (ETMR1_BA+0x0C) /*!< Enhance Timer 1 Interrupt Enable Register */
+ #define REG_ETMR1_ISR (ETMR1_BA+0x10) /*!< Enhance Timer 1 Interrupt Status Register */
+ #define REG_ETMR1_DR (ETMR1_BA+0x14) /*!< Enhance Timer 1 Data Register */
+ #define REG_ETMR1_TCAP (ETMR1_BA+0x18) /*!< Enhance Timer 1 Capture Data Register */
+
+ #define REG_ETMR2_CTL (ETMR2_BA+0x00) /*!< Enhance Timer 2 Control Register */
+ #define REG_ETMR2_PRECNT (ETMR2_BA+0x04) /*!< Enhance Timer 2 Pre-Scale Counter Register */
+ #define REG_ETMR2_CMPR (ETMR2_BA+0x08) /*!< Enhance Timer 2 Compare Register */
+ #define REG_ETMR2_IER (ETMR2_BA+0x0C) /*!< Enhance Timer 2 Interrupt Enable Register */
+ #define REG_ETMR2_ISR (ETMR2_BA+0x10) /*!< Enhance Timer 2 Interrupt Status Register */
+ #define REG_ETMR2_DR (ETMR2_BA+0x14) /*!< Enhance Timer 2 Data Register */
+ #define REG_ETMR2_TCAP (ETMR2_BA+0x18) /*!< Enhance Timer 2 Capture Data Register */
+
+ #define REG_ETMR3_CTL (ETMR3_BA+0x00) /*!< Enhance Timer 3 Control Register */
+ #define REG_ETMR3_PRECNT (ETMR3_BA+0x04) /*!< Enhance Timer 3 Pre-Scale Counter Register */
+ #define REG_ETMR3_CMPR (ETMR3_BA+0x08) /*!< Enhance Timer 3 Compare Register */
+ #define REG_ETMR3_IER (ETMR3_BA+0x0C) /*!< Enhance Timer 3 Interrupt Enable Register */
+ #define REG_ETMR3_ISR (ETMR3_BA+0x10) /*!< Enhance Timer 3 Interrupt Status Register */
+ #define REG_ETMR3_DR (ETMR3_BA+0x14) /*!< Enhance Timer 3 Data Register */
+ #define REG_ETMR3_TCAP (ETMR3_BA+0x18) /*!< Enhance Timer 3 Capture Data Register */
+ /**@}*/ /* end of ETIMER register group */
+
+ /*---------------------- WDT Controller -------------------------*/
+ /**
+ @addtogroup WDT Watch Dog Timer Controller(WDT)
+ Memory Mapped Structure for WDT Controller
+ @{ */
+
+ #define REG_WDT_CTL (WDT_BA+0x00) /*!< WDT Control Register */
+ #define REG_WDT_ALTCTL (WDT_BA+0x04) /*!< WDT Alternative Control Register */
+
+ /**@}*/ /* end of WDT register group */
+
+ /*---------------------- WWDT Controller -------------------------*/
+ /**
+ @addtogroup WWDT Window Watch Dog Timer Controller(WWDT)
+ Memory Mapped Structure for WWDT Controller
+ @{ */
+
+ #define REG_WWDT_RLDCNT (WWDT_BA+0x00) /*!< WWDT Reload Counter Register */
+ #define REG_WWDT_CTL (WWDT_BA+0x04) /*!< WWDT Control Register */
+ #define REG_WWDT_STATUS (WWDT_BA+0x08) /*!< WWDT Status Register */
+ #define REG_WWDT_CNT (WWDT_BA+0x0C) /*!< WWDT Counter Value Register */
+
+ /**@}*/ /* end of WWDT register group */
+
+ /*---------------------- SC Host Interface -------------------------*/
+ /**
+ @addtogroup SC Smart Card Host Interface (SC)
+ Memory Mapped Structure for Smart Card Host Interface
+ @{ */
+
+ #define REG_SC0_DAT (SC0_BA+0x00) /*!< SC0 Receiving/Transmit Holding Buffer Register */
+ #define REG_SC0_CTL (SC0_BA+0x04) /*!< SC0 Control Register */
+ #define REG_SC0_ALTCTL (SC0_BA+0x08) /*!< SC0 Alternate Control Register */
+ #define REG_SC0_EGT (SC0_BA+0x0C) /*!< SC0 Extend Guard Time Register */
+ #define REG_SC0_RXTOUT (SC0_BA+0x10) /*!< SC0 Receive Buffer Time-out Register */
+ #define REG_SC0_ETUCTL (SC0_BA+0x14) /*!< SC0 ETU Control Register */
+ #define REG_SC0_INTEN (SC0_BA+0x18) /*!< SC0 Interrupt Enable Control Register */
+ #define REG_SC0_INTSTS (SC0_BA+0x1C) /*!< SC0 Interrupt Status Register */
+ #define REG_SC0_STATUS (SC0_BA+0x20) /*!< SC0 Status Register */
+ #define REG_SC0_PINCTL (SC0_BA+0x24) /*!< SC0 Pin Control State Register */
+ #define REG_SC0_TMRCTL0 (SC0_BA+0x28) /*!< SC0 Internal Timer Control Register 0 */
+ #define REG_SC0_TMRCTL1 (SC0_BA+0x2C) /*!< SC0 Internal Timer Control Register 1 */
+ #define REG_SC0_TMRCTL2 (SC0_BA+0x30) /*!< SC0 Internal Timer Control Register 2 */
+ #define REG_SC0_UARTCTL (SC0_BA+0x34) /*!< SC0 UART Mode Control Register */
+ #define REG_SC0_TMRDAT0 (SC0_BA+0x38) /*!< SC0 Timer Current Data Register 0 */
+ #define REG_SC0_TMRDAT1 (SC0_BA+0x3C) /*!< SC0 Timer Current Data Register 1 */
+
+ #define REG_SC1_DAT (SC1_BA+0x00) /*!< SC1 Receiving/Transmit Holding Buffer Register */
+ #define REG_SC1_CTL (SC1_BA+0x04) /*!< SC1 Control Register */
+ #define REG_SC1_ALTCTL (SC1_BA+0x08) /*!< SC1 Alternate Control Register */
+ #define REG_SC1_EGT (SC1_BA+0x0C) /*!< SC1 Extend Guard Time Register */
+ #define REG_SC1_RXTOUT (SC1_BA+0x10) /*!< SC1 Receive Buffer Time-out Register */
+ #define REG_SC1_ETUCTL (SC1_BA+0x14) /*!< SC1 ETU Control Register */
+ #define REG_SC1_INTEN (SC1_BA+0x18) /*!< SC1 Interrupt Enable Control Register */
+ #define REG_SC1_INTSTS (SC1_BA+0x1C) /*!< SC1 Interrupt Status Register */
+ #define REG_SC1_STATUS (SC1_BA+0x20) /*!< SC1 Status Register */
+ #define REG_SC1_PINCTL (SC1_BA+0x24) /*!< SC1 Pin Control State Register */
+ #define REG_SC1_TMRCTL0 (SC1_BA+0x28) /*!< SC1 Internal Timer Control Register 0 */
+ #define REG_SC1_TMRCTL1 (SC1_BA+0x2C) /*!< SC1 Internal Timer Control Register 1 */
+ #define REG_SC1_TMRCTL2 (SC1_BA+0x30) /*!< SC1 Internal Timer Control Register 2 */
+ #define REG_SC1_UARTCTL (SC1_BA+0x34) /*!< SC1 UART Mode Control Register */
+ #define REG_SC1_TMRDAT0 (SC1_BA+0x38) /*!< SC1 Timer Current Data Register 0 */
+ #define REG_SC1_TMRDAT1 (SC1_BA+0x3C) /*!< SC1 Timer Current Data Register 1 */
+
+ /**@}*/ /* end of SC register group */
+
+
+ /*---------------------- Advance Interrupt Controller -------------------------*/
+ /**
+ @addtogroup AIC Advance Interrupt Controller(AIC)
+ Memory Mapped Structure for AIC Controller
+ @{ */
+
+ #define REG_AIC_SCR1 (AIC_BA+0x00) /*!< Source control register 1 */
+ #define REG_AIC_SCR2 (AIC_BA+0x04) /*!< Source control register 2 */
+ #define REG_AIC_SCR3 (AIC_BA+0x08) /*!< Source control register 3 */
+ #define REG_AIC_SCR4 (AIC_BA+0x0C) /*!< Source control register 4 */
+ #define REG_AIC_SCR5 (AIC_BA+0x10) /*!< Source control register 5 */
+ #define REG_AIC_SCR6 (AIC_BA+0x14) /*!< Source control register 6 */
+ #define REG_AIC_SCR7 (AIC_BA+0x18) /*!< Source control register 7 */
+ #define REG_AIC_SCR8 (AIC_BA+0x1C) /*!< Source control register 8 */
+ #define REG_AIC_SCR9 (AIC_BA+0x20) /*!< Source control register 9 */
+ #define REG_AIC_SCR10 (AIC_BA+0x24) /*!< Source control register 10 */
+ #define REG_AIC_SCR11 (AIC_BA+0x28) /*!< Source control register 11 */
+ #define REG_AIC_SCR12 (AIC_BA+0x2C) /*!< Source control register 12 */
+ #define REG_AIC_SCR13 (AIC_BA+0x30) /*!< Source control register 13 */
+ #define REG_AIC_SCR14 (AIC_BA+0x34) /*!< Source control register 14 */
+ #define REG_AIC_SCR15 (AIC_BA+0x38) /*!< Source control register 15 */
+ #define REG_AIC_SCR16 (AIC_BA+0x3C) /*!< Source control register 16 */
+ #define REG_AIC_IRSR (AIC_BA+0x100) /*!< Interrupt raw status register */
+ #define REG_AIC_IRSRH (AIC_BA+0x104) /*!< Interrupt raw status register (Hign) */
+ #define REG_AIC_IASR (AIC_BA+0x108) /*!< Interrupt active status register */
+ #define REG_AIC_IASRH (AIC_BA+0x10C) /*!< Interrupt active status register (Hign) */
+ #define REG_AIC_ISR (AIC_BA+0x110) /*!< Interrupt status register */
+ #define REG_AIC_ISRH (AIC_BA+0x114) /*!< Interrupt status register (High) */
+ #define REG_AIC_IPER (AIC_BA+0x118) /*!< Interrupt priority encoding register */
+ #define REG_AIC_ISNR (AIC_BA+0x120) /*!< Interrupt source number register */
+ #define REG_AIC_OISR (AIC_BA+0x124) /*!< Output interrupt status register */
+ #define REG_AIC_IMR (AIC_BA+0x128) /*!< Interrupt mask register */
+ #define REG_AIC_IMRH (AIC_BA+0x12C) /*!< Interrupt mask register (High) */
+ #define REG_AIC_MECR (AIC_BA+0x130) /*!< Mask enable command register */
+ #define REG_AIC_MECRH (AIC_BA+0x134) /*!< Mask enable command register (High) */
+ #define REG_AIC_MDCR (AIC_BA+0x138) /*!< Mask disable command register */
+ #define REG_AIC_MDCRH (AIC_BA+0x13C) /*!< Mask disable command register (High) */
+ #define REG_AIC_SSCR (AIC_BA+0x140) /*!< Source Set Command Register */
+ #define REG_AIC_SSCRH (AIC_BA+0x144) /*!< Source Set Command Register (High) */
+ #define REG_AIC_SCCR (AIC_BA+0x148) /*!< Source Clear Command Register */
+ #define REG_AIC_SCCRH (AIC_BA+0x14C) /*!< Source Clear Command Register (High) */
+ #define REG_AIC_EOSCR (AIC_BA+0x150) /*!< End of service command register */
+
+ /**@}*/ /* end of AIC register group */
+
+
+ /*---------------------- General Purpose Input/Output Controller -------------------------*/
+ /**
+ @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
+ Memory Mapped Structure for GPIO Controller
+ @{ */
+
+ #define REG_GPIOA_DIR (GPIO_BA+0x000) /*!< GPIO portA direction control register */
+ #define REG_GPIOA_DATAOUT (GPIO_BA+0x004) /*!< GPIO portA data output register */
+ #define REG_GPIOA_DATAIN (GPIO_BA+0x008) /*!< GPIO portA data input register */
+ #define REG_GPIOA_IMD (GPIO_BA+0x00C) /*!< GPIO Port A Interrupt Mode Register */
+ #define REG_GPIOA_IREN (GPIO_BA+0x010) /*!< GPIO Port A Interrupt Rising-Edge or Level-High Enable Register */
+ #define REG_GPIOA_IFEN (GPIO_BA+0x014) /*!< GPIO Port A Interrupt Falling-Edge or Level-Low Enable Register */
+ #define REG_GPIOA_ISR (GPIO_BA+0x018) /*!< GPIO Port A Interrupt Status Register */
+ #define REG_GPIOA_DBEN (GPIO_BA+0x01C) /*!< GPIO Port A De-bounce Enable Register */
+ #define REG_GPIOA_PUEN (GPIO_BA+0x020) /*!< GPIO Port A Pull-Up Enable Register */
+ #define REG_GPIOA_PDEN (GPIO_BA+0x024) /*!< GPIO Port A Pull-Down Enable Register */
+ #define REG_GPIOA_ICEN (GPIO_BA+0x028) /*!< GPIO Port A CMOS Input Enable Register */
+ #define REG_GPIOA_ISEN (GPIO_BA+0x02C) /*!< GPIO Port A Schmitt-Trigger Input Enable Register */
+
+ #define REG_GPIOB_DIR (GPIO_BA+0x040) /*!< GPIO port B direction control register */
+ #define REG_GPIOB_DATAOUT (GPIO_BA+0x044) /*!< GPIO port B data output register */
+ #define REG_GPIOB_DATAIN (GPIO_BA+0x048) /*!< GPIO port B data input register */
+ #define REG_GPIOB_IMD (GPIO_BA+0x04C) /*!< GPIO Port B Interrupt Mode Register */
+ #define REG_GPIOB_IREN (GPIO_BA+0x050) /*!< GPIO Port B Interrupt Rising-Edge or Level-High Enable Register */
+ #define REG_GPIOB_IFEN (GPIO_BA+0x054) /*!< GPIO Port B Interrupt Falling-Edge or Level-Low Enable Register */
+ #define REG_GPIOB_ISR (GPIO_BA+0x058) /*!< GPIO Port B Interrupt Status Register */
+ #define REG_GPIOB_DBEN (GPIO_BA+0x05C) /*!< GPIO Port B De-bounce Enable Register */
+ #define REG_GPIOB_PUEN (GPIO_BA+0x060) /*!< GPIO Port B Pull-Up Enable Register */
+ #define REG_GPIOB_PDEN (GPIO_BA+0x064) /*!< GPIO Port B Pull-Down Enable Register */
+ #define REG_GPIOB_ICEN (GPIO_BA+0x068) /*!< GPIO Port B CMOS Input Enable Register */
+ #define REG_GPIOB_ISEN (GPIO_BA+0x06C) /*!< GPIO Port B Schmitt-Trigger Input Enable Register */
+
+ #define REG_GPIOC_DIR (GPIO_BA+0x080) /*!< GPIO port C direction control register */
+ #define REG_GPIOC_DATAOUT (GPIO_BA+0x084) /*!< GPIO port C data output register */
+ #define REG_GPIOC_DATAIN (GPIO_BA+0x088) /*!< GPIO port C data input register */
+ #define REG_GPIOC_IMD (GPIO_BA+0x08C) /*!< GPIO Port C Interrupt Mode Register */
+ #define REG_GPIOC_IREN (GPIO_BA+0x090) /*!< GPIO Port C Interrupt Rising-Edge or Level-High Enable Register */
+ #define REG_GPIOC_IFEN (GPIO_BA+0x094) /*!< GPIO Port C Interrupt Falling-Edge or Level-Low Enable Register */
+ #define REG_GPIOC_ISR (GPIO_BA+0x098) /*!< GPIO Port C Interrupt Status Register */
+ #define REG_GPIOC_DBEN (GPIO_BA+0x09C) /*!< GPIO Port C De-bounce Enable Register */
+ #define REG_GPIOC_PUEN (GPIO_BA+0x0A0) /*!< GPIO Port C Pull-Up Enable Register */
+ #define REG_GPIOC_PDEN (GPIO_BA+0x0A4) /*!< GPIO Port C Pull-Down Enable Register */
+ #define REG_GPIOC_ICEN (GPIO_BA+0x0A8) /*!< GPIO Port C CMOS Input Enable Register */
+ #define REG_GPIOC_ISEN (GPIO_BA+0x0AC) /*!< GPIO Port C Schmitt-Trigger Input Enable Register */
+
+ #define REG_GPIOD_DIR (GPIO_BA+0x0C0) /*!< GPIO port D direction control register */
+ #define REG_GPIOD_DATAOUT (GPIO_BA+0x0C4) /*!< GPIO port D data output register */
+ #define REG_GPIOD_DATAIN (GPIO_BA+0x0C8) /*!< GPIO port D data input register */
+ #define REG_GPIOD_IMD (GPIO_BA+0x0CC) /*!< GPIO Port D Interrupt Mode Register */
+ #define REG_GPIOD_IREN (GPIO_BA+0x0D0) /*!< GPIO Port D Interrupt Rising-Edge or Level-High Enable Register */
+ #define REG_GPIOD_IFEN (GPIO_BA+0x0D4) /*!< GPIO Port D Interrupt Falling-Edge or Level-Low Enable Register */
+ #define REG_GPIOD_ISR (GPIO_BA+0x0D8) /*!< GPIO Port D Interrupt Status Register */
+ #define REG_GPIOD_DBEN (GPIO_BA+0x0DC) /*!< GPIO Port D De-bounce Enable Register */
+ #define REG_GPIOD_PUEN (GPIO_BA+0x0E0) /*!< GPIO Port D Pull-Up Enable Register */
+ #define REG_GPIOD_PDEN (GPIO_BA+0x0E4) /*!< GPIO Port D Pull-Down Enable Register */
+ #define REG_GPIOD_ICEN (GPIO_BA+0x0E8) /*!< GPIO Port D CMOS Input Enable Register */
+ #define REG_GPIOD_ISEN (GPIO_BA+0x0EC) /*!< GPIO Port D Schmitt-Trigger Input Enable Register */
+
+ #define REG_GPIOE_DIR (GPIO_BA+0x100) /*!< GPIO port E direction control register */
+ #define REG_GPIOE_DATAOUT (GPIO_BA+0x104) /*!< GPIO port E data output register */
+ #define REG_GPIOE_DATAIN (GPIO_BA+0x108) /*!< GPIO port E data input register */
+ #define REG_GPIOE_IMD (GPIO_BA+0x10C) /*!< GPIO Port E Interrupt Mode Register */
+ #define REG_GPIOE_IREN (GPIO_BA+0x110) /*!< GPIO Port E Interrupt Rising-Edge or Level-High Enable Register */
+ #define REG_GPIOE_IFEN (GPIO_BA+0x114) /*!< GPIO Port E Interrupt Falling-Edge or Level-Low Enable Register */
+ #define REG_GPIOE_ISR (GPIO_BA+0x118) /*!< GPIO Port E Interrupt Status Register */
+ #define REG_GPIOE_DBEN (GPIO_BA+0x11C) /*!< GPIO Port E De-bounce Enable Register */
+ #define REG_GPIOE_PUEN (GPIO_BA+0x120) /*!< GPIO Port E Pull-Up Enable Register */
+ #define REG_GPIOE_PDEN (GPIO_BA+0x124) /*!< GPIO Port E Pull-Down Enable Register */
+ #define REG_GPIOE_ICEN (GPIO_BA+0x128) /*!< GPIO Port E CMOS Input Enable Register */
+ #define REG_GPIOE_ISEN (GPIO_BA+0x12C) /*!< GPIO Port E Schmitt-Trigger Input Enable Register */
+
+ #define REG_GPIOF_DIR (GPIO_BA+0x140) /*!< GPIO port F direction control register */
+ #define REG_GPIOF_DATAOUT (GPIO_BA+0x144) /*!< GPIO port F data output register */
+ #define REG_GPIOF_DATAIN (GPIO_BA+0x148) /*!< GPIO port F data input register */
+ #define REG_GPIOF_IMD (GPIO_BA+0x14C) /*!< GPIO Port F Interrupt Mode Register */
+ #define REG_GPIOF_IREN (GPIO_BA+0x150) /*!< GPIO Port F Interrupt Rising-Edge or Level-High Enable Register */
+ #define REG_GPIOF_IFEN (GPIO_BA+0x154) /*!< GPIO Port F Interrupt Falling-Edge or Level-Low Enable Register */
+ #define REG_GPIOF_ISR (GPIO_BA+0x158) /*!< GPIO Port F Interrupt Status Register */
+ #define REG_GPIOF_DBEN (GPIO_BA+0x15C) /*!< GPIO Port F De-bounce Enable Register */
+ #define REG_GPIOF_PUEN (GPIO_BA+0x160) /*!< GPIO Port F Pull-Up Enable Register */
+ #define REG_GPIOF_PDEN (GPIO_BA+0x164) /*!< GPIO Port F Pull-Down Enable Register */
+ #define REG_GPIOF_ICEN (GPIO_BA+0x168) /*!< GPIO Port F CMOS Input Enable Register */
+ #define REG_GPIOF_ISEN (GPIO_BA+0x16C) /*!< GPIO Port F Schmitt-Trigger Input Enable Register */
+
+ #define REG_GPIOG_DIR (GPIO_BA+0x180) /*!< GPIO port G direction control register */
+ #define REG_GPIOG_DATAOUT (GPIO_BA+0x184) /*!< GPIO port G data output register */
+ #define REG_GPIOG_DATAIN (GPIO_BA+0x188) /*!< GPIO port G data input register */
+ #define REG_GPIOG_IMD (GPIO_BA+0x18C) /*!< GPIO Port G Interrupt Mode Register */
+ #define REG_GPIOG_IREN (GPIO_BA+0x190) /*!< GPIO Port G Interrupt Rising-Edge or Level-High Enable Register */
+ #define REG_GPIOG_IFEN (GPIO_BA+0x194) /*!< GPIO Port G Interrupt Falling-Edge or Level-Low Enable Register */
+ #define REG_GPIOG_ISR (GPIO_BA+0x198) /*!< GPIO Port G Interrupt Status Register */
+ #define REG_GPIOG_DBEN (GPIO_BA+0x19C) /*!< GPIO Port G De-bounce Enable Register */
+ #define REG_GPIOG_PUEN (GPIO_BA+0x1A0) /*!< GPIO Port G Pull-Up Enable Register */
+ #define REG_GPIOG_PDEN (GPIO_BA+0x1A4) /*!< GPIO Port G Pull-Down Enable Register */
+ #define REG_GPIOG_ICEN (GPIO_BA+0x1A8) /*!< GPIO Port G CMOS Input Enable Register */
+ #define REG_GPIOG_ISEN (GPIO_BA+0x1AC) /*!< GPIO Port G Schmitt-Trigger Input Enable Register */
+
+ #define REG_GPIOH_DIR (GPIO_BA+0x1C0) /*!< GPIO port H direction control register */
+ #define REG_GPIOH_DATAOUT (GPIO_BA+0x1C4) /*!< GPIO port H data output register */
+ #define REG_GPIOH_DATAIN (GPIO_BA+0x1C8) /*!< GPIO port H data input register */
+ #define REG_GPIOH_IMD (GPIO_BA+0x1CC) /*!< GPIO Port H Interrupt Mode Register */
+ #define REG_GPIOH_IREN (GPIO_BA+0x1D0) /*!< GPIO Port H Interrupt Rising-Edge or Level-High Enable Register */
+ #define REG_GPIOH_IFEN (GPIO_BA+0x1D4) /*!< GPIO Port H Interrupt Falling-Edge or Level-Low Enable Register */
+ #define REG_GPIOH_ISR (GPIO_BA+0x1D8) /*!< GPIO Port H Interrupt Status Register */
+ #define REG_GPIOH_DBEN (GPIO_BA+0x1DC) /*!< GPIO Port H De-bounce Enable Register */
+ #define REG_GPIOH_PUEN (GPIO_BA+0x1E0) /*!< GPIO Port H Pull-Up Enable Register */
+ #define REG_GPIOH_PDEN (GPIO_BA+0x1E4) /*!< GPIO Port H Pull-Down Enable Register */
+ #define REG_GPIOH_ICEN (GPIO_BA+0x1E8) /*!< GPIO Port H CMOS Input Enable Register */
+ #define REG_GPIOH_ISEN (GPIO_BA+0x1EC) /*!< GPIO Port H Schmitt-Trigger Input Enable Register */
+
+ #define REG_GPIOI_DIR (GPIO_BA+0x200) /*!< GPIO port I direction control register */
+ #define REG_GPIOI_DATAOUT (GPIO_BA+0x204) /*!< GPIO port I data output register */
+ #define REG_GPIOI_DATAIN (GPIO_BA+0x208) /*!< GPIO port I data input register */
+ #define REG_GPIOI_IMD (GPIO_BA+0x20C) /*!< GPIO Port I Interrupt Mode Register */
+ #define REG_GPIOI_IREN (GPIO_BA+0x210) /*!< GPIO Port I Interrupt Rising-Edge or Level-High Enable Register */
+ #define REG_GPIOI_IFEN (GPIO_BA+0x214) /*!< GPIO Port I Interrupt Falling-Edge or Level-Low Enable Register */
+ #define REG_GPIOI_ISR (GPIO_BA+0x218) /*!< GPIO Port I Interrupt Status Register */
+ #define REG_GPIOI_DBEN (GPIO_BA+0x21C) /*!< GPIO Port I De-bounce Enable Register */
+ #define REG_GPIOI_PUEN (GPIO_BA+0x220) /*!< GPIO Port I Pull-Up Enable Register */
+ #define REG_GPIOI_PDEN (GPIO_BA+0x224) /*!< GPIO Port I Pull-Down Enable Register */
+ #define REG_GPIOI_ICEN (GPIO_BA+0x228) /*!< GPIO Port I CMOS Input Enable Register */
+ #define REG_GPIOI_ISEN (GPIO_BA+0x22C) /*!< GPIO Port I Schmitt-Trigger Input Enable Register */
+
+ #define REG_GPIOJ_DIR (GPIO_BA+0x240) /*!< GPIO port J direction control register */
+ #define REG_GPIOJ_DATAOUT (GPIO_BA+0x244) /*!< GPIO port J data output register */
+ #define REG_GPIOJ_DATAIN (GPIO_BA+0x248) /*!< GPIO port J data input register */
+ #define REG_GPIOJ_IMD (GPIO_BA+0x24C) /*!< GPIO Port J Interrupt Mode Register */
+ #define REG_GPIOJ_IREN (GPIO_BA+0x250) /*!< GPIO Port J Interrupt Rising-Edge or Level-High Enable Register */
+ #define REG_GPIOJ_IFEN (GPIO_BA+0x254) /*!< GPIO Port J Interrupt Falling-Edge or Level-Low Enable Register */
+ #define REG_GPIOJ_ISR (GPIO_BA+0x258) /*!< GPIO Port J Interrupt Status Register */
+ #define REG_GPIOJ_DBEN (GPIO_BA+0x25C) /*!< GPIO Port J De-bounce Enable Register */
+ #define REG_GPIOJ_PUEN (GPIO_BA+0x260) /*!< GPIO Port J Pull-Up Enable Register */
+ #define REG_GPIOJ_PDEN (GPIO_BA+0x264) /*!< GPIO Port J Pull-Down Enable Register */
+ #define REG_GPIOJ_ICEN (GPIO_BA+0x268) /*!< GPIO Port J CMOS Input Enable Register */
+ #define REG_GPIOJ_ISEN (GPIO_BA+0x26C) /*!< GPIO Port J Schmitt-Trigger Input Enable Register */
+
+ #define REG_GPIO_DBNCECON (GPIO_BA+0x3F0) /*!< GPIO Debounce Control Register */
+ #define REG_GPIO_ISR (GPIO_BA+0x3FC) /*!< GPIO Port Interrupt Status Register */
+
+ /**@}*/ /* end of GPIO register group */
+
+
+ /*---------------------- Real Time Clock Controller -------------------------*/
+ /**
+ @addtogroup RTC Real Time Clock Controller(RTC)
+ Memory Mapped Structure for RTC Controller
+ @{ */
+
+ #define REG_RTC_INIT (RTC_BA+0x00) /*!< RTC Initiation Register */
+ #define REG_RTC_RWEN (RTC_BA+0x04) /*!< RTC Access Enable Register */
+ #define REG_RTC_FREQADJ (RTC_BA+0x08) /*!< RTC Frequency Compensation Register */
+ #define REG_RTC_TIME (RTC_BA+0x0C) /*!< Time Loading Register */
+ #define REG_RTC_CAL (RTC_BA+0x10) /*!< Calendar Loading Register */
+ #define REG_RTC_TIMEFMT (RTC_BA+0x14) /*!< Time Format Selection Register */
+ #define REG_RTC_WEEKDAY (RTC_BA+0x18) /*!< Day of the Week Register */
+ #define REG_RTC_TALM (RTC_BA+0x1C) /*!< Time Alarm Register */
+ #define REG_RTC_CALM (RTC_BA+0x20) /*!< Calendar Alarm Register */
+ #define REG_RTC_LEAPYEAR (RTC_BA+0x24) /*!< Leap year Indicator Register */
+ #define REG_RTC_INTEN (RTC_BA+0x28) /*!< RTC Interrupt Enable Register */
+ #define REG_RTC_INTSTS (RTC_BA+0x2C) /*!< RTC Interrupt Indicator Register */
+ #define REG_RTC_TICK (RTC_BA+0x30) /*!< RTC Time Tick Register */
+ #define REG_RTC_PWRCTL (RTC_BA+0x34) /*!< Power Control Register */
+ #define REG_RTC_PWRCNT (RTC_BA+0x38) /*!< Power Control Counter Register */
+ #define REG_RTC_SPR0 (RTC_BA+0x40) /*!< Spare REgistger 0 */
+ #define REG_RTC_SPR1 (RTC_BA+0x44) /*!< Spare REgistger 1 */
+ #define REG_RTC_SPR2 (RTC_BA+0x48) /*!< Spare REgistger 2 */
+ #define REG_RTC_SPR3 (RTC_BA+0x4C) /*!< Spare REgistger 3 */
+ #define REG_RTC_SPR4 (RTC_BA+0x50) /*!< Spare REgistger 4 */
+ #define REG_RTC_SPR5 (RTC_BA+0x54) /*!< Spare REgistger 5 */
+ #define REG_RTC_SPR6 (RTC_BA+0x58) /*!< Spare REgistger 6 */
+ #define REG_RTC_SPR7 (RTC_BA+0x5C) /*!< Spare REgistger 7 */
+ #define REG_RTC_SPR8 (RTC_BA+0x60) /*!< Spare REgistger 8 */
+ #define REG_RTC_SPR9 (RTC_BA+0x64) /*!< Spare REgistger 9 */
+ #define REG_RTC_SPR10 (RTC_BA+0x68) /*!< Spare REgistger 10 */
+ #define REG_RTC_SPR11 (RTC_BA+0x6C) /*!< Spare REgistger 11 */
+ #define REG_RTC_SPR12 (RTC_BA+0x70) /*!< Spare REgistger 12 */
+ #define REG_RTC_SPR13 (RTC_BA+0x74) /*!< Spare REgistger 13 */
+ #define REG_RTC_SPR14 (RTC_BA+0x78) /*!< Spare REgistger 14 */
+ #define REG_RTC_SPR15 (RTC_BA+0x7C) /*!< Spare REgistger 15 */
+
+ /**@}*/ /* end of RTC register group */
+
+ /*---------------------- Inter-IC Bus Controller -------------------------*/
+ /**
+ @addtogroup I2C Inter-IC Bus Controller(I2C)
+ Memory Mapped Structure for I2C Controller
+ @{ */
+
+ #define REG_I2C0_CSR (I2C0_BA+0x00) /*!< Control and Status Register */
+ #define REG_I2C0_DIVIDER (I2C0_BA+0x04) /*!< Clock Prescale Register */
+ #define REG_I2C0_CMDR (I2C0_BA+0x08) /*!< Command Register */
+ #define REG_I2C0_SWR (I2C0_BA+0x0C) /*!< Software Mode Control Register */
+ #define REG_I2C0_RXR (I2C0_BA+0x10) /*!< Data Receive Register */
+ #define REG_I2C0_TXR (I2C0_BA+0x14) /*!< Data Transmit Register */
+
+ #define REG_I2C1_CSR (I2C1_BA+0x00) /*!< Control and Status Register */
+ #define REG_I2C1_DIVIDER (I2C1_BA+0x04) /*!< Clock Prescale Register */
+ #define REG_I2C1_CMDR (I2C1_BA+0x08) /*!< Command Register */
+ #define REG_I2C1_SWR (I2C1_BA+0x0C) /*!< Software Mode Control Register */
+ #define REG_I2C1_RXR (I2C1_BA+0x10) /*!< Data Receive Register */
+ #define REG_I2C1_TXR (I2C1_BA+0x14) /*!< Data Transmit Register */
+
+ /**@}*/ /* end of I2C register group */
+
+
+ /*---------------------- Serial Peripheral Interface Controller -------------------------*/
+ /**
+ @addtogroup SPI Serial Peripheral Interface Controller(SPI)
+ Memory Mapped Structure for SPI Controller
+ @{ */
+
+ #define REG_SPI0_CNTRL (SPI0_BA+0x00) /*!< Control and Status Register */
+ #define REG_SPI0_DIVIDER (SPI0_BA+0x04) /*!< Clock Divider Register */
+ #define REG_SPI0_SSR (SPI0_BA+0x08) /*!< Slave Select Register */
+ #define REG_SPI0_RX0 (SPI0_BA+0x10) /*!< Data Receive Register 0 */
+ #define REG_SPI0_RX1 (SPI0_BA+0x14) /*!< Data Receive Register 1 */
+ #define REG_SPI0_RX2 (SPI0_BA+0x18) /*!< Data Receive Register 2 */
+ #define REG_SPI0_RX3 (SPI0_BA+0x1C) /*!< Data Receive Register 3 */
+ #define REG_SPI0_TX0 (SPI0_BA+0x10) /*!< Data Transmit Register 0 */
+ #define REG_SPI0_TX1 (SPI0_BA+0x14) /*!< Data Transmit Register 1 */
+ #define REG_SPI0_TX2 (SPI0_BA+0x18) /*!< Data Transmit Register 2 */
+ #define REG_SPI0_TX3 (SPI0_BA+0x1C) /*!< Data Transmit Register 3 */
+
+ #define REG_SPI1_CNTRL (SPI1_BA+0x00) /*!< Control and Status Register */
+ #define REG_SPI1_DIVIDER (SPI1_BA+0x04) /*!< Clock Divider Register */
+ #define REG_SPI1_SSR (SPI1_BA+0x08) /*!< Slave Select Register */
+ #define REG_SPI1_RX0 (SPI1_BA+0x10) /*!< Data Receive Register 0 */
+ #define REG_SPI1_RX1 (SPI1_BA+0x14) /*!< Data Receive Register 1 */
+ #define REG_SPI1_RX2 (SPI1_BA+0x18) /*!< Data Receive Register 2 */
+ #define REG_SPI1_RX3 (SPI1_BA+0x1C) /*!< Data Receive Register 3 */
+ #define REG_SPI1_TX0 (SPI1_BA+0x10) /*!< Data Transmit Register 0 */
+ #define REG_SPI1_TX1 (SPI1_BA+0x14) /*!< Data Transmit Register 1 */
+ #define REG_SPI1_TX2 (SPI1_BA+0x18) /*!< Data Transmit Register 2 */
+ #define REG_SPI1_TX3 (SPI1_BA+0x1C) /*!< Data Transmit Register 3 */
+
+ /**@}*/ /* end of SPI register group */
+
+
+ /*---------------------- Pulse Width Modulation Controller -------------------------*/
+ /**
+ @addtogroup PWM Pulse Width Modulation Controller(PWM)
+ Memory Mapped Structure for PWM Controller
+ @{ */
+
+ #define REG_PWM_PPR (PWM_BA+0x00) /*!< PWM Pre-scale Register 0 */
+ #define REG_PWM_CSR (PWM_BA+0x04) /*!< PWM Clock Select Register */
+ #define REG_PWM_PCR (PWM_BA+0x08) /*!< PWM Control Register */
+ #define REG_PWM_CNR0 (PWM_BA+0x0C) /*!< PWM Counter Register 0 */
+ #define REG_PWM_CMR0 (PWM_BA+0x10) /*!< PWM Comparator Register 0 */
+ #define REG_PWM_PDR0 (PWM_BA+0x14) /*!< PWM Data Register 0 */
+ #define REG_PWM_CNR1 (PWM_BA+0x18) /*!< PWM Counter Register 1 */
+ #define REG_PWM_CMR1 (PWM_BA+0x1C) /*!< PWM Comparator Register 1 */
+ #define REG_PWM_PDR1 (PWM_BA+0x20) /*!< PWM Data Register 1 */
+ #define REG_PWM_CNR2 (PWM_BA+0x24) /*!< PWM Counter Register 2 */
+ #define REG_PWM_CMR2 (PWM_BA+0x28) /*!< PWM Comparator Register 2 */
+ #define REG_PWM_PDR2 (PWM_BA+0x2C) /*!< PWM Data Register 2 */
+ #define REG_PWM_CNR3 (PWM_BA+0x30) /*!< PWM Counter Register 3 */
+ #define REG_PWM_CMR3 (PWM_BA+0x34) /*!< PWM Comparator Register 3 */
+ #define REG_PWM_PDR3 (PWM_BA+0x38) /*!< PWM Data Register 3 */
+ #define REG_PWM_PIER (PWM_BA+0x3C) /*!< PWM Timer Interrupt Enable Register */
+ #define REG_PWM_PIIR (PWM_BA+0x40) /*!< PWM Timer Interrupt Identification Register */
+
+ /**@}*/ /* end of PWM register group */
+
+
+ /*---------------------- Analog to Digital Converter -------------------------*/
+ /**
+ @addtogroup ADC Analog to Digital Converter(ADC)
+ Memory Mapped Structure for ADC Controller
+ @{ */
+
+ #define REG_ADC_CTL (ADC_BA+0x000) /*!< ADC Contrl */
+ #define REG_ADC_CONF (ADC_BA+0x004) /*!< ADC Configure */
+ #define REG_ADC_IER (ADC_BA+0x008) /*!< ADC Interrupt Enable Register */
+ #define REG_ADC_ISR (ADC_BA+0x00C) /*!< ADC Interrupt Status Register */
+ #define REG_ADC_WKISR (ADC_BA+0x010) /*!< ADC Wake Up Interrupt Status Register */
+ #define REG_ADC_XYDATA (ADC_BA+0x020) /*!< ADC Touch XY Pressure Data */
+ #define REG_ADC_ZDATA (ADC_BA+0x024) /*!< ADC Touch Z Pressure Data */
+ #define REG_ADC_DATA (ADC_BA+0x028) /*!< ADC Normal Conversion Data */
+ #define REG_ADC_VBADATA (ADC_BA+0x02C) /*!< ADC Battery Detection Data */
+ #define REG_ADC_KPDATA (ADC_BA+0x030) /*!< ADC Key Pad Data */
+ #define REG_ADC_SELFDATA (ADC_BA+0x034) /*!< ADC Self-Test Data */
+ #define REG_ADC_XYSORT0 (ADC_BA+0x1F4) /*!< ADC Touch XY Position Mean Value Sort 0 */
+ #define REG_ADC_XYSORT1 (ADC_BA+0x1F8) /*!< ADC Touch XY Position Mean Value Sort 1 */
+ #define REG_ADC_XYSORT2 (ADC_BA+0x1FC) /*!< ADC Touch XY Position Mean Value Sort 2 */
+ #define REG_ADC_XYSORT3 (ADC_BA+0x200) /*!< ADC Touch XY Position Mean Value Sort 3 */
+ #define REG_ADC_ZSORT0 (ADC_BA+0x204) /*!< ADC Touch Z Pressure Mean Value Sort 0 */
+ #define REG_ADC_ZSORT1 (ADC_BA+0x208) /*!< ADC Touch Z Pressure Mean Value Sort 1 */
+ #define REG_ADC_ZSORT2 (ADC_BA+0x20C) /*!< ADC Touch Z Pressure Mean Value Sort 2 */
+ #define REG_ADC_ZSORT3 (ADC_BA+0x210) /*!< ADC Touch Z Pressure Mean Value Sort 3 */
+ #define REG_ADC_MTMULCK (ADC_BA+0x220) /*!< ADC Manual Test Mode Unlock */
+ #define REG_ADC_MTCONF (ADC_BA+0x224) /*!< ADC Manual Test Mode Configure */
+ #define REG_ADC_MTCON (ADC_BA+0x228) /*!< ADC Manual Test Mode Control */
+ #define REG_ADC_ADCAII (ADC_BA+0x22C) /*!< ADC Analog Interface Information */
+ #define REG_ADC_ADCAIIRLT (ADC_BA+0x230) /*!< ADC Analog Interface Information Result */
+
+ /**@}*/ /* end of ADC register group */
+
+ /*------------------ Capture Sensor Interface Controller ---------------------*/
+ /**
+ @addtogroup CAP Capture Sensor Interface Controller(CAP)
+ Memory Mapped Structure for CAP Controller
+ @{ */
+
+ #define REG_CAP_CTL (CAP_BA+0x000) /*!< Image Capture Interface Control Register */
+ #define REG_CAP_PAR (CAP_BA+0x004) /*!< Image Capture Interface Parameter Register */
+ #define REG_CAP_INT (CAP_BA+0x008) /*!< Image Capture Interface Interrupt Registe */
+ #define REG_CAP_POSTERIZE (CAP_BA+0x00C) /*!< YUV Component Posterizing Factor Register */
+ #define REG_CAP_MD (CAP_BA+0x010) /*!< Motion Detection Register */
+ #define REG_CAP_MDADDR (CAP_BA+0x014) /*!< Motion Detection Output Address Register */
+ #define REG_CAP_MDYADDR (CAP_BA+0x018) /*!< Motion Detection Temp YOutput Address Register */
+ #define REG_CAP_SEPIA (CAP_BA+0x01C) /*!< Sepia Effect Control Register */
+ #define REG_CAP_CWSP (CAP_BA+0x020) /*!< Cropping Window Starting Address Register */
+ #define REG_CAP_CWS (CAP_BA+0x024) /*!< Cropping Window Size Register */
+ #define REG_CAP_PKTSL (CAP_BA+0x028) /*!< Packet Scaling Vertical/Horizontal Factor Register (LSB) */
+ #define REG_CAP_PLNSL (CAP_BA+0x02C) /*!< Planar Scaling Vertical/Horizontal Factor Register (LSB) */
+ #define REG_CAP_FRCTL (CAP_BA+0x030) /*!< Scaling Frame Rate Factor Register */
+ #define REG_CAP_STRIDE (CAP_BA+0x034) /*!< Frame Output Pixel Stride Register */
+ #define REG_CAP_FIFOTH (CAP_BA+0x03C) /*!< FIFO threshold Register */
+ #define REG_CAP_CMPADDR (CAP_BA+0x040) /*!< Compare Packet Memory Base Address Register */
+ #define REG_CAP_PKTSM (CAP_BA+0x048) /*!< Packet Scaling Vertical/Horizontal Factor Register (MSB) */
+ #define REG_CAP_PLNSM (CAP_BA+0x04C) /*!< Planar Scaling Vertical/Horizontal Factor Register (MSB) */
+ #define REG_CAP_CURADDRP (CAP_BA+0x050) /*!< Current Packet System Memory Address Register */
+ #define REG_CAP_CURADDRY (CAP_BA+0x054) /*!< Current Planar Y System Memory Address Register */
+ #define REG_CAP_CURADDRU (CAP_BA+0x058) /*!< Current Planar U System Memory Address Register */
+ #define REG_CAP_CURADDRV (CAP_BA+0x05C) /*!< Current Planar V System Memory Address Register */
+ #define REG_CAP_PKTBA0 (CAP_BA+0x060) /*!< System Memory Packet Base Address Register */
+ #define REG_CAP_PKTBA1 (CAP_BA+0x064) /*!< System Memory Packet Base Address Register */
+ #define REG_CAP_YBA (CAP_BA+0x080) /*!< System Memory Planar Y Base Address Register */
+ #define REG_CAP_UBA (CAP_BA+0x084) /*!< System Memory Planar U Base Address Register */
+ #define REG_CAP_VBA (CAP_BA+0x088) /*!< System Memory Planar V Base Address Register */
+
+ /**@}*/ /* end of CAP register group */
+
+ /*------------------ SDRAM Interface Controller ---------------------*/
+ /**
+ @addtogroup SDIC SDRAM Interface Controller(SDIC)
+ Memory Mapped Structure for SDIC Controller
+ @{ */
+
+ #define REG_SDIC_OPMCTL (SDIC_BA+0x000) /*!< SDRAM Controller Operation Mode Control Register */
+ #define REG_SDIC_CMD (SDIC_BA+0x004) /*!< SDRAM Command Register */
+ #define REG_SDIC_REFCTL (SDIC_BA+0x008) /*!< SDRAM Controller Refresh Control Register */
+ #define REG_SDIC_SIZE0 (SDIC_BA+0x010) /*!< SDRAM 0 Size Register */
+ #define REG_SDIC_SIZE1 (SDIC_BA+0x014) /*!< SDRAM 1 Size Register */
+ #define REG_SDIC_MR (SDIC_BA+0x018) /*!< SDRAM Mode Register */
+ #define REG_SDIC_EMR (SDIC_BA+0x01C) /*!< SDRAM Extended Mode Register */
+ #define REG_SDIC_EMR2 (SDIC_BA+0x020) /*!< SDRAM Extended Mode Register 2 */
+ #define REG_SDIC_EMR3 (SDIC_BA+0x024) /*!< SDRAM Extended Mode Register 3 */
+ #define REG_SDIC_TIME (SDIC_BA+0x028) /*!< SDRAM Timing Control Register */
+ #define REG_SDIC_DQSODS (SDIC_BA+0x030) /*!< DQS Output Delay Selection Register */
+ #define REG_SDIC_CKDQSDS (SDIC_BA+0x034) /*!< Clock and DQS Delay Selection Register */
+ #define REG_SDIC_DAENSEL (SDIC_BA+0x038) /*!< Data Latch Enable Selection Register */
+
+ /**@}*/ /* end of SDIC register group */
+
+ /*---------------------- Controller Area Network -------------------------*/
+ /**
+ @addtogroup CAN Controller Area Network(CAN)
+ Memory Mapped Structure for CAN Controller
+ @{ */
+
+ #define REG_CAN0_CON (CAN0_BA+0x00) /*!< Control Register */
+ #define REG_CAN0_STATUS (CAN0_BA+0x04) /*!< Status Register */
+ #define REG_CAN0_ERR (CAN0_BA+0x08) /*!< Error Counter Register */
+ #define REG_CAN0_BTIME (CAN0_BA+0x0C) /*!< Bit Time Register */
+ #define REG_CAN0_IIDR (CAN0_BA+0x10) /*!< Interrupt Identifier Register */
+ #define REG_CAN0_TEST (CAN0_BA+0x14) /*!< Test Register */
+ #define REG_CAN0_BRPE (CAN0_BA+0x18) /*!< BRP Extension Register */
+ #define REG_CAN0_IF1_CREQ (CAN0_BA+0x20) /*!< IF1 Command Request Register */
+ #define REG_CAN0_IF2_CREQ (CAN0_BA+0x80) /*!< IF2 Command Request Register */
+ #define REG_CAN0_IF1_CMASK (CAN0_BA+0x24) /*!< IF1 Command Mask Register */
+ #define REG_CAN0_IF2_CMASK (CAN0_BA+0x84) /*!< IF2 Command Mask Register */
+ #define REG_CAN0_IF1_MASK1 (CAN0_BA+0x28) /*!< IF1 Msak 1 Register */
+ #define REG_CNA0_IF2_MASK1 (CAN0_BA+0x88) /*!< IF2 Mask 1 Register */
+ #define REG_CAN0_IF1_MASK2 (CAN0_BA+0x2C) /*!< IF1 Mask 2 Register */
+ #define REG_CAN0_IF2_MASK2 (CAN0_BA+0x8C) /*!< IF2 Mask 2 REgister */
+ #define REG_CAN0_IF1_ARB1 (CAN0_BA+0x30) /*!< IF1 Arbitration 1 Register */
+ #define REG_CAN0_IF2_ARB1 (CAN0_BA+0x90) /*!< IF2 Arbitration 1 Register */
+ #define REG_CAN0_IF1_ARB2 (CAN0_BA+0x34) /*!< IF1 Arbitration 2 Register */
+ #define REG_CAN0_IF2_ARB2 (CAN0_BA+0x94) /*!< IF2 Arbitration 2 Register */
+ #define REG_CAN0_IF1_MCON (CAN0_BA+0x38) /*!< IF1 Message Control Register */
+ #define REG_CAN0_IF2_MCON (CAN0_BA+0x98) /*!< IF2 Message Control Register */
+ #define REG_CAN0_IF1_DAT_A1 (CAN0_BA+0x3C) /*!< IF1 Data A1 Register */
+ #define REG_CAN0_IF1_DAT_A2 (CAN0_BA+0x40) /*!< IF1 Data A2 Register */
+ #define REG_CAN0_IF1_DAT_B1 (CAN0_BA+0x44) /*!< IF1 Data B1 Register */
+ #define REG_CAN0_IF1_DAT_B2 (CAN0_BA+0x48) /*!< IF1 Data B2 Register */
+ #define REG_CAN0_IF2_DAT_A1 (CAN0_BA+0x9C) /*!< IF2 Data A1 Register */
+ #define REG_CAN0_IF2_DAT_A2 (CAN0_BA+0xA0) /*!< IF2 Data A2 Register */
+ #define REG_CAN0_IF2_DAT_B1 (CAN0_BA+0xA4) /*!< IF2 Data B1 Register */
+ #define REG_CAN0_IF2_DAT_B2 (CAN0_BA+0xA8) /*!< IF2 Data B2 Register */
+ #define REG_CAN0_TXREQ1 (CAN0_BA+0x100) /*!< Transmission Request Register 1 */
+ #define REG_CAN0_TXREQ2 (CAN0_BA+0x104) /*!< Transmission Request Register 2 */
+ #define REG_CAN0_NDAT1 (CAN0_BA+0x120) /*!< New Data Register 1 */
+ #define REG_CAN0_NDAT2 (CAN0_BA+0x124) /*!< New Data Register 2 */
+ #define REG_CAN0_IPND1 (CAN0_BA+0x140) /*!< Interrupt Pending Register 1 */
+ #define REG_CAN0_IPND2 (CAN0_BA+0x142) /*!< Interrupt Pending Register 2 */
+ #define REG_CAN0_MVLD1 (CAN0_BA+0x160) /*!< Message Valid Register 1 */
+ #define REG_CAN0_MVLD2 (CAN0_BA+0x164) /*!< Message Valid Register 2 */
+ #define REG_CAN0_WU_EN (CAN0_BA+0x168) /*!< Wake-up Function Enable */
+ #define REG_CAN0_WU_STATUS (CAN0_BA+0x16C) /*!< Wake-up Function Status */
+
+ #define REG_CAN1_CON (CAN1_BA+0x00) /*!< Control Register */
+ #define REG_CAN1_STATUS (CAN1_BA+0x04) /*!< Status Register */
+ #define REG_CAN1_ERR (CAN1_BA+0x08) /*!< Error Counter Register */
+ #define REG_CAN1_BTIME (CAN1_BA+0x0C) /*!< Bit Time Register */
+ #define REG_CAN1_IIDR (CAN1_BA+0x10) /*!< Interrupt Identifier Register */
+ #define REG_CAN1_TEST (CAN1_BA+0x14) /*!< Test Register */
+ #define REG_CAN1_BRPE (CAN1_BA+0x18) /*!< BRP Extension Register */
+ #define REG_CAN1_IF1_CREQ (CAN1_BA+0x20) /*!< IF1 Command Request Register */
+ #define REG_CAN1_IF2_CREQ (CAN1_BA+0x80) /*!< IF2 Command Request Register */
+ #define REG_CAN1_IF1_CMASK (CAN1_BA+0x24) /*!< IF1 Command Mask Register */
+ #define REG_CAN1_IF2_CMASK (CAN1_BA+0x84) /*!< IF2 Command Mask Register */
+ #define REG_CAN1_IF1_MASK1 (CAN1_BA+0x28) /*!< IF1 Msak 1 Register */
+ #define REG_CNA1_IF2_MASK1 (CAN1_BA+0x88) /*!< IF2 Mask 1 Register */
+ #define REG_CAN1_IF1_MASK2 (CAN1_BA+0x2C) /*!< IF1 Mask 2 Register */
+ #define REG_CAN1_IF2_MASK2 (CAN1_BA+0x8C) /*!< IF2 Mask 2 REgister */
+ #define REG_CAN1_IF1_ARB1 (CAN1_BA+0x30) /*!< IF1 Arbitration 1 Register */
+ #define REG_CAN1_IF2_ARB1 (CAN1_BA+0x90) /*!< IF2 Arbitration 1 Register */
+ #define REG_CAN1_IF1_ARB2 (CAN1_BA+0x34) /*!< IF1 Arbitration 2 Register */
+ #define REG_CAN1_IF2_ARB2 (CAN1_BA+0x94) /*!< IF2 Arbitration 2 Register */
+ #define REG_CAN1_IF1_MCON (CAN1_BA+0x38) /*!< IF1 Message Control Register */
+ #define REG_CAN1_IF2_MCON (CAN1_BA+0x98) /*!< IF2 Message Control Register */
+ #define REG_CAN1_IF1_DAT_A1 (CAN1_BA+0x3C) /*!< IF1 Data A1 Register */
+ #define REG_CAN1_IF1_DAT_A2 (CAN1_BA+0x40) /*!< IF1 Data A2 Register */
+ #define REG_CAN1_IF1_DAT_B1 (CAN1_BA+0x44) /*!< IF1 Data B1 Register */
+ #define REG_CAN1_IF1_DAT_B2 (CAN1_BA+0x48) /*!< IF1 Data B2 Register */
+ #define REG_CAN1_IF2_DAT_A1 (CAN1_BA+0x9C) /*!< IF2 Data A1 Register */
+ #define REG_CAN1_IF2_DAT_A2 (CAN1_BA+0xA0) /*!< IF2 Data A2 Register */
+ #define REG_CAN1_IF2_DAT_B1 (CAN1_BA+0xA4) /*!< IF2 Data B1 Register */
+ #define REG_CAN1_IF2_DAT_B2 (CAN1_BA+0xA8) /*!< IF2 Data B2 Register */
+ #define REG_CAN1_TXREQ1 (CAN1_BA+0x100) /*!< Transmission Request Register 1 */
+ #define REG_CAN1_TXREQ2 (CAN1_BA+0x104) /*!< Transmission Request Register 2 */
+ #define REG_CAN1_NDAT1 (CAN1_BA+0x120) /*!< New Data Register 1 */
+ #define REG_CAN1_NDAT2 (CAN1_BA+0x124) /*!< New Data Register 2 */
+ #define REG_CAN1_IPND1 (CAN1_BA+0x140) /*!< Interrupt Pending Register 1 */
+ #define REG_CAN1_IPND2 (CAN1_BA+0x142) /*!< Interrupt Pending Register 2 */
+ #define REG_CAN1_MVLD1 (CAN1_BA+0x160) /*!< Message Valid Register 1 */
+ #define REG_CAN1_MVLD2 (CAN1_BA+0x164) /*!< Message Valid Register 2 */
+ #define REG_CAN1_WU_EN (CAN1_BA+0x168) /*!< Wake-up Function Enable */
+ #define REG_CAN1_WU_STATUS (CAN1_BA+0x16C) /*!< Wake-up Function Status */
+
+ /**@}*/ /* end of CAN register group */
+
+
+ /*------------------- Multi-Time Programmable Controller --------------------*/
+ /**
+ @addtogroup MTP Multi-Time Programmable Controller (MTP)
+ Memory Mapped Structure for MTP Controller
+ @{ */
+
+ #define MTP_KEYEN (MTP_BA+0x000) /*!< MTP Key Enable Register */
+ #define MTP_USERDATA (MTP_BA+0x00C) /*!< MTP User Defined Data Register */
+ #define MTP_KEY0 (MTP_BA+0x010) /*!< MTP KEY 0 Register */
+ #define MTP_KEY1 (MTP_BA+0x014) /*!< MTP KEY 1 Register */
+ #define MTP_KEY2 (MTP_BA+0x018) /*!< MTP KEY 2 Register */
+ #define MTP_KEY3 (MTP_BA+0x01C) /*!< MTP KEY 3 Register */
+ #define MTP_KEY4 (MTP_BA+0x020) /*!< MTP KEY 4 Register */
+ #define MTP_KEY5 (MTP_BA+0x024) /*!< MTP KEY 5 Register */
+ #define MTP_KEY6 (MTP_BA+0x028) /*!< MTP KEY 6 Register */
+ #define MTP_KEY7 (MTP_BA+0x02C) /*!< MTP KEY 7 Register */
+ #define MTP_PCYCLE (MTP_BA+0x030) /*!< MTP Program Cycle Program Count Register */
+ #define MTP_CTL (MTP_BA+0x034) /*!< MTP Control Register */
+ #define MTP_PSTART (MTP_BA+0x038) /*!< MTP Program Start Registe */
+ #define MTP_STATUS (MTP_BA+0x040) /*!< MTP Status Registe */
+ #define MTP_REGLCTL (MTP_BA+0x050) /*!< MTP Register Write-Protection Control Register*/
+
+ /**@}*/ /* end of MTP register group */
+
+
+ /*------------------- JPEG Controller --------------------*/
+ /**
+ @addtogroup JPEG JPEG Controller (JPEG)
+ Memory Mapped Structure for JPEG Controller
+ @{ */
+ #define JMCR (JPEG_BA+0x00) /*!< JPEG Mode Control Register */
+ #define JHEADER (JPEG_BA+0x04) /*!< JPEG Encode Header Control Register */
+ #define JITCR (JPEG_BA+0x08) /*!< JPEG Image Type Control Register */
+ #define JPRIQC (JPEG_BA+0x10) /*!< JPEG Primary Q-Table Control Register */
+ #define JTHBQC (JPEG_BA+0x14) /*!< JPEG Thumbnail Q-Table Control Register */
+ #define JPRIWH (JPEG_BA+0x18) /*!< JPEG Encode Primary Width/Height Register */
+ #define JTHBWH (JPEG_BA+0x1C) /*!< JPEG Encode Thumbnail Width/Height Register */
+ #define JPRST (JPEG_BA+0x20) /*!< JPEG Encode Primary Restart Interval Register */
+ #define JTRST (JPEG_BA+0x24) /*!< JPEG Encode Thumbnail Restart Interval */
+ #define JDECWH (JPEG_BA+0x28) /*!< JPEG Decode Image Width/Height Register */
+ #define JINTCR (JPEG_BA+0x2C) /*!< JPEG Interrupt Control and Status Register */
+ #define JDOWFBS (JPEG_BA+0x3c) /*!< JPEG Decoding Output Wait Frame Buffer Size */
+ #define JPEG_BSBAD (JPEG_BA+0x40) /*!< JPEG Test Control Register */
+ #define JWINDEC0 (JPEG_BA+0x44) /*!< JPEG Window Decode Mode Control Register 0 */
+ #define JWINDEC1 (JPEG_BA+0x48) /*!< JPEG Window Decode Mode Control Register 1 */
+ #define JWINDEC2 (JPEG_BA+0x4C) /*!< JPEG Window Decode Mode Control Register 2 */
+ #define JMACR (JPEG_BA+0x50) /*!< JPEG Memory Address Mode Control Register */
+ #define JPSCALU (JPEG_BA+0x54) /*!< JPEG Primary Scaling-Up Control Register */
+ #define JPSCALD (JPEG_BA+0x58) /*!< JPEG Primary Scaling-Down Control Register */
+ #define JTSCALD (JPEG_BA+0x5C) /*!< JPEG Thumbnail Scaling-Down Control Register */
+ #define JDBCR (JPEG_BA+0x60) /*!< JPEG Dual-Buffer Control Register */
+ #define JRESERVE (JPEG_BA+0x70) /*!< JPEG Encode Primary Bit-stream Reserved Size Register */
+ #define JOFFSET (JPEG_BA+0x74) /*!< JPEG Offset Between Primary & Thumbnail Register */
+ #define JFSTRIDE (JPEG_BA+0x78) /*!< JPEG Encode Bit-stream Frame Stride Register */
+ #define JYADDR0 (JPEG_BA+0x7C) /*!< JPEG Y Component Frame Buffer-0 Starting Address Register */
+ #define JUADDR0 (JPEG_BA+0x80) /*!< JPEG U Component Frame Buffer-0 Starting Address Register */
+ #define JVADDR0 (JPEG_BA+0x84) /*!< JPEG V Component Frame Buffer-0 Starting Address Register */
+ #define JYADDR1 (JPEG_BA+0x88) /*!< JPEG Y Component Frame Buffer-1 Starting Address Register */
+ #define JUADDR1 (JPEG_BA+0x8C) /*!< JPEG U Component Frame Buffer-1 Starting Address Register */
+ #define JVADDR1 (JPEG_BA+0x90) /*!< JPEG V Component Frame Buffer-1 Starting Address Register */
+ #define JYSTRIDE (JPEG_BA+0x94) /*!< JPEG Y Component Frame Buffer Stride Register */
+ #define JUSTRIDE (JPEG_BA+0x98) /*!< JPEG U Component Frame Buffer Stride Register */
+ #define JVSTRIDE (JPEG_BA+0x9C) /*!< JPEG V Component Frame Buffer Stride Register */
+ #define JIOADDR0 (JPEG_BA+0xA0) /*!< JPEG Bit-stream Frame Buffer-0 Starting Address Register */
+ #define JIOADDR1 (JPEG_BA+0xA4) /*!< JPEG Bit-stream Frame Buffer-1 Starting Address Register */
+ #define JPRI_SIZE (JPEG_BA+0xA8) /*!< JPEG Encode Primary Image Bit-stream Size Register */
+ #define JTHB_SIZE (JPEG_BA+0xAC) /*!< JPEG Encode Thumbnail Image Bit-stream Size Register */
+ #define JUPRAT (JPEG_BA+0xB0) /*!< JPEG Encode Up-Scale Ratio Register */
+ #define JBSFIFO (JPEG_BA+0xB4) /*!< JPEG Bit-stream FIFO Control Register */
+ #define JSRCH (JPEG_BA+0xB8) /*!< JPEG Encode Source Image Height */
+ #define JQTAB0 (JPEG_BA+0x100) /*!< JPEG Quantization-Table 0 Register */
+ #define JQTAB1 (JPEG_BA+0x140) /*!< JPEG Quantization-Table 1 Register */
+ #define JQTAB2 (JPEG_BA+0x180) /*!< JPEG Quantization-Table 2 Register */
+
+ /**@}*/ /* end of JPEG register group */
+
+
+
+ /*@}*/ /* end of group N9H30_Peripherals */
+
+
+ /** @addtogroup N9H30_IO_ROUTINE N9H30 I/O Routines
+ The Declaration of N9H30 I/O Routines
+ @{
+ */
+
+ typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type
+ typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type
+ typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type
+
+ /**
+ * @brief Get a 8-bit unsigned value from specified address
+ * @param[in] addr Address to get 8-bit data from
+ * @return 8-bit unsigned value stored in specified address
+ */
+ #define M8(addr) (*((vu8 *) (addr)))
+
+ /**
+ * @brief Get a 16-bit unsigned value from specified address
+ * @param[in] addr Address to get 16-bit data from
+ * @return 16-bit unsigned value stored in specified address
+ * @note The input address must be 16-bit aligned
+ */
+ #define M16(addr) (*((vu16 *) (addr)))
+
+ /**
+ * @brief Get a 32-bit unsigned value from specified address
+ * @param[in] addr Address to get 32-bit data from
+ * @return 32-bit unsigned value stored in specified address
+ * @note The input address must be 32-bit aligned
+ */
+ #define M32(addr) (*((vu32 *) (addr)))
+
+ /**
+ * @brief Set a 32-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 32-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 32-bit aligned
+ */
+ #define outpw(port,value) *((volatile unsigned int *)(port)) = value
+
+ /**
+ * @brief Get a 32-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 32-bit data from
+ * @return 32-bit unsigned value stored in specified I/O port
+ * @note The input port must be 32-bit aligned
+ */
+ #define inpw(port) (*((volatile unsigned int *)(port)))
+
+ /**
+ * @brief Set a 16-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 16-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 16-bit aligned
+ */
+ #define outps(port,value) *((volatile unsigned short *)(port)) = value
+
+ /**
+ * @brief Get a 16-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 16-bit data from
+ * @return 16-bit unsigned value stored in specified I/O port
+ * @note The input port must be 16-bit aligned
+ */
+ #define inps(port) (*((volatile unsigned short *)(port)))
+
+ /**
+ * @brief Set a 8-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 8-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ */
+ #define outpb(port,value) *((volatile unsigned char *)(port)) = value
+
+ /**
+ * @brief Get a 8-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 8-bit data from
+ * @return 8-bit unsigned value stored in specified I/O port
+ */
+ #define inpb(port) (*((volatile unsigned char *)(port)))
+
+ /**
+ * @brief Set a 32-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 32-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 32-bit aligned
+ */
+ #define outp32(port,value) *((volatile unsigned int *)(port)) = value
+
+ /**
+ * @brief Get a 32-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 32-bit data from
+ * @return 32-bit unsigned value stored in specified I/O port
+ * @note The input port must be 32-bit aligned
+ */
+ #define inp32(port) (*((volatile unsigned int *)(port)))
+
+ /**
+ * @brief Set a 16-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 16-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ * @note The output port must be 16-bit aligned
+ */
+ #define outp16(port,value) *((volatile unsigned short *)(port)) = value
+
+ /**
+ * @brief Get a 16-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 16-bit data from
+ * @return 16-bit unsigned value stored in specified I/O port
+ * @note The input port must be 16-bit aligned
+ */
+ #define inp16(port) (*((volatile unsigned short *)(port)))
+
+ /**
+ * @brief Set a 8-bit unsigned value to specified I/O port
+ * @param[in] port Port address to set 8-bit data
+ * @param[in] value Value to write to I/O port
+ * @return None
+ */
+ #define outp8(port,value) *((volatile unsigned char *)(port)) = value
+
+ /**
+ * @brief Get a 8-bit unsigned value from specified I/O port
+ * @param[in] port Port address to get 8-bit data from
+ * @return 8-bit unsigned value stored in specified I/O port
+ */
+ #define inp8(port) (*((volatile unsigned char *)(port)))
+
+
+ /*@}*/ /* end of group N9H30_IO_ROUTINE */
+
+ /******************************************************************************/
+ /* Legacy Constants */
+ /******************************************************************************/
+ /** @addtogroup N9H30_legacy_Constants N9H30 Legacy Constants
+ N9H30 Legacy Constants
+ @{
+ */
+ typedef void *PVOID; ///< Define void pointer data type
+ typedef void VOID; ///< Define void data type
+ typedef char BOOL; ///< Define bool data type
+ typedef char *PBOOL; ///< Define bool pointer data type
+
+ typedef char INT8; ///< Define 8-bit singed data type
+ typedef char CHAR; ///< Define char data type
+ typedef char *PINT8; ///< Define 8-bit singed pointer data type
+ typedef char *PCHAR; ///< Define char pointer data type
+ typedef unsigned char UINT8; ///< Define 8-bit unsigned data type
+ typedef unsigned char UCHAR; ///< Define char unsigned data type
+ typedef unsigned char *PUINT8; ///< Define 8-bit unsigned pointer data type
+ typedef unsigned char *PUCHAR; ///< Define char unsigned pointer data type
+ typedef char *PSTR; ///< Define string pointer data type
+ typedef const char *PCSTR; ///< Define constant string pointer data type
+
+ typedef short SHORT; ///< Define short signed data type
+ typedef short *PSHORT; ///< Define short signed pointer data type
+ typedef unsigned short USHORT; ///< Define short unsigned data type
+ typedef unsigned short *PUSHORT; ///< Define short unsigned pointer data type
+
+ typedef short INT16; ///< Define 16-bit signed data type
+ typedef short *PINT16; ///< Define 16-bit signed pointer data type
+ typedef unsigned short UINT16; ///< Define 16-bit unsigned data type
+ typedef unsigned short *PUINT16; ///< Define 16-bit unsigned pointer data type
+
+ typedef int INT; ///< Define integer signed data type
+ typedef int *PINT; ///< Define integer signed pointer data type
+ typedef unsigned int UINT; ///< Define integer unsigned data type
+ typedef unsigned int *PUINT; ///< Define integer unsigned pointer data type
+
+ typedef int INT32; ///< Define 32-bit signed data type
+ typedef int *PINT32; ///< Define 32-bit signed pointer data type
+ typedef unsigned int UINT32; ///< Define 32-bit unsigned data type
+ typedef unsigned int *PUINT32; ///< Define 32-bit unsigned pointer data type
+
+ #if defined ( __GNUC__ ) && !(__CC_ARM)
+ typedef long long INT64;
+ typedef unsigned long long UINT64;
+ #else
+ typedef __int64 INT64; ///< Define 64-bit signed data type
+ typedef unsigned __int64 UINT64; ///< Define 64-bit unsigned data type
+ #endif
+
+ typedef float FLOAT; ///< Define float data type
+ typedef float *PFLOAT; ///< Define float pointer data type
+
+ typedef double DOUBLE; ///< Define double data type
+ typedef double *PDOUBLE; ///< Define double pointer data type
+
+ typedef int SIZE_T; ///< Define size of data type
+
+ typedef unsigned char REG8; ///< Define 8-bit register data type
+ typedef unsigned short REG16; ///< Define 16-bit register data type
+ typedef unsigned int REG32; ///< Define 32-bit register data type
+
+
+ #ifndef NULL
+ #define NULL (0) ///< NULL pointer
+ #endif
+
+ #define TRUE (1) ///< Boolean true, define to use in API parameters or return value
+ #define FALSE (0) ///< Boolean false, define to use in API parameters or return value
+
+ #define ENABLE (1) ///< Enable, define to use in API parameters
+ #define DISABLE (0) ///< Disable, define to use in API parameters
+
+
+ #define Successful 0 ///< Function return value success
+ #define Fail 1 ///< Function return value failed
+
+ /* Define one bit mask */
+ #define BIT0 (0x00000001) ///< Bit 0 mask of an 32 bit integer
+ #define BIT1 (0x00000002) ///< Bit 1 mask of an 32 bit integer
+ #define BIT2 (0x00000004) ///< Bit 2 mask of an 32 bit integer
+ #define BIT3 (0x00000008) ///< Bit 3 mask of an 32 bit integer
+ #define BIT4 (0x00000010) ///< Bit 4 mask of an 32 bit integer
+ #define BIT5 (0x00000020) ///< Bit 5 mask of an 32 bit integer
+ #define BIT6 (0x00000040) ///< Bit 6 mask of an 32 bit integer
+ #define BIT7 (0x00000080) ///< Bit 7 mask of an 32 bit integer
+ #define BIT8 (0x00000100) ///< Bit 8 mask of an 32 bit integer
+ #define BIT9 (0x00000200) ///< Bit 9 mask of an 32 bit integer
+ #define BIT10 (0x00000400) ///< Bit 10 mask of an 32 bit integer
+ #define BIT11 (0x00000800) ///< Bit 11 mask of an 32 bit integer
+ #define BIT12 (0x00001000) ///< Bit 12 mask of an 32 bit integer
+ #define BIT13 (0x00002000) ///< Bit 13 mask of an 32 bit integer
+ #define BIT14 (0x00004000) ///< Bit 14 mask of an 32 bit integer
+ #define BIT15 (0x00008000) ///< Bit 15 mask of an 32 bit integer
+ #define BIT16 (0x00010000) ///< Bit 16 mask of an 32 bit integer
+ #define BIT17 (0x00020000) ///< Bit 17 mask of an 32 bit integer
+ #define BIT18 (0x00040000) ///< Bit 18 mask of an 32 bit integer
+ #define BIT19 (0x00080000) ///< Bit 19 mask of an 32 bit integer
+ #define BIT20 (0x00100000) ///< Bit 20 mask of an 32 bit integer
+ #define BIT21 (0x00200000) ///< Bit 21 mask of an 32 bit integer
+ #define BIT22 (0x00400000) ///< Bit 22 mask of an 32 bit integer
+ #define BIT23 (0x00800000) ///< Bit 23 mask of an 32 bit integer
+ #define BIT24 (0x01000000) ///< Bit 24 mask of an 32 bit integer
+ #define BIT25 (0x02000000) ///< Bit 25 mask of an 32 bit integer
+ #define BIT26 (0x04000000) ///< Bit 26 mask of an 32 bit integer
+ #define BIT27 (0x08000000) ///< Bit 27 mask of an 32 bit integer
+ #define BIT28 (0x10000000) ///< Bit 28 mask of an 32 bit integer
+ #define BIT29 (0x20000000) ///< Bit 29 mask of an 32 bit integer
+ #define BIT30 (0x40000000) ///< Bit 30 mask of an 32 bit integer
+ #define BIT31 (0x80000000) ///< Bit 31 mask of an 32 bit integer
+
+ /* Byte Mask Definitions */
+ #define BYTE0_Msk (0x000000FF) ///< Mask to get bit0~bit7 from a 32 bit integer
+ #define BYTE1_Msk (0x0000FF00) ///< Mask to get bit8~bit15 from a 32 bit integer
+ #define BYTE2_Msk (0x00FF0000) ///< Mask to get bit16~bit23 from a 32 bit integer
+ #define BYTE3_Msk (0xFF000000) ///< Mask to get bit24~bit31 from a 32 bit integer
+
+ #define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
+ #define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
+ #define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
+ #define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
+
+ #ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+ #else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+ #endif
+ #define __O volatile /*!< Defines 'write only' permissions */
+ #define __IO volatile /*!< Defines 'read / write' permissions */
+
+ extern void __nop(void);
+
+#endif /* __N9H30_H__ */
+
+/*@}*/ /* end of group N9H30_legacy_Constants */
diff --git a/bsp/nuvoton/libraries/n9h30/Driver/Include/NuMicro.h b/bsp/nuvoton/libraries/n9h30/Driver/Include/NuMicro.h
new file mode 100644
index 0000000000000000000000000000000000000000..6e949c843dbb50a9979a60a114115be8051d67c2
--- /dev/null
+++ b/bsp/nuvoton/libraries/n9h30/Driver/Include/NuMicro.h
@@ -0,0 +1,51 @@
+/**************************************************************************//**
+ * @file NuMicro.h
+ * @version V1.00
+ * @brief NuMicro peripheral access layer header file.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NUMICRO_H__
+#define __NUMICRO_H__
+
+#include "N9H30.h"
+#include "nu_adc.h"
+#include "nu_uart.h"
+#include "nu_spi.h"
+#include "nu_i2c.h"
+#include "nu_etimer.h"
+#include "nu_emac.h"
+#include "nu_sdh.h"
+#include "nu_gpio.h"
+#include "nu_rtc.h"
+#include "nu_wdt.h"
+//#include "nu_ebi.h"
+#include "nu_scuart.h"
+#include "nu_pwm.h"
+//#include "nu_crypto.h"
+#include "nu_can.h"
+#include "nu_i2s.h"
+#include "nu_usbd.h"
+#include "nu_lcd.h"
+#include "nu_jpegcodec.h"
+#include "nu_2d.h"
+#include "nu_crypto.h"
+
+#include "nu_sys.h"
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+
+#ifndef __CLZ
+ #if defined(__CC_ARM)
+ #define __CLZ __clz
+ #else
+ #define __CLZ __builtin_clz
+ #endif
+#endif
+
+#endif /* __NUMICRO_H__ */
+
+
diff --git a/bsp/nuvoton/libraries/n9h30/Driver/Include/emac_reg.h b/bsp/nuvoton/libraries/n9h30/Driver/Include/emac_reg.h
new file mode 100644
index 0000000000000000000000000000000000000000..f9ad5efceb57f7397e1e7d671ebb59932eb74c51
--- /dev/null
+++ b/bsp/nuvoton/libraries/n9h30/Driver/Include/emac_reg.h
@@ -0,0 +1,2063 @@
+/**************************************************************************//**
+ * @file emac_reg.h
+ * @version V1.00
+ * @brief EMAC register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EMAC_REG_H__
+#define __EMAC_REG_H__
+
+#if defined ( __CC_ARM )
+ #pragma anon_unions
+#endif
+
+/**
+ @addtogroup REGISTER Control Register
+ @{
+*/
+
+/**
+ @addtogroup EMAC Ethernet MAC Controller(EMAC)
+ Memory Mapped Structure for EMAC Controller
+@{ */
+
+typedef struct
+{
+
+ /**
+ * @var EMAC_T::CAMCTL
+ * Offset: 0x00 CAM Comparison Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |AUP |Accept Unicast Packet
+ * | | |The AUP controls the unicast packet reception
+ * | | |If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address.
+ * | | |0 = EMAC receives packet depends on the CAM comparison result.
+ * | | |1 = EMAC receives all unicast packets.
+ * |[1] |AMP |Accept Multicast Packet
+ * | | |The AMP controls the multicast packet reception
+ * | | |If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address.
+ * | | |0 = EMAC receives packet depends on the CAM comparison result.
+ * | | |1 = EMAC receives all multicast packets.
+ * |[2] |ABP |Accept Broadcast Packet
+ * | | |The ABP controls the broadcast packet reception
+ * | | |If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address.
+ * | | |0 = EMAC receives packet depends on the CAM comparison result.
+ * | | |1 = EMAC receives all broadcast packets.
+ * |[3] |COMPEN |Complement CAM Comparison Enable Bit
+ * | | |The COMPEN controls the complement of the CAM comparison result
+ * | | |If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address
+ * | | |configured in CAM entry will be dropped
+ * | | |And the incoming packet with destination MAC address does not configured in any CAM entry will be received.
+ * | | |0 = Complement CAM comparison result Disabled.
+ * | | |1 = Complement CAM comparison result Enabled.
+ * |[4] |CMPEN |CAM Compare Enable Bit
+ * | | |The CMPEN controls the enable of CAM comparison function for destination MAC address recognition
+ * | | |If software wants to receive a packet with specific destination MAC address, configures the MAC address
+ * | | |into CAM 12~0, then enables that CAM entry and set CMPEN to 1.
+ * | | |0 = CAM comparison function for destination MAC address recognition Disabled.
+ * | | |1 = CAM comparison function for destination MAC address recognition Enabled.
+ * @var EMAC_T::CAMEN
+ * Offset: 0x04 CAM Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CAMxEN |CAM Entry X Enable Bit
+ * | | |The CAMxEN controls the validation of CAM entry x.
+ * | | |The CAM entry 13, 14 and 15 are for PAUSE control frame transmission
+ * | | |If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM
+ * | | |entries all must be enabled first.
+ * | | |0 = CAM entry x Disabled.
+ * | | |1 = CAM entry x Enabled.
+ * @var EMAC_T::CAM0M
+ * Offset: 0x08 CAM0 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM0L
+ * Offset: 0x0C CAM0 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM1M
+ * Offset: 0x10 CAM1 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM1L
+ * Offset: 0x14 CAM1 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM2M
+ * Offset: 0x18 CAM2 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM2L
+ * Offset: 0x1C CAM2 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM3M
+ * Offset: 0x20 CAM3 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM3L
+ * Offset: 0x24 CAM3 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM4M
+ * Offset: 0x28 CAM4 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM4L
+ * Offset: 0x2C CAM4 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM5M
+ * Offset: 0x30 CAM5 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM5L
+ * Offset: 0x34 CAM5 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM6M
+ * Offset: 0x38 CAM6 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM6L
+ * Offset: 0x3C CAM6 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM7M
+ * Offset: 0x40 CAM7 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM7L
+ * Offset: 0x44 CAM7 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM8M
+ * Offset: 0x48 CAM8 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM8L
+ * Offset: 0x4C CAM8 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM9M
+ * Offset: 0x50 CAM9 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM9L
+ * Offset: 0x54 CAM9 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM10M
+ * Offset: 0x58 CAM10 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM10L
+ * Offset: 0x5C CAM10 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM11M
+ * Offset: 0x60 CAM11 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM11L
+ * Offset: 0x64 CAM11 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM12M
+ * Offset: 0x68 CAM12 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM12L
+ * Offset: 0x6C CAM12 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM13M
+ * Offset: 0x70 CAM13 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM13L
+ * Offset: 0x74 CAM13 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM14M
+ * Offset: 0x78 CAM14 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |MACADDR2 |MAC Address Byte 2
+ * |[15:8] |MACADDR3 |MAC Address Byte 3
+ * |[23:16] |MACADDR4 |MAC Address Byte 4
+ * |[31:24] |MACADDR5 |MAC Address Byte 5
+ * | | |The CAMxM keeps the bit 47~16 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM14L
+ * Offset: 0x7C CAM14 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:16] |MACADDR0 |MAC Address Byte 0
+ * |[31:24] |MACADDR1 |MAC Address Byte 1
+ * | | |The CAMxL keeps the bit 15~0 of MAC address
+ * | | |The x can be the 0~14
+ * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.
+ * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is
+ * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
+ * @var EMAC_T::CAM15MSB
+ * Offset: 0x80 CAM15 Most Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |OPCODE |OP Code Field of PAUSE Control Frame
+ * | | |In the PAUSE control frame, an op code field defined and is 0x0001.
+ * |[31:16] |LENGTH |LENGTH Field of PAUSE Control Frame
+ * | | |In the PAUSE control frame, a LENGTH field defined and is 0x8808.
+ * @var EMAC_T::CAM15LSB
+ * Offset: 0x84 CAM15 Least Significant Word Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:24] |OPERAND |Pause Parameter
+ * | | |In the PAUSE control frame, an OPERAND field defined and controls how much time the destination
+ * | | |Ethernet MAC Controller paused
+ * | | |The unit of the OPERAND is a slot time, the 512-bit time.
+ * @var EMAC_T::TXDSA
+ * Offset: 0x88 Transmit Descriptor Link List Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |TXDSA |Transmit Descriptor Link-list Start Address
+ * | | |The TXDSA keeps the start address of transmit descriptor link-list
+ * | | |If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the
+ * | | |current transmit descriptor start address register (EMAC_CTXDSA)
+ * | | |The TXDSA does not be updated by EMAC
+ * | | |During the operation, EMAC will ignore the bits [1:0] of TXDSA
+ * | | |This means that TX descriptors must locate at word boundary memory address.
+ * @var EMAC_T::RXDSA
+ * Offset: 0x8C Receive Descriptor Link List Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RXDSA |Receive Descriptor Link-list Start Address
+ * | | |The RXDSA keeps the start address of receive descriptor link-list
+ * | | |If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current
+ * | | |receive descriptor start address register (EMAC_CRXDSA)
+ * | | |The RXDSA does not be updated by EMAC
+ * | | |During the operation, EMAC will ignore the bits [1:0] of RXDSA
+ * | | |This means that RX descriptors must locate at word boundary memory address.
+ * @var EMAC_T::CTL
+ * Offset: 0x90 MAC Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXON |Frame Reception ON
+ * | | |The RXON controls the normal packet reception of EMAC
+ * | | |If the RXON is set to high, the EMAC starts the packet reception process, including the RX
+ * | | |descriptor fetching, packet reception and RX descriptor modification.
+ * | | |It is necessary to finish EMAC initial sequence before enable RXON
+ * | | |Otherwise, the EMAC operation is undefined.
+ * | | |If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet
+ * | | |reception process after the current packet reception finished.
+ * | | |0 = Packet reception process stopped.
+ * | | |1 = Packet reception process started.
+ * |[1] |ALP |Accept Long Packet
+ * | | |The ALP controls the long packet, which packet length is greater than 1518 bytes, reception
+ * | | |If the ALP is set to high, the EMAC will accept the long packet.
+ * | | |Otherwise, the long packet will be dropped.
+ * | | |0 = Ethernet MAC controller dropped the long packet.
+ * | | |1 = Ethernet MAC controller received the long packet.
+ * |[2] |ARP |Accept Runt Packet
+ * | | |The ARP controls the runt packet, which length is less than 64 bytes, reception
+ * | | |If the ARP is set to high, the EMAC will accept the runt packet.
+ * | | |Otherwise, the runt packet will be dropped.
+ * | | |0 = Ethernet MAC controller dropped the runt packet.
+ * | | |1 = Ethernet MAC controller received the runt packet.
+ * |[3] |ACP |Accept Control Packet
+ * | | |The ACP controls the control frame reception
+ * | | |If the ACP is set to high, the EMAC will accept the control frame
+ * | | |Otherwise, the control frame will be dropped
+ * | | |It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode.
+ * | | |0 = Ethernet MAC controller dropped the control frame.
+ * | | |1 = Ethernet MAC controller received the control frame.
+ * |[4] |AEP |Accept CRC Error Packet
+ * | | |The AEP controls the EMAC accepts or drops the CRC error packet
+ * | | |If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet.
+ * | | |0 = Ethernet MAC controller dropped the CRC error packet.
+ * | | |1 = Ethernet MAC controller received the CRC error packet.
+ * |[5] |STRIPCRC |Strip CRC Checksum
+ * | | |The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum
+ * | | |If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet.
+ * | | |0 = The 4 bytes CRC checksum is included in packet length calculation.
+ * | | |1 = The 4 bytes CRC checksum is excluded in packet length calculation.
+ * |[6] |WOLEN |Wake on LAN Enable Bit
+ * | | |The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet
+ * | | |is Magic Packet and wakeup system from Power-down mode.
+ * | | |If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller
+ * | | |would generate a wakeup event to wake system up from Power-down mode.
+ * | | |0 = Wake-up by Magic Packet function Disabled.
+ * | | |1 = Wake-up by Magic Packet function Enabled.
+ * |[8] |TXON |Frame Transmission ON
+ * | | |The TXON controls the normal packet transmission of EMAC
+ * | | |If the TXON is set to high, the EMAC starts the packet transmission process, including the TX
+ * | | |descriptor fetching, packet transmission and TX descriptor modification.
+ * | | |It is must to finish EMAC initial sequence before enable TXON
+ * | | |Otherwise, the EMAC operation is undefined.
+ * | | |If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet
+ * | | |transmission process after the current packet transmission finished.
+ * | | |0 = Packet transmission process stopped.
+ * | | |1 = Packet transmission process started.
+ * |[9] |NODEF |No Deferral
+ * | | |The NODEF controls the enable of deferral exceed counter
+ * | | |If NODEF is set to high, the deferral exceed counter is disabled
+ * | | |The NODEF is only useful while EMAC is operating on half duplex mode.
+ * | | |0 = The deferral exceed counter Enabled.
+ * | | |1 = The deferral exceed counter Disabled.
+ * |[16] |SDPZ |Send PAUSE Frame
+ * | | |The SDPZ controls the PAUSE control frame transmission.
+ * | | |If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured
+ * | | |first and the corresponding CAM enable bit of CAMEN register also must be set.
+ * | | |Then, set SDPZ to 1 enables the PAUSE control frame transmission.
+ * | | |The SDPZ is a self-clear bit
+ * | | |This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically.
+ * | | |It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode.
+ * | | |0 = PAUSE control frame transmission completed.
+ * | | |1 = PAUSE control frame transmission Enabled.
+ * |[17] |SQECHKEN |SQE Checking Enable Bit
+ * | | |The SQECHKEN controls the enable of SQE checking
+ * | | |The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode
+ * | | |In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100Mbps
+ * | | |or full duplex mode.
+ * | | |0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode.
+ * | | |1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode.
+ * |[18] |FUDUP |Full Duplex Mode Selection
+ * | | |The FUDUP controls that if EMAC is operating on full or half duplex mode.
+ * | | |0 = EMAC operates in half duplex mode.
+ * | | |1 = EMAC operates in full duplex mode.
+ * |[19] |RMIIRXCTL |RMII RX Control
+ * | | |The RMIIRXCTL control the receive data sample in RMII mode
+ * | | |It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high.
+ * | | |0 = RMII RX control disabled.
+ * | | |1 = RMII RX control enabled.
+ * |[20] |OPMODE |Operation Mode Selection
+ * | | |The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode
+ * | | |The RST (EMAC_CTL[24]) would not affect OPMODE value.
+ * | | |0 = EMAC operates in 10Mbps mode.
+ * | | |1 = EMAC operates in 100Mbps mode.
+ * |[22] |RMIIEN |RMII Mode Enable Bit
+ * | | |This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII
+ * | | |interface or RMII interface
+ * | | |The RST (EMAC_CTL[24]) would not affect RMIIEN value.
+ * | | |0 = Ethernet MAC controller RMII mode Disabled.
+ * | | |1 = Ethernet MAC controller RMII mode Enabled.
+ * | | |NOTE: This field must keep 1.
+ * |[24] |RST |Software Reset
+ * | | |The RST implements a reset function to make the EMAC return default state
+ * | | |The RST is a self-clear bit
+ * | | |This means after the software reset finished, the RST will be cleared automatically
+ * | | |Enable RST can also reset all control and status registers, exclusive of the control bits
+ * | | |RMIIEN (EMAC_CTL[22]), and OPMODE (EMAC_CTL[20]).
+ * | | |The EMAC re-initial is necessary after the software reset completed.
+ * | | |0 = Software reset completed.
+ * | | |1 = Software reset Enabled.
+ * @var EMAC_T::MIIMDAT
+ * Offset: 0x94 MII Management Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |DATA |MII Management Data
+ * | | |The DATA is the 16 bits data that will be written into the registers of external PHY for MII
+ * | | |Management write command or the data from the registers of external PHY for MII Management read command.
+ * @var EMAC_T::MIIMCTL
+ * Offset: 0x98 MII Management Control and Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |PHYREG |PHY Register Address
+ * | | |The PHYREG keeps the address to indicate which register of external PHY is the target of the
+ * | | |MII management command.
+ * |[12:8] |PHYADDR |PHY Address
+ * | | |The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command.
+ * |[16] |WRITE |Write Command
+ * | | |The Write defines the MII management command is a read or write.
+ * | | |0 = MII management command is a read command.
+ * | | |1 = MII management command is a write command.
+ * |[17] |BUSY |Busy Bit
+ * | | |The BUSY controls the enable of the MII management frame generation
+ * | | |If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates
+ * | | |the MII management frame to external PHY through MII Management I/F
+ * | | |The BUSY is a self-clear bit
+ * | | |This means the BUSY will be cleared automatically after the MII management command finished.
+ * | | |0 = MII management command generation finished.
+ * | | |1 = MII management command generation Enabled.
+ * |[18] |PREAMSP |Preamble Suppress
+ * | | |The PREAMSP controls the preamble field generation of MII management frame
+ * | | |If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped.
+ * | | |0 = Preamble field generation of MII management frame not skipped.
+ * | | |1 = Preamble field generation of MII management frame skipped.
+ * |[19] |MDCON |MDC Clock ON
+ * | | |The MDC controls the MDC clock generation. If the MDCON is set to high, the MDC clock is turned on.
+ * | | |0 = MDC clock off.
+ * | | |1 = MDC clock on.
+ * @var EMAC_T::FIFOCTL
+ * Offset: 0x9C FIFO Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |RXFIFOTH |RXFIFO Low Threshold
+ * | | |The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO
+ * | | |and system memory
+ * | | |The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold
+ * | | |The low threshold is the half of high threshold always
+ * | | |During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to
+ * | | |transfer frame data from RXFIFO to system memory
+ * | | |If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame
+ * | | |data to system memory.
+ * | | |00 = Depend on the burst length setting
+ * | | |If the burst length is 8 words, high threshold is 8 words, too.
+ * | | |01 = RXFIFO high threshold is 64B and low threshold is 32B.
+ * | | |10 = RXFIFO high threshold is 128B and low threshold is 64B.
+ * | | |11 = RXFIFO high threshold is 192B and low threshold is 96B.
+ * |[9:8] |TXFIFOTH |TXFIFO Low Threshold
+ * | | |The TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system
+ * | | |memory and TXFIFO
+ * | | |The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold
+ * | | |The high threshold is the twice of low threshold always
+ * | | |During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops
+ * | | |generate request to transfer frame data from system memory to TXFIFO
+ * | | |If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data
+ * | | |from system memory to TXFIFO.
+ * | | |The TXFIFOTH also defines when the TXMAC starts to transmit frame out to network
+ * | | |The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold
+ * | | |during the transmission of the frame
+ * | | |If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame
+ * | | |out after the frame data are all inside the TXFIFO.
+ * | | |00 = Undefined.
+ * | | |01 = TXFIFO low threshold is 64B and high threshold is 128B.
+ * | | |10 = TXFIFO low threshold is 80B and high threshold is 160B.
+ * | | |11 = TXFIFO low threshold is 96B and high threshold is 192B.
+ * |[21:20] |BURSTLEN |DMA Burst Length
+ * | | |This defines the burst length of AHB bus cycle while EMAC accesses system memory.
+ * | | |00 = 4 words.
+ * | | |01 = 8 words.
+ * | | |10 = 16 words.
+ * | | |11 = 16 words.
+ * @var EMAC_T::TXST
+ * Offset: 0xA0 Transmit Start Demand Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |TXST |Transmit Start Demand
+ * | | |If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled,
+ * | | |the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted
+ * | | |After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write
+ * | | |command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission.
+ * | | |The EMAC_TXST is a write only register and read from this register is undefined.
+ * | | |The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state.
+ * @var EMAC_T::RXST
+ * Offset: 0xA4 Receive Start Demand Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RXST |Receive Start Demand
+ * | | |If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled,
+ * | | |the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted
+ * | | |After the S/W has prepared the new RX descriptor for frame reception, it must issue a write
+ * | | |command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception.
+ * | | |The EMAC_RXST is a write only register and read from this register is undefined.
+ * | | |The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state.
+ * @var EMAC_T::MRFL
+ * Offset: 0xA8 Maximum Receive Frame Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |MRFL |Maximum Receive Frame Length
+ * | | |The MRFL defines the maximum frame length for received frame
+ * | | |If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8])
+ * | | |is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered.
+ * | | |It is recommended that only use MRFL to qualify the length of received frame while S/W wants to
+ * | | |receive a frame which length is greater than 1518 bytes.
+ * @var EMAC_T::INTEN
+ * Offset: 0xAC MAC Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXIEN |Receive Interrupt Enable Bit
+ * | | |The RXIEN controls the RX interrupt generation.
+ * | | |If RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU
+ * | | |If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1]
+ * | | |is set and the corresponding bit of EMAC_INTEN is enabled
+ * | | |In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled
+ * | | |And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit.
+ * | | |0 = RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled.
+ * | | |1 = RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled.
+ * |[1] |CRCEIEN |CRC Error Interrupt Enable Bit
+ * | | |The CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation
+ * | | |If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |CRCEIF (EMAC_INTSTS[1]) is set.
+ * | | |0 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled.
+ * | | |1 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled.
+ * |[2] |RXOVIEN |Receive FIFO Overflow Interrupt Enable Bit
+ * | | |The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation
+ * | | |If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |RXOVIF (EMAC_INTSTS[2]) is set.
+ * | | |0 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled.
+ * | | |1 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled.
+ * |[3] |LPIEN |Long Packet Interrupt Enable Bit
+ * | | |The LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation
+ * | | |If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC
+ * | | |generates the RX interrupt to CPU
+ * | | |If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF
+ * | | |(EMAC_INTSTS[3]) is set.
+ * | | |0 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled.
+ * | | |1 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled.
+ * |[4] |RXGDIEN |Receive Good Interrupt Enable Bit
+ * | | |The RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation
+ * | | |If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |RXGDIF (EMAC_INTSTS[4]) is set.
+ * | | |0 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled.
+ * | | |1 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled.
+ * |[5] |ALIEIEN |Alignment Error Interrupt Enable Bit
+ * | | |The ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation
+ * | | |If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |ALIEIF (EMAC_INTSTS[5]) is set.
+ * | | |0 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled.
+ * | | |1 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled.
+ * |[6] |RPIEN |Runt Packet Interrupt Enable Bit
+ * | | |The RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation
+ * | | |If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC
+ * | | |generates the RX interrupt to CPU
+ * | | |If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |RPIF (EMAC_INTSTS[6]) is set.
+ * | | |0 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled.
+ * | | |1 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled.
+ * |[7] |MPCOVIEN |Miss Packet Counter Overrun Interrupt Enable Bit
+ * | | |The MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation
+ * | | |If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled,
+ * | | |the EMAC generates the RX interrupt to CPU
+ * | | |If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |MPCOVIF (EMAC_INTSTS[7]) is set.
+ * | | |0 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled.
+ * | | |1 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled.
+ * |[8] |MFLEIEN |Maximum Frame Length Exceed Interrupt Enable Bit
+ * | | |The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation
+ * | | |If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |MFLEIF (EMAC_INTSTS[8]) is set.
+ * | | |0 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled.
+ * | | |1 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled.
+ * |[9] |DENIEN |DMA Early Notification Interrupt Enable Bit
+ * | | |The DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation
+ * | | |If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |DENIF (EMAC_INTSTS[9]) is set.
+ * | | |0 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled.
+ * | | |1 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled.
+ * |[10] |RDUIEN |Receive Descriptor Unavailable Interrupt Enable Bit
+ * | | |The RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation
+ * | | |If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |RDUIF (EMAC_MIOSTA[10]) register is set.
+ * | | |0 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled.
+ * | | |1 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled.
+ * |[11] |RXBEIEN |Receive Bus Error Interrupt Enable Bit
+ * | | |The RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation
+ * | | |If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |RXBEIF (EMAC_INTSTS[11]) is set.
+ * | | |0 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled.
+ * | | |1 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled.
+ * |[14] |CFRIEN |Control Frame Receive Interrupt Enable Bit
+ * | | |The CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation
+ * | | |If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the
+ * | | |EMAC generates the RX interrupt to CPU
+ * | | |If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |CFRIF (EMAC_INTSTS[14]) register is set.
+ * | | |0 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled.
+ * | | |1 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled.
+ * |[15] |WOLIEN |Wake on LAN Interrupt Enable Bit
+ * | | |The WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation
+ * | | |If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled,
+ * | | |the EMAC generates the RX interrupt to CPU
+ * | | |If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the
+ * | | |WOLIF (EMAC_INTSTS[15]) is set.
+ * | | |0 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled.
+ * | | |1 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled.
+ * |[16] |TXIEN |Transmit Interrupt Enable Bit
+ * | | |The TXIEN controls the TX interrupt generation.
+ * | | |If TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU
+ * | | |If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of
+ * | | |EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled
+ * | | |In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled
+ * | | |And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit.
+ * | | |0 = TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled.
+ * | | |1 = TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled.
+ * |[17] |TXUDIEN |Transmit FIFO Underflow Interrupt Enable Bit
+ * | | |The TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation
+ * | | |If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+ * | | |the EMAC generates the TX interrupt to CPU
+ * | | |If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even
+ * | | |the TXUDIF (EMAC_INTSTS[17]) is set.
+ * | | |0 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled.
+ * | | |1 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled.
+ * |[18] |TXCPIEN |Transmit Completion Interrupt Enable Bit
+ * | | |The TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation
+ * | | |If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+ * | | |the EMAC generates the TX interrupt to CPU
+ * | | |If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+ * | | |TXCPIF (EMAC_INTSTS[18]) is set.
+ * | | |0 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled.
+ * | | |1 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled.
+ * |[19] |EXDEFIEN |Defer Exceed Interrupt Enable Bit
+ * | | |The EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation
+ * | | |If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+ * | | |the EMAC generates the TX interrupt to CPU
+ * | | |If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+ * | | |EXDEFIF (EMAC_INTSTS[19]) is set.
+ * | | |0 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled.
+ * | | |1 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled.
+ * |[20] |NCSIEN |No Carrier Sense Interrupt Enable Bit
+ * | | |The NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation
+ * | | |If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+ * | | |EMAC generates the TX interrupt to CPU
+ * | | |If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+ * | | |NCSIF (EMAC_INTSTS[20]) is set.
+ * | | |0 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled.
+ * | | |1 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled.
+ * |[21] |TXABTIEN |Transmit Abort Interrupt Enable Bit
+ * | | |The TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation
+ * | | |If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled,
+ * | | |the EMAC generates the TX interrupt to CPU
+ * | | |If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+ * | | |TXABTIF (EMAC_INTSTS[21]) is set.
+ * | | |0 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled.
+ * | | |1 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled.
+ * |[22] |LCIEN |Late Collision Interrupt Enable Bit
+ * | | |The LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation
+ * | | |If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+ * | | |EMAC generates the TX interrupt to CPU
+ * | | |If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+ * | | |LCIF (EMAC_INTSTS[22]) is set.
+ * | | |0 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled.
+ * | | |1 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled.
+ * |[23] |TDUIEN |Transmit Descriptor Unavailable Interrupt Enable Bit
+ * | | |The TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation
+ * | | |If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+ * | | |EMAC generates the TX interrupt to CPU
+ * | | |If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+ * | | |TDUIF (EMAC_INTSTS[23]) is set.
+ * | | |0 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled.
+ * | | |1 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled.
+ * |[24] |TXBEIEN |Transmit Bus Error Interrupt Enable Bit
+ * | | |The TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation
+ * | | |If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the
+ * | | |EMAC generates the TX interrupt to CPU
+ * | | |If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the
+ * | | |TXBEIF (EMAC_INTSTS[24]) is set.
+ * | | |0 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled.
+ * | | |1 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled.
+ * |[28] |TSALMIEN |Time Stamp Alarm Interrupt Enable Bit
+ * | | |The TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation
+ * | | |If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the
+ * | | |EMAC generates the TX interrupt to CPU
+ * | | |If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the
+ * | | |TXTSALMIF (EMAC_INTEN[28]) is set.
+ * | | |0 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled.
+ * | | |1 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled.
+ * @var EMAC_T::INTSTS
+ * Offset: 0xB0 MAC Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXIF |Receive Interrupt
+ * | | |The RXIF indicates the RX interrupt status.
+ * | | |If RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates
+ * | | |the EMAC generates RX interrupt to CPU
+ * | | |If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated.
+ * | | |The RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1]
+ * | | |In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in
+ * | | |EMAC_INTEN[15:1] is also enabled, the RXIF will be high.
+ * | | |Because the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too.
+ * | | |0 = No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled.
+ * | | |1 = At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in
+ * | | |EMAC_INTEN[15:1] is enabled, too.
+ * |[1] |CRCEIF |CRC Error Interrupt
+ * | | |The CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped
+ * | | |If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and
+ * | | |CRCEIF will not be set.
+ * | | |If the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the CRCEIF status.
+ * | | |0 = The frame does not incur CRC error.
+ * | | |1 = The frame incurred CRC error.
+ * |[2] |RXOVIF |Receive FIFO Overflow Interrupt
+ * | | |The RXOVIF high indicates the RXFIFO overflow occurred during packet reception
+ * | | |While the RXFIFO overflow occurred, the EMAC drops the current receiving packer
+ * | | |If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control,
+ * | | |the RXFIFOTH of FFTCR register, to higher level.
+ * | | |If the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the RXOVIF status.
+ * | | |0 = No RXFIFO overflow occurred during packet reception.
+ * | | |1 = RXFIFO overflow occurred during packet reception.
+ * |[3] |LPIF |Long Packet Interrupt Flag
+ * | | |The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the
+ * | | |incoming packet is dropped
+ * | | |If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set.
+ * | | |If the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the LPIF status.
+ * | | |0 = The incoming frame is not a long frame or S/W wants to receive a long frame.
+ * | | |1 = The incoming frame is a long frame and dropped.
+ * |[4] |RXGDIF |Receive Good Interrupt
+ * | | |The RXGDIF high indicates the frame reception has completed.
+ * | | |If the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the RXGDIF status.
+ * | | |0 = The frame reception has not complete yet.
+ * | | |1 = The frame reception has completed.
+ * |[5] |ALIEIF |Alignment Error Interrupt
+ * | | |The ALIEIF high indicates the length of the incoming frame is not a multiple of byte
+ * | | |If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the ALIEIF status.
+ * | | |0 = The frame length is a multiple of byte.
+ * | | |1 = The frame length is not a multiple of byte.
+ * |[6] |RPIF |Runt Packet Interrupt
+ * | | |The RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped
+ * | | |If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set.
+ * | | |If the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the RPIF status.
+ * | | |0 = The incoming frame is not a short frame or S/W wants to receive a short frame.
+ * | | |1 = The incoming frame is a short frame and dropped.
+ * |[7] |MPCOVIF |Missed Packet Counter Overrun Interrupt Flag
+ * | | |The MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow
+ * | | |If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the MPCOVIF status.
+ * | | |0 = The MPCNT has not rolled over yet.
+ * | | |1 = The MPCNT has rolled over yet.
+ * |[8] |MFLEIF |Maximum Frame Length Exceed Interrupt Flag
+ * | | |The MFLEIF high indicates the length of the incoming packet has exceeded the length limitation
+ * | | |configured in DMARFC register and the incoming packet is dropped
+ * | | |If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the MFLEIF status.
+ * | | |0 = The length of the incoming packet does not exceed the length limitation configured in DMARFC.
+ * | | |1 = The length of the incoming packet has exceeded the length limitation configured in DMARFC.
+ * |[9] |DENIF |DMA Early Notification Interrupt
+ * | | |The DENIF high indicates the EMAC has received the LENGTH field of the incoming packet.
+ * | | |If the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the DENIF status.
+ * | | |0 = The LENGTH field of incoming packet has not received yet.
+ * | | |1 = The LENGTH field of incoming packet has received.
+ * |[10] |RDUIF |Receive Descriptor Unavailable Interrupt
+ * | | |The RDUIF high indicates that there is no available RX descriptor for packet reception and
+ * | | |RXDMA will stay at Halt state
+ * | | |Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to
+ * | | |make RXDMA leave Halt state while new RX descriptor is available.
+ * | | |If the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the RDUIF status.
+ * | | |0 = RX descriptor is available.
+ * | | |1 = RX descriptor is unavailable.
+ * |[11] |RXBEIF |Receive Bus Error Interrupt
+ * | | |The RXBEIF high indicates the memory controller replies ERROR response while EMAC access
+ * | | |system memory through RXDMA during packet reception process
+ * | | |Reset EMAC is recommended while RXBEIF status is high.
+ * | | |If the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the RXBEIF status.
+ * | | |0 = No ERROR response is received.
+ * | | |1 = ERROR response is received.
+ * |[14] |CFRIF |Control Frame Receive Interrupt
+ * | | |The CFRIF high indicates EMAC receives a flow control frame
+ * | | |The CFRIF only available while EMAC is operating on full duplex mode.
+ * | | |If the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the CFRIF status.
+ * | | |0 = The EMAC does not receive the flow control frame.
+ * | | |1 = The EMAC receives a flow control frame.
+ * |[15] |WOLIF |Wake on LAN Interrupt Flag
+ * | | |The WOLIF high indicates EMAC receives a Magic Packet
+ * | | |The CFRIF only available while system is in power down mode and WOLEN is set high.
+ * | | |If the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high
+ * | | |Write 1 to this bit clears the WOLIF status.
+ * | | |0 = The EMAC does not receive the Magic Packet.
+ * | | |1 = The EMAC receives a Magic Packet.
+ * |[16] |TXIF |Transmit Interrupt
+ * | | |The TXIF indicates the TX interrupt status.
+ * | | |If TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates
+ * | | |the EMAC generates TX interrupt to CPU
+ * | | |If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated.
+ * | | |The TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17]
+ * | | |In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit
+ * | | |in EMAC_INTEN[28:17] is also enabled, the TXIF will be high
+ * | | |Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too.
+ * | | |0 = No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled.
+ * | | |1 = At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit
+ * | | |in EMAC_INTEN[28:17] is enabled, too.
+ * |[17] |TXUDIF |Transmit FIFO Underflow Interrupt
+ * | | |The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission
+ * | | |While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically
+ * | | |without S/W intervention
+ * | | |If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control,
+ * | | |the TXFIFOTH of FFTCR register, to higher level.
+ * | | |If the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high
+ * | | |Write 1 to this bit clears the TXUDIF status.
+ * | | |0 = No TXFIFO underflow occurred during packet transmission.
+ * | | |1 = TXFIFO underflow occurred during packet transmission.
+ * |[18] |TXCPIF |Transmit Completion Interrupt
+ * | | |The TXCPIF indicates the packet transmission has completed correctly.
+ * | | |If the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high
+ * | | |Write 1 to this bit clears the TXCPIF status.
+ * | | |0 = The packet transmission not completed.
+ * | | |1 = The packet transmission has completed.
+ * |[19] |EXDEFIF |Defer Exceed Interrupt
+ * | | |The EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms
+ * | | |on 100Mbps mode, or 3.2768ms on 10Mbps mode.
+ * | | |The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC
+ * | | |is operating on half-duplex mode.
+ * | | |If the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high
+ * | | |Write 1 to this bit clears the EXDEFIF status.
+ * | | |0 = Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
+ * | | |1 = Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
+ * |[20] |NCSIF |No Carrier Sense Interrupt
+ * | | |The NCSIF high indicates the MII I/F signal CRS does not active at the start of or during
+ * | | |the packet transmission
+ * | | |The NCSIF is only available while EMAC is operating on half-duplex mode
+ * | | |If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high.
+ * | | |Write 1 to this bit clears the NCSIF status.
+ * | | |0 = CRS signal actives correctly.
+ * | | |1 = CRS signal does not active at the start of or during the packet transmission.
+ * |[21] |TXABTIF |Transmit Abort Interrupt
+ * | | |The TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission,
+ * | | |and then the transmission process for this packet is aborted
+ * | | |The transmission abort is only available while EMAC is operating on half-duplex mode.
+ * | | |If the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high
+ * | | |Write 1 to this bit clears the TXABTIF status.
+ * | | |0 = Packet does not incur 16 consecutive collisions during transmission.
+ * | | |1 = Packet incurred 16 consecutive collisions during transmission.
+ * |[22] |LCIF |Late Collision Interrupt
+ * | | |The LCIF high indicates the collision occurred in the outside of 64 bytes collision window
+ * | | |This means after the 64 bytes of a frame has been transmitted out to the network, the collision
+ * | | |still occurred.
+ * | | |The late collision check will only be done while EMAC is operating on half-duplex mode
+ * | | |If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high.
+ * | | |Write 1 to this bit clears the LCIF status.
+ * | | |0 = No collision occurred in the outside of 64 bytes collision window.
+ * | | |1 = Collision occurred in the outside of 64 bytes collision window.
+ * |[23] |TDUIF |Transmit Descriptor Unavailable Interrupt
+ * | | |The TDUIF high indicates that there is no available TX descriptor for packet transmission and
+ * | | |TXDMA will stay at Halt state.
+ * | | |Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make
+ * | | |TXDMA leave Halt state while new TX descriptor is available.
+ * | | |If the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high.
+ * | | |Write 1 to this bit clears the TDUIF status.
+ * | | |0 = TX descriptor is available.
+ * | | |1 = TX descriptor is unavailable.
+ * |[24] |TXBEIF |Transmit Bus Error Interrupt
+ * | | |The TXBEIF high indicates the memory controller replies ERROR response while EMAC access system
+ * | | |memory through TXDMA during packet transmission process
+ * | | |Reset EMAC is recommended while TXBEIF status is high.
+ * | | |If the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high.
+ * | | |Write 1 to this bit clears the TXBEIF status.
+ * | | |0 = No ERROR response is received.
+ * | | |1 = ERROR response is received.
+ * |[28] |TSALMIF |Time Stamp Alarm Interrupt
+ * | | |The TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and
+ * | | |EMAC_TSSUBSEC register value equals to register EMAC_ALMSUBLSR.
+ * | | |If TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high.
+ * | | |Write 1 to this bit clears the TSALMIF status.
+ * | | |0 = EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC.
+ * | | |1 = EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC.
+ * @var EMAC_T::GENSTS
+ * Offset: 0xB4 MAC General Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CFR |Control Frame Received
+ * | | |The CFRIF high indicates EMAC receives a flow control frame
+ * | | |The CFRIF only available while EMAC is operating on full duplex mode.
+ * | | |0 = The EMAC does not receive the flow control frame.
+ * | | |1 = The EMAC receives a flow control frame.
+ * |[1] |RXHALT |Receive Halted
+ * | | |The RXHALT high indicates the next normal packet reception process will be halted because
+ * | | |the bit RXON of MCMDR is disabled be S/W.
+ * | | |0 = Next normal packet reception process will go on.
+ * | | |1 = Next normal packet reception process will be halted.
+ * |[2] |RXFFULL |RXFIFO Full
+ * | | |The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO
+ * | | |and the following incoming packet will be dropped.
+ * | | |0 = The RXFIFO is not full.
+ * | | |1 = The RXFIFO is full and the following incoming packet will be dropped.
+ * |[7:4] |COLCNT |Collision Count
+ * | | |The COLCNT indicates that how many collisions occurred consecutively during a packet transmission
+ * | | |If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be
+ * | | |0 and bit TXABTIF will be set to 1.
+ * |[8] |DEF |Deferred Transmission
+ * | | |The DEF high indicates the packet transmission has deferred once
+ * | | |The DEF is only available while EMAC is operating on half-duplex mode.
+ * | | |0 = Packet transmission does not defer.
+ * | | |1 = Packet transmission has deferred once.
+ * |[9] |TXPAUSED |Transmission Paused
+ * | | |The TXPAUSED high indicates the next normal packet transmission process will be paused temporally
+ * | | |because EMAC received a PAUSE control frame.
+ * | | |0 = Next normal packet transmission process will go on.
+ * | | |1 = Next normal packet transmission process will be paused.
+ * |[10] |SQE |Signal Quality Error
+ * | | |The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode
+ * | | |The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC
+ * | | |is operating on 10Mbps half-duplex mode.
+ * | | |0 = No SQE error found at end of packet transmission.
+ * | | |1 = SQE error found at end of packet transmission.
+ * |[11] |TXHALT |Transmission Halted
+ * | | |The TXHALT high indicates the next normal packet transmission process will be halted because
+ * | | |the bit TXON (EMAC_CTL[8]) is disabled be S/W.
+ * | | |0 = Next normal packet transmission process will go on.
+ * | | |1 = Next normal packet transmission process will be halted.
+ * |[12] |RPSTS |Remote Pause Status
+ * | | |The RPSTS indicates that remote pause counter down counting actives.
+ * | | |After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause
+ * | | |counter down counting
+ * | | |When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet
+ * | | |transmission until the down counting done.
+ * | | |0 = Remote pause counter down counting done.
+ * | | |1 = Remote pause counter down counting actives.
+ * @var EMAC_T::MPCNT
+ * Offset: 0xB8 Missed Packet Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |MPCNT |Miss Packet Count
+ * | | |The MPCNT indicates the number of packets that were dropped due to various types of receive errors
+ * | | |The following type of receiving error makes missed packet counter increase:
+ * | | |1. Incoming packet is incurred RXFIFO overflow.
+ * | | |2. Incoming packet is dropped due to RXON is disabled.
+ * | | |3. Incoming packet is incurred CRC error.
+ * @var EMAC_T::RPCNT
+ * Offset: 0xBC MAC Receive Pause Count Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RPCNT |MAC Receive Pause Count
+ * | | |The RPCNT keeps the OPERAND field of the PAUSE control frame
+ * | | |It indicates how many slot time (512 bit time) the TX of EMAC will be paused.
+ * @var EMAC_T::FRSTS
+ * Offset: 0xC8 DMA Receive Frame Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RXFLT |Receive Frame LENGTH
+ * | | |The RXFLT keeps the LENGTH field of each incoming Ethernet packet
+ * | | |If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has
+ * | | |received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt.
+ * | | |And, the content of LENGTH field will be stored in RXFLT.
+ * @var EMAC_T::CTXDSA
+ * Offset: 0xCC Current Transmit Descriptor Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CTXDSA |Current Transmit Descriptor Start Address
+ * | | |The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently
+ * | | |The CTXDSA is read only and write to this register has no effect.
+ * @var EMAC_T::CTXBSA
+ * Offset: 0xD0 Current Transmit Buffer Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CTXBSA |Current Transmit Buffer Start Address
+ * | | |The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently
+ * | | |The CTXBSA is read only and write to this register has no effect.
+ * @var EMAC_T::CRXDSA
+ * Offset: 0xD4 Current Receive Descriptor Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CRXDSA |Current Receive Descriptor Start Address
+ * | | |The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently
+ * | | |The CRXDSA is read only and write to this register has no effect.
+ * @var EMAC_T::CRXBSA
+ * Offset: 0xD8 Current Receive Buffer Start Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CRXBSA |Current Receive Buffer Start Address
+ * | | |The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently
+ * | | |The CRXBSA is read only and write to this register has no effect.
+ * @var EMAC_T::TSCTL
+ * Offset: 0x100 Time Stamp Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TSEN |Time Stamp Function Enable Bit
+ * | | |This bit controls if the IEEE 1588 PTP time stamp function is enabled or not.
+ * | | |Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low
+ * | | |to disable IEEE 1588 PTP time stamp function.
+ * | | |0 = I EEE 1588 PTP time stamp function Disabled.
+ * | | |1 = IEEE 1588 PTP time stamp function Enabled.
+ * |[1] |TSIEN |Time Stamp Counter Initialization Enable Bit
+ * | | |Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC
+ * | | |and EMAC_UPDSUBSEC to PTP time stamp counter.
+ * | | |After the load operation finished, Ethernet MAC controller clear this bit to low automatically.
+ * | | |0 = Time stamp counter initialization done.
+ * | | |1 = Time stamp counter initialization Enabled.
+ * |[2] |TSMODE |Time Stamp Fine Update Enable Bit
+ * | | |This bit chooses the time stamp counter update mode.
+ * | | |0 = Time stamp counter is in coarse update mode.
+ * | | |1 = Time stamp counter is in fine update mode.
+ * |[3] |TSUPDATE |Time Stamp Counter Time Update Enable Bit
+ * | | |Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and
+ * | | |EMAC_UPDSUBSEC to PTP time stamp counter.
+ * | | |After the add operation finished, Ethernet MAC controller clear this bit to low automatically.
+ * | | |0 = No action.
+ * | | |1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC.
+ * |[5] |TSALMEN |Time Stamp Alarm Enable Bit
+ * | | |Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when
+ * | | |EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
+ * | | |0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
+ * | | |1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
+ * @var EMAC_T::TSSEC
+ * Offset: 0x110 Time Stamp Counter Second Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SEC |Time Stamp Counter Second
+ * | | |This register reflects the bit [63:32] value of 64-bit reference timing counter
+ * | | |This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
+ * @var EMAC_T::TSSUBSEC
+ * Offset: 0x114 Time Stamp Counter Sub Second Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SUBSEC |Time Stamp Counter Sub-second
+ * | | |This register reflects the bit [31:0] value of 64-bit reference timing counter
+ * | | |This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
+ * @var EMAC_T::TSINC
+ * Offset: 0x118 Time Stamp Increment Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CNTINC |Time Stamp Counter Increment
+ * | | |Time stamp counter increment value.
+ * | | |If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every
+ * | | |time when it wants to increase the EMAC_TSSUBSEC value.
+ * @var EMAC_T::TSADDEND
+ * Offset: 0x11C Time Stamp Addend Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ADDEND |Time Stamp Counter Addend
+ * | | |This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC.
+ * | | |If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator
+ * | | |with this 32-bit value in each HCLK
+ * | | |Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit
+ * | | |value kept in register EMAC_TSINC.
+ * @var EMAC_T::UPDSEC
+ * Offset: 0x120 Time Stamp Update Second Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SEC |Time Stamp Counter Second Update
+ * | | |When TSIEN (EMAC_TSCTL[1]) is high
+ * | | |EMAC loads this 32-bit value to EMAC_TSSEC directly
+ * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value.
+ * @var EMAC_T::UPDSUBSEC
+ * Offset: 0x124 Time Stamp Update Sub Second Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SUBSEC |Time Stamp Counter Sub-second Update
+ * | | |When TSIEN (EMAC_TSCTL[1]) is high
+ * | | |EMAC loads this 32-bit value to EMAC_TSSUBSEC directly
+ * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value.
+ * @var EMAC_T::ALMSEC
+ * Offset: 0x128 Time Stamp Alarm Second Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SEC |Time Stamp Counter Second Alarm
+ * | | |Time stamp counter second part alarm value.
+ * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high
+ * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to
+ * | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
+ * @var EMAC_T::ALMSUBSEC
+ * Offset: 0x12C Time Stamp Alarm Sub Second Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SUBSEC |Time Stamp Counter Sub-second Alarm
+ * | | |Time stamp counter sub-second part alarm value.
+ * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high
+ * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to
+ * | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
+ */
+ __IO uint32_t CAMCTL; /*!< [0x0000] CAM Comparison Control Register */
+ __IO uint32_t CAMEN; /*!< [0x0004] CAM Enable Register */
+ __IO uint32_t CAM0M; /*!< [0x0008] CAM0 Most Significant Word Register */
+ __IO uint32_t CAM0L; /*!< [0x000c] CAM0 Least Significant Word Register */
+ __IO uint32_t CAM1M; /*!< [0x0010] CAM1 Most Significant Word Register */
+ __IO uint32_t CAM1L; /*!< [0x0014] CAM1 Least Significant Word Register */
+ __IO uint32_t CAM2M; /*!< [0x0018] CAM2 Most Significant Word Register */
+ __IO uint32_t CAM2L; /*!< [0x001c] CAM2 Least Significant Word Register */
+ __IO uint32_t CAM3M; /*!< [0x0020] CAM3 Most Significant Word Register */
+ __IO uint32_t CAM3L; /*!< [0x0024] CAM3 Least Significant Word Register */
+ __IO uint32_t CAM4M; /*!< [0x0028] CAM4 Most Significant Word Register */
+ __IO uint32_t CAM4L; /*!< [0x002c] CAM4 Least Significant Word Register */
+ __IO uint32_t CAM5M; /*!< [0x0030] CAM5 Most Significant Word Register */
+ __IO uint32_t CAM5L; /*!< [0x0034] CAM5 Least Significant Word Register */
+ __IO uint32_t CAM6M; /*!< [0x0038] CAM6 Most Significant Word Register */
+ __IO uint32_t CAM6L; /*!< [0x003c] CAM6 Least Significant Word Register */
+ __IO uint32_t CAM7M; /*!< [0x0040] CAM7 Most Significant Word Register */
+ __IO uint32_t CAM7L; /*!< [0x0044] CAM7 Least Significant Word Register */
+ __IO uint32_t CAM8M; /*!< [0x0048] CAM8 Most Significant Word Register */
+ __IO uint32_t CAM8L; /*!< [0x004c] CAM8 Least Significant Word Register */
+ __IO uint32_t CAM9M; /*!< [0x0050] CAM9 Most Significant Word Register */
+ __IO uint32_t CAM9L; /*!< [0x0054] CAM9 Least Significant Word Register */
+ __IO uint32_t CAM10M; /*!< [0x0058] CAM10 Most Significant Word Register */
+ __IO uint32_t CAM10L; /*!< [0x005c] CAM10 Least Significant Word Register */
+ __IO uint32_t CAM11M; /*!< [0x0060] CAM11 Most Significant Word Register */
+ __IO uint32_t CAM11L; /*!< [0x0064] CAM11 Least Significant Word Register */
+ __IO uint32_t CAM12M; /*!< [0x0068] CAM12 Most Significant Word Register */
+ __IO uint32_t CAM12L; /*!< [0x006c] CAM12 Least Significant Word Register */
+ __IO uint32_t CAM13M; /*!< [0x0070] CAM13 Most Significant Word Register */
+ __IO uint32_t CAM13L; /*!< [0x0074] CAM13 Least Significant Word Register */
+ __IO uint32_t CAM14M; /*!< [0x0078] CAM14 Most Significant Word Register */
+ __IO uint32_t CAM14L; /*!< [0x007c] CAM14 Least Significant Word Register */
+ __IO uint32_t CAM15MSB; /*!< [0x0080] CAM15 Most Significant Word Register */
+ __IO uint32_t CAM15LSB; /*!< [0x0084] CAM15 Least Significant Word Register */
+ __IO uint32_t TXDSA; /*!< [0x0088] Transmit Descriptor Link List Start Address Register */
+ __IO uint32_t RXDSA; /*!< [0x008c] Receive Descriptor Link List Start Address Register */
+ __IO uint32_t CTL; /*!< [0x0090] MAC Control Register */
+ __IO uint32_t MIIMDAT; /*!< [0x0094] MII Management Data Register */
+ __IO uint32_t MIIMCTL; /*!< [0x0098] MII Management Control and Address Register */
+ __IO uint32_t FIFOCTL; /*!< [0x009c] FIFO Threshold Control Register */
+ __O uint32_t TXST; /*!< [0x00a0] Transmit Start Demand Register */
+ __O uint32_t RXST; /*!< [0x00a4] Receive Start Demand Register */
+ __IO uint32_t MRFL; /*!< [0x00a8] Maximum Receive Frame Control Register */
+ __IO uint32_t INTEN; /*!< [0x00ac] MAC Interrupt Enable Register */
+ __IO uint32_t INTSTS; /*!< [0x00b0] MAC Interrupt Status Register */
+ __IO uint32_t GENSTS; /*!< [0x00b4] MAC General Status Register */
+ __IO uint32_t MPCNT; /*!< [0x00b8] Missed Packet Count Register */
+ __I uint32_t RPCNT; /*!< [0x00bc] MAC Receive Pause Count Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE0[2];
+ /** @endcond */
+ __IO uint32_t FRSTS; /*!< [0x00c8] DMA Receive Frame Status Register */
+ __I uint32_t CTXDSA; /*!< [0x00cc] Current Transmit Descriptor Start Address Register */
+ __I uint32_t CTXBSA; /*!< [0x00d0] Current Transmit Buffer Start Address Register */
+ __I uint32_t CRXDSA; /*!< [0x00d4] Current Receive Descriptor Start Address Register */
+ __I uint32_t CRXBSA; /*!< [0x00d8] Current Receive Buffer Start Address Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE1[9];
+ /** @endcond */
+ __IO uint32_t TSCTL; /*!< [0x0100] Time Stamp Control Register */
+ /** @cond HIDDEN_SYMBOLS */
+ __I uint32_t RESERVE2[3];
+ /** @endcond */
+ __I uint32_t TSSEC; /*!< [0x0110] Time Stamp Counter Second Register */
+ __I uint32_t TSSUBSEC; /*!< [0x0114] Time Stamp Counter Sub Second Register */
+ __IO uint32_t TSINC; /*!< [0x0118] Time Stamp Increment Register */
+ __IO uint32_t TSADDEND; /*!< [0x011c] Time Stamp Addend Register */
+ __IO uint32_t UPDSEC; /*!< [0x0120] Time Stamp Update Second Register */
+ __IO uint32_t UPDSUBSEC; /*!< [0x0124] Time Stamp Update Sub Second Register */
+ __IO uint32_t ALMSEC; /*!< [0x0128] Time Stamp Alarm Second Register */
+ __IO uint32_t ALMSUBSEC; /*!< [0x012c] Time Stamp Alarm Sub Second Register */
+
+} EMAC_T;
+
+/**
+ @addtogroup EMAC_CONST EMAC Bit Field Definition
+ Constant Definitions for EMAC Controller
+@{ */
+
+#define EMAC_CAMCTL_AUP_Pos (0) /*!< EMAC_T::CAMCTL: AUP Position */
+#define EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos) /*!< EMAC_T::CAMCTL: AUP Mask */
+
+#define EMAC_CAMCTL_AMP_Pos (1) /*!< EMAC_T::CAMCTL: AMP Position */
+#define EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos) /*!< EMAC_T::CAMCTL: AMP Mask */
+
+#define EMAC_CAMCTL_ABP_Pos (2) /*!< EMAC_T::CAMCTL: ABP Position */
+#define EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos) /*!< EMAC_T::CAMCTL: ABP Mask */
+
+#define EMAC_CAMCTL_COMPEN_Pos (3) /*!< EMAC_T::CAMCTL: COMPEN Position */
+#define EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos) /*!< EMAC_T::CAMCTL: COMPEN Mask */
+
+#define EMAC_CAMCTL_CMPEN_Pos (4) /*!< EMAC_T::CAMCTL: CMPEN Position */
+#define EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos) /*!< EMAC_T::CAMCTL: CMPEN Mask */
+
+#define EMAC_CAMEN_CAMxEN_Pos (0) /*!< EMAC_T::CAMEN: CAMxEN Position */
+#define EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos) /*!< EMAC_T::CAMEN: CAMxEN Mask */
+
+#define EMAC_CAM0M_MACADDR2_Pos (0) /*!< EMAC_T::CAM0M: MACADDR2 Position */
+#define EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos) /*!< EMAC_T::CAM0M: MACADDR2 Mask */
+
+#define EMAC_CAM0M_MACADDR3_Pos (8) /*!< EMAC_T::CAM0M: MACADDR3 Position */
+#define EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos) /*!< EMAC_T::CAM0M: MACADDR3 Mask */
+
+#define EMAC_CAM0M_MACADDR4_Pos (16) /*!< EMAC_T::CAM0M: MACADDR4 Position */
+#define EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos) /*!< EMAC_T::CAM0M: MACADDR4 Mask */
+
+#define EMAC_CAM0M_MACADDR5_Pos (24) /*!< EMAC_T::CAM0M: MACADDR5 Position */
+#define EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos) /*!< EMAC_T::CAM0M: MACADDR5 Mask */
+
+#define EMAC_CAM0L_MACADDR0_Pos (16) /*!< EMAC_T::CAM0L: MACADDR0 Position */
+#define EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos) /*!< EMAC_T::CAM0L: MACADDR0 Mask */
+
+#define EMAC_CAM0L_MACADDR1_Pos (24) /*!< EMAC_T::CAM0L: MACADDR1 Position */
+#define EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos) /*!< EMAC_T::CAM0L: MACADDR1 Mask */
+
+#define EMAC_CAM1M_MACADDR2_Pos (0) /*!< EMAC_T::CAM1M: MACADDR2 Position */
+#define EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos) /*!< EMAC_T::CAM1M: MACADDR2 Mask */
+
+#define EMAC_CAM1M_MACADDR3_Pos (8) /*!< EMAC_T::CAM1M: MACADDR3 Position */
+#define EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos) /*!< EMAC_T::CAM1M: MACADDR3 Mask */
+
+#define EMAC_CAM1M_MACADDR4_Pos (16) /*!< EMAC_T::CAM1M: MACADDR4 Position */
+#define EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos) /*!< EMAC_T::CAM1M: MACADDR4 Mask */
+
+#define EMAC_CAM1M_MACADDR5_Pos (24) /*!< EMAC_T::CAM1M: MACADDR5 Position */
+#define EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos) /*!< EMAC_T::CAM1M: MACADDR5 Mask */
+
+#define EMAC_CAM1L_MACADDR0_Pos (16) /*!< EMAC_T::CAM1L: MACADDR0 Position */
+#define EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos) /*!< EMAC_T::CAM1L: MACADDR0 Mask */
+
+#define EMAC_CAM1L_MACADDR1_Pos (24) /*!< EMAC_T::CAM1L: MACADDR1 Position */
+#define EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos) /*!< EMAC_T::CAM1L: MACADDR1 Mask */
+
+#define EMAC_CAM2M_MACADDR2_Pos (0) /*!< EMAC_T::CAM2M: MACADDR2 Position */
+#define EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos) /*!< EMAC_T::CAM2M: MACADDR2 Mask */
+
+#define EMAC_CAM2M_MACADDR3_Pos (8) /*!< EMAC_T::CAM2M: MACADDR3 Position */
+#define EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos) /*!< EMAC_T::CAM2M: MACADDR3 Mask */
+
+#define EMAC_CAM2M_MACADDR4_Pos (16) /*!< EMAC_T::CAM2M: MACADDR4 Position */
+#define EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos) /*!< EMAC_T::CAM2M: MACADDR4 Mask */
+
+#define EMAC_CAM2M_MACADDR5_Pos (24) /*!< EMAC_T::CAM2M: MACADDR5 Position */
+#define EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos) /*!< EMAC_T::CAM2M: MACADDR5 Mask */
+
+#define EMAC_CAM2L_MACADDR0_Pos (16) /*!< EMAC_T::CAM2L: MACADDR0 Position */
+#define EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos) /*!< EMAC_T::CAM2L: MACADDR0 Mask */
+
+#define EMAC_CAM2L_MACADDR1_Pos (24) /*!< EMAC_T::CAM2L: MACADDR1 Position */
+#define EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos) /*!< EMAC_T::CAM2L: MACADDR1 Mask */
+
+#define EMAC_CAM3M_MACADDR2_Pos (0) /*!< EMAC_T::CAM3M: MACADDR2 Position */
+#define EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos) /*!< EMAC_T::CAM3M: MACADDR2 Mask */
+
+#define EMAC_CAM3M_MACADDR3_Pos (8) /*!< EMAC_T::CAM3M: MACADDR3 Position */
+#define EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos) /*!< EMAC_T::CAM3M: MACADDR3 Mask */
+
+#define EMAC_CAM3M_MACADDR4_Pos (16) /*!< EMAC_T::CAM3M: MACADDR4 Position */
+#define EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos) /*!< EMAC_T::CAM3M: MACADDR4 Mask */
+
+#define EMAC_CAM3M_MACADDR5_Pos (24) /*!< EMAC_T::CAM3M: MACADDR5 Position */
+#define EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos) /*!< EMAC_T::CAM3M: MACADDR5 Mask */
+
+#define EMAC_CAM3L_MACADDR0_Pos (16) /*!< EMAC_T::CAM3L: MACADDR0 Position */
+#define EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos) /*!< EMAC_T::CAM3L: MACADDR0 Mask */
+
+#define EMAC_CAM3L_MACADDR1_Pos (24) /*!< EMAC_T::CAM3L: MACADDR1 Position */
+#define EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos) /*!< EMAC_T::CAM3L: MACADDR1 Mask */
+
+#define EMAC_CAM4M_MACADDR2_Pos (0) /*!< EMAC_T::CAM4M: MACADDR2 Position */
+#define EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos) /*!< EMAC_T::CAM4M: MACADDR2 Mask */
+
+#define EMAC_CAM4M_MACADDR3_Pos (8) /*!< EMAC_T::CAM4M: MACADDR3 Position */
+#define EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos) /*!< EMAC_T::CAM4M: MACADDR3 Mask */
+
+#define EMAC_CAM4M_MACADDR4_Pos (16) /*!< EMAC_T::CAM4M: MACADDR4 Position */
+#define EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos) /*!< EMAC_T::CAM4M: MACADDR4 Mask */
+
+#define EMAC_CAM4M_MACADDR5_Pos (24) /*!< EMAC_T::CAM4M: MACADDR5 Position */
+#define EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos) /*!< EMAC_T::CAM4M: MACADDR5 Mask */
+
+#define EMAC_CAM4L_MACADDR0_Pos (16) /*!< EMAC_T::CAM4L: MACADDR0 Position */
+#define EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos) /*!< EMAC_T::CAM4L: MACADDR0 Mask */
+
+#define EMAC_CAM4L_MACADDR1_Pos (24) /*!< EMAC_T::CAM4L: MACADDR1 Position */
+#define EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos) /*!< EMAC_T::CAM4L: MACADDR1 Mask */
+
+#define EMAC_CAM5M_MACADDR2_Pos (0) /*!< EMAC_T::CAM5M: MACADDR2 Position */
+#define EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos) /*!< EMAC_T::CAM5M: MACADDR2 Mask */
+
+#define EMAC_CAM5M_MACADDR3_Pos (8) /*!< EMAC_T::CAM5M: MACADDR3 Position */
+#define EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos) /*!< EMAC_T::CAM5M: MACADDR3 Mask */
+
+#define EMAC_CAM5M_MACADDR4_Pos (16) /*!< EMAC_T::CAM5M: MACADDR4 Position */
+#define EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos) /*!< EMAC_T::CAM5M: MACADDR4 Mask */
+
+#define EMAC_CAM5M_MACADDR5_Pos (24) /*!< EMAC_T::CAM5M: MACADDR5 Position */
+#define EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos) /*!< EMAC_T::CAM5M: MACADDR5 Mask */
+
+#define EMAC_CAM5L_MACADDR0_Pos (16) /*!< EMAC_T::CAM5L: MACADDR0 Position */
+#define EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos) /*!< EMAC_T::CAM5L: MACADDR0 Mask */
+
+#define EMAC_CAM5L_MACADDR1_Pos (24) /*!< EMAC_T::CAM5L: MACADDR1 Position */
+#define EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos) /*!< EMAC_T::CAM5L: MACADDR1 Mask */
+
+#define EMAC_CAM6M_MACADDR2_Pos (0) /*!< EMAC_T::CAM6M: MACADDR2 Position */
+#define EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos) /*!< EMAC_T::CAM6M: MACADDR2 Mask */
+
+#define EMAC_CAM6M_MACADDR3_Pos (8) /*!< EMAC_T::CAM6M: MACADDR3 Position */
+#define EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos) /*!< EMAC_T::CAM6M: MACADDR3 Mask */
+
+#define EMAC_CAM6M_MACADDR4_Pos (16) /*!< EMAC_T::CAM6M: MACADDR4 Position */
+#define EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos) /*!< EMAC_T::CAM6M: MACADDR4 Mask */
+
+#define EMAC_CAM6M_MACADDR5_Pos (24) /*!< EMAC_T::CAM6M: MACADDR5 Position */
+#define EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos) /*!< EMAC_T::CAM6M: MACADDR5 Mask */
+
+#define EMAC_CAM6L_MACADDR0_Pos (16) /*!< EMAC_T::CAM6L: MACADDR0 Position */
+#define EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos) /*!< EMAC_T::CAM6L: MACADDR0 Mask */
+
+#define EMAC_CAM6L_MACADDR1_Pos (24) /*!< EMAC_T::CAM6L: MACADDR1 Position */
+#define EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos) /*!< EMAC_T::CAM6L: MACADDR1 Mask */
+
+#define EMAC_CAM7M_MACADDR2_Pos (0) /*!< EMAC_T::CAM7M: MACADDR2 Position */
+#define EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos) /*!< EMAC_T::CAM7M: MACADDR2 Mask */
+
+#define EMAC_CAM7M_MACADDR3_Pos (8) /*!< EMAC_T::CAM7M: MACADDR3 Position */
+#define EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos) /*!< EMAC_T::CAM7M: MACADDR3 Mask */
+
+#define EMAC_CAM7M_MACADDR4_Pos (16) /*!< EMAC_T::CAM7M: MACADDR4 Position */
+#define EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos) /*!< EMAC_T::CAM7M: MACADDR4 Mask */
+
+#define EMAC_CAM7M_MACADDR5_Pos (24) /*!< EMAC_T::CAM7M: MACADDR5 Position */
+#define EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos) /*!< EMAC_T::CAM7M: MACADDR5 Mask */
+
+#define EMAC_CAM7L_MACADDR0_Pos (16) /*!< EMAC_T::CAM7L: MACADDR0 Position */
+#define EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos) /*!< EMAC_T::CAM7L: MACADDR0 Mask */
+
+#define EMAC_CAM7L_MACADDR1_Pos (24) /*!< EMAC_T::CAM7L: MACADDR1 Position */
+#define EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos) /*!< EMAC_T::CAM7L: MACADDR1 Mask */
+
+#define EMAC_CAM8M_MACADDR2_Pos (0) /*!< EMAC_T::CAM8M: MACADDR2 Position */
+#define EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos) /*!< EMAC_T::CAM8M: MACADDR2 Mask */
+
+#define EMAC_CAM8M_MACADDR3_Pos (8) /*!< EMAC_T::CAM8M: MACADDR3 Position */
+#define EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos) /*!< EMAC_T::CAM8M: MACADDR3 Mask */
+
+#define EMAC_CAM8M_MACADDR4_Pos (16) /*!< EMAC_T::CAM8M: MACADDR4 Position */
+#define EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos) /*!< EMAC_T::CAM8M: MACADDR4 Mask */
+
+#define EMAC_CAM8M_MACADDR5_Pos (24) /*!< EMAC_T::CAM8M: MACADDR5 Position */
+#define EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos) /*!< EMAC_T::CAM8M: MACADDR5 Mask */
+
+#define EMAC_CAM8L_MACADDR0_Pos (16) /*!< EMAC_T::CAM8L: MACADDR0 Position */
+#define EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos) /*!< EMAC_T::CAM8L: MACADDR0 Mask */
+
+#define EMAC_CAM8L_MACADDR1_Pos (24) /*!< EMAC_T::CAM8L: MACADDR1 Position */
+#define EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos) /*!< EMAC_T::CAM8L: MACADDR1 Mask */
+
+#define EMAC_CAM9M_MACADDR2_Pos (0) /*!< EMAC_T::CAM9M: MACADDR2 Position */
+#define EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos) /*!< EMAC_T::CAM9M: MACADDR2 Mask */
+
+#define EMAC_CAM9M_MACADDR3_Pos (8) /*!< EMAC_T::CAM9M: MACADDR3 Position */
+#define EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos) /*!< EMAC_T::CAM9M: MACADDR3 Mask */
+
+#define EMAC_CAM9M_MACADDR4_Pos (16) /*!< EMAC_T::CAM9M: MACADDR4 Position */
+#define EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos) /*!< EMAC_T::CAM9M: MACADDR4 Mask */
+
+#define EMAC_CAM9M_MACADDR5_Pos (24) /*!< EMAC_T::CAM9M: MACADDR5 Position */
+#define EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos) /*!< EMAC_T::CAM9M: MACADDR5 Mask */
+
+#define EMAC_CAM9L_MACADDR0_Pos (16) /*!< EMAC_T::CAM9L: MACADDR0 Position */
+#define EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos) /*!< EMAC_T::CAM9L: MACADDR0 Mask */
+
+#define EMAC_CAM9L_MACADDR1_Pos (24) /*!< EMAC_T::CAM9L: MACADDR1 Position */
+#define EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos) /*!< EMAC_T::CAM9L: MACADDR1 Mask */
+
+#define EMAC_CAM10M_MACADDR2_Pos (0) /*!< EMAC_T::CAM10M: MACADDR2 Position */
+#define EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos) /*!< EMAC_T::CAM10M: MACADDR2 Mask */
+
+#define EMAC_CAM10M_MACADDR3_Pos (8) /*!< EMAC_T::CAM10M: MACADDR3 Position */
+#define EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos) /*!< EMAC_T::CAM10M: MACADDR3 Mask */
+
+#define EMAC_CAM10M_MACADDR4_Pos (16) /*!< EMAC_T::CAM10M: MACADDR4 Position */
+#define EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos) /*!< EMAC_T::CAM10M: MACADDR4 Mask */
+
+#define EMAC_CAM10M_MACADDR5_Pos (24) /*!< EMAC_T::CAM10M: MACADDR5 Position */
+#define EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos) /*!< EMAC_T::CAM10M: MACADDR5 Mask */
+
+#define EMAC_CAM10L_MACADDR0_Pos (16) /*!< EMAC_T::CAM10L: MACADDR0 Position */
+#define EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos) /*!< EMAC_T::CAM10L: MACADDR0 Mask */
+
+#define EMAC_CAM10L_MACADDR1_Pos (24) /*!< EMAC_T::CAM10L: MACADDR1 Position */
+#define EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos) /*!< EMAC_T::CAM10L: MACADDR1 Mask */
+
+#define EMAC_CAM11M_MACADDR2_Pos (0) /*!< EMAC_T::CAM11M: MACADDR2 Position */
+#define EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos) /*!< EMAC_T::CAM11M: MACADDR2 Mask */
+
+#define EMAC_CAM11M_MACADDR3_Pos (8) /*!< EMAC_T::CAM11M: MACADDR3 Position */
+#define EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos) /*!< EMAC_T::CAM11M: MACADDR3 Mask */
+
+#define EMAC_CAM11M_MACADDR4_Pos (16) /*!< EMAC_T::CAM11M: MACADDR4 Position */
+#define EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos) /*!< EMAC_T::CAM11M: MACADDR4 Mask */
+
+#define EMAC_CAM11M_MACADDR5_Pos (24) /*!< EMAC_T::CAM11M: MACADDR5 Position */
+#define EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos) /*!< EMAC_T::CAM11M: MACADDR5 Mask */
+
+#define EMAC_CAM11L_MACADDR0_Pos (16) /*!< EMAC_T::CAM11L: MACADDR0 Position */
+#define EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos) /*!< EMAC_T::CAM11L: MACADDR0 Mask */
+
+#define EMAC_CAM11L_MACADDR1_Pos (24) /*!< EMAC_T::CAM11L: MACADDR1 Position */
+#define EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos) /*!< EMAC_T::CAM11L: MACADDR1 Mask */
+
+#define EMAC_CAM12M_MACADDR2_Pos (0) /*!< EMAC_T::CAM12M: MACADDR2 Position */
+#define EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos) /*!< EMAC_T::CAM12M: MACADDR2 Mask */
+
+#define EMAC_CAM12M_MACADDR3_Pos (8) /*!< EMAC_T::CAM12M: MACADDR3 Position */
+#define EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos) /*!< EMAC_T::CAM12M: MACADDR3 Mask */
+
+#define EMAC_CAM12M_MACADDR4_Pos (16) /*!< EMAC_T::CAM12M: MACADDR4 Position */
+#define EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos) /*!< EMAC_T::CAM12M: MACADDR4 Mask */
+
+#define EMAC_CAM12M_MACADDR5_Pos (24) /*!< EMAC_T::CAM12M: MACADDR5 Position */
+#define EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos) /*!< EMAC_T::CAM12M: MACADDR5 Mask */
+
+#define EMAC_CAM12L_MACADDR0_Pos (16) /*!< EMAC_T::CAM12L: MACADDR0 Position */
+#define EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos) /*!< EMAC_T::CAM12L: MACADDR0 Mask */
+
+#define EMAC_CAM12L_MACADDR1_Pos (24) /*!< EMAC_T::CAM12L: MACADDR1 Position */
+#define EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos) /*!< EMAC_T::CAM12L: MACADDR1 Mask */
+
+#define EMAC_CAM13M_MACADDR2_Pos (0) /*!< EMAC_T::CAM13M: MACADDR2 Position */
+#define EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos) /*!< EMAC_T::CAM13M: MACADDR2 Mask */
+
+#define EMAC_CAM13M_MACADDR3_Pos (8) /*!< EMAC_T::CAM13M: MACADDR3 Position */
+#define EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos) /*!< EMAC_T::CAM13M: MACADDR3 Mask */
+
+#define EMAC_CAM13M_MACADDR4_Pos (16) /*!< EMAC_T::CAM13M: MACADDR4 Position */
+#define EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos) /*!< EMAC_T::CAM13M: MACADDR4 Mask */
+
+#define EMAC_CAM13M_MACADDR5_Pos (24) /*!< EMAC_T::CAM13M: MACADDR5 Position */
+#define EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos) /*!< EMAC_T::CAM13M: MACADDR5 Mask */
+
+#define EMAC_CAM13L_MACADDR0_Pos (16) /*!< EMAC_T::CAM13L: MACADDR0 Position */
+#define EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos) /*!< EMAC_T::CAM13L: MACADDR0 Mask */
+
+#define EMAC_CAM13L_MACADDR1_Pos (24) /*!< EMAC_T::CAM13L: MACADDR1 Position */
+#define EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos) /*!< EMAC_T::CAM13L: MACADDR1 Mask */
+
+#define EMAC_CAM14M_MACADDR2_Pos (0) /*!< EMAC_T::CAM14M: MACADDR2 Position */
+#define EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos) /*!< EMAC_T::CAM14M: MACADDR2 Mask */
+
+#define EMAC_CAM14M_MACADDR3_Pos (8) /*!< EMAC_T::CAM14M: MACADDR3 Position */
+#define EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos) /*!< EMAC_T::CAM14M: MACADDR3 Mask */
+
+#define EMAC_CAM14M_MACADDR4_Pos (16) /*!< EMAC_T::CAM14M: MACADDR4 Position */
+#define EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos) /*!< EMAC_T::CAM14M: MACADDR4 Mask */
+
+#define EMAC_CAM14M_MACADDR5_Pos (24) /*!< EMAC_T::CAM14M: MACADDR5 Position */
+#define EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos) /*!< EMAC_T::CAM14M: MACADDR5 Mask */
+
+#define EMAC_CAM14L_MACADDR0_Pos (16) /*!< EMAC_T::CAM14L: MACADDR0 Position */
+#define EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos) /*!< EMAC_T::CAM14L: MACADDR0 Mask */
+
+#define EMAC_CAM14L_MACADDR1_Pos (24) /*!< EMAC_T::CAM14L: MACADDR1 Position */
+#define EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos) /*!< EMAC_T::CAM14L: MACADDR1 Mask */
+
+#define EMAC_CAM15MSB_OPCODE_Pos (0) /*!< EMAC_T::CAM15MSB: OPCODE Position */
+#define EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos) /*!< EMAC_T::CAM15MSB: OPCODE Mask */
+
+#define EMAC_CAM15MSB_LENGTH_Pos (16) /*!< EMAC_T::CAM15MSB: LENGTH Position */
+#define EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos) /*!< EMAC_T::CAM15MSB: LENGTH Mask */
+
+#define EMAC_CAM15LSB_OPERAND_Pos (24) /*!< EMAC_T::CAM15LSB: OPERAND Position */
+#define EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos) /*!< EMAC_T::CAM15LSB: OPERAND Mask */
+
+#define EMAC_TXDSA_TXDSA_Pos (0) /*!< EMAC_T::TXDSA: TXDSA Position */
+#define EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos) /*!< EMAC_T::TXDSA: TXDSA Mask */
+
+#define EMAC_RXDSA_RXDSA_Pos (0) /*!< EMAC_T::RXDSA: RXDSA Position */
+#define EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos) /*!< EMAC_T::RXDSA: RXDSA Mask */
+
+#define EMAC_CTL_RXON_Pos (0) /*!< EMAC_T::CTL: RXON Position */
+#define EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos) /*!< EMAC_T::CTL: RXON Mask */
+
+#define EMAC_CTL_ALP_Pos (1) /*!< EMAC_T::CTL: ALP Position */
+#define EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos) /*!< EMAC_T::CTL: ALP Mask */
+
+#define EMAC_CTL_ARP_Pos (2) /*!< EMAC_T::CTL: ARP Position */
+#define EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos) /*!< EMAC_T::CTL: ARP Mask */
+
+#define EMAC_CTL_ACP_Pos (3) /*!< EMAC_T::CTL: ACP Position */
+#define EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos) /*!< EMAC_T::CTL: ACP Mask */
+
+#define EMAC_CTL_AEP_Pos (4) /*!< EMAC_T::CTL: AEP Position */
+#define EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos) /*!< EMAC_T::CTL: AEP Mask */
+
+#define EMAC_CTL_STRIPCRC_Pos (5) /*!< EMAC_T::CTL: STRIPCRC Position */
+#define EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos) /*!< EMAC_T::CTL: STRIPCRC Mask */
+
+#define EMAC_CTL_WOLEN_Pos (6) /*!< EMAC_T::CTL: WOLEN Position */
+#define EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos) /*!< EMAC_T::CTL: WOLEN Mask */
+
+#define EMAC_CTL_TXON_Pos (8) /*!< EMAC_T::CTL: TXON Position */
+#define EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos) /*!< EMAC_T::CTL: TXON Mask */
+
+#define EMAC_CTL_NODEF_Pos (9) /*!< EMAC_T::CTL: NODEF Position */
+#define EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos) /*!< EMAC_T::CTL: NODEF Mask */
+
+#define EMAC_CTL_SDPZ_Pos (16) /*!< EMAC_T::CTL: SDPZ Position */
+#define EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos) /*!< EMAC_T::CTL: SDPZ Mask */
+
+#define EMAC_CTL_SQECHKEN_Pos (17) /*!< EMAC_T::CTL: SQECHKEN Position */
+#define EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos) /*!< EMAC_T::CTL: SQECHKEN Mask */
+
+#define EMAC_CTL_FUDUP_Pos (18) /*!< EMAC_T::CTL: FUDUP Position */
+#define EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos) /*!< EMAC_T::CTL: FUDUP Mask */
+
+#define EMAC_CTL_RMIIRXCTL_Pos (19) /*!< EMAC_T::CTL: RMIIRXCTL Position */
+#define EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos) /*!< EMAC_T::CTL: RMIIRXCTL Mask */
+
+#define EMAC_CTL_OPMODE_Pos (20) /*!< EMAC_T::CTL: OPMODE Position */
+#define EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos) /*!< EMAC_T::CTL: OPMODE Mask */
+
+#define EMAC_CTL_RMIIEN_Pos (22) /*!< EMAC_T::CTL: RMIIEN Position */
+#define EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos) /*!< EMAC_T::CTL: RMIIEN Mask */
+
+#define EMAC_CTL_RST_Pos (24) /*!< EMAC_T::CTL: RST Position */
+#define EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos) /*!< EMAC_T::CTL: RST Mask */
+
+#define EMAC_MIIMDAT_DATA_Pos (0) /*!< EMAC_T::MIIMDAT: DATA Position */
+#define EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos) /*!< EMAC_T::MIIMDAT: DATA Mask */
+
+#define EMAC_MIIMCTL_PHYREG_Pos (0) /*!< EMAC_T::MIIMCTL: PHYREG Position */
+#define EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos) /*!< EMAC_T::MIIMCTL: PHYREG Mask */
+
+#define EMAC_MIIMCTL_PHYADDR_Pos (8) /*!< EMAC_T::MIIMCTL: PHYADDR Position */
+#define EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos) /*!< EMAC_T::MIIMCTL: PHYADDR Mask */
+
+#define EMAC_MIIMCTL_WRITE_Pos (16) /*!< EMAC_T::MIIMCTL: WRITE Position */
+#define EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos) /*!< EMAC_T::MIIMCTL: WRITE Mask */
+
+#define EMAC_MIIMCTL_BUSY_Pos (17) /*!< EMAC_T::MIIMCTL: BUSY Position */
+#define EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos) /*!< EMAC_T::MIIMCTL: BUSY Mask */
+
+#define EMAC_MIIMCTL_PREAMSP_Pos (18) /*!< EMAC_T::MIIMCTL: PREAMSP Position */
+#define EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos) /*!< EMAC_T::MIIMCTL: PREAMSP Mask */
+
+#define EMAC_MIIMCTL_MDCON_Pos (19) /*!< EMAC_T::MIIMCTL: MDCON Position */
+#define EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos) /*!< EMAC_T::MIIMCTL: MDCON Mask */
+
+#define EMAC_FIFOCTL_RXFIFOTH_Pos (0) /*!< EMAC_T::FIFOCTL: RXFIFOTH Position */
+#define EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: RXFIFOTH Mask */
+
+#define EMAC_FIFOCTL_TXFIFOTH_Pos (8) /*!< EMAC_T::FIFOCTL: TXFIFOTH Position */
+#define EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: TXFIFOTH Mask */
+
+#define EMAC_FIFOCTL_BURSTLEN_Pos (20) /*!< EMAC_T::FIFOCTL: BURSTLEN Position */
+#define EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos) /*!< EMAC_T::FIFOCTL: BURSTLEN Mask */
+
+#define EMAC_TXST_TXST_Pos (0) /*!< EMAC_T::TXST: TXST Position */
+#define EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos) /*!< EMAC_T::TXST: TXST Mask */
+
+#define EMAC_RXST_RXST_Pos (0) /*!< EMAC_T::RXST: RXST Position */
+#define EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos) /*!< EMAC_T::RXST: RXST Mask */
+
+#define EMAC_MRFL_MRFL_Pos (0) /*!< EMAC_T::MRFL: MRFL Position */
+#define EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos) /*!< EMAC_T::MRFL: MRFL Mask */
+
+#define EMAC_INTEN_RXIEN_Pos (0) /*!< EMAC_T::INTEN: RXIEN Position */
+#define EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos) /*!< EMAC_T::INTEN: RXIEN Mask */
+
+#define EMAC_INTEN_CRCEIEN_Pos (1) /*!< EMAC_T::INTEN: CRCEIEN Position */
+#define EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos) /*!< EMAC_T::INTEN: CRCEIEN Mask */
+
+#define EMAC_INTEN_RXOVIEN_Pos (2) /*!< EMAC_T::INTEN: RXOVIEN Position */
+#define EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos) /*!< EMAC_T::INTEN: RXOVIEN Mask */
+
+#define EMAC_INTEN_LPIEN_Pos (3) /*!< EMAC_T::INTEN: LPIEN Position */
+#define EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos) /*!< EMAC_T::INTEN: LPIEN Mask */
+
+#define EMAC_INTEN_RXGDIEN_Pos (4) /*!< EMAC_T::INTEN: RXGDIEN Position */
+#define EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos) /*!< EMAC_T::INTEN: RXGDIEN Mask */
+
+#define EMAC_INTEN_ALIEIEN_Pos (5) /*!< EMAC_T::INTEN: ALIEIEN Position */
+#define EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos) /*!< EMAC_T::INTEN: ALIEIEN Mask */
+
+#define EMAC_INTEN_RPIEN_Pos (6) /*!< EMAC_T::INTEN: RPIEN Position */
+#define EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos) /*!< EMAC_T::INTEN: RPIEN Mask */
+
+#define EMAC_INTEN_MPCOVIEN_Pos (7) /*!< EMAC_T::INTEN: MPCOVIEN Position */
+#define EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos) /*!< EMAC_T::INTEN: MPCOVIEN Mask */
+
+#define EMAC_INTEN_MFLEIEN_Pos (8) /*!< EMAC_T::INTEN: MFLEIEN Position */
+#define EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos) /*!< EMAC_T::INTEN: MFLEIEN Mask */
+
+#define EMAC_INTEN_DENIEN_Pos (9) /*!< EMAC_T::INTEN: DENIEN Position */
+#define EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos) /*!< EMAC_T::INTEN: DENIEN Mask */
+
+#define EMAC_INTEN_RDUIEN_Pos (10) /*!< EMAC_T::INTEN: RDUIEN Position */
+#define EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos) /*!< EMAC_T::INTEN: RDUIEN Mask */
+
+#define EMAC_INTEN_RXBEIEN_Pos (11) /*!< EMAC_T::INTEN: RXBEIEN Position */
+#define EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos) /*!< EMAC_T::INTEN: RXBEIEN Mask */
+
+#define EMAC_INTEN_CFRIEN_Pos (14) /*!< EMAC_T::INTEN: CFRIEN Position */
+#define EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos) /*!< EMAC_T::INTEN: CFRIEN Mask */
+
+#define EMAC_INTEN_WOLIEN_Pos (15) /*!< EMAC_T::INTEN: WOLIEN Position */
+#define EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos) /*!< EMAC_T::INTEN: WOLIEN Mask */
+
+#define EMAC_INTEN_TXIEN_Pos (16) /*!< EMAC_T::INTEN: TXIEN Position */
+#define EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos) /*!< EMAC_T::INTEN: TXIEN Mask */
+
+#define EMAC_INTEN_TXUDIEN_Pos (17) /*!< EMAC_T::INTEN: TXUDIEN Position */
+#define EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos) /*!< EMAC_T::INTEN: TXUDIEN Mask */
+
+#define EMAC_INTEN_TXCPIEN_Pos (18) /*!< EMAC_T::INTEN: TXCPIEN Position */
+#define EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos) /*!< EMAC_T::INTEN: TXCPIEN Mask */
+
+#define EMAC_INTEN_EXDEFIEN_Pos (19) /*!< EMAC_T::INTEN: EXDEFIEN Position */
+#define EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos) /*!< EMAC_T::INTEN: EXDEFIEN Mask */
+
+#define EMAC_INTEN_NCSIEN_Pos (20) /*!< EMAC_T::INTEN: NCSIEN Position */
+#define EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos) /*!< EMAC_T::INTEN: NCSIEN Mask */
+
+#define EMAC_INTEN_TXABTIEN_Pos (21) /*!< EMAC_T::INTEN: TXABTIEN Position */
+#define EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos) /*!< EMAC_T::INTEN: TXABTIEN Mask */
+
+#define EMAC_INTEN_LCIEN_Pos (22) /*!< EMAC_T::INTEN: LCIEN Position */
+#define EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos) /*!< EMAC_T::INTEN: LCIEN Mask */
+
+#define EMAC_INTEN_TDUIEN_Pos (23) /*!< EMAC_T::INTEN: TDUIEN Position */
+#define EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos) /*!< EMAC_T::INTEN: TDUIEN Mask */
+
+#define EMAC_INTEN_TXBEIEN_Pos (24) /*!< EMAC_T::INTEN: TXBEIEN Position */
+#define EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos) /*!< EMAC_T::INTEN: TXBEIEN Mask */
+
+#define EMAC_INTEN_TSALMIEN_Pos (28) /*!< EMAC_T::INTEN: TSALMIEN Position */
+#define EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos) /*!< EMAC_T::INTEN: TSALMIEN Mask */
+
+#define EMAC_INTSTS_RXIF_Pos (0) /*!< EMAC_T::INTSTS: RXIF Position */
+#define EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos) /*!< EMAC_T::INTSTS: RXIF Mask */
+
+#define EMAC_INTSTS_CRCEIF_Pos (1) /*!< EMAC_T::INTSTS: CRCEIF Position */
+#define EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos) /*!< EMAC_T::INTSTS: CRCEIF Mask */
+
+#define EMAC_INTSTS_RXOVIF_Pos (2) /*!< EMAC_T::INTSTS: RXOVIF Position */
+#define EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos) /*!< EMAC_T::INTSTS: RXOVIF Mask */
+
+#define EMAC_INTSTS_LPIF_Pos (3) /*!< EMAC_T::INTSTS: LPIF Position */
+#define EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos) /*!< EMAC_T::INTSTS: LPIF Mask */
+
+#define EMAC_INTSTS_RXGDIF_Pos (4) /*!< EMAC_T::INTSTS: RXGDIF Position */
+#define EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos) /*!< EMAC_T::INTSTS: RXGDIF Mask */
+
+#define EMAC_INTSTS_ALIEIF_Pos (5) /*!< EMAC_T::INTSTS: ALIEIF Position */
+#define EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos) /*!< EMAC_T::INTSTS: ALIEIF Mask */
+
+#define EMAC_INTSTS_RPIF_Pos (6) /*!< EMAC_T::INTSTS: RPIF Position */
+#define EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos) /*!< EMAC_T::INTSTS: RPIF Mask */
+
+#define EMAC_INTSTS_MPCOVIF_Pos (7) /*!< EMAC_T::INTSTS: MPCOVIF Position */
+#define EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos) /*!< EMAC_T::INTSTS: MPCOVIF Mask */
+
+#define EMAC_INTSTS_MFLEIF_Pos (8) /*!< EMAC_T::INTSTS: MFLEIF Position */
+#define EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos) /*!< EMAC_T::INTSTS: MFLEIF Mask */
+
+#define EMAC_INTSTS_DENIF_Pos (9) /*!< EMAC_T::INTSTS: DENIF Position */
+#define EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos) /*!< EMAC_T::INTSTS: DENIF Mask */
+
+#define EMAC_INTSTS_RDUIF_Pos (10) /*!< EMAC_T::INTSTS: RDUIF Position */
+#define EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos) /*!< EMAC_T::INTSTS: RDUIF Mask */
+
+#define EMAC_INTSTS_RXBEIF_Pos (11) /*!< EMAC_T::INTSTS: RXBEIF Position */
+#define EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos) /*!< EMAC_T::INTSTS: RXBEIF Mask */
+
+#define EMAC_INTSTS_CFRIF_Pos (14) /*!< EMAC_T::INTSTS: CFRIF Position */
+#define EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos) /*!< EMAC_T::INTSTS: CFRIF Mask */
+
+#define EMAC_INTSTS_WOLIF_Pos (15) /*!< EMAC_T::INTSTS: WOLIF Position */
+#define EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos) /*!< EMAC_T::INTSTS: WOLIF Mask */
+
+#define EMAC_INTSTS_TXIF_Pos (16) /*!< EMAC_T::INTSTS: TXIF Position */
+#define EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos) /*!< EMAC_T::INTSTS: TXIF Mask */
+
+#define EMAC_INTSTS_TXUDIF_Pos (17) /*!< EMAC_T::INTSTS: TXUDIF Position */
+#define EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos) /*!< EMAC_T::INTSTS: TXUDIF Mask */
+
+#define EMAC_INTSTS_TXCPIF_Pos (18) /*!< EMAC_T::INTSTS: TXCPIF Position */
+#define EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos) /*!< EMAC_T::INTSTS: TXCPIF Mask */
+
+#define EMAC_INTSTS_EXDEFIF_Pos (19) /*!< EMAC_T::INTSTS: EXDEFIF Position */
+#define EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos) /*!< EMAC_T::INTSTS: EXDEFIF Mask */
+
+#define EMAC_INTSTS_NCSIF_Pos (20) /*!< EMAC_T::INTSTS: NCSIF Position */
+#define EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos) /*!< EMAC_T::INTSTS: NCSIF Mask */
+
+#define EMAC_INTSTS_TXABTIF_Pos (21) /*!< EMAC_T::INTSTS: TXABTIF Position */
+#define EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos) /*!< EMAC_T::INTSTS: TXABTIF Mask */
+
+#define EMAC_INTSTS_LCIF_Pos (22) /*!< EMAC_T::INTSTS: LCIF Position */
+#define EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos) /*!< EMAC_T::INTSTS: LCIF Mask */
+
+#define EMAC_INTSTS_TDUIF_Pos (23) /*!< EMAC_T::INTSTS: TDUIF Position */
+#define EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos) /*!< EMAC_T::INTSTS: TDUIF Mask */
+
+#define EMAC_INTSTS_TXBEIF_Pos (24) /*!< EMAC_T::INTSTS: TXBEIF Position */
+#define EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos) /*!< EMAC_T::INTSTS: TXBEIF Mask */
+
+#define EMAC_INTSTS_TSALMIF_Pos (28) /*!< EMAC_T::INTSTS: TSALMIF Position */
+#define EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos) /*!< EMAC_T::INTSTS: TSALMIF Mask */
+
+#define EMAC_GENSTS_CFR_Pos (0) /*!< EMAC_T::GENSTS: CFR Position */
+#define EMAC_GENSTS_CFR_Msk (0x1ul << EMAC_GENSTS_CFR_Pos) /*!< EMAC_T::GENSTS: CFR Mask */
+
+#define EMAC_GENSTS_RXHALT_Pos (1) /*!< EMAC_T::GENSTS: RXHALT Position */
+#define EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos) /*!< EMAC_T::GENSTS: RXHALT Mask */
+
+#define EMAC_GENSTS_RXFFULL_Pos (2) /*!< EMAC_T::GENSTS: RXFFULL Position */
+#define EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos) /*!< EMAC_T::GENSTS: RXFFULL Mask */
+
+#define EMAC_GENSTS_COLCNT_Pos (4) /*!< EMAC_T::GENSTS: COLCNT Position */
+#define EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos) /*!< EMAC_T::GENSTS: COLCNT Mask */
+
+#define EMAC_GENSTS_DEF_Pos (8) /*!< EMAC_T::GENSTS: DEF Position */
+#define EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos) /*!< EMAC_T::GENSTS: DEF Mask */
+
+#define EMAC_GENSTS_TXPAUSED_Pos (9) /*!< EMAC_T::GENSTS: TXPAUSED Position */
+#define EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos) /*!< EMAC_T::GENSTS: TXPAUSED Mask */
+
+#define EMAC_GENSTS_SQE_Pos (10) /*!< EMAC_T::GENSTS: SQE Position */
+#define EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos) /*!< EMAC_T::GENSTS: SQE Mask */
+
+#define EMAC_GENSTS_TXHALT_Pos (11) /*!< EMAC_T::GENSTS: TXHALT Position */
+#define EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos) /*!< EMAC_T::GENSTS: TXHALT Mask */
+
+#define EMAC_GENSTS_RPSTS_Pos (12) /*!< EMAC_T::GENSTS: RPSTS Position */
+#define EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos) /*!< EMAC_T::GENSTS: RPSTS Mask */
+
+#define EMAC_MPCNT_MPCNT_Pos (0) /*!< EMAC_T::MPCNT: MPCNT Position */
+#define EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos) /*!< EMAC_T::MPCNT: MPCNT Mask */
+
+#define EMAC_RPCNT_RPCNT_Pos (0) /*!< EMAC_T::RPCNT: RPCNT Position */
+#define EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos) /*!< EMAC_T::RPCNT: RPCNT Mask */
+
+#define EMAC_FRSTS_RXFLT_Pos (0) /*!< EMAC_T::FRSTS: RXFLT Position */
+#define EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos) /*!< EMAC_T::FRSTS: RXFLT Mask */
+
+#define EMAC_CTXDSA_CTXDSA_Pos (0) /*!< EMAC_T::CTXDSA: CTXDSA Position */
+#define EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos) /*!< EMAC_T::CTXDSA: CTXDSA Mask */
+
+#define EMAC_CTXBSA_CTXBSA_Pos (0) /*!< EMAC_T::CTXBSA: CTXBSA Position */
+#define EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos) /*!< EMAC_T::CTXBSA: CTXBSA Mask */
+
+#define EMAC_CRXDSA_CRXDSA_Pos (0) /*!< EMAC_T::CRXDSA: CRXDSA Position */
+#define EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos) /*!< EMAC_T::CRXDSA: CRXDSA Mask */
+
+#define EMAC_CRXBSA_CRXBSA_Pos (0) /*!< EMAC_T::CRXBSA: CRXBSA Position */
+#define EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos) /*!< EMAC_T::CRXBSA: CRXBSA Mask */
+
+#define EMAC_TSCTL_TSEN_Pos (0) /*!< EMAC_T::TSCTL: TSEN Position */
+#define EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos) /*!< EMAC_T::TSCTL: TSEN Mask */
+
+#define EMAC_TSCTL_TSIEN_Pos (1) /*!< EMAC_T::TSCTL: TSIEN Position */
+#define EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos) /*!< EMAC_T::TSCTL: TSIEN Mask */
+
+#define EMAC_TSCTL_TSMODE_Pos (2) /*!< EMAC_T::TSCTL: TSMODE Position */
+#define EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos) /*!< EMAC_T::TSCTL: TSMODE Mask */
+
+#define EMAC_TSCTL_TSUPDATE_Pos (3) /*!< EMAC_T::TSCTL: TSUPDATE Position */
+#define EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos) /*!< EMAC_T::TSCTL: TSUPDATE Mask */
+
+#define EMAC_TSCTL_TSALMEN_Pos (5) /*!< EMAC_T::TSCTL: TSALMEN Position */
+#define EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos) /*!< EMAC_T::TSCTL: TSALMEN Mask */
+
+#define EMAC_TSSEC_SEC_Pos (0) /*!< EMAC_T::TSSEC: SEC Position */
+#define EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos) /*!< EMAC_T::TSSEC: SEC Mask */
+
+#define EMAC_TSSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::TSSUBSEC: SUBSEC Position */
+#define EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos) /*!< EMAC_T::TSSUBSEC: SUBSEC Mask */
+
+#define EMAC_TSINC_CNTINC_Pos (0) /*!< EMAC_T::TSINC: CNTINC Position */
+#define EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos) /*!< EMAC_T::TSINC: CNTINC Mask */
+
+#define EMAC_TSADDEND_ADDEND_Pos (0) /*!< EMAC_T::TSADDEND: ADDEND Position */
+#define EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos) /*!< EMAC_T::TSADDEND: ADDEND Mask */
+
+#define EMAC_UPDSEC_SEC_Pos (0) /*!< EMAC_T::UPDSEC: SEC Position */
+#define EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos) /*!< EMAC_T::UPDSEC: SEC Mask */
+
+#define EMAC_UPDSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::UPDSUBSEC: SUBSEC Position */
+#define EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos) /*!< EMAC_T::UPDSUBSEC: SUBSEC Mask */
+
+#define EMAC_ALMSEC_SEC_Pos (0) /*!< EMAC_T::ALMSEC: SEC Position */
+#define EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos) /*!< EMAC_T::ALMSEC: SEC Mask */
+
+#define EMAC_ALMSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::ALMSUBSEC: SUBSEC Position */
+#define EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos) /*!< EMAC_T::ALMSUBSEC: SUBSEC Mask */
+
+/**@}*/ /* EMAC_CONST */
+/**@}*/ /* end of EMAC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM )
+ #pragma no_anon_unions
+#endif
+
+#endif /* __EMAC_REG_H__ */
diff --git a/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_2d.h b/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_2d.h
new file mode 100644
index 0000000000000000000000000000000000000000..36275b15eaf7d4004324607a1c68aaefd76ad951
--- /dev/null
+++ b/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_2d.h
@@ -0,0 +1,190 @@
+/**************************************************************************//**
+* @file 2d.h
+* @brief N9H30 2DGE driver header file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NU_2D_H__
+#define __NU_2D_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+ @{
+*/
+
+/** @addtogroup N9H30_GE2D_Driver GE2D Driver
+ @{
+*/
+
+/** @addtogroup N9H30_GE2D_EXPORTED_CONSTANTS GE2D Exported Constants
+ @{
+*/
+
+/// @cond HIDDEN_SYMBOLS
+typedef struct
+{
+ UINT32 PatternA;
+ UINT32 PatternB;
+} MONOPATTERN;
+
+#define COLOR_KEY 0xFF000000
+/// @endcond HIDDEN_SYMBOLS
+
+///////////////////////////////////////////////////////////////////////////////
+// Definition of ROP2
+///////////////////////////////////////////////////////////////////////////////
+#define BLACKNESS 0x00 /*!< rop code: 0 */
+#define DSTINVERT 0x55 /*!< rop code: Dn */
+#define MERGECOPY 0xC0 /*!< rop code: PSa */
+#define MERGEPAINT 0xBB /*!< rop code: DSno */
+#define NOTSRCCOPY 0x33 /*!< rop code: Sn */
+#define NOTSRCERASE 0x11 /*!< rop code: DSon */
+#define PATCOPY 0xF0 /*!< rop code: P */
+#define PATINVERT 0x5A /*!< rop code: DPx */
+#define PATPAINT 0xFB /*!< rop code: DPSnoo */
+#define SRCAND 0x88 /*!< rop code: DSa */
+#define SRCCOPY 0xCC /*!< rop code: S */
+#define SRCERASE 0x44 /*!< rop code: SDna */
+#define SRCINVERT 0x66 /*!< rop code: DSx */
+#define SRCPAINT 0xEE /*!< rop code: DSo */
+#define WHITENESS 0xFF /*!< rop code: 1 */
+
+///////////////////////////////////////////////////////////////////////////////
+// Definition of Pen Styles
+///////////////////////////////////////////////////////////////////////////////
+#define PS_SOLID 0xffff /*!< pan style: solid */ //1111111111111111 (1111111111111111)
+#define PS_DASH 0xcccc /*!< pan style: dash */ //1100110011001100 (1111000011110000)
+#define PS_DOT 0xaaaa /*!< pan style: dot */ //1010101010101010 (1100110011001100)
+#define PS_DASHDOT 0xe4e4 /*!< pan style: dash and dot */ //1110010011100100 (1111110000110000)
+#define PS_DASHDOTDOT 0xeaea /*!< pan style: dash and two dots */ //1110101011101010 (1111110011001100)
+#define PS_NULL 0x0000 /*!< pan style: null */ //0000000000000000 (0000000000000000)
+
+///////////////////////////////////////////////////////////////////////////////
+// Definition of Brush Styles
+//
+// HS_HORIZONTAL: 00000000 HS_BDIAGONAL: 00000001
+// 00000000 00000010
+// 00000000 00000100
+// 00000000 00001000
+// 11111111 00010000
+// 00000000 00100000
+// 00000000 01000000
+// 00000000 10000000
+//
+// HS_VERTICAL: 00001000 HS_CROSS: 00001000
+// 00001000 00001000
+// 00001000 00001000
+// 00001000 00001000
+// 00001000 11111111
+// 00001000 00001000
+// 00001000 00001000
+// 00001000 00001000
+//
+// HS_FDIAGONAL: 10000000 HS_DIAGCROSS: 10000001
+// 01000000 01000010
+// 00100000 00100100
+// 00010000 00011000
+// 00001000 00011000
+// 00000100 00100100
+// 00000010 01000010
+// 00000001 10000001
+///////////////////////////////////////////////////////////////////////////////
+#define HS_HORIZONTAL 0 /*!< brush style: horizontal */
+#define HS_VERTICAL 1 /*!< brush style: vertical */
+#define HS_FDIAGONAL 2 /*!< brush style: fdiagonal */
+#define HS_BDIAGONAL 3 /*!< brush style: bdiagonal */
+#define HS_CROSS 4 /*!< brush style: cross */
+#define HS_DIAGCROSS 5 /*!< brush style: diagcross */
+
+#define MODE_OPAQUE 0 /*!< opaque mode */
+#define MODE_TRANSPARENT 1 /*!< transparent mode */
+#define MODE_SRC_TRANSPARENT MODE_TRANSPARENT /*!< source transparent mode */
+#define MODE_DEST_TRANSPARENT 2 /*!< destination transparent mode */
+
+#define MODE_INSIDE_CLIP 0 /*!< clip inside */
+#define MODE_OUTSIDE_CLIP 1 /*!< clip outside */
+
+#define TYPE_MONO 0 /*!< mono */
+#define TYPE_COLOR 1 /*!< color */
+
+#define GE_BPP_8 0x00000000 /*!< 8bpp display */
+#define GE_BPP_16 0x00000010 /*!< 16bpp display */
+#define GE_BPP_32 0x00000020 /*!< 32bpp display */
+
+#define RGB332 1 /*!< 8bpp display */
+#define RGB565 2 /*!< 16bpp display */
+#define RGB888 3 /*!< 24bpp display */
+
+#define F8x8 0 /*!< 8x8 font support */
+#define F8x16 1 /*!< 8x16 font support */
+
+/*@}*/ /* end of group N9H30_GE2D_EXPORTED_CONSTANTS */
+
+/** @addtogroup N9H30_GE2D_EXPORTED_FUNCTIONS GE2D Exported Functions
+ @{
+*/
+
+void ge2dClearScreen(int color);
+void ge2dSetWriteMask(int mask);
+void ge2dSetSourceOriginStarting(void *ptr);
+void ge2dSetDestinationOriginStarting(void *ptr);
+void ge2dInit(int bpp, int width, int height, void *destination);
+void ge2dReset(void);
+void ge2dResetFIFO(void);
+void ge2dBitblt_SetDrawMode(int opt, int ckey, int mask);
+int ge2dBitblt_SetAlphaMode(int opt, int ks, int kd);
+void ge2dBitblt_ScreenToScreen(int srcx, int srcy, int destx, int desty, int width, int height);
+void ge2dBitblt_ScreenToScreenRop(int srcx, int srcy, int destx, int desty, int width, int height, int rop);
+void ge2dBitblt_SourceToDestination(int srcx, int srcy, int destx, int desty, int width, int height, int srcpitch, int destpitch);
+void ge2dClip_SetClip(int x1, int y1, int x2, int y2);
+void ge2dClip_SetClipMode(int opt);
+void ge2dDrawFrame(int x1, int y1, int x2, int y2, int color, int opt);
+void ge2dLine_DrawSolidLine(int x1, int y1, int x2, int y2, int color);
+void ge2dLine_DrawSolidLine_RGB565(int x1, int y1, int x2, int y2, int color);
+void ge2dLine_DrawStyledLine(int x1, int y1, int x2, int y2, int style, int fgcolor, int bkcolor, int draw_mode);
+void ge2dLine_DrawStyledLine_RGB565(int x1, int y1, int x2, int y2, int style, int fgcolor, int bkcolor, int draw_mode);
+void ge2dFill_Solid(int dx, int dy, int width, int height, int color);
+void ge2dFill_Solid_RGB565(int dx, int dy, int width, int height, int color);
+void ge2dFill_SolidBackground(int dx, int dy, int width, int height, int color);
+void ge2dFill_ColorPattern(int dx, int dy, int width, int height);
+void ge2dFill_MonoPattern(int dx, int dy, int width, int height, int opt);
+void ge2dFill_ColorPatternROP(int sx, int sy, int width, int height, int rop);
+void ge2dFill_MonoPatternROP(int sx, int sy, int width, int height, int rop, int opt);
+void ge2dFill_TileBlt(int srcx, int srcy, int destx, int desty, int width, int height, int x_count, int y_count);
+void ge2dHostBlt_Write(int x, int y, int width, int height, void *buf);
+void ge2dHostBlt_Read(int x, int y, int width, int height, void *buf);
+void ge2dHostBlt_Sprite(int x, int y, int width, int height, void *buf);
+void ge2dRotation(int srcx, int srcy, int destx, int desty, int width, int height, int ctl);
+void ge2dSpriteBlt_Screen(int destx, int desty, int sprite_width, int sprite_height, void *buf);
+void ge2dSpriteBltx_Screen(int x, int y, int sprite_sx, int sprite_sy, int width, int height, int sprite_width, int sprite_height, void *buf);
+void ge2dSpriteBlt_ScreenRop(int x, int y, int sprite_width, int sprite_height, void *buf, int rop);
+void ge2dSpriteBltx_ScreenRop(int x, int y, int sprite_sx, int sprite_sy, int width, int height, int sprite_width, int sprite_height, void *buf, int rop);
+void ge2dColorExpansionBlt(int x, int y, int width, int height, int fore_color, int back_color, int opt, void *buf);
+void ge2dHostColorExpansionBlt(int x, int y, int width, int height, int fore_color, int back_color, int opt, void *buf);
+void ge2dInitMonoPattern(int opt, int fore_color, int back_color);
+void ge2dInitMonoInputPattern(UINT32 PatternA, UINT32 PatternB, int fore_color, int back_color);
+void ge2dInitColorPattern(int patformat, void *patdata);
+void ge2dFont_PutChar(int x, int y, char asc_code, int fore_color, int back_color, int draw_mode, int font_id);
+void ge2dFont_PutString(int x, int y, char *str, int fore_color, int back_color, int draw_mode, int font_id);
+
+/*@}*/ /* end of group N9H30_GE2D_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group N9H30_GE2D_Driver */
+
+/*@}*/ /* end of group N9H30_Device_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__NU_2D_H__
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_adc.h b/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_adc.h
new file mode 100644
index 0000000000000000000000000000000000000000..6747946db503675328e1cc052758baa169c4f37e
--- /dev/null
+++ b/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_adc.h
@@ -0,0 +1,198 @@
+/**************************************************************************//**
+* @file adc.h
+* @brief N9H30 ADC driver header file
+*
+* @note
+* SPDX-License-Identifier: Apache-2.0
+* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NU_ADC_H__
+#define __NU_ADC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup N9H30_Device_Driver N9H30 Device Driver
+ @{
+*/
+
+/** @addtogroup N9H30_ADC_Driver ADC Driver
+ @{
+*/
+
+/** @addtogroup N9H30_ADC_EXPORTED_CONSTANTS ADC Exported Constants
+ @{
+*/
+
+#define ADC_ERR_ARGS 1 /*!< The arguments is wrong */
+#define ADC_ERR_CMD 2 /*!< The command is wrong */
+
+/// @cond HIDDEN_SYMBOLS
+typedef int32_t(*ADC_CALLBACK)(uint32_t status, uint32_t userData);
+/// @endcond HIDDEN_SYMBOLS
+/*---------------------------------------------------------------------------------------------------------*/
+/* ADC_CTL constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ADC_CTL_ADEN 0x00000001 /*!< ADC Power Control */
+#define ADC_CTL_VBGEN 0x00000002 /*!< ADC Internal Bandgap Power Control */
+#define ADC_CTL_PWKPEN 0x00000004 /*!< ADC Keypad Power Enable Control */
+#define ADC_CTL_MST 0x00000100 /*!< Menu Start Conversion */
+#define ADC_CTL_PEDEEN 0x00000200 /*!< Pen Down Event Enable */
+#define ADC_CTL_WKPEN 0x00000400 /*!< Keypad Press Wake Up Enable */
+#define ADC_CTL_WKTEN 0x00000800 /*!< Touch Wake Up Enable */
+#define ADC_CTL_WMSWCH 0x00010000 /*!< Wire Mode Switch For 5-Wire/4-Wire Configuration */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ADC_CONF constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ADC_CONF_TEN 0x00000001 /*!< Touch Enable */
+#define ADC_CONF_ZEN 0x00000002 /*!< Press Enable */
+#define ADC_CONF_NACEN 0x00000004 /*!< Normal AD Conversion Enable */
+#define ADC_CONF_VBATEN 0x00000100 /*!< Voltage Battery Enable */
+#define ADC_CONF_KPCEN 0x00000200 /*!< Keypad Press Conversion Enable */
+#define ADC_CONF_SELFTEN 0x00000400 /*!< Selft Test Enable */
+#define ADC_CONF_DISTMAVEN (1<<20) /*!< Display T Mean Average Enable */
+#define ADC_CONF_DISZMAVEN (1<<21) /*!< Display Z Mean Average Enable */
+#define ADC_CONF_HSPEED (1<<22) /*!< High Speed Enable */
+
+#define ADC_CONF_CHSEL_Pos 3 /*!< Channel Selection Position */
+#define ADC_CONF_CHSEL_Msk (7<<3) /*!< Channel Selection Mask */
+#define ADC_CONF_CHSEL_VBT (0<<3) /*!< ADC input channel select VBT */
+#define ADC_CONF_CHSEL_VHS (1<<3) /*!< ADC input channel select VHS */
+#define ADC_CONF_CHSEL_A2 (2<<3) /*!< ADC input channel select A2 */
+#define ADC_CONF_CHSEL_A3 (3<<3) /*!< ADC input channel select A3 */
+#define ADC_CONF_CHSEL_YM (4<<3) /*!< ADC input channel select YM */
+#define ADC_CONF_CHSEL_YP (5<<3) /*!< ADC input channel select YP */
+#define ADC_CONF_CHSEL_XM (6<<3) /*!< ADC input channel select XM */
+#define ADC_CONF_CHSEL_XP (7<<3) /*!< ADC input channel select XP */
+
+#define ADC_CONF_REFSEL_Pos 6 /*!< Reference Selection Position */
+#define ADC_CONF_REFSEL_Msk (3<<6) /*!< Reference Selection Mask */
+#define ADC_CONF_REFSEL_VREF (0<<6) /*!< ADC reference select VREF input or 2.5v buffer output */
+#define ADC_CONF_REFSEL_YMYP (1<<6) /*!< ADC reference select YM vs YP */
+#define ADC_CONF_REFSEL_XMXP (2<<6) /*!< ADC reference select XM vs XP */
+#define ADC_CONF_REFSEL_AVDD33 (3<<6) /*!< ADC reference select AGND33 vs AVDD33 */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ADC_IER constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ADC_IER_MIEN 0x00000001 /*!< Menu Interrupt Enable */
+#define ADC_IER_KPEIEN 0x00000002 /*!< Keypad Press Event Interrupt Enable */
+#define ADC_IER_PEDEIEN 0x00000004 /*!< Pen Down Even Interrupt Enable */
+#define ADC_IER_WKTIEN 0x00000008 /*!< Wake Up Touch Interrupt Enable */
+#define ADC_IER_WKPIEN 0x00000010 /*!< Wake Up Keypad Press Interrupt Enable */
+#define ADC_IER_KPUEIEN 0x00000020 /*!< Keypad Press Up Event Interrupt Enable */
+#define ADC_IER_PEUEIEN 0x00000040 /*!< Pen Up Event Interrupt Enable */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ADC_ISR constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ADC_ISR_MF 0x00000001 /*!< Menu Complete Flag */
+#define ADC_ISR_KPEF 0x00000002 /*!< Keypad Press Event Flag */
+#define ADC_ISR_PEDEF 0x00000004 /*!< Pen Down Event Flag */
+#define ADC_ISR_KPUEF 0x00000008 /*!< Keypad Press Up Event Flag */
+#define ADC_ISR_PEUEF 0x00000010 /*!< Pen Up Event Flag */
+#define ADC_ISR_TF 0x00000100 /*!< Touch Conversion Finish */
+#define ADC_ISR_ZF 0x00000200 /*!< Press Conversion Finish */
+#define ADC_ISR_NACF 0x00000400 /*!< Normal AD Conversion Finish */
+#define ADC_ISR_VBF 0x00000800 /*!< Voltage Battery Conversion Finish */
+#define ADC_ISR_KPCF 0x00001000 /*!< Keypad Press Conversion Finish */
+#define ADC_ISR_SELFTF 0x00002000 /*!< Self-Test Conversion Finish */
+#define ADC_ISR_INTKP 0x00010000 /*!< Interrupt Signal For Keypad Detection */
+#define ADC_ISR_INTTC 0x00020000 /*!< Interrupt Signal For Touch Screen Touching Detection */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ADC_WKISR constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ADC_WKISR_WKPEF 0x00000001 /*!< Wake Up Pen Down Event Flag */
+#define ADC_WKISR_WPEDEF 0x00000002 /*!< Wake Up Keypad Press Event Flage */
+
+/** \brief Structure type of ADC_CHAN
+ */
+typedef enum
+{
+ AIN0 = ADC_CONF_CHSEL_VBT, /*!< ADC input channel select \ref ADC_CONF_CHSEL_VBT */
+ AIN1 = ADC_CONF_CHSEL_VHS, /*!< ADC input channel select \ref ADC_CONF_CHSEL_VHS */
+ AIN2 = ADC_CONF_CHSEL_A2, /*!< ADC input channel select \ref ADC_CONF_CHSEL_A2 */
+ AIN3 = ADC_CONF_CHSEL_A3, /*!< ADC input channel select \ref ADC_CONF_CHSEL_A3 */
+ AIN4 = ADC_CONF_CHSEL_YM, /*!< ADC input channel select \ref ADC_CONF_CHSEL_YM */
+ AIN5 = ADC_CONF_CHSEL_XP, /*!< ADC input channel select \ref ADC_CONF_CHSEL_XP */
+ AIN6 = ADC_CONF_CHSEL_XM, /*!< ADC input channel select \ref ADC_CONF_CHSEL_XM */
+ AIN7 = ADC_CONF_CHSEL_XP /*!< ADC input channel select \ref ADC_CONF_CHSEL_XP */
+} ADC_CHAN;
+
+/** \brief Structure type of ADC_CMD
+ */
+typedef enum
+{
+ START_MST, /*!