diff --git a/bsp/nrf51822/Libraries/nrf51822/Include/compiler_abstraction.h b/bsp/nrf51822/Libraries/nrf51822/Include/compiler_abstraction.h new file mode 100644 index 0000000000000000000000000000000000000000..c239fd11cdeb3f978b7978230df7b6489a3368d8 --- /dev/null +++ b/bsp/nrf51822/Libraries/nrf51822/Include/compiler_abstraction.h @@ -0,0 +1,255 @@ +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _COMPILER_ABSTRACTION_H +#define _COMPILER_ABSTRACTION_H + +/*lint ++flb "Enter library region" */ + +#ifndef NRF_STRING_CONCATENATE_IMPL + #define NRF_STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs +#endif +#ifndef NRF_STRING_CONCATENATE + #define NRF_STRING_CONCATENATE(lhs, rhs) NRF_STRING_CONCATENATE_IMPL(lhs, rhs) +#endif + +#if defined ( __CC_ARM ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE __inline + #endif + + #ifndef __WEAK + #define __WEAK __weak + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __align(n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif + + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + + #define GET_SP() __current_sp() + + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) \ + ;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) } + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE __inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(n))) + #endif + + #ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) + #endif + + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + + #define GET_SP() __current_sp() + + #ifndef NRF_STATIC_ASSERT + #ifdef __cplusplus + #ifndef _Static_assert + #define _Static_assert static_assert + #endif + #endif + #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg) + #endif + +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __weak + #endif + + #if (__VER__ >= 8000000) + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(x))) + #endif + + #ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) + #endif + #else + #ifndef __ALIGN + #define STRING_PRAGMA(x) _Pragma(#x) + #define __ALIGN(n) STRING_PRAGMA(data_alignment = n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif + #endif + + #ifndef __UNUSED + #define __UNUSED + #endif + + #define GET_SP() __get_SP() + + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) + #endif + +#elif defined ( __GNUC__ ) || defined ( __clang__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(n))) + #endif + + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + + #define GET_SP() gcc_current_sp() + + static inline unsigned int gcc_current_sp(void) + { + unsigned int stack_pointer = 0; + __asm__ __volatile__ ("mov %0, sp" : "=r"(stack_pointer)); + return stack_pointer; + } + + #ifndef NRF_STATIC_ASSERT + #ifdef __cplusplus + #ifndef _Static_assert + #define _Static_assert static_assert + #endif + #endif + #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg) + #endif + +#elif defined ( __TASKING__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __align(n) + #endif + + /* Not defined for TASKING. */ + #ifndef __PACKED + #define __PACKED + #endif + + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + + #define GET_SP() __get_MSP() + + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) + #endif + +#endif + +#define NRF_MDK_VERSION_ASSERT_AT_LEAST(major, minor, micro) \ + NRF_STATIC_ASSERT( \ + ( \ + (major < MDK_MAJOR_VERSION) || \ + (major == MDK_MAJOR_VERSION && minor < MDK_MINOR_VERSION) || \ + (major == MDK_MAJOR_VERSION && minor == MDK_MINOR_VERSION && micro < MDK_MICRO_VERSION) \ + ), "MDK version mismatch.") + +#define NRF_MDK_VERSION_ASSERT_EXACT(major, minor, micro) \ + NRF_STATIC_ASSERT( \ + ( \ + (major != MDK_MAJOR_VERSION) || \ + (major != MDK_MAJOR_VERSION) || \ + (major != MDK_MAJOR_VERSION) \ + ), "MDK version mismatch.") + +/*lint --flb "Leave library region" */ + +#endif diff --git a/bsp/nrf51822/Libraries/nrf51822/Include/nrf.h b/bsp/nrf51822/Libraries/nrf51822/Include/nrf.h new file mode 100644 index 0000000000000000000000000000000000000000..6f47bd4211cb2726add793e5716274437f7b6468 --- /dev/null +++ b/bsp/nrf51822/Libraries/nrf51822/Include/nrf.h @@ -0,0 +1,189 @@ +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF_H +#define NRF_H + +/* MDK version */ +#define MDK_MAJOR_VERSION 8 +#define MDK_MINOR_VERSION 38 +#define MDK_MICRO_VERSION 0 + + +/* Define coprocessor domains */ +#if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK) + #ifndef NRF5340_XXAA + #define NRF5340_XXAA + #endif +#endif +#if defined (NRF5340_XXAA_APPLICATION) + #ifndef NRF_APPLICATION + #define NRF_APPLICATION + #endif +#endif +#if defined (NRF5340_XXAA_NETWORK) + #ifndef NRF_NETWORK + #define NRF_NETWORK + #endif +#endif + +/* Apply compatibility macros for old nRF5340 macros */ +#if defined(NRF5340_XXAA) + #if defined (NRF_APPLICATION) + #ifndef NRF5340_XXAA_APPLICATION + #define NRF5340_XXAA_APPLICATION + #endif + #endif + #if defined (NRF_NETWORK) + #ifndef NRF5340_XXAA_NETWORK + #define NRF5340_XXAA_NETWORK + #endif + #endif +#endif + +/* Define NRF51_SERIES for common use in nRF51 series devices. Only if not previously defined. */ +#if defined (NRF51) ||\ + defined (NRF51422_XXAA) ||\ + defined (NRF51422_XXAB) ||\ + defined (NRF51422_XXAC) ||\ + defined (NRF51801_XXAB) ||\ + defined (NRF51802_XXAA) ||\ + defined (NRF51822_XXAA) ||\ + defined (NRF51822_XXAB) ||\ + defined (NRF51822_XXAC) ||\ + defined (NRF51824_XXAA) + #ifndef NRF51_SERIES + #define NRF51_SERIES + #endif + #ifndef NRF51 + #define NRF51 + #endif +#endif + +/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */ +#if defined (NRF52) + #ifndef NRF52832_XXAA + #define NRF52832_XXAA + #endif +#endif + +/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */ +#if defined (NRF52805_XXAA) || defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52820_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52833_XXAA) || defined (NRF52840_XXAA) + #ifndef NRF52_SERIES + #define NRF52_SERIES + #endif +#endif + +/* Define NRF53_SERIES for common use in nRF53 series devices. */ +#if defined (NRF5340_XXAA) + #ifndef NRF53_SERIES + #define NRF53_SERIES + #endif +#endif + +/* Define NRF91_SERIES for common use in nRF91 series devices. */ +#if defined (NRF9160_XXAA) + #ifndef NRF91_SERIES + #define NRF91_SERIES + #endif +#endif + +/* Device selection for device includes. */ +#if defined (NRF51) + #include "nrf51.h" + #include "nrf51_bitfields.h" + #include "nrf51_deprecated.h" + +#elif defined (NRF52805_XXAA) + #include "nrf52805.h" + #include "nrf52805_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_to_nrf52811.h" +#elif defined (NRF52810_XXAA) + #include "nrf52810.h" + #include "nrf52810_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_name_change.h" +#elif defined (NRF52811_XXAA) + #include "nrf52811.h" + #include "nrf52811_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_to_nrf52811.h" +#elif defined (NRF52820_XXAA) + #include "nrf52820.h" + #include "nrf52820_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_to_nrf52833.h" + #include "nrf52833_to_nrf52820.h" +#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB) + #include "nrf52.h" + #include "nrf52_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_name_change.h" +#elif defined (NRF52833_XXAA) + #include "nrf52833.h" + #include "nrf52833_bitfields.h" + #include "nrf52_to_nrf52833.h" + #include "nrf51_to_nrf52.h" +#elif defined (NRF52840_XXAA) + #include "nrf52840.h" + #include "nrf52840_bitfields.h" + #include "nrf51_to_nrf52840.h" + #include "nrf52_to_nrf52840.h" + +#elif defined (NRF5340_XXAA) + #if defined(NRF_APPLICATION) + #include "nrf5340_application.h" + #include "nrf5340_application_bitfields.h" + #include "nrf5340_application_name_change.h" + #elif defined (NRF_NETWORK) + #include "nrf5340_network.h" + #include "nrf5340_network_bitfields.h" + #include "nrf5340_network_name_change.h" + #endif + +#elif defined (NRF9160_XXAA) + #include "nrf9160.h" + #include "nrf9160_bitfields.h" + #include "nrf9160_name_change.h" + +#else + #error "Device must be defined. See nrf.h." +#endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */ + +#include "compiler_abstraction.h" + +#endif /* NRF_H */ + diff --git a/bsp/nrf51822/Libraries/nrf51822/Include/nrf51_deprecated.h b/bsp/nrf51822/Libraries/nrf51822/Include/nrf51_deprecated.h new file mode 100644 index 0000000000000000000000000000000000000000..a59e9d479b89026958c52e85a98447bd82130e29 --- /dev/null +++ b/bsp/nrf51822/Libraries/nrf51822/Include/nrf51_deprecated.h @@ -0,0 +1,446 @@ +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF51_DEPRECATED_H +#define NRF51_DEPRECATED_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and + * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these + * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead. + */ + +/* NVMC */ +/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */ +#define ERASEPROTECTEDPAGE ERASEPCR0 + + +/* LPCOMP */ +/* The interrupt ISR was renamed. Adding old name to the macros. */ +#define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler +#define LPCOMP_COMP_IRQn LPCOMP_IRQn +/* Corrected typo in RESULT register. */ +#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below + + +/* MPU */ +/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */ +#define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos +#define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk +#define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1 +#define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0 + + +/* POWER */ +/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_OFFRAM3_Pos (19UL) +#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) +#define POWER_RAMON_OFFRAM3_RAM3Off (0UL) +#define POWER_RAMON_OFFRAM3_RAM3On (1UL) +/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_OFFRAM2_Pos (18UL) +#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) +#define POWER_RAMON_OFFRAM2_RAM2Off (0UL) +#define POWER_RAMON_OFFRAM2_RAM2On (1UL) +/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_ONRAM3_Pos (3UL) +#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) +#define POWER_RAMON_ONRAM3_RAM3Off (0UL) +#define POWER_RAMON_ONRAM3_RAM3On (1UL) +/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_ONRAM2_Pos (2UL) +#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) +#define POWER_RAMON_ONRAM2_RAM2Off (0UL) +#define POWER_RAMON_ONRAM2_RAM2On (1UL) + + +/* RADIO */ +/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */ +#define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm +/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ +#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip +/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */ +#define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos +#define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk +#define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled +#define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled +/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */ +#define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos +#define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk +#define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled +#define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled + + +/* FICR */ +/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */ +#define SIZERAMBLOCK0 SIZERAMBLOCKS +#define SIZERAMBLOCK1 SIZERAMBLOCKS +#define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ +#define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ +/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ +#define DEVICEID0 DEVICEID[0] +#define DEVICEID1 DEVICEID[1] +/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ +#define ER0 ER[0] +#define ER1 ER[1] +#define ER2 ER[2] +#define ER3 ER[3] +/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ +#define IR0 IR[0] +#define IR1 IR[1] +#define IR2 IR[2] +#define IR3 IR[3] +/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ +#define DEVICEADDR0 DEVICEADDR[0] +#define DEVICEADDR1 DEVICEADDR[1] + + +/* PPI */ +/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ +#define TASKS_CHG0EN TASKS_CHG[0].EN +#define TASKS_CHG0DIS TASKS_CHG[0].DIS +#define TASKS_CHG1EN TASKS_CHG[1].EN +#define TASKS_CHG1DIS TASKS_CHG[1].DIS +#define TASKS_CHG2EN TASKS_CHG[2].EN +#define TASKS_CHG2DIS TASKS_CHG[2].DIS +#define TASKS_CHG3EN TASKS_CHG[3].EN +#define TASKS_CHG3DIS TASKS_CHG[3].DIS +/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ +#define CH0_EEP CH[0].EEP +#define CH0_TEP CH[0].TEP +#define CH1_EEP CH[1].EEP +#define CH1_TEP CH[1].TEP +#define CH2_EEP CH[2].EEP +#define CH2_TEP CH[2].TEP +#define CH3_EEP CH[3].EEP +#define CH3_TEP CH[3].TEP +#define CH4_EEP CH[4].EEP +#define CH4_TEP CH[4].TEP +#define CH5_EEP CH[5].EEP +#define CH5_TEP CH[5].TEP +#define CH6_EEP CH[6].EEP +#define CH6_TEP CH[6].TEP +#define CH7_EEP CH[7].EEP +#define CH7_TEP CH[7].TEP +#define CH8_EEP CH[8].EEP +#define CH8_TEP CH[8].TEP +#define CH9_EEP CH[9].EEP +#define CH9_TEP CH[9].TEP +#define CH10_EEP CH[10].EEP +#define CH10_TEP CH[10].TEP +#define CH11_EEP CH[11].EEP +#define CH11_TEP CH[11].TEP +#define CH12_EEP CH[12].EEP +#define CH12_TEP CH[12].TEP +#define CH13_EEP CH[13].EEP +#define CH13_TEP CH[13].TEP +#define CH14_EEP CH[14].EEP +#define CH14_TEP CH[14].TEP +#define CH15_EEP CH[15].EEP +#define CH15_TEP CH[15].TEP +/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ +#define CHG0 CHG[0] +#define CHG1 CHG[1] +#define CHG2 CHG[2] +#define CHG3 CHG[3] +/* All bitfield macros for the CHGx registers therefore changed name. */ +#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included +#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included +#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included +#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included + +/* SPIS */ +/* nRF51 devices do not have an SPIS0, only SPIS1. SPIS0_EASYDMA_MAXCNT_SIZE was therefore renamed. */ +#define SPIS0_EASYDMA_MAXCNT_SIZE SPIS1_EASYDMA_MAXCNT_SIZE + + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_DEPRECATED_H */ + diff --git a/bsp/nrf51822/Libraries/nrf51822/Include/system_nrf51.h b/bsp/nrf51822/Libraries/nrf51822/Include/system_nrf51.h index ae613609dd893761505f7d052034fb83e9e3bad0..9db78f961c6cad60771f50ab4c94d1df37780081 100644 --- a/bsp/nrf51822/Libraries/nrf51822/Include/system_nrf51.h +++ b/bsp/nrf51822/Libraries/nrf51822/Include/system_nrf51.h @@ -1,32 +1,25 @@ -/* Copyright (c) 2013, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ +/* + +Copyright (c) 2009-2021 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + #ifndef SYSTEM_NRF51_H #define SYSTEM_NRF51_H @@ -56,7 +49,7 @@ extern void SystemInit (void); * @param none * @return none * - * @brief Updates the SystemCoreClock with current core Clock + * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/bsp/nrf51822/Libraries/nrf51822/Source/templates/arm/arm_startup_nrf51.s b/bsp/nrf51822/Libraries/nrf51822/Source/templates/arm/arm_startup_nrf51.s index e06b1423b24ec33cb48ef3a39e09a5d5980f4fa1..cad23a65958a3d34263a5c3beb0ed9c988e19977 100644 --- a/bsp/nrf51822/Libraries/nrf51822/Source/templates/arm/arm_startup_nrf51.s +++ b/bsp/nrf51822/Libraries/nrf51822/Source/templates/arm/arm_startup_nrf51.s @@ -1,42 +1,55 @@ -; Copyright (c) 2013, Nordic Semiconductor ASA -; All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: +; SPDX-License-Identifier: Apache-2.0 ; -; * Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at ; -; * Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. +; www.apache.org/licenses/LICENSE-2.0 ; -; * Neither the name of Nordic Semiconductor ASA nor the names of its -; contributors may be used to endorse or promote products derived from -; this software without specific prior written permission. +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. ; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -; NOTE: Template files (including this one) are application specific and therefore -; expected to be copied into the application project folder prior to its use! - -; Description message - -Stack_Size EQU 0x00000400 - AREA STACK, NOINIT, READWRITE, ALIGN=3 +; NOTICE: This file has been modified by Nordic Semiconductor ASA. + + IF :DEF: __STARTUP_CONFIG +#ifdef __STARTUP_CONFIG +#include "startup_config.h" +#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#endif +#endif + ENDIF + + IF :DEF: __STARTUP_CONFIG +Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE + ELIF :DEF: __STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 2048 + ENDIF + + IF :DEF: __STARTUP_CONFIG +Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT + ELSE +Stack_Align EQU 3 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align Stack_Mem SPACE Stack_Size __initial_sp -Heap_Size EQU 0x00000000 + IF :DEF: __STARTUP_CONFIG +Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE + ELIF :DEF: __HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 2048 + ENDIF AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base @@ -54,9 +67,9 @@ __heap_limit EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved @@ -64,46 +77,45 @@ __Vectors DCD __initial_sp ; Top of Stack DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler + DCD SVC_Handler DCD 0 ; Reserved DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler + DCD PendSV_Handler + DCD SysTick_Handler ; External Interrupts - DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK - DCD RADIO_IRQHandler ;RADIO - DCD UART0_IRQHandler ;UART0 - DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0 - DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1 - DCD 0 ;Reserved - DCD GPIOTE_IRQHandler ;GPIOTE - DCD ADC_IRQHandler ;ADC - DCD TIMER0_IRQHandler ;TIMER0 - DCD TIMER1_IRQHandler ;TIMER1 - DCD TIMER2_IRQHandler ;TIMER2 - DCD RTC0_IRQHandler ;RTC0 - DCD TEMP_IRQHandler ;TEMP - DCD RNG_IRQHandler ;RNG - DCD ECB_IRQHandler ;ECB - DCD CCM_AAR_IRQHandler ;CCM_AAR - DCD WDT_IRQHandler ;WDT - DCD RTC1_IRQHandler ;RTC1 - DCD QDEC_IRQHandler ;QDEC - DCD LPCOMP_IRQHandler ;LPCOMP - DCD SWI0_IRQHandler ;SWI0 - DCD SWI1_IRQHandler ;SWI1 - DCD SWI2_IRQHandler ;SWI2 - DCD SWI3_IRQHandler ;SWI3 - DCD SWI4_IRQHandler ;SWI4 - DCD SWI5_IRQHandler ;SWI5 - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - + DCD POWER_CLOCK_IRQHandler + DCD RADIO_IRQHandler + DCD UART0_IRQHandler + DCD SPI0_TWI0_IRQHandler + DCD SPI1_TWI1_IRQHandler + DCD 0 ; Reserved + DCD GPIOTE_IRQHandler + DCD ADC_IRQHandler + DCD TIMER0_IRQHandler + DCD TIMER1_IRQHandler + DCD TIMER2_IRQHandler + DCD RTC0_IRQHandler + DCD TEMP_IRQHandler + DCD RNG_IRQHandler + DCD ECB_IRQHandler + DCD CCM_AAR_IRQHandler + DCD WDT_IRQHandler + DCD RTC1_IRQHandler + DCD QDEC_IRQHandler + DCD LPCOMP_IRQHandler + DCD SWI0_IRQHandler + DCD SWI1_IRQHandler + DCD SWI2_IRQHandler + DCD SWI3_IRQHandler + DCD SWI4_IRQHandler + DCD SWI5_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved __Vectors_End @@ -113,16 +125,16 @@ __Vectors_Size EQU __Vectors_End - __Vectors ; Reset Handler -NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address -NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address -NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask +NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address +NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address +NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main - - MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk + + MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk LDR R0, =NRF_POWER_RAMON_ADDRESS LDR R2, [R0] @@ -133,7 +145,7 @@ Reset_Handler PROC LDR R2, [R0] ORRS R2, R2, R1 STR R2, [R0] - + LDR R0, =SystemInit BLX R0 LDR R0, =__main @@ -216,7 +228,6 @@ SWI2_IRQHandler SWI3_IRQHandler SWI4_IRQHandler SWI5_IRQHandler - B . ENDP ALIGN @@ -224,7 +235,7 @@ SWI5_IRQHandler ; User Initial Stack & Heap IF :DEF:__MICROLIB - + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit @@ -233,17 +244,18 @@ SWI5_IRQHandler IMPORT __use_two_region_memory EXPORT __user_initial_stackheap -__user_initial_stackheap + +__user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR + ENDP ALIGN ENDIF END - diff --git a/bsp/nrf51822/Libraries/nrf51822/Source/templates/system_nrf51.c b/bsp/nrf51822/Libraries/nrf51822/Source/templates/system_nrf51.c index 712114e6c19b1b421cac4fd5850f81a9d892710e..3c036c8cbd745ba6bdffef689f82ff4444b7c41c 100644 --- a/bsp/nrf51822/Libraries/nrf51822/Source/templates/system_nrf51.c +++ b/bsp/nrf51822/Libraries/nrf51822/Source/templates/system_nrf51.c @@ -1,39 +1,32 @@ -/* Copyright (c) 2013, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* NOTE: Template files (including this one) are application specific and therefore expected to +/* + +Copyright (c) 2009-2021 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +/* NOTE: Template files (including this one) are application specific and therefore expected to be copied into the application project folder prior to its use! */ #include #include #include "nrf.h" +#include "nrf_erratas.h" #include "system_nrf51.h" /*lint ++flb "Enter library region" */ @@ -41,12 +34,8 @@ #define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ -static bool is_manual_peripheral_setup_needed(void); -static bool is_disabled_in_debug_needed(void); - - #if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; #elif defined ( __ICCARM__ ) __root uint32_t SystemCoreClock = __SYSTEM_CLOCK; #elif defined ( __GNUC__ ) @@ -65,57 +54,36 @@ void SystemInit(void) /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required to enable the use of peripherals" found at Product Anomaly document for your device found at - https://www.nordicsemi.com/. The side effect of executing these instructions in the devices + https://infocenter.nordicsemi.com/index.jsp The side effect of executing these instructions in the devices that do not need it is that the new peripherals in the second generation devices (LPCOMP for example) will not be available. */ - if (is_manual_peripheral_setup_needed()) + if (nrf51_errata_26()) { *(uint32_t volatile *)0x40000504 = 0xC007FFDF; *(uint32_t volatile *)0x40006C18 = 0x00008000; } - + /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG - register is incorrect" found at Product Anomaly document four your device found at - https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */ - if (is_disabled_in_debug_needed()) + register is incorrect" found at Product Anomaly document for your device found at + https://infocenter.nordicsemi.com/index.jsp There is no side effect of using these instruction if not needed. */ + if (nrf51_errata_59()) { NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos; } -} - -static bool is_manual_peripheral_setup_needed(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; + /* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices, + as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document + for your device found at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf51_errata_76()){ + if (*(uint32_t volatile *)0x4006EC00 != 1){ + *(uint32_t volatile *)0x4006EC00 = 0x9375; + while (*(uint32_t volatile *)0x4006EC00 != 1){ + } } + *(uint32_t volatile *)0x4006EC14 = 0xC0; } - - return false; -} -static bool is_disabled_in_debug_needed(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - } - - return false; + SystemCoreClockUpdate(); } /*lint --flb "Leave library region" */ diff --git a/bsp/nrf51822/drivers/board.c b/bsp/nrf51822/drivers/board.c index 933e2237ccc7cc2ebf57853c0a351c3587074d23..3a43db4cc4150b07f0af9111af997e2f0ca9d9b2 100644 --- a/bsp/nrf51822/drivers/board.c +++ b/bsp/nrf51822/drivers/board.c @@ -80,7 +80,7 @@ void RTC0_IRQHandler(void) */ void rt_hw_board_init() { - lfclk_config(); + //lfclk_config(); rtc_config(); NRF_RTC0->TASKS_START = 1; /* Initial usart deriver, and set console device */ diff --git a/bsp/nrf51822/drivers/uart.c b/bsp/nrf51822/drivers/uart.c index a959bf50c23f572e0fa72ab72b2e5e1d780442e3..f83dde20864c7648b22f1435adc7f111d3c399a7 100644 --- a/bsp/nrf51822/drivers/uart.c +++ b/bsp/nrf51822/drivers/uart.c @@ -72,7 +72,7 @@ static rt_err_t rt_uart_init (rt_device_t dev) NRF_UART0->CONFIG = (UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos); } - NRF_UART0->BAUDRATE = (UART_BAUDRATE_BAUDRATE_Baud38400 << UART_BAUDRATE_BAUDRATE_Pos); + NRF_UART0->BAUDRATE = (UART_BAUDRATE_BAUDRATE_Baud115200 << UART_BAUDRATE_BAUDRATE_Pos); NRF_UART0->ENABLE = (UART_ENABLE_ENABLE_Enabled << UART_ENABLE_ENABLE_Pos); NRF_UART0->TASKS_STARTTX = 1; NRF_UART0->TASKS_STARTRX = 1; diff --git a/bsp/nrf51822/drivers/uart.h b/bsp/nrf51822/drivers/uart.h index 5ad910d3aaf22ed8a6220596b735606485686e87..7e7c33c8d168b614d24d0d6f5d2dc387efbb4e9e 100644 --- a/bsp/nrf51822/drivers/uart.h +++ b/bsp/nrf51822/drivers/uart.h @@ -14,10 +14,10 @@ -#define RX_PIN_NUMBER 23 +#define RX_PIN_NUMBER 25 #define TX_PIN_NUMBER 24 -#define CTS_PIN_NUMBER 25 -#define RTS_PIN_NUMBER 22 +#define CTS_PIN_NUMBER 26 +#define RTS_PIN_NUMBER 27 #define HWFC false diff --git a/bsp/nrf51822/project.uvoptx b/bsp/nrf51822/project.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..2aab7cd1fe5382af3de96f53052aa5469a933dae --- /dev/null +++ b/bsp/nrf51822/project.uvoptx @@ -0,0 +1,673 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 5 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U17935099 -O78 -S8 -ZTIFSpeedSel50000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN1 -FF0nrf51xxx_sde -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx_sde.flm) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP" -U9901000052564e450054600b00000018 -O78 -S7 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC4000 -FN1 -FF0nrf51xxx_sde.flm -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx_sde.flm) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC4000 -FD20000000 -FF0nrf51xxx -FL0200000 -FS00 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 5000 + + + + + + Kernel + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\src\clock.c + clock.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\src\components.c + components.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\..\src\cpu.c + cpu.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\..\src\device.c + device.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + ..\..\src\idle.c + idle.c + 0 + 0 + + + 1 + 6 + 1 + 0 + 0 + 0 + ..\..\src\ipc.c + ipc.c + 0 + 0 + + + 1 + 7 + 1 + 0 + 0 + 0 + ..\..\src\irq.c + irq.c + 0 + 0 + + + 1 + 8 + 1 + 0 + 0 + 0 + ..\..\src\kservice.c + kservice.c + 0 + 0 + + + 1 + 9 + 1 + 0 + 0 + 0 + ..\..\src\mem.c + mem.c + 0 + 0 + + + 1 + 10 + 1 + 0 + 0 + 0 + ..\..\src\mempool.c + mempool.c + 0 + 0 + + + 1 + 11 + 1 + 0 + 0 + 0 + ..\..\src\object.c + object.c + 0 + 0 + + + 1 + 12 + 1 + 0 + 0 + 0 + ..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 1 + 13 + 1 + 0 + 0 + 0 + ..\..\src\signal.c + signal.c + 0 + 0 + + + 1 + 14 + 1 + 0 + 0 + 0 + ..\..\src\thread.c + thread.c + 0 + 0 + + + 1 + 15 + 1 + 0 + 0 + 0 + ..\..\src\timer.c + timer.c + 0 + 0 + + + + + Applications + 1 + 0 + 0 + 0 + + 2 + 16 + 1 + 0 + 0 + 0 + applications\application.c + application.c + 0 + 0 + + + 2 + 17 + 1 + 0 + 0 + 0 + applications\startup.c + startup.c + 0 + 0 + + + + + Drivers + 1 + 0 + 0 + 0 + + 3 + 18 + 1 + 0 + 0 + 0 + drivers\board.c + board.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + drivers\uart.c + uart.c + 0 + 0 + + + + + cpu + 1 + 0 + 0 + 0 + + 4 + 20 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 4 + 21 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 4 + 22 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 4 + 23 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m0\cpuport.c + cpuport.c + 0 + 0 + + + 4 + 24 + 2 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m0\context_rvds.S + context_rvds.S + 0 + 0 + + + + + DeviceDrivers + 1 + 0 + 0 + 0 + + 5 + 25 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 5 + 26 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 5 + 27 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 5 + 28 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + + + finsh + 1 + 0 + 0 + 0 + + 6 + 32 + 1 + 0 + 0 + 0 + ..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 6 + 33 + 1 + 0 + 0 + 0 + ..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/bsp/nrf51822/project.uvproj b/bsp/nrf51822/project.uvprojx similarity index 70% rename from bsp/nrf51822/project.uvproj rename to bsp/nrf51822/project.uvprojx index de8e9fc0847ac702c9947375046dd2ba534155a0..f2b7ab028d3b941adbdc2d9451930b154f36cc3e 100644 --- a/bsp/nrf51822/project.uvproj +++ b/bsp/nrf51822/project.uvprojx @@ -1,41 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread 0x4 ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 nRF51822_xxAA Nordic Semiconductor - NordicSemiconductor.nRF_DeviceFamilyPack.1.1.4 - http://developer.nordicsemi.com/nRF51_SDK/pieces/nRF_DeviceFamilyPack/ - IROM(0x00000000,0x40000) IRAM(0x20000000,0x4000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)) + NordicSemiconductor.nRF_DeviceFamilyPack.8.38.0 + http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/ + IRAM(0x20000000,0x00004000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)) 0 $$Device:nRF51822_xxAA$Device\Include\nrf.h - - - - - - - - - - $$Device:nRF51822_xxAA$SVD\nrf51.xml + + + + + + + + + + $$Device:nRF51822_xxAA$SVD\nrf51.svd 0 0 - - - - - + + + + + 0 0 @@ -47,7 +52,7 @@ template 1 0 - 0 + 1 1 1 .\build\ @@ -57,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -67,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -77,13 +82,15 @@ 0 0 - - + + 0 0 + 0 + 0 0 - + 0 @@ -97,13 +104,13 @@ 0 0 3 - - + + 1 SARMCM3.DLL - + DARMCM1.DLL -pCM0 SARMCM3.DLL @@ -119,47 +126,6 @@ 0 16 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 1 - - 0 - 6 - - - - - - - - - - - - - - Segger\JL2CM3.dll - @@ -173,10 +139,10 @@ 1 BIN\UL2CM3.DLL "" () - - - - + + + + 0 @@ -209,7 +175,7 @@ 0 0 "Cortex-M0" - + 0 0 0 @@ -218,12 +184,14 @@ 0 0 0 + 0 0 0 8 0 0 0 + 0 3 3 0 @@ -340,7 +308,7 @@ 0x0 - + 1 @@ -357,11 +325,19 @@ 0 0 0 + 0 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 --c99 NRF51, USE_STDPERIPH_DRIVER - + .;..\..\include;applications;.;drivers;Libraries\CMSIS\Include;Libraries\nrf51822\Include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\common @@ -375,11 +351,12 @@ 0 0 0 + 0 - - - - + + + + @@ -391,13 +368,13 @@ 0 0x08000000 0x20000000 - - - - - - - + + .\build\template.sct + + + + + @@ -410,99 +387,71 @@ 1 ..\..\src\clock.c - - components.c 1 ..\..\src\components.c - - cpu.c 1 ..\..\src\cpu.c - - device.c 1 ..\..\src\device.c - - idle.c 1 ..\..\src\idle.c - - ipc.c 1 ..\..\src\ipc.c - - irq.c 1 ..\..\src\irq.c - - kservice.c 1 ..\..\src\kservice.c - - mem.c 1 ..\..\src\mem.c - - mempool.c 1 ..\..\src\mempool.c - - object.c 1 ..\..\src\object.c - - scheduler.c 1 ..\..\src\scheduler.c - - signal.c 1 ..\..\src\signal.c - - thread.c 1 ..\..\src\thread.c - - timer.c 1 @@ -518,8 +467,6 @@ 1 applications\application.c - - startup.c 1 @@ -535,8 +482,6 @@ 1 drivers\board.c - - uart.c 1 @@ -544,23 +489,6 @@ - - Startup Code - - - system_nrf51.c - 1 - Libraries\nrf51822\Source\templates\system_nrf51.c - - - - - arm_startup_nrf51.s - 2 - Libraries\nrf51822\Source\templates\arm\arm_startup_nrf51.s - - - cpu @@ -569,29 +497,21 @@ 1 ..\..\libcpu\arm\common\backtrace.c - - div0.c 1 ..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\libcpu\arm\common\showmem.c - - cpuport.c 1 ..\..\libcpu\arm\cortex-m0\cpuport.c - - context_rvds.S 2 @@ -607,43 +527,31 @@ 1 ..\..\components\drivers\src\completion.c - - dataqueue.c 1 ..\..\components\drivers\src\dataqueue.c - - pipe.c 1 ..\..\components\drivers\src\pipe.c - - ringblk_buf.c 1 ..\..\components\drivers\src\ringblk_buf.c - - ringbuffer.c 1 ..\..\components\drivers\src\ringbuffer.c - - waitqueue.c 1 ..\..\components\drivers\src\waitqueue.c - - workqueue.c 1 @@ -659,15 +567,11 @@ 1 ..\..\components\finsh\shell.c - - cmd.c 1 ..\..\components\finsh\cmd.c - - msh.c 1 @@ -675,7 +579,73 @@ + + ::Device + + + + + + + + + + + + + + + + + + + + + RTE\Device\nRF51802_xxAA\arm_startup_nrf51.s + + + + + + RTE\Device\nRF51802_xxAA\startup_config.h + + + + + + RTE\Device\nRF51802_xxAA\system_nrf51.c + + + + + + RTE\Device\nRF51822_xxAA\arm_startup_nrf51.s + + + + + + + + RTE\Device\nRF51822_xxAA\startup_config.h + + + + + + + + RTE\Device\nRF51822_xxAA\system_nrf51.c + + + + + + + + + diff --git a/bsp/nrf51822/rtconfig.h b/bsp/nrf51822/rtconfig.h index 66a727c89896afdc7351dbbcc1b4a76162fc5371..6820739faf9f93e203b9ecd673e87c5c54f74d63 100644 --- a/bsp/nrf51822/rtconfig.h +++ b/bsp/nrf51822/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 6 +#define RT_NAME_MAX 6 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 8 +#define RT_THREAD_PRIORITY_MAX 8 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -24,20 +24,20 @@ /* Using Hook */ #define RT_USING_HOOK -#define IDLE_THREAD_STACK_SIZE 512 +#define IDLE_THREAD_STACK_SIZE 512 /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 100 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 100 /* SECTION: IPC */ /* Using Semaphore*/ #define RT_USING_SEMAPHORE /* Using Mutex */ -/* #define RT_USING_MUTEX */ +#define RT_USING_MUTEX /* Using Event */ /* #define RT_USING_EVENT */ @@ -74,9 +74,9 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_CONSOLE_DEVICE_NAME "uart0" @@ -84,8 +84,8 @@ #define RT_USING_FINSH /* configure finsh parameters */ #define FINSH_THREAD_PRIORITY 6 -#define FINSH_THREAD_STACK_SIZE 512 -#define FINSH_HISTORY_LINES 1 +#define FINSH_THREAD_STACK_SIZE 512 +#define FINSH_HISTORY_LINES 1 /* Using symbol table */ #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION