From 0ec79d4a0ea2a32f163a85f8caa760b4a65ad71d Mon Sep 17 00:00:00 2001 From: zohar123 Date: Mon, 24 Dec 2018 17:17:27 +0800 Subject: [PATCH] [bsp]add swm320-lq100 bsp --- bsp/swm320-lq100/.config | 413 + bsp/swm320-lq100/Kconfig | 25 + .../CMSIS/CoreSupport/arm_common_tables.h | 136 + .../CMSIS/CoreSupport/arm_const_structs.h | 79 + .../Libraries/CMSIS/CoreSupport/arm_math.h | 7538 +++++++++++++++++ .../Libraries/CMSIS/CoreSupport/core_cm0.h | 711 ++ .../CMSIS/CoreSupport/core_cm0plus.h | 822 ++ .../Libraries/CMSIS/CoreSupport/core_cm3.h | 1650 ++++ .../Libraries/CMSIS/CoreSupport/core_cm4.h | 1802 ++++ .../Libraries/CMSIS/CoreSupport/core_cm7.h | 2221 +++++ .../Libraries/CMSIS/CoreSupport/core_cmFunc.h | 637 ++ .../CMSIS/CoreSupport/core_cmInstr.h | 880 ++ .../Libraries/CMSIS/CoreSupport/core_cmSimd.h | 697 ++ .../Libraries/CMSIS/DeviceSupport/SWM320.h | 2548 ++++++ .../startup/arm/startup_SWM320.s | 558 ++ .../startup/gcc/startup_SWM320.s | 406 + .../startup/iar/startup_SWM320.s | 464 + .../CMSIS/DeviceSupport/system_SWM320.c | 215 + .../CMSIS/DeviceSupport/system_SWM320.h | 24 + bsp/swm320-lq100/Libraries/SConscript | 18 + .../SWM320_StdPeriph_Driver/SWM320_adc.c | 522 ++ .../SWM320_StdPeriph_Driver/SWM320_adc.h | 83 + .../SWM320_StdPeriph_Driver/SWM320_can.c | 687 ++ .../SWM320_StdPeriph_Driver/SWM320_can.h | 141 + .../SWM320_StdPeriph_Driver/SWM320_crc.c | 51 + .../SWM320_StdPeriph_Driver/SWM320_crc.h | 39 + .../SWM320_StdPeriph_Driver/SWM320_dma.c | 138 + .../SWM320_StdPeriph_Driver/SWM320_dma.h | 20 + .../SWM320_StdPeriph_Driver/SWM320_exti.c | 131 + .../SWM320_StdPeriph_Driver/SWM320_exti.h | 20 + .../SWM320_StdPeriph_Driver/SWM320_flash.c | 95 + .../SWM320_StdPeriph_Driver/SWM320_flash.h | 9 + .../SWM320_StdPeriph_Driver/SWM320_gpio.c | 279 + .../SWM320_StdPeriph_Driver/SWM320_gpio.h | 17 + .../SWM320_StdPeriph_Driver/SWM320_i2c.c | 150 + .../SWM320_StdPeriph_Driver/SWM320_i2c.h | 27 + .../SWM320_StdPeriph_Driver/SWM320_lcd.c | 259 + .../SWM320_StdPeriph_Driver/SWM320_lcd.h | 96 + .../SWM320_StdPeriph_Driver/SWM320_norflash.c | 174 + .../SWM320_StdPeriph_Driver/SWM320_norflash.h | 39 + .../SWM320_StdPeriph_Driver/SWM320_port.c | 221 + .../SWM320_StdPeriph_Driver/SWM320_port.h | 482 ++ .../SWM320_StdPeriph_Driver/SWM320_pwm.c | 744 ++ .../SWM320_StdPeriph_Driver/SWM320_pwm.h | 57 + .../SWM320_StdPeriph_Driver/SWM320_rtc.c | 413 + .../SWM320_StdPeriph_Driver/SWM320_rtc.h | 76 + .../SWM320_StdPeriph_Driver/SWM320_sdio.c | 436 + .../SWM320_StdPeriph_Driver/SWM320_sdio.h | 139 + .../SWM320_StdPeriph_Driver/SWM320_sdram.c | 58 + .../SWM320_StdPeriph_Driver/SWM320_sdram.h | 23 + .../SWM320_StdPeriph_Driver/SWM320_spi.c | 447 + .../SWM320_StdPeriph_Driver/SWM320_spi.h | 75 + .../SWM320_StdPeriph_Driver/SWM320_timr.c | 381 + .../SWM320_StdPeriph_Driver/SWM320_timr.h | 23 + .../SWM320_StdPeriph_Driver/SWM320_uart.c | 543 ++ .../SWM320_StdPeriph_Driver/SWM320_uart.h | 95 + .../SWM320_StdPeriph_Driver/SWM320_wdt.c | 126 + .../SWM320_StdPeriph_Driver/SWM320_wdt.h | 19 + bsp/swm320-lq100/README.md | 126 + bsp/swm320-lq100/SConscript | 11 + bsp/swm320-lq100/SConstruct | 39 + bsp/swm320-lq100/applications/SConscript | 9 + bsp/swm320-lq100/applications/main.c | 27 + bsp/swm320-lq100/drivers/Kconfig | 154 + bsp/swm320-lq100/drivers/SConscript | 52 + bsp/swm320-lq100/drivers/board.c | 54 + bsp/swm320-lq100/drivers/board.h | 40 + bsp/swm320-lq100/drivers/drv_gpio.c | 599 ++ bsp/swm320-lq100/drivers/drv_gpio.h | 16 + bsp/swm320-lq100/drivers/drv_i2c.c | 70 + bsp/swm320-lq100/drivers/drv_i2c.h | 16 + bsp/swm320-lq100/drivers/drv_iwg.c | 77 + bsp/swm320-lq100/drivers/drv_iwg.h | 16 + bsp/swm320-lq100/drivers/drv_nor_flash.c | 125 + bsp/swm320-lq100/drivers/drv_nor_flash.h | 16 + bsp/swm320-lq100/drivers/drv_pwm.c | 190 + bsp/swm320-lq100/drivers/drv_pwm.h | 16 + bsp/swm320-lq100/drivers/drv_rtc.c | 177 + bsp/swm320-lq100/drivers/drv_rtc.h | 16 + bsp/swm320-lq100/drivers/drv_spi.c | 288 + bsp/swm320-lq100/drivers/drv_spi.h | 27 + bsp/swm320-lq100/drivers/drv_sram.c | 47 + bsp/swm320-lq100/drivers/drv_sram.h | 16 + bsp/swm320-lq100/drivers/drv_uart.c | 260 + bsp/swm320-lq100/drivers/drv_uart.h | 16 + .../drivers/linker_scripts/link.icf | 62 + .../drivers/linker_scripts/link.lds | 137 + .../drivers/linker_scripts/link.sct | 15 + bsp/swm320-lq100/figures/SWXT-LQ100-32102.jpg | Bin 0 -> 560656 bytes bsp/swm320-lq100/project.uvoptx | 1389 +++ bsp/swm320-lq100/project.uvprojx | 980 +++ bsp/swm320-lq100/rtconfig.h | 212 + bsp/swm320-lq100/rtconfig.py | 92 + bsp/swm320-lq100/template.uvoptx | 177 + bsp/swm320-lq100/template.uvprojx | 389 + 95 files changed, 35132 insertions(+) create mode 100644 bsp/swm320-lq100/.config create mode 100644 bsp/swm320-lq100/Kconfig create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c create mode 100644 bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h create mode 100644 bsp/swm320-lq100/Libraries/SConscript create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h create mode 100644 bsp/swm320-lq100/README.md create mode 100644 bsp/swm320-lq100/SConscript create mode 100644 bsp/swm320-lq100/SConstruct create mode 100644 bsp/swm320-lq100/applications/SConscript create mode 100644 bsp/swm320-lq100/applications/main.c create mode 100644 bsp/swm320-lq100/drivers/Kconfig create mode 100644 bsp/swm320-lq100/drivers/SConscript create mode 100644 bsp/swm320-lq100/drivers/board.c create mode 100644 bsp/swm320-lq100/drivers/board.h create mode 100644 bsp/swm320-lq100/drivers/drv_gpio.c create mode 100644 bsp/swm320-lq100/drivers/drv_gpio.h create mode 100644 bsp/swm320-lq100/drivers/drv_i2c.c create mode 100644 bsp/swm320-lq100/drivers/drv_i2c.h create mode 100644 bsp/swm320-lq100/drivers/drv_iwg.c create mode 100644 bsp/swm320-lq100/drivers/drv_iwg.h create mode 100644 bsp/swm320-lq100/drivers/drv_nor_flash.c create mode 100644 bsp/swm320-lq100/drivers/drv_nor_flash.h create mode 100644 bsp/swm320-lq100/drivers/drv_pwm.c create mode 100644 bsp/swm320-lq100/drivers/drv_pwm.h create mode 100644 bsp/swm320-lq100/drivers/drv_rtc.c create mode 100644 bsp/swm320-lq100/drivers/drv_rtc.h create mode 100644 bsp/swm320-lq100/drivers/drv_spi.c create mode 100644 bsp/swm320-lq100/drivers/drv_spi.h create mode 100644 bsp/swm320-lq100/drivers/drv_sram.c create mode 100644 bsp/swm320-lq100/drivers/drv_sram.h create mode 100644 bsp/swm320-lq100/drivers/drv_uart.c create mode 100644 bsp/swm320-lq100/drivers/drv_uart.h create mode 100644 bsp/swm320-lq100/drivers/linker_scripts/link.icf create mode 100644 bsp/swm320-lq100/drivers/linker_scripts/link.lds create mode 100644 bsp/swm320-lq100/drivers/linker_scripts/link.sct create mode 100644 bsp/swm320-lq100/figures/SWXT-LQ100-32102.jpg create mode 100644 bsp/swm320-lq100/project.uvoptx create mode 100644 bsp/swm320-lq100/project.uvprojx create mode 100644 bsp/swm320-lq100/rtconfig.h create mode 100644 bsp/swm320-lq100/rtconfig.py create mode 100644 bsp/swm320-lq100/template.uvoptx create mode 100644 bsp/swm320-lq100/template.uvprojx diff --git a/bsp/swm320-lq100/.config b/bsp/swm320-lq100/.config new file mode 100644 index 0000000000..4a9cc31e92 --- /dev/null +++ b/bsp/swm320-lq100/.config @@ -0,0 +1,413 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40000 +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=8 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=8 +CONFIG_DFS_FD_MAX=8 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_CAN is not set +CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +CONFIG_RT_USING_I2C_BITOPS=y +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +CONFIG_RT_USING_PWM=y +CONFIG_RT_USING_MTD_NOR=y +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_W25QXX is not set +# CONFIG_RT_USING_GD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +CONFIG_RT_USING_WDT=y +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_POSIX is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set + +# +# sample package +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set +CONFIG_SOC_SWM320VET7=y + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y + +# +# UART Drivers +# +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set + +# +# SPI Drivers +# +# CONFIG_BSP_USING_SPI0 is not set +# CONFIG_BSP_USING_SPI1 is not set + +# +# I2C Drivers +# +# CONFIG_BSP_USING_I2C is not set + +# +# PWM module +# +# CONFIG_BSP_USING_PWM0 is not set +# CONFIG_BSP_USING_PWM1 is not set +# CONFIG_BSP_USING_PWM2 is not set +# CONFIG_BSP_USING_PWM3 is not set + +# +# RTC module +# + +# +# RTC SET +# +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_WDT is not set + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_EXT_SRAM is not set +# CONFIG_BSP_USING_NOR_FLASH is not set + +# +# Offboard Peripheral Drivers +# diff --git a/bsp/swm320-lq100/Kconfig b/bsp/swm320-lq100/Kconfig new file mode 100644 index 0000000000..5c6ef90e9c --- /dev/null +++ b/bsp/swm320-lq100/Kconfig @@ -0,0 +1,25 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_SWM320VET7 + bool + default y + +source "drivers/Kconfig" diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h new file mode 100644 index 0000000000..76aadca490 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 31. July 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +//extern const q31_t realCoefAQ31[1024]; +//extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h new file mode 100644 index 0000000000..217f1d50e2 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 31. July 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h new file mode 100644 index 0000000000..f06a0713eb --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h @@ -0,0 +1,7538 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 12. March 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvproj + * + * + * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2014 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY + #elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __CSMC__ /* Cosmic */ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ( + q31_t data); + + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + + ((q15_t) x * (q15_t) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +//SMMLAR +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//SMMLA +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) //Keil + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) // Cosmic + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h new file mode 100644 index 0000000000..5186cb4838 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h @@ -0,0 +1,711 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h new file mode 100644 index 0000000000..17e43984fc --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h @@ -0,0 +1,822 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h new file mode 100644 index 0000000000..e1357c6735 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h @@ -0,0 +1,1650 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h new file mode 100644 index 0000000000..bb6be1305d --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h @@ -0,0 +1,1802 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h new file mode 100644 index 0000000000..242540f8b1 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h @@ -0,0 +1,2221 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 01. September 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000 + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0 + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0 + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0 + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1]; + __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93]; + __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15]; + __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1]; + __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1]; + __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6]; + __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1]; + __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/* Cache Level ID register */ +#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* Cache Type register */ +#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ + +/* Cache Size ID Register */ +#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ + +/* Cache Size Selection Register */ +#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register */ +#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ + +/* Instruction Tightly-Coupled Memory Control Register*/ +#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Registers */ +#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register */ +#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register */ +#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ + +/* AHBS control register */ +#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register */ +#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## Cache functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) +#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) + + +/** \brief Enable I-Cache + + The function turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; // invalidate I-Cache + SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable I-Cache + + The function turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache + SCB->ICIALLU = 0; // invalidate I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate I-Cache + + The function invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; + __DSB(); + __ISB(); + #endif +} + + +/** \brief Enable D-Cache + + The function turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + __DSB(); + + SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable D-Cache + + The function turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate D-Cache + + The function invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean D-Cache + + The function cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCSW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean & Invalidate D-Cache + + The function cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h new file mode 100644 index 0000000000..01089f1333 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h new file mode 100644 index 0000000000..d14110b2ab --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h new file mode 100644 index 0000000000..ee58eee56d --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h new file mode 100644 index 0000000000..79d9baa156 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h @@ -0,0 +1,2548 @@ +#ifndef __SWM320_H__ +#define __SWM320_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ +typedef enum IRQn +{ + /****** Cortex-M0 Processor Exceptions Numbers **********************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + + /****** Cortex-M4 specific Interrupt Numbers ************************************************/ + GPIOA0_IRQn = 0, + GPIOA1_IRQn = 1, + GPIOA2_IRQn = 2, + GPIOA3_IRQn = 3, + GPIOA4_IRQn = 4, + GPIOA5_IRQn = 5, + GPIOA6_IRQn = 6, + GPIOA7_IRQn = 7, + GPIOB0_IRQn = 8, + GPIOB1_IRQn = 9, + GPIOB2_IRQn = 10, + GPIOB3_IRQn = 11, + GPIOB4_IRQn = 12, + GPIOB5_IRQn = 13, + GPIOB6_IRQn = 14, + GPIOB7_IRQn = 15, + GPIOC0_IRQn = 16, + GPIOC1_IRQn = 17, + GPIOC2_IRQn = 18, + GPIOC3_IRQn = 19, + GPIOC4_IRQn = 20, + GPIOC5_IRQn = 21, + GPIOC6_IRQn = 22, + GPIOC7_IRQn = 23, + GPIOM0_IRQn = 24, + GPIOM1_IRQn = 25, + GPIOM2_IRQn = 26, + GPIOM3_IRQn = 27, + GPIOM4_IRQn = 28, + GPIOM5_IRQn = 29, + GPIOM6_IRQn = 30, + GPIOM7_IRQn = 31, + DMA_IRQn = 32, + LCD_IRQn = 33, + NORFLC_IRQn = 34, + CAN_IRQn = 35, + PULSE_IRQn = 36, + WDT_IRQn = 37, + PWM_IRQn = 38, + UART0_IRQn = 39, + UART1_IRQn = 40, + UART2_IRQn = 41, + UART3_IRQn = 42, + UART4_IRQn = 43, + I2C0_IRQn = 44, + I2C1_IRQn = 45, + SPI0_IRQn = 46, + ADC0_IRQn = 47, + RTC_IRQn = 48, + ANAC_IRQn = 49, + SDIO_IRQn = 50, + GPIOA_IRQn = 51, + GPIOB_IRQn = 52, + GPIOC_IRQn = 53, + GPIOM_IRQn = 54, + GPION_IRQn = 55, + GPIOP_IRQn = 56, + ADC1_IRQn = 57, + FPU_IRQn = 58, + SPI1_IRQn = 59, + TIMR0_IRQn = 60, + TIMR1_IRQn = 61, + TIMR2_IRQn = 62, + TIMR3_IRQn = 63, + TIMR4_IRQn = 64, + TIMR5_IRQn = 65, +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M0 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< SWM320 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< SWM320 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#if defined(__CC_ARM) + #pragma anon_unions +#endif + +#include +#include "core_cm4.h" /* Cortex-M0 processor and core peripherals */ +#include "system_SWM320.h" + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ +typedef struct +{ + __IO uint32_t CLKSEL; //Clock Select + + __IO uint32_t CLKDIV; + + __IO uint32_t CLKEN; //Clock Enable + + __IO uint32_t SLEEP; + + uint32_t RESERVED0[6]; + + __IO uint32_t RTCBKP_ISO; //[0] 1 RTCé—è·¨å–é‹å©šå¹é‘芥晸閹归顣å¹é–¿å¬¬çˆ±é—è·¨å–é‹å©šå¹é‘芥晸閼哄倿娼婚å¹é‘芥晸閺傘倖瀚归悩鑸碘å“锟� 0 RTCé—è·¨å–é‹å©šå¹é‘芥晸閹归顣å¹é–¿å¬¬çˆ±é—è·¨å–é‹å©šå¹æ¤‹åº¡å¹–é—è·¨å–é‹å©šå¹é‘芥晸閿燂拷 + + __IO uint32_t RTCWKEN; //[0] 1 娴ｅ潡é撻弬銈嗗î¶RTCé—è·¨å–é‹å©šå¹é‘芥晸ç¼æ„­ç‰œå¨…㈤å¹é‘芥晸閺傘倖瀚� + + uint32_t RESERVED[52 + 64]; + + __IO uint32_t PAWKEN; //Port A Wakeup Enable + __IO uint32_t PBWKEN; + __IO uint32_t PCWKEN; + + uint32_t RESERVED2[1 + 4]; + + __IO uint32_t PAWKSR; //Port A Wakeup Status Registeré—è·¨å–é‹å©šå¹å®„æ¿æ™¸1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� + __IO uint32_t PBWKSR; + __IO uint32_t PCWKSR; + + uint32_t RESERVED3[64 - 11]; + + __IO uint32_t REMAP; //0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£ŽÃºOMé—è·¨å–é‹å©šå¹é–¿å¬ªâ’”é—è·¨å–é‹å©šå¹é”Ÿï¿½ 1 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£ŽÃ©LASHé—è·¨å–é‹å©šå¹é–¿å¬ªâ’”é—è·¨å–é‹å©šå¹é”Ÿï¿½ + + __IO uint32_t RSTCR; //Reset Control Register + __IO uint32_t RSTSR; //Reset Status Register + + uint32_t RESERVED4[61 + 64]; + + __IO uint32_t BKP[3]; //é—è·¨å–é‹å©šå¹é‘芥晸閹归攱éžå©šå¹é‘芥晸閹瑰嘲é¦åº¢æ½éî„€î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ + + //RTC Power Domain: 0x4001E000 + uint32_t RESERVED5[(0x4001E000 - 0x40000508) / 4 - 1]; + + __IO uint32_t RTCBKP[8]; //RTCé—è·¨å–é‹å©šå¹é–¿å¬¬çˆ±é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿祹閹æ’瀚归柨é”稿祹éŽé›å«¯éŽ»îˆå¹é‘芥晸閺傘倖瀚� + + __IO uint32_t LRCCR; //Low speed RC Control Register + __IO uint32_t LRCTRIM0; //Low speed RC Trim + __IO uint32_t LRCTRIM1; + + uint32_t RESERVED6; + + __IO uint32_t RTCLDOTRIM; //RTC Power Domain LDO Trim + + //Analog Control: 0x40031000 + uint32_t RESERVED7[(0x40031000 - 0x4001E030) / 4 - 1]; + + __IO uint32_t HRCCR; //High speed RC Control Register + __IO uint32_t HRC20M; //[24:0] High speed RC Trim Value for 20MHz + __IO uint32_t HRC40M; //[24:0] High speed RC Trim Value for 40MHz + + uint32_t RESERVED8[3]; + + __IO uint32_t BGTRIM; + + __IO uint32_t TEMPCR; //é—跨喖鎽î…惔锕佹彧閹风兘é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å“„ç±éŽé›å«¯éŽ»îˆå¹é‘芥晸閺傘倖瀚� + + __IO uint32_t XTALCR; + + __IO uint32_t PLLCR; + __IO uint32_t PLLDIV; + __IO uint32_t PLLSET; + __IO uint32_t PLLLOCK; //[0] 1 PLLé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· + + __IO uint32_t BODIE; + __IO uint32_t BODIF; + + __IO uint32_t ADC1IN7; + + __IO uint32_t BODCR; +} SYS_TypeDef; + +#define SYS_CLKSEL_LFCK_Pos 0 //Low Frequency Clock Source 0 LRC 1 PLL +#define SYS_CLKSEL_LFCK_Msk (0x01 << SYS_CLKSEL_LFCK_Pos) +#define SYS_CLKSEL_HFCK_Pos 1 //High Frequency Clock Source 0 HRC 1 XTAL +#define SYS_CLKSEL_HFCK_Msk (0x01 << SYS_CLKSEL_HFCK_Pos) +#define SYS_CLKSEL_SYS_Pos 2 //ç¼îˆå´µç»®æ´ªå¼®é«æ›Ÿæ™¸é–ºå‚˜å€–瀚归柅澶愭晸閺傘倖瀚� 0 LFCK 1 HFCK +#define SYS_CLKSEL_SYS_Msk (0x01 << SYS_CLKSEL_SYS_Pos) + +#define SYS_CLKDIV_SYS_Pos 0 //ç¼îˆå´µç»®æ´ªå¼®é«æ›Ÿæ™¸é–¹æ’儱é¤æ ­å¹é‘筋暥 0 1é—è·¨å–é‹å©šå¹é‘筋暥 1 2é—è·¨å–é‹å©šå¹é‘筋暥 +#define SYS_CLKDIV_SYS_Msk (0x01 << SYS_CLKDIV_SYS_Pos) +#define SYS_CLKDIV_PWM_Pos 1 //PWM 閺冨爼é撻幒銉ュ殩閹风兘顣� 0 1é—è·¨å–é‹å©šå¹é‘筋暥 1 8é—è·¨å–é‹å©šå¹é‘筋暥 +#define SYS_CLKDIV_PWM_Msk (0x01 << SYS_CLKDIV_PWM_Pos) +#define SYS_CLKDIV_SDRAM_Pos 2 //SDRAM閺冨爼é撻幒銉ュ殩閹风兘顣� 0 1é—è·¨å–é‹å©šå¹é‘筋暥 1 2é—è·¨å–é‹å©šå¹é‘筋暥 2 4é—è·¨å–é‹å©šå¹é‘筋暥 +#define SYS_CLKDIV_SDRAM_Msk (0x03 << SYS_CLKDIV_SDRAM_Pos) +#define SYS_CLKDIV_SDIO_Pos 4 //SDIO閺冨爼é撻幒銉ュ殩閹风兘顣� 0 1é—è·¨å–é‹å©šå¹é‘筋暥 1 2é—è·¨å–é‹å©šå¹é‘筋暥 2 4é—è·¨å–é‹å©šå¹é‘筋暥 3 8é—è·¨å–é‹å©šå¹é‘筋暥 +#define SYS_CLKDIV_SDIO_Msk (0x03 << SYS_CLKDIV_SDIO_Pos) + +#define SYS_CLKEN_GPIOA_Pos 0 +#define SYS_CLKEN_GPIOA_Msk (0x01 << SYS_CLKEN_GPIOA_Pos) +#define SYS_CLKEN_GPIOB_Pos 1 +#define SYS_CLKEN_GPIOB_Msk (0x01 << SYS_CLKEN_GPIOB_Pos) +#define SYS_CLKEN_GPIOC_Pos 2 +#define SYS_CLKEN_GPIOC_Msk (0x01 << SYS_CLKEN_GPIOC_Pos) +#define SYS_CLKEN_GPIOM_Pos 4 +#define SYS_CLKEN_GPIOM_Msk (0x01 << SYS_CLKEN_GPIOM_Pos) +#define SYS_CLKEN_GPION_Pos 5 +#define SYS_CLKEN_GPION_Msk (0x01 << SYS_CLKEN_GPION_Pos) +#define SYS_CLKEN_TIMR_Pos 6 +#define SYS_CLKEN_TIMR_Msk (0x01 << SYS_CLKEN_TIMR_Pos) +#define SYS_CLKEN_WDT_Pos 7 +#define SYS_CLKEN_WDT_Msk (0x01 << SYS_CLKEN_WDT_Pos) +#define SYS_CLKEN_ADC0_Pos 8 +#define SYS_CLKEN_ADC0_Msk (0x01 << SYS_CLKEN_ADC0_Pos) +#define SYS_CLKEN_PWM_Pos 9 +#define SYS_CLKEN_PWM_Msk (0x01 << SYS_CLKEN_PWM_Pos) +#define SYS_CLKEN_RTC_Pos 10 +#define SYS_CLKEN_RTC_Msk (0x01 << SYS_CLKEN_RTC_Pos) +#define SYS_CLKEN_UART0_Pos 11 +#define SYS_CLKEN_UART0_Msk (0x01 << SYS_CLKEN_UART0_Pos) +#define SYS_CLKEN_UART1_Pos 12 +#define SYS_CLKEN_UART1_Msk (0x01 << SYS_CLKEN_UART1_Pos) +#define SYS_CLKEN_UART2_Pos 13 +#define SYS_CLKEN_UART2_Msk (0x01 << SYS_CLKEN_UART2_Pos) +#define SYS_CLKEN_UART3_Pos 14 +#define SYS_CLKEN_UART3_Msk (0x01 << SYS_CLKEN_UART3_Pos) +#define SYS_CLKEN_UART4_Pos 15 +#define SYS_CLKEN_UART4_Msk (0x01 << SYS_CLKEN_UART4_Pos) +#define SYS_CLKEN_SPI0_Pos 16 +#define SYS_CLKEN_SPI0_Msk (0x01 << SYS_CLKEN_SPI0_Pos) +#define SYS_CLKEN_I2C0_Pos 17 +#define SYS_CLKEN_I2C0_Msk (0x01 << SYS_CLKEN_I2C0_Pos) +#define SYS_CLKEN_I2C1_Pos 18 +#define SYS_CLKEN_I2C1_Msk (0x01 << SYS_CLKEN_I2C1_Pos) +#define SYS_CLKEN_I2C2_Pos 19 +#define SYS_CLKEN_I2C2_Msk (0x01 << SYS_CLKEN_I2C2_Pos) +#define SYS_CLKEN_LCD_Pos 20 +#define SYS_CLKEN_LCD_Msk (0x01 << SYS_CLKEN_LCD_Pos) +#define SYS_CLKEN_GPIOP_Pos 21 +#define SYS_CLKEN_GPIOP_Msk (0x01 << SYS_CLKEN_GPIOP_Pos) +#define SYS_CLKEN_ANAC_Pos 22 //濡ç¹é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘筋暥é—跨喓娈曢鈺傚敾閹风兘é撶紒éåž«îŸé–¹é£Žå…˜é撻敓锟� +#define SYS_CLKEN_ANAC_Msk (0x01 << SYS_CLKEN_ANAC_Pos) +#define SYS_CLKEN_CRC_Pos 23 +#define SYS_CLKEN_CRC_Msk (0x01 << SYS_CLKEN_CRC_Pos) +#define SYS_CLKEN_RTCBKP_Pos 24 +#define SYS_CLKEN_RTCBKP_Msk (0x01 << SYS_CLKEN_RTCBKP_Pos) +#define SYS_CLKEN_CAN_Pos 25 +#define SYS_CLKEN_CAN_Msk (0x01 << SYS_CLKEN_CAN_Pos) +#define SYS_CLKEN_SDRAM_Pos 26 +#define SYS_CLKEN_SDRAM_Msk (0x01 << SYS_CLKEN_SDRAM_Pos) +#define SYS_CLKEN_NORFL_Pos 27 //NOR Flash +#define SYS_CLKEN_NORFL_Msk (0x01 << SYS_CLKEN_NORFL_Pos) +#define SYS_CLKEN_RAMC_Pos 28 +#define SYS_CLKEN_RAMC_Msk (0x01 << SYS_CLKEN_RAMC_Pos) +#define SYS_CLKEN_SDIO_Pos 29 +#define SYS_CLKEN_SDIO_Msk (0x01 << SYS_CLKEN_SDIO_Pos) +#define SYS_CLKEN_ADC1_Pos 30 +#define SYS_CLKEN_ADC1_Msk (0x01 << SYS_CLKEN_ADC1_Pos) +#define SYS_CLKEN_ALIVE_Pos 31 //CHIPALIVEé—è·¨å–é‹å©šå¹é–¿å¬¬çˆ±é—è·¨å–é‹å©šå¹æ¤‹åº¨å…‡ç¼‚佺å–妞傞柨é”å‘Šç®é–¹ç–¯æ¸¹æ¿žå›¬æŸ¨é”å‘Šç®é–¹å‡¤æ‹· +#define SYS_CLKEN_ALIVE_Msk (0x01 << SYS_CLKEN_ALIVE_Pos) + +#define SYS_SLEEP_SLEEP_Pos 0 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚�1é—è·¨å–é‹å©šå¹æ¤‹åº¨å…‡ç¼‚佺喖é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚ç­LEEP濡€崇础 +#define SYS_SLEEP_SLEEP_Msk (0x01 << SYS_SLEEP_SLEEP_Pos) +#define SYS_SLEEP_DEEP_Pos 1 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚�1é—è·¨å–é‹å©šå¹æ¤‹åº¨å…‡ç¼‚佺喖é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚ç­TOP SLEEP濡€崇础 +#define SYS_SLEEP_DEEP_Msk (0x01 << SYS_SLEEP_DEEP_Pos) + +#define SYS_RSTCR_SYS_Pos 0 //閸愶拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚圭化鑽ょ埠é—è·¨å–é‹å©šå¹é“šå‚œç§´é—è·¨å–é‹å©šå¹æ¤‹åº˜â‚¬æ ­æŸ¨é”å‘Šç®é–¹é£Žå…˜é撻惃é¡æ°¼å•‡é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ +#define SYS_RSTCR_SYS_Msk (0x01 << SYS_RSTCR_SYS_Pos) +#define SYS_RSTCR_FLASH_Pos 1 //閸愶拷1é—è·¨å–é‹å©šå¹ç»‹îš²ASHé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œî±é—跨喕濞囬棃鈺傚î¶å¨´ï½…秹é撻弬銈嗗î¶ç»¾î…§å‰Ÿé撻弬銈嗗î¶é—跨喓娈曠拋瑙勫î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SYS_RSTCR_FLASH_Msk (0x01 << SYS_RSTCR_FLASH_Pos) +#define SYS_RSTCR_PWM_Pos 2 //閸愶拷1é—è·¨å–é‹å©šå¹ç»‹ç™¢Mé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规稉鈧柨é”诲â–闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨é”烘畷é ä½½î‰ç€šå½’柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define SYS_RSTCR_PWM_Msk (0x01 << SYS_RSTCR_PWM_Pos) +#define SYS_RSTCR_CPU_Pos 3 //閸愶拷1é—è·¨å–é‹å©šå¹ç»‹î”¶Ué—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规稉鈧柨é”诲â–闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨é”烘畷é ä½½î‰ç€šå½’柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define SYS_RSTCR_CPU_Msk (0x01 << SYS_RSTCR_CPU_Pos) +#define SYS_RSTCR_DMA_Pos 4 //閸愶拷1é—è·¨å–é‹å©šå¹ç»‹î—³Aé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规稉鈧柨é”诲â–闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨é”烘畷é ä½½î‰ç€šå½’柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define SYS_RSTCR_DMA_Msk (0x01 << SYS_RSTCR_DMA_Pos) +#define SYS_RSTCR_NORFLASH_Pos 5 //閸愶拷1é—è·¨å–é‹å©šå¹ç»‹ç”‡R Flashé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œî±é—跨喕濞囬棃鈺傚î¶å¨´ï½…秹é撻弬銈嗗î¶ç»¾î…§å‰Ÿé撻弬銈嗗î¶é—跨喓娈曠拋瑙勫î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SYS_RSTCR_NORFLASH_Msk (0x01 << SYS_RSTCR_NORFLASH_Pos) +#define SYS_RSTCR_SRAM_Pos 6 //閸愶拷1é—è·¨å–é‹å©šå¹ç»‹ç¢¦AMé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œî±é—跨喕濞囬棃鈺傚î¶å¨´ï½…秹é撻弬銈嗗î¶ç»¾î…§å‰Ÿé撻弬銈嗗î¶é—跨喓娈曠拋瑙勫î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SYS_RSTCR_SRAM_Msk (0x01 << SYS_RSTCR_SRAM_Pos) +#define SYS_RSTCR_SDRAM_Pos 7 //閸愶拷1é—è·¨å–é‹å©šå¹ç»‹ç¢ŠRAMé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œî±é—跨喕濞囬棃鈺傚î¶å¨´ï½…秹é撻弬銈嗗î¶ç»¾î…§å‰Ÿé撻弬銈嗗î¶é—跨喓娈曠拋瑙勫î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SYS_RSTCR_SDRAM_Msk (0x01 << SYS_RSTCR_SDRAM_Pos) +#define SYS_RSTCR_SDIO_Pos 8 //閸愶拷1é—è·¨å–é‹å©šå¹ç»‹ç¢ŠIOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规稉鈧柨é”诲â–闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨é”烘畷é ä½½î‰ç€šå½’柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define SYS_RSTCR_SDIO_Msk (0x01 << SYS_RSTCR_SDIO_Pos) +#define SYS_RSTCR_LCD_Pos 9 //閸愶拷1é—è·¨å–é‹å©šå¹ç»‹ç»Dé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规稉鈧柨é”诲â–闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨é”烘畷é ä½½î‰ç€šå½’柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define SYS_RSTCR_LCD_Msk (0x01 << SYS_RSTCR_LCD_Pos) +#define SYS_RSTCR_CAN_Pos 10 //閸愶拷1é—è·¨å–é‹å©šå¹ç»‹î”§Né—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规稉鈧柨é”诲â–闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨é”烘畷é ä½½î‰ç€šå½’柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define SYS_RSTCR_CAN_Msk (0x01 << SYS_RSTCR_CAN_Pos) + +#define SYS_RSTSR_POR_Pos 0 //1 é—è·¨å–é‹å©šå¹é‘芥晸éžæ¶™îšˆå¨…㈤å¹ç»‹ç™˜Ré—è·¨å–é‹å©šå¹é“šå‚œç§´é—è·¨å–é‹å©šå¹å®„æ¿æ™¸1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SYS_RSTSR_POR_Msk (0x01 << SYS_RSTSR_POR_Pos) +#define SYS_RSTSR_BOD_Pos 1 //1 é—è·¨å–é‹å©šå¹é‘芥晸éžæ¶™îšˆå¨…㈤å¹ç»‹î“•Dé—è·¨å–é‹å©šå¹é“šå‚œç§´é—è·¨å–é‹å©šå¹å®„æ¿æ™¸1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SYS_RSTSR_BOD_Msk (0x01 << SYS_RSTSR_BOD_Pos) +#define SYS_RSTSR_PIN_Pos 2 //1 é—è·¨å–é‹å©šå¹é‘芥晸éžæ¶™îšˆå¨…㈤å¹é‘芥晸éŸæ¬™ç¶éŽæ’®æŸ¨é”å‘Šç®é–¹é£Žå…˜é撻懘姘舵交閹疯渹ç¼å‘´æŸ¨é”å‘Šç®é–¹å³°å˜²éŸï¿½1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SYS_RSTSR_PIN_Msk (0x01 << SYS_RSTSR_PIN_Pos) +#define SYS_RSTSR_WDT_Pos 3 //1 é—è·¨å–é‹å©šå¹é‘芥晸éžæ¶™îšˆå¨…㈤å¹ç»‹ç¯‹Té—è·¨å–é‹å©šå¹é“šå‚œç§´é—è·¨å–é‹å©šå¹å®„æ¿æ™¸1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SYS_RSTSR_WDT_Msk (0x01 << SYS_RSTSR_WDT_Pos) +#define SYS_RSTSR_SWRST_Pos 4 //Software Reset, 1 é—è·¨å–é‹å©šå¹é‘芥晸éžæ¶™îšˆå¨…㈤å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撴潪澶哥串閹风兘é撻崣é¡î„嫹1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SYS_RSTSR_SWRST_Msk (0x01 << SYS_RSTSR_SWRST_Pos) + +#define SYS_LRCCR_OFF_Pos 0 //Low Speed RC Off +#define SYS_LRCCR_OFF_Msk (0x01 << SYS_LRCCR_OFF_Pos) + +#define SYS_LRCTRIM0_R_Pos 0 //LRCé—跨喕顢滅喊澶嬪î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担锟� +#define SYS_LRCTRIM0_R_Msk (0x7FFF << SYS_LRCTRIM0_R_Pos) +#define SYS_LRCTRIM0_M_Pos 15 //LRCé—跨喎褰ㄧ喊澶嬪î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担锟� +#define SYS_LRCTRIM0_M_Msk (0x3F << SYS_LRCTRIM2_M_Pos) +#define SYS_LRCTRIM0_F_Pos 21 //LRC缂佸æ£é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担锟� +#define SYS_LRCTRIM0_F_Msk (0x7FF << SYS_LRCTRIM0_F_Pos) + +#define SYS_LRCTRIM1_U_Pos 0 //LRC Ué—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹ç–¯æ¸¹ç¼ï¿½ +#define SYS_LRCTRIM1_U_Msk (0x7FFF << SYS_LRCTRIM1_U_Pos) + +#define SYS_HRCCR_DBL_Pos 0 //Double Frequency 0 20MHz 1 40MHz +#define SYS_HRCCR_DBL_Msk (0x01 << SYS_HRCCR_DBL_Pos) +#define SYS_HRCCR_OFF_Pos 1 //High speed RC Off +#define SYS_HRCCR_OFF_Msk (0x01 << SYS_HRCCR_OFF_Pos) + +#define SYS_HRC20M_R_Pos 0 //HRC 20MHzé—跨喕顢滅喊澶嬪î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担锟� +#define SYS_HRC20M_R_Msk (0x3FFF << SYS_HRC20M_R_Pos) +#define SYS_HRC20M_F_Pos 16 //HRC 20MHz缂佸æ£é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担锟� +#define SYS_HRC20M_F_Msk (0x7FF << SYS_HRC20M_F_Pos) + +#define SYS_HRC40M_R_Pos 0 //HRC 40MHzé—跨喕顢滅喊澶嬪î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担锟� +#define SYS_HRC40M_R_Msk (0x3FFF << SYS_HRC40M_R_Pos) +#define SYS_HRC40M_F_Pos 16 //HRC 40MHz缂佸æ£é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担锟� +#define SYS_HRC40M_F_Msk (0x7FF << SYS_HRC40M_F_Pos) + +#define SYS_TEMPCR_OFF_Pos 0 //é—跨喖鎽î…惔锕佹彧閹风兘é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閹æ­äºéžå©šå¹é”Ÿï¿½ +#define SYS_TEMPCR_OFF_Msk (0x01 << SYS_TEMPCR_OFF_Pos) +#define SYS_TEMPCR_TRIM_Pos 4 //é—跨喖鎽î…惔锕佹彧閹风兘é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹ç»‹ç¤¡IM +#define SYS_TEMPCR_TRIM_Msk (0x3F << SYS_TEMPCR_TRIM_Pos) + +#define SYS_XTALCR_EN_Pos 0 +#define SYS_XTALCR_EN_Msk (0x01 << SYS_XTALCR_EN_Pos) + +#define SYS_PLLCR_OUTEN_Pos 0 //閸欘亪é撻弬銈嗗î¶LOCKé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define SYS_PLLCR_OUTEN_Msk (0x01 << SYS_PLLCR_OUTEN_Pos) +#define SYS_PLLCR_INSEL_Pos 1 //0 XTAL 1 HRC +#define SYS_PLLCR_INSEL_Msk (0x01 << SYS_PLLCR_INSEL_Pos) +#define SYS_PLLCR_OFF_Pos 2 +#define SYS_PLLCR_OFF_Msk (0x01 << SYS_PLLCR_OFF_Pos) + +#define SYS_PLLDIV_FBDIV_Pos 0 //PLL FeedBacké—è·¨å–é‹å©šå¹é‘筋暥é—è·¨å–鑼庢æ½éî„€î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ +//VCOé—è·¨å–é‹å©šå¹é‘芥晸閻欙紕顣å¹é‘芥晸閿燂拷 = PLLé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归弮é«æ›Ÿæ™¸é–ºå‚˜å€–瀚� / INDIV * 4 * FBDIV +//PLLé—è·¨å–é‹å©šå¹é‘芥晸閻欙紕顣å¹é‘芥晸閿燂拷 = PLLé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归弮é«æ›Ÿæ™¸é–ºå‚˜å€–瀚� / INDIV * 4 * FBDIV / OUTDIV = VCOé—è·¨å–é‹å©šå¹é‘芥晸閻欙紕顣å¹é‘芥晸閿燂拷 / OUTDIV +#define SYS_PLLDIV_FBDIV_Msk (0x1FF << SYS_PLLDIV_FBDIV_Pos) +#define SYS_PLLDIV_ADDIV_Pos 9 //ADC閺冨爼é撻幒銉ょ串閹风兘é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹ç»‹çª©Oé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å“„ç±ç»¾æ¿î˜°ç€šå½’柨é”å‘Šç®é–¹çƒ½æ”±å¦žå‚žæŸ¨é”稿å¤é–¿æ¿†ç¹‘瀚归柨é”å‘Šç®é–¹é£ŽîŸ…DDIVé—è·¨å–é‹å©šå¹é‘筋暥é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规稉绡圖Cé—è·¨å–é‹å©šå¹é¤îˆ›ç¥®é—è·¨å–é‹å©šå¹é–¿å¬«î˜§é—è·¨å–é‹å©šå¹é”Ÿï¿½ +#define SYS_PLLDIV_ADDIV_Msk (0x1F << SYS_PLLDIV_ADDIV_Pos) +#define SYS_PLLDIV_ADVCO_Pos 14 //0 VCOé—è·¨å–é‹å©šå¹é‘芥晸閿燂拷16é—è·¨å–é‹å©šå¹é‘筋暥é—è·¨å–é‹å©šå¹é“šå‚礋ADC閺冨爼é撻幒銉ょ串閹凤拷 1 VCOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻敓锟�32é—è·¨å–é‹å©šå¹é‘筋暥é—è·¨å–é‹å©šå¹é“šå‚礋ADC閺冨爼é撻幒銉ょ串閹凤拷 2 VCOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻敓锟�64é—è·¨å–é‹å©šå¹é‘筋暥é—è·¨å–é‹å©šå¹é“šå‚礋ADC閺冨爼é撻幒銉ょ串閹凤拷 +#define SYS_PLLDIV_ADVCO_Msk (0x03 << SYS_PLLDIV_ADVCO_Pos) +#define SYS_PLLDIV_INDIV_Pos 16 //PLL é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚瑰┃鎰é—è·¨å–甯撮崙銈嗗î¶å¦«å¸®æ‹· +#define SYS_PLLDIV_INDIV_Msk (0x1F << SYS_PLLDIV_INDIV_Pos) +#define SYS_PLLDIV_OUTDIV_Pos 24 //PLL é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å“„ç±ç»¾æ¿î˜°ç€šå½’柨é•å‚›å«¹0 8é—è·¨å–é‹å©šå¹é‘筋暥 1 4é—è·¨å–é‹å©šå¹é‘筋暥 0 2é—è·¨å–é‹å©šå¹é‘筋暥 +#define SYS_PLLDIV_OUTDIV_Msk (0x03 << SYS_PLLDIV_OUTDIV_Pos) + +#define SYS_PLLSET_LPFBW_Pos 0 //PLL Low Pass Filter Bandwidth +#define SYS_PLLSET_LPFBW_Msk (0x0F << SYS_PLLSET_LPFBW_Pos) +#define SYS_PLLSET_BIASADJ_Pos 4 //PLL Current Bias Adjustment +#define SYS_PLLSET_BIASADJ_Msk (0x03 << SYS_PLLSET_BIASADJ_Pos) +#define SYS_PLLSET_REFVSEL_Pos 6 //PLL Reference Voltage Select +#define SYS_PLLSET_REFVSEL_Msk (0x03 << SYS_PLLSET_REFVSEL_Pos) +#define SYS_PLLSET_CHPADJL_Pos 8 //PLL charge pump LSB current Adjustment +#define SYS_PLLSET_CHPADJL_Msk (0x07 << SYS_PLLSET_CHPADJL_Pos) +#define SYS_PLLSET_CHPADJM_Pos 11 //PLL charge pump MSB current Adjustment +#define SYS_PLLSET_CHPADJM_Msk (0x03 << SYS_PLLSET_CHPADJM_Pos) + +#define SYS_BODIE_1V9_Pos 0 //BOD 1.9Vé—跨喖銈虹涵閿嬪î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”峰建é ä½½î‰ç€šè§„æ‹…é§æ¥æ™¸é–ºå‚˜å€–瀚� +#define SYS_BODIE_1V9_Msk (0x01 << SYS_BODIE_1V9_Pos) +#define SYS_BODIE_2V2_Pos 1 //BOD 2.2Vé—跨喖銈虹涵閿嬪î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”峰建é ä½½î‰ç€šè§„æ‹…é§æ¥æ™¸é–ºå‚˜å€–瀚� +#define SYS_BODIE_2V2_Msk (0x01 << SYS_BODIE_2V2_Pos) + +#define SYS_BODIF_1V9_Pos 0 //BOD 1.9Vé—跨喖銈虹涵閿嬪î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”峰建é ä½½î‰ç€šå½’悩鑸碘å“渚€é撻弬銈嗗î¶é–¸æ„¶æ‹·1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SYS_BODIF_1V9_Msk (0x01 << SYS_BODIF_1V9_Pos) +#define SYS_BODIF_2V2_Pos 1 //BOD 2.2Vé—跨喖銈虹涵閿嬪î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”峰建é ä½½î‰ç€šå½’悩鑸碘å“渚€é撻弬銈嗗î¶é–¸æ„¶æ‹·1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SYS_BODIF_2V2_Msk (0x01 << SYS_BODIF_2V2_Pos) + +#define SYS_ADC1IN7_SEL_Pos 0 //ADC1濡ç¹é撻弬銈嗗î¶æ¿¡îˆ¤ç¹é撻弬銈嗗î¶é—岸é撻弬銈嗗î¶7é—è·¨å–é‹å©šå¹é”Ÿï¿½1 é—跨喖鎽î…惔锕佹彧閹风兘é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ 2 é—è·¨å–é‹å©šå¹é–¿å¬¬æ¯‰é—跨喓é›ã‚‰æ•“锟� 3 RTCé—è·¨å–é‹å©šå¹é–¿å¬¬çˆ±é—è·¨å–é‹å©šå¹ç»‹î“ 4 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚瑰┃鎰版晸閺傘倖瀚笲G 5 PDM33 +#define SYS_ADC1IN7_SEL_Msk (0x0F << SYS_ADC1IN7_SEL_Pos) +#define SYS_ADC1IN7_IOON_Pos 4 //ADC1濡ç¹é撻弬銈嗗î¶æ¿¡îˆ¤ç¹é撻弬銈嗗î¶é—岸é撻弬銈嗗î¶7é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚笽Oé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SYS_ADC1IN7_IOON_Msk (0x01 << SYS_ADC1IN7_IOON_Pos) + +#define SYS_BODCR_EN_Pos 0 +#define SYS_BODCR_EN_Msk (0x01 << SYS_BODCR_EN_Pos) + +typedef struct +{ + __IO uint32_t PORTA_SEL; //é—è·¨å–é‹å©šå¹ç»‹ç™˜RTA_SEL[2n+2:2n]é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规惔éƒå Ÿæ™¸é–ºå‚˜å€–瀚归å´æ¿‚告晸閺傘倖瀚归柨é”å‘Šç®é–¹é£ŽÃ²ORTA.PINné—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻惌é¡ã‚ŽåŠœé–¹é£ŽÄ›PIOé—è·¨å–é‹å©šå¹é–¿å¬†ä¾€æŸ¨é”æ掗妴渚€é撻弬銈嗗î¶é—跨喕顢滅粵澶屾îŸé–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ + //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归å´é—‚磋礋PORTA_PINn_FUNMUX閺冨爼é撻弬銈嗗î¶PORTA.PINné—è·¨å–é‹å©šå¹é‘芥晸閼存艾çå‘´å¹é‘解å“姘舵晸閺傘倖瀚筆ORTA_MUXé—è·¨å–鑼庢æ½éî„€î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿å¤ç»¾æ¿î˜°ç€šå½’柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ + __IO uint32_t PORTB_SEL; + + __IO uint32_t PORTC_SEL; + + uint32_t RESERVED[5]; + + __IO uint32_t PORTM_SEL0; + + __IO uint32_t PORTM_SEL1; + + uint32_t RESERVED2[2]; + + __IO uint32_t PORTN_SEL0; + + __IO uint32_t PORTN_SEL1; + + uint32_t RESERVED3[2]; + + __IO uint32_t PORTP_SEL0; + + __IO uint32_t PORTP_SEL1; + + uint32_t RESERVED4[46]; + + __IO uint32_t PORTA_MUX0; + + __IO uint32_t PORTA_MUX1; + + uint32_t RESERVED5[2]; + + __IO uint32_t PORTB_MUX0; + + __IO uint32_t PORTB_MUX1; + + uint32_t RESERVED6[2]; + + __IO uint32_t PORTC_MUX0; + + __IO uint32_t PORTC_MUX1; + + uint32_t RESERVED7[14]; + + __IO uint32_t PORTM_MUX0; + + __IO uint32_t PORTM_MUX1; + + __IO uint32_t PORTM_MUX2; + + __IO uint32_t PORTM_MUX3; + + __IO uint32_t PORTN_MUX0; + + __IO uint32_t PORTN_MUX1; + + __IO uint32_t PORTN_MUX2; + + uint32_t RESERVED8; + + __IO uint32_t PORTP_MUX0; + + __IO uint32_t PORTP_MUX1; + + __IO uint32_t PORTP_MUX2; + + __IO uint32_t PORTP_MUX3; + + uint32_t RESERVED9[28]; + + __IO uint32_t PORTA_PULLU; //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担é§æ¥æ™¸é–ºå‚˜å€–瀚� + + uint32_t RESERVED10[3]; + + __IO uint32_t PORTC_PULLU; + + uint32_t RESERVED11[3]; + + __IO uint32_t PORTM_PULLU; + + uint32_t RESERVED12[3]; + + __IO uint32_t PORTP_PULLU; + + uint32_t RESERVED13[51]; + + __IO uint32_t PORTB_PULLD; //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担é§æ¥æ™¸é–ºå‚˜å€–瀚� + + uint32_t RESERVED14[3]; + + __IO uint32_t PORTD_PULLD; + + uint32_t RESERVED15[3]; + + __IO uint32_t PORTN_PULLD; + + uint32_t RESERVED16[135]; + + __IO uint32_t PORTM_DRIVS; //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚瑰娲î…晸閺傘倖瀚� + + uint32_t RESERVED17[3]; + + __IO uint32_t PORTN_DRIVS; + + uint32_t RESERVED18[3]; + + __IO uint32_t PORTP_DRIVS; + + uint32_t RESERVED19[39]; + + __IO uint32_t PORTA_INEN; //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担é§æ¥æ™¸é–ºå‚˜å€–瀚� + + uint32_t RESERVED20[3]; + + __IO uint32_t PORTB_INEN; + + uint32_t RESERVED21[3]; + + __IO uint32_t PORTC_INEN; + + uint32_t RESERVED22[7]; + + __IO uint32_t PORTM_INEN; + + uint32_t RESERVED23[3]; + + __IO uint32_t PORTN_INEN; + + uint32_t RESERVED24[3]; + + __IO uint32_t PORTP_INEN; +} PORT_TypeDef; + +typedef struct +{ + __IO uint32_t DATA; +#define PIN0 0 +#define PIN1 1 +#define PIN2 2 +#define PIN3 3 +#define PIN4 4 +#define PIN5 5 +#define PIN6 6 +#define PIN7 7 +#define PIN8 8 +#define PIN9 9 +#define PIN10 10 +#define PIN11 11 +#define PIN12 12 +#define PIN13 13 +#define PIN14 14 +#define PIN15 15 +#define PIN16 16 +#define PIN17 17 +#define PIN18 18 +#define PIN19 19 +#define PIN20 20 +#define PIN21 21 +#define PIN22 22 +#define PIN23 23 +#define PIN24 24 + + __IO uint32_t DIR; //0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� 1 é—è·¨å–é‹å©šå¹é‘芥晸閿燂拷 + + __IO uint32_t INTLVLTRG; //Interrupt Level Trigger 1 é—è·¨å–é‹å©šå¹å®„伴挬é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”峰建é ä½½î‰ç€šï¿½ 0 é—è·¨å–é‹å©šå¹é‘芥晸閹æ­äº£éŽ»îˆå¹é‘芥晸閺傘倖瀚归柨é”峰建é ä½½î‰ç€šï¿½ + + __IO uint32_t INTBE; //Both Edgeé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚笽NTLVLTRGé—è·¨å–é‹å©šå¹é“šå‚礋é—è·¨å–é‹å©šå¹é‘芥晸閹æ­äº£éŽ»îˆå¹é‘芥晸閺傘倖瀚归柨é”峰建é ä½½î‰ç€šå½’å¼®é«æ›Ÿæ™¸é–ºå‚˜å€–瀚归柨é”å‘Šç®é–¹ç–¯æ¸¹ç¼å‘´æŸ¨é”å‘Šç®é–¹å‡¤æ‹·1é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿焻閻氬瓨瀚归柨é”兼應閺傘倖瀚归柨é”稿焻é ä½½î‰ç€šå½’柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喎褰ㄩ弬顓ㄧ秶閹风兘é撻弬銈嗗î¶0閺冨爼é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶INTRISEENé—éæ’»å¼¬éŠˆå——î¶ + + __IO uint32_t INTRISEEN; //Interrupt Rise Edge Enable 1 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹·/é—跨喓é¡î†å–Šæ¾¶å¬ªî¶æ¥ ç‚´å¨Šé撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閸欘å‰é¡”æ„°å¹é”Ÿï¿½ 0 é—跨喖鎽îˆå¼¬éŠˆå——î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½/é—跨喖é™è™¹å–Šæ¾¶å¬ªî¶æ¥ ç‚´å¨Šé撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閸欘å‰é¡”æ„°å¹é”Ÿï¿½ + + __IO uint32_t INTEN; //1 é—跨喎褰ㄧ拋瑙勫î¶å¨´ï½…潡éæ’»å¼¬éŠˆå——î¶ 0 é—跨喎褰ㄩ弬顓熸ç®é–¹çƒ½æ”±é¡’� + + __IO uint32_t INTRAWSTAT; //é—跨喎褰ㄩ弬顓犮€嬮å¹æ¤‹åº¡ç¦ƒé–µå¤‹æ£æµœçƒ½å¹é–¿å¬¬æ‡žé—è·¨å–é‹å©šå¹æ¤‹åº¡ç¦ƒé–ºå‚˜å€–瀚归懜婊堟晸閺傘倖瀚归柨é”å‘Šç®é–¹å³°å˜²å®“忕化濠氭晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻敓锟� 1 é—è·¨å–é‹å©šå¹æ¤‹åº¡ç¦ƒé–ºå‚˜å€–瀚归柨é”å‘Šç®é–¹å³°å˜²å®“忓ú妤呮晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨噦鎷� 0 濞岋ç¹é撻崣é¡ã‚ƒâ‚¬å¬®å¹æ¤‹åº¡ç¦ƒé–ºå‚˜å€–瀚归崡é›å©„é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻敓锟� + + __IO uint32_t INTSTAT; //INTSTAT.PIN0 = INTRAWSTAT.PIN0 & INTEN.PIN0 + + __IO uint32_t INTCLR; //閸愶拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归崡绋款€掗柨é”活敎閹惧æ‡ç€šå½’柨é”活敎娴兼瑦瀚归崨姗€é撻弬銈嗗î¶é–¸æ¥Šå™£é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹å®„æ¿ç¥»é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é•å‚›å«¹ +} GPIO_TypeDef; + +typedef struct +{ + __IO uint32_t LDVAL; //é—è·¨å–é‹å©šå¹é–¿å¬«î˜§é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å³°å˜²éˆ§î„€ã‚¸é撻弬銈嗗î¶å¨´ï½…潡é撻弶鎵皑閹烽攱妞傞柨é”å‘Šç®é–¹é£Žå…˜é撻幒銉ㄦ彧閹风兘é撻弬銈嗗î¶é–¸å©‚ジé撻弬銈嗗î¶å©µî†¼îƒ‰é撻弬銈嗗î¶é—跨喖鎽îˆæŸ…鎺斻€嬮å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· + + __I uint32_t CVAL; //é—è·¨å–é‹å©šå¹é–¿å¬«î˜§é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归崜宥呪å“濂告晸閺傘倖瀚ç­DVAL-CVAL é—跨喓é—崇涵閿嬪î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”虹哺ç¼æ¥æ¢¹éžå©šå¹é‘芥晸閿燂拷 + + __IO uint32_t CTRL; +} TIMR_TypeDef; + +#define TIMR_CTRL_EN_Pos 0 //é—è·¨å–é‹å©šå¹é“šå‚œç§´é—è·¨å–é‹å©šå¹é”Ÿï¿½1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚筎IMRé—è·¨å–é‹å©šå¹ç»‹ç¼VALé—è·¨å–é‹å©šå¹å®„邦潗é—è·¨å–é‹å©šå¹é‘芥晸é—å¥å³éˆ§î„帞銆嬮å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define TIMR_CTRL_EN_Msk (0x01 << TIMR_CTRL_EN_Pos) +#define TIMR_CTRL_CLKSRC_Pos 1 //閺冨爼é撻弬銈嗗î¶æ¿ Ñ„劙é撻弬銈嗗î¶0 é—跨喕濡拠褎瀚圭化鑽ょ埠閺冨爼éæ’»å¼¬éŠˆå——î¶ 1 é—跨喕袙é—劑é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨噦鎷� +#define TIMR_CTRL_CLKSRC_Msk (0x01 << TIMR_CTRL_CLKSRC_Pos) +#define TIMR_CTRL_CASCADE_Pos 2 //1 TIMRxé—è·¨å–鑼庣涵閿嬪î¶é—è·¨å–é‹å©šå¹é–¿å¬«î˜§é—è·¨å–é‹å©šå¹é“šå‚礋TIMRx-1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£ŽæŸ‰å¦«æ—ˆæŸ¨é•å‚›å«¹ +#define TIMR_CTRL_CASCADE_Msk (0x01 << TIMR_CTRL_CASCADE_Pos) + +typedef struct +{ + __IO uint32_t PCTRL; //Pulse Controlé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–鑼庨æ•è¹‡æ–¿î¶é—è·¨å–é‹å©šå¹é‘芥晸閻欌€崇槑é‰å ¢å“瀚归柨é”å‘Šç®é–¹å‡¤æ‹· + + __I uint32_t PCVAL; //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喓绮æ幉瀣î¶é—è·¨å–é‹å©šå¹é‘芥晸éŸæ¬å¸žé©æ»ˆæ•“锟� + + uint32_t RESERVED[2]; + + __IO uint32_t IE; + + __IO uint32_t IF; + + __IO uint32_t HALT; +} TIMRG_TypeDef; + +#define TIMRG_PCTRL_EN_Pos 0 //é—è·¨å–é‹å©šå¹å®„邦潗é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹·32娴ｅ秹é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹·0é—è·¨å–é‹å©šå¹å®„邦潗é—è·¨å–é‹å©šå¹é‘芥晸é‰å å•°éŠ†å¬®å¹é‘芥晸閺傘倖瀚� +#define TIMRG_PCTRL_EN_Msk (0x01 << TIMRG_PCTRL_EN_Pos) +#define TIMRG_PCTRL_HIGH_Pos 1 //0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”ç…Žå¾ç»¾æ¿î˜°ç€šå½’ç®éŽ¶èŠ¥æ™¸é–ºå‚˜å€–瀚归柨é”å‘Šç®é–¹å‡¤æ‹· 1 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”侯仾绾æ¿î˜°ç€šå½’ç®éŽ¶èŠ¥æ™¸é–ºå‚˜å€–瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define TIMRG_PCTRL_HIGH_Msk (0x01 << TIMRG_PCTRL_HIGH_Pos) +#define TIMRG_PCTRL_CLKSRC_Pos 2 //閺冨爼é撻弬銈嗗î¶æ¿ Ñ„劙é撻弬銈嗗î¶0 é—跨喕濡拠褎瀚圭化鑽ょ埠閺冨爼éæ’»å¼¬éŠˆå——î¶ 1 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撴笟銉秶閹风兘é撻弬銈嗗î¶é—è·¨å–褰导娆愬î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归å´é¡’勬晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define TIMRG_PCTRL_CLKSRC_Msk (0x01 << TIMRG_PCTRL_CLKSRC_Pos) + +#define TIMRG_IE_TIMR0_Pos 0 +#define TIMRG_IE_TIMR0_Msk (0x01 << TIMRG_IE_TIMR0_Pos) +#define TIMRG_IE_TIMR1_Pos 1 +#define TIMRG_IE_TIMR1_Msk (0x01 << TIMRG_IE_TIMR1_Pos) +#define TIMRG_IE_TIMR2_Pos 2 +#define TIMRG_IE_TIMR2_Msk (0x01 << TIMRG_IE_TIMR2_Pos) +#define TIMRG_IE_TIMR3_Pos 3 +#define TIMRG_IE_TIMR3_Msk (0x01 << TIMRG_IE_TIMR3_Pos) +#define TIMRG_IE_TIMR4_Pos 4 +#define TIMRG_IE_TIMR4_Msk (0x01 << TIMRG_IE_TIMR4_Pos) +#define TIMRG_IE_TIMR5_Pos 5 +#define TIMRG_IE_TIMR5_Msk (0x01 << TIMRG_IE_TIMR5_Pos) +#define TIMRG_IE_PULSE_Pos 16 +#define TIMRG_IE_PULSE_Msk (0x01 << TIMRG_IE_PULSE_Pos) + +#define TIMRG_IF_TIMR0_Pos 0 //閸愶拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define TIMRG_IF_TIMR0_Msk (0x01 << TIMRG_IF_TIMR0_Pos) +#define TIMRG_IF_TIMR1_Pos 1 +#define TIMRG_IF_TIMR1_Msk (0x01 << TIMRG_IF_TIMR1_Pos) +#define TIMRG_IF_TIMR2_Pos 2 +#define TIMRG_IF_TIMR2_Msk (0x01 << TIMRG_IF_TIMR2_Pos) +#define TIMRG_IF_TIMR3_Pos 3 +#define TIMRG_IF_TIMR3_Msk (0x01 << TIMRG_IF_TIMR3_Pos) +#define TIMRG_IF_TIMR4_Pos 4 +#define TIMRG_IF_TIMR4_Msk (0x01 << TIMRG_IF_TIMR4_Pos) +#define TIMRG_IF_TIMR5_Pos 5 +#define TIMRG_IF_TIMR5_Msk (0x01 << TIMRG_IF_TIMR5_Pos) +#define TIMRG_IF_PULSE_Pos 16 +#define TIMRG_IF_PULSE_Msk (0x01 << TIMRG_IF_PULSE_Pos) + +#define TIMRG_HALT_TIMR0_Pos 0 //1 é—è·¨å–é‹å©šå¹å®„é¢ç²»é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define TIMRG_HALT_TIMR0_Msk (0x01 << TIMRG_HALT_TIMR0_Pos) +#define TIMRG_HALT_TIMR1_Pos 1 +#define TIMRG_HALT_TIMR1_Msk (0x01 << TIMRG_HALT_TIMR1_Pos) +#define TIMRG_HALT_TIMR2_Pos 2 +#define TIMRG_HALT_TIMR2_Msk (0x01 << TIMRG_HALT_TIMR2_Pos) +#define TIMRG_HALT_TIMR3_Pos 3 +#define TIMRG_HALT_TIMR3_Msk (0x01 << TIMRG_HALT_TIMR3_Pos) +#define TIMRG_HALT_TIMR4_Pos 4 +#define TIMRG_HALT_TIMR4_Msk (0x01 << TIMRG_HALT_TIMR4_Pos) +#define TIMRG_HALT_TIMR5_Pos 5 +#define TIMRG_HALT_TIMR5_Msk (0x01 << TIMRG_HALT_TIMR5_Pos) + +typedef struct +{ + __IO uint32_t DATA; + + __IO uint32_t CTRL; + + __IO uint32_t BAUD; + + __IO uint32_t FIFO; + + __IO uint32_t LINCR; + + union + { + __IO uint32_t CTSCR; + + __IO uint32_t RTSCR; + }; +} UART_TypeDef; + +#define UART_DATA_DATA_Pos 0 +#define UART_DATA_DATA_Msk (0x1FF << UART_DATA_DATA_Pos) +#define UART_DATA_VALID_Pos 9 //é—è·¨å–é‹å©šå¹ç»‹î—§TAé—跨喕顢滅拋瑙勫î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归弫é«ãƒ¦æ™¸å¨“氥儲é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–ºå†¨çˆ¼é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œç§´ç»¾î…§å‰Ÿé撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归崣é晸閺傘倖瀚归柨é”稿祹閻氬瓨瀚归柨é”烘畷é ä½½î‰ç€šå½’柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define UART_DATA_VALID_Msk (0x01 << UART_DATA_VALID_Pos) +#define UART_DATA_PAERR_Pos 10 //Parity Error +#define UART_DATA_PAERR_Msk (0x01 << UART_DATA_PAERR_Pos) + +#define UART_CTRL_TXIDLE_Pos 0 //TX IDLE: 0 é—è·¨å–é‹å©šå¹é‘芥晸閼哄倸é¤æ ­å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ 1 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归悩鑸碘å“渚€é撻弬銈嗗î¶æ¿žå²‹ç¹é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閹瑰嘲é¤æ ­å¹é‘芥晸閺傘倖瀚� +#define UART_CTRL_TXIDLE_Msk (0x01 << UART_CTRL_TXIDLE_Pos) +#define UART_CTRL_TXFF_Pos 1 //TX FIFO Full +#define UART_CTRL_TXFF_Msk (0x01 << UART_CTRL_TXFF_Pos) +#define UART_CTRL_TXIE_Pos 2 //TX é—跨喎褰ㄧ拋瑙勫î¶å¨´ï½…潡é撻弬銈嗗î¶: 1 TX FF é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閸婄喎é£é¹ƒæŸ¨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–ºå†¨çˆ¼é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閸欘å‰é¡”æ„°å¹é”Ÿï¿½ +#define UART_CTRL_TXIE_Msk (0x01 << UART_CTRL_TXIE_Pos) +#define UART_CTRL_RXNE_Pos 3 //RX FIFO Not Empty +#define UART_CTRL_RXNE_Msk (0x01 << UART_CTRL_RXNE_Pos) +#define UART_CTRL_RXIE_Pos 4 //RX é—跨喎褰ㄧ拋瑙勫î¶å¨´ï½…潡é撻弬銈嗗î¶: 1 RX FF é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿祹é‰å Ÿå„³é©å²„柨é”å°å“é”风暰é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归弮é«æ›Ÿæ™¸é–ºå‚˜å€–瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻崣é¡ãƒ®å•‡é–¹å‡¤æ‹· +#define UART_CTRL_RXIE_Msk (0x01 << UART_CTRL_RXIE_Pos) +#define UART_CTRL_RXOV_Pos 5 //RX FIFO Overflowé—è·¨å–é‹å©šå¹å®„æ¿æ™¸1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define UART_CTRL_RXOV_Msk (0x01 << UART_CTRL_RXOV_Pos) +#define UART_CTRL_TXDOIE_Pos 6 //TX Done é—跨喎褰ㄧ拋瑙勫î¶å¨´ï½…潡é撻弶甯秶閹风兘é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹ç»‹îš¯FOé—è·¨å–é‹å©šå¹é‘芥晸閹活厼é¤æ ­å¹é‘芥晸é—伴潧é¤æ ­å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹ç–¯æ¸¹ç¼å‘´æŸ¨é”惰寧é‰å ¢å“瀚归柨é”å‘Šç®é–¹é£Žå…˜é撶粣éㄦç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–褰弲éх串閹风兘é撻弬銈嗗î¶ç¼‚佺喖éæ’´îšœéšå­˜å«¹ +#define UART_CTRL_TXDOIE_Msk (0x01 << UART_CTRL_TXDOIE_Pos) +#define UART_CTRL_EN_Pos 9 +#define UART_CTRL_EN_Msk (0x01 << UART_CTRL_EN_Pos) +#define UART_CTRL_LOOP_Pos 10 +#define UART_CTRL_LOOP_Msk (0x01 << UART_CTRL_LOOP_Pos) +#define UART_CTRL_BAUDEN_Pos 13 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归崘锟�1 +#define UART_CTRL_BAUDEN_Msk (0x01 << UART_CTRL_BAUDEN_Pos) +#define UART_CTRL_TOIE_Pos 14 //TimeOut é—跨喎褰ㄧ拋瑙勫î¶å¨´ï½…潡é撻弶甯秶閹风兘é撻弬銈嗗î¶é—跨喓笑绾æ¿î˜°ç€šå½’柨é”è¤çª›é—‚堚晜瀚归柨é”活敎閸戙倖瀚归柨é”活殼閿涘瞼顒查å¹é‘芥晸閺傘倖瀚� TOTIME/BAUDRAUD é—è·¨å–é‹å©šå¹é–¿å¬¬æ¢¾é—跨喎褰ㄩ弬銈嗗î¶é—跨喓笑绾æ¿î˜°ç€šå½’柨é”兼應绾æ¿î˜°ç€šå½’柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define UART_CTRL_TOIE_Msk (0x01 << UART_CTRL_TOIE_Pos) +#define UART_CTRL_BRKDET_Pos 15 //LIN Break Detecté—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归悰é“хオIN Breaké—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚筊Xé—è·¨å–é‹å©šå¹é‘芥晸é‰å å•°éŠ†å¬®å¹æ¤‹åº¡ç¦ƒé–ºå‚˜å€–瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻敓锟�11娴ｅ秹é撻柊é¢æ®¿æšœé–¹å³°å˜²é–½ï¿½ +#define UART_CTRL_BRKDET_Msk (0x01 << UART_CTRL_BRKDET_Pos) +#define UART_CTRL_BRKIE_Pos 16 //LIN Break Detect é—跨喎褰ㄧ拋瑙勫î¶å¨´ï½…潡éæ’»å¼¬éŠˆå——î¶ +#define UART_CTRL_BRKIE_Msk (0x01 << UART_CTRL_BRKIE_Pos) +#define UART_CTRL_GENBRK_Pos 17 //Generate LIN Breaké—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£ŽÃ¬IN Break +#define UART_CTRL_GENBRK_Msk (0x01 << UART_CTRL_GENBRK_Pos) +#define UART_CTRL_DATA9b_Pos 18 //1 9娴ｅ秹é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œç§´ 0 8娴ｅ秹é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œç§´ +#define UART_CTRL_DATA9b_Msk (0x01 << UART_CTRL_DATA9b_Pos) +#define UART_CTRL_PARITY_Pos 19 //000 é—è·¨å–é‹å©šå¹é–¿å¬¬å¢¡é—è·¨å–é‹å©šå¹é”Ÿï¿½ 001 é—è·¨å–é‹å©šå¹é–¿å¬¬å¢¡é—è·¨å–é‹å©šå¹é”Ÿï¿½ 011 閸嬭埖é—庨柨é”å‘Šç®é–¹å‡¤æ‹· 101 é—è·¨å–é†â‚¬é ä½½î‰ç€šè§„稉锟�1 111 é—è·¨å–é†â‚¬é ä½½î‰ç€šè§„稉锟�0 +#define UART_CTRL_PARITY_Msk (0x07 << UART_CTRL_PARITY_Pos) +#define UART_CTRL_STOP2b_Pos 22 //1 2娴ｅ秴浠犲î¢é¡«î… ç§´ 0 1娴ｅ秴浠犲î¢é¡«î… ç§´ +#define UART_CTRL_STOP2b_Msk (0x03 << UART_CTRL_STOP2b_Pos) +#define UART_CTRL_TOTIME_Pos 24 //TimeOut 閺冨爼éæ’»å¼¬éŠˆå——î¶ = TOTIME/(BAUDRAUD/10) é—è·¨å–é‹å©šå¹é”Ÿï¿½ +//#define UART_CTRL_TOTIME_Msk (0xFF << UART_CTRL_TOTIME_Pos) é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喕濮らæ•é”Ÿï¿½ integer operation result is out of range +#define UART_CTRL_TOTIME_Msk ((uint32_t)0xFF << UART_CTRL_TOTIME_Pos) + +#define UART_BAUD_BAUD_Pos 0 //é—è·¨å–é‹å©šå¹é‘芥晸閼哄倽顕滈å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· = SYS_Freq/16/BAUD - 1 +#define UART_BAUD_BAUD_Msk (0x3FFF << UART_BAUD_BAUD_Pos) +#define UART_BAUD_TXD_Pos 14 //é—岸é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œç§´é—è·¨å–é‹å©šå¹æ¤‹åº¢çº¯é—è·¨å–甯寸拋瑙勫î¶é–¸æ¬ç‰ é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹ç»‹ç¤¨Dé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”è¤çª›é–»ã„¥å«®é¡£î‡€å¹å®„伴挬 +#define UART_BAUD_TXD_Msk (0x01 << UART_BAUD_TXD_Pos) +#define UART_BAUD_RXD_Pos 15 //é—岸é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œç§´é—è·¨å–é‹å©šå¹æ¤‹åº¢çº¯é—è·¨å–甯寸拋瑙勫î¶é–¸æ¬ç‰ é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹ç»‹çž‚Dé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”è¤çª›é–»ã„¥å«®é¡£î‡€å¹å®„伴挬 +#define UART_BAUD_RXD_Msk (0x01 << UART_BAUD_RXD_Pos) +#define UART_BAUD_RXTOIF_Pos 16 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚�&é—è·¨å–é‹å©šå¹é–¿å¬«î˜§é—è·¨å–é‹å©šå¹é‘芥晸閸欘å…éŒå›¬å¹‰ç€£î‚¢î¶éŸ«å›·æ‹· = RXIF | TOIF +#define UART_BAUD_RXTOIF_Msk (0x01 << UART_BAUD_RXTOIF_Pos) +#define UART_BAUD_TXIF_Pos 17 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”峰建閺傤厽éžå©šå¹å®„扮箶 = TXTHRF & TXIE +#define UART_BAUD_TXIF_Msk (0x01 << UART_BAUD_TXIF_Pos) +#define UART_BAUD_BRKIF_Pos 18 //LIN Break Detect é—跨喎褰ㄩ弬顓熷敾閹峰嘲绻旈柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–»æ¶˜å¢½ç»ç‹ªN Break閺冨爼é撻弬銈嗗î¶BRKIE=1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨é”å‘Šç®é–¹ç–¯æ¸¹ç¼ï¿½ +#define UART_BAUD_BRKIF_Msk (0x01 << UART_BAUD_BRKIF_Pos) +#define UART_BAUD_RXTHRF_Pos 19 //RX FIFO Threshold Flagé—è·¨å–é‹å©šå¹ç»‹çž‚ FIFOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿祹é‰å Ÿå„³é©å²„柨é”å°å“é”风暰é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£ŽÃºXLVL >= RXTHRé—è·¨å–é‹å©šå¹é–¿å¬«î˜§ç»¾î…§å‰Ÿé撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½1 +#define UART_BAUD_RXTHRF_Msk (0x01 << UART_BAUD_RXTHRF_Pos) +#define UART_BAUD_TXTHRF_Pos 20 //TX FIFO Threshold Flagé—è·¨å–é‹å©šå¹ç»‹ç¤¨ FIFOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閸婄喎é£é¹ƒæŸ¨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹ç»‹ç¤¨LVL <= TXTHRé—è·¨å–é‹å©šå¹é–¿å¬«î˜§ç»¾î…§å‰Ÿé撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½1 +#define UART_BAUD_TXTHRF_Msk (0x01 << UART_BAUD_TXTHRF_Pos) +#define UART_BAUD_TOIF_Pos 21 //TimeOut é—跨喎褰ㄩ弬顓熷敾閹峰嘲绻旈柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ TOTIME/BAUDRAUD é—è·¨å–é‹å©šå¹é–¿å¬¬æ¢¾é—跨喎褰ㄩ弬銈嗗î¶é—跨喓笑绾æ¿î˜°ç€šå½’柨é”兼應绾æ¿î˜°ç€šå½’柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–ºå†¨çˆ¼é撻弬銈嗗î¶TOIE=1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨é”å‘Šç®é–¹ç–¯æ¸¹ç¼ï¿½ +#define UART_BAUD_TOIF_Msk (0x01 << UART_BAUD_TOIF_Pos) +#define UART_BAUD_RXIF_Pos 22 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”峰建閺傤厽éžå©šå¹å®„扮箶 = RXTHRF & RXIE +#define UART_BAUD_RXIF_Msk (0x01 << UART_BAUD_RXIF_Pos) +#define UART_BAUD_ABREN_Pos 23 //Auto Baudrate Enableé—è·¨å–é‹å©šå¹å®„æ¿æ™¸1é—è·¨å–é‹å©šå¹é‘芥晸閻ㄥ棜顔愰å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–ºå¶â‚¬å†²æ«™é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归悵濠囨晸閺傘倖瀚规潻婊堟晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻敓锟� +#define UART_BAUD_ABREN_Msk (0x01 << UART_BAUD_ABREN_Pos) +#define UART_BAUD_ABRBIT_Pos 24 //Auto Baudrate Bité—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”诲Î绾攱瀚归柨é”奉潟濞夈垽é撻弬銈嗗î¶é—跨喓绮æ惃é•î…œâ‚¬å¬®å¹é‘芥晸é‰ç‚²ã˜ç»±î‡€å¹é‘芥晸閺傘倖瀚归柨é•å‚›å«¹0 1娴ｅ秹é撻弬銈嗗î¶é—岸é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规慨瀣╃秴 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±é‹ç‚ºâ€¦éŽºæ’³î¶é—è·¨å–é‹å©šå¹å®„æ¿â’–é—è·¨å–褰æ´ãˆ î¶é—è·¨å–é‹å©šå¹é–¿å¬ªîŒé–ºå Ÿæ£ƒé撻弬銈嗗î¶é—跨噦鎷�0xFF +// 1 2娴ｅ秹é撻弬銈嗗î¶é—岸é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规慨瀣╃秴é—è·¨å–é‹å©šå¹é”Ÿï¿½1娴ｅ秹é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œç§´é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±é‹ç‚ºâ€¦éŽºæ’³î¶é—è·¨å–é‹å©šå¹å®„æ¿â’–é—è·¨å–褰æ´ãˆ î¶é—è·¨å–é‹å©šå¹é–¿å¬ªîŒé–ºå Ÿæ£ƒé撻弬銈嗗î¶é—跨噦鎷�0xFE +// 1 4娴ｅ秹é撻弬銈嗗î¶é—岸é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规慨瀣╃秴é—è·¨å–é‹å©šå¹é”Ÿï¿½3娴ｅ秹é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œç§´é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±é‹ç‚ºâ€¦éŽºæ’³î¶é—è·¨å–é‹å©šå¹å®„æ¿â’–é—è·¨å–褰æ´ãˆ î¶é—è·¨å–é‹å©šå¹é–¿å¬ªîŒé–ºå Ÿæ£ƒé撻弬銈嗗î¶é—跨噦鎷�0xF8 +// 1 8娴ｅ秹é撻弬銈嗗î¶é—岸é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规慨瀣╃秴é—è·¨å–é‹å©šå¹é”Ÿï¿½7娴ｅ秹é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œç§´é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±é‹ç‚ºâ€¦éŽºæ’³î¶é—è·¨å–é‹å©šå¹å®„æ¿â’–é—è·¨å–褰æ´ãˆ î¶é—è·¨å–é‹å©šå¹é–¿å¬ªîŒé–ºå Ÿæ£ƒé撻弬銈嗗î¶é—跨噦鎷�0x80 +#define UART_BAUD_ABRBIT_Msk (0x03 << UART_BAUD_ABRBIT_Pos) +#define UART_BAUD_ABRERR_Pos 26 //Auto Baudrate Erroré—è·¨å–é‹å©šå¹é”Ÿï¿½0 é—跨喓娈曠拋瑙勫î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±é—庨崙é¡æ¶™æ™¸ç¼‚傚娅㈤å¹é”Ÿï¿½ 1 é—跨喓娈曠拋瑙勫î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±é—庨崙é¡æ¤¼äº¼é—è·¨å–é‹å©šå¹é”Ÿï¿½ +#define UART_BAUD_ABRERR_Msk (0x01 << UART_BAUD_ABRERR_Pos) +#define UART_BAUD_TXDOIF_Pos 27 //TX Done é—跨喎褰ㄩ弬顓熷敾閹峰嘲绻旈柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹ç»‹îš¯FOé—è·¨å–é‹å©šå¹é‘芥晸閹活厼é¤æ ­å¹é‘芥晸é—伴潧é¤æ ­å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹ç–¯æ¸¹ç¼å‘´æŸ¨é”惰寧é‰å ¢å“瀚归柨é”å‘Šç®é–¹é£Žå…˜é撶粣éㄦç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–褰弲éх串閹风兘é撻弬銈嗗î¶ç¼‚佺喖éæ’´îšœéšå­˜å«¹ +#define UART_BAUD_TXDOIF_Msk (0x01 << UART_BAUD_TXDOIF_Pos) + +#define UART_FIFO_RXLVL_Pos 0 //RX FIFO Levelé—è·¨å–é‹å©šå¹ç»‹çž‚ FIFO é—è·¨å–é‹å©šå¹é‘芥晸éžæ¶™îš…é¤æ ­å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define UART_FIFO_RXLVL_Msk (0xFF << UART_FIFO_RXLVL_Pos) +#define UART_FIFO_TXLVL_Pos 8 //TX FIFO Levelé—è·¨å–é‹å©šå¹ç»‹ç¤¨ FIFO é—è·¨å–é‹å©šå¹é‘芥晸éžæ¶™îš…é¤æ ­å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define UART_FIFO_TXLVL_Msk (0xFF << UART_FIFO_TXLVL_Pos) +#define UART_FIFO_RXTHR_Pos 16 //RX FIFO Thresholdé—è·¨å–é‹å©šå¹ç»‹çž‚é—跨喎褰ㄩ弬顓℃彧閹风兘é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閻å“ç¼å›¬å¹é‘芥晸閸欘å‰é¡”æ„°å¹é“šå‚šâ–é—è·¨å–é‹å©šå¹é–¿å¬«î˜§ RXLVL >= RXTHR é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚筊Xé—è·¨å–Žè¤°ã„§æ‹‹ç‘™å‹«î¶ +#define UART_FIFO_RXTHR_Msk (0xFF << UART_FIFO_RXTHR_Pos) +#define UART_FIFO_TXTHR_Pos 24 //TX FIFO Thresholdé—è·¨å–é‹å©šå¹ç»‹ç¤¨é—跨喎褰ㄩ弬顓℃彧閹风兘é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閻å“ç¼å›¬å¹é‘芥晸閸欘å‰é¡”æ„°å¹é“šå‚šâ–é—è·¨å–é‹å©šå¹é–¿å¬«î˜§ TXLVL <= TXTHR é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚筎Xé—è·¨å–Žè¤°ã„§æ‹‹ç‘™å‹«î¶ +//#define UART_FIFO_TXTHR_Msk (0xFF << UART_FIFO_TXTHR_Pos) é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喕濮らæ•é”Ÿï¿½ integer operation result is out of range +#define UART_FIFO_TXTHR_Msk ((uint32_t)0xFF << UART_FIFO_TXTHR_Pos) + +#define UART_LINCR_BRKDETIE_Pos 0 //é—è·¨å–é‹å©šå¹æ¤‹åº¡ç¦ƒç¼æ’å„N Breaké—跨喎褰ㄧ拋瑙勫î¶å¨´ï½…潡éæ’»å¼¬éŠˆå——î¶ +#define UART_LINCR_BRKDETIE_Msk (0xFF << UART_LINCR_BRKDETIE_Pos) +#define UART_LINCR_BRKDETIF_Pos 1 //é—è·¨å–é‹å©šå¹æ¤‹åº¡ç¦ƒç¼æ’å„N Breaké—跨喎褰ㄧ拋瑙勫î¶é–»æ¨¿åŸ–鈧拷 +#define UART_LINCR_BRKDETIF_Msk (0xFF << UART_LINCR_BRKDETIF_Pos) +#define UART_LINCR_GENBRKIE_Pos 2 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚ç­IN Breaké—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归崡鎼佹晸缂佺åŸå¨…㈤å¹é‘芥晸閿燂拷 +#define UART_LINCR_GENBRKIE_Msk (0xFF << UART_LINCR_GENBRKIE_Pos) +#define UART_LINCR_GENBRKIF_Pos 3 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚ç­IN Breaké—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归崡鎼佹晸闂冭泛é©ï¿ æ•“锟� +#define UART_LINCR_GENBRKIF_Msk (0xFF << UART_LINCR_GENBRKIF_Pos) +#define UART_LINCR_GENBRK_Pos 4 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚ç­IN Breaké—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é¤îˆœç®¼é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é•å‚›å«¹ +#define UART_LINCR_GENBRK_Msk (0xFF << UART_LINCR_GENBRK_Pos) + +#define UART_CTSCR_EN_Pos 0 //CTSé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担é§æ¥æ™¸é–ºå‚˜å€–瀚� +#define UART_CTSCR_EN_Msk (0x01 << UART_CTSCR_EN_Pos) +#define UART_CTSCR_POL_Pos 2 //CTSé—跨喕é“奸崣椋庛€嬮å¹é‘芥晸閻ㄥ棴ç¼å›¬å¹é”Ÿï¿½0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归弫é«ãƒ¦æ™¸é–ºå‚˜å€–瀚笴TSé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规稉娲î…晸é—æ¿çšéžå©šå¹æ¤‹åº›ä»›é—è·¨å–é‹å©šå¹é‘芥晸閻ㄥ棗é¤æ ­å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define UART_CTSCR_POL_Msk (0x01 << UART_CTSCR_POL_Pos) +#define UART_CTSCR_STAT_Pos 7 //CTSé—跨喕é“奸崣椋庢畱绾æ¿î˜°ç€šå½’崜宥囧Ц閹拷 +#define UART_CTSCR_STAT_Msk (0x01 << UART_CTSCR_STAT_Pos) + +#define UART_RTSCR_EN_Pos 1 //RTSé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担é§æ¥æ™¸é–ºå‚˜å€–瀚� +#define UART_RTSCR_EN_Msk (0x01 << UART_RTSCR_EN_Pos) +#define UART_RTSCR_POL_Pos 3 //RTSé—跨喕é“奸崣椋庛€嬮å¹é‘芥晸閺傘倖瀚� 0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归弫é«ãƒ¦æ™¸é–ºå‚˜å€–瀚筊TSé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规稉娲î…晸é—æ¿çšéžå©šå¹æ¤‹åº›ä»›é—è·¨å–é‹å©šå¹é‘芥晸閻ㄥ棙é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define UART_RTSCR_POL_Msk (0x01 << UART_RTSCR_POL_Pos) +#define UART_RTSCR_THR_Pos 4 //RTSé—è·¨å–é‹å©šå¹é‘芥晸閹æ­äºžå¨ˆæˆžæ½éî„€î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归å´é”Ÿï¿½ 0 1é—è·¨å–•é¡¢æ»ˆå¼¬éŠˆå——î¶ 1 2é—è·¨å–•é¡¢æ»ˆå¼¬éŠˆå——î¶ 2 4é—è·¨å–•é¡¢æ»ˆå¼¬éŠˆå——î¶ 3 6é—è·¨å–•é¡¢æ»ˆå¼¬éŠˆå——î¶ +#define UART_RTSCR_THR_Msk (0x07 << UART_RTSCR_THR_Pos) +#define UART_RTSCR_STAT_Pos 8 //RTSé—跨喕é“奸崣椋庢畱绾æ¿î˜°ç€šå½’崜宥囧Ц閹拷 +#define UART_RTSCR_STAT_Msk (0x01 << UART_RTSCR_STAT_Pos) + +typedef struct +{ + __IO uint32_t CTRL; + + __IO uint32_t DATA; + + __IO uint32_t STAT; + + __IO uint32_t IE; + + __IO uint32_t IF; +} SPI_TypeDef; + +#define SPI_CTRL_CLKDIV_Pos 0 //Clock Divider, SPIé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归弮é«æ›Ÿæ™¸é–ºå‚˜å€–瀚� = SYS_Freq/pow(2, CLKDIV+2) +#define SPI_CTRL_CLKDIV_Msk (0x07 << SPI_CTRL_CLKDIV_Pos) +#define SPI_CTRL_EN_Pos 3 +#define SPI_CTRL_EN_Msk (0x01 << SPI_CTRL_EN_Pos) +#define SPI_CTRL_SIZE_Pos 4 //Data Size Select, é–¸æ¬ç‰•éˆ§î„Šæ‹·3--15é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚圭粈锟�4--16娴ï½æ‹· +#define SPI_CTRL_SIZE_Msk (0x0F << SPI_CTRL_SIZE_Pos) +#define SPI_CTRL_CPHA_Pos 8 //0 é—è·¨å–é‹å©šå¹ç»‹ç¢ˆLKé—è·¨å–鑼庣喊澶嬪î¶å¨‘æ’¯å“é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻幋é¡å›¶åš‹é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� 1 é—è·¨å–é‹å©šå¹ç»‹ç¢ˆLKé—è·¨å–鑼庣粭顒冾啇閹风兘é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿焻é å›‡å‹«î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define SPI_CTRL_CPHA_Msk (0x01 << SPI_CTRL_CPHA_Pos) +#define SPI_CTRL_CPOL_Pos 9 //0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归悩鑸碘å“渚€é撻弬銈嗗î¶SCLK娑撴椽é撻柊é¢æ®¿æšœé–¹å³°å˜²é–½ï¿½ 1 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归悩鑸碘å“渚€é撻弬銈嗗î¶SCLK娑撴椽é撶粩顓狀暜閹峰嘲閽� +#define SPI_CTRL_CPOL_Msk (0x01 << SPI_CTRL_CPOL_Pos) +#define SPI_CTRL_FFS_Pos 10 //Frame Format Select, 0 SPI 1 TI SSI 2 SPI 3 SPI +#define SPI_CTRL_FFS_Msk (0x03 << SPI_CTRL_FFS_Pos) +#define SPI_CTRL_MSTR_Pos 12 //Master, 1 é—è·¨å–é‹å©šå¹é–¿å¬†ä½¸î‡£é”Ÿï¿½ 0 é—è·¨å–é‹å©šå¹é–¿å¬†ä½¸î‡£é”Ÿï¿½ +#define SPI_CTRL_MSTR_Msk (0x01 << SPI_CTRL_MSTR_Pos) +#define SPI_CTRL_FAST_Pos 13 //1 SPIé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归弮é«æ›Ÿæ™¸é–ºå‚˜å€–瀚� = SYS_Freq/2 0 SPIé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归弮é«æ›Ÿæ™¸é–ºå‚˜å€–瀚归柨é”å‘Šç®é–¹é£ŽÃ¹PI->CTRL.CLKDIVé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SPI_CTRL_FAST_Msk (0x01 << SPI_CTRL_FAST_Pos) +#define SPI_CTRL_FILTE_Pos 16 //1 é—è·¨å–é‹å©šå¹ç»‹ç¢¢Ié—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”诲壖閸欓攱é‹å©šå¹é‘芥晸閺傘倖瀚归崢濠氭晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ 0 é—è·¨å–é‹å©šå¹ç»‹ç¢¢Ié—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”诲壖閸欑柉顕滈å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å³°å˜²éªžæ’»æŸ¨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ +#define SPI_CTRL_FILTE_Msk (0x01 << SPI_CTRL_FILTE_Pos) +#define SPI_CTRL_SSN_H_Pos 17 //0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喓ç»ç ˆN婵é撻弬銈嗗î¶å¨‘æ“„æ‹·0 1 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喓é“崠鈩冨î¶é–¸Ñ€å“é—跨喕顢滈é¡æ¨ºî¶é—跨喓绮ㄧ亸é燬Né—è·¨å–é‹å©šå¹é‘芥晸ç¼æ—‘厼æ´æ»ˆå¹é‘芥晸ç¼æ’îš…LKé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SPI_CTRL_SSN_H_Msk (0x01 << SPI_CTRL_SSN_H_Pos) +#define SPI_CTRL_TFCLR_Pos 24 //TX FIFO Clear +#define SPI_CTRL_TFCLR_Msk (0x01 << SPI_CTRL_TFCLR_Pos) +#define SPI_CTRL_RFCLR_Pos 25 //RX FIFO Clear +#define SPI_CTRL_RFCLR_Msk (0x01 << SPI_CTRL_RFCLR_Pos) + +#define SPI_STAT_WTC_Pos 0 //Word Transmit Completeé—è·¨å–é‹å©šå¹é–¿å¬¬æ§¨é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻幓顓濈串閹风兘é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻幒銉嚋閹风兘é撻弬銈嗗î¶é—跨噦鎷�1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”峰建閿燂拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SPI_STAT_WTC_Msk (0x01 << SPI_STAT_WTC_Pos) +#define SPI_STAT_TFE_Pos 1 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚笷IFO Empty +#define SPI_STAT_TFE_Msk (0x01 << SPI_STAT_TFE_Pos) +#define SPI_STAT_TFNF_Pos 2 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚笷IFO Not Full +#define SPI_STAT_TFNF_Msk (0x01 << SPI_STAT_TFNF_Pos) +#define SPI_STAT_RFNE_Pos 3 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚笷IFO Not Empty +#define SPI_STAT_RFNE_Msk (0x01 << SPI_STAT_RFNE_Pos) +#define SPI_STAT_RFF_Pos 4 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚笷IFO Full +#define SPI_STAT_RFF_Msk (0x01 << SPI_STAT_RFF_Pos) +#define SPI_STAT_RFOVF_Pos 5 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚笷IFO Overflow +#define SPI_STAT_RFOVF_Msk (0x01 << SPI_STAT_RFOVF_Pos) +#define SPI_STAT_TFLVL_Pos 6 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚笷IFOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿祹闂堚晜瀚归柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ 0 TFNF=0閺冨爼é撻弬銈嗗î¶ç¼â‚¬ç»¡å¶ªFOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚�8é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿祹閿濆繑瀚筎FNF=1閺冨爼é撻弬銈嗗î¶ç¼â‚¬ç»¡å¶ªFOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚�0é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· 1--7 FIFOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚�1--7é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define SPI_STAT_TFLVL_Msk (0x07 << SPI_STAT_TFLVL_Pos) +#define SPI_STAT_RFLVL_Pos 9 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚笷IFOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿祹闂堚晜瀚归柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ 0 RFF=1閺冨爼é撻弬銈嗗î¶ç¼â‚¬ç»¡å¶ªFOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚�8é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿祹閿濆繑瀚� RFF=0閺冨爼é撻弬銈嗗î¶ç¼â‚¬ç»¡å¶ªFOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚�0é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· 1--7 FIFOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚�1--7é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define SPI_STAT_RFLVL_Msk (0x07 << SPI_STAT_RFLVL_Pos) +#define SPI_STAT_BUSY_Pos 15 +#define SPI_STAT_BUSY_Msk (0x01 << SPI_STAT_BUSY_Pos) + +#define SPI_IE_RFOVF_Pos 0 +#define SPI_IE_RFOVF_Msk (0x01 << SPI_IE_RFOVF_Pos) +#define SPI_IE_RFF_Pos 1 +#define SPI_IE_RFF_Msk (0x01 << SPI_IE_RFF_Pos) +#define SPI_IE_RFHF_Pos 2 +#define SPI_IE_RFHF_Msk (0x01 << SPI_IE_RFHF_Pos) +#define SPI_IE_TFE_Pos 3 +#define SPI_IE_TFE_Msk (0x01 << SPI_IE_TFE_Pos) +#define SPI_IE_TFHF_Pos 4 +#define SPI_IE_TFHF_Msk (0x01 << SPI_IE_TFHF_Pos) +#define SPI_IE_WTC_Pos 8 //Word Transmit Complete +#define SPI_IE_WTC_Msk (0x01 << SPI_IE_WTC_Pos) +#define SPI_IE_FTC_Pos 9 //Frame Transmit Complete +#define SPI_IE_FTC_Msk (0x01 << SPI_IE_FTC_Pos) + +#define SPI_IF_RFOVF_Pos 0 //閸愶拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SPI_IF_RFOVF_Msk (0x01 << SPI_IF_RFOVF_Pos) +#define SPI_IF_RFF_Pos 1 +#define SPI_IF_RFF_Msk (0x01 << SPI_IF_RFF_Pos) +#define SPI_IF_RFHF_Pos 2 +#define SPI_IF_RFHF_Msk (0x01 << SPI_IF_RFHF_Pos) +#define SPI_IF_TFE_Pos 3 +#define SPI_IF_TFE_Msk (0x01 << SPI_IF_TFE_Pos) +#define SPI_IF_TFHF_Pos 4 +#define SPI_IF_TFHF_Msk (0x01 << SPI_IF_TFHF_Pos) +#define SPI_IF_WTC_Pos 8 //Word Transmit Completeé—è·¨å–é‹å©šå¹é–¿å¬¬æ§¨é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻幓顓濈串閹风兘é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻幒銉嚋閹风兘é撻弬銈嗗î¶é—跨噦鎷�1 +#define SPI_IF_WTC_Msk (0x01 << SPI_IF_WTC_Pos) +#define SPI_IF_FTC_Pos 9 //Frame Transmit Completeé—è·¨å–é‹å©šå¹ç»‹ç¯¢Cé—è·¨å–é‹å©šå¹é“šå‚œç§´é–ºå†¨çˆ¼é撻弬銈嗗î¶TX FIFOé—跨喕顫楃粚é“规畱閿濆繑瀚归柨é”å‘Šç®é–¹é£ŽÃ©TCé—è·¨å–é‹å©šå¹é“šå‚œç§´ +#define SPI_IF_FTC_Msk (0x01 << SPI_IF_FTC_Pos) + +typedef struct +{ + __IO uint32_t CLKDIV; //[15:0] é—跨喕顕犵亸é¡æ¶™æ™¸é–¼å“„倽顕滈å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é¡£å •æŸ¨é”虹哺閸掑棛顣å¹ç»‹ç¢ˆL妫版垿é撶紒é殿暜閹凤拷5é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£ŽÃ¡LKDIV = SYS_Freq/5/SCL_Freq - 1 + + __IO uint32_t CTRL; + + __IO uint32_t MSTDAT; + + __IO uint32_t MSTCMD; + + __IO uint32_t SLVCR; + + __IO uint32_t SLVIF; + + __IO uint32_t SLVTX; + + __IO uint32_t SLVRX; +} I2C_TypeDef; + +#define I2C_CTRL_MSTIE_Pos 6 +#define I2C_CTRL_MSTIE_Msk (0x01 << I2C_CTRL_MSTIE_Pos) +#define I2C_CTRL_EN_Pos 7 +#define I2C_CTRL_EN_Msk (0x01 << I2C_CTRL_EN_Pos) + +#define I2C_MSTCMD_IF_Pos 0 //1 é—跨喎褰ㄧ粵澶庢彧閹风兘é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归崡绋跨瑖é—跨喎褰ㄩ敓锟�1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘界氨é—跨喕濞囬å¹éŠ‰îŸ‘嚋閹风兘é撻弬銈嗗î¶é—跨喕濞囨导娆愬î¶é—跨噦鎷�1é—è·¨å–é‹å©šå¹é“šå‚œî±é—è·¨å–é‹å©šå¹é‘芥晸éžæ¶™îš‰æ¿¡î…Ÿæ½éî„€î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é•å‚›å«¹ 2é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”侯仾閸戙倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±å¨¼å ¥æŸ¨é”å‘Šç®é–¹å³°å˜²éŠ‡ï¿½ +#define I2C_MSTCMD_IF_Msk (0x01 << I2C_MSTCMD_IF_Pos) +#define I2C_MSTCMD_TIP_Pos 1 //Transmission In Process +#define I2C_MSTCMD_TIP_Msk (0x01 << I2C_MSTCMD_TIP_Pos) +#define I2C_MSTCMD_ACK_Pos 3 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚瑰Ο鈥崇础é—跨喖鎽îˆæ•è¹‡æ–¿î¶0 é—è·¨å–é‹å©šå¹é‘芥晸é—扮數é¡î„„崙銈嗗î¶é—è·¨å–é‹å©šå¹ç»‹çƒ K 1 é—è·¨å–é‹å©šå¹é‘芥晸é—扮數é¡î„„崙銈嗗î¶é—è·¨å–é‹å©šå¹ç»‹ç“µCK +#define I2C_MSTCMD_ACK_Msk (0x01 << I2C_MSTCMD_ACK_Pos) +#define I2C_MSTCMD_WR_Pos 4 // é—è·¨å–é‹å©šå¹ç»‹ç£ave閸愭瑩é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é–¿å¬«î˜§é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹ç–¯æ¸¹ç»”存担宥呭晸1é—è·¨å–é‹å©šå¹é‘芥晸閻ㄥ棜顔愰å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define I2C_MSTCMD_WR_Msk (0x01 << I2C_MSTCMD_WR_Pos) +#define I2C_MSTCMD_RD_Pos 5 //閸愭瑩é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹ç»‹ç£aveé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±å¦žå‚žæŸ¨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œî±å¨´ï½…秴éŸï¿½1é—è·¨å–é‹å©šå¹é‘芥晸閻ㄥ棜顔愰å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£ŽÄ«2C濡ç¹é撻弬銈嗗î¶å©¢è·ºå´¬éªžæ’»æŸ¨é”å‘Šç®é–¹é£Žå…˜é撶粩顓犳畱閸戙倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±å¨¼å ¥å¼®é“佲€栭柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶1 +#define I2C_MSTCMD_RD_Msk (0x01 << I2C_MSTCMD_RD_Pos) +#define I2C_MSTCMD_BUSY_Pos 6 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–»æ¶˜å¢½ç»ç ŠART娑斿é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œî±å¨´ï½…秹é撻弬銈嗗î¶1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½î—“宓曠徊濂P娑斿é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œî±å¨´ï½…秹é撻弬銈嗗î¶0 +#define I2C_MSTCMD_BUSY_Msk (0x01 << I2C_MSTCMD_BUSY_Pos) +#define I2C_MSTCMD_STO_Pos 6 //閸愭瑩é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚ç­TOPé—è·¨å–é‹å©šå¹é‘芥晸閻ㄥ棜顔愰å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define I2C_MSTCMD_STO_Msk (0x01 << I2C_MSTCMD_STO_Pos) +#define I2C_MSTCMD_RXACK_Pos 7 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撶粔éヮ暜閹风兘é撻弬銈嗗î¶Slaveé—è·¨å–é‹å©šå¹ç»‹çƒ K娴ｅ秹é撻弬銈嗗î¶0 é—跨喓笑绾æ¿î˜°ç€šç¬°CK 1 é—跨喓笑绾æ¿î˜°ç€šç­ƒACK +#define I2C_MSTCMD_RXACK_Msk (0x01 << I2C_MSTCMD_RXACK_Pos) +#define I2C_MSTCMD_STA_Pos 7 //閸愭瑩é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚ç­TARTé—è·¨å–é‹å©šå¹é‘芥晸閻ㄥ棜顔愰å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define I2C_MSTCMD_STA_Msk (0x01 << I2C_MSTCMD_STA_Pos) + +#define I2C_SLVCR_IM_RXEND_Pos 0 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–¸æ¥ç“•ç»¶ä¼´æŸ¨é”活敎閿燂拷 +#define I2C_SLVCR_IM_RXEND_Msk (0x01 << I2C_SLVCR_IM_RXEND_Pos) +#define I2C_SLVCR_IM_TXEND_Pos 1 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–¸æ¥ç“•ç»¶ä¼´æŸ¨é”活敎閿燂拷 +#define I2C_SLVCR_IM_TXEND_Msk (0x01 << I2C_SLVCR_IM_TXEND_Pos) +#define I2C_SLVCR_IM_STADET_Pos 2 //é—è·¨å–é‹å©šå¹æ¤‹åº¡ç¦ƒé–ºå‚˜å€–瀚归柨é”虹哺绾攱瀚归崡å§å²€é’’é—跨喕顢滈敓锟� +#define I2C_SLVCR_IM_STADET_Msk (0x01 << I2C_SLVCR_IM_STADET_Pos) +#define I2C_SLVCR_IM_STODET_Pos 3 //é—è·¨å–é‹å©šå¹æ¤‹åº¡ç¦ƒé—扮绾ч惂é›å©‚î¶é–¸æ¥ç“•ç»¶ä¼´æŸ¨é”活敎閿燂拷 +#define I2C_SLVCR_IM_STODET_Msk (0x01 << I2C_SLVCR_IM_STODET_Pos) +#define I2C_SLVCR_IM_RDREQ_Pos 4 //é—è·¨å–é‹å©šå¹é‘芥晸ç¼å¤Šæ‘œé¡£î‡€å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喎褰ㄩ弬顓熸ç®é–¹çƒ½æ”±é¡’� +#define I2C_SLVCR_IM_RDREQ_Msk (0x01 << I2C_SLVCR_IM_RDREQ_Pos) +#define I2C_SLVCR_IM_WRREQ_Pos 5 //é—è·¨å–é‹å©šå¹é‘芥晸ç¼å¤Šæ‘œé¡£î‡€å¹å®„æ¿æ™¸é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”峰建閺傤厽é‹å©šå¹é–¿å¬µå‰¾ +#define I2C_SLVCR_IM_WRREQ_Msk (0x01 << I2C_SLVCR_IM_WRREQ_Pos) +#define I2C_SLVCR_ADDR7b_Pos 16 //1 7娴ｅ秹é撻弬銈嗗î¶é–¸Ñ€å“濡€崇础 0 10娴ｅ秹é撻弬銈嗗î¶é–¸Ñ€å“濡€崇础 +#define I2C_SLVCR_ADDR7b_Msk (0x01 << I2C_SLVCR_ADDR7b_Pos) +#define I2C_SLVCR_ACK_Pos 17 //1 鎼存棃é撻弬銈嗗î¶ACK 0 鎼存棃é撻弬銈嗗î¶NACK +#define I2C_SLVCR_ACK_Msk (0x01 << I2C_SLVCR_ACK_Pos) +#define I2C_SLVCR_SLAVE_Pos 18 //1 é—è·¨å–甯存导娆愬î¶æ¿¡îˆ—€崇础 0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚瑰Ο鈥崇础 +#define I2C_SLVCR_SLAVE_Msk (0x01 << I2C_SLVCR_SLAVE_Pos) +#define I2C_SLVCR_DEBOUNCE_Pos 19 //閸樺é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚šâ–é—è·¨å–é‹å©šå¹é”Ÿï¿½ +#define I2C_SLVCR_DEBOUNCE_Msk (0x01 << I2C_SLVCR_DEBOUNCE_Pos) +#define I2C_SLVCR_ADDR_Pos 20 //é—è·¨å–甯存导娆愬î¶é—è·¨å–é‹å©šå¹å®„版絻 +#define I2C_SLVCR_ADDR_Msk (0x3FF << I2C_SLVCR_ADDR_Pos) + +#define I2C_SLVIF_RXEND_Pos 0 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–¸æ¥ƒÇ¹é¡ŽæŽ—柨é”活敎閹惧æ‡ç€šå½’柨é”峰建閿燂拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define I2C_SLVIF_RXEND_Msk (0x01 << I2C_SLVIF_RXEND_Pos) +#define I2C_SLVIF_TXEND_Pos 1 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–¸æ¥ƒÇ¹é¡ŽæŽ—柨é”活敎閹惧æ‡ç€šå½’柨é”峰建閿燂拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define I2C_SLVIF_TXEND_Msk (0x01 << I2C_SLVIF_TXEND_Pos) +#define I2C_SLVIF_STADET_Pos 2 //é—è·¨å–é‹å©šå¹æ¤‹åº¡ç¦ƒé–ºå‚˜å€–瀚归柨é”虹哺绾攱瀚归崡绋款€掗柨é”活敎閹惧æ‡ç€šå½’柨é”峰建閿燂拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define I2C_SLVIF_STADET_Msk (0x01 << I2C_SLVIF_STADET_Pos) +#define I2C_SLVIF_STODET_Pos 3 //é—è·¨å–é‹å©šå¹æ¤‹åº¡ç¦ƒé—扮绾ч惂é›å©‚î¶é–¸æ¥ƒÇ¹é¡ŽæŽ—柨é”活敎閹惧æ‡ç€šå½’柨é”峰建閿燂拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define I2C_SLVIF_STODET_Msk (0x01 << I2C_SLVIF_STODET_Pos) +#define I2C_SLVIF_RDREQ_Pos 4 //é—è·¨å–é‹å©šå¹é‘芥晸ç¼å¤Šæ‘œé¡£î‡€å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喎褰ㄩ弬顓熷敾閹峰嘲绻� +#define I2C_SLVIF_RDREQ_Msk (0x01 << I2C_SLVIF_RDREQ_Pos) +#define I2C_SLVIF_WRREQ_Pos 5 //é—è·¨å–é‹å©šå¹é‘芥晸ç¼å¤Šæ‘œé¡£î‡€å¹å®„æ¿æ™¸é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”峰建閺傤厽éžå©šå¹å®„扮箶 +#define I2C_SLVIF_WRREQ_Msk (0x01 << I2C_SLVIF_WRREQ_Pos) +#define I2C_SLVIF_ACTIVE_Pos 6 //slave é—è·¨å–é‹å©šå¹é–¿å¬«æ« +#define I2C_SLVIF_ACTIVE_Msk (0x01 << I2C_SLVIF_ACTIVE_Pos) + +typedef struct +{ + __IO uint32_t CTRL; + + __IO uint32_t START; + + __IO uint32_t IE; + + __IO uint32_t IF; + + struct + { + __IO uint32_t STAT; + + __IO uint32_t DATA; + + uint32_t RESERVED[2]; + } CH[8]; + + __IO uint32_t CTRL1; + + __IO uint32_t CTRL2; + + uint32_t RESERVED[2]; + + __IO uint32_t CALIBSET; + + __IO uint32_t CALIBEN; +} ADC_TypeDef; + +#define ADC_CTRL_CH0_Pos 0 //é—岸é撻弬銈嗗î¶é—éæ’»å¼¬éŠˆå——î¶ +#define ADC_CTRL_CH0_Msk (0x01 << ADC_CTRL_CH0_Pos) +#define ADC_CTRL_CH1_Pos 1 +#define ADC_CTRL_CH1_Msk (0x01 << ADC_CTRL_CH1_Pos) +#define ADC_CTRL_CH2_Pos 2 +#define ADC_CTRL_CH2_Msk (0x01 << ADC_CTRL_CH2_Pos) +#define ADC_CTRL_CH3_Pos 3 +#define ADC_CTRL_CH3_Msk (0x01 << ADC_CTRL_CH3_Pos) +#define ADC_CTRL_CH4_Pos 4 +#define ADC_CTRL_CH4_Msk (0x01 << ADC_CTRL_CH4_Pos) +#define ADC_CTRL_CH5_Pos 5 +#define ADC_CTRL_CH5_Msk (0x01 << ADC_CTRL_CH5_Pos) +#define ADC_CTRL_CH6_Pos 6 +#define ADC_CTRL_CH6_Msk (0x01 << ADC_CTRL_CH6_Pos) +#define ADC_CTRL_CH7_Pos 7 +#define ADC_CTRL_CH7_Msk (0x01 << ADC_CTRL_CH7_Pos) +#define ADC_CTRL_AVG_Pos 8 //0 1é—跨喕濞囩拠褎瀚归柨é”å‘Šç®é–¹å‡¤æ‹· 1 2é—跨喕濞囩拠褎瀚归柨é”å‘Šç®é–¹å³°å˜²è¤°å›¬ç®éŽ¶èŠ¥æ™¸é–ºå‚˜å€–瀚归å´é”Ÿï¿½ 3 4é—跨喕濞囩拠褎瀚归柨é”å‘Šç®é–¹å³°å˜²è¤°å›¬ç®éŽ¶èŠ¥æ™¸é–ºå‚˜å€–瀚归å´é”Ÿï¿½ 7 8é—跨喕濞囩拠褎瀚归柨é”å‘Šç®é–¹å³°å˜²è¤°å›¬ç®éŽ¶èŠ¥æ™¸é–ºå‚˜å€–瀚归å´é”Ÿï¿½ 15 16é—跨喕濞囩拠褎瀚归柨é”å‘Šç®é–¹å³°å˜²è¤°å›¬ç®éŽ¶èŠ¥æ™¸é–ºå‚˜å€–瀚归å´é”Ÿï¿½ +#define ADC_CTRL_AVG_Msk (0x0F << ADC_CTRL_AVG_Pos) +#define ADC_CTRL_EN_Pos 12 +#define ADC_CTRL_EN_Msk (0x01 << ADC_CTRL_EN_Pos) +#define ADC_CTRL_CONT_Pos 13 //Continuous conversioné—è·¨å–é‹å©šå¹å®„æ¿æ¶§é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撴笟銉æ‚閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻崣é¡åº¡ç§µç€šå½’柨é•å‚›å«¹0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规潪顒勬晸閺傘倖瀚归柨é”å‘Šç®é–¹é£ŽæŸ‰å¨´å—›æŸ¨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–»æ¿†ï¹ªé撶徊濂RT娴ｅ秹é撻惃é¡æ°¼å•‡é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喖é™æ´ªæ•é‘¸ç¢‰ç´°æ¤¤å¿“孩瀚归柨é•å‚›å«¹ +#define ADC_CTRL_CONT_Msk (0x01 << ADC_CTRL_CONT_Pos) // 1 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规潪顒勬晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–褰å¹éŠâ€³æ•¾é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸闂冮浜烽å¹é‘芥晸閺傘倖瀚归柨é”活敎閹æ’瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸ç¼æ’ã‚£ART娴ï½æ‹· +#define ADC_CTRL_TRIG_Pos 14 //é‰çƒ†å‰Ÿé撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å³°å˜²ç»±ï¿ æŸ¨é”å‘Šç®é–¹å‡¤æ‹·0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”兼▉椤忓孩瀚归柨é•å‚›å«¹ 1 PWMé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define ADC_CTRL_TRIG_Msk (0x01 << ADC_CTRL_TRIG_Pos) +#define ADC_CTRL_CLKSRC_Pos 15 //0 VCO 1 HRC +#define ADC_CTRL_CLKSRC_Msk (0x01 << ADC_CTRL_CLKSRC_Pos) +#define ADC_CTRL_FIFOCLR_Pos 24 //[24] CH0_FIFO_CLR [25] CH1_FIFO_CLR ... [31] CH7_FIFO_CLR +#define ADC_CTRL_FIFOCLR_Msk (((uint32_t)0xFF) << ADC_CTRL_FIFOCLR_Pos) + +#define ADC_START_GO_Pos 0 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撴笟銉æ‚閺傘倖瀚归å¹éŠã‚†æ™¸é–¸æ¬˜å“鎷�1é—è·¨å–é‹å©šå¹ç»‹çƒ¡Cé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£ŽæŸ‰å¨´å—›æŸ¨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喕濡喊澶嬪î¶é—è·¨å–é‹å©šå¹é–¿å¬†ä½¸î‡£è¹‡æ¶™æ™¸é–ºå‚˜å€–瀚规潪顒勬晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½î—“寮烽柨é”稿å¤é å›‡å‹«î¶é—è·¨å–é‹å©šå¹é¤îˆœç®¼é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归幃éæ‘墾閹风兘é撶紓鎼厜閹风兘é撴笟銉æ‚閺傘倖瀚归崡銈夋晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–¸æ„¶æ‹·0閸嬫ç²é¡’汚DCé‰çƒ†å‰Ÿéæ’»å¼¬éŠˆå——î¶ +#define ADC_START_GO_Msk (0x01 << ADC_START_GO_Pos) +#define ADC_START_BUSY_Pos 4 +#define ADC_START_BUSY_Msk (0x01 << ADC_START_BUSY_Pos) + +#define ADC_IE_CH0EOC_Pos 0 //End Of Convertion +#define ADC_IE_CH0EOC_Msk (0x01 << ADC_IE_CH0EOC_Pos) +#define ADC_IE_CH0OVF_Pos 1 //Overflow +#define ADC_IE_CH0OVF_Msk (0x01 << ADC_IE_CH0OVF_Pos) +#define ADC_IE_CH0HFULL_Pos 2 //FIFO Half Full +#define ADC_IE_CH0HFULL_Msk (0x01 << ADC_IE_CH0HFULL_Pos) +#define ADC_IE_CH0FULL_Pos 3 //FIFO Full +#define ADC_IE_CH0FULL_Msk (0x01 << ADC_IE_CH0FULL_Pos) +#define ADC_IE_CH1EOC_Pos 4 +#define ADC_IE_CH1EOC_Msk (0x01 << ADC_IE_CH1EOC_Pos) +#define ADC_IE_CH1OVF_Pos 5 +#define ADC_IE_CH1OVF_Msk (0x01 << ADC_IE_CH1OVF_Pos) +#define ADC_IE_CH1HFULL_Pos 6 +#define ADC_IE_CH1HFULL_Msk (0x01 << ADC_IE_CH1HFULL_Pos) +#define ADC_IE_CH1FULL_Pos 7 +#define ADC_IE_CH1FULL_Msk (0x01 << ADC_IE_CH1FULL_Pos) +#define ADC_IE_CH2EOC_Pos 8 +#define ADC_IE_CH2EOC_Msk (0x01 << ADC_IE_CH2EOC_Pos) +#define ADC_IE_CH2OVF_Pos 9 +#define ADC_IE_CH2OVF_Msk (0x01 << ADC_IE_CH2OVF_Pos) +#define ADC_IE_CH2HFULL_Pos 10 +#define ADC_IE_CH2HFULL_Msk (0x01 << ADC_IE_CH2HFULL_Pos) +#define ADC_IE_CH2FULL_Pos 11 +#define ADC_IE_CH2FULL_Msk (0x01 << ADC_IE_CH2FULL_Pos) +#define ADC_IE_CH3EOC_Pos 12 +#define ADC_IE_CH3EOC_Msk (0x01 << ADC_IE_CH3EOC_Pos) +#define ADC_IE_CH3OVF_Pos 13 +#define ADC_IE_CH3OVF_Msk (0x01 << ADC_IE_CH3OVF_Pos) +#define ADC_IE_CH3HFULL_Pos 14 +#define ADC_IE_CH3HFULL_Msk (0x01 << ADC_IE_CH3HFULL_Pos) +#define ADC_IE_CH3FULL_Pos 15 +#define ADC_IE_CH3FULL_Msk (0x01 << ADC_IE_CH3FULL_Pos) +#define ADC_IE_CH4EOC_Pos 16 +#define ADC_IE_CH4EOC_Msk (0x01 << ADC_IE_CH4EOC_Pos) +#define ADC_IE_CH4OVF_Pos 17 +#define ADC_IE_CH4OVF_Msk (0x01 << ADC_IE_CH4OVF_Pos) +#define ADC_IE_CH4HFULL_Pos 18 +#define ADC_IE_CH4HFULL_Msk (0x01 << ADC_IE_CH4HFULL_Pos) +#define ADC_IE_CH4FULL_Pos 19 +#define ADC_IE_CH4FULL_Msk (0x01 << ADC_IE_CH4FULL_Pos) +#define ADC_IE_CH5EOC_Pos 20 +#define ADC_IE_CH5EOC_Msk (0x01 << ADC_IE_CH5EOC_Pos) +#define ADC_IE_CH5OVF_Pos 21 +#define ADC_IE_CH5OVF_Msk (0x01 << ADC_IE_CH5OVF_Pos) +#define ADC_IE_CH5HFULL_Pos 22 +#define ADC_IE_CH5HFULL_Msk (0x01 << ADC_IE_CH5HFULL_Pos) +#define ADC_IE_CH5FULL_Pos 23 +#define ADC_IE_CH5FULL_Msk (0x01 << ADC_IE_CH5FULL_Pos) +#define ADC_IE_CH6EOC_Pos 24 +#define ADC_IE_CH6EOC_Msk (0x01 << ADC_IE_CH6EOC_Pos) +#define ADC_IE_CH6OVF_Pos 25 +#define ADC_IE_CH6OVF_Msk (0x01 << ADC_IE_CH6OVF_Pos) +#define ADC_IE_CH6HFULL_Pos 26 +#define ADC_IE_CH6HFULL_Msk (0x01 << ADC_IE_CH6HFULL_Pos) +#define ADC_IE_CH6FULL_Pos 27 +#define ADC_IE_CH6FULL_Msk (0x01 << ADC_IE_CH6FULL_Pos) +#define ADC_IE_CH7EOC_Pos 28 +#define ADC_IE_CH7EOC_Msk (0x01 << ADC_IE_CH7EOC_Pos) +#define ADC_IE_CH7OVF_Pos 29 +#define ADC_IE_CH7OVF_Msk (0x01 << ADC_IE_CH7OVF_Pos) +#define ADC_IE_CH7HFULL_Pos 30 +#define ADC_IE_CH7HFULL_Msk (0x01 << ADC_IE_CH7HFULL_Pos) +#define ADC_IE_CH7FULL_Pos 31 +//#define ADC_IE_CH7FULL_Msk (0x01 << ADC_IE_CH7FULL_Pos) é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喕濮らæ•é”Ÿï¿½ integer operation result is out of range +#define ADC_IE_CH7FULL_Msk ((uint32_t)0x01 << ADC_IE_CH7FULL_Pos) + +#define ADC_IF_CH0EOC_Pos 0 //閸愶拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define ADC_IF_CH0EOC_Msk (0x01 << ADC_IF_CH0EOC_Pos) +#define ADC_IF_CH0OVF_Pos 1 //閸愶拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define ADC_IF_CH0OVF_Msk (0x01 << ADC_IF_CH0OVF_Pos) +#define ADC_IF_CH0HFULL_Pos 2 //閸愶拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define ADC_IF_CH0HFULL_Msk (0x01 << ADC_IF_CH0HFULL_Pos) +#define ADC_IF_CH0FULL_Pos 3 //閸愶拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define ADC_IF_CH0FULL_Msk (0x01 << ADC_IF_CH0FULL_Pos) +#define ADC_IF_CH1EOC_Pos 4 +#define ADC_IF_CH1EOC_Msk (0x01 << ADC_IF_CH1EOC_Pos) +#define ADC_IF_CH1OVF_Pos 5 +#define ADC_IF_CH1OVF_Msk (0x01 << ADC_IF_CH1OVF_Pos) +#define ADC_IF_CH1HFULL_Pos 6 +#define ADC_IF_CH1HFULL_Msk (0x01 << ADC_IF_CH1HFULL_Pos) +#define ADC_IF_CH1FULL_Pos 7 +#define ADC_IF_CH1FULL_Msk (0x01 << ADC_IF_CH1FULL_Pos) +#define ADC_IF_CH2EOC_Pos 8 +#define ADC_IF_CH2EOC_Msk (0x01 << ADC_IF_CH2EOC_Pos) +#define ADC_IF_CH2OVF_Pos 9 +#define ADC_IF_CH2OVF_Msk (0x01 << ADC_IF_CH2OVF_Pos) +#define ADC_IF_CH2HFULL_Pos 10 +#define ADC_IF_CH2HFULL_Msk (0x01 << ADC_IF_CH2HFULL_Pos) +#define ADC_IF_CH2FULL_Pos 11 +#define ADC_IF_CH2FULL_Msk (0x01 << ADC_IF_CH2FULL_Pos) +#define ADC_IF_CH3EOC_Pos 12 +#define ADC_IF_CH3EOC_Msk (0x01 << ADC_IF_CH3EOC_Pos) +#define ADC_IF_CH3OVF_Pos 13 +#define ADC_IF_CH3OVF_Msk (0x01 << ADC_IF_CH3OVF_Pos) +#define ADC_IF_CH3HFULL_Pos 14 +#define ADC_IF_CH3HFULL_Msk (0x01 << ADC_IF_CH3HFULL_Pos) +#define ADC_IF_CH3FULL_Pos 15 +#define ADC_IF_CH3FULL_Msk (0x01 << ADC_IF_CH3FULL_Pos) +#define ADC_IF_CH4EOC_Pos 16 +#define ADC_IF_CH4EOC_Msk (0x01 << ADC_IF_CH4EOC_Pos) +#define ADC_IF_CH4OVF_Pos 17 +#define ADC_IF_CH4OVF_Msk (0x01 << ADC_IF_CH4OVF_Pos) +#define ADC_IF_CH4HFULL_Pos 18 +#define ADC_IF_CH4HFULL_Msk (0x01 << ADC_IF_CH4HFULL_Pos) +#define ADC_IF_CH4FULL_Pos 19 +#define ADC_IF_CH4FULL_Msk (0x01 << ADC_IF_CH4FULL_Pos) +#define ADC_IF_CH5EOC_Pos 20 +#define ADC_IF_CH5EOC_Msk (0x01 << ADC_IF_CH5EOC_Pos) +#define ADC_IF_CH5OVF_Pos 21 +#define ADC_IF_CH5OVF_Msk (0x01 << ADC_IF_CH5OVF_Pos) +#define ADC_IF_CH5HFULL_Pos 22 +#define ADC_IF_CH5HFULL_Msk (0x01 << ADC_IF_CH5HFULL_Pos) +#define ADC_IF_CH5FULL_Pos 23 +#define ADC_IF_CH5FULL_Msk (0x01 << ADC_IF_CH5FULL_Pos) +#define ADC_IF_CH6EOC_Pos 24 +#define ADC_IF_CH6EOC_Msk (0x01 << ADC_IF_CH6EOC_Pos) +#define ADC_IF_CH6OVF_Pos 25 +#define ADC_IF_CH6OVF_Msk (0x01 << ADC_IF_CH6OVF_Pos) +#define ADC_IF_CH6HFULL_Pos 26 +#define ADC_IF_CH6HFULL_Msk (0x01 << ADC_IF_CH6HFULL_Pos) +#define ADC_IF_CH6FULL_Pos 27 +#define ADC_IF_CH6FULL_Msk (0x01 << ADC_IF_CH6FULL_Pos) +#define ADC_IF_CH7EOC_Pos 28 +#define ADC_IF_CH7EOC_Msk (0x01 << ADC_IF_CH7EOC_Pos) +#define ADC_IF_CH7OVF_Pos 29 +#define ADC_IF_CH7OVF_Msk (0x01 << ADC_IF_CH7OVF_Pos) +#define ADC_IF_CH7HFULL_Pos 30 +#define ADC_IF_CH7HFULL_Msk (0x01 << ADC_IF_CH7HFULL_Pos) +#define ADC_IF_CH7FULL_Pos 31 +#define ADC_IF_CH7FULL_Msk (0x01 << ADC_IF_CH7FULL_Pos) + +#define ADC_STAT_EOC_Pos 0 //閸愶拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define ADC_STAT_EOC_Msk (0x01 << ADC_STAT_EOC_Pos) +#define ADC_STAT_OVF_Pos 1 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿祹éŽé›å«¯éŽ»îˆå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻敓锟� +#define ADC_STAT_OVF_Msk (0x01 << ADC_STAT_OVF_Pos) +#define ADC_STAT_HFULL_Pos 2 +#define ADC_STAT_HFULL_Msk (0x01 << ADC_STAT_HFULL_Pos) +#define ADC_STAT_FULL_Pos 3 +#define ADC_STAT_FULL_Msk (0x01 << ADC_STAT_FULL_Pos) +#define ADC_STAT_EMPTY_Pos 4 +#define ADC_STAT_EMPTY_Msk (0x01 << ADC_STAT_EMPTY_Pos) + +#define ADC_CTRL1_RIN_Pos 4 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å°å“é”稿îŽé—è·¨å–é‹å©šå¹é”Ÿï¿½0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é•å‚›å«¹ 1 105K 2 90K 3 75K 4 60K 5 45K 6 30K 7 15K +#define ADC_CTRL1_RIN_Msk (0x07 << ADC_CTRL1_RIN_Pos) + +#define ADC_CTRL2_RESET_Pos 0 //é—è·¨å–é‹å©šå¹é‘芥晸éžæ¶™îšˆé¡£î‡€å¹é¤îˆœç†…é—è·¨å–é‹å©šå¹é“šå‚œç§´ +#define ADC_CTRL2_RESET_Msk (0x01 << ADC_CTRL2_RESET_Pos) +#define ADC_CTRL2_ADCEVCM_Pos 1 //ADC External VCMé—è·¨å–é‹å©šå¹ç»‹çƒ¡Cé—è·¨å–é‹å©šå¹ç»‹ç™ŽAé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”惰寧閿濆繑瀚归柨é”å“„ç±ç¼æ„­ç‰‘妲勯å¹é‘芥晸閿燂拷 +#define ADC_CTRL2_ADCEVCM_Msk (0x01 << ADC_CTRL2_ADCEVCM_Pos) +#define ADC_CTRL2_PGAIVCM_Pos 2 //PGA Internal VCMé—è·¨å–é‹å©šå¹ç»‹ç™ŽAé—è·¨å–é‹å©šå¹é‘芥晸é å›¶å„é™â€³ÎŸé”ŸçŠ³æ™¸é–ºå‚˜å€–瀚归ç®éŽ¶è§£å“澶愭晸閺傘倖瀚� +#define ADC_CTRL2_PGAIVCM_Msk (0x01 << ADC_CTRL2_PGAIVCM_Pos) +#define ADC_CTRL2_PGAGAIN_Pos 3 //0 25.1dB 1 21.6dB 2 11.1dB 3 3.5dB 4 0dB(1.8V) 5 -2.9dB 6 -5.3dB +#define ADC_CTRL2_PGAGAIN_Msk (0x07 << ADC_CTRL2_PGAGAIN_Pos) +#define ADC_CTRL2_REFPOUT_Pos 23 //1 ADC é—跨喕濡拠褎瀚� 1.2V REFPé—è·¨å–é‹å©šå¹å®„æ¿ç«¾é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½î—“宕扮缓宀ç¢Pé—è·¨å–é‹å©šå¹é‘芥晸閼存熬ç¼å›¬å¹é‘芥晸閺傘倖瀚归柨é”诲Îé å›‡å‹«î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é¤îˆ£æ´£1.2Vé—跨喕袙é—墽EFP閺冨爼é撻弬銈嗗î¶é–»îƒç·šé撶紓瀛樺敾閹凤拷 +#define ADC_CTRL2_REFPOUT_Msk (0x01 << ADC_CTRL2_REFPOUT_Pos +#define ADC_CTRL2_CLKDIV_Pos 24 //閺冨爼é撻幒銉ュ殩閹风兘顣堕柨é”å‘Šç®é–¹å³°å˜²è¤°Ñ‡æŸ¨é”å‘Šç®é–¹çƒ½æ”±å¦žå‚žæŸ¨é”å‘Šç®é–¹çƒ½æ”±ç»¨î†½ç¨‰ç»¡æ€°C閺冨爼é撻弬銈嗗î¶é–ºä¾Šæ‹· +#define ADC_CTRL2_CLKDIV_Msk (0x1F << ADC_CTRL2_CLKDIV_Pos) +#define ADC_CTRL2_PGAVCM_Pos 29 +#define ADC_CTRL2_PGAVCM_Msk (((uint32_t)0x07) << ADC_CTRL2_PGAVCM_Pos) + +#define ADC_CALIBSET_OFFSET_Pos 0 +#define ADC_CALIBSET_OFFSET_Msk (0x1FF << ADC_CALIBSET_OFFSET_Pos) +#define ADC_CALIBSET_K_Pos 16 +#define ADC_CALIBSET_K_Msk (0x1FF << ADC_CALIBSET_K_Pos) + +#define ADC_CALIBEN_OFFSET_Pos 0 +#define ADC_CALIBEN_OFFSET_Msk (0x01 << ADC_CALIBEN_OFFSET_Pos) +#define ADC_CALIBEN_K_Pos 1 +#define ADC_CALIBEN_K_Msk (0x01 << ADC_CALIBEN_K_Pos) + +typedef struct +{ + __IO uint32_t MODE; //0 é—è·¨å–é‹å©šå¹é‘解å“姘佸蹇涙晸閺傘倖瀚笰é—è·¨å–é‹å©šå¹ç»‹ï¿ æŸ¨é”å‘Šç®é–¹é£ŽæŸ‰é­é¹ƒæŸ¨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· + //1 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚瑰Ο鈥崇础é—è·¨å–é‹å©šå¹ç»‹ç†¼æŸ¨é”å‘Šç®é–¹é£ŽÄé—è·¨å–é‹å©šå¹é¤îˆœç†…é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撶徊é¢æ€°Aé—è·¨å–é‹å©šå¹ç»‹â†–GHAé—è·¨å–é‹å©šå¹é‘芥晸閻欌槄ç¼å›¬å¹ç»‹ï¼„æ„顖炴晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜éæ’¶æ§å§å²€ç†…é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–¸çŠ³å´˜éŽ»îˆå¹é‘芥晸閺傘倖瀚归柨é”烘ãŸZAé—è·¨å–é‹å©šå¹ç»‹î˜€Bé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚笰é—è·¨å–é‹å©šå¹ç»‹ï¼„æ„顖炴晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归惉銉╂晸缂佺åžéžå©šå¹é‘芥晸閿燂拷 + //2 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚瑰Ο鈥崇础é—è·¨å–é‹å©šå¹å®„版倱é—è·¨å–é‹å©šå¹é‘解å“姘佸蹇涙晸閺傘倖瀚归柨é”å‘Šç®é–¹ç–¯æ¸¹ç»”撮柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喕濡悮瀛樺î¶é—跨喓娈曠拋瑙勫î¶é–¸å¬«ç²é¡’� + //3 é—跨喓娈曠粵瑙勫î¶æ¿¡îˆ—€崇础é—è·¨å–é‹å©šå¹ç»‹ç†¼æŸ¨é”å‘Šç®é–¹é£ŽÄé—è·¨å–é‹å©šå¹é¤îˆœç†…é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喕濡拠褎瀚归柨é”å‘Šç®é–¹ç–¯æ¸¹ç»”撮柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–¸æ„©åž½é撻弬銈嗗î¶é–»â•‚挳é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿疆娴兼瑦瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻悪锛勵暜閹峰嘲绱￠柨é”å‘Šç®é–¹é£Žå…˜é撻幓顓濈串閹风兘é撻敓锟� + //4 é—跨喓娈曠粔棰佺串閹风兘é撻弬銈嗗î¶æ¿¡îˆ—€崇础é—è·¨å–é‹å©šå¹é‘芥晸閻ㄥ棛顒查å¹é–¿å¬†ä½¸î‡£è¹‡æ¶™æ™¸é—æ¿å€ç»±î‡€å¹é‘芥晸閺傘倖瀚瑰Ο鈥崇础é—è·¨å–é‹å©šå¹é‘芥晸濡æ¥æ¢»çã„©å¹é”Ÿï¿½ + + __IO uint32_t PERA; //[15:0] é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� + + __IO uint32_t HIGHA; //[15:0] é—跨喓é¡î†å–Šæ¾¶å¬ªî¶æ¥ ç‚´å¨Šé撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é–¿å¬«î˜§é—è·¨å–é‹å©šå¹é”Ÿï¿½ + + __IO uint32_t DZA; //[9:0] é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻悪锛勵劜閹烽攱妞傞柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚圭亸蹇涙晸閺傘倖瀚笻IGHA + + __IO uint32_t PERB; + + __IO uint32_t HIGHB; + + __IO uint32_t DZB; + + __IO uint32_t INIOUT; //Init Output levelé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规慨瀣晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻悪鈽呮嫹 +} PWM_TypeDef; + +#define PWM_INIOUT_PWMA_Pos 0 +#define PWM_INIOUT_PWMA_Msk (0x01 << PWM_INIOUT_PWMA_Pos) +#define PWM_INIOUT_PWMB_Pos 1 +#define PWM_INIOUT_PWMB_Msk (0x01 << PWM_INIOUT_PWMB_Pos) + +typedef struct +{ + __IO uint32_t FORCEH; + + __IO uint32_t ADTRG0A; + __IO uint32_t ADTRG0B; + + __IO uint32_t ADTRG1A; + __IO uint32_t ADTRG1B; + + __IO uint32_t ADTRG2A; + __IO uint32_t ADTRG2B; + + __IO uint32_t ADTRG3A; + __IO uint32_t ADTRG3B; + + __IO uint32_t ADTRG4A; + __IO uint32_t ADTRG4B; + + __IO uint32_t ADTRG5A; + __IO uint32_t ADTRG5B; + + uint32_t RESERVED[3]; + + __IO uint32_t HALT; //閸掑綊é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� + + __IO uint32_t CHEN; + + __IO uint32_t IE; + + __IO uint32_t IF; + + __IO uint32_t IM; //Interrupt Mask + + __IO uint32_t IRS; //Interrupt Raw Stat +} PWMG_TypeDef; + +#define PWMG_FORCEH_PWM0_Pos 0 +#define PWMG_FORCEH_PWM0_Msk (0x01 << PWMG_FORCEH_PWM0_Pos) +#define PWMG_FORCEH_PWM1_Pos 1 +#define PWMG_FORCEH_PWM1_Msk (0x01 << PWMG_FORCEH_PWM1_Pos) +#define PWMG_FORCEH_PWM2_Pos 2 +#define PWMG_FORCEH_PWM2_Msk (0x01 << PWMG_FORCEH_PWM2_Pos) +#define PWMG_FORCEH_PWM3_Pos 3 +#define PWMG_FORCEH_PWM3_Msk (0x01 << PWMG_FORCEH_PWM3_Pos) +#define PWMG_FORCEH_PWM4_Pos 4 +#define PWMG_FORCEH_PWM4_Msk (0x01 << PWMG_FORCEH_PWM4_Pos) +#define PWMG_FORCEH_PWM5_Pos 5 +#define PWMG_FORCEH_PWM5_Msk (0x01 << PWMG_FORCEH_PWM5_Pos) + +#define PWMG_ADTRG_VALUE_Pos 0 +#define PWMG_ADTRG_VALUE_Msk (0xFFFF << PWMG_ADTRG0A_VALUE_Pos) +#define PWMG_ADTRG_EVEN_Pos 16 //1 閸嬪爼é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±é…� 0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é–¿å¬«æ« +#define PWMG_ADTRG_EVEN_Msk (0x01 << PWMG_ADTRG0A_EVEN_Pos) +#define PWMG_ADTRG_EN_Pos 17 +#define PWMG_ADTRG_EN_Msk (0x01 << PWMG_ADTRG0A_EN_Pos) + +#define PWMG_HALT_EN_Pos 0 +#define PWMG_HALT_EN_Msk (0x01 << PWMG_HALT_EN_Pos) +#define PWMG_HALT_PWM0_Pos 1 +#define PWMG_HALT_PWM0_Msk (0x01 << PWMG_HALT_PWM0_Pos) +#define PWMG_HALT_PWM1_Pos 2 +#define PWMG_HALT_PWM1_Msk (0x01 << PWMG_HALT_PWM1_Pos) +#define PWMG_HALT_PWM2_Pos 3 +#define PWMG_HALT_PWM2_Msk (0x01 << PWMG_HALT_PWM2_Pos) +#define PWMG_HALT_PWM3_Pos 4 +#define PWMG_HALT_PWM3_Msk (0x01 << PWMG_HALT_PWM3_Pos) +#define PWMG_HALT_PWM4_Pos 5 +#define PWMG_HALT_PWM4_Msk (0x01 << PWMG_HALT_PWM4_Pos) +#define PWMG_HALT_PWM5_Pos 6 +#define PWMG_HALT_PWM5_Msk (0x01 << PWMG_HALT_PWM5_Pos) +#define PWMG_HALT_STOPCNT_Pos 7 //1 閸掑綊é撻弬銈嗗î¶é–ºå†¨çˆ¼é撻弬銈嗗î¶PWMé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喎顫曢æ•çžæˆ’粻濮濄垽é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ 0 閸掑綊é撻弬銈嗗î¶é–ºå†¨çˆ¼é撻弬銈嗗î¶PWMé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define PWMG_HALT_STOPCNT_Msk (0x01 << PWMG_HALT_STOPCNT_Pos) +#define PWMG_HALT_INLVL_Pos 8 //1 閸掑綊é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归崣鈺呮晸閻欌å‰é‹å©šå¹é‘芥晸閸欘å“鎷� +#define PWMG_HALT_INLVL_Msk (0x01 << PWMG_HALT_INLVL_Pos) +#define PWMG_HALT_OUTLVL_Pos 9 //1 閸掑綊é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹å®„æ¿æ¸é—跨喓瀚涢敓锟� +#define PWMG_HALT_OUTLVL_Msk (0x01 << PWMG_HALT_OUTLVL_Pos) +#define PWMG_HALT_STAT_Pos 10 //1 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归崚褰掓晸閺傘倖瀚� +#define PWMG_HALT_STAT_Msk (0x01 << PWMG_HALT_STAT_Pos) + +#define PWMG_CHEN_PWM0A_Pos 0 +#define PWMG_CHEN_PWM0A_Msk (0x01 << PWMG_CHEN_PWM0A_Pos) +#define PWMG_CHEN_PWM0B_Pos 1 +#define PWMG_CHEN_PWM0B_Msk (0x01 << PWMG_CHEN_PWM0B_Pos) +#define PWMG_CHEN_PWM1A_Pos 2 +#define PWMG_CHEN_PWM1A_Msk (0x01 << PWMG_CHEN_PWM1A_Pos) +#define PWMG_CHEN_PWM1B_Pos 3 +#define PWMG_CHEN_PWM1B_Msk (0x01 << PWMG_CHEN_PWM1B_Pos) +#define PWMG_CHEN_PWM2A_Pos 4 +#define PWMG_CHEN_PWM2A_Msk (0x01 << PWMG_CHEN_PWM2A_Pos) +#define PWMG_CHEN_PWM2B_Pos 5 +#define PWMG_CHEN_PWM2B_Msk (0x01 << PWMG_CHEN_PWM2B_Pos) +#define PWMG_CHEN_PWM3A_Pos 6 +#define PWMG_CHEN_PWM3A_Msk (0x01 << PWMG_CHEN_PWM3A_Pos) +#define PWMG_CHEN_PWM3B_Pos 7 +#define PWMG_CHEN_PWM3B_Msk (0x01 << PWMG_CHEN_PWM3B_Pos) +#define PWMG_CHEN_PWM4A_Pos 8 +#define PWMG_CHEN_PWM4A_Msk (0x01 << PWMG_CHEN_PWM4A_Pos) +#define PWMG_CHEN_PWM4B_Pos 9 +#define PWMG_CHEN_PWM4B_Msk (0x01 << PWMG_CHEN_PWM4B_Pos) +#define PWMG_CHEN_PWM5A_Pos 10 +#define PWMG_CHEN_PWM5A_Msk (0x01 << PWMG_CHEN_PWM5A_Pos) +#define PWMG_CHEN_PWM5B_Pos 11 +#define PWMG_CHEN_PWM5B_Msk (0x01 << PWMG_CHEN_PWM5B_Pos) + +#define PWMG_IE_NEWP0A_Pos 0 +#define PWMG_IE_NEWP0A_Msk (0x01 << PWMG_IE_NEWP0A_Pos) +#define PWMG_IE_NEWP0B_Pos 1 +#define PWMG_IE_NEWP0B_Msk (0x01 << PWMG_IE_NEWP0B_Pos) +#define PWMG_IE_NEWP1A_Pos 2 +#define PWMG_IE_NEWP1A_Msk (0x01 << PWMG_IE_NEWP1A_Pos) +#define PWMG_IE_NEWP1B_Pos 3 +#define PWMG_IE_NEWP1B_Msk (0x01 << PWMG_IE_NEWP1B_Pos) +#define PWMG_IE_NEWP2A_Pos 4 +#define PWMG_IE_NEWP2A_Msk (0x01 << PWMG_IE_NEWP2A_Pos) +#define PWMG_IE_NEWP2B_Pos 5 +#define PWMG_IE_NEWP2B_Msk (0x01 << PWMG_IE_NEWP2B_Pos) +#define PWMG_IE_NEWP3A_Pos 6 +#define PWMG_IE_NEWP3A_Msk (0x01 << PWMG_IE_NEWP3A_Pos) +#define PWMG_IE_NEWP3B_Pos 7 +#define PWMG_IE_NEWP3B_Msk (0x01 << PWMG_IE_NEWP3B_Pos) +#define PWMG_IE_NEWP4A_Pos 8 +#define PWMG_IE_NEWP4A_Msk (0x01 << PWMG_IE_NEWP4A_Pos) +#define PWMG_IE_NEWP4B_Pos 9 +#define PWMG_IE_NEWP4B_Msk (0x01 << PWMG_IE_NEWP4B_Pos) +#define PWMG_IE_NEWP5A_Pos 10 +#define PWMG_IE_NEWP5A_Msk (0x01 << PWMG_IE_NEWP5A_Pos) +#define PWMG_IE_NEWP5B_Pos 11 +#define PWMG_IE_NEWP5B_Msk (0x01 << PWMG_IE_NEWP5B_Pos) +#define PWMG_IE_HEND0A_Pos 12 +#define PWMG_IE_HEND0A_Msk (0x01 << PWMG_IE_HEND0A_Pos) +#define PWMG_IE_HEND0B_Pos 13 +#define PWMG_IE_HEND0B_Msk (0x01 << PWMG_IE_HEND0B_Pos) +#define PWMG_IE_HEND1A_Pos 14 +#define PWMG_IE_HEND1A_Msk (0x01 << PWMG_IE_HEND1A_Pos) +#define PWMG_IE_HEND1B_Pos 15 +#define PWMG_IE_HEND1B_Msk (0x01 << PWMG_IE_HEND1B_Pos) +#define PWMG_IE_HEND2A_Pos 16 +#define PWMG_IE_HEND2A_Msk (0x01 << PWMG_IE_HEND2A_Pos) +#define PWMG_IE_HEND2B_Pos 17 +#define PWMG_IE_HEND2B_Msk (0x01 << PWMG_IE_HEND2B_Pos) +#define PWMG_IE_HEND3A_Pos 18 +#define PWMG_IE_HEND3A_Msk (0x01 << PWMG_IE_HEND3A_Pos) +#define PWMG_IE_HEND3B_Pos 19 +#define PWMG_IE_HEND3B_Msk (0x01 << PWMG_IE_HEND3B_Pos) +#define PWMG_IE_HEND4A_Pos 20 +#define PWMG_IE_HEND4A_Msk (0x01 << PWMG_IE_HEND4A_Pos) +#define PWMG_IE_HEND4B_Pos 21 +#define PWMG_IE_HEND4B_Msk (0x01 << PWMG_IE_HEND4B_Pos) +#define PWMG_IE_HEND5A_Pos 22 +#define PWMG_IE_HEND5A_Msk (0x01 << PWMG_IE_HEND5A_Pos) +#define PWMG_IE_HEND5B_Pos 23 +#define PWMG_IE_HEND5B_Msk (0x01 << PWMG_IE_HEND5B_Pos) +#define PWMG_IE_HALT_Pos 24 +#define PWMG_IE_HALT_Msk (0x01 << PWMG_IE_HALT_Pos) + +#define PWMG_IF_NEWP0A_Pos 0 +#define PWMG_IF_NEWP0A_Msk (0x01 << PWMG_IF_NEWP0A_Pos) +#define PWMG_IF_NEWP0B_Pos 1 +#define PWMG_IF_NEWP0B_Msk (0x01 << PWMG_IF_NEWP0B_Pos) +#define PWMG_IF_NEWP1A_Pos 2 +#define PWMG_IF_NEWP1A_Msk (0x01 << PWMG_IF_NEWP1A_Pos) +#define PWMG_IF_NEWP1B_Pos 3 +#define PWMG_IF_NEWP1B_Msk (0x01 << PWMG_IF_NEWP1B_Pos) +#define PWMG_IF_NEWP2A_Pos 4 +#define PWMG_IF_NEWP2A_Msk (0x01 << PWMG_IF_NEWP2A_Pos) +#define PWMG_IF_NEWP2B_Pos 5 +#define PWMG_IF_NEWP2B_Msk (0x01 << PWMG_IF_NEWP2B_Pos) +#define PWMG_IF_NEWP3A_Pos 6 +#define PWMG_IF_NEWP3A_Msk (0x01 << PWMG_IF_NEWP3A_Pos) +#define PWMG_IF_NEWP3B_Pos 7 +#define PWMG_IF_NEWP3B_Msk (0x01 << PWMG_IF_NEWP3B_Pos) +#define PWMG_IF_NEWP4A_Pos 8 +#define PWMG_IF_NEWP4A_Msk (0x01 << PWMG_IF_NEWP4A_Pos) +#define PWMG_IF_NEWP4B_Pos 9 +#define PWMG_IF_NEWP4B_Msk (0x01 << PWMG_IF_NEWP4B_Pos) +#define PWMG_IF_NEWP5A_Pos 10 +#define PWMG_IF_NEWP5A_Msk (0x01 << PWMG_IF_NEWP5A_Pos) +#define PWMG_IF_NEWP5B_Pos 11 +#define PWMG_IF_NEWP5B_Msk (0x01 << PWMG_IF_NEWP5B_Pos) +#define PWMG_IF_HEND0A_Pos 12 +#define PWMG_IF_HEND0A_Msk (0x01 << PWMG_IF_HEND0A_Pos) +#define PWMG_IF_HEND0B_Pos 13 +#define PWMG_IF_HEND0B_Msk (0x01 << PWMG_IF_HEND0B_Pos) +#define PWMG_IF_HEND1A_Pos 14 +#define PWMG_IF_HEND1A_Msk (0x01 << PWMG_IF_HEND1A_Pos) +#define PWMG_IF_HEND1B_Pos 15 +#define PWMG_IF_HEND1B_Msk (0x01 << PWMG_IF_HEND1B_Pos) +#define PWMG_IF_HEND2A_Pos 16 +#define PWMG_IF_HEND2A_Msk (0x01 << PWMG_IF_HEND2A_Pos) +#define PWMG_IF_HEND2B_Pos 17 +#define PWMG_IF_HEND2B_Msk (0x01 << PWMG_IF_HEND2B_Pos) +#define PWMG_IF_HEND3A_Pos 18 +#define PWMG_IF_HEND3A_Msk (0x01 << PWMG_IF_HEND3A_Pos) +#define PWMG_IF_HEND3B_Pos 19 +#define PWMG_IF_HEND3B_Msk (0x01 << PWMG_IF_HEND3B_Pos) +#define PWMG_IF_HEND4A_Pos 20 +#define PWMG_IF_HEND4A_Msk (0x01 << PWMG_IF_HEND4A_Pos) +#define PWMG_IF_HEND4B_Pos 21 +#define PWMG_IF_HEND4B_Msk (0x01 << PWMG_IF_HEND4B_Pos) +#define PWMG_IF_HEND5A_Pos 22 +#define PWMG_IF_HEND5A_Msk (0x01 << PWMG_IF_HEND5A_Pos) +#define PWMG_IF_HEND5B_Pos 23 +#define PWMG_IF_HEND5B_Msk (0x01 << PWMG_IF_HEND5B_Pos) +#define PWMG_IF_HALT_Pos 24 +#define PWMG_IF_HALT_Msk (0x01 << PWMG_IF_HALT_Pos) + +#define PWMG_IM_NEWP0A_Pos 0 //Interrupt Mask +#define PWMG_IM_NEWP0A_Msk (0x01 << PWMG_IM_NEWP0A_Pos) +#define PWMG_IM_NEWP0B_Pos 1 +#define PWMG_IM_NEWP0B_Msk (0x01 << PWMG_IM_NEWP0B_Pos) +#define PWMG_IM_NEWP1A_Pos 2 +#define PWMG_IM_NEWP1A_Msk (0x01 << PWMG_IM_NEWP1A_Pos) +#define PWMG_IM_NEWP1B_Pos 3 +#define PWMG_IM_NEWP1B_Msk (0x01 << PWMG_IM_NEWP1B_Pos) +#define PWMG_IM_NEWP2A_Pos 4 +#define PWMG_IM_NEWP2A_Msk (0x01 << PWMG_IM_NEWP2A_Pos) +#define PWMG_IM_NEWP2B_Pos 5 +#define PWMG_IM_NEWP2B_Msk (0x01 << PWMG_IM_NEWP2B_Pos) +#define PWMG_IM_NEWP3A_Pos 6 +#define PWMG_IM_NEWP3A_Msk (0x01 << PWMG_IM_NEWP3A_Pos) +#define PWMG_IM_NEWP3B_Pos 7 +#define PWMG_IM_NEWP3B_Msk (0x01 << PWMG_IM_NEWP3B_Pos) +#define PWMG_IM_NEWP4A_Pos 8 +#define PWMG_IM_NEWP4A_Msk (0x01 << PWMG_IM_NEWP4A_Pos) +#define PWMG_IM_NEWP4B_Pos 9 +#define PWMG_IM_NEWP4B_Msk (0x01 << PWMG_IM_NEWP4B_Pos) +#define PWMG_IM_NEWP5A_Pos 10 +#define PWMG_IM_NEWP5A_Msk (0x01 << PWMG_IM_NEWP5A_Pos) +#define PWMG_IM_NEWP5B_Pos 11 +#define PWMG_IM_NEWP5B_Msk (0x01 << PWMG_IM_NEWP5B_Pos) +#define PWMG_IM_HEND0A_Pos 12 +#define PWMG_IM_HEND0A_Msk (0x01 << PWMG_IM_HEND0A_Pos) +#define PWMG_IM_HEND0B_Pos 13 +#define PWMG_IM_HEND0B_Msk (0x01 << PWMG_IM_HEND0B_Pos) +#define PWMG_IM_HEND1A_Pos 14 +#define PWMG_IM_HEND1A_Msk (0x01 << PWMG_IM_HEND1A_Pos) +#define PWMG_IM_HEND1B_Pos 15 +#define PWMG_IM_HEND1B_Msk (0x01 << PWMG_IM_HEND1B_Pos) +#define PWMG_IM_HEND2A_Pos 16 +#define PWMG_IM_HEND2A_Msk (0x01 << PWMG_IM_HEND2A_Pos) +#define PWMG_IM_HEND2B_Pos 17 +#define PWMG_IM_HEND2B_Msk (0x01 << PWMG_IM_HEND2B_Pos) +#define PWMG_IM_HEND3A_Pos 18 +#define PWMG_IM_HEND3A_Msk (0x01 << PWMG_IM_HEND3A_Pos) +#define PWMG_IM_HEND3B_Pos 19 +#define PWMG_IM_HEND3B_Msk (0x01 << PWMG_IM_HEND3B_Pos) +#define PWMG_IM_HEND4A_Pos 20 +#define PWMG_IM_HEND4A_Msk (0x01 << PWMG_IM_HEND4A_Pos) +#define PWMG_IM_HEND4B_Pos 21 +#define PWMG_IM_HEND4B_Msk (0x01 << PWMG_IM_HEND4B_Pos) +#define PWMG_IM_HEND5A_Pos 22 +#define PWMG_IM_HEND5A_Msk (0x01 << PWMG_IM_HEND5A_Pos) +#define PWMG_IM_HEND5B_Pos 23 +#define PWMG_IM_HEND5B_Msk (0x01 << PWMG_IM_HEND5B_Pos) +#define PWMG_IM_HALT_Pos 24 +#define PWMG_IM_HALT_Msk (0x01 << PWMG_IM_HALT_Pos) + +#define PWMG_IRS_NEWP0A_Pos 0 //Interrupt Raw State +#define PWMG_IRS_NEWP0A_Msk (0x01 << PWMG_IRS_NEWP0A_Pos) +#define PWMG_IRS_NEWP0B_Pos 1 +#define PWMG_IRS_NEWP0B_Msk (0x01 << PWMG_IRS_NEWP0B_Pos) +#define PWMG_IRS_NEWP1A_Pos 2 +#define PWMG_IRS_NEWP1A_Msk (0x01 << PWMG_IRS_NEWP1A_Pos) +#define PWMG_IRS_NEWP1B_Pos 3 +#define PWMG_IRS_NEWP1B_Msk (0x01 << PWMG_IRS_NEWP1B_Pos) +#define PWMG_IRS_NEWP2A_Pos 4 +#define PWMG_IRS_NEWP2A_Msk (0x01 << PWMG_IRS_NEWP2A_Pos) +#define PWMG_IRS_NEWP2B_Pos 5 +#define PWMG_IRS_NEWP2B_Msk (0x01 << PWMG_IRS_NEWP2B_Pos) +#define PWMG_IRS_NEWP3A_Pos 6 +#define PWMG_IRS_NEWP3A_Msk (0x01 << PWMG_IRS_NEWP3A_Pos) +#define PWMG_IRS_NEWP3B_Pos 7 +#define PWMG_IRS_NEWP3B_Msk (0x01 << PWMG_IRS_NEWP3B_Pos) +#define PWMG_IRS_NEWP4A_Pos 8 +#define PWMG_IRS_NEWP4A_Msk (0x01 << PWMG_IRS_NEWP4A_Pos) +#define PWMG_IRS_NEWP4B_Pos 9 +#define PWMG_IRS_NEWP4B_Msk (0x01 << PWMG_IRS_NEWP4B_Pos) +#define PWMG_IRS_NEWP5A_Pos 10 +#define PWMG_IRS_NEWP5A_Msk (0x01 << PWMG_IRS_NEWP5A_Pos) +#define PWMG_IRS_NEWP5B_Pos 11 +#define PWMG_IRS_NEWP5B_Msk (0x01 << PWMG_IRS_NEWP5B_Pos) +#define PWMG_IRS_HEND0A_Pos 12 +#define PWMG_IRS_HEND0A_Msk (0x01 << PWMG_IRS_HEND0A_Pos) +#define PWMG_IRS_HEND0B_Pos 13 +#define PWMG_IRS_HEND0B_Msk (0x01 << PWMG_IRS_HEND0B_Pos) +#define PWMG_IRS_HEND1A_Pos 14 +#define PWMG_IRS_HEND1A_Msk (0x01 << PWMG_IRS_HEND1A_Pos) +#define PWMG_IRS_HEND1B_Pos 15 +#define PWMG_IRS_HEND1B_Msk (0x01 << PWMG_IRS_HEND1B_Pos) +#define PWMG_IRS_HEND2A_Pos 16 +#define PWMG_IRS_HEND2A_Msk (0x01 << PWMG_IRS_HEND2A_Pos) +#define PWMG_IRS_HEND2B_Pos 17 +#define PWMG_IRS_HEND2B_Msk (0x01 << PWMG_IRS_HEND2B_Pos) +#define PWMG_IRS_HEND3A_Pos 18 +#define PWMG_IRS_HEND3A_Msk (0x01 << PWMG_IRS_HEND3A_Pos) +#define PWMG_IRS_HEND3B_Pos 19 +#define PWMG_IRS_HEND3B_Msk (0x01 << PWMG_IRS_HEND3B_Pos) +#define PWMG_IRS_HEND4A_Pos 20 +#define PWMG_IRS_HEND4A_Msk (0x01 << PWMG_IRS_HEND4A_Pos) +#define PWMG_IRS_HEND4B_Pos 21 +#define PWMG_IRS_HEND4B_Msk (0x01 << PWMG_IRS_HEND4B_Pos) +#define PWMG_IRS_HEND5A_Pos 22 +#define PWMG_IRS_HEND5A_Msk (0x01 << PWMG_IRS_HEND5A_Pos) +#define PWMG_IRS_HEND5B_Pos 23 +#define PWMG_IRS_HEND5B_Msk (0x01 << PWMG_IRS_HEND5B_Pos) +#define PWMG_IRS_HALT_Pos 24 +#define PWMG_IRS_HALT_Msk (0x01 << PWMG_IRS_HALT_Pos) + +typedef struct +{ + __IO uint32_t EN; //[0] ENABLE + + __IO uint32_t IE; //閸欘亪é撻弬銈嗗î¶å¨‘æ“„æ‹·1閺冨爼é撻弬銈嗗î¶IF[CHx]é—è·¨å–é‹å©šå¹ç»‹î—³Aé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撶紒éæ‘敾閹风兘é撻弬銈嗗î¶å§’Ñ„ç‘©é撴潪é–℃嫹1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹ç–¯æ¸¹ç»”撮惄鎾晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶0 + + __IO uint32_t IM; //é—è·¨å–é‹å©šå¹é“šå‚礋1閺冨爼é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚šâ–IF[CHx]娑擄拷1é—è·¨å–é‹å©šå¹ç»Œå®®a_int娑旂喖é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归崥顕€é撻敓锟�1 + + __IO uint32_t IF; //閸愶拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� + + uint32_t RESERVED[12]; + + struct + { + __IO uint32_t CR; + + __IO uint32_t AM; //Adress Mode + + __IO uint32_t SRC; + + __IO uint32_t SRCSGADDR1; //閸欘亪é撻弬銈嗗î¶Scatter Gather濡€崇础é—è·¨å–é‹å©šå¹é“šå‚šâ–é—è·¨å–é‹å©šå¹é”Ÿï¿½ + + __IO uint32_t SRCSGADDR2; //閸欘亪é撻弬銈嗗î¶Scatter Gather濡€崇础é—è·¨å–é‹å©šå¹é“šå‚šâ–é—è·¨å–é‹å©šå¹é”Ÿï¿½ + + __IO uint32_t SRCSGADDR3; //閸欘亪é撻弬銈嗗î¶Scatter Gather濡€崇础é—è·¨å–é‹å©šå¹é“šå‚šâ–é—è·¨å–é‹å©šå¹é”Ÿï¿½ + + __IO uint32_t SRCSGLEN; //閸欘亪é撻弬銈嗗î¶Scatter Gather濡€崇础é—è·¨å–é‹å©šå¹é“šå‚šâ–é—è·¨å–é‹å©šå¹é”Ÿï¿½ + + __IO uint32_t DST; + + __IO uint32_t DSTSGADDR1; //閸欘亪é撻弬銈嗗î¶Scatter Gather濡€崇础é—è·¨å–é‹å©šå¹é“šå‚šâ–é—è·¨å–é‹å©šå¹é”Ÿï¿½ + + __IO uint32_t DSTSGADDR2; //閸欘亪é撻弬銈嗗î¶Scatter Gather濡€崇础é—è·¨å–é‹å©šå¹é“šå‚šâ–é—è·¨å–é‹å©šå¹é”Ÿï¿½ + + __IO uint32_t DSTSGADDR3; //閸欘亪é撻弬銈嗗î¶Scatter Gather濡€崇础é—è·¨å–é‹å©šå¹é“šå‚šâ–é—è·¨å–é‹å©šå¹é”Ÿï¿½ + + __IO uint32_t DSTSGLEN; //閸欘亪é撻弬銈嗗î¶Scatter Gather濡€崇础é—è·¨å–é‹å©šå¹é“šå‚šâ–é—è·¨å–é‹å©šå¹é”Ÿï¿½ + + uint32_t RESERVED[4]; + } CH[3]; +} DMA_TypeDef; + +#define DMA_IE_CH0_Pos 0 +#define DMA_IE_CH0_Msk (0x01 << DMA_IE_CH0_Pos) +#define DMA_IE_CH1_Pos 1 +#define DMA_IE_CH1_Msk (0x01 << DMA_IE_CH1_Pos) +#define DMA_IE_CH2_Pos 2 +#define DMA_IE_CH2_Msk (0x01 << DMA_IE_CH2_Pos) +#define DMA_IE_CH3_Pos 3 +#define DMA_IE_CH3_Msk (0x01 << DMA_IE_CH3_Pos) +#define DMA_IE_CH4_Pos 4 +#define DMA_IE_CH4_Msk (0x01 << DMA_IE_CH4_Pos) +#define DMA_IE_CH5_Pos 5 +#define DMA_IE_CH5_Msk (0x01 << DMA_IE_CH5_Pos) +#define DMA_IE_CH6_Pos 6 +#define DMA_IE_CH6_Msk (0x01 << DMA_IE_CH6_Pos) +#define DMA_IE_CH7_Pos 7 +#define DMA_IE_CH7_Msk (0x01 << DMA_IE_CH7_Pos) + +#define DMA_IM_CH0_Pos 0 +#define DMA_IM_CH0_Msk (0x01 << DMA_IM_CH0_Pos) +#define DMA_IM_CH1_Pos 1 +#define DMA_IM_CH1_Msk (0x01 << DMA_IM_CH1_Pos) +#define DMA_IM_CH2_Pos 2 +#define DMA_IM_CH2_Msk (0x01 << DMA_IM_CH2_Pos) +#define DMA_IM_CH3_Pos 3 +#define DMA_IM_CH3_Msk (0x01 << DMA_IM_CH3_Pos) +#define DMA_IM_CH4_Pos 4 +#define DMA_IM_CH4_Msk (0x01 << DMA_IM_CH4_Pos) +#define DMA_IM_CH5_Pos 5 +#define DMA_IM_CH5_Msk (0x01 << DMA_IM_CH5_Pos) +#define DMA_IM_CH6_Pos 6 +#define DMA_IM_CH6_Msk (0x01 << DMA_IM_CH6_Pos) +#define DMA_IM_CH7_Pos 7 +#define DMA_IM_CH7_Msk (0x01 << DMA_IM_CH7_Pos) + +#define DMA_IF_CH0_Pos 0 +#define DMA_IF_CH0_Msk (0x01 << DMA_IF_CH0_Pos) +#define DMA_IF_CH1_Pos 1 +#define DMA_IF_CH1_Msk (0x01 << DMA_IF_CH1_Pos) +#define DMA_IF_CH2_Pos 2 +#define DMA_IF_CH2_Msk (0x01 << DMA_IF_CH2_Pos) +#define DMA_IF_CH3_Pos 3 +#define DMA_IF_CH3_Msk (0x01 << DMA_IF_CH3_Pos) +#define DMA_IF_CH4_Pos 4 +#define DMA_IF_CH4_Msk (0x01 << DMA_IF_CH4_Pos) +#define DMA_IF_CH5_Pos 5 +#define DMA_IF_CH5_Msk (0x01 << DMA_IF_CH5_Pos) +#define DMA_IF_CH6_Pos 6 +#define DMA_IF_CH6_Msk (0x01 << DMA_IF_CH6_Pos) +#define DMA_IF_CH7_Pos 7 +#define DMA_IF_CH7_Msk (0x01 << DMA_IF_CH7_Pos) + +#define DMA_CR_LEN_Pos 0 //é—è·¨å–é‹å©šå¹é‘解å“姘舵晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–婢冪粵瑙勫î¶é—跨喖銈洪æ•è¹‡æ–¿î¶0é—è·¨å–é‹å©šå¹å®„扮安1é—跨喕顢滈懞éŒï¸¾ç§¶é–¹é£Žå…˜é撻弬銈嗗î¶é—跨噦鎷�4096é—è·¨å–•é¡¢æ»ˆå¼¬éŠˆå——î¶ +#define DMA_CR_LEN_Msk (0xFFF << DMA_CR_LEN_Pos) +#define DMA_CR_RXEN_Pos 16 +#define DMA_CR_RXEN_Msk (0x01 << DMA_CR_RXEN_Pos) +#define DMA_CR_TXEN_Pos 17 +#define DMA_CR_TXEN_Msk (0x01 << DMA_CR_TXEN_Pos) +#define DMA_CR_AUTORE_Pos 18 //Auto Restart, é—岸é撻弬銈嗗î¶é—跨喕濡æ½éî„€î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归悵濠囨晸閺傘倖瀚瑰▎é˜ç»˜æ™¸é–ºå‚˜å€–瀚规潻婊堟晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨噦鎷� +#define DMA_CR_AUTORE_Msk (0x01 << DMA_CR_AUTORE_Pos) + +#define DMA_AM_SRCAM_Pos 0 //Address Mode 0 é—è·¨å–é‹å©šå¹å®„版絻é—è·¨å–é†â‚¬é ä½½î‰ç€šï¿½ 1 é—è·¨å–é‹å©šå¹å®„版絻é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� 2 scatter gather濡€崇础 +#define DMA_AM_SRCAM_Msk (0x03 << DMA_AM_SRCAM_Pos) +#define DMA_AM_DSTAM_Pos 8 +#define DMA_AM_DSTAM_Msk (0x03 << DMA_AM_DSTAM_Pos) +#define DMA_AM_BURST_Pos 16 +#define DMA_AM_BURST_Msk (0x01 << DMA_AM_BURST_Pos) + +typedef struct +{ + __IO uint32_t CR; //Control Register + + __O uint32_t CMD; //Command Register + + __I uint32_t SR; //Status Register + + __I uint32_t IF; //Interrupt Flag + + __IO uint32_t IE; //Interrupt Enable + + uint32_t RESERVED; + + __IO uint32_t BT0; //Bit Time Register 0 + + __IO uint32_t BT1; //Bit Time Register 1 + + uint32_t RESERVED2[3]; + + __I uint32_t ALC; //Arbitration Lost Capture, é—跨喎濮憗浣筋啇閹峰嘲銇戦柨é”å‘Šç®é–¹çƒ½æ”±å®•ï¿½ + + __I uint32_t ECC; //Error code capture, é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±é§å²„煫璇ф嫹 + + __IO uint32_t EWLIM; //Error Warning Limit, é—è·¨å–é‹å©šå¹é‘芥晸éŸæ¥ƒå–濮ら幘é›î†¼î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� + + __IO uint32_t RXERR; //RXé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻敓锟� + + __IO uint32_t TXERR; //TXé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻敓锟� + + union + { + struct //é—跨喕濡棃鈺傚î¶å¨´ï½…秵妞傞柨é”哄嵆é ä½½î‰ç€šå½’崘娆撴晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚瑰Ο鈥崇础é—跨喖鎽î†æ‹ è¤Žç€šå½’柨é”哄嵆閸戙倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· + { + __IO uint32_t ACR[4]; //Acceptance Check Register, é—è·¨å–é‹å©šå¹é‘芥晸ç¼å¤ŒÇ¹é¦åº¢æ½éî„€î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ + + __IO uint32_t AMR[4]; //Acceptance Mask Register, é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撴潪é¨î†¾æ§‘é‰å ¢å“瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹å®„扮安娴ｅ秴éŸï¿½0é—è·¨å–é‹å©šå¹ç»‹ã€¥é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–¸æ¥ƒå§µæ¿¯çƒ½æŸ¨é”å‘Šç®é–¹é£Žå…˜é撻悪掳éŽå©šå¹é‘芥晸閿燂拷 + + uint32_t RESERVED[5]; + } FILTER; + + union //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é–¿å¬†ä½¸î‡£è¹‡æ¶™æ™¸é—炬澘褰茬拋瑙勫î¶é–¸æ„­ç‘©é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œç§´é–ºå†¨çˆ¼é撻弬銈嗗î¶é—跨喓é—抽崙銈嗗î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ + { + struct + { + __O uint32_t INFO; + + __O uint32_t DATA[12]; + } TXFRAME; + + struct + { + __I uint32_t INFO; + + __I uint32_t DATA[12]; + } RXFRAME; + }; + }; + + __I uint32_t RMCNT; //Receive Message Count + + uint32_t RESERVED3[66]; + + struct //TXFRAMEé—è·¨å–鑼庣拋瑙勫î¶é—è·¨å–ç”¯æ’®å´ éˆ©å†¨î¶ + { + __I uint32_t INFO; + + __I uint32_t DATA[12]; + } TXFRAME_R; +} CAN_TypeDef; + +#define CAN_CR_RST_Pos 0 +#define CAN_CR_RST_Msk (0x01 << CAN_CR_RST_Pos) +#define CAN_CR_LOM_Pos 1 //Listen Only Mode +#define CAN_CR_LOM_Msk (0x01 << CAN_CR_LOM_Pos) +#define CAN_CR_STM_Pos 2 //Self Test Mode, é—è·¨å–é‹å©šå¹é–¿å¬†ä½¸î‡£è¹‡æ¶™æ™¸é—炬壆銆嬮å¹é“šå‚šâ–濞岋ç¹é撻弬銈嗗î¶éŽ¼å­˜æ£ƒé撻弬銈嗗î¶CANé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹ç–¯æ¸¹ç»¡å†®æŸ¨é”å‘Šç®é–¹é£Žå…˜é撻惃é¡æ¨ºç‡é–»Ñƒæ†¡ç€šå½’柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define CAN_CR_STM_Msk (0x01 << CAN_CR_STM_Pos) +#define CAN_CR_AFM_Pos 3 //Acceptance Filter Mode, 1 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喎澹欑拠褎瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶32娴ｅ秹éæ’»å¼¬éŠˆå——î¶ 0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喎澹欑拠褎瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶16娴ｅ秹éæ’»å¼¬éŠˆå——î¶ +#define CAN_CR_AFM_Msk (0x01 << CAN_CR_AFM_Pos) +#define CAN_CR_SLEEP_Pos 4 //閸愶拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归惈锟犳晸閺傘倖瀚瑰Ο鈥崇础é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撶粩顓熸ãŸé–¸æ–»åŠ‘é撻弬銈嗗î¶é—跨喎褰ㄧ拋瑙勫î¶é–ºå†¨çˆ¼é撻弬銈嗗î¶é—跨喓é›ã‚‡æ‹ è¤Žç€šå½’柨é”烘畷é ä½½î‰ç€šå½’柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喕濞囬敓锟� +#define CAN_CR_SLEEP_Msk (0x01 << CAN_CR_SLEEP_Pos) +#define CAN_CR_DMAEN_Pos 5 +#define CAN_CR_DMAEN_Msk (0x01 << CAN_CR_DMAEN_Pos) + +#define CAN_CMD_TXREQ_Pos 0 //Transmission Request +#define CAN_CMD_TXREQ_Msk (0x01 << CAN_CMD_TXREQ_Pos) +#define CAN_CMD_ABTTX_Pos 1 //Abort Transmission +#define CAN_CMD_ABTTX_Msk (0x01 << CAN_CMD_ABTTX_Pos) +#define CAN_CMD_RRB_Pos 2 //Release Receive Buffer +#define CAN_CMD_RRB_Msk (0x01 << CAN_CMD_RRB_Pos) +#define CAN_CMD_CLROV_Pos 3 //Clear Data Overrun +#define CAN_CMD_CLROV_Msk (0x01 << CAN_CMD_CLROV_Pos) +#define CAN_CMD_SRR_Pos 4 //Self Reception Request +#define CAN_CMD_SRR_Msk (0x01 << CAN_CMD_SRR_Pos) + +#define CAN_SR_RXDA_Pos 0 //Receive Data Availableé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£ŽÃ©IFOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é–¿å¬©ç´–é—è·¨å–é‹å©šå¹é‘芥晸閻ㄥ棜顔愰å¹å®„æ¿çµ¿ +#define CAN_SR_RXDA_Msk (0x01 << CAN_SR_RXDA_Pos) +#define CAN_SR_RXOV_Pos 1 //Receive FIFO Overruné—è·¨å–é‹å©šå¹é‘芥晸é—剧増é‹å©šå¹é‘芥晸ç¼å¤Šæ‘œé¡£î‡€å¹é‘芥晸閺傘倖瀚归å¹é¡–炴晸閺傘倖瀚归柨é”诲Î閺傘倖瀚归柨é”å‘Šç®é–¹é£ŽÃ©IFOé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ +#define CAN_SR_RXOV_Msk (0x01 << CAN_SR_RXOV_Pos) +#define CAN_SR_TXBR_Pos 2 //Transmit Buffer Releaseé—è·¨å–é‹å©šå¹é”Ÿï¿½0 é—è·¨å–é‹å©šå¹é‘芥晸閼哄倽鎻îˆå¹é‘芥晸閺傘倖瀚归崜宥夋晸閺傘倖瀚规慨é¡æ¶™æ™¸é–ºå‚˜å€–瀚归崑婊堟晸閺傘倖瀚归柨é”å‘Šç®é–¹é£ŽæŸ‰é¦î„„柨é”å‘Šç®é–¹é£Žå…˜é撻崣é¡ãƒ¦å½§é–¹çƒ½î—“é¡£é柨é”å‘Šç®é–¹é£Žå…˜éæ’´æ½é挎嫹 1 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归崘娆撴晸閺傘倖瀚归柨é”兼應绾æ¿î˜°ç€šå½’柨é”å‘Šç®é–¹çƒ½æ”±æµ¼å‘´æŸ¨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define CAN_SR_TXBR_Msk (0x01 << CAN_SR_TXBR_Pos) +#define CAN_SR_TXOK_Pos 3 //Transmit OKé—è·¨å–é‹å©šå¹ç»Œæ¼¸ccessfully completed +#define CAN_SR_TXOK_Msk (0x01 << CAN_SR_TXOK_Pos) +#define CAN_SR_RXBUSY_Pos 4 //Receive Busyé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”诲Î閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define CAN_SR_RXBUSY_Msk (0x01 << CAN_SR_RXBUSY_Pos) +#define CAN_SR_TXBUSY_Pos 5 //Transmit Busyé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”诲Î閸戙倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define CAN_SR_TXBUSY_Msk (0x01 << CAN_SR_TXBUSY_Pos) +#define CAN_SR_ERRWARN_Pos 6 //1 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规稉鈧柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—åž®éªéŽ·ï¿½ Warning Limit +#define CAN_SR_ERRWARN_Msk (0x01 << CAN_SR_ERRWARN_Pos) +#define CAN_SR_BUSOFF_Pos 7 //1 CAN é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”侯仾閸忚櫕éžå©šå¹æ¤‹åº¡Ð¦é–¹îƒ¿ç·šé撻弬銈嗗î¶æ¿žå²‹ç¹é撻崣é¡ãƒ®åš‹é–¹é£Žå…˜é撶拠é¡ãˆ ç…‚é—è·¨å–é‹å©šå¹é‘芥晸ç¼æ—‘厽妞å—å´é”Ÿï¿½ +#define CAN_SR_BUSOFF_Msk (0x01 << CAN_SR_BUSOFF_Pos) + +#define CAN_IF_RXDA_Pos 0 //IF.RXDA = SR.RXDA & IE.RXDA +#define CAN_IF_RXDA_Msk (0x01 << CAN_IF_RXDA_Pos) +#define CAN_IF_TXBR_Pos 1 //é—è·¨å–é‹å©šå¹ç»‹ã€¦.TXBR=1閺冨爼é撻弬銈嗗î¶SR.TXBRé—è·¨å–é‹å©šå¹é”Ÿï¿½0é—è·¨å–é‹å©šå¹é‘芥晸閿燂拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚规担锟� +#define CAN_IF_TXBR_Msk (0x01 << CAN_IF_TXBR_Pos) +#define CAN_IF_ERRWARN_Pos 2 //é—è·¨å–é‹å©šå¹ç»‹ã€¦.ERRWARN=1閺冨爼é撻弬銈嗗î¶SR.ERRWARNé—è·¨å–é‹å©šå¹ç»‹ç¢¦.BUSOFF 0-to-1 é—è·¨å–é‹å©šå¹é”Ÿï¿½ 1-to-0é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚规担锟� +#define CAN_IF_ERRWARN_Msk (0x01 << CAN_IF_ERRWARN_Pos) +#define CAN_IF_RXOV_Pos 3 //IF.RXOV = SR.RXOV & IE.RXOV +#define CAN_IF_RXOV_Msk (0x01 << CAN_IF_RXOV_Pos) +#define CAN_IF_WKUP_Pos 4 //é—è·¨å–é‹å©šå¹ç»‹ã€¦.WKUP=1閺冨爼é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹æ¤‹åº¢è’‹é—è·¨å–é‹å©šå¹é–¿å¬†ä½¸î‡£è¹‡æ¶™æ™¸é—炬壆顣å¹ç»‹î”§Né—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–»æ¶šå“é‹å©šå¹é‘芥晸閺傘倖瀚归崨瀣î„澔椤曞ç绨㈢拠褎瀚归柨é”å‘Šç®é–¹é£Žå…˜é撴潪é–℃嫹 +#define CAN_IF_WKUP_Msk (0x01 << CAN_IF_WKUP_Pos) +#define CAN_IF_ERRPASS_Pos 5 // +#define CAN_IF_ERRPASS_Msk (0x01 << CAN_IF_ERRPASS_Pos) +#define CAN_IF_ARBLOST_Pos 6 //Arbitration Losté—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚笽E.ARBLOST=1閺冨爼é撻弬銈嗗î¶CANé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶å©¢å •äº¶éæ’»å´é¡ãƒ®æ¢¿é–¹æ’瀚圭仦閬嶆晸閺傘倖瀚规æ½å¦¤å‘®æ™¸ç¼‚佺å›ç»¨ãˆ¢æ‹ è¤Žç€šå½’柨é”å‘Šç®é–¹é£Žå…˜é撴潪é–℃嫹 +#define CAN_IF_ARBLOST_Msk (0x01 << CAN_IF_ARBLOST_Pos) +#define CAN_IF_BUSERR_Pos 7 //é—è·¨å–é‹å©šå¹ç»‹ã€¦.BUSERR=1閺冨爼é撻弬銈嗗î¶CANé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–»æ¶šå“é‹å©šå¹é‘芥晸閺傘倖瀚归崣浠嬫晸閺傘倖瀚归柨é”虹哺鎼æ‘洩顕滈å¹é‘芥晸閺傘倖瀚归柨é”诲â–閿燂拷 +#define CAN_IF_BUSERR_Msk (0x01 << CAN_IF_BUSERR_Pos) + +#define CAN_IE_RXDA_Pos 0 +#define CAN_IE_RXDA_Msk (0x01 << CAN_IE_RXDA_Pos) +#define CAN_IE_TXBR_Pos 1 +#define CAN_IE_TXBR_Msk (0x01 << CAN_IE_TXBR_Pos) +#define CAN_IE_ERRWARN_Pos 2 +#define CAN_IE_ERRWARN_Msk (0x01 << CAN_IE_ERRWARN_Pos) +#define CAN_IE_RXOV_Pos 3 +#define CAN_IE_RXOV_Msk (0x01 << CAN_IE_RXOV_Pos) +#define CAN_IE_WKUP_Pos 4 +#define CAN_IE_WKUP_Msk (0x01 << CAN_IE_WKUP_Pos) +#define CAN_IE_ERRPASS_Pos 5 +#define CAN_IE_ERRPASS_Msk (0x01 << CAN_IE_ERRPASS_Pos) +#define CAN_IE_ARBLOST_Pos 6 +#define CAN_IE_ARBLOST_Msk (0x01 << CAN_IE_ARBLOST_Pos) +#define CAN_IE_BUSERR_Pos 7 +#define CAN_IE_BUSERR_Msk (0x01 << CAN_IE_BUSERR_Pos) + +#define CAN_BT0_BRP_Pos 0 //Baud Rate Prescaleré—è·¨å–é‹å©šå¹ç»‹î”§N閺冨爼é撻幋鎺æˆç¤‹å¨´ï½æ‹·=2*Tsysclk*(BRP+1) +#define CAN_BT0_BRP_Msk (0x3F << CAN_BT0_BRP_Pos) +#define CAN_BT0_SJW_Pos 6 //Synchronization Jump Width +#define CAN_BT0_SJW_Msk (0x03 << CAN_BT0_SJW_Pos) + +#define CAN_BT1_TSEG1_Pos 0 //t_tseg1 = CAN閺冨爼é撻幋鎺æˆç¤‹å¨´ï½æ‹· * (TSEG1+1) +#define CAN_BT1_TSEG1_Msk (0x0F << CAN_BT1_TSEG1_Pos) +#define CAN_BT1_TSEG2_Pos 4 //t_tseg2 = CAN閺冨爼é撻幋鎺æˆç¤‹å¨´ï½æ‹· * (TSEG2+1) +#define CAN_BT1_TSEG2_Msk (0x07 << CAN_BT1_TSEG2_Pos) +#define CAN_BT1_SAM_Pos 7 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ 0: sampled once 1: sampled three times +#define CAN_BT1_SAM_Msk (0x01 << CAN_BT1_SAM_Pos) + +#define CAN_ECC_SEGCODE_Pos 0 //Segment Code +#define CAN_ECC_SEGCODE_Msk (0x0F << CAN_ECC_SEGCODE_Pos) +#define CAN_ECC_DIR_Pos 4 //0 error occurred during transmission 1 during reception +#define CAN_ECC_DIR_Msk (0x01 << CAN_ECC_DIR_Pos) +#define CAN_ECC_ERRCODE_Pos 5 //Error Codeé—è·¨å–é‹å©šå¹é”Ÿï¿½0 Bit error 1 Form error 2 Stuff error 3 other error +#define CAN_ECC_ERRCODE_Msk (0x03 << CAN_ECC_ERRCODE_Pos) + +#define CAN_INFO_DLC_Pos 0 //Data Length Control +#define CAN_INFO_DLC_Msk (0x0F << CAN_INFO_DLC_Pos) +#define CAN_INFO_RTR_Pos 6 //Remote Frameé—è·¨å–é‹å©šå¹é”Ÿï¿½1 é‰â•‚粓é撻弬銈嗗î¶é¢îˆ¤æ‹· 0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚圭敮锟� +#define CAN_INFO_RTR_Msk (0x01 << CAN_INFO_RTR_Pos) +#define CAN_INFO_FF_Pos 7 //Frame Formaté—è·¨å–é‹å©šå¹é”Ÿï¿½0 é—è·¨å–é‹å©šå¹å®„æ¿æ«™é¢îˆ†å›¨æ™¸é–ºå‚˜å€–瀚瑰锟� 1 é—è·¨å–é‹å©šå¹å®„扮潔é¢îˆ†å›¨æ™¸é–ºå‚˜å€–瀚瑰锟� +#define CAN_INFO_FF_Msk (0x01 << CAN_INFO_FF_Pos) + +typedef struct +{ + __IO uint32_t IE; //[0] 娑擄拷0é—è·¨å–é‹å©šå¹é–¿å¬«î˜§é—è·¨å–é‹å©šå¹ç»‹ã€§[0]缂佹挳é撻弬銈嗗î¶å¨‘æ“„æ‹·0 + + __IO uint32_t IF; //[0] é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”活敎闂堚晜瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶å¦¤ï½…﹪é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é¤îˆšç¦‚é—è·¨å–é‹å©šå¹é‘芥晸缂佺åžéžå©šå¹é‘芥晸閿燂拷1é—è·¨å–é‹å©šå¹å®„æ¿æ™¸1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� + + __IO uint32_t IM; //[0] é—è·¨å–é‹å©šå¹é‘芥晸閻å„é¦åº¢æ½éî„€î¶é—è·¨å–é‹å©šå¹é“šå‚礋1閺冨爼é撻弬銈嗗î¶LCDCé—è·¨å–é‹å©šå¹é‘芥晸閸欘å…éŒå›©æ‹ è¤Žç€šå½’柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸é‰å å•©ç¼å—™ç²µç‘™å‹«î¶é—è·¨å–é‹å©šå¹å®„æ¿ç¥»ç€¹å‹¶ç¹é撻弬銈嗗î¶é–½â‚¬å®¥å——é—è·¨å–é‹å©šå¹é‘芥晸閿燂拷 + + __IO uint32_t START; + + __IO uint32_t SRCADDR; //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚瑰┃鎰版晸閺傘倖瀚归崸鈧柨é”惰寧é‰å ¢å“瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶30娴ｅ秹é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规担宥夋晸閻ㄥ棜顔愰å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· + + __IO uint32_t CR0; + + __IO uint32_t CR1; + + __IO uint32_t PRECMDV; //é—è·¨å–é‹å©šå¹ç»‹ç’“Ué—è·¨å–甯撮崠鈩冨î¶é—跨喎褰ㄩæ•è¹‡æ–¿î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é–¸æ’³ç§¹é撻弬銈嗗î¶RSé—è·¨å–é‹å©šå¹é‘芥晸é—扮數顣å¹é‘芥晸閺傘倖瀚规稉鈧柨é”惰寧閿濆繑瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”è¤çª›ç»¾æ¿î˜°ç€šå½’å´é”Ÿï¿½ +} LCD_TypeDef; + +#define LCD_START_MPUEN_Pos 0 //0 RGBé—è·¨å–ç”¯æ’®å´ éˆ©å†¨î¶ 1 MPUé—è·¨å–ç”¯æ’®å´ éˆ©å†¨î¶ +#define LCD_START_MPUEN_Msk (0x01 << LCD_START_MPUEN_Pos) +#define LCD_START_GO_Pos 1 //閸愶拷1é—è·¨å–é‹å©šå¹å®„邦潗é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻幑é‘ょ秶閹风兘é撻弬銈嗗î¶é—è·¨å–宓庢æ½éî„€î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é‰â•‚粓é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閿燂拷 +#define LCD_START_GO_Msk (0x01 << LCD_START_GO_Pos) +#define LCD_START_BURST_Pos 2 +#define LCD_START_BURST_Msk (0x01 << LCD_START_BURST_Pos) +#define LCD_START_POSTCMDE_Pos 3 //é—è·¨å–é‹å©šå¹é“šå‚œæ˜‚é—è·¨å–é‹å©šå¹é¤îˆ£æ´£é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归崘娆撴晸閺傘倖瀚归å¹é¥î„晸閺傘倖瀚归柨é”活敎椤曞棙瀚归摶éœä½¸åŠ‰é—è·¨å–褰æ´ãˆ î¶é—è·¨å–褰导娆愬î¶é—跨噦鎷�0x80é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸éžæ¶™îšéŽ·ï¿½ +#define LCD_START_POSTCMDE_Msk (0x01 << LCD_START_POSTCMDE_Pos) +#define LCD_START_POSTCMDV_Pos 4 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸éžæ¶™îš†éŽ·æ¿‹å¹é‘芥晸閺傘倖瀚归崘éŠã‚†æ™¸é–ºå‚˜å€–瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚圭化濠氭晸éžæ¶™îšˆé¡£î‡€å¹é‘芥晸娓氥儺é“ã„©å¹é‘芥晸閺傘倖瀚归柨é•å‚›å«¹0x80é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é¤îˆ£æ´£é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define LCD_START_POSTCMDV_Msk (0xFFFF << LCD_START_POSTCMDV_Pos) + +#define LCD_CR0_VPIX_Pos 0 //é—è·¨å–é‹å©šå¹ç»Œæ­°rtrait娑擄拷0閺冨爼é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›é—è·¨å–é‹å©šå¹æ¤‹åº¢çº¯é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶å¦«ï½†îšŠé撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閿燂拷0é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撴潪é–℃嫹767 +//é—è·¨å–é‹å©šå¹ç»Œæ­°rtrait娑擄拷1閺冨爼é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›æ¿®æ¨»æ½™é–½â•…柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规＃妤呮晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻敓锟�0é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撴潪é–℃嫹767 +#define LCD_CR0_VPIX_Msk (0x3FF << LCD_CR0_VPIX_Pos) +#define LCD_CR0_HPIX_Pos 10 //é—è·¨å–é‹å©šå¹ç»Œæ­°rtrait娑擄拷0閺冨爼é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›æ¿®æ¨»æ½™é–½â•…柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规＃妤呮晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻敓锟�0é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撴潪é–℃嫹1023 +//é—è·¨å–é‹å©šå¹ç»Œæ­°rtrait娑擄拷1閺冨爼é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›é—è·¨å–é‹å©šå¹æ¤‹åº¢çº¯é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶å¦«ï½†îšŠé撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閿燂拷0é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撴潪é–℃嫹1023 +#define LCD_CR0_HPIX_Msk (0x3FF << LCD_CR0_HPIX_Pos) +#define LCD_CR0_DCLK_Pos 20 //0 DOTCLK娑撯å“閻╂挳é撻弬銈嗗î¶é‰çƒ‡æ‹· 1 DOTCLKé—跨喕濡崠鈩冨î¶é—è·¨å–é‹å©šå¹é–¿å¬«î˜§é–¸å¬«ç²“é撻弬銈嗗î¶1 +#define LCD_CR0_DCLK_Msk (0x01 << LCD_CR0_DCLK_Pos) +#define LCD_CR0_HLOW_Pos 21 //é—è·¨å–é‹å©šå¹é‘芥晸ç¼è¾©ç¬ŒYNCé—跨喖é™è™¹å–Šæ¾¶å¬ªî¶æ¥ ç‚´å¨Šé撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”峰Л闂堚晜瀚笵OTCLKé—è·¨å–é‹å©šå¹é‘芥晸閼哄åŠç¼å›¬å¹é”Ÿï¿½0é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define LCD_CR0_HLOW_Msk (0x03 << LCD_CR0_HLOW_Pos) + +#define LCD_CR0_DLEN_Pos 0 //MPUé—è·¨å–甯撮崠鈩冨î¶é–ºå†¨çˆ¼é撻弬銈嗗î¶é—跨喎澹æ¬â–Žé™‡é¡•æ»ˆå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–宓庣粵瑙勫î¶é—跨喖銈洪æ•è¹‡æ–¿î¶é—è·¨å–é‹å©šå¹é“šå‚œç§´å¨‘撴椽é撶悰妤勫Î閿濆繑瀚�0é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›1é—è·¨å–é‹å©šå¹é”Ÿï¿½ +#define LCD_CR0_DLEN_Msk (0x1FFFFF << LCD_CR0_DLEN_Pos) + +#define LCD_CR1_DIRV_Pos 0 //0 portrait=0é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±è†©ç€µî‡†æ‹· 1 portrait=1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±è†©ç€µî‡†æ‹· +#define LCD_CR1_DIRV_Msk (0x01 << LCD_CR1_DIRV_Pos) +#define LCD_CR1_VFP_Pos 1 +#define LCD_CR1_VFP_Msk (0x07 << LCD_CR1_VFP_Pos) +#define LCD_CR1_VBP_Pos 4 +#define LCD_CR1_VBP_Msk (0x1F << LCD_CR1_VBP_Pos) +#define LCD_CR1_HFP_Pos 9 +#define LCD_CR1_HFP_Msk (0x1F << LCD_CR1_HFP_Pos) +#define LCD_CR1_HBP_Pos 14 +#define LCD_CR1_HBP_Msk (0x7F << LCD_CR1_HBP_Pos) +#define LCD_CR1_DCLKDIV_Pos 21 //DOTCLKé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”惰寧閿濆繑瀚归柨é”虹哺閹æ’瀚归å¹éŠ‰ãƒ®æ½’é—跨喓瀚涚喊澶嬪î¶å§’é撻敓锟�0é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›2é—è·¨å–é‹å©šå¹é‘筋暥é—è·¨å–é‹å©šå¹é”Ÿï¿½1é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›4é—è·¨å–é‹å©šå¹é‘筋暥 ... +#define LCD_CR1_DCLKDIV_Msk (0x1F << LCD_CR1_DCLKDIV_Pos) +#define LCD_CR1_DCLKINV_Pos 26 //1 é—è·¨å–é‹å©šå¹é‘芥晸ç¼è¾©ç‹TCLKé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规惔éƒå Ÿæ™¸é–ºå‚˜å€–瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶DOTCLKé—跨喖鎽îˆå¼¬éŠˆå——î¶é—è·¨å–é©å‘¯æ‹ è¤Žç€šå½’柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–宓庣喊澶嬪î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ +#define LCD_CR1_DCLKINV_Msk (0x01 << LCD_CR1_DCLKINV_Pos) + +#define LCD_CR1_REG_Pos 0 //LCD_CR1_CMD_Posé–¸æ¬ç‰•éˆ§î„Šæ‹·1閺冨爼é撻弬銈嗗î¶é—è·¨å–鑼庢æ½éî„€î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å³°å˜²éˆ§î„Šæ‹· +#define LCD_CR1_REG_Msk (0xFFFF << LCD_CR1_REG_Pos) +#define LCD_CR1_I80_Pos 16 //1 é—è·¨å–甯撮崠鈩冨î¶å¨‘撶瘨80 0 é—è·¨å–甯撮崠鈩冨î¶å¨‘撶瘲68 +#define LCD_CR1_I80_Msk (0x01 << LCD_CR1_I80_Pos) +#define LCD_CR1_CMD_Pos 17 //0 é—è·¨å–é‹å©šå¹é‘芥晸閹圭柉鎻îˆå¹é‘芥晸閹存帪绱濋柨é”å‘Šç®é–¹é£ŽÃºS娑撴椽é撶粩顓狀暜閹峰嘲閽� 1 é—è·¨å–é‹å©šå¹é‘芥晸ç¼æ¶˜îƒ„绱堕柨é”稿çŠé–¿æ¶˜çŸ‚é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归å¹é¥î„晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”虹ゲS娑撴椽é撻柊é¢æ®¿æšœé–¹å³°å˜²é–½ï¿½ +#define LCD_CR1_CMD_Msk (0x01 << LCD_CR1_CMD_Pos) +#define LCD_CR1_TTAIL_Pos 18 //CSné—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿焻绾æ¿î˜°ç€šç¬´Sné—跨喖鎽îˆå¼¬éŠˆå——î¶é—è·¨å–é©å‘¯å–Šæ¾¶å¬ªî¶é–ºå†¨çˆ¼éæ’»å¼¬éŠˆå——î¶ +#define LCD_CR1_TTAIL_Msk (0x07 << LCD_CR1_TTAIL_Pos) +#define LCD_CR1_TAH_Pos 21 //WRné—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿焻绾æ¿î˜°ç€šç¬´Sné—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿焻绾æ¿î˜°ç€šå½’å¼®é«æ›Ÿæ™¸é–ºå‚˜å€–瀚� +#define LCD_CR1_TAH_Msk (0x03 << LCD_CR1_TAH_Pos) +#define LCD_CR1_TPWLW_Pos 23 //WRné—跨喖é™è™¹å–Šæ¾¶å¬ªî¶æ¥ ç‚´å¨Šé撴笟銉ь劜閹风兘é撻弬銈嗗î¶é–ºå†¨çˆ¼éæ’»å¼¬éŠˆå——î¶ +#define LCD_CR1_TPWLW_Msk (0x07 << LCD_CR1_TPWLW_Pos) +#define LCD_CR1_TAS_Pos 26 //CSné—跨喖鎽îˆå¼¬éŠˆå——î¶é—è·¨å–é©å‘¯å–Šæ¾¶å¬ªî¶WRné—跨喖鎽îˆå¼¬éŠˆå——î¶é—è·¨å–é©å‘¯å–Šæ¾¶å¬ªî¶é–ºå†¨çˆ¼éæ’»å¼¬éŠˆå——î¶ +#define LCD_CR1_TAS_Msk (0x03 << LCD_CR1_TAS_Pos) + +typedef struct +{ + __IO uint32_t DMA_MEM_ADDR; + + __IO uint32_t BLK; //Block Size and Count + + __IO uint32_t ARG; //Argument + + __IO uint32_t CMD; //Command + + __IO uint32_t RESP[4]; //Response + + __IO uint32_t DATA; + + __IO uint32_t STAT; + + __IO uint32_t CR1; + + __IO uint32_t CR2; + + __IO uint32_t IF; + + __IO uint32_t IE; + + __IO uint32_t IM; + + __IO uint32_t CMD12ERR; + + __IO uint32_t INFO; + + __IO uint32_t MAXCURR; +} SDIO_TypeDef; + +#define SDIO_BLK_SIZE_Pos 0 //0x200 512é—è·¨å–•é¡¢æ»ˆå¼¬éŠˆå——î¶ 0x400 1024é—è·¨å–•é¡¢æ»ˆå¼¬éŠˆå——î¶ 0x800 2048é—è·¨å–•é¡¢æ»ˆå¼¬éŠˆå——î¶ +#define SDIO_BLK_SIZE_Msk (0xFFF << SDIO_BLK_SIZE_Pos) +#define SDIO_BLK_COUNT_Pos 16 //0 Stop Transfer 1 1é—è·¨å–é‹å©šå¹é”Ÿï¿½ 2 2é—è·¨å–é‹å©šå¹é”Ÿï¿½ ... ... +#define SDIO_BLK_COUNT_Msk (0xFFF << SDIO_BLK_COUNT_Pos) + +#define SDIO_CMD_DMAEN_Pos 0 +#define SDIO_CMD_DMAEN_Msk (0x01 << SDIO_CMD_DMAEN_Pos) +#define SDIO_CMD_BLKCNTEN_Pos 1 +#define SDIO_CMD_BLKCNTEN_Msk (0x01 << SDIO_CMD_BLKCNTEN_Pos) +#define SDIO_CMD_AUTOCMD12_Pos 2 +#define SDIO_CMD_AUTOCMD12_Msk (0x01 << SDIO_CMD_AUTOCMD12_Pos) +#define SDIO_CMD_DIRREAD_Pos 4 //0 Write, Host to Card 1 Read, Card to Host +#define SDIO_CMD_DIRREAD_Msk (0x01 << SDIO_CMD_DIRREAD_Pos) +#define SDIO_CMD_MULTBLK_Pos 5 //0 Single Block 1 Multiple Block +#define SDIO_CMD_MULTBLK_Msk (0x01 << SDIO_CMD_MULTBLK_Pos) +#define SDIO_CMD_RESPTYPE_Pos 16 //é—è·¨å–é‹å©šå¹å®„扮安é—è·¨å–é‹å©šå¹é‘芥晸é—扮ç¼å›¬å¹é”Ÿï¿½0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规惔锟� 1 136娴ｅ秹é撻弬銈嗗î¶éŽ¼è¾¾æ‹· 2 48娴ｅ秹é撻弬銈嗗î¶éŽ¼è¾¾æ‹· 3 48娴ｅ秹é撻弬銈嗗î¶éŽ¼å­˜æ£ƒé撻弬銈嗗î¶Busy after response +#define SDIO_CMD_RESPTYPE_Msk (0x03 << SDIO_CMD_RESPTYPE_Pos) +#define SDIO_CMD_CRCCHECK_Pos 19 //Command CRC Check Enable +#define SDIO_CMD_CRCCHECK_Msk (0x01 << SDIO_CMD_CRCCHECK_Pos) +#define SDIO_CMD_IDXCHECK_Pos 20 //Command Index Check Enable +#define SDIO_CMD_IDXCHECK_Msk (0x01 << SDIO_CMD_IDXCHECK_Pos) +#define SDIO_CMD_HAVEDATA_Pos 21 //0 No Data Present 1 Data Present +#define SDIO_CMD_HAVEDATA_Msk (0x01 << SDIO_CMD_HAVEDATA_Pos) +#define SDIO_CMD_CMDTYPE_Pos 22 //0 NORMAL 1 SUSPEND 2 RESUME 3 ABORT +#define SDIO_CMD_CMDTYPE_Msk (0x03 << SDIO_CMD_CMDTYPE_Pos) +#define SDIO_CMD_CMDINDX_Pos 24 //Command Indexé—è·¨å–é‹å©šå¹ç»‹î”³D0-63é—è·¨å–é‹å©šå¹ç»‹çƒ MD0-63 +#define SDIO_CMD_CMDINDX_Msk (0x3F << SDIO_CMD_CMDINDX_Pos) + +#define SDIO_CR1_4BIT_Pos 1 //1 4 bit mode 0 1 bit mode +#define SDIO_CR1_4BIT_Msk (0x01 << SDIO_CR1_4BIT_Pos) +#define SDIO_CR1_8BIT_Pos 5 //1 8 bit mode is selected 0 8 bit mode is not selected +#define SDIO_CR1_8BIT_Msk (0x01 << SDIO_CR1_8BIT_Pos) +#define SDIO_CR1_CDBIT_Pos 6 //0 No Card 1 Card Inserted +#define SDIO_CR1_CDBIT_Msk (0x01 << SDIO_CR1_CDBIT_Pos) +#define SDIO_CR1_CDSRC_Pos 7 //Card Detect Source, 1 CR1.CDBIT娴ï½æ‹· 0 SD_Detecté—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define SDIO_CR1_CDSRC_Msk (0x01 << SDIO_CR1_CDSRC_Pos) +#define SDIO_CR1_PWRON_Pos 8 //1 Power on 0 Power off +#define SDIO_CR1_PWRON_Msk (0x01 << SDIO_CR1_PWRON_Pos) +#define SDIO_CR1_VOLT_Pos 9 //7 3.3V 6 3.0V 5 1.8V +#define SDIO_CR1_VOLT_Msk (0x07 << SDIO_CR1_VOLT_Pos) + +#define SDIO_CR2_CLKEN_Pos 0 //Internal Clock Enable +#define SDIO_CR2_CLKEN_Msk (0x01 << SDIO_CR2_CLKEN_Pos) +#define SDIO_CR2_CLKRDY_Pos 1 //Internal Clock Stable/Ready +#define SDIO_CR2_CLKRDY_Msk (0x01 << SDIO_CR2_CLKRDY_Pos) +#define SDIO_CR2_SDCLKEN_Pos 2 //SDCLK Enable +#define SDIO_CR2_SDCLKEN_Msk (0x01 << SDIO_CR2_SDCLKEN_Pos) +#define SDIO_CR2_SDCLKDIV_Pos 8 //SDCLK Frequency Div, 0x00 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规ï¼é”Ÿï¿½ 0x01 2é—è·¨å–é‹å©šå¹é‘筋暥 0x02 4é—è·¨å–é‹å©šå¹é‘筋暥 0x04 8é—è·¨å–é‹å©šå¹é‘筋暥 0x08 16é—è·¨å–é‹å©šå¹é‘筋暥 ... 0x80 256é—è·¨å–é‹å©šå¹é‘筋暥 +#define SDIO_CR2_SDCLKDIV_Msk (0xFF << SDIO_CR2_SDCLKDIV_Pos) +#define SDIO_CR2_TIMEOUT_Pos 16 //0000 TMCLK*2^13 +#define SDIO_CR2_TIMEOUT_Msk (0x0F << SDIO_CR2_TIMEOUT_Pos) +#define SDIO_CR2_RSTALL_Pos 24 //Software Reset for All +#define SDIO_CR2_RSTALL_Msk (0x01 << SDIO_CR2_RSTALL_Pos) +#define SDIO_CR2_RSTCMD_Pos 25 //Software Reset for CMD Line +#define SDIO_CR2_RSTCMD_Msk (0x01 << SDIO_CR2_RSTCMD_Pos) +#define SDIO_CR2_RSTDAT_Pos 26 //Software Reset for DAT Line +#define SDIO_CR2_RSTDAT_Msk (0x01 << SDIO_CR2_RSTDAT_Pos) + +#define SDIO_IF_CMDDONE_Pos 0 +#define SDIO_IF_CMDDONE_Msk (0x01 << SDIO_IF_CMDDONE_Pos) +#define SDIO_IF_TRXDONE_Pos 1 +#define SDIO_IF_TRXDONE_Msk (0x01 << SDIO_IF_TRXDONE_Pos) +#define SDIO_IF_BLKGAP_Pos 2 +#define SDIO_IF_BLKGAP_Msk (0x01 << SDIO_IF_BLKGAP_Pos) +#define SDIO_IF_DMADONE_Pos 3 +#define SDIO_IF_DMADONE_Msk (0x01 << SDIO_IF_DMADONE_Pos) +#define SDIO_IF_BUFWRRDY_Pos 4 +#define SDIO_IF_BUFWRRDY_Msk (0x01 << SDIO_IF_BUFWRRDY_Pos) +#define SDIO_IF_BUFRDRDY_Pos 5 +#define SDIO_IF_BUFRDRDY_Msk (0x01 << SDIO_IF_BUFRDRDY_Pos) +#define SDIO_IF_CARDINSR_Pos 6 +#define SDIO_IF_CARDINSR_Msk (0x01 << SDIO_IF_CARDINSR_Pos) +#define SDIO_IF_CARDRMOV_Pos 7 +#define SDIO_IF_CARDRMOV_Msk (0x01 << SDIO_IF_CARDRMOV_Pos) +#define SDIO_IF_CARD_Pos 8 +#define SDIO_IF_CARD_Msk (0x01 << SDIO_IF_CARD_Pos) +#define SDIO_IF_ERROR_Pos 15 +#define SDIO_IF_ERROR_Msk (0x01 << SDIO_IF_ERROR_Pos) +#define SDIO_IF_CMDTIMEOUT_Pos 16 +#define SDIO_IF_CMDTIMEOUT_Msk (0x01 << SDIO_IF_CMDTIMEOUT_Pos) +#define SDIO_IF_CMDCRCERR_Pos 17 +#define SDIO_IF_CMDCRCERR_Msk (0x01 << SDIO_IF_CMDCRCERR_Pos) +#define SDIO_IF_CMDENDERR_Pos 18 +#define SDIO_IF_CMDENDERR_Msk (0x01 << SDIO_IF_CMDENDCERR_Pos) +#define SDIO_IF_CMDIDXERR_Pos 19 +#define SDIO_IF_CMDIDXERR_Msk (0x01 << SDIO_IF_CMDIDXCERR_Pos) +#define SDIO_IF_DATTIMEOUT_Pos 20 +#define SDIO_IF_DATTIMEOUT_Msk (0x01 << SDIO_IF_DATTIMEOUT_Pos) +#define SDIO_IF_DATCRCERR_Pos 21 +#define SDIO_IF_DATCRCERR_Msk (0x01 << SDIO_IF_DATCRCERR_Pos) +#define SDIO_IF_DATENDERR_Pos 22 +#define SDIO_IF_DATENDERR_Msk (0x01 << SDIO_IF_DATENDCERR_Pos) +#define SDIO_IF_CURLIMERR_Pos 23 +#define SDIO_IF_CURLIMERR_Msk (0x01 << SDIO_IF_CURLIMERR_Pos) +#define SDIO_IF_CMD12ERR_Pos 24 +#define SDIO_IF_CMD12ERR_Msk (0x01 << SDIO_IF_CMD12ERR_Pos) +#define SDIO_IF_DMAERR_Pos 25 +#define SDIO_IF_DMAERR_Msk (0x01 << SDIO_IF_DMAERR_Pos) +#define SDIO_IF_RESPERR_Pos 28 +#define SDIO_IF_RESPERR_Msk (0x01 << SDIO_IF_RESPERR_Pos) + +#define SDIO_IE_CMDDONE_Pos 0 //Command Complete Status Enable +#define SDIO_IE_CMDDONE_Msk (0x01 << SDIO_IE_CMDDONE_Pos) +#define SDIO_IE_TRXDONE_Pos 1 //Transfer Complete Status Enable +#define SDIO_IE_TRXDONE_Msk (0x01 << SDIO_IE_TRXDONE_Pos) +#define SDIO_IE_BLKGAP_Pos 2 //Block Gap Event Status Enable +#define SDIO_IE_BLKGAP_Msk (0x01 << SDIO_IE_BLKGAP_Pos) +#define SDIO_IE_DMADONE_Pos 3 //DMA Interrupt Status Enable +#define SDIO_IE_DMADONE_Msk (0x01 << SDIO_IE_DMADONE_Pos) +#define SDIO_IE_BUFWRRDY_Pos 4 //Buffer Write Ready Status Enable +#define SDIO_IE_BUFWRRDY_Msk (0x01 << SDIO_IE_BUFWRRDY_Pos) +#define SDIO_IE_BUFRDRDY_Pos 5 //Buffer Read Ready Status Enable +#define SDIO_IE_BUFRDRDY_Msk (0x01 << SDIO_IE_BUFRDRDY_Pos) +#define SDIO_IE_CARDINSR_Pos 6 //Card Insertion Status Enable +#define SDIO_IE_CARDINSR_Msk (0x01 << SDIO_IE_CARDINSR_Pos) +#define SDIO_IE_CARDRMOV_Pos 7 //Card Removal Status Enable +#define SDIO_IE_CARDRMOV_Msk (0x01 << SDIO_IE_CARDRMOV_Pos) +#define SDIO_IE_CARD_Pos 8 +#define SDIO_IE_CARD_Msk (0x01 << SDIO_IE_CARD_Pos) +#define SDIO_IE_CMDTIMEOUT_Pos 16 //Command Timeout Error Status Enable +#define SDIO_IE_CMDTIMEOUT_Msk (0x01 << SDIO_IE_CMDTIMEOUT_Pos) +#define SDIO_IE_CMDCRCERR_Pos 17 //Command CRC Error Status Enable +#define SDIO_IE_CMDCRCERR_Msk (0x01 << SDIO_IE_CMDCRCERR_Pos) +#define SDIO_IE_CMDENDERR_Pos 18 //Command End Bit Error Status Enable +#define SDIO_IE_CMDENDERR_Msk (0x01 << SDIO_IE_CMDENDCERR_Pos) +#define SDIO_IE_CMDIDXERR_Pos 19 //Command Index Error Status Enable +#define SDIO_IE_CMDIDXERR_Msk (0x01 << SDIO_IE_CMDIDXCERR_Pos) +#define SDIO_IE_DATTIMEOUT_Pos 20 //Data Timeout Error Status Enable +#define SDIO_IE_DATTIMEOUT_Msk (0x01 << SDIO_IE_DATTIMEOUT_Pos) +#define SDIO_IE_DATCRCERR_Pos 21 //Data CRC Error Status Enable +#define SDIO_IE_DATCRCERR_Msk (0x01 << SDIO_IE_DATCRCERR_Pos) +#define SDIO_IE_DATENDERR_Pos 22 //Data End Bit Error Status Enable +#define SDIO_IE_DATENDERR_Msk (0x01 << SDIO_IE_DATENDCERR_Pos) +#define SDIO_IE_CURLIMERR_Pos 23 //Current Limit Error Status Enable +#define SDIO_IE_CURLIMERR_Msk (0x01 << SDIO_IE_CURLIMERR_Pos) +#define SDIO_IE_CMD12ERR_Pos 24 //Auto CMD12 Error Status Enable +#define SDIO_IE_CMD12ERR_Msk (0x01 << SDIO_IE_CMD12ERR_Pos) +#define SDIO_IE_DMAERR_Pos 25 //ADMA Error Status Enable +#define SDIO_IE_DMAERR_Msk (0x01 << SDIO_IE_DMAERR_Pos) +#define SDIO_IE_RESPERR_Pos 28 //Target Response Error Status Enable +#define SDIO_IE_RESPERR_Msk (0x01 << SDIO_IE_RESPERR_Pos) + +#define SDIO_IM_CMDDONE_Pos 0 +#define SDIO_IM_CMDDONE_Msk (0x01 << SDIO_IM_CMDDONE_Pos) +#define SDIO_IM_TRXDONE_Pos 1 +#define SDIO_IM_TRXDONE_Msk (0x01 << SDIO_IM_TRXDONE_Pos) +#define SDIO_IM_BLKGAP_Pos 2 +#define SDIO_IM_BLKGAP_Msk (0x01 << SDIO_IM_BLKGAP_Pos) +#define SDIO_IM_DMADONE_Pos 3 +#define SDIO_IM_DMADONE_Msk (0x01 << SDIO_IM_DMADONE_Pos) +#define SDIO_IM_BUFWRRDY_Pos 4 +#define SDIO_IM_BUFWRRDY_Msk (0x01 << SDIO_IM_BUFWRRDY_Pos) +#define SDIO_IM_BUFRDRDY_Pos 5 +#define SDIO_IM_BUFRDRDY_Msk (0x01 << SDIO_IM_BUFRDRDY_Pos) +#define SDIO_IM_CARDINSR_Pos 6 +#define SDIO_IM_CARDINSR_Msk (0x01 << SDIO_IM_CARDINSR_Pos) +#define SDIO_IM_CARDRMOV_Pos 7 +#define SDIO_IM_CARDRMOV_Msk (0x01 << SDIO_IM_CARDRMOV_Pos) +#define SDIO_IM_CARD_Pos 8 +#define SDIO_IM_CARD_Msk (0x01 << SDIO_IM_CARD_Pos) +#define SDIO_IM_CMDTIMEOUT_Pos 16 +#define SDIO_IM_CMDTIMEOUT_Msk (0x01 << SDIO_IM_CMDTIMEOUT_Pos) +#define SDIO_IM_CMDCRCERR_Pos 17 +#define SDIO_IM_CMDCRCERR_Msk (0x01 << SDIO_IM_CMDCRCERR_Pos) +#define SDIO_IM_CMDENDERR_Pos 18 +#define SDIO_IM_CMDENDERR_Msk (0x01 << SDIO_IM_CMDENDCERR_Pos) +#define SDIO_IM_CMDIDXERR_Pos 19 +#define SDIO_IM_CMDIDXERR_Msk (0x01 << SDIO_IM_CMDIDXCERR_Pos) +#define SDIO_IM_DATTIMEOUT_Pos 20 +#define SDIO_IM_DATTIMEOUT_Msk (0x01 << SDIO_IM_DATTIMEOUT_Pos) +#define SDIO_IM_DATCRCERR_Pos 21 +#define SDIO_IM_DATCRCERR_Msk (0x01 << SDIO_IM_DATCRCERR_Pos) +#define SDIO_IM_DATENDERR_Pos 22 +#define SDIO_IM_DATENDERR_Msk (0x01 << SDIO_IM_DATENDCERR_Pos) +#define SDIO_IM_CURLIMERR_Pos 23 +#define SDIO_IM_CURLIMERR_Msk (0x01 << SDIO_IM_CURLIMERR_Pos) +#define SDIO_IM_CMD12ERR_Pos 24 +#define SDIO_IM_CMD12ERR_Msk (0x01 << SDIO_IM_CMD12ERR_Pos) +#define SDIO_IM_DMAERR_Pos 25 +#define SDIO_IM_DMAERR_Msk (0x01 << SDIO_IM_DMAERR_Pos) +#define SDIO_IM_RESPERR_Pos 28 +#define SDIO_IM_RESPERR_Msk (0x01 << SDIO_IM_RESPERR_Pos) + +typedef struct +{ + __IO uint32_t DATA; + __IO uint32_t ADDR; + __IO uint32_t ERASE; + __IO uint32_t CACHE; + __IO uint32_t CFG0; + __IO uint32_t CFG1; + __IO uint32_t CFG2; + __IO uint32_t CFG3; + __IO uint32_t STAT; +} FLASH_Typedef; + +#define FLASH_ERASE_REQ_Pos 31 +#define FLASH_ERASE_REQ_Msk ((uint32_t)0x01 << FLASH_ERASE_REQ_Pos) + +#define FLASH_CACHE_PROG_Pos 2 +#define FLASH_CACHE_PROG_Msk (0x01 << FLASH_CACHE_PROG_Pos) +#define FLASH_CACHE_CLEAR_Pos 3 +#define FLASH_CACHE_CLEAR_Msk (0x01 << FLASH_CACHE_CLEAR_Pos) + +#define FLASH_STAT_ERASE_GOING_Pos 0 +#define FLASH_STAT_ERASE_GOING_Msk (0X01 << FLASH_STAT_ERASE_GOING_Pos) +#define FLASH_STAT_PROG_GOING_Pos 1 +#define FLASH_STAT_PROG_GOING_Msk (0x01 << FLASH_STAT_PROG_GOING_Pos) +#define FALSH_STAT_FIFO_EMPTY_Pos 3 +#define FLASH_STAT_FIFO_EMPTY_Msk (0x01 << FALSH_STAT_FIFO_EMPTY_Pos) +#define FALSH_STAT_FIFO_FULL_Pos 4 +#define FLASH_STAT_FIFO_FULL_Msk (0x01 << FALSH_STAT_FIFO_FULL_Pos) + +typedef struct +{ + __IO uint32_t CR; +} SRAMC_TypeDef; + +#define SRAMC_CR_RWTIME_Pos 0 //é—è·¨å–é‹å©šå¹å®„æ¿æ™¸é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閸旑åŠå¨¼å©šå¹é–¿å¬«î˜§é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”诲Î閳藉æ‡ç€šï¿½0é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›1é—è·¨å–é‹å©šå¹é–¿å¬«î˜§é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”诲Î閳藉æ‡ç€šå½’柨é”å‘Šç®é–¹å³°å˜²é¨î„„柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶å¨‘æ“„æ‹·4 +#define SRAMC_CR_RWTIME_Msk (0x0F << SRAMC_CR_RWTIME_Pos) +#define SRAMC_CR_BYTEIF_Pos 4 //é—跨喕袙é—å¨RAMé—è·¨å–é‹å©šå¹é‘芥晸閹瑰嘲çå‘´å¹é‘ç•Œä¼é—跨噦鎷�0 16娴ï½æ‹· 1 8娴ï½æ‹· +#define SRAMC_CR_BYTEIF_Msk (0x01 << SRAMC_CR_BYTEIF_Pos) +#define SRAMC_CR_HBLBDIS_Pos 5 //1 ADDR[23:22]娑撴椽é撻弬銈嗗î¶é–¸Ñ€å“é—è·¨å–é‹å©šå¹é”Ÿï¿½ 0 ADDR[23]娑撴椽é撻弬銈嗗î¶é—跨喕顢滈弬銈嗗î¶å¨´ï½…潡é撻弶甯秶閹风DDR[22]娑撴椽é撻弬銈嗗î¶é—跨喕顢滈弬銈嗗î¶å¨´ï½…潡éæ’»å¼¬éŠˆå——î¶ +#define SRAMC_CR_HBLBDIS_Msk (0x01 << SRAMC_CR_HBLBDIS_Pos) + +typedef struct +{ + __IO uint32_t CR0; + + __IO uint32_t CR1; + + __IO uint32_t REFRESH; + + __IO uint32_t NOPNUM; //[15:0] é—è·¨å–é‹å©šå¹å®„邦潗é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归悵濠囨晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”活敎椤旂å›æ´æ»ˆå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±æ¿®å›¬æŸ¨é”å‘Šç®é–¹ç–¯æ¸¹ç»»åº¨æŸ¨é”虹ガOPé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� + + __IO uint32_t LATCH; + + __IO uint32_t REFDONE; //[0] Frefresh Doneé—è·¨å–é‹å©šå¹é‘芥晸é‰å å•°é¡£î‡€å¹é‘芥晸缂佺åŸéŠ†å¬®å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +} SDRAMC_TypeDef; + +#define SDRAMC_CR0_BURSTLEN_Pos 0 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归崣锟�2é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚圭粈绡塽rst Length娑擄拷4 +#define SDRAMC_CR0_BURSTLEN_Msk (0x07 << SDRAMC_CR0_BURSTLEN_Pos) +#define SDRAMC_CR0_CASDELAY_Pos 4 //CAS Latencyé—è·¨å–é‹å©šå¹é”Ÿï¿½ 2 2 3 3 +#define SDRAMC_CR0_CASDELAY_Msk (0x07 << SDRAMC_CR0_CASDELAY_Pos) + +#define SDRAMC_CR1_TRP_Pos 0 +#define SDRAMC_CR1_TRP_Msk (0x07 << SDRAMC_CR1_TRP_Pos) +#define SDRAMC_CR1_TRCD_Pos 3 +#define SDRAMC_CR1_TRCD_Msk (0x07 << SDRAMC_CR1_TRCD_Pos) +#define SDRAMC_CR1_TRC_Pos 6 +#define SDRAMC_CR1_TRC_Msk (0x0F << SDRAMC_CR1_TRC_Pos) +#define SDRAMC_CR1_TRAS_Pos 10 +#define SDRAMC_CR1_TRAS_Msk (0x07 << SDRAMC_CR1_TRAS_Pos) +#define SDRAMC_CR1_TRRD_Pos 13 +#define SDRAMC_CR1_TRRD_Msk (0x03 << SDRAMC_CR1_TRRD_Pos) +#define SDRAMC_CR1_TMRD_Pos 15 +#define SDRAMC_CR1_TMRD_Msk (0x07 << SDRAMC_CR1_TMRD_Pos) +#define SDRAMC_CR1_32BIT_Pos 18 //SDRAMCé—è·¨å–鑼庨幒銉ュ皡閹风兘é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œç§´é—è·¨å–é‹å©šå¹é”Ÿï¿½1 32bit 0 16bit +#define SDRAMC_CR1_32BIT_Msk (0x01 << SDRAMC_CR1_32BIT_Pos) +#define SDRAMC_CR1_BANK_Pos 19 //SDRAM濮ｅ繘é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”峰建绾攱瀚归柨é”å‘Šç®é–¹é£Žâ¿°anké—è·¨å–é‹å©šå¹é”Ÿï¿½0 2 banks 1 4 banks +#define SDRAMC_CR1_BANK_Msk (0x01 << SDRAMC_CR1_BANK_Pos) +#define SDRAMC_CR1_CELL32BIT_Pos 20 //SDRAMé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹ç–¯æ¸¹ç¼å‘´æŸ¨é”å‘Šç®é–¹å‡¤æ‹·1 32bit 0 16bit +#define SDRAMC_CR1_CELL32BIT_Msk (0x01 << SDRAMC_CR1_CELL32BIT_Pos) +#define SDRAMC_CR1_CELLSIZE_Pos 21 //SDRAMé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚�0 64Mb 1 128Mb 2 256Mb 3 16Mb +#define SDRAMC_CR1_CELLSIZE_Msk (0x03 << SDRAMC_CR1_CELLSIZE_Pos) +#define SDRAMC_CR1_HIGHSPEED_Pos 23 //é—è·¨å–é‹å©šå¹ç»Œæˆlké—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚�100MHz閺冨爼é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é“šå‚œî±å¨´ï½…秹é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹ç–¯æ¸¹ç’�1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹ç–¯æ¸¹ç’�0 +#define SDRAMC_CR1_HIGHSPEED_Msk (0x01 << SDRAMC_CR1_HIGHSPEED_Pos) + +#define SDRAMC_REFRESH_RATE_Pos 0 +#define SDRAMC_REFRESH_RATE_Msk (0xFFF << SDRAMC_REFRESH_RATE_Pos) +#define SDRAMC_REFRESH_EN_Pos 12 +#define SDRAMC_REFRESH_EN_Msk (0x01 << SDRAMC_REFRESH_EN_Pos) + +#define SDRAMC_LATCH_INEDGE_Pos 0 //é—è·¨å–鑼庨棃鈺傚î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喓ç»çŸ°RAMé—跨喎褰ㄧ拋瑙勫î¶é—è·¨å–é©å‘¯å–Šæ¾¶å¬ªî¶é—è·¨å–é‹å©šå¹é‘芥晸閹瑰嚖ç¼å›¬å¹é”Ÿï¿½0 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· 1 é—跨喖鎽îˆå¼¬éŠˆå——î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ +#define SDRAMC_LATCH_INEDGE_Msk (0x01 << SDRAMC_LATCH_INEDGE_Pos) +#define SDRAMC_LATCH_OUTEDGE_Pos 1 //é—è·¨å–鑼庨棃鈺傚î¶é—è·¨å–é‹å©šå¹å®„æ¿ç®µé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”ç…Žå¾é—‚堚晜瀚ç­DRAMé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿祹閿濆繑瀚�1 é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· 0 é—跨喖鎽îˆå¼¬éŠˆå——î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ +#define SDRAMC_LATCH_OUTEDGE_Msk (0x01 << SDRAMC_LATCH_OUTEDGE_Pos) +#define SDRAMC_LATCH_WAITST_Pos 2 +#define SDRAMC_LATCH_WAITST_Msk (0x01 << SDRAMC_LATCH_WAITST_Pos) + +typedef struct +{ + __IO uint32_t IE; + + __IO uint32_t IF; //閸愶拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� + + __IO uint32_t IM; + + __IO uint32_t CR; + + __IO uint32_t ADDR; + + __IO uint32_t CMD; +} NORFLC_TypeDef; + +#define NORFLC_IE_FINISH_Pos 0 +#define NORFLC_IE_FINISH_Msk (0x01 << NORFLC_IE_FINISH_Pos) +#define NORFLC_IE_TIMEOUT_Pos 1 +#define NORFLC_IE_TIMEOUT_Msk (0x01 << NORFLC_IE_TIMEOUT_Pos) + +#define NORFLC_IF_FINISH_Pos 0 +#define NORFLC_IF_FINISH_Msk (0x01 << NORFLC_IF_FINISH_Pos) +#define NORFLC_IF_TIMEOUT_Pos 1 +#define NORFLC_IF_TIMEOUT_Msk (0x01 << NORFLC_IF_TIMEOUT_Pos) + +#define NORFLC_IM_FINISH_Pos 0 +#define NORFLC_IM_FINISH_Msk (0x01 << NORFLC_IM_FINISH_Pos) +#define NORFLC_IM_TIMEOUT_Pos 1 +#define NORFLC_IM_TIMEOUT_Msk (0x01 << NORFLC_IM_TIMEOUT_Pos) + +#define NORFLC_CR_RDTIME_Pos 0 //Oené—跨喖鎽îˆå¼¬éŠˆå——î¶é—è·¨å–é©å‘´æ‚®ç€›æ¨ºî¶é—è·¨å–é‹å©šå¹é“šå‚œç®®é—跨喓绮æ幉瀣î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚圭拠銈夋晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é©å‘¯å–Šæ¾¶å¬ªî¶é—è·¨å–é‹å©šå¹é‘芥晸閹瑰çšå¦²å‹¯å¹é”Ÿï¿½0é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›1é—è·¨å–é‹å©šå¹é–¿å¬«î˜§é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define NORFLC_CR_RDTIME_Msk (0x1F << NORFLC_CR_RDTIME_Pos) +#define NORFLC_CR_WRTIME_Pos 5 //é—è·¨å–é‹å©šå¹é‘芥晸ç¼æ’穲né—è·¨å–鑼庢担æ´ï½Žæšœé–¹å³°å˜²é–½â•…柨é”å‘Šç®é–¹å³°å˜²è¤°å›¬æŸ¨é•å‚›å«¹0é—è·¨å–é‹å©šå¹æ¤‹åº›ä»›1é—è·¨å–é‹å©šå¹é–¿å¬«î˜§é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define NORFLC_CR_WRTIME_Msk (0x07 << NORFLC_CR_WRTIME_Pos) +#define NORFLC_CR_BYTEIF_Pos 8 //é—跨喕袙é—垷OR FLASHé—è·¨å–é‹å©šå¹é‘芥晸閹瑰嘲çå‘´å¹é‘ç•Œä¼é—跨噦鎷�1 8娴ï½æ‹· 0 16娴ï½æ‹· +#define NORFLC_CR_BYTEIF_Msk (0x01 << NORFLC_CR_BYTEIF_Pos) + +#define NORFLC_CMD_DATA_Pos 0 //é—è·¨å–é‹å©šå¹ç»‹ç™›OGRAMé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”峰建閿濆繑瀚笵ATAé—è·¨å–é‹å©šå¹é¤îˆ£æ´£é–¸æ„­ç‘©é撻弬銈嗗î¶NOR FLASHé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”稿祹閿濆繑瀚归柨é”å‘Šç®é–¹é£ŽÃºEADé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”峰建閿濆繑瀚笵ATAé—跨喕顫æ¥æ½éî„€î¶NOR FLASHé—è·¨å–é‹å©šå¹é‘芥晸閹æ­äºžé¡£î‡€å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define NORFLC_CMD_DATA_Msk (0xFFFF << NORFLC_CMD_DATA_Pos) +#define NORFLC_CMD_CMD_Pos 16 //é—è·¨å–é‹å©šå¹é¤îˆ£æ´£é–¹ç¬›å›¨æ™¸é–¸æ¬˜å†é¡£î‡€å¹é‘芥晸閺傘倖瀚归柨é”虹摂閿涳拷0 READ 1 RESET 2 AUTOMATIC SELECT 3 PROGRAM 4 CHIP ERASE 5 SECTOR ERASE +#define NORFLC_CMD_CMD_Msk (0x07 << NORFLC_CMD_CMD_Pos) + +typedef struct +{ + __IO uint32_t CR; + + __O uint32_t DATAIN; + + __IO uint32_t INIVAL; + + __I uint32_t RESULT; +} CRC_TypeDef; + +#define CRC_CR_EN_Pos 0 +#define CRC_CR_EN_Msk (0x01 << CRC_CR_EN_Pos) +#define CRC_CR_OREV_Pos 1 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撶憴鎺æˆæ®©é–¹é£ŽæŸ‰å¨´ï¿½ +#define CRC_CR_OREV_Msk (0x01 << CRC_CR_OREV_Pos) +#define CRC_CR_ONOT_Pos 2 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撶憴鎺æˆæ®©é–¹å³°å˜²è¤°å›¬æŸ¨é”å‘Šç®é–¹å‡¤æ‹· +#define CRC_CR_ONOT_Msk (0x01 << CRC_CR_ONOT_Pos) +#define CRC_CR_CRC16_Pos 3 //1 CRC16 0 CRC32 +#define CRC_CR_CRC16_Msk (0x01 << CRC_CR_CRC16_Pos) +#define CRC_CR_IBITS_Pos 4 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é–¿å¬«æ«å¨´ï½…秹éæ’»å¼¬éŠˆå——î¶ 0 32娴ï½æ‹· 1 16娴ï½æ‹· 2 8娴ï½æ‹· +#define CRC_CR_IBITS_Msk (0x03 << CRC_CR_IBITS_Pos) + +typedef struct +{ + __IO uint32_t MINSEC; //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻敓锟� + + __IO uint32_t DATHUR; //é—è·¨å–é‹å©šå¹é–¿å¬«î˜§é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� + + __IO uint32_t MONDAY; //é—è·¨å–é‹å©šå¹é‘芥晸閺夋壆銆嬮å¹é‘芥晸閺傘倖瀚� + + __IO uint32_t YEAR; //[11:0] é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撶悰妞﹀秵瀚归柨é•å‚›å«¹1901-2199 + + __IO uint32_t MINSECAL; //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� + + __IO uint32_t DAYHURAL; //é—è·¨å–é‹å©šå¹é–¿å¬«î˜§é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ + + __IO uint32_t LOAD; //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”虹å“éŽé›å«¯éŽ»îˆå¹é‘芥晸閺傘倖瀚归柨é”峰建绾æ¿î˜°ç€šå½’å´é“庢倱é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚筊TCé—跨喎褰ㄩæ•è¹‡æ–¿î¶é–¸æ°¬çŸ‚é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚规潻婊堟晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻敓锟� + + __IO uint32_t IE; + + __IO uint32_t IF; //閸愶拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� + + __IO uint32_t EN; //[0] 1 RTC娴ｅ潡éæ’»å¼¬éŠˆå——î¶ + + __IO uint32_t CFGABLE; //[0] 1 RTCé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· + + __IO uint32_t TRIM; //閺冨爼é撻幒銉ь暜閹风兘éæ’»å¼¬éŠˆå——î¶ + + __IO uint32_t TRIMM; //閺冨爼é撻弬銈嗗î¶ç€µé‚¦å™£é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ +} RTC_TypeDef; + +#define RTC_LOAD_TIME_Pos 0 +#define RTC_LOAD_TIME_Msk (0x01 << RTC_LOAD_TIME_Pos) +#define RTC_LOAD_ALARM_Pos 1 +#define RTC_LOAD_ALARM_Msk (0x01 << RTC_LOAD_ALARM_Pos) + +#define RTC_MINSEC_SEC_Pos 0 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é•å‚›å«¹ +#define RTC_MINSEC_SEC_Msk (0x3F << RTC_MINSEC_SEC_Pos) +#define RTC_MINSEC_MIN_Pos 6 //é—è·¨å–é‹å©šå¹é‘芥晸閹æ’儳銆嬮å¹é‘芥晸閺傘倖瀚� +#define RTC_MINSEC_MIN_Msk (0x3F << RTC_MINSEC_MIN_Pos) + +#define RTC_DATHUR_HOUR_Pos 0 //é忓繑妞傞柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define RTC_DATHUR_HOUR_Msk (0x1F << RTC_DATHUR_HOUR_Pos) +#define RTC_DATHUR_DATE_Pos 5 //date of month +#define RTC_DATHUR_DATE_Msk (0x1F << RTC_DATHUR_DATE_Pos) + +#define RTC_MONDAY_DAY_Pos 0 //day of week +#define RTC_MONDAY_DAY_Msk (0x07 << RTC_MONDAY_DAY_Pos) +#define RTC_MONDAY_MON_Pos 3 //é—跨喖鎽î…禒é£å±»â‚¬å¬®å¹é‘芥晸閺傘倖瀚� +#define RTC_MONDAY_MON_Msk (0x0F << RTC_MONDAY_MON_Pos) + +#define RTC_MINSECAL_SEC_Pos 0 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é”Ÿï¿½ +#define RTC_MINSECAL_SEC_Msk (0x3F << RTC_MINSECAL_SEC_Pos) +#define RTC_MINSECAL_MIN_Pos 6 //é—è·¨å–é‹å©šå¹é‘芥晸閹æ’儱é¤æ ­å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜éæ’»å¼¬éŠˆå——î¶ +#define RTC_MINSECAL_MIN_Msk (0x3F << RTC_MINSECAL_MIN_Pos) + +#define RTC_DAYHURAL_HOUR_Pos 0 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚圭亸蹇旀é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define RTC_DAYHURAL_HOUR_Msk (0x1F << RTC_DAYHURAL_HOUR_Pos) +#define RTC_DAYHURAL_SUN_Pos 5 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é–¿å¬«æ« +#define RTC_DAYHURAL_SUN_Msk (0x01 << RTC_DAYHURAL_SUN_Pos) +#define RTC_DAYHURAL_MON_Pos 6 //é—è·¨å–é‹å©šå¹é“šå‚œî±é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±é…� +#define RTC_DAYHURAL_MON_Msk (0x01 << RTC_DAYHURAL_MON_Pos) +#define RTC_DAYHURAL_TUE_Pos 7 //é—è·¨å–婢冪拋瑙勫î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹çƒ½æ”±é…� +#define RTC_DAYHURAL_TUE_Msk (0x01 << RTC_DAYHURAL_TUE_Pos) +#define RTC_DAYHURAL_WED_Pos 8 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é–¿å¬«æ« +#define RTC_DAYHURAL_WED_Msk (0x01 << RTC_DAYHURAL_WED_Pos) +#define RTC_DAYHURAL_THU_Pos 9 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é–¿å¬«æ« +#define RTC_DAYHURAL_THU_Msk (0x01 << RTC_DAYHURAL_THU_Pos) +#define RTC_DAYHURAL_FRI_Pos 10 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é–¿å¬«æ« +#define RTC_DAYHURAL_FRI_Msk (0x01 << RTC_DAYHURAL_FRI_Pos) +#define RTC_DAYHURAL_SAT_Pos 11 //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é–¿å¬«æ« +#define RTC_DAYHURAL_SAT_Msk (0x01 << RTC_DAYHURAL_SAT_Pos) + +#define RTC_IE_SEC_Pos 0 //é—è·¨å–é‹å©šå¹é‘芥晸閸欘å‰é¡”æ„°å¹é“šå‚šâ–é—è·¨å–é‹å©šå¹é”Ÿï¿½ +#define RTC_IE_SEC_Msk (0x01 << RTC_IE_SEC_Pos) +#define RTC_IE_MIN_Pos 1 +#define RTC_IE_MIN_Msk (0x01 << RTC_IE_MIN_Pos) +#define RTC_IE_HOUR_Pos 2 +#define RTC_IE_HOUR_Msk (0x01 << RTC_IE_HOUR_Pos) +#define RTC_IE_DATE_Pos 3 +#define RTC_IE_DATE_Msk (0x01 << RTC_IE_DATE_Pos) +#define RTC_IE_ALARM_Pos 4 +#define RTC_IE_ALARM_Msk (0x01 << RTC_IE_ALARM_Pos) + +#define RTC_IF_SEC_Pos 0 //閸愶拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚� +#define RTC_IF_SEC_Msk (0x01 << RTC_IF_SEC_Pos) +#define RTC_IF_MIN_Pos 1 +#define RTC_IF_MIN_Msk (0x01 << RTC_IF_MIN_Pos) +#define RTC_IF_HOUR_Pos 2 +#define RTC_IF_HOUR_Msk (0x01 << RTC_IF_HOUR_Pos) +#define RTC_IF_DATE_Pos 3 +#define RTC_IF_DATE_Msk (0x01 << RTC_IF_DATE_Pos) +#define RTC_IF_ALARM_Pos 4 +#define RTC_IF_ALARM_Msk (0x01 << RTC_IF_ALARM_Pos) + +#define RTC_TRIM_ADJ_Pos 0 //é—è·¨å–é‹å©šå¹é‘芥晸閼哄倻顣å¹é‘芥晸閺傘倖瀚笲ASECNTé—è·¨å–鑼庣涵閿嬪î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”诲Î閿濆繑瀚规姗€é撻弬銈嗗î¶å¨‘æ“„æ‹·32768é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”烘ãŸEC娑擄拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é¤îˆœæ¨é—è·¨å–é‹å©šå¹é‘芥晸é‰ç‚²å°…鎷�32768-ADJé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喕濞囬敓锟�32768+ADJ +#define RTC_TRIM_ADJ_Msk (0xFF << RTC_TRIM_ADJ_Pos) +#define RTC_TRIM_DEC_Pos 8 +#define RTC_TRIM_DEC_Msk (0x01 << RTC_TRIM_DEC_Pos) + +#define RTC_TRIMM_CYCLE_Pos 0 //é—è·¨å–é‹å©šå¹é‘芥晸閼哄倻銆嬮å¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶ç€µé‚¦å™£é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”虹イNC娑擄拷1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å“„å´Ÿé—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—跨喕濡喊澶嬪î¶é—è·¨å–é‹å©šå¹é“šå‚礋(32768é—è·¨å–é‹å©šå¹ç»‹çƒ¡J)+1,é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹é£Žå…˜é撴潪é–℃嫹(32768é—è·¨å–é‹å©šå¹ç»‹çƒ¡J)-1 +//cycles=0閺冨爼é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å³°å˜²æµœæ›¢æŸ¨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹ç»Œåª¦cles=1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚筺娑擄拷2é—è·¨å–é‹å©šå¹ç»Œåª¦cles=7é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚筺娑擄拷8é—è·¨å–é‹å©šå¹é‘芥晸閻ㄥ棜鎻îˆå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹· +#define RTC_TRIMM_CYCLE_Msk (0x07 << RTC_TRIMM_CYCLE_Pos) +#define RTC_TRIMM_INC_Pos 3 +#define RTC_TRIMM_INC_Msk (0x01 << RTC_TRIMM_INC_Pos) + +typedef struct +{ + __IO uint32_t LOAD; //閸犲倿é撻弬銈嗗î¶å¨´ï½…潡é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚圭憗é›å­˜æ™¸é–ºå‚˜å€–瀚ç­OADé–¸å©æ‹· + + __I uint32_t VALUE; + + __IO uint32_t CR; + + __IO uint32_t IF; //é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”å‘Šç®é–¹å‡¤æ‹·0閺冨墎鈥栭柨é”å‘Šç®é–¹é£Žå…˜é撻弬銈嗗î¶å¨´ï½…秹é撻弬銈嗗î¶é—è·¨å–é‹å©šå¹é‘芥晸閸欘å“鎷�1é—è·¨å–é‹å©šå¹é‘芥晸閺傘倖瀚归柨é”活敎閿燂拷 + + __IO uint32_t FEED; //閸愶拷0x55閸犲倿éæ’»å¼¬éŠˆå——î¶ +} WDT_TypeDef; + +#define WDT_CR_EN_Pos 0 +#define WDT_CR_EN_Msk (0x01 << WDT_CR_EN_Pos) +#define WDT_CR_RSTEN_Pos 1 +#define WDT_CR_RSTEN_Msk (0x01 << WDT_CR_RSTEN_Pos) + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +#define RAM_BASE 0x20000000 +#define AHB_BASE 0x40000000 +#define APB_BASE 0x40010000 + +#define NORFLC_BASE 0x60000000 +#define NORFLM_BASE 0x61000000 + +#define SRAMC_BASE 0x68000000 +#define SRAMM_BASE 0x69000000 + +#define SDRAMC_BASE 0x78000000 +#define SDRAMM_BASE 0x70000000 + +/* AHB Peripheral memory map */ +#define SYS_BASE (AHB_BASE + 0x00000) + +#define DMA_BASE (AHB_BASE + 0x01000) + +#define LCD_BASE (AHB_BASE + 0x02000) + +#define CRC_BASE (AHB_BASE + 0x03000) + +#define SDIO_BASE (AHB_BASE + 0x04000) + +/* APB Peripheral memory map */ +#define PORT_BASE (APB_BASE + 0x00000) + +#define GPIOA_BASE (APB_BASE + 0x01000) +#define GPIOB_BASE (APB_BASE + 0x02000) +#define GPIOC_BASE (APB_BASE + 0x03000) +#define GPIOD_BASE (APB_BASE + 0x04000) +#define GPIOM_BASE (APB_BASE + 0x05000) +#define GPION_BASE (APB_BASE + 0x06000) +#define GPIOP_BASE (APB_BASE + 0x08000) + +#define TIMR0_BASE (APB_BASE + 0x07000) +#define TIMR1_BASE (APB_BASE + 0x0700C) +#define TIMR2_BASE (APB_BASE + 0x07018) +#define TIMR3_BASE (APB_BASE + 0x07024) +#define TIMR4_BASE (APB_BASE + 0x07030) +#define TIMR5_BASE (APB_BASE + 0x0703C) +#define TIMRG_BASE (APB_BASE + 0x07060) + +#define WDT_BASE (APB_BASE + 0x09000) + +#define PWM0_BASE (APB_BASE + 0x0A000) +#define PWM1_BASE (APB_BASE + 0x0A020) +#define PWM2_BASE (APB_BASE + 0x0A040) +#define PWM3_BASE (APB_BASE + 0x0A060) +#define PWM4_BASE (APB_BASE + 0x0A080) +#define PWM5_BASE (APB_BASE + 0x0A0A0) +#define PWMG_BASE (APB_BASE + 0x0A180) + +#define RTC_BASE (APB_BASE + 0x0B000) + +#define ADC0_BASE (APB_BASE + 0x0C000) +#define ADC1_BASE (APB_BASE + 0x0D000) + +#define FLASH_BASE (APB_BASE + 0x0F000) + +#define UART0_BASE (APB_BASE + 0x10000) +#define UART1_BASE (APB_BASE + 0x11000) +#define UART2_BASE (APB_BASE + 0x12000) +#define UART3_BASE (APB_BASE + 0x13000) + +#define I2C0_BASE (APB_BASE + 0x18000) +#define I2C1_BASE (APB_BASE + 0x19000) + +#define SPI0_BASE (APB_BASE + 0x1C000) +#define SPI1_BASE (APB_BASE + 0x1D000) + +#define CAN_BASE (APB_BASE + 0x20000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define SYS ((SYS_TypeDef *)SYS_BASE) + +#define PORT ((PORT_TypeDef *)PORT_BASE) + +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOM ((GPIO_TypeDef *)GPIOM_BASE) +#define GPION ((GPIO_TypeDef *)GPION_BASE) +#define GPIOP ((GPIO_TypeDef *)GPIOP_BASE) + +#define TIMR0 ((TIMR_TypeDef *)TIMR0_BASE) +#define TIMR1 ((TIMR_TypeDef *)TIMR1_BASE) +#define TIMR2 ((TIMR_TypeDef *)TIMR2_BASE) +#define TIMR3 ((TIMR_TypeDef *)TIMR3_BASE) +#define TIMR4 ((TIMR_TypeDef *)TIMR4_BASE) +#define TIMR5 ((TIMR_TypeDef *)TIMR5_BASE) +#define TIMRG ((TIMRG_TypeDef *)TIMRG_BASE) + +#define UART0 ((UART_TypeDef *)UART0_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define UART3 ((UART_TypeDef *)UART3_BASE) + +#define SPI0 ((SPI_TypeDef *)SPI0_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) + +#define I2C0 ((I2C_TypeDef *)I2C0_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) + +#define ADC0 ((ADC_TypeDef *)ADC0_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) + +#define PWM0 ((PWM_TypeDef *)PWM0_BASE) +#define PWM1 ((PWM_TypeDef *)PWM1_BASE) +#define PWM2 ((PWM_TypeDef *)PWM2_BASE) +#define PWM3 ((PWM_TypeDef *)PWM3_BASE) +#define PWM4 ((PWM_TypeDef *)PWM4_BASE) +#define PWM5 ((PWM_TypeDef *)PWM5_BASE) +#define PWMG ((PWMG_TypeDef *)PWMG_BASE) + +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) + +#define DMA ((DMA_TypeDef *)DMA_BASE) + +#define CAN ((CAN_TypeDef *)CAN_BASE) + +#define LCD ((LCD_TypeDef *)LCD_BASE) + +#define CRC ((CRC_TypeDef *)CRC_BASE) + +#define RTC ((RTC_TypeDef *)RTC_BASE) + +#define WDT ((WDT_TypeDef *)WDT_BASE) + +#define FLASH ((FLASH_Typedef *)FLASH_BASE) + +#define SRAMC ((SRAMC_TypeDef *)SRAMC_BASE) + +#define NORFLC ((NORFLC_TypeDef *)NORFLC_BASE) + +#define SDRAMC ((SDRAMC_TypeDef *)SDRAMC_BASE) + +#include "SWM320_port.h" +#include "SWM320_gpio.h" +#include "SWM320_exti.h" +#include "SWM320_timr.h" +#include "SWM320_uart.h" +#include "SWM320_spi.h" +#include "SWM320_i2c.h" +#include "SWM320_pwm.h" +#include "SWM320_adc.h" +#include "SWM320_dma.h" +#include "SWM320_lcd.h" +#include "SWM320_can.h" +#include "SWM320_sdio.h" +#include "SWM320_flash.h" +#include "SWM320_norflash.h" +#include "SWM320_sdram.h" +#include "SWM320_crc.h" +#include "SWM320_rtc.h" +#include "SWM320_wdt.h" + +#endif //__SWM320_H__ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s new file mode 100644 index 0000000000..025782b081 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s @@ -0,0 +1,558 @@ +;****************************************************************************************************************************************** +; ÎļþÃû³Æ: startup_SWM2400.s +; ¹¦ÄÜ˵Ã÷: SWM2400µ¥Æ¬»úµÄÆô¶¯Îļþ +; ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +; ×¢ÒâÊÂÏî: +; °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +; Éý¼¶¼Ç¼: +; +; +;****************************************************************************************************************************************** +; @attention +; +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +; REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +; FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +; -ECTION WITH THEIR PRODUCTS. +; +; COPYRIGHT 2012 Synwit Technology +;****************************************************************************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD GPIOA0_Handler + DCD GPIOA1_Handler + DCD GPIOA2_Handler + DCD GPIOA3_Handler + DCD GPIOA4_Handler + DCD GPIOA5_Handler + DCD GPIOA6_Handler + DCD GPIOA7_Handler + DCD GPIOB0_Handler + DCD GPIOB1_Handler + DCD GPIOB2_Handler + DCD GPIOB3_Handler + DCD GPIOB4_Handler + DCD GPIOB5_Handler + DCD GPIOB6_Handler + DCD GPIOB7_Handler + DCD GPIOC0_Handler + DCD GPIOC1_Handler + DCD GPIOC2_Handler + DCD GPIOC3_Handler + DCD GPIOC4_Handler + DCD GPIOC5_Handler + DCD GPIOC6_Handler + DCD GPIOC7_Handler + DCD GPIOM0_Handler + DCD GPIOM1_Handler + DCD GPIOM2_Handler + DCD GPIOM3_Handler + DCD GPIOM4_Handler + DCD GPIOM5_Handler + DCD GPIOM6_Handler + DCD GPIOM7_Handler + DCD DMA_Handler + DCD LCD_Handler + DCD NORFLC_Handler + DCD CAN_Handler + DCD PULSE_Handler + DCD WDT_Handler + DCD PWM_Handler + DCD UART0_Handler + DCD UART1_Handler + DCD UART2_Handler + DCD UART3_Handler + DCD 0 + DCD I2C0_Handler + DCD I2C1_Handler + DCD SPI0_Handler + DCD ADC0_Handler + DCD RTC_Handler + DCD ANAC_Handler + DCD SDIO_Handler + DCD GPIOA_Handler + DCD GPIOB_Handler + DCD GPIOC_Handler + DCD GPIOM_Handler + DCD GPION_Handler + DCD GPIOP_Handler + DCD ADC1_Handler + DCD FPU_Handler + DCD SPI1_Handler + DCD TIMR0_Handler + DCD TIMR1_Handler + DCD TIMR2_Handler + DCD TIMR3_Handler + DCD TIMR4_Handler + DCD TIMR5_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + + + AREA |.text|, CODE, READONLY + + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +GPIOA0_Handler PROC + EXPORT GPIOA0_Handler [WEAK] + B . + ENDP + +GPIOA1_Handler PROC + EXPORT GPIOA1_Handler [WEAK] + B . + ENDP + +GPIOA2_Handler PROC + EXPORT GPIOA2_Handler [WEAK] + B . + ENDP + +GPIOA3_Handler PROC + EXPORT GPIOA3_Handler [WEAK] + B . + ENDP + +GPIOA4_Handler PROC + EXPORT GPIOA4_Handler [WEAK] + B . + ENDP + +GPIOA5_Handler PROC + EXPORT GPIOA5_Handler [WEAK] + B . + ENDP + +GPIOA6_Handler PROC + EXPORT GPIOA6_Handler [WEAK] + B . + ENDP + +GPIOA7_Handler PROC + EXPORT GPIOA7_Handler [WEAK] + B . + ENDP + +GPIOB0_Handler PROC + EXPORT GPIOB0_Handler [WEAK] + B . + ENDP + +GPIOB1_Handler PROC + EXPORT GPIOB1_Handler [WEAK] + B . + ENDP + +GPIOB2_Handler PROC + EXPORT GPIOB2_Handler [WEAK] + B . + ENDP + +GPIOB3_Handler PROC + EXPORT GPIOB3_Handler [WEAK] + B . + ENDP + +GPIOB4_Handler PROC + EXPORT GPIOB4_Handler [WEAK] + B . + ENDP + +GPIOB5_Handler PROC + EXPORT GPIOB5_Handler [WEAK] + B . + ENDP + +GPIOB6_Handler PROC + EXPORT GPIOB6_Handler [WEAK] + B . + ENDP + +GPIOB7_Handler PROC + EXPORT GPIOB7_Handler [WEAK] + B . + ENDP + +GPIOC0_Handler PROC + EXPORT GPIOC0_Handler [WEAK] + B . + ENDP + +GPIOC1_Handler PROC + EXPORT GPIOC1_Handler [WEAK] + B . + ENDP + +GPIOC2_Handler PROC + EXPORT GPIOC2_Handler [WEAK] + B . + ENDP + +GPIOC3_Handler PROC + EXPORT GPIOC3_Handler [WEAK] + B . + ENDP + +GPIOC4_Handler PROC + EXPORT GPIOC4_Handler [WEAK] + B . + ENDP + +GPIOC5_Handler PROC + EXPORT GPIOC5_Handler [WEAK] + B . + ENDP + +GPIOC6_Handler PROC + EXPORT GPIOC6_Handler [WEAK] + B . + ENDP + +GPIOC7_Handler PROC + EXPORT GPIOC7_Handler [WEAK] + B . + ENDP + +GPIOM0_Handler PROC + EXPORT GPIOM0_Handler [WEAK] + B . + ENDP + +GPIOM1_Handler PROC + EXPORT GPIOM1_Handler [WEAK] + B . + ENDP + +GPIOM2_Handler PROC + EXPORT GPIOM2_Handler [WEAK] + B . + ENDP + +GPIOM3_Handler PROC + EXPORT GPIOM3_Handler [WEAK] + B . + ENDP + +GPIOM4_Handler PROC + EXPORT GPIOM4_Handler [WEAK] + B . + ENDP + +GPIOM5_Handler PROC + EXPORT GPIOM5_Handler [WEAK] + B . + ENDP + +GPIOM6_Handler PROC + EXPORT GPIOM6_Handler [WEAK] + B . + ENDP + +GPIOM7_Handler PROC + EXPORT GPIOM7_Handler [WEAK] + B . + ENDP + +DMA_Handler PROC + EXPORT DMA_Handler [WEAK] + B . + ENDP + +LCD_Handler PROC + EXPORT LCD_Handler [WEAK] + B . + ENDP + +NORFLC_Handler PROC + EXPORT NORFLC_Handler [WEAK] + B . + ENDP + +CAN_Handler PROC + EXPORT CAN_Handler [WEAK] + B . + ENDP + +PULSE_Handler PROC + EXPORT PULSE_Handler [WEAK] + B . + ENDP + +WDT_Handler PROC + EXPORT WDT_Handler [WEAK] + B . + ENDP + +PWM_Handler PROC + EXPORT PWM_Handler [WEAK] + B . + ENDP + +UART0_Handler PROC + EXPORT UART0_Handler [WEAK] + B . + ENDP + +UART1_Handler PROC + EXPORT UART1_Handler [WEAK] + B . + ENDP + +UART2_Handler PROC + EXPORT UART2_Handler [WEAK] + B . + ENDP + +UART3_Handler PROC + EXPORT UART3_Handler [WEAK] + B . + ENDP + +I2C0_Handler PROC + EXPORT I2C0_Handler [WEAK] + B . + ENDP + +I2C1_Handler PROC + EXPORT I2C1_Handler [WEAK] + B . + ENDP + +SPI0_Handler PROC + EXPORT SPI0_Handler [WEAK] + B . + ENDP + +ADC0_Handler PROC + EXPORT ADC0_Handler [WEAK] + B . + ENDP + +RTC_Handler PROC + EXPORT RTC_Handler [WEAK] + B . + ENDP + +ANAC_Handler PROC + EXPORT ANAC_Handler [WEAK] + B . + ENDP + +SDIO_Handler PROC + EXPORT SDIO_Handler [WEAK] + B . + ENDP + +GPIOA_Handler PROC + EXPORT GPIOA_Handler [WEAK] + B . + ENDP + +GPIOB_Handler PROC + EXPORT GPIOB_Handler [WEAK] + B . + ENDP + +GPIOC_Handler PROC + EXPORT GPIOC_Handler [WEAK] + B . + ENDP + +GPIOM_Handler PROC + EXPORT GPIOM_Handler [WEAK] + B . + ENDP + +GPION_Handler PROC + EXPORT GPION_Handler [WEAK] + B . + ENDP + +GPIOP_Handler PROC + EXPORT GPIOP_Handler [WEAK] + B . + ENDP + +ADC1_Handler PROC + EXPORT ADC1_Handler [WEAK] + B . + ENDP + +FPU_Handler PROC + EXPORT FPU_Handler [WEAK] + B . + ENDP + +SPI1_Handler PROC + EXPORT SPI1_Handler [WEAK] + B . + ENDP + +TIMR0_Handler PROC + EXPORT TIMR0_Handler [WEAK] + B . + ENDP + +TIMR1_Handler PROC + EXPORT TIMR1_Handler [WEAK] + B . + ENDP + +TIMR2_Handler PROC + EXPORT TIMR2_Handler [WEAK] + B . + ENDP + +TIMR3_Handler PROC + EXPORT TIMR3_Handler [WEAK] + B . + ENDP + +TIMR4_Handler PROC + EXPORT TIMR4_Handler [WEAK] + B . + ENDP + +TIMR5_Handler PROC + EXPORT TIMR5_Handler [WEAK] + B . + ENDP + + ALIGN + + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s new file mode 100644 index 0000000000..c0bf32e04a --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s @@ -0,0 +1,406 @@ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the application's entry point.*/ + bl entry + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word GPIOA0_Handler + .word GPIOA1_Handler + .word GPIOA2_Handler + .word GPIOA3_Handler + .word GPIOA4_Handler + .word GPIOA5_Handler + .word GPIOA6_Handler + .word GPIOA7_Handler + .word GPIOB0_Handler + .word GPIOB1_Handler + .word GPIOB2_Handler + .word GPIOB3_Handler + .word GPIOB4_Handler + .word GPIOB5_Handler + .word GPIOB6_Handler + .word GPIOB7_Handler + .word GPIOC0_Handler + .word GPIOC1_Handler + .word GPIOC2_Handler + .word GPIOC3_Handler + .word GPIOC4_Handler + .word GPIOC5_Handler + .word GPIOC6_Handler + .word GPIOC7_Handler + .word GPIOM0_Handler + .word GPIOM1_Handler + .word GPIOM2_Handler + .word GPIOM3_Handler + .word GPIOM4_Handler + .word GPIOM5_Handler + .word GPIOM6_Handler + .word GPIOM7_Handler + .word DMA_Handler + .word LCD_Handler + .word NORFLC_Handler + .word CAN_Handler + .word PULSE_Handler + .word WDT_Handler + .word PWM_Handler + .word UART0_Handler + .word UART1_Handler + .word UART2_Handler + .word UART3_Handler + .word 0 + .word I2C0_Handler + .word I2C1_Handler + .word SPI0_Handler + .word ADC0_Handler + .word RTC_Handler + .word ANAC_Handler + .word SDIO_Handler + .word GPIOA_Handler + .word GPIOB_Handler + .word GPIOC_Handler + .word GPIOM_Handler + .word GPION_Handler + .word GPIOP_Handler + .word ADC1_Handler + .word FPU_Handler + .word SPI1_Handler + .word TIMR0_Handler + .word TIMR1_Handler + .word TIMR2_Handler + .word TIMR3_Handler + .word TIMR4_Handler + .word TIMR5_Handler +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak GPIOA0_Handler + .thumb_set GPIOA0_Handler,Default_Handler + + .weak GPIOA1_Handler + .thumb_set GPIOA1_Handler,Default_Handler + + .weak GPIOA2_Handler + .thumb_set GPIOA2_Handler,Default_Handler + + .weak GPIOA3_Handler + .thumb_set GPIOA3_Handler,Default_Handler + + .weak GPIOA4_Handler + .thumb_set GPIOA4_Handler,Default_Handler + + .weak GPIOA5_Handler + .thumb_set GPIOA5_Handler,Default_Handler + + .weak GPIOA6_Handler + .thumb_set GPIOA6_Handler,Default_Handler + + .weak GPIOA7_Handler + .thumb_set GPIOA7_Handler,Default_Handler + + .weak GPIOB0_Handler + .thumb_set GPIOB0_Handler,Default_Handler + + .weak GPIOB1_Handler + .thumb_set GPIOB1_Handler,Default_Handler + + .weak GPIOB2_Handler + .thumb_set GPIOB2_Handler,Default_Handler + + .weak GPIOB3_Handler + .thumb_set GPIOB3_Handler,Default_Handler + + .weak GPIOB4_Handler + .thumb_set GPIOB4_Handler,Default_Handler + + .weak GPIOB5_Handler + .thumb_set GPIOB5_Handler,Default_Handler + + .weak GPIOB6_Handler + .thumb_set GPIOB6_Handler,Default_Handler + + .weak GPIOB7_Handler + .thumb_set GPIOB7_Handler,Default_Handler + + .weak GPIOC0_Handler + .thumb_set GPIOC0_Handler,Default_Handler + + .weak GPIOC1_Handler + .thumb_set GPIOC1_Handler,Default_Handler + + .weak GPIOC2_Handler + .thumb_set GPIOC2_Handler,Default_Handler + + .weak GPIOC3_Handler + .thumb_set GPIOC3_Handler,Default_Handler + + .weak GPIOC4_Handler + .thumb_set GPIOC4_Handler,Default_Handler + + .weak GPIOC5_Handler + .thumb_set GPIOC5_Handler,Default_Handler + + .weak GPIOC6_Handler + .thumb_set GPIOC6_Handler,Default_Handler + + .weak GPIOC7_Handler + .thumb_set GPIOC7_Handler,Default_Handler + + .weak GPIOM0_Handler + .thumb_set GPIOM0_Handler,Default_Handler + + .weak GPIOM1_Handler + .thumb_set GPIOM1_Handler,Default_Handler + + .weak GPIOM2_Handler + .thumb_set GPIOM2_Handler,Default_Handler + + .weak GPIOM3_Handler + .thumb_set GPIOM3_Handler,Default_Handler + + .weak GPIOM4_Handler + .thumb_set GPIOM4_Handler,Default_Handler + + .weak GPIOM5_Handler + .thumb_set GPIOM5_Handler,Default_Handler + + .weak GPIOM6_Handler + .thumb_set GPIOM6_Handler,Default_Handler + + .weak GPIOM7_Handler + .thumb_set GPIOM7_Handler,Default_Handler + + .weak DMA_Handler + .thumb_set DMA_Handler,Default_Handler + + .weak LCD_Handler + .thumb_set LCD_Handler,Default_Handler + + .weak NORFLC_Handler + .thumb_set NORFLC_Handler,Default_Handler + + .weak CAN_Handler + .thumb_set CAN_Handler,Default_Handler + + .weak PULSE_Handler + .thumb_set PULSE_Handler,Default_Handler + + .weak WDT_Handler + .thumb_set WDT_Handler,Default_Handler + + .weak PWM_Handler + .thumb_set PWM_Handler,Default_Handler + + .weak UART0_Handler + .thumb_set UART0_Handler,Default_Handler + + .weak UART1_Handler + .thumb_set UART1_Handler,Default_Handler + + .weak UART2_Handler + .thumb_set UART2_Handler,Default_Handler + + .weak UART3_Handler + .thumb_set UART3_Handler,Default_Handler + + .weak I2C0_Handler + .thumb_set I2C0_Handler,Default_Handler + + .weak I2C1_Handler + .thumb_set I2C1_Handler,Default_Handler + + .weak SPI0_Handler + .thumb_set SPI0_Handler,Default_Handler + + .weak ADC0_Handler + .thumb_set ADC0_Handler,Default_Handler + + .weak RTC_Handler + .thumb_set RTC_Handler,Default_Handler + + .weak ANAC_Handler + .thumb_set ANAC_Handler,Default_Handler + + .weak SDIO_Handler + .thumb_set SDIO_Handler,Default_Handler + + .weak GPIOA_Handler + .thumb_set GPIOA_Handler,Default_Handler + + .weak GPIOB_Handler + .thumb_set GPIOB_Handler,Default_Handler + + .weak GPIOC_Handler + .thumb_set GPIOC_Handler,Default_Handler + + .weak GPIOM_Handler + .thumb_set GPIOM_Handler,Default_Handler + + .weak GPION_Handler + .thumb_set GPION_Handler,Default_Handler + + .weak GPIOP_Handler + .thumb_set GPIOP_Handler,Default_Handler + + .weak ADC1_Handler + .thumb_set ADC1_Handler,Default_Handler + + .weak FPU_Handler + .thumb_set FPU_Handler,Default_Handler + + .weak SPI1_Handler + .thumb_set SPI1_Handler,Default_Handler + + .weak TIMR0_Handler + .thumb_set TIMR0_Handler,Default_Handler + + .weak TIMR1_Handler + .thumb_set TIMR1_Handler,Default_Handler + + .weak TIMR2_Handler + .thumb_set TIMR2_Handler,Default_Handler + + .weak TIMR3_Handler + .thumb_set TIMR3_Handler,Default_Handler + + .weak TIMR4_Handler + .thumb_set TIMR4_Handler,Default_Handler + + .weak TIMR5_Handler + .thumb_set TIMR5_Handler,Default_Handler + diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s new file mode 100644 index 0000000000..baecc70d02 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s @@ -0,0 +1,464 @@ +;****************************************************************************************************************************************** +; 文件å称: startup_SWM2400.s +; 功能说明: SWM2400å•ç‰‡æœºçš„å¯åŠ¨æ–‡ä»¶ +; 技术支æŒ: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +; 注æ„事项: +; 版本日期: V1.0.0 2016å¹´1月30æ—¥ +; å‡çº§è®°å½•: +; +; +;****************************************************************************************************************************************** +; @attention +; +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +; REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +; FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +; -ECTION WITH THEIR PRODUCTS. +; +; COPYRIGHT 2012 Synwit Technology +;****************************************************************************************************************************************** + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD GPIOA0_Handler + DCD GPIOA1_Handler + DCD GPIOA2_Handler + DCD GPIOA3_Handler + DCD GPIOA4_Handler + DCD GPIOA5_Handler + DCD GPIOA6_Handler + DCD GPIOA7_Handler + DCD GPIOB0_Handler + DCD GPIOB1_Handler + DCD GPIOB2_Handler + DCD GPIOB3_Handler + DCD GPIOB4_Handler + DCD GPIOB5_Handler + DCD GPIOB6_Handler + DCD GPIOB7_Handler + DCD GPIOC0_Handler + DCD GPIOC1_Handler + DCD GPIOC2_Handler + DCD GPIOC3_Handler + DCD GPIOC4_Handler + DCD GPIOC5_Handler + DCD GPIOC6_Handler + DCD GPIOC7_Handler + DCD GPIOM0_Handler + DCD GPIOM1_Handler + DCD GPIOM2_Handler + DCD GPIOM3_Handler + DCD GPIOM4_Handler + DCD GPIOM5_Handler + DCD GPIOM6_Handler + DCD GPIOM7_Handler + DCD DMA_Handler + DCD LCD_Handler + DCD NORFLC_Handler + DCD CAN_Handler + DCD TIMR_Handler + DCD WDT_Handler + DCD PWM_Handler + DCD UART0_Handler + DCD UART1_Handler + DCD UART2_Handler + DCD UART3_Handler + DCD 0 + DCD I2C0_Handler + DCD I2C1_Handler + DCD SPI0_Handler + DCD ADC0_Handler + DCD RTC_Handler + DCD ANAC_Handler + DCD SDIO_Handler + DCD GPIOA_Handler + DCD GPIOB_Handler + DCD GPIOC_Handler + DCD GPIOM_Handler + DCD GPION_Handler + DCD GPIOP_Handler + DCD ADC1_Handler + DCD FPU_Handler + DCD SPI1_Handler + + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK GPIOA0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA0_Handler + B GPIOA0_Handler + + PUBWEAK GPIOA1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA1_Handler + B GPIOA1_Handler + + PUBWEAK GPIOA2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA2_Handler + B GPIOA2_Handler + + PUBWEAK GPIOA3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA3_Handler + B GPIOA3_Handler + + PUBWEAK GPIOA4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA4_Handler + B GPIOA4_Handler + + PUBWEAK GPIOA5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA5_Handler + B GPIOA5_Handler + + PUBWEAK GPIOA6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA6_Handler + B GPIOA6_Handler + + PUBWEAK GPIOA7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA7_Handler + B GPIOA7_Handler + + PUBWEAK GPIOB0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB0_Handler + B GPIOB0_Handler + + PUBWEAK GPIOB1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB1_Handler + B GPIOB1_Handler + + PUBWEAK GPIOB2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB2_Handler + B GPIOB2_Handler + + PUBWEAK GPIOB3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB3_Handler + B GPIOB3_Handler + + PUBWEAK GPIOB4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB4_Handler + B GPIOB4_Handler + + PUBWEAK GPIOB5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB5_Handler + B GPIOB5_Handler + + PUBWEAK GPIOB6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB6_Handler + B GPIOB6_Handler + + PUBWEAK GPIOB7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB7_Handler + B GPIOB7_Handler + + PUBWEAK GPIOC0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC0_Handler + B GPIOC0_Handler + + PUBWEAK GPIOC1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC1_Handler + B GPIOC1_Handler + + PUBWEAK GPIOC2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC2_Handler + B GPIOC2_Handler + + PUBWEAK GPIOC3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC3_Handler + B GPIOC3_Handler + + PUBWEAK GPIOC4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC4_Handler + B GPIOC4_Handler + + PUBWEAK GPIOC5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC5_Handler + B GPIOC5_Handler + + PUBWEAK GPIOC6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC6_Handler + B GPIOC6_Handler + + PUBWEAK GPIOC7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC7_Handler + B GPIOC7_Handler + + PUBWEAK GPIOM0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM0_Handler + B GPIOM0_Handler + + PUBWEAK GPIOM1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM1_Handler + B GPIOM1_Handler + + PUBWEAK GPIOM2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM2_Handler + B GPIOM2_Handler + + PUBWEAK GPIOM3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM3_Handler + B GPIOM3_Handler + + PUBWEAK GPIOM4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM4_Handler + B GPIOM4_Handler + + PUBWEAK GPIOM5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM5_Handler + B GPIOM5_Handler + + PUBWEAK GPIOM6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM6_Handler + B GPIOM6_Handler + + PUBWEAK GPIOM7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM7_Handler + B GPIOM7_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Handler + B DMA_Handler + + PUBWEAK LCD_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_Handler + B LCD_Handler + + PUBWEAK NORFLC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NORFLC_Handler + B NORFLC_Handler + + PUBWEAK CAN_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_Handler + B CAN_Handler + + PUBWEAK TIMR_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR_Handler + B TIMR_Handler + + PUBWEAK WDT_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT_Handler + B WDT_Handler + + PUBWEAK PWM_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM_Handler + B PWM_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK UART2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_Handler + B UART2_Handler + + PUBWEAK UART3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART3_Handler + B UART3_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK SPI0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI0_Handler + B SPI0_Handler + + PUBWEAK ADC0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_Handler + B ADC0_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Handler + B RTC_Handler + + PUBWEAK ANAC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ANAC_Handler + B ANAC_Handler + + PUBWEAK SDIO_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_Handler + B SDIO_Handler + + PUBWEAK GPIOA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA_Handler + B GPIOA_Handler + + PUBWEAK GPIOB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB_Handler + B GPIOB_Handler + + PUBWEAK GPIOC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC_Handler + B GPIOC_Handler + + PUBWEAK GPIOM_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM_Handler + B GPIOM_Handler + + PUBWEAK GPION_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPION_Handler + B GPION_Handler + + PUBWEAK GPIOP_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOP_Handler + B GPIOP_Handler + + PUBWEAK ADC1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_Handler + B ADC1_Handler + + PUBWEAK FPU_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_Handler + B FPU_Handler + + PUBWEAK SPI1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_Handler + B SPI1_Handler + + + END diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c new file mode 100644 index 0000000000..d6e7c61809 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c @@ -0,0 +1,215 @@ +/****************************************************************************************************************************************** +* 文件å称: system_SWM320.c +* 功能说明: SWM320å•ç‰‡æœºçš„时钟设置 +* 技术支æŒ: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注æ„事项: +* 版本日期: V1.1.0 2017å¹´10月25æ—¥ +* å‡çº§è®°å½•: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include +#include "SWM320.h" + +/****************************************************************************************************************************************** + * 系统时钟设定 + *****************************************************************************************************************************************/ +#define SYS_CLK_20MHz 0 //0 内部高频20MHz RC振è¡å™¨ +#define SYS_CLK_40MHz 1 //1 内部高频40MHz RC振è¡å™¨ +#define SYS_CLK_32KHz 2 //2 内部低频32KHz RC振è¡å™¨ +#define SYS_CLK_XTAL 3 //3 外部晶体振è¡å™¨ï¼ˆ2-30MHz） +#define SYS_CLK_PLL 4 //4 片内é”相环输出 + +#define SYS_CLK SYS_CLK_PLL + +#define SYS_CLK_DIV_1 0 +#define SYS_CLK_DIV_2 1 + +#define SYS_CLK_DIV SYS_CLK_DIV_1 + +#define __HSI (20000000UL) //高速内部时钟 +#define __LSI (32000UL) //低速内部时钟 +#define __HSE (20000000UL) //高速外部时钟 + +/********************************** PLL 设定 ********************************************** + * VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV + * PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV + *****************************************************************************************/ +#define SYS_PLL_SRC SYS_CLK_XTAL //å¯å–值SYS_CLK_20MHzã€SYS_CLK_XTAL + +#define PLL_IN_DIV 5 + +#define PLL_FB_DIV 60 + +#define PLL_OUT_DIV8 0 +#define PLL_OUT_DIV4 1 +#define PLL_OUT_DIV2 2 + +#define PLL_OUT_DIV PLL_OUT_DIV8 + +uint32_t SystemCoreClock = (120000000UL); //System Clock Frequency (Core Clock) +uint32_t CyclesPerUs = ((120000000UL) / 1000000); //Cycles per micro second + +/****************************************************************************************************************************************** +* 函数å称: +* 功能说明: This function is used to update the variable SystemCoreClock and must be called whenever the core clock is changed +* 输 å…¥: +* 输 出: +* 注æ„事项: +******************************************************************************************************************************************/ +void SystemCoreClockUpdate(void) +{ + if (SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) //SYS_CLK <= HFCK + { + if (SYS->CLKSEL & SYS_CLKSEL_HFCK_Msk) //HFCK <= XTAL + { + SystemCoreClock = __HSE; + } + else //HFCK <= HRC + { + if (SYS->HRCCR & SYS_HRCCR_DBL_Msk) //HRC = 40MHz + { + SystemCoreClock = __HSI * 2; + } + else //HRC = 20MHz + { + SystemCoreClock = __HSI; + } + } + } + else //SYS_CLK <= LFCK + { + if (SYS->CLKSEL & SYS_CLKSEL_LFCK_Msk) //LFCK <= PLL + { + if (SYS->PLLCR & SYS_PLLCR_INSEL_Msk) //PLL_SRC <= HRC + { + SystemCoreClock = __HSI; + } + else //PLL_SRC <= XTAL + { + SystemCoreClock = __HSE; + } + + SystemCoreClock = SystemCoreClock / PLL_IN_DIV * PLL_FB_DIV * 4 / (2 << (2 - PLL_OUT_DIV)); + } + else //LFCK <= LRC + { + SystemCoreClock = __LSI; + } + } + + if (SYS->CLKDIV & SYS_CLKDIV_SYS_Msk) + SystemCoreClock /= 2; +} + +/****************************************************************************************************************************************** +* 函数å称: +* 功能说明: The necessary initializaiton of systerm +* 输 å…¥: +* 输 出: +* 注æ„事项: +******************************************************************************************************************************************/ +void SystemInit(void) +{ + uint32_t i; + + SYS->CLKEN |= (1 << SYS_CLKEN_ANAC_Pos); + + switch (SYS_CLK) + { + case SYS_CLK_20MHz: //0 内部高频20MHz RC振è¡å™¨ + SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | + (0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz + + SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK + break; + + case SYS_CLK_40MHz: //1 内部高频40MHz RC振è¡å™¨ + SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | + (1 << SYS_HRCCR_DBL_Pos); //HRC = 40MHz + + SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK + break; + + case SYS_CLK_32KHz: //2 内部低频32KHz RC振è¡å™¨ + SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos); + + SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); + + for (i = 0; i < 20000; i++) + ; + + SYS->CLKSEL &= ~SYS_CLKSEL_LFCK_Msk; //LFCK <= LRC + SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK + break; + + case SYS_CLK_XTAL: //3 外部晶体振è¡å™¨ï¼ˆ2-30MHz） + SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos); + + for (i = 0; i < 20000; i++) + ; + + SYS->CLKSEL |= (1 << SYS_CLKSEL_HFCK_Pos); //HFCK <= XTAL + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK + break; + + case SYS_CLK_PLL: //4 片内é”相环输出 + PLLInit(); + SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos); + + SYS->CLKSEL |= (1 << SYS_CLKSEL_LFCK_Pos); //LFCK <= PLL + SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK + break; + } + + SYS->CLKDIV &= ~SYS_CLKDIV_SYS_Msk; + SYS->CLKDIV |= (SYS_CLK_DIV << SYS_CLKDIV_SYS_Pos); + + SystemCoreClockUpdate(); +} + +void PLLInit(void) +{ + uint32_t i; + + if (SYS_PLL_SRC == SYS_CLK_20MHz) + { + SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | + (0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz + + SYS->PLLCR |= (1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= HRC + } + else if (SYS_PLL_SRC == SYS_CLK_XTAL) + { + SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos); + + for (i = 0; i < 20000; i++) + ; + + SYS->PLLCR &= ~(1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= XTAL + } + + SYS->PLLDIV &= ~(SYS_PLLDIV_INDIV_Msk | + SYS_PLLDIV_FBDIV_Msk | + SYS_PLLDIV_OUTDIV_Msk); + SYS->PLLDIV |= (PLL_IN_DIV << SYS_PLLDIV_INDIV_Pos) | + (PLL_FB_DIV << SYS_PLLDIV_FBDIV_Pos) | + (PLL_OUT_DIV << SYS_PLLDIV_OUTDIV_Pos); + + SYS->PLLCR &= ~(1 << SYS_PLLCR_OFF_Pos); + + while (SYS->PLLLOCK == 0) + ; //等待PLLé”定 +} diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h new file mode 100644 index 0000000000..4f44ccd3ab --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h @@ -0,0 +1,24 @@ +#ifndef __SYSTEM_SWM320_H__ +#define __SYSTEM_SWM320_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern uint32_t CyclesPerUs; // Cycles per micro second + + +extern void SystemInit(void); + +extern void SystemCoreClockUpdate(void); + +extern void PLLInit(void); + + +#ifdef __cplusplus +} +#endif + +#endif //__SYSTEM_SWM320_H__ diff --git a/bsp/swm320-lq100/Libraries/SConscript b/bsp/swm320-lq100/Libraries/SConscript new file mode 100644 index 0000000000..d00266489b --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SConscript @@ -0,0 +1,18 @@ +from building import * +import rtconfig +cwd = GetCurrentDir() +src = Glob('CMSIS/DeviceSupport/*.c') +CPPPATH = [cwd + '/CMSIS/CoreSupport', cwd + '/CMSIS/DeviceSupport', cwd + '/SWM320_StdPeriph_Driver'] + +src += Glob('SWM320_StdPeriph_Driver/*.c') + +if rtconfig.CROSS_TOOL == 'gcc': + src += ['CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += ['CMSIS/DeviceSupport/startup/arm/startup_SWM320.s'] +elif rtconfig.CROSS_TOOL == 'iar': + print('Not Support iar now\n') + exit(0) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c new file mode 100644 index 0000000000..d6c48b10d4 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c @@ -0,0 +1,522 @@ +/****************************************************************************************************************************************** +* 文件å称: SWM320_adc.c +* 功能说明: SWM320å•ç‰‡æœºçš„ADC数模转æ¢å™¨åŠŸèƒ½é©±åŠ¨åº“ +* 技术支æŒ: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注æ„事项: +* 版本日期: V1.1.0 2017å¹´10月25æ—¥ +* å‡çº§è®°å½•: +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_adc.h" + +/****************************************************************************************************************************************** +* 函数å称: ADC_Init() +* 功能说明: ADC模数转æ¢å™¨åˆå§‹åŒ– +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，有效值包括ADC0ã€ADC1 +* ADC_InitStructure * initStruct 包å«ADCå„相关定值的结构体 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitStructure *initStruct) +{ + switch ((uint32_t)ADCx) + { + case ((uint32_t)ADC0): + SYS->CLKEN |= (0x01 << SYS_CLKEN_ADC0_Pos); + break; + + case ((uint32_t)ADC1): + SYS->CLKEN |= (0x01 << SYS_CLKEN_ADC1_Pos); + break; + } + + ADC_Close(ADCx); //一些关键寄存器åªèƒ½åœ¨ADC关闭时设置 + + if (initStruct->clk_src == ADC_CLKSRC_HRC) + { + ADCx->CTRL |= (1 << ADC_CTRL_CLKSRC_Pos); + + ADCx->CTRL2 &= ~ADC_CTRL2_CLKDIV_Msk; + ADCx->CTRL2 |= (initStruct->clk_div << ADC_CTRL2_CLKDIV_Pos); + } + else + { + if (SYS->PLLCR & SYS_PLLCR_OFF_Msk) + PLLInit(); + + ADCx->CTRL &= ~(1 << ADC_CTRL_CLKSRC_Pos); + + SYS->PLLDIV &= ~SYS_PLLDIV_ADVCO_Msk; + SYS->PLLDIV |= ((initStruct->clk_src - 2) << SYS_PLLDIV_ADVCO_Pos); + + SYS->PLLDIV &= ~SYS_PLLDIV_ADDIV_Msk; + SYS->PLLDIV |= (initStruct->clk_div << SYS_PLLDIV_ADDIV_Pos); + } + + ADCx->CTRL2 &= ~(ADC_CTRL2_ADCEVCM_Msk | ADC_CTRL2_PGAIVCM_Msk | ADC_CTRL2_PGAGAIN_Msk | ADC_CTRL2_PGAVCM_Msk); + ADCx->CTRL2 |= (0 << ADC_CTRL2_ADCEVCM_Pos) | + (PGA_VCM_INTERNAL << ADC_CTRL2_PGAIVCM_Pos) | + (6 << ADC_CTRL2_PGAGAIN_Pos) | + ((uint32_t)6 << ADC_CTRL2_PGAVCM_Pos); + + ADCx->CTRL &= ~(0xFF << ADC_CTRL_CH0_Pos); + ADCx->CTRL |= (initStruct->channels << ADC_CTRL_CH0_Pos); + + ADCx->CTRL &= ~(ADC_CTRL_AVG_Msk | ADC_CTRL_TRIG_Msk | ADC_CTRL_CONT_Msk); + ADCx->CTRL |= (initStruct->samplAvg << ADC_CTRL_AVG_Pos) | + (initStruct->trig_src << ADC_CTRL_TRIG_Pos) | + (initStruct->Continue << ADC_CTRL_CONT_Pos); + + ADCx->IF = 0xFFFFFFFF; //清除中断标志 + + ADCx->IE &= ~(ADC_IE_CH0EOC_Msk | ADC_IE_CH1EOC_Msk | ADC_IE_CH2EOC_Msk | ADC_IE_CH3EOC_Msk | + ADC_IE_CH4EOC_Msk | ADC_IE_CH5EOC_Msk | ADC_IE_CH6EOC_Msk | ADC_IE_CH7EOC_Msk); + ADCx->IE |= (((initStruct->EOC_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7EOC_Pos); + + ADCx->IE &= ~(ADC_IE_CH0OVF_Msk | ADC_IE_CH1OVF_Msk | ADC_IE_CH2OVF_Msk | ADC_IE_CH3OVF_Msk | + ADC_IE_CH4OVF_Msk | ADC_IE_CH5OVF_Msk | ADC_IE_CH6OVF_Msk | ADC_IE_CH7OVF_Msk); + ADCx->IE |= (((initStruct->OVF_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7OVF_Pos); + + ADCx->IE &= ~(ADC_IE_CH0HFULL_Msk | ADC_IE_CH1HFULL_Msk | ADC_IE_CH2HFULL_Msk | ADC_IE_CH3HFULL_Msk | + ADC_IE_CH4HFULL_Msk | ADC_IE_CH5HFULL_Msk | ADC_IE_CH6HFULL_Msk | ADC_IE_CH7HFULL_Msk); + ADCx->IE |= (((initStruct->HFULL_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7HFULL_Pos); + + ADCx->IE &= ~(uint32_t)(ADC_IE_CH0FULL_Msk | ADC_IE_CH1FULL_Msk | ADC_IE_CH2FULL_Msk | ADC_IE_CH3FULL_Msk | + ADC_IE_CH4FULL_Msk | ADC_IE_CH5FULL_Msk | ADC_IE_CH6FULL_Msk | ADC_IE_CH7FULL_Msk); + ADCx->IE |= (((initStruct->FULL_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7FULL_Pos); + + switch ((uint32_t)ADCx) + { + case ((uint32_t)ADC0): + if (initStruct->EOC_IEn | initStruct->OVF_IEn | initStruct->HFULL_IEn | initStruct->FULL_IEn) + { + NVIC_EnableIRQ(ADC0_IRQn); + } + else + { + NVIC_DisableIRQ(ADC0_IRQn); + } + break; + + case ((uint32_t)ADC1): + if (initStruct->EOC_IEn | initStruct->OVF_IEn | initStruct->HFULL_IEn | initStruct->FULL_IEn) + { + NVIC_EnableIRQ(ADC1_IRQn); + } + else + { + NVIC_DisableIRQ(ADC1_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_Open() +* 功能说明: ADCå¼€å¯ï¼Œå¯ä»¥è½¯ä»¶å¯åŠ¨ã€æˆ–硬件触å‘ADCè½¬æ¢ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_Open(ADC_TypeDef *ADCx) +{ + ADCx->CTRL |= (0x01 << ADC_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_Close() +* 功能说明: ADC关闭，无法软件å¯åŠ¨ã€æˆ–硬件触å‘ADCè½¬æ¢ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_Close(ADC_TypeDef *ADCx) +{ + ADCx->CTRL &= ~(0x01 << ADC_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_Start() +* 功能说明: 软件触å‘模å¼ä¸‹å¯åŠ¨ADCè½¬æ¢ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_Start(ADC_TypeDef *ADCx) +{ + ADCx->START |= (0x01 << ADC_START_GO_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_Stop() +* 功能说明: 软件触å‘模å¼ä¸‹åœæ­¢ADCè½¬æ¢ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_Stop(ADC_TypeDef *ADCx) +{ + ADCx->START &= ~(0x01 << ADC_START_GO_Pos); +} + +static uint32_t chn2idx(uint32_t chn) +{ + uint32_t idx = 0; + + switch (chn) + { + case 0x01: + idx = 0; + break; + case 0x02: + idx = 1; + break; + case 0x04: + idx = 2; + break; + case 0x08: + idx = 3; + break; + case 0x10: + idx = 4; + break; + case 0x20: + idx = 5; + break; + case 0x40: + idx = 6; + break; + case 0x80: + idx = 7; + break; + } + + return idx; +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_Read() +* 功能说明: 从指定通é“读å–转æ¢ç»“æžœ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦è¯»å–转æ¢ç»“果的通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: uint32_t 读å–到的转æ¢ç»“æžœ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t ADC_Read(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t dat = 0; + uint32_t idx = chn2idx(chn); + + dat = ADCx->CH[idx].DATA; + + ADCx->CH[idx].STAT = 0x01; //清除EOC标志 + + return dat; +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IsEOC() +* 功能说明: 指定通é“是å¦End Of Conversion +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦æŸ¥è¯¢çŠ¶æ€çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: uint32_t 1 该通é“完æˆäº†è½¬æ¢ 0 该通é“未完æˆè½¬æ¢ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t ADC_IsEOC(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->CH[idx].STAT & ADC_STAT_EOC_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_ChnSelect() +* 功能说明: ADC通é“选通，模数转æ¢ä¼šåœ¨é€‰é€šçš„通é“上ä¾æ¬¡é‡‡æ ·è½¬æ¢ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chns è¦é€‰é€šçš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7åŠå…¶ç»„åˆï¼ˆå³â€œæŒ‰ä½æˆ–â€è¿ç®—） +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_ChnSelect(ADC_TypeDef *ADCx, uint32_t chns) +{ + ADCx->CTRL &= ~(0xFF << ADC_CTRL_CH0_Pos); + ADCx->CTRL |= (chns << ADC_CTRL_CH0_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntEOCEn() +* 功能说明: 转æ¢å®Œæˆä¸­æ–­ä½¿èƒ½ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦è®¾ç½®çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_IntEOCEn(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE |= (0x01 << (idx * 4)); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntEOCDis() +* 功能说明: 转æ¢å®Œæˆä¸­æ–­ç¦æ­¢ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦è®¾ç½®çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_IntEOCDis(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE &= ~(0x01 << (idx * 4)); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntEOCClr() +* 功能说明: 转æ¢å®Œæˆä¸­æ–­æ ‡å¿—清除 +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦è®¾ç½®çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_IntEOCClr(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IF = (0x01 << (idx * 4)); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntEOCStat() +* 功能说明: 转æ¢å®Œæˆä¸­æ–­çŠ¶æ€ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦æŸ¥è¯¢çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: uint32_t 1 该通é“完æˆäº†è½¬æ¢ 0 该通é“未完æˆè½¬æ¢ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t ADC_IntEOCStat(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->IF & (0x01 << (idx * 4))) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntOVFEn() +* 功能说明: æ•°æ®æº¢å‡ºä¸­æ–­ä½¿èƒ½ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦è®¾ç½®çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_IntOVFEn(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE |= (0x01 << (idx * 4 + 1)); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntOVFDis() +* 功能说明: æ•°æ®æº¢å‡ºä¸­æ–­ç¦æ­¢ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦è®¾ç½®çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_IntOVFDis(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE &= ~(0x01 << (idx * 4 + 1)); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntOVFClr() +* 功能说明: æ•°æ®æº¢å‡ºä¸­æ–­æ ‡å¿—清除 +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦è®¾ç½®çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_IntOVFClr(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IF = (0x01 << (idx * 4 + 1)); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntOVFStat() +* 功能说明: æ•°æ®æº¢å‡ºä¸­æ–­çŠ¶æ€ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦æŸ¥è¯¢çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: uint32_t 1 该通é“完æˆäº†è½¬æ¢ 0 该通é“未完æˆè½¬æ¢ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t ADC_IntOVFStat(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->IF & (0x01 << (idx * 4 + 1))) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntHFULLEn() +* 功能说明: FIFOåŠæ»¡ä¸­æ–­ä½¿èƒ½ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦è®¾ç½®çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_IntHFULLEn(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE |= (0x01 << (idx * 4 + 2)); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntHFULLDis() +* 功能说明: FIFOåŠæ»¡ä¸­æ–­ç¦æ­¢ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦è®¾ç½®çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_IntHFULLDis(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE &= ~(0x01 << (idx * 4 + 2)); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntHFULLClr() +* 功能说明: FIFOåŠæ»¡ä¸­æ–­æ ‡å¿—清除 +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦è®¾ç½®çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_IntHFULLClr(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IF = (0x01 << (idx * 4 + 2)); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntHFULLStat() +* 功能说明: FIFOåŠæ»¡ä¸­æ–­çŠ¶æ€ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦æŸ¥è¯¢çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: uint32_t 1 该通é“完æˆäº†è½¬æ¢ 0 该通é“未完æˆè½¬æ¢ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t ADC_IntHFULLStat(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->IF & (0x01 << (idx * 4 + 2))) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntFULLEn() +* 功能说明: FIFO满中断使能 +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦è®¾ç½®çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_IntFULLEn(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE |= (0x01 << (idx * 4 + 3)); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntFULLDis() +* 功能说明: FIFO满中断ç¦æ­¢ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦è®¾ç½®çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_IntFULLDis(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE &= ~(0x01 << (idx * 4 + 3)); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntFULLClr() +* 功能说明: FIFO满中断标志清除 +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦è®¾ç½®çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void ADC_IntFULLClr(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IF = (0x01 << (idx * 4 + 3)); +} + +/****************************************************************************************************************************************** +* 函数å称: ADC_IntFULLStat() +* 功能说明: FIFOæ»¡ä¸­æ–­çŠ¶æ€ +* 输 å…¥: ADC_TypeDef * ADCx 指定è¦è¢«è®¾ç½®çš„ADC，å¯å–值包括ADC +* uint32_t chn è¦æŸ¥è¯¢çš„通é“，有效值ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7 +* 输 出: uint32_t 1 该通é“完æˆäº†è½¬æ¢ 0 该通é“未完æˆè½¬æ¢ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t ADC_IntFULLStat(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->IF & (0x01 << (idx * 4 + 3))) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h new file mode 100644 index 0000000000..b5906af908 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h @@ -0,0 +1,83 @@ +#ifndef __SWM320_ADC_H__ +#define __SWM320_ADC_H__ + +typedef struct +{ + uint8_t clk_src; //ADC转æ¢æ—¶é’Ÿæºï¼šADC_CLKSRC_HRCã€ADC_CLKSRC_VCO_DIV16ã€ADC_CLKSRC_VCO_DIV32ã€ADC_CLKSRC_VCO_DIV32 + uint8_t clk_div; //ADC转æ¢æ—¶é’Ÿåˆ†é¢‘，å–值1--31 + uint8_t channels; //ADC转æ¢é€šé“选中，ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7åŠå…¶ç»„åˆï¼ˆå³â€œæŒ‰ä½æˆ–â€è¿ç®—） + uint8_t samplAvg; //采样å–å¹³å‡ï¼Œè§¦å‘å¯åŠ¨ADC转æ¢åŽï¼ŒADC在一个通é“上连续采样ã€è½¬æ¢å¤šæ¬¡ï¼Œå¹¶å°†å®ƒä»¬çš„å¹³å‡å€¼ä½œä¸ºè¯¥é€šé“转æ¢ç»“æžœ + uint8_t trig_src; //ADC触å‘æ–¹å¼ï¼šADC_TRIGSRC_SWã€ADC_TRIGSRC_PWMã€ADC_TRIGSRC_TIMR2ã€ADC_TRIGSRC_TIMR3 + uint8_t Continue; //在软件触å‘模å¼ä¸‹ï¼š1 连续转æ¢æ¨¡å¼ï¼Œå¯åŠ¨åŽä¸€ç›´é‡‡æ ·ã€è½¬æ¢ï¼Œç›´åˆ°è½¯ä»¶æ¸…除STARTä½ + // 0 å•æ¬¡è½¬æ¢æ¨¡å¼ï¼Œè½¬æ¢å®ŒæˆåŽSTARTä½è‡ªåŠ¨æ¸…除åœæ­¢è½¬æ¢ + uint8_t EOC_IEn; //EOC中断使能，å¯é’ˆå¯¹æ¯ä¸ªé€šé“设置，其有效值为ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7åŠå…¶ç»„åˆï¼ˆå³â€œæŒ‰ä½æˆ–â€è¿ç®—） + uint8_t OVF_IEn; //OVF中断使能，å¯é’ˆå¯¹æ¯ä¸ªé€šé“设置，其有效值为ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7åŠå…¶ç»„åˆï¼ˆå³â€œæŒ‰ä½æˆ–â€è¿ç®—） + uint8_t HFULL_IEn; //FIFOåŠæ»¡ä¸­æ–­ä½¿èƒ½ï¼Œå¯é’ˆå¯¹æ¯ä¸ªé€šé“设置，其有效值为ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7åŠå…¶ç»„åˆï¼ˆå³â€œæŒ‰ä½æˆ–â€è¿ç®—） + uint8_t FULL_IEn; //FIFO 满中断使能，å¯é’ˆå¯¹æ¯ä¸ªé€šé“设置，其有效值为ADC_CH0ã€ADC_CH1ã€... ... ã€ADC_CH7åŠå…¶ç»„åˆï¼ˆå³â€œæŒ‰ä½æˆ–â€è¿ç®—） +} ADC_InitStructure; + +#define ADC_CH0 0x01 +#define ADC_CH1 0x02 +#define ADC_CH2 0x04 +#define ADC_CH3 0x08 +#define ADC_CH4 0x10 +#define ADC_CH5 0x20 +#define ADC_CH6 0x40 +#define ADC_CH7 0x80 + +#define ADC_CLKSRC_HRC 1 +#define ADC_CLKSRC_VCO_DIV16 2 +#define ADC_CLKSRC_VCO_DIV32 3 +#define ADC_CLKSRC_VCO_DIV64 4 + +#define ADC_AVG_SAMPLE1 0 +#define ADC_AVG_SAMPLE2 1 //一次å¯åŠ¨è¿žç»­é‡‡æ ·ã€è½¬æ¢2次，并计算两次结果的平å‡å€¼ä½œä¸ºè½¬æ¢ç»“æžœ +#define ADC_AVG_SAMPLE4 3 +#define ADC_AVG_SAMPLE8 7 +#define ADC_AVG_SAMPLE16 15 + +#define ADC_TRIGSRC_SW 0 //软件触å‘，å³ADC->START.GO写1å¯åŠ¨è½¬æ¢ +#define ADC_TRIGSRC_PWM 1 + +#define PGA_VCM_INTERNAL 1 //PGA输入共模电平由内部电路产生，ADC_REFPå’ŒADC_REFNå¯æ‚¬ç©º +#define PGA_VCM_EXTERNAL 0 //PGA输入共模电平由外部引脚æ供，(ADC_REFP + ADC_REFN) 电平值须与é‡ç¨‹ç›¸åŒ + +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitStructure *initStruct); //ADC模数转æ¢å™¨åˆå§‹åŒ– +void ADC_Open(ADC_TypeDef *ADCx); //ADCå¼€å¯ï¼Œå¯ä»¥è½¯ä»¶å¯åŠ¨ã€æˆ–硬件触å‘ADCè½¬æ¢ +void ADC_Close(ADC_TypeDef *ADCx); //ADC关闭，无法软件å¯åŠ¨ã€æˆ–硬件触å‘ADCè½¬æ¢ +void ADC_Start(ADC_TypeDef *ADCx); //å¯åŠ¨æŒ‡å®šADCï¼Œå¼€å§‹æ¨¡æ•°è½¬æ¢ +void ADC_Stop(ADC_TypeDef *ADCx); //关闭指定ADC，åœæ­¢æ¨¡æ•°è½¬æ¢ + +uint32_t ADC_Read(ADC_TypeDef *ADCx, uint32_t chn); //从指定通é“读å–转æ¢ç»“æžœ +uint32_t ADC_IsEOC(ADC_TypeDef *ADCx, uint32_t chn); //指定通é“是å¦End Of Conversion + +void ADC_ChnSelect(ADC_TypeDef *ADCx, uint32_t chns); + +void ADC_IntEOCEn(ADC_TypeDef *ADCx, uint32_t chn); //转æ¢å®Œæˆä¸­æ–­ä½¿èƒ½ +void ADC_IntEOCDis(ADC_TypeDef *ADCx, uint32_t chn); //转æ¢å®Œæˆä¸­æ–­ç¦æ­¢ +void ADC_IntEOCClr(ADC_TypeDef *ADCx, uint32_t chn); //转æ¢å®Œæˆä¸­æ–­æ ‡å¿—清除 +uint32_t ADC_IntEOCStat(ADC_TypeDef *ADCx, uint32_t chn); //转æ¢å®Œæˆä¸­æ–­çŠ¶æ€ + +void ADC_IntOVFEn(ADC_TypeDef *ADCx, uint32_t chn); //æ•°æ®æº¢å‡ºä¸­æ–­ä½¿èƒ½ +void ADC_IntOVFDis(ADC_TypeDef *ADCx, uint32_t chn); //æ•°æ®æº¢å‡ºä¸­æ–­ç¦æ­¢ +void ADC_IntOVFClr(ADC_TypeDef *ADCx, uint32_t chn); //æ•°æ®æº¢å‡ºä¸­æ–­æ ‡å¿—清除 +uint32_t ADC_IntOVFStat(ADC_TypeDef *ADCx, uint32_t chn); //æ•°æ®æº¢å‡ºä¸­æ–­çŠ¶æ€ + +void ADC_IntHFULLEn(ADC_TypeDef *ADCx, uint32_t chn); //FIFOåŠæ»¡ä¸­æ–­ä½¿èƒ½ +void ADC_IntHFULLDis(ADC_TypeDef *ADCx, uint32_t chn); //FIFOåŠæ»¡ä¸­æ–­ç¦æ­¢ +void ADC_IntHFULLClr(ADC_TypeDef *ADCx, uint32_t chn); //FIFOåŠæ»¡ä¸­æ–­æ ‡å¿—清除 +uint32_t ADC_IntHFULLStat(ADC_TypeDef *ADCx, uint32_t chn); //FIFOåŠæ»¡ä¸­æ–­çŠ¶æ€ + +void ADC_IntFULLEn(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断使能 +void ADC_IntFULLDis(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断ç¦æ­¢ +void ADC_IntFULLClr(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断标志清除 +uint32_t ADC_IntFULLStat(ADC_TypeDef *ADCx, uint32_t chn); //FIFOæ»¡ä¸­æ–­çŠ¶æ€ + +/* ADC 内部 1.2V REFP电压输出到外部REFP引脚，用于测é‡ï¼Œæˆ–在需è¦1.2V外部REFP时节çœæˆæœ¬ */ +#define ADC_TEST_INNER_REFP_OUT_EN(ADCx) (ADCx->CTRL3 |= (1 << ADC_CTRL3_REFP_OUT_Pos)) +#define ADC_TEST_INNER_REFP_OUT_DIS(ADCx) (ADCx->CTRL3 &= ~(1 << ADC_CTRL3_REFP_OUT_Pos)) + +#define ADC_TEST_ADC_PGA_EXT_VCM_EN(ADCx) (ADCx->CTRL3 |= (1 << ADC_CTRL3_EXTVCM_Pos)) +#define ADC_TEST_ADC_PGA_EXT_VCM_DIS(ADCx) (ADCx->CTRL3 &= ~(1 << ADC_CTRL3_EXTVCM_Pos)) + +#endif //__SWM320_ADC_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c new file mode 100644 index 0000000000..2f9a345b21 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c @@ -0,0 +1,687 @@ +/****************************************************************************************************************************************** +* 文件å称: SWM320_can.c +* 功能说明: SWM320å•ç‰‡æœºçš„CAN模å—驱动库 +* 技术支æŒ: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注æ„事项: +* 版本日期: V1.1.0 2017å¹´10月25æ—¥ +* å‡çº§è®°å½•: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_can.h" + +/****************************************************************************************************************************************** +* 函数å称: CAN_Init() +* 功能说明: CAN接å£åˆå§‹åŒ– +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* CAN_InitStructure * initStruct 包å«CAN接å£ç›¸å…³è®¾å®šå€¼çš„结构体 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_Init(CAN_TypeDef *CANx, CAN_InitStructure *initStruct) +{ + switch ((uint32_t)CANx) + { + case ((uint32_t)CAN): + SYS->CLKEN |= (0x01 << SYS_CLKEN_CAN_Pos); + break; + } + + CAN_Close(CANx); //一些关键寄存器åªèƒ½åœ¨CAN关闭时设置 + + CANx->CR &= ~(CAN_CR_LOM_Msk | CAN_CR_STM_Msk | CAN_CR_AFM_Msk); + CANx->CR |= (initStruct->Mode << CAN_CR_LOM_Pos) | + (initStruct->FilterMode << CAN_CR_AFM_Pos); + + CANx->FILTER.AMR[3] = initStruct->FilterMask32b & 0xFF; + CANx->FILTER.AMR[2] = (initStruct->FilterMask32b >> 8) & 0xFF; + CANx->FILTER.AMR[1] = (initStruct->FilterMask32b >> 16) & 0xFF; + CANx->FILTER.AMR[0] = (initStruct->FilterMask32b >> 24) & 0xFF; + + CANx->FILTER.ACR[3] = initStruct->FilterCheck32b & 0xFF; + CANx->FILTER.ACR[2] = (initStruct->FilterCheck32b >> 8) & 0xFF; + CANx->FILTER.ACR[1] = (initStruct->FilterCheck32b >> 16) & 0xFF; + CANx->FILTER.ACR[0] = (initStruct->FilterCheck32b >> 24) & 0xFF; + + CANx->BT1 = (0 << CAN_BT1_SAM_Pos) | + (initStruct->CAN_BS1 << CAN_BT1_TSEG1_Pos) | + (initStruct->CAN_BS2 << CAN_BT1_TSEG2_Pos); + + CANx->BT0 = (initStruct->CAN_SJW << CAN_BT0_SJW_Pos) | + ((SystemCoreClock / 2 / initStruct->Baudrate / (1 + (initStruct->CAN_BS1 + 1) + (initStruct->CAN_BS2 + 1)) - 1) << CAN_BT0_BRP_Pos); + + CANx->RXERR = 0; //åªèƒ½åœ¨å¤ä½æ¨¡å¼ä¸‹æ¸…除 + CANx->TXERR = 0; + + CANx->IE = (initStruct->RXNotEmptyIEn << CAN_IE_RXDA_Pos) | + (initStruct->RXOverflowIEn << CAN_IE_RXOV_Pos) | + (initStruct->ArbitrLostIEn << CAN_IE_ARBLOST_Pos) | + (initStruct->ErrPassiveIEn << CAN_IE_ERRPASS_Pos); + + switch ((uint32_t)CANx) + { + case ((uint32_t)CAN): + if (initStruct->RXNotEmptyIEn | initStruct->RXOverflowIEn | initStruct->ArbitrLostIEn | initStruct->ErrPassiveIEn) + { + NVIC_EnableIRQ(CAN_IRQn); + } + else + { + NVIC_DisableIRQ(CAN_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_Open() +* 功能说明: CAN接å£æ‰“å¼€ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_Open(CAN_TypeDef *CANx) +{ + CANx->CR &= ~(0x01 << CAN_CR_RST_Pos); //退出å¤ä½æ¨¡å¼ï¼Œè¿›å…¥å·¥ä½œæ¨¡å¼ +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_Close() +* 功能说明: CAN接å£å…³é—­ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_Close(CAN_TypeDef *CANx) +{ + CANx->CR |= (0x01 << CAN_CR_RST_Pos); //进入å¤ä½æ¨¡å¼ï¼Œä¸èƒ½å‘é€å’ŒæŽ¥æ”¶æ•°æ® +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_Transmit() +* 功能说明: CANå‘é€æ•°æ® +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* uint32_t format CAN_FRAME_STD 标准帧 CAN_FRAME_EXT 扩展帧 +* uint32_t id 消æ¯ID +* uint8_t data[] è¦å‘é€çš„æ•°æ® +* uint32_t size è¦å‘é€çš„æ•°æ®çš„个数 +* uint32_t once åªå‘é€ä¸€æ¬¡ï¼Œå³ä½¿å‘é€å¤±è´¥ï¼ˆä»²è£ä¸¢å¤±ã€å‘é€å‡ºé”™ã€NAK）也ä¸å°è¯•é‡å‘ +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_Transmit(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint8_t data[], uint32_t size, uint32_t once) +{ + uint32_t i; + + if (format == CAN_FRAME_STD) + { + CANx->TXFRAME.INFO = (0 << CAN_INFO_FF_Pos) | + (0 << CAN_INFO_RTR_Pos) | + (size << CAN_INFO_DLC_Pos); + + CANx->TXFRAME.DATA[0] = id >> 3; + CANx->TXFRAME.DATA[1] = id << 5; + + for (i = 0; i < size; i++) + { + CANx->TXFRAME.DATA[i + 2] = data[i]; + } + } + else //if(format == CAN_FRAME_EXT) + { + CANx->TXFRAME.INFO = (1 << CAN_INFO_FF_Pos) | + (0 << CAN_INFO_RTR_Pos) | + (size << CAN_INFO_DLC_Pos); + + CANx->TXFRAME.DATA[0] = id >> 21; + CANx->TXFRAME.DATA[1] = id >> 13; + CANx->TXFRAME.DATA[2] = id >> 5; + CANx->TXFRAME.DATA[3] = id << 3; + + for (i = 0; i < size; i++) + { + CANx->TXFRAME.DATA[i + 4] = data[i]; + } + } + + if (CANx->CR & CAN_CR_STM_Msk) + { + CANx->CMD = (1 << CAN_CMD_SRR_Pos); + } + else + { + if (once == 0) + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos); + } + else + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos) | (1 << CAN_CMD_ABTTX_Pos); + } + } +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_TransmitRequest() +* 功能说明: CANå‘é€è¿œç¨‹è¯·æ±‚，请求远程节点å‘é€æ•°æ® +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* uint32_t format CAN_FRAME_STD 标准帧 CAN_FRAME_EXT 扩展帧 +* uint32_t id 消æ¯ID +* uint32_t once åªå‘é€ä¸€æ¬¡ï¼Œå³ä½¿å‘é€å¤±è´¥ï¼ˆä»²è£ä¸¢å¤±ã€å‘é€å‡ºé”™ã€NAK）也ä¸å°è¯•é‡å‘ +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32_t once) +{ + if (format == CAN_FRAME_STD) + { + CANx->TXFRAME.INFO = (0 << CAN_INFO_FF_Pos) | + (1 << CAN_INFO_RTR_Pos) | + (0 << CAN_INFO_DLC_Pos); + + CANx->TXFRAME.DATA[0] = id >> 3; + CANx->TXFRAME.DATA[1] = id << 5; + } + else //if(format == CAN_FRAME_EXT) + { + CANx->TXFRAME.INFO = (1 << CAN_INFO_FF_Pos) | + (1 << CAN_INFO_RTR_Pos) | + (0 << CAN_INFO_DLC_Pos); + + CANx->TXFRAME.DATA[0] = id >> 21; + CANx->TXFRAME.DATA[1] = id >> 13; + CANx->TXFRAME.DATA[2] = id >> 5; + CANx->TXFRAME.DATA[3] = id << 3; + } + + if (once == 0) + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos); + } + else + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos) | (1 << CAN_CMD_ABTTX_Pos); + } +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_Receive() +* 功能说明: CANæŽ¥æ”¶æ•°æ® +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* CAN_RXMessage *msg 接收到的消æ¯å­˜å‚¨åœ¨æ­¤ç»“构体å˜é‡ä¸­ +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_Receive(CAN_TypeDef *CANx, CAN_RXMessage *msg) +{ + uint32_t i; + uint32_t format = (CANx->RXFRAME.INFO & CAN_INFO_FF_Msk) >> CAN_INFO_FF_Pos; + + msg->remote = (CANx->RXFRAME.INFO & CAN_INFO_RTR_Msk) >> CAN_INFO_RTR_Pos; + msg->size = (CANx->RXFRAME.INFO & CAN_INFO_DLC_Msk) >> CAN_INFO_DLC_Pos; + + if (format == CAN_FRAME_STD) + { + msg->id = (CANx->RXFRAME.DATA[0] << 3) | (CANx->RXFRAME.DATA[1] >> 5); + + for (i = 0; i < msg->size; i++) + { + msg->data[i] = CANx->RXFRAME.DATA[i + 2]; + } + } + else //if(format == CAN_FRAME_EXT) + { + msg->id = (CANx->RXFRAME.DATA[0] << 21) | (CANx->RXFRAME.DATA[1] << 13) | (CANx->RXFRAME.DATA[2] << 5) | (CANx->RXFRAME.DATA[3] >> 3); + + for (i = 0; i < msg->size; i++) + { + msg->data[i] = CANx->RXFRAME.DATA[i + 4]; + } + } + + CANx->CMD = (1 << CAN_CMD_RRB_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_TXComplete() +* 功能说明: å‘é€æ˜¯å¦å®Œæˆ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: uint32_t 1 å·²ç»å®Œæˆ 0 è¿˜æœªå®Œæˆ +* 注æ„事项: å‘é€è¢«Abort也会触å‘å‘é€å®Œæˆï¼Œä½†ä¸ä¼šè§¦å‘å‘é€æˆåŠŸ +******************************************************************************************************************************************/ +uint32_t CAN_TXComplete(CAN_TypeDef *CANx) +{ + return (CANx->SR & CAN_SR_TXBR_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_TXSuccess() +* 功能说明: å‘é€æ˜¯å¦æˆåŠŸ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: uint32_t 1 å‘é€æˆåŠŸ 0 å‘é€å¤±è´¥ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t CAN_TXSuccess(CAN_TypeDef *CANx) +{ + return (CANx->SR & CAN_SR_TXOK_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_AbortTransmit() +* 功能说明: 终止å‘é€ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: 正在进行的å‘é€æ— æ³•ç»ˆæ­¢ï¼Œä½†æ‰§è¡Œæ­¤å‘½ä»¤åŽè‹¥å‘é€å¤±è´¥ä¸ä¼šå†é‡å‘ +******************************************************************************************************************************************/ +void CAN_AbortTransmit(CAN_TypeDef *CANx) +{ + CANx->CMD = (1 << CAN_CMD_ABTTX_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_TXBufferReady() +* 功能说明: TX Buffer是å¦å‡†å¤‡å¥½å¯ä»¥å†™å…¥æ¶ˆæ¯ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: uint32_t 1 已准备好 0 未准备好 +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t CAN_TXBufferReady(CAN_TypeDef *CANx) +{ + return (CANx->SR & CAN_SR_TXBR_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_RXDataAvailable() +* 功能说明: RX FIFO中是å¦æœ‰æ•°æ®å¯è¯»å‡º +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: uint32_t 1 有数æ®å¯è¯»å‡º 0 æ²¡æœ‰æ•°æ® +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t CAN_RXDataAvailable(CAN_TypeDef *CANx) +{ + return (CANx->SR & CAN_SR_RXDA_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_SetBaudrate() +* 功能说明: 设置波特率 +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* uint32_t baudrate 波特率，å³ä½ä¼ è¾“速率 +* uint32_t CAN_BS1 CAN_BS1_1tqã€CAN_BS1_2tqã€... ... ã€CAN_BS1_16tq +* uint32_t CAN_BS2 CAN_BS2_1tqã€CAN_BS2_2tqã€... ... ã€CAN_BS2_8tq +* uint32_t CAN_SJW CAN_SJW_1tqã€CAN_SJW_2tqã€CAN_SJW_3tqã€CAN_SJW_4tq +* 输 出: æ—  +* 注æ„事项: 设置å‰éœ€è¦å…ˆè°ƒç”¨CAN_Close()关闭CANæ¨¡å— +******************************************************************************************************************************************/ +void CAN_SetBaudrate(CAN_TypeDef *CANx, uint32_t baudrate, uint32_t CAN_BS1, uint32_t CAN_BS2, uint32_t CAN_SJW) +{ + CANx->BT1 = (0 << CAN_BT1_SAM_Pos) | + (CAN_BS1 << CAN_BT1_TSEG1_Pos) | + (CAN_BS2 << CAN_BT1_TSEG2_Pos); + + CANx->BT0 = (CAN_SJW << CAN_BT0_SJW_Pos) | + ((SystemCoreClock / 2 / baudrate / (1 + (CAN_BS1 + 1) + (CAN_BS2 + 1)) - 1) << CAN_BT0_BRP_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_SetFilter32b() +* 功能说明: 设置接收滤波器，1个32ä½æ»¤æ³¢å™¨ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* uint32_t check 与mask一起决定了接收到的Message是å¦æ˜¯è‡ªå·±éœ€è¦çš„：check & (~mask) == ID & (~mask)çš„Message通过过滤 +* uint32_t mask +* 输 出: æ—  +* 注æ„事项: 设置å‰éœ€è¦å…ˆè°ƒç”¨CAN_Close()关闭CANæ¨¡å— +******************************************************************************************************************************************/ +void CAN_SetFilter32b(CAN_TypeDef *CANx, uint32_t check, uint32_t mask) +{ + CANx->CR &= ~CAN_CR_AFM_Msk; + CANx->CR |= (CAN_FILTER_32b << CAN_CR_AFM_Pos); + + CANx->FILTER.AMR[0] = mask & 0xFF; + CANx->FILTER.AMR[1] = (mask >> 8) & 0xFF; + CANx->FILTER.AMR[2] = (mask >> 16) & 0xFF; + CANx->FILTER.AMR[3] = (mask >> 24) & 0xFF; + + CANx->FILTER.ACR[0] = check & 0xFF; + CANx->FILTER.ACR[1] = (check >> 8) & 0xFF; + CANx->FILTER.ACR[2] = (check >> 16) & 0xFF; + CANx->FILTER.ACR[3] = (check >> 24) & 0xFF; +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_SetFilter16b() +* 功能说明: 设置接收滤波器，2个16ä½æ»¤æ³¢å™¨ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* uint16_t check1 与mask一起决定了接收到的Message是å¦æ˜¯è‡ªå·±éœ€è¦çš„：check & (~mask) == ID & (~mask)çš„Message通过过滤 +* uint16_t mask1 +* uint16_t check2 +* uint16_t mask2 +* 输 出: æ—  +* 注æ„事项: 设置å‰éœ€è¦å…ˆè°ƒç”¨CAN_Close()关闭CANæ¨¡å— +******************************************************************************************************************************************/ +void CAN_SetFilter16b(CAN_TypeDef *CANx, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2) +{ + CANx->CR &= ~CAN_CR_AFM_Msk; + CANx->CR |= (CAN_FILTER_16b << CAN_CR_AFM_Pos); + + CANx->FILTER.AMR[0] = mask1 & 0xFF; + CANx->FILTER.AMR[1] = (mask1 >> 8) & 0xFF; + CANx->FILTER.AMR[2] = mask2 & 0xFF; + CANx->FILTER.AMR[3] = (mask2 >> 8) & 0xFF; + + CANx->FILTER.ACR[0] = check1 & 0xFF; + CANx->FILTER.ACR[1] = (check1 >> 8) & 0xFF; + CANx->FILTER.ACR[2] = check2 & 0xFF; + CANx->FILTER.ACR[3] = (check2 >> 8) & 0xFF; +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTRXNotEmptyEn() +* 功能说明: 当RX FIFO中有数æ®æ—¶ï¼ˆéžç©ºï¼‰è§¦å‘中断使能 +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTRXNotEmptyEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_RXDA_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTRXNotEmptyDis() +* 功能说明: 当RX FIFO中有数æ®æ—¶ï¼ˆéžç©ºï¼‰è§¦å‘中断ç¦æ­¢ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTRXNotEmptyDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_RXDA_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTRXNotEmptyStat() +* 功能说明: RX FIFOéžç©ºä¸­æ–­æ˜¯å¦è§¦å‘ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: uint32_t 1 å·²è§¦å‘ 0 æœªè§¦å‘ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t CAN_INTRXNotEmptyStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_RXDA_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTTXBufEmptyEn() +* 功能说明: 当TX Buffer空时触å‘中断使能 +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTTXBufEmptyEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_TXBR_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTTXBufEmptyDis() +* 功能说明: 当TX Buffer空时触å‘中断ç¦æ­¢ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTTXBufEmptyDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_TXBR_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTTXBufEmptyStat() +* 功能说明: TX Buffer空中断是å¦è§¦å‘ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: uint32_t 1 å·²è§¦å‘ 0 æœªè§¦å‘ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t CAN_INTTXBufEmptyStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_TXBR_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTErrWarningEn() +* 功能说明: TXERR/RXERR计数值达到Error Warning Limit时触å‘中断使能 +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTErrWarningEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_ERRWARN_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTErrWarningDis() +* 功能说明: TXERR/RXERR计数值达到Error Warning Limit时触å‘中断ç¦æ­¢ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTErrWarningDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_ERRWARN_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTErrWarningStat() +* 功能说明: TXERR/RXERR计数值达到Error Warning Limit中断是å¦è§¦å‘ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: uint32_t 1 å·²è§¦å‘ 0 æœªè§¦å‘ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t CAN_INTErrWarningStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_ERRWARN_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTRXOverflowEn() +* 功能说明: RX FIFO 溢出时触å‘中断使能 +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTRXOverflowEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_RXOV_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTRXOverflowDis() +* 功能说明: RX FIFO 溢出时触å‘中断ç¦æ­¢ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTRXOverflowDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_RXOV_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTRXOverflowStat() +* 功能说明: RX FIFO 溢出中断是å¦è§¦å‘ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: uint32_t 1 å·²è§¦å‘ 0 æœªè§¦å‘ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t CAN_INTRXOverflowStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_RXOV_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTRXOverflowClear() +* 功能说明: RX FIFO 溢出中断清除 +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTRXOverflowClear(CAN_TypeDef *CANx) +{ + CANx->CMD = (1 << CAN_CMD_CLROV_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTWakeupEn() +* 功能说明: 唤醒事件触å‘中断使能 +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTWakeupEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_WKUP_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTWakeupDis() +* 功能说明: 唤醒事件触å‘中断ç¦æ­¢ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTWakeupDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_WKUP_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTWakeupStat() +* 功能说明: 唤醒事件中断是å¦è§¦å‘ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: uint32_t 1 å·²è§¦å‘ 0 æœªè§¦å‘ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t CAN_INTWakeupStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_WKUP_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTErrPassiveEn() +* 功能说明: TXERR/RXERR计数值达到127时中断使能 +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTErrPassiveEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_ERRPASS_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTErrPassiveDis() +* 功能说明: TXERR/RXERR计数值达到127时中断ç¦æ­¢ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTErrPassiveDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_ERRPASS_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTErrPassiveStat() +* 功能说明: TXERR/RXERR计数值达到127中断是å¦è§¦å‘ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: uint32_t 1 å·²è§¦å‘ 0 æœªè§¦å‘ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t CAN_INTErrPassiveStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_ERRPASS_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTArbitrLostEn() +* 功能说明: 仲è£å¤±è´¥ä¸­æ–­ä½¿èƒ½ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTArbitrLostEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_ARBLOST_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTArbitrLostDis() +* 功能说明: 仲è£å¤±è´¥ä¸­æ–­ç¦æ­¢ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTArbitrLostDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_ARBLOST_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTArbitrLostStat() +* 功能说明: 仲è£å¤±è´¥ä¸­æ–­æ˜¯å¦è§¦å‘ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: uint32_t 1 å·²è§¦å‘ 0 æœªè§¦å‘ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t CAN_INTArbitrLostStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_ARBLOST_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTBusErrorEn() +* 功能说明: 总线错误中断使能 +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTBusErrorEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_BUSERR_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTBusErrorDis() +* 功能说明: 总线错误中断ç¦æ­¢ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void CAN_INTBusErrorDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_BUSERR_Pos); +} + +/****************************************************************************************************************************************** +* 函数å称: CAN_INTBusErrorStat() +* 功能说明: 总线错误中断是å¦è§¦å‘ +* 输 å…¥: CAN_TypeDef * CANx 指定è¦è¢«è®¾ç½®çš„CAN接å£ï¼Œæœ‰æ•ˆå€¼åŒ…括CAN +* 输 出: uint32_t 1 å·²è§¦å‘ 0 æœªè§¦å‘ +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t CAN_INTBusErrorStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_BUSERR_Msk) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h new file mode 100644 index 0000000000..6a239c84b3 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h @@ -0,0 +1,141 @@ +#ifndef __SWM320_CAN_H__ +#define __SWM320_CAN_H__ + +#define CAN_FRAME_STD 0 +#define CAN_FRAME_EXT 1 + +typedef struct +{ + uint8_t Mode; //CAN_MODE_NORMAL¡¢CAN_MODE_LISTEN¡¢CAN_MODE_SELFTEST + uint8_t CAN_BS1; //CAN_BS1_1tq¡¢CAN_BS1_2tq¡¢... ... ¡¢CAN_BS1_16tq + uint8_t CAN_BS2; //CAN_BS2_1tq¡¢CAN_BS2_2tq¡¢... ... ¡¢CAN_BS2_8tq + uint8_t CAN_SJW; //CAN_SJW_1tq¡¢CAN_SJW_2tq¡¢CAN_SJW_3tq¡¢CAN_SJW_4tq + uint32_t Baudrate; //²¨ÌØÂÊ£¬¼´Î»´«ÊäËÙÂÊ£¬È¡Öµ1--1000000 + uint8_t FilterMode; //CAN_FILTER_16b¡¢CAN_FILTER_32b + union + { + uint32_t FilterMask32b; //FilterCheck & (~FilterMask) == ID & (~FilterMask)µÄMessageͨ¹ý¹ýÂË + struct // 0 must match 1 don't care + { + uint16_t FilterMask16b1; + uint16_t FilterMask16b2; + }; + }; + union + { + uint32_t FilterCheck32b; + struct + { + uint16_t FilterCheck16b1; + uint16_t FilterCheck16b2; + }; + }; + uint8_t RXNotEmptyIEn; //½ÓÊÕFIFO·Ç¿Õ£¬ÓÐÊý¾Ý¿É¶Á + uint8_t RXOverflowIEn; //½ÓÊÕFIFOÒç³ö£¬ÓÐÊý¾Ý¶ªÊ§ + uint8_t ArbitrLostIEn; //¿ØÖÆÆ÷¶ªÊ§Öٲñä³É½ÓÊÕ·½ + uint8_t ErrPassiveIEn; //½ÓÊÕ/·¢ËÍ´íÎó¼ÆÊýÖµ´ïµ½127 +} CAN_InitStructure; + +#define CAN_MODE_NORMAL 0 //³£¹æģʽ +#define CAN_MODE_LISTEN 1 //¼àÌýģʽ +#define CAN_MODE_SELFTEST 2 //×Ô²âģʽ + +#define CAN_BS1_1tq 0 +#define CAN_BS1_2tq 1 +#define CAN_BS1_3tq 2 +#define CAN_BS1_4tq 3 +#define CAN_BS1_5tq 4 +#define CAN_BS1_6tq 5 +#define CAN_BS1_7tq 6 +#define CAN_BS1_8tq 7 +#define CAN_BS1_9tq 8 +#define CAN_BS1_10tq 9 +#define CAN_BS1_11tq 10 +#define CAN_BS1_12tq 11 +#define CAN_BS1_13tq 12 +#define CAN_BS1_14tq 13 +#define CAN_BS1_15tq 14 +#define CAN_BS1_16tq 15 + +#define CAN_BS2_1tq 0 +#define CAN_BS2_2tq 1 +#define CAN_BS2_3tq 2 +#define CAN_BS2_4tq 3 +#define CAN_BS2_5tq 4 +#define CAN_BS2_6tq 5 +#define CAN_BS2_7tq 6 +#define CAN_BS2_8tq 7 + +#define CAN_SJW_1tq 0 +#define CAN_SJW_2tq 1 +#define CAN_SJW_3tq 2 +#define CAN_SJW_4tq 3 + +#define CAN_FILTER_16b 0 //Á½¸ö16λ¹ýÂËÆ÷ +#define CAN_FILTER_32b 1 //Ò»¸ö32λ¹ýÂËÆ÷ + +typedef struct +{ + uint32_t id; //ÏûÏ¢ID + uint8_t remote; //ÏûÏ¢ÊÇ·ñΪԶ³ÌÖ¡ + uint8_t data[8]; //½ÓÊÕµ½µÄÊý¾Ý + uint8_t size; //½ÓÊÕµ½µÄÊý¾Ý¸öÊý +} CAN_RXMessage; + + +void CAN_Init(CAN_TypeDef *CANx, CAN_InitStructure *initStruct); +void CAN_Open(CAN_TypeDef *CANx); +void CAN_Close(CAN_TypeDef *CANx); + +void CAN_Transmit(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint8_t data[], uint32_t size, uint32_t once); +void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32_t once); +void CAN_Receive(CAN_TypeDef *CANx, CAN_RXMessage *msg); + +uint32_t CAN_TXComplete(CAN_TypeDef *CANx); +uint32_t CAN_TXSuccess(CAN_TypeDef *CANx); + +void CAN_AbortTransmit(CAN_TypeDef *CANx); + +uint32_t CAN_TXBufferReady(CAN_TypeDef *CANx); +uint32_t CAN_RXDataAvailable(CAN_TypeDef *CANx); + +void CAN_SetBaudrate(CAN_TypeDef *CANx, uint32_t baudrate, uint32_t CAN_BS1, uint32_t CAN_BS2, uint32_t CAN_SJW); + +void CAN_SetFilter32b(CAN_TypeDef *CANx, uint32_t check, uint32_t mask); +void CAN_SetFilter16b(CAN_TypeDef *CANx, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2); + + +void CAN_INTRXNotEmptyEn(CAN_TypeDef *CANx); +void CAN_INTRXNotEmptyDis(CAN_TypeDef *CANx); +uint32_t CAN_INTRXNotEmptyStat(CAN_TypeDef *CANx); + +void CAN_INTTXBufEmptyEn(CAN_TypeDef *CANx); +void CAN_INTTXBufEmptyDis(CAN_TypeDef *CANx); +uint32_t CAN_INTTXBufEmptyStat(CAN_TypeDef *CANx); + +void CAN_INTErrWarningEn(CAN_TypeDef *CANx); +void CAN_INTErrWarningDis(CAN_TypeDef *CANx); +uint32_t CAN_INTErrWarningStat(CAN_TypeDef *CANx); + +void CAN_INTRXOverflowEn(CAN_TypeDef *CANx); +void CAN_INTRXOverflowDis(CAN_TypeDef *CANx); +uint32_t CAN_INTRXOverflowStat(CAN_TypeDef *CANx); +void CAN_INTRXOverflowClear(CAN_TypeDef *CANx); + +void CAN_INTWakeupEn(CAN_TypeDef *CANx); +void CAN_INTWakeupDis(CAN_TypeDef *CANx); +uint32_t CAN_INTWakeupStat(CAN_TypeDef *CANx); + +void CAN_INTErrPassiveEn(CAN_TypeDef *CANx); +void CAN_INTErrPassiveDis(CAN_TypeDef *CANx); +uint32_t CAN_INTErrPassiveStat(CAN_TypeDef *CANx); + +void CAN_INTArbitrLostEn(CAN_TypeDef *CANx); +void CAN_INTArbitrLostDis(CAN_TypeDef *CANx); +uint32_t CAN_INTArbitrLostStat(CAN_TypeDef *CANx); + +void CAN_INTBusErrorEn(CAN_TypeDef *CANx); +void CAN_INTBusErrorDis(CAN_TypeDef *CANx); +uint32_t CAN_INTBusErrorStat(CAN_TypeDef *CANx); + +#endif //__SWM320_CAN_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c new file mode 100644 index 0000000000..0258c90382 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c @@ -0,0 +1,51 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_crc.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄCRCÄ£¿éÇý¶¯¿â +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_crc.h" + + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: CRC_Init() +* ¹¦ÄÜ˵Ã÷: CRC ³õʼ»¯ +* Êä Èë: CRC_TypeDef * CRCx Ö¸¶¨Òª±»ÉèÖõÄCRC½Ó¿Ú£¬ÓÐЧֵ°üÀ¨CRC +* uint32_t mode ¹¤×÷ģʽ£¬ÓÐЧֵÓУºCRC32_IN32¡¢CRC32_IN16¡¢CRC32_IN8¡¢CRC16_IN16¡¢CRC16_IN8 +* uint32_t out_not Êä³ö½á¹ûÊÇ·ñÈ¡·´ +* uint32_t out_rev Êä³ö½á¹ûÊÇ·ñ·­×ª +* uint32_t ini_val CRC³õʼֵ +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void CRC_Init(CRC_TypeDef *CRCx, uint32_t mode, uint32_t out_not, uint32_t out_rev, uint32_t ini_val) +{ + switch ((uint32_t)CRCx) + { + case ((uint32_t)CRC): + SYS->CLKEN |= (0x01 << SYS_CLKEN_CRC_Pos); + break; + } + + CRCx->CR = (1 << CRC_CR_EN_Pos) | + (mode << CRC_CR_CRC16_Pos) | + (out_not << CRC_CR_ONOT_Pos) | + (out_rev << CRC_CR_OREV_Pos); + + CRCx->INIVAL = ini_val; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h new file mode 100644 index 0000000000..947bf85455 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h @@ -0,0 +1,39 @@ +#ifndef __SWM320_CRC_H__ +#define __SWM320_CRC_H__ + + +#define CRC32_IN32 0 //CRC32Ëã·¨£¬ÊäÈëÊý¾Ý32λ +#define CRC32_IN16 2 //CRC32Ëã·¨£¬ÊäÈëÊý¾Ý16λ +#define CRC32_IN8 4 //CRC32Ëã·¨£¬ÊäÈëÊý¾Ý 8λ +#define CRC16_IN16 3 //CRC16Ëã·¨£¬ÊäÈëÊý¾Ý16λ +#define CRC16_IN8 5 //CRC16Ëã·¨£¬ÊäÈëÊý¾Ý 8λ + + +void CRC_Init(CRC_TypeDef *CRCx, uint32_t mode, uint32_t out_not, uint32_t out_rev, uint32_t ini_val); + + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: CRC_Write() +* ¹¦ÄÜ˵Ã÷: CRCдÈëÊý¾Ý +* Êä Èë: uint32_t data ҪдÈëµÄÊý¾Ý +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +static __INLINE void CRC_Write(uint32_t data) +{ + CRC->DATAIN = data; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: CRC_Result() +* ¹¦ÄÜ˵Ã÷: »ñÈ¡CRC¼ÆËã½á¹û +* Êä Èë: ÎÞ +* Êä ³ö: uint32_t CRC ¼ÆËã½á¹û +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +static __INLINE uint32_t CRC_Result(void) +{ + return CRC->RESULT; +} + +#endif //__SWM320_CRC_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c new file mode 100644 index 0000000000..3abb4c4b3a --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c @@ -0,0 +1,138 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_dma.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄDMA¹¦ÄÜÇý¶¯¿â +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_dma.h" + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: DMA_CHM_Config() +* ¹¦ÄÜ˵Ã÷: DMAͨµÀÅäÖã¬ÓÃÓÚ´æ´¢Æ÷¼ä£¨ÈçFlashºÍRAM¼ä£©°áÔËÊý¾Ý +* Êä Èë: uint32_t chn Ö¸¶¨ÒªÅäÖõÄͨµÀ£¬ÓÐЧֵÓÐDMA_CH0¡¢DMA_CH1¡¢DMA_CH1 +* uint32_t src_addr Ô´µØÖ·£¬±ØÐë×Ö¶ÔÆ룬¼´µØÖ·µÄ×îµÍ2λ±ØÐëÊÇ00 +* uint32_t src_addr_incr 0 ¹Ì¶¨µØÖ· 1 µØÖ·µÝÔö +* uint32_t dst_addr Ä¿µÄµØÖ·£¬±ØÐë×Ö¶ÔÆ룬¼´µØÖ·µÄ×îµÍ2λ±ØÐëÊÇ00 +* uint32_t dst_addr_incr 0 ¹Ì¶¨µØÖ· 1 µØÖ·µÝÔö +* uint32_t num_word Òª°áÔ˵ÄÊý¾Ý×ÖÊý£¬×î´ó1024 +* uint32_t int_en ÖжÏʹÄÜ£¬1 Êý¾Ý°áÔËÍê³Éºó²úÉúÖÐ¶Ï 0 Êý¾Ý°áÔËÍê³Éºó²»²úÉúÖÐ¶Ï +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: °áÔËÊý¾ÝÁ¿ÒÔ×ÖΪµ¥Ôª£¬²»ÊÇ×Ö½Ú +******************************************************************************************************************************************/ +void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en) +{ + DMA->EN = 1; //ÿ¸öͨµÀ¶¼ÓÐ×Ô¼º¶ÀÁ¢µÄ¿ª¹Ø¿ØÖÆ£¬ËùÒÔ×Ü¿ª¹Ø¿ÉÒÔÊÇÒ»Ö±¿ªÆôµÄ + + DMA_CH_Close(chn); //ÅäÖÃÇ°ÏȹرոÃͨµÀ + + DMA->CH[chn].SRC = src_addr; + DMA->CH[chn].DST = dst_addr; + + DMA->CH[chn].CR = ((num_word * 4 - 1) << DMA_CR_LEN_Pos) | + (0 << DMA_CR_AUTORE_Pos); + + DMA->CH[chn].AM = (src_addr_incr << DMA_AM_SRCAM_Pos) | + (dst_addr_incr << DMA_AM_DSTAM_Pos) | + (0 << DMA_AM_BURST_Pos); + + DMA->IF = (1 << chn); //Çå³ýÖжϱêÖ¾ + DMA->IE |= (1 << chn); + if (int_en) DMA->IM &= ~(1 << chn); + else DMA->IM |= (1 << chn); + + if (int_en) + { + NVIC_EnableIRQ(DMA_IRQn); + } + else + { + //²»Äܵ÷ÓÃNVIC_DisalbeIRQ(DMA_IRQn)£¬ÒòΪÆäËûͨµÀ¿ÉÄÜʹÓÃDMAÖÐ¶Ï + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: DMA_CH_Open() +* ¹¦ÄÜ˵Ã÷: DMAͨµÀ´ò¿ª +* Êä Èë: uint32_t chn Ö¸¶¨ÒªÅäÖõÄͨµÀ£¬ÓÐЧֵÓÐDMA_CH0¡¢DMA_CH1¡¢DMA_CH1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void DMA_CH_Open(uint32_t chn) +{ + DMA->CH[chn].CR |= (1 << DMA_CR_TXEN_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: DMA_CH_Close() +* ¹¦ÄÜ˵Ã÷: DMAͨµÀ¹Ø±Õ +* Êä Èë: uint32_t chn Ö¸¶¨ÒªÅäÖõÄͨµÀ£¬ÓÐЧֵÓÐDMA_CH0¡¢DMA_CH1¡¢DMA_CH1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void DMA_CH_Close(uint32_t chn) +{ + DMA->CH[chn].CR &= ~(1 << DMA_CR_TXEN_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: DMA_CH_INTEn() +* ¹¦ÄÜ˵Ã÷: DMAÖжÏʹÄÜ£¬Êý¾Ý°áÔËÍê³Éºó´¥·¢ÖÐ¶Ï +* Êä Èë: uint32_t chn Ö¸¶¨ÒªÅäÖõÄͨµÀ£¬ÓÐЧֵÓÐDMA_CH0¡¢DMA_CH1¡¢DMA_CH1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void DMA_CH_INTEn(uint32_t chn) +{ + DMA->IM &= ~(1 << chn); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: DMA_CH_INTDis() +* ¹¦ÄÜ˵Ã÷: DMAÖжϽûÖ¹£¬Êý¾Ý°áÔËÍê³Éºó²»´¥·¢ÖÐ¶Ï +* Êä Èë: uint32_t chn Ö¸¶¨ÒªÅäÖõÄͨµÀ£¬ÓÐЧֵÓÐDMA_CH0¡¢DMA_CH1¡¢DMA_CH1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void DMA_CH_INTDis(uint32_t chn) +{ + DMA->IM |= (1 << chn); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: DMA_CH_INTClr() +* ¹¦ÄÜ˵Ã÷: DMAÖжϱêÖ¾Çå³ý +* Êä Èë: uint32_t chn Ö¸¶¨ÒªÅäÖõÄͨµÀ£¬ÓÐЧֵÓÐDMA_CH0¡¢DMA_CH1¡¢DMA_CH1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void DMA_CH_INTClr(uint32_t chn) +{ + DMA->IF = (1 << chn); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: DMA_CH_INTStat() +* ¹¦ÄÜ˵Ã÷: DMAÖжÏ״̬²éѯ +* Êä Èë: uint32_t chn Ö¸¶¨ÒªÅäÖõÄͨµÀ£¬ÓÐЧֵÓÐDMA_CH0¡¢DMA_CH1¡¢DMA_CH1 +* Êä ³ö: uint32_t 1 Êý¾Ý°áÔËÍê³É 0 Êý¾Ý°áÔËδÍê³É +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t DMA_CH_INTStat(uint32_t chn) +{ + return (DMA->IF & (1 << chn)) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h new file mode 100644 index 0000000000..fc4cd98ca8 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h @@ -0,0 +1,20 @@ +#ifndef __SWM320_DMA_H__ +#define __SWM320_DMA_H__ + + +#define DMA_CH0 0 +#define DMA_CH1 1 +#define DMA_CH2 2 + + +void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en); //DMAͨµÀÅäÖã¬ÓÃÓÚ´æ´¢Æ÷¼ä£¨ÈçFlashºÍRAM¼ä£©°áÔËÊý¾Ý +void DMA_CH_Open(uint32_t chn); //DMAͨµÀ´ò¿ª +void DMA_CH_Close(uint32_t chn); //DMAͨµÀ¹Ø±Õ + +void DMA_CH_INTEn(uint32_t chn); //DMAÖжÏʹÄÜ£¬Êý¾Ý°áÔËÍê³Éºó´¥·¢ÖÐ¶Ï +void DMA_CH_INTDis(uint32_t chn); //DMAÖжϽûÖ¹£¬Êý¾Ý°áÔËÍê³Éºó²»´¥·¢ÖÐ¶Ï +void DMA_CH_INTClr(uint32_t chn); //DMAÖжϱêÖ¾Çå³ý +uint32_t DMA_CH_INTStat(uint32_t chn); //DMAÖжÏ״̬²éѯ£¬1 Êý¾Ý°áÔËÍê³É 0 Êý¾Ý°áÔËδÍê³É + + +#endif //__SWM320_DMA_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c new file mode 100644 index 0000000000..0214767e6b --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c @@ -0,0 +1,131 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_exti.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄÍⲿÖжϹ¦ÄÜÇý¶¯¿â +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_exti.h" + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: EXTI_Init() +* ¹¦ÄÜ˵Ã÷: Ö¸¶¨Òý½ÅÍⲿÖжϳõʼ»¯ +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨²úÉúÍⲿÖжϵÄGPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨²úÉúÍⲿÖжϵÄGPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* uint32_t mode ÓÐЧֵÓÐEXTI_FALL_EDGE¡¢EXTI_RISE_EDGE¡¢EXTI_BOTH_EDGE¡¢EXTI_LOW_LEVEL¡¢EXTI_HIGH_LEVEL +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÓÉÓÚGPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOMµÄPIN0--7Òý½Å¼´¿ÉÒÔ½ÓÈëNVICÖеÄÒý½ÅÖжϣ¨ÈçGPIOA0_IRQn£©£¬Ò²¿ÉÒÔ½ÓÈëNVICµÄ×éÖжϣ¨GPIOA_IRQn£©£¬ +* ËùÒÔ²»Ôڴ˺¯ÊýÖе÷ÓÃNVIC_EnableIRQ()ʹÄÜNVICÖжϣ¬´Ó¶ø¿ÉÒÔ¸ù¾ÝÐèÒªµ÷ÓÃNVIC_EnableIRQ(GPIOA0_IRQn)ºÍNVIC_EnableIRQ(GPIOA_IRQn) +******************************************************************************************************************************************/ +void EXTI_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t mode) +{ + EXTI_Close(GPIOx, n); //ÅäÖùؼü¼Ä´æÆ÷Ç°ÏÈ¹Ø±Õ + + if (mode & 0x10) + { + GPIOx->INTLVLTRG |= (0x01 << n); //µçƽ´¥·¢ + + if (mode & 0x01) + GPIOx->INTRISEEN |= (0x01 << n); //¸ßµçƽ´¥·¢ + else + GPIOx->INTRISEEN &= ~(0x01 << n); //µÍµçƽ´¥·¢ + } + else + { + GPIOx->INTLVLTRG &= ~(0x01 << n); //±ßÑØ´¥·¢ + + if (mode & 0x02) + { + GPIOx->INTBE |= (0x01 << n); //Ë«±ßÑØ´¥·¢ + } + else + { + GPIOx->INTBE &= ~(0x01 << n); //µ¥±ßÑØ´¥·¢ + + if (mode & 0x01) + GPIOx->INTRISEEN |= (0x01 << n); //ÉÏÉýÑØ´¥·¢ + else + GPIOx->INTRISEEN &= ~(0x01 << n); //ϽµÑØ´¥·¢ + } + } + + GPIOx->INTCLR = (1 << n); //Çå³ýµôÒòΪģʽÅäÖÿÉÄܲúÉúµÄÖÐ¶Ï +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: EXTI_Open() +* ¹¦ÄÜ˵Ã÷: Ö¸¶¨Òý½ÅÍⲿÖжϴò¿ª£¨¼´Ê¹ÄÜ£© +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨²úÉúÍⲿÖжϵÄGPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨²úÉúÍⲿÖжϵÄGPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n) +{ + GPIOx->INTEN |= (0x01 << n); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: EXTI_Close() +* ¹¦ÄÜ˵Ã÷: Ö¸¶¨Òý½ÅÍⲿÖжϹرգ¨¼´½ûÄÜ£© +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨²úÉúÍⲿÖжϵÄGPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨²úÉúÍⲿÖжϵÄGPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n) +{ + GPIOx->INTEN &= ~(0x01 << n); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: EXTI_State() +* ¹¦ÄÜ˵Ã÷: Ö¸¶¨Òý½ÅÊÇ·ñ´¥·¢ÁËÖÐ¶Ï +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨²úÉúÍⲿÖжϵÄGPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨²úÉúÍⲿÖжϵÄGPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* Êä ³ö: uint32_t 1 ´ËÒý½Å´¥·¢ÁËÖÐ¶Ï 0 ´ËÒý½Åδ´¥·¢ÖÐ¶Ï +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n) +{ + return (GPIOx->INTSTAT >> n) & 0x01; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: EXTI_RawState() +* ¹¦ÄÜ˵Ã÷: Ö¸¶¨Òý½ÅÊÇ·ñÂú×ã¹ý/ÁËÖжϴ¥·¢Ìõ¼þ£¬µ±´ËÖжϹرÕʱ¿Éͨ¹ýµ÷Óô˺¯ÊýÒÔ²éѯµÄ·½Ê½¼ì²âÒý½ÅÉÏÊÇ·ñÂú×ã¹ý/ÁËÖжϴ¥·¢Ìõ¼þ +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨²úÉúÍⲿÖжϵÄGPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨²úÉúÍⲿÖжϵÄGPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* Êä ³ö: uint32_t 1 ´ËÒý½ÅÂú×ã¹ý/ÁËÖжϴ¥·¢Ìõ¼þ 0 ´ËÒý½ÅδÂú×ã¹ý/ÁËÖжϴ¥·¢Ìõ¼þ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t EXTI_RawState(GPIO_TypeDef *GPIOx, uint32_t n) +{ + return (GPIOx->INTRAWSTAT >> 1) & 0x01; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: EXTI_Clear() +* ¹¦ÄÜ˵Ã÷: Ö¸¶¨Òý½ÅÍⲿÖжÏÇå³ý£¨¼´Çå³ýÖжϱêÖ¾£¬ÒÔÃâÔٴνøÈë´ËÖжϣ© +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨²úÉúÍⲿÖжϵÄGPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨²úÉúÍⲿÖжϵÄGPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: Ö»ÄÜÇå³ý±ßÑØ´¥·¢ÖжϵıêÖ¾£¬µçƽ´¥·¢ÖжϵıêÖ¾ÎÞ·¨Çå³ý£¬Ö»ÄÜÔÚÒý½Åµçƽ²»·ûºÏÖжϴ¥·¢Ìõ¼þºóÓ²¼þ×Ô¶¯Çå³ý +******************************************************************************************************************************************/ +void EXTI_Clear(GPIO_TypeDef *GPIOx, uint32_t n) +{ + GPIOx->INTCLR = (0x01 << n); +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h new file mode 100644 index 0000000000..f645fa69f8 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h @@ -0,0 +1,20 @@ +#ifndef __SWM320_EXTI_H__ +#define __SWM320_EXTI_H__ + +void EXTI_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t mode); //Ö¸¶¨Òý½ÅÍⲿÖжϳõʼ»¯ +void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n); //Ö¸¶¨Òý½ÅÍⲿÖжϴò¿ª£¨¼´Ê¹ÄÜ£© +void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n); //Ö¸¶¨Òý½ÅÍⲿÖжϹرգ¨¼´½ûÄÜ£© + +uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n); //Ö¸¶¨Òý½ÅÊÇ·ñ´¥·¢ÁËÖÐ¶Ï +uint32_t EXTI_RawState(GPIO_TypeDef *GPIOx, uint32_t n); //Ö¸¶¨Òý½ÅÊÇ·ñÂú×ã¹ý/ÁËÖжϴ¥·¢Ìõ¼þ£¬µ±´ËÖжϹرÕʱ¿Éͨ¹ýµ÷Óô˺¯ÊýÒÔ²éѯµÄ·½Ê½¼ì²âÒý½ÅÉÏÊÇ·ñÂú×ã¹ý/ÁËÖжϴ¥·¢Ìõ¼þ +void EXTI_Clear(GPIO_TypeDef *GPIOx, uint32_t n); //Ö¸¶¨Òý½ÅÍⲿÖжÏÇå³ý£¨¼´Çå³ýÖжϱêÖ¾£¬ÒÔÃâÔٴνøÈë´ËÖжϣ© + + +#define EXTI_FALL_EDGE 0x00 //ϽµÑØ´¥·¢ÖÐ¶Ï +#define EXTI_RISE_EDGE 0x01 //ÉÏÉýÑØ´¥·¢ÖÐ¶Ï +#define EXTI_BOTH_EDGE 0x02 //Ë«±ßÑØ´¥·¢ÖÐ¶Ï +#define EXTI_LOW_LEVEL 0x10 //µÍµçƽ´¥·¢ÖÐ¶Ï +#define EXTI_HIGH_LEVEL 0x11 //¸ßµçƽ´¥·¢ÖÐ¶Ï + + +#endif //__SWM320_EXTI_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c new file mode 100644 index 0000000000..fa619e566c --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c @@ -0,0 +1,95 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_flash.c +* ¹¦ÄÜ˵Ã÷: ʹÓÃоƬµÄIAP¹¦Äܽ«Æ¬ÉÏFlashÄ£Äâ³ÉEEPROMÀ´±£´æÊý¾Ý£¬µôµçºó²»¶ªÊ§ +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_flash.h" + + +__attribute__((section("PlaceInRAM"))) +static void switchTo80M(void) +{ + uint32_t i; + + for (i = 0; i < 50; i++) __NOP(); + + FLASH->CFG0 = 0x4bf; + FLASH->CFG1 = 0xabfc7a6e; + + for (i = 0; i < 50; i++) __NOP(); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: FLASH_Erase() +* ¹¦ÄÜ˵Ã÷: ƬÄÚFlash²Á³ý +* Êä Èë: uint32_t addr ²Á³ýµØÖ· +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void FLASH_Erase(uint32_t addr) +{ +// switchTo80M(); + + FLASH->ERASE = addr | ((uint32_t)1 << FLASH_ERASE_REQ_Pos); + while ((FLASH->STAT & FLASH_STAT_ERASE_GOING_Msk) == 0); + while ((FLASH->STAT & FLASH_STAT_ERASE_GOING_Msk) == 1); + + FLASH->ERASE = 0; + +// switchTo40M(); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: FLASH_Write() +* ¹¦ÄÜ˵Ã÷: ƬÄÚFlashдÈë +* Êä Èë: uint32_t addr дÈëµØÖ· +* uint32_t buff[] ҪдÈëµÄÊý¾Ý +* uint32_t size ҪдÈëÊý¾ÝµÄ¸öÊý£¬×ÖΪµ¥Î» +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t size) +{ + uint32_t i, j; + + switchTo80M(); + + FLASH->CACHE |= (1 << FLASH_CACHE_PROG_Pos); + + for (i = 0; i < size / 4; i++) + { + FLASH->ADDR = addr + i * 4 * 4; + + for (j = 0; j < 4; j++) + FLASH->DATA = buff[i * 4 + j]; + while ((FLASH->STAT & FLASH_STAT_FIFO_EMPTY_Msk) == 0) __NOP(); + } + if ((size % 4) != 0) + { + FLASH->ADDR = addr + i * 4 * 4; + + for (j = 0; j < size % 4; j++) + FLASH->DATA = buff[i * 4 + j]; + while ((FLASH->STAT & FLASH_STAT_FIFO_EMPTY_Msk) == 0) __NOP(); + } + while (FLASH->STAT & FLASH_STAT_PROG_GOING_Msk); + + FLASH->CACHE |= (1 << FLASH_CACHE_CLEAR_Pos); + FLASH->CACHE = 0; + +// switchTo40M(); +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h new file mode 100644 index 0000000000..5a4bfbb89f --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h @@ -0,0 +1,9 @@ +#ifndef __SWM320_FLASH_H__ +#define __SWM320_FLASH_H__ + + +void FLASH_Erase(uint32_t addr); +void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t size); + + +#endif //__SWM320_FLASH_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c new file mode 100644 index 0000000000..dd81e75952 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c @@ -0,0 +1,279 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_gpio.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄͨÓÃÊäÈëÊä³ö¹¦ÄÜÇý¶¯¿â +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_gpio.h" + + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: GPIO_Init() +* ¹¦ÄÜ˵Ã÷: Òý½Å³õʼ»¯£¬°üº¬Òý½Å·½Ïò¡¢ÉÏÀ­µç×è¡¢ÏÂÀ­µç×è¡¢¿ªÂ©Êä³ö +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨GPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨GPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* uint32_t dir Òý½Å·½Ïò£¬0 ÊäÈë 1 Êä³ö +* uint32_t pull_up ÉÏÀ­µç×裬0 ¹Ø±ÕÉÏÀ­ 1 ¿ªÆôÉÏÀ­ +* uint32_t pull_down ÏÂÀ­µç×裬0 ¹Ø±ÕÏÂÀ­ 1 ¿ªÆôÏÂÀ­ +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down) +{ + switch ((uint32_t)GPIOx) + { + case ((uint32_t)GPIOA): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOA_Pos); + + PORT_Init(PORTA, n, 0, 1); //PORTA.PINnÒý½ÅÅäÖÃΪGPIO¹¦ÄÜ£¬Êý×ÖÊäÈ뿪Æô + if (dir == 1) + { + GPIOA->DIR |= (0x01 << n); + } + else + { + GPIOA->DIR &= ~(0x01 << n); + } + + if (pull_up == 1) + PORT->PORTA_PULLU |= (0x01 << n); + else + PORT->PORTA_PULLU &= ~(0x01 << n); + break; + + case ((uint32_t)GPIOB): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOB_Pos); + + PORT_Init(PORTB, n, 0, 1); //PORTB.PINnÒý½ÅÅäÖÃΪGPIO¹¦ÄÜ£¬Êý×ÖÊäÈ뿪Æô + if (dir == 1) + { + GPIOB->DIR |= (0x01 << n); + } + else + { + GPIOB->DIR &= ~(0x01 << n); + } + + if (pull_down == 1) + PORT->PORTB_PULLD |= (0x01 << n); + else + PORT->PORTB_PULLD &= ~(0x01 << n); + break; + + case ((uint32_t)GPIOC): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOC_Pos); + + PORT_Init(PORTC, n, 0, 1); //PORTC.PINnÒý½ÅÅäÖÃΪGPIO¹¦ÄÜ£¬Êý×ÖÊäÈ뿪Æô + if (dir == 1) + { + GPIOC->DIR |= (0x01 << n); + } + else + { + GPIOC->DIR &= ~(0x01 << n); + } + + if (pull_up == 1) + PORT->PORTC_PULLU |= (0x01 << n); + else + PORT->PORTC_PULLU &= ~(0x01 << n); + break; + + case ((uint32_t)GPIOM): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOM_Pos); + + PORT_Init(PORTM, n, 0, 1); //PORTM.PINnÒý½ÅÅäÖÃΪGPIO¹¦ÄÜ£¬Êý×ÖÊäÈ뿪Æô + if (dir == 1) + { + GPIOM->DIR |= (0x01 << n); + } + else + { + GPIOM->DIR &= ~(0x01 << n); + } + + if (pull_up == 1) + PORT->PORTM_PULLU |= (0x01 << n); + else + PORT->PORTM_PULLU &= ~(0x01 << n); + break; + + case ((uint32_t)GPION): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPION_Pos); + + PORT_Init(PORTN, n, 0, 1); //PORTN.PINnÒý½ÅÅäÖÃΪGPIO¹¦ÄÜ£¬Êý×ÖÊäÈ뿪Æô + if (dir == 1) + { + GPION->DIR |= (0x01 << n); + } + else + { + GPION->DIR &= ~(0x01 << n); + } + + if (pull_down == 1) + PORT->PORTN_PULLD |= (0x01 << n); + else + PORT->PORTN_PULLD &= ~(0x01 << n); + break; + + case ((uint32_t)GPIOP): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOP_Pos); + + PORT_Init(PORTP, n, 0, 1); //PORTP.PINnÒý½ÅÅäÖÃΪGPIO¹¦ÄÜ£¬Êý×ÖÊäÈ뿪Æô + if (dir == 1) + { + GPIOP->DIR |= (0x01 << n); + } + else + { + GPIOP->DIR &= ~(0x01 << n); + } + + if (pull_up == 1) + PORT->PORTP_PULLU |= (0x01 << n); + else + PORT->PORTP_PULLU &= ~(0x01 << n); + break; + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: GPIO_SetBit() +* ¹¦ÄÜ˵Ã÷: ½«²ÎÊýÖ¸¶¨µÄÒý½ÅµçƽÖÃ¸ß +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨GPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨GPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n) +{ + GPIOx->DATA |= (0x01 << n); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: GPIO_ClrBit() +* ¹¦ÄÜ˵Ã÷: ½«²ÎÊýÖ¸¶¨µÄÒý½ÅµçƽÖÃµÍ +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨GPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨GPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n) +{ + GPIOx->DATA &= ~(0x01 << n); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: GPIO_InvBit() +* ¹¦ÄÜ˵Ã÷: ½«²ÎÊýÖ¸¶¨µÄÒý½Åµçƽ·´×ª +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨GPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨GPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n) +{ + GPIOx->DATA ^= (0x01 << n); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: GPIO_GetBit() +* ¹¦ÄÜ˵Ã÷: ¶ÁÈ¡²ÎÊýÖ¸¶¨µÄÒý½ÅµÄµçƽ״̬ +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨GPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨GPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* Êä ³ö: ²ÎÊýÖ¸¶¨µÄÒý½ÅµÄµçƽ״̬ 0 µÍµçƽ 1 ¸ßµçƽ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n) +{ + return ((GPIOx->DATA >> n) & 0x01); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: GPIO_SetBits() +* ¹¦ÄÜ˵Ã÷: ½«²ÎÊýÖ¸¶¨µÄ´Ón¿ªÊ¼µÄwλÁ¬ÐøÒý½ÅµÄµçƽÖÃ¸ß +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨GPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨GPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* uint32_t w Ö¸¶¨Òª½«Òý½ÅµçƽÖøߵÄÒý½ÅµÄ¸öÊý +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + GPIOx->DATA |= (bits << n); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: GPIO_ClrBits() +* ¹¦ÄÜ˵Ã÷: ½«²ÎÊýÖ¸¶¨µÄ´Ón¿ªÊ¼µÄwλÁ¬ÐøÒý½ÅµÄµçƽÖÃµÍ +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨GPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨GPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* uint32_t w Ö¸¶¨Òª½«Òý½ÅµçƽÖõ͵ÄÒý½ÅµÄ¸öÊý +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + GPIOx->DATA &= ~(bits << n); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: GPIO_InvBits() +* ¹¦ÄÜ˵Ã÷: ½«²ÎÊýÖ¸¶¨µÄ´Ón¿ªÊ¼µÄwλÁ¬ÐøÒý½ÅµÄµçƽ·´×ª +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨GPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨GPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* uint32_t w Ö¸¶¨Òª½«Òý½Åµçƽ·´×ªµÄÒý½ÅµÄ¸öÊý +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + GPIOx->DATA ^= (bits << n); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: GPIO_GetBits() +* ¹¦ÄÜ˵Ã÷: ¶ÁÈ¡²ÎÊýÖ¸¶¨µÄ´Ón¿ªÊ¼µÄwλÁ¬ÐøÒý½ÅµÄµçƽ״̬ +* Êä Èë: GPIO_TypeDef * GPIOx Ö¸¶¨GPIO¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨GPIOA¡¢GPIOB¡¢GPIOC¡¢GPIOM¡¢GPION¡¢GPIOP +* uint32_t n Ö¸¶¨GPIOÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* uint32_t w Ö¸¶¨Òª½«Òý½ÅµçƽÖøߵÄÒý½ÅµÄ¸öÊý +* Êä ³ö: ²ÎÊýÖ¸¶¨µÄ´Ón¿ªÊ¼µÄwλÁ¬ÐøÒý½ÅµÄµçƽ״̬ 0 µÍµçƽ 1 ¸ßµçƽ +* ·µ»ØÖµµÄµÚ0λ±íʾÒý½ÅnµÄµçƽ״̬¡¢·µ»ØÖµµÄµÚ1λ±íʾÒý½Ån+1µÄµçƽ״̬... ...·µ»ØÖµµÄµÚwλ±íʾÒý½Ån+wµÄµçƽ״̬ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + return ((GPIOx->DATA >> n) & bits); +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h new file mode 100644 index 0000000000..a0f84999bd --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h @@ -0,0 +1,17 @@ +#ifndef __SWM320_GPIO_H__ +#define __SWM320_GPIO_H__ + + +void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down); //Òý½Å³õʼ»¯£¬°üº¬Òý½Å·½Ïò¡¢ÉÏÀ­µç×è¡¢ÏÂÀ­µç×è + +void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n); //½«²ÎÊýÖ¸¶¨µÄÒý½ÅµçƽÖÃ¸ß +void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n); //½«²ÎÊýÖ¸¶¨µÄÒý½ÅµçƽÖÃµÍ +void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n); //½«²ÎÊýÖ¸¶¨µÄÒý½Åµçƽ·´×ª +uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n); //¶ÁÈ¡²ÎÊýÖ¸¶¨µÄÒý½ÅµÄµçƽ״̬ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //½«²ÎÊýÖ¸¶¨µÄ´Ón¿ªÊ¼µÄwλÁ¬ÐøÒý½ÅµÄµçƽÖÃ¸ß +void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //½«²ÎÊýÖ¸¶¨µÄ´Ón¿ªÊ¼µÄwλÁ¬ÐøÒý½ÅµÄµçƽÖÃµÍ +void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //½«²ÎÊýÖ¸¶¨µÄ´Ón¿ªÊ¼µÄwλÁ¬ÐøÒý½ÅµÄµçƽ·´×ª +uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //¶ÁÈ¡²ÎÊýÖ¸¶¨µÄ´Ón¿ªÊ¼µÄwλÁ¬ÐøÒý½ÅµÄµçƽ״̬ + + +#endif //__SWM320_GPIO_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c new file mode 100644 index 0000000000..34de5c5610 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c @@ -0,0 +1,150 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_i2c.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄI2C´®Ðнӿڹ¦ÄÜÇý¶¯¿â +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIES AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIEE. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIES ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_i2c.h" + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: I2C_Init() +* ¹¦ÄÜ˵Ã÷: I2C³õʼ»¯ +* Êä Èë: I2C_TypeDef * I2Cx Ö¸¶¨Òª±»ÉèÖõÄI2C£¬ÓÐЧֵ°üÀ¨I2C0¡¢I2C1 +* I2C_InitStructure * initStruct °üº¬I2CÏà¹ØÉ趨ֵµÄ½á¹¹Ìå +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: Ä£¿éÖ»Äܹ¤×÷ÓÚÖ÷»úģʽ +******************************************************************************************************************************************/ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct) +{ + switch ((uint32_t)I2Cx) + { + case ((uint32_t)I2C0): + SYS->CLKEN |= (0x01 << SYS_CLKEN_I2C0_Pos); + break; + + case ((uint32_t)I2C1): + SYS->CLKEN |= (0x01 << SYS_CLKEN_I2C1_Pos); + break; + } + + I2C_Close(I2Cx); //һЩ¹Ø¼ü¼Ä´æÆ÷Ö»ÄÜÔÚI2C¹Ø±ÕʱÉèÖà + + if (initStruct->Master == 1) + { + I2Cx->CLKDIV = SystemCoreClock / 5 / initStruct->MstClk; + + I2Cx->MSTCMD = (I2Cx->MSTCMD & (~I2C_MSTCMD_IF_Msk)) | (1 << I2C_MSTCMD_IF_Pos); //ʹÄÜÖжÏ֮ǰÏÈÇå³ýÖжϱêÖ¾ + I2Cx->CTRL &= ~I2C_CTRL_MSTIE_Msk; + I2Cx->CTRL |= (initStruct->MstIEn << I2C_CTRL_MSTIE_Pos); + + switch ((uint32_t)I2Cx) + { + case ((uint32_t)I2C0): + if (initStruct->MstIEn) + { + NVIC_EnableIRQ(I2C0_IRQn); + } + else + { + NVIC_DisableIRQ(I2C0_IRQn); + } + break; + + case ((uint32_t)I2C1): + if (initStruct->MstIEn) + { + NVIC_EnableIRQ(I2C1_IRQn); + } + else + { + NVIC_DisableIRQ(I2C1_IRQn); + } + break; + } + } + else + { + I2Cx->SLVCR |= (1 << I2C_SLVCR_SLAVE_Pos); + + I2Cx->SLVCR &= ~(I2C_SLVCR_ADDR7b_Msk | I2C_SLVCR_ADDR_Msk); + I2Cx->SLVCR |= (1 << I2C_SLVCR_ACK_Pos) | + (initStruct->Addr7b << I2C_SLVCR_ADDR7b_Pos) | + (initStruct->SlvAddr << I2C_SLVCR_ADDR_Pos); + + I2Cx->SLVIF = I2C_SLVIF_RXEND_Msk | I2C_SLVIF_TXEND_Msk | I2C_SLVIF_STADET_Msk | I2C_SLVIF_STODET_Msk; //ÇåÖжϱêÖ¾ + I2Cx->SLVCR &= ~(I2C_SLVCR_IM_RXEND_Msk | I2C_SLVCR_IM_TXEND_Msk | I2C_SLVCR_IM_STADET_Msk | I2C_SLVCR_IM_STODET_Msk | + I2C_SLVCR_IM_RDREQ_Msk | I2C_SLVCR_IM_WRREQ_Msk); + I2Cx->SLVCR |= ((initStruct->SlvRxEndIEn ? 0 : 1) << I2C_SLVCR_IM_RXEND_Pos) | + ((initStruct->SlvTxEndIEn ? 0 : 1) << I2C_SLVCR_IM_TXEND_Pos) | + ((initStruct->SlvSTADetIEn ? 0 : 1) << I2C_SLVCR_IM_STADET_Pos) | + ((initStruct->SlvSTODetIEn ? 0 : 1) << I2C_SLVCR_IM_STODET_Pos) | + ((initStruct->SlvRdReqIEn ? 0 : 1) << I2C_SLVCR_IM_RDREQ_Pos) | + ((initStruct->SlvWrReqIEn ? 0 : 1) << I2C_SLVCR_IM_WRREQ_Pos); + + switch ((uint32_t)I2Cx) + { + case ((uint32_t)I2C0): + if (initStruct->SlvRxEndIEn | initStruct->SlvTxEndIEn | initStruct->SlvSTADetIEn | + initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn) + { + NVIC_EnableIRQ(I2C0_IRQn); + } + else + { + NVIC_DisableIRQ(I2C0_IRQn); + } + break; + + case ((uint32_t)I2C1): + if (initStruct->SlvRxEndIEn | initStruct->SlvTxEndIEn | initStruct->SlvSTADetIEn | + initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn) + { + NVIC_EnableIRQ(I2C1_IRQn); + } + else + { + NVIC_DisableIRQ(I2C1_IRQn); + } + break; + } + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: I2C_Open() +* ¹¦ÄÜ˵Ã÷: I2C´ò¿ª£¬ÔÊÐíÊÕ·¢ +* Êä Èë: I2C_TypeDef * I2Cx Ö¸¶¨Òª±»ÉèÖõÄI2C£¬ÓÐЧֵ°üÀ¨I2C0¡¢I2C1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void I2C_Open(I2C_TypeDef *I2Cx) +{ + I2Cx->CTRL |= (0x01 << I2C_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: I2C_Close() +* ¹¦ÄÜ˵Ã÷: I2C¹Ø±Õ£¬½ûÖ¹ÊÕ·¢ +* Êä Èë: I2C_TypeDef * I2Cx Ö¸¶¨Òª±»ÉèÖõÄI2C£¬ÓÐЧֵ°üÀ¨I2C0¡¢I2C1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void I2C_Close(I2C_TypeDef *I2Cx) +{ + I2Cx->CTRL &= ~I2C_CTRL_EN_Msk; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h new file mode 100644 index 0000000000..769f5a2b55 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h @@ -0,0 +1,27 @@ +#ifndef __SWM320_I2C_H__ +#define __SWM320_I2C_H__ + +typedef struct +{ + uint8_t Master; //1 Ö÷»úģʽ + uint8_t Addr7b; //1 7λµØÖ· 0 10λµØÖ· + + uint32_t MstClk; //Ö÷»ú´«ÊäʱÖÓƵÂÊ + uint8_t MstIEn; //Ö÷»úģʽÖжÏʹÄÜ + + uint16_t SlvAddr; //´Ó»úµØÖ· + uint8_t SlvRxEndIEn; //´Ó»ú½ÓÊÕÍê³ÉÖжÏʹÄÜ + uint8_t SlvTxEndIEn; //´Ó»ú·¢ËÍÍê³ÉÖжÏʹÄÜ + uint8_t SlvSTADetIEn; //´Ó»ú¼ì²âµ½ÆðʼÖжÏʹÄÜ + uint8_t SlvSTODetIEn; //´Ó»ú¼ì²âµ½ÖÕÖ¹ÖжÏʹÄÜ + uint8_t SlvRdReqIEn; //´Ó»ú½ÓÊÕµ½¶ÁÇëÇóÖжÏʹÄÜ + uint8_t SlvWrReqIEn; //´Ó»ú½ÓÊÕµ½Ð´ÇëÇóÖжÏʹÄÜ +} I2C_InitStructure; + + +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct); + +void I2C_Open(I2C_TypeDef *I2Cx); +void I2C_Close(I2C_TypeDef *I2Cx); + +#endif //__SWM320_I2C_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c new file mode 100644 index 0000000000..742c5b35dd --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c @@ -0,0 +1,259 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_lcd.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄLCD¹¦ÄÜÇý¶¯¿â +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_lcd.h" + +#include + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: LCD_Init() +* ¹¦ÄÜ˵Ã÷: LCD³õʼ»¯ +* Êä Èë: LCD_TypeDef * LCDx Ö¸¶¨Òª±»ÉèÖõÄLCD£¬ÓÐЧֵ°üÀ¨LCD +* LCD_InitStructure * initStruct °üº¬LCDÏà¹ØÉ趨ֵµÄ½á¹¹Ìå +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct) +{ + switch ((uint32_t)LCDx) + { + case ((uint32_t)LCD): + SYS->CLKEN |= (0x01 << SYS_CLKEN_LCD_Pos); + break; + } + + if (initStruct->Interface == LCD_INTERFACE_RGB) + { + LCDx->START = (0 << LCD_START_MPUEN_Pos); + + if (initStruct->Dir == LCD_DIR_LANDSCAPE) + { + LCDx->CR0 = ((initStruct->HnPixel - 1) << LCD_CR0_HPIX_Pos) | + ((initStruct->VnPixel - 1) << LCD_CR0_VPIX_Pos) | + (initStruct->ClkAlways << LCD_CR0_DCLK_Pos) | + (initStruct->HsyncWidth << LCD_CR0_HLOW_Pos); + + LCDx->CR1 = (initStruct->Dir << LCD_CR1_DIRV_Pos) | + ((initStruct->Hfp - 1) << LCD_CR1_HFP_Pos) | + ((initStruct->Hbp - 1) << LCD_CR1_HBP_Pos) | + ((initStruct->Vfp - 1) << LCD_CR1_VFP_Pos) | + ((initStruct->Vbp - 1) << LCD_CR1_VBP_Pos) | + (initStruct->ClkDiv << LCD_CR1_DCLKDIV_Pos) | + (initStruct->SamplEdge << LCD_CR1_DCLKINV_Pos); + } + else + { + LCDx->CR0 = ((initStruct->HnPixel - 1) << LCD_CR0_VPIX_Pos) | + ((initStruct->VnPixel - 1) << LCD_CR0_HPIX_Pos) | + (initStruct->ClkAlways << LCD_CR0_DCLK_Pos) | + (initStruct->HsyncWidth << LCD_CR0_HLOW_Pos); + + LCDx->CR1 = (initStruct->Dir << LCD_CR1_DIRV_Pos) | + ((initStruct->Hfp - 1) << LCD_CR1_VFP_Pos) | + ((initStruct->Hbp - 1) << LCD_CR1_VBP_Pos) | + ((initStruct->Vfp - 1) << LCD_CR1_HFP_Pos) | + ((initStruct->Vbp - 1) << LCD_CR1_HBP_Pos) | + (initStruct->ClkDiv << LCD_CR1_DCLKDIV_Pos) | + (initStruct->SamplEdge << LCD_CR1_DCLKINV_Pos); + } + } + else if (initStruct->Interface == LCD_INTERFACE_I80) + { + LCDx->START = (1 << LCD_START_MPUEN_Pos); + + LCDx->CR1 = (1 << LCD_CR1_I80_Pos) | + (initStruct->T_CSf_WRf << LCD_CR1_TAS_Pos) | + (initStruct->T_WRnHold << LCD_CR1_TPWLW_Pos) | + (initStruct->T_WRr_CSr << LCD_CR1_TAH_Pos) | + (initStruct->T_CSr_CSf << LCD_CR1_TTAIL_Pos); + } + + LCDx->IE = 1; + LCDx->IF = 1; //Çå³ý±êÖ¾ + if (initStruct->IntEOTEn) LCD_INTEn(LCDx); + else LCD_INTDis(LCDx); + + switch ((uint32_t)LCDx) + { + case ((uint32_t)LCD): + if (initStruct->IntEOTEn) + { + NVIC_EnableIRQ(LCD_IRQn); + } + else + { + NVIC_DisableIRQ(LCD_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: LCD_Start() +* ¹¦ÄÜ˵Ã÷: Æô¶¯Ò»´ÎÊý¾Ý´«Êä +* Êä Èë: LCD_TypeDef * LCDx Ö¸¶¨Òª±»ÉèÖõÄLCD£¬ÓÐЧֵ°üÀ¨LCD +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void LCD_Start(LCD_TypeDef *LCDx) +{ + LCDx->START |= (1 << LCD_START_GO_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: LCD_IsBusy() +* ¹¦ÄÜ˵Ã÷: ÊÇ·ñÕýÔÚ½øÐÐÊý¾Ý´«Êä +* Êä Èë: LCD_TypeDef * LCDx Ö¸¶¨Òª±»ÉèÖõÄLCD£¬ÓÐЧֵ°üÀ¨LCD +* Êä ³ö: uint32_t 1 ÕýÔÚ´«ÊäÊý¾Ý 0 Êý¾Ý´«ÊäÒÑÍê³É +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t LCD_IsBusy(LCD_TypeDef *LCDx) +{ + return (LCDx->START & LCD_START_GO_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: LCD_I80_WriteReg() +* ¹¦ÄÜ˵Ã÷: MPU½Ó¿Úʱ£¬Ð´¼Ä´æÆ÷ +* Êä Èë: LCD_TypeDef * LCDx Ö¸¶¨Òª±»ÉèÖõÄLCD£¬ÓÐЧֵ°üÀ¨LCD +* uint16_t reg ҪдµÄ¼Ä´æÆ÷ÆäʵµØÖ·£¬µØÖ·×ÔÔö +* uint16_t val[] ¼Ä´æÆ÷Öµ£¬Êý×éµØÖ·±ØÐë×Ô¶ÔÆë +* uint16_t cnt ҪдµÄ¼Ä´æÆ÷¸öÊý +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void LCD_I80_WriteReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val[], uint16_t cnt) +{ + LCD->SRCADDR = (uint32_t)val; + LCD->CR0 &= ~LCD_CR0_DLEN_Msk; + LCD->CR0 |= ((cnt - 1) << LCD_CR0_DLEN_Pos); + + LCD->CR1 |= (1 << LCD_CR1_CMD_Pos); + LCD->CR1 &= ~LCD_CR1_REG_Msk; + LCD->CR1 |= (reg << LCD_CR1_REG_Pos); + + LCD_Start(LCDx); + while (LCD_IsBusy(LCDx)); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: LCD_I80_WriteOneReg() +* ¹¦ÄÜ˵Ã÷: MPU½Ó¿Úʱ£¬Ð´¼Ä´æÆ÷ +* Êä Èë: LCD_TypeDef * LCDx Ö¸¶¨Òª±»ÉèÖõÄLCD£¬ÓÐЧֵ°üÀ¨LCD +* uint16_t reg ҪдµÄ¼Ä´æÆ÷ÆäʵµØÖ· +* uint16_t val ¼Ä´æÆ÷Öµ +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void LCD_I80_WriteOneReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val) +{ + uint16_t buf[1] __attribute__((aligned(4))); + + buf[0] = val; + + LCD_I80_WriteReg(LCDx, reg, buf, 1); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: LCD_I80_WriteData() +* ¹¦ÄÜ˵Ã÷: MPU½Ó¿Úʱ£¬Ð´Êý¾Ý +* Êä Èë: LCD_TypeDef * LCDx Ö¸¶¨Òª±»ÉèÖõÄLCD£¬ÓÐЧֵ°üÀ¨LCD +* uint16_t val[] ҪдµÄÊý¾Ý£¬Êý×éµØÖ·±ØÐë×Ô¶ÔÆë +* uint16_t cnt ҪдµÄÊý¾Ý¸öÊý +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void LCD_I80_WriteData(LCD_TypeDef *LCDx, uint16_t val[], uint16_t cnt) +{ + LCD->SRCADDR = (uint32_t)val; + LCD->CR0 &= ~LCD_CR0_DLEN_Msk; + LCD->CR0 |= ((cnt - 1) << LCD_CR0_DLEN_Pos); + + LCD->CR1 &= ~(1 << LCD_CR1_CMD_Pos); + + LCD_Start(LCDx); + while (LCD_IsBusy(LCDx)); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: LCD_I80_WriteOneData() +* ¹¦ÄÜ˵Ã÷: MPU½Ó¿Úʱ£¬Ð´Êý¾Ý +* Êä Èë: LCD_TypeDef * LCDx Ö¸¶¨Òª±»ÉèÖõÄLCD£¬ÓÐЧֵ°üÀ¨LCD +* uint16_t val ҪдµÄÊý¾Ý +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void LCD_I80_WriteOneData(LCD_TypeDef *LCDx, uint16_t val) +{ + uint16_t buf[1] __attribute__((aligned(4))); + + buf[0] = val; + + LCD_I80_WriteData(LCDx, buf, 2); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: LCD_INTEn() +* ¹¦ÄÜ˵Ã÷: LCDÖжÏʹÄÜ£¬Íê³ÉÖ¸¶¨³¤¶ÈµÄÊý¾Ý´«Êäʱ´¥·¢ÖÐ¶Ï +* Êä Èë: LCD_TypeDef * LCDx Ö¸¶¨Òª±»ÉèÖõÄLCD£¬ÓÐЧֵ°üÀ¨LCD +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void LCD_INTEn(LCD_TypeDef *LCDx) +{ + LCDx->IM = 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: LCD_INTDis() +* ¹¦ÄÜ˵Ã÷: LCDÖжϽûÖ¹£¬Íê³ÉÖ¸¶¨³¤¶ÈµÄÊý¾Ý´«Êäʱ²»´¥·¢ÖÐ¶Ï +* Êä Èë: LCD_TypeDef * LCDx Ö¸¶¨Òª±»ÉèÖõÄLCD£¬ÓÐЧֵ°üÀ¨LCD +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void LCD_INTDis(LCD_TypeDef *LCDx) +{ + LCDx->IM = 1; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: LCD_INTClr() +* ¹¦ÄÜ˵Ã÷: LCDÖжϱêÖ¾Çå³ý +* Êä Èë: LCD_TypeDef * LCDx Ö¸¶¨Òª±»ÉèÖõÄLCD£¬ÓÐЧֵ°üÀ¨LCD +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void LCD_INTClr(LCD_TypeDef *LCDx) +{ + LCDx->IF = 1; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: LCD_INTStat() +* ¹¦ÄÜ˵Ã÷: LCDÖжÏ״̬²éѯ +* Êä Èë: LCD_TypeDef * LCDx Ö¸¶¨Òª±»ÉèÖõÄLCD£¬ÓÐЧֵ°üÀ¨LCD +* Êä ³ö: uint32_t 1 Íê³ÉÖ¸¶¨³¤¶ÈµÄÊý¾Ý´«Êä 0 δÍê³ÉÖ¸¶¨³¤¶ÈµÄÊý¾Ý´«Êä +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t LCD_INTStat(LCD_TypeDef *LCDx) +{ + return (LCDx->IF & 0x01) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h new file mode 100644 index 0000000000..0b9d9b53c3 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h @@ -0,0 +1,96 @@ +#ifndef __SWM320_LCD_H__ +#define __SWM320_LCD_H__ + + +typedef struct +{ + uint8_t Interface; //LCDÆÁ½Ó¿Ú£ºLCD_INTERFACE_RGB¡¢LCD_INTERFACE_I80¡¢LCD_INTERFACE_M68 + + /* RGBͬ²½½Ó¿Ú²ÎÊý */ + uint8_t Dir; //LCD_DIR_LANDSCAPE ºáÆÁ LCD_DIR_PORTRAIT ÊúÆÁ + uint16_t HnPixel; //ˮƽ·½ÏòÏñËظöÊý£¬×î´óÈ¡Öµ1024 + uint16_t VnPixel; //´¹Ö±·½ÏòÏñËظöÊý£¬×î´óÈ¡Öµ 768 + uint8_t Hfp; //horizonal front porch£¬×î´óÈ¡Öµ32 + uint8_t Hbp; //horizonal back porch£¬ ×î´óÈ¡Öµ128 + uint8_t Vfp; //vertical front porch£¬ ×î´óÈ¡Öµ8 + uint8_t Vbp; //vertical back porch£¬ ×î´óÈ¡Öµ32 + uint8_t ClkDiv; //ϵͳʱÖÓ¾­ClkDiv·ÖƵºó²úÉúDOCCLK£¬0 2·ÖƵ 1 4·ÖƵ 2 6·ÖƵ ... ... 31 64·ÖƵ + uint8_t SamplEdge; //ÆÁÄ»ÔÚDOTCLKµÄÄĸö±ßÑزÉÑùÊý¾Ý£ºLCD_SAMPLEDGE_RISE¡¢LCD_SAMPLEDGE_FALL + uint8_t ClkAlways; //1 Ò»Ö±Êä³öDOTCLK 0 Ö»ÔÚ´«ÊäÊý¾ÝʱÊä³öDOTCLK + uint8_t HsyncWidth; //HSYNCµÍµçƽ³ÖÐø¶àÉÙ¸öDOTCLK£¬È¡Öµ£ºLCD_HSYNC_1DOTCLK¡¢LCD_HSYNC_2DOTCLK¡¢LCD_HSYNC_3DOTCLK¡¢LCD_HSYNC_4DOTCLK + + /* MPU£¨8080£©½Ó¿Ú²ÎÊý */ + uint8_t T_CSf_WRf; //CSnϽµÑص½WRnϽµÑصÄʱ¼ä£¬È¡Öµ0--3 + uint8_t T_WRnHold; //WRnµÍµçƽµÄ³ÖÐøʱ¼ä£¬ È¡Öµ0--7 + uint8_t T_WRr_CSr; //WRnÉÏÉýÑص½CSnÉÏÉýÑصÄʱ¼ä£¬È¡Öµ0--3 + uint8_t T_CSr_CSf; //CSnÉÏÉýÑص½CSnϽµÑصÄʱ¼ä£¬È¡Öµ0--7 + + uint8_t IntEOTEn; //End of Transter£¨´«ÊäÍê³É£©ÖжÏʹÄÜ +} LCD_InitStructure; + + +#define LCD_INTERFACE_RGB 0 +#define LCD_INTERFACE_I80 1 +#define LCD_INTERFACE_M68 2 + +#define LCD_DIR_LANDSCAPE 0 //ºáÆÁ +#define LCD_DIR_PORTRAIT 1 //ÊúÆÁ + +#define LCD_SAMPLEDGE_RISE 0 //ÆÁÄ»ÔÚDOTCLKµÄÉÏÉýÑزÉÑùÊý¾Ý +#define LCD_SAMPLEDGE_FALL 1 //ÆÁÄ»ÔÚDOTCLKµÄϽµÑزÉÑùÊý¾Ý + +#define LCD_HSYNC_1DOTCLK 0 //1¸öDOTCLK +#define LCD_HSYNC_2DOTCLK 1 +#define LCD_HSYNC_3DOTCLK 2 +#define LCD_HSYNC_4DOTCLK 3 + +#define LCD_CLKDIV_2 0 +#define LCD_CLKDIV_4 1 +#define LCD_CLKDIV_6 2 +#define LCD_CLKDIV_8 3 +#define LCD_CLKDIV_10 4 +#define LCD_CLKDIV_12 5 +#define LCD_CLKDIV_14 6 +#define LCD_CLKDIV_16 7 +#define LCD_CLKDIV_18 8 +#define LCD_CLKDIV_20 9 +#define LCD_CLKDIV_22 10 +#define LCD_CLKDIV_24 11 +#define LCD_CLKDIV_26 12 +#define LCD_CLKDIV_28 13 +#define LCD_CLKDIV_30 14 +#define LCD_CLKDIV_32 15 +#define LCD_CLKDIV_34 16 +#define LCD_CLKDIV_36 17 +#define LCD_CLKDIV_38 18 +#define LCD_CLKDIV_40 19 +#define LCD_CLKDIV_42 20 +#define LCD_CLKDIV_44 21 +#define LCD_CLKDIV_46 22 +#define LCD_CLKDIV_48 23 +#define LCD_CLKDIV_50 24 +#define LCD_CLKDIV_52 25 +#define LCD_CLKDIV_54 26 +#define LCD_CLKDIV_56 27 +#define LCD_CLKDIV_58 28 +#define LCD_CLKDIV_60 29 +#define LCD_CLKDIV_62 30 +#define LCD_CLKDIV_64 31 + + +void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct); +void LCD_Start(LCD_TypeDef *LCDx); +uint32_t LCD_IsBusy(LCD_TypeDef *LCDx); + +void LCD_I80_WriteReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val[], uint16_t cnt); +void LCD_I80_WriteOneReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val); +void LCD_I80_WriteData(LCD_TypeDef *LCDx, uint16_t data[], uint16_t cnt); +void LCD_I80_WriteOneData(LCD_TypeDef *LCDx, uint16_t val); + +void LCD_INTEn(LCD_TypeDef *LCDx); +void LCD_INTDis(LCD_TypeDef *LCDx); +void LCD_INTClr(LCD_TypeDef *LCDx); +uint32_t LCD_INTStat(LCD_TypeDef *LCDx); + + +#endif //__SWM320_LCD_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c new file mode 100644 index 0000000000..0d183cee36 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c @@ -0,0 +1,174 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_norflash.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄNOR FlashÇý¶¯³ÌÐò +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_norflash.h" + + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: NORFL_Init() +* ¹¦ÄÜ˵Ã÷: NOR Flash¿ØÖÆÆ÷³õʼ»¯ +* Êä Èë: NORFL_InitStructure * initStruct °üº¬NOR Flash¿ØÖÆÆ÷Ïà¹ØÉ趨ֵµÄ½á¹¹Ìå +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void NORFL_Init(NORFL_InitStructure *initStruct) +{ + uint32_t i; + + // ÅäÖÃSRAMÇ°ÐèҪˢÐÂÏÂSDRAM¿ØÖÆÆ÷ + do + { + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + + while (SDRAMC->REFDONE == 0); + SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); + + for (i = 0; i < 1000; i++) __NOP(); + SYS->CLKEN &= ~(1 << SYS_CLKEN_SDRAM_Pos); + } + while (0); + + SYS->CLKEN |= (1 << SYS_CLKEN_NORFL_Pos); + + NORFLC->CR = ((initStruct->DataWidth == 8 ? 1 : 0) << NORFLC_CR_BYTEIF_Pos) | + (initStruct->WELowPulseTime << NORFLC_CR_WRTIME_Pos) | + (initStruct->OEPreValidTime << NORFLC_CR_RDTIME_Pos); + + NORFLC->IE = 3; + NORFLC->IF = 3; // Çå³ýÖжϱêÖ¾ + if (initStruct->OperFinishIEn) NORFLC->IM &= ~(1 << NORFLC_IM_FINISH_Pos); + else NORFLC->IM |= (1 << NORFLC_IM_FINISH_Pos); + if (initStruct->OperTimeoutIEn) NORFLC->IM &= ~(1 << NORFLC_IM_TIMEOUT_Pos); + else NORFLC->IM |= (1 << NORFLC_IM_TIMEOUT_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: NORFL_ChipErase() +* ¹¦ÄÜ˵Ã÷: NOR FlashÕûƬ²Á³ý +* Êä Èë: ÎÞ +* Êä ³ö: uint32_t 0 ²Á³ý³É¹¦ 1 ²Á³ý³¬Ê± +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t NORFL_ChipErase(void) +{ + uint32_t res; + + NORFLC->CMD = (NORFL_CMD_CHIP_ERASE << NORFLC_CMD_CMD_Pos); + + while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + + if (NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; + else res = 1; + + NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; + + return res; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: NORFL_SectorErase() +* ¹¦ÄÜ˵Ã÷: NOR FlashÉÈÇø²Á³ý +* Êä Èë: uint32_t addr Òª²Á³ýÉÈÇøµÄÆðʼµØÖ· +* Êä ³ö: uint32_t 0 ²Á³ý³É¹¦ 1 ²Á³ý³¬Ê± +* ×¢ÒâÊÂÏî: MX29LV128DB Ç°8ÉÈÇøΪ8K¡¢ºó255ÉÈÇøΪ64K MX29LV128DT Ç°255ÉÈÇøΪ64K¡¢ºó8ÉÈÇøΪ8K +******************************************************************************************************************************************/ +uint32_t NORFL_SectorErase(uint32_t addr) +{ + uint32_t res; + + NORFLC->ADDR = addr; + NORFLC->CMD = (NORFL_CMD_SECTOR_ERASE << NORFLC_CMD_CMD_Pos); + + while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + + if (NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; + else res = 1; + + NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; + + return res; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: NORFL_Write() +* ¹¦ÄÜ˵Ã÷: NOR Flashд +* Êä Èë: uint32_t addr Êý¾ÝҪдÈëµÄµØÖ· +* uint32_t data ҪдÈëµÄÊý¾Ý +* Êä ³ö: uint32_t 0 дÈë³É¹¦ 1 дÈ볬ʱ +* ×¢ÒâÊÂÏî: Ó²¼þÁ¬½Ó£¬Êý¾ÝÏßΪ16λʱ£¬°ë×ÖдÈ룻Êý¾ÝÏßΪ8λʱ£¬×Ö½ÚдÈë +******************************************************************************************************************************************/ +uint32_t NORFL_Write(uint32_t addr, uint32_t data) +{ + uint32_t res; + + NORFLC->ADDR = addr; + NORFLC->CMD = (NORFL_CMD_PROGRAM << NORFLC_CMD_CMD_Pos) | (data << NORFLC_CMD_DATA_Pos); + + while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + + if (NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; + else res = 1; + + NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; + + return res; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: NORFL_Read() +* ¹¦ÄÜ˵Ã÷: NOR Flash¶Á +* Êä Èë: uint32_t addr Êý¾ÝÒª¶Á³öµÄµØÖ· +* Êä ³ö: uint32_t ¶Á³öµÄÊý¾Ý +* ×¢ÒâÊÂÏî: Ó²¼þÁ¬½Ó£¬Êý¾ÝÏßΪ16λʱ£¬°ë×Ö¶Á³ö£»Êý¾ÝÏßΪ8λʱ£¬×Ö½Ú¶Á³ö +******************************************************************************************************************************************/ +uint32_t NORFL_Read(uint32_t addr) +{ + NORFLC->ADDR = addr; + NORFLC->CMD = (NORFL_CMD_READ << NORFLC_CMD_CMD_Pos); + + return (NORFLC->CMD & NORFLC_CMD_DATA_Msk); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: NORFL_ReadID() +* ¹¦ÄÜ˵Ã÷: NOR Flash¶ÁID +* Êä Èë: uint32_t id_addr IDµØÖ·£¬´Ë²ÎÊýÊÇоƬÏà¹ØµÄ£¬Ã¿ÖÖоƬ¶¼²»Í¬ +* Êä ³ö: uint16_t ¶ÁÈ¡µ½µÄID +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint16_t NORFL_ReadID(uint32_t id_addr) +{ + uint16_t id; + + NORFLC->CMD = (NORFL_CMD_AUTO_SELECT << NORFLC_CMD_CMD_Pos); + + NORFLC->ADDR = id_addr; + NORFLC->CMD = (NORFL_CMD_READ << NORFLC_CMD_CMD_Pos); + + id = NORFLC->CMD & NORFLC_CMD_DATA_Msk; + + NORFLC->CMD = (NORFL_CMD_RESET << NORFLC_CMD_CMD_Pos); // Í˳öID¶Áȡģʽ + + return id; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h new file mode 100644 index 0000000000..fc859268fb --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h @@ -0,0 +1,39 @@ +#ifndef __SWM320_NORFLASH_H__ +#define __SWM320_NORFLASH_H__ + +typedef struct +{ + uint8_t DataWidth; // 8¡¢16 + + uint8_t WELowPulseTime; // WE# pulse width£¬µ¥Î»ÎªÏµÍ³Ê±ÖÓÖÜÆÚ£¬×î´óֵΪ7 + uint8_t OEPreValidTime; // Valid data output after OE# low£¬µ¥Î»ÎªÏµÍ³Ê±ÖÓÖÜÆÚ£¬×î´óֵΪ15 + + uint8_t OperFinishIEn; // ²Ù×÷(дÈë¡¢²Á³ý)Íê³ÉÖжÏʹÄÜ + uint8_t OperTimeoutIEn; +} NORFL_InitStructure; + + + +void NORFL_Init(NORFL_InitStructure *initStruct); +uint32_t NORFL_ChipErase(void); +uint32_t NORFL_SectorErase(uint32_t addr); +uint32_t NORFL_Write(uint32_t addr, uint32_t data); +uint32_t NORFL_Read(uint32_t addr); +uint16_t NORFL_ReadID(uint32_t id_addr); + + +/* µ±Ç°°æ±¾×ÜÏ߶ÁÖ»Ö§³Ö×Ö¶Á +#define NORFL_Read8(addr) *((volatile uint8_t *)(NORFLM_BASE + addr)) +#define NORFL_Read16(addr) *((volatile uint16_t *)(NORFLM_BASE + addr)) */ +#define NORFL_Read32(addr) *((volatile uint32_t *)(NORFLM_BASE + addr)) + + + +#define NORFL_CMD_READ 0 +#define NORFL_CMD_RESET 1 +#define NORFL_CMD_AUTO_SELECT 2 +#define NORFL_CMD_PROGRAM 3 +#define NORFL_CMD_CHIP_ERASE 4 +#define NORFL_CMD_SECTOR_ERASE 5 + +#endif // __SWM320_NORFLASH_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c new file mode 100644 index 0000000000..bc7a555a30 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c @@ -0,0 +1,221 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_port.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄ¶Ë¿ÚÒý½Å¹¦ÄÜÑ¡Ôñ¿âº¯Êý +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_port.h" + + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: PORT_Init() +* ¹¦ÄÜ˵Ã÷: ¶Ë¿ÚÒý½Å¹¦ÄÜÑ¡Ôñ£¬¿ÉÓõŦÄܼû"SWM320_port.h"Îļþ +* Êä Èë: uint32_t PORTx Ö¸¶¨PORT¶Ë¿Ú£¬ÓÐЧֵ°üÀ¨PORTA¡¢PORTB¡¢PORTC¡¢PORTM¡¢PORTN¡¢PORTP +* uint32_t n Ö¸¶¨PORTÒý½Å£¬ÓÐЧֵ°üÀ¨PIN0¡¢PIN1¡¢PIN2¡¢... ... PIN22¡¢PIN23 +* uint32_t func Ö¸¶¨¶Ë¿ÚÒý½ÅÒªÉ趨µÄ¹¦ÄÜ£¬Æä¿ÉÈ¡Öµ¼û"SWM320_port.h"Îļþ +* uint32_t digit_in_en Êý×ÖÊäÈëʹÄÜ +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: µ±Òý½Å±êºÅnΪżÊýʱ£¬funcÈ¡ÖµÖ»ÄÜÊÇFUNMUX0¿ªÍ·µÄ£¬ÈçFUNMUX0_UART0_RXD +* µ±Òý½Å±êºÅnΪÆæÊýʱ£¬funcÈ¡ÖµÖ»ÄÜÊÇFUNMUX1¿ªÍ·µÄ£¬ÈçFUNMUX1_UART0_TXD +******************************************************************************************************************************************/ +void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en) +{ + switch ((uint32_t)PORTx) + { + case ((uint32_t)PORTA): + if (func > 99) + { + if (n < PIN6) + { + PORT->PORTA_MUX0 &= ~(0x1F << (n * 5)); + PORT->PORTA_MUX0 |= (func - 100) << (n * 5); + } + else if (n < PIN12) + { + PORT->PORTA_MUX1 &= ~(0x1F << ((n - 6) * 5)); + PORT->PORTA_MUX1 |= (func - 100) << ((n - 6) * 5); + } + } + + PORT->PORTA_SEL &= ~(0x03 << (n * 2)); + PORT->PORTA_SEL |= (func > 99 ? 1 : func) << (n * 2); + + PORT->PORTA_INEN &= ~(0x01 << n); + PORT->PORTA_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTB): + if (func > 99) + { + if (n < PIN6) + { + PORT->PORTB_MUX0 &= ~(0x1F << (n * 5)); + PORT->PORTB_MUX0 |= (func - 100) << (n * 5); + } + else if (n < PIN12) + { + PORT->PORTB_MUX1 &= ~(0x1F << ((n - 6) * 5)); + PORT->PORTB_MUX1 |= (func - 100) << ((n - 6) * 5); + } + } + + PORT->PORTB_SEL &= ~(0x03 << (n * 2)); + PORT->PORTB_SEL |= (func > 99 ? 1 : func) << (n * 2); + + PORT->PORTB_INEN &= ~(0x01 << n); + PORT->PORTB_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTC): + if (func > 99) + { + if (n < PIN6) + { + PORT->PORTC_MUX0 &= ~(0x1F << (n * 5)); + PORT->PORTC_MUX0 |= (func - 100) << (n * 5); + } + else if (n < PIN12) + { + PORT->PORTC_MUX1 &= ~(0x1F << ((n - 6) * 5)); + PORT->PORTC_MUX1 |= (func - 100) << ((n - 6) * 5); + } + } + + PORT->PORTC_SEL &= ~(0x03 << (n * 2)); + PORT->PORTC_SEL |= (func > 99 ? 1 : func) << (n * 2); + + PORT->PORTC_INEN &= ~(0x01 << n); + PORT->PORTC_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTM): + if (func > 99) + { + if (n < PIN6) + { + PORT->PORTM_MUX0 &= ~(0x1F << (n * 5)); + PORT->PORTM_MUX0 |= (func - 100) << (n * 5); + } + else if (n < PIN12) + { + PORT->PORTM_MUX1 &= ~(0x1F << ((n - 6) * 5)); + PORT->PORTM_MUX1 |= (func - 100) << ((n - 6) * 5); + } + else if (n < PIN18) + { + PORT->PORTM_MUX2 &= ~(0x1F << ((n - 12) * 5)); + PORT->PORTM_MUX2 |= (func - 100) << ((n - 12) * 5); + } + else if (n < PIN24) + { + PORT->PORTM_MUX3 &= ~(0x1F << ((n - 18) * 5)); + PORT->PORTM_MUX3 |= (func - 100) << ((n - 18) * 5); + } + } + + if (n < 16) + { + PORT->PORTM_SEL0 &= ~(0x03 << (n * 2)); + PORT->PORTM_SEL0 |= (func > 99 ? 1 : func) << (n * 2); + } + else + { + PORT->PORTM_SEL1 &= ~(0x03 << ((n - 16) * 2)); + PORT->PORTM_SEL1 |= (func > 99 ? 1 : func) << ((n - 16) * 2); + } + + PORT->PORTM_INEN &= ~(0x01 << n); + PORT->PORTM_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTN): + if (func > 99) + { + if (n < PIN6) + { + PORT->PORTN_MUX0 &= ~(0x1F << (n * 5)); + PORT->PORTN_MUX0 |= (func - 100) << (n * 5); + } + else if (n < PIN12) + { + PORT->PORTN_MUX1 &= ~(0x1F << ((n - 6) * 5)); + PORT->PORTN_MUX1 |= (func - 100) << ((n - 6) * 5); + } + else if (n < PIN18) + { + PORT->PORTN_MUX2 &= ~(0x1F << ((n - 12) * 5)); + PORT->PORTN_MUX2 |= (func - 100) << ((n - 12) * 5); + } + } + + if (n < 16) + { + PORT->PORTN_SEL0 &= ~(0x03 << (n * 2)); + PORT->PORTN_SEL0 |= (func > 99 ? 1 : func) << (n * 2); + } + else + { + PORT->PORTN_SEL1 &= ~(0x03 << ((n - 16) * 2)); + PORT->PORTN_SEL1 |= (func > 99 ? 1 : func) << ((n - 16) * 2); + } + + PORT->PORTN_INEN &= ~(0x01 << n); + PORT->PORTN_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTP): + if (func > 99) + { + if (n < PIN6) + { + PORT->PORTP_MUX0 &= ~(0x1F << (n * 5)); + PORT->PORTP_MUX0 |= (func - 100) << (n * 5); + } + else if (n < PIN12) + { + PORT->PORTP_MUX1 &= ~(0x1F << ((n - 6) * 5)); + PORT->PORTP_MUX1 |= (func - 100) << ((n - 6) * 5); + } + else if (n < PIN18) + { + PORT->PORTP_MUX2 &= ~(0x1F << ((n - 12) * 5)); + PORT->PORTP_MUX2 |= (func - 100) << ((n - 12) * 5); + } + else if (n < PIN24) + { + PORT->PORTP_MUX3 &= ~(0x1F << ((n - 18) * 5)); + PORT->PORTP_MUX3 |= (func - 100) << ((n - 18) * 5); + } + } + + if (n < 16) + { + PORT->PORTP_SEL0 &= ~(0x03 << (n * 2)); + PORT->PORTP_SEL0 |= (func > 99 ? 1 : func) << (n * 2); + } + else + { + PORT->PORTP_SEL1 &= ~(0x03 << ((n - 16) * 2)); + PORT->PORTP_SEL1 |= (func > 99 ? 1 : func) << ((n - 16) * 2); + } + + PORT->PORTP_INEN &= ~(0x01 << n); + PORT->PORTP_INEN |= (digit_in_en << n); + break; + } +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h new file mode 100644 index 0000000000..ff0fd9cdc9 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h @@ -0,0 +1,482 @@ +#ifndef __SWM320_PORT_H__ +#define __SWM320_PORT_H__ + +void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en); //¶Ë¿ÚÒý½Å¹¦ÄÜÑ¡Ôñ£¬Æä¿ÉÈ¡ÖµÈçÏ£º + +#define PORTA 0 +#define PORTB 1 +#define PORTC 2 +#define PORTM 3 +#define PORTN 4 +#define PORTP 5 + +#define PORTA_PIN0_GPIO 0 +#define PORTA_PIN0_FUNMUX 1 +#define PORTA_PIN0_SWCLK 2 + +#define PORTA_PIN1_GPIO 0 +#define PORTA_PIN1_FUNMUX 1 +#define PORTA_PIN1_SWDIO 2 + +#define PORTA_PIN2_GPIO 0 +#define PORTA_PIN2_FUNMUX 1 + +#define PORTA_PIN3_GPIO 0 +#define PORTA_PIN3_FUNMUX 1 + +#define PORTA_PIN4_GPIO 0 +#define PORTA_PIN4_FUNMUX 1 + +#define PORTA_PIN5_GPIO 0 +#define PORTA_PIN5_FUNMUX 1 + +#define PORTA_PIN6_GPIO 0 +#define PORTA_PIN6_FUNMUX 1 + +#define PORTA_PIN7_GPIO 0 +#define PORTA_PIN7_FUNMUX 1 + +#define PORTA_PIN8_GPIO 0 +#define PORTA_PIN8_FUNMUX 1 + +#define PORTA_PIN9_GPIO 0 +#define PORTA_PIN9_FUNMUX 1 +#define PORTA_PIN9_ADC0_IN7 3 + +#define PORTA_PIN10_GPIO 0 +#define PORTA_PIN10_FUNMUX 1 +#define PORTA_PIN10_ADC0_IN6 3 + +#define PORTA_PIN11_GPIO 0 +#define PORTA_PIN11_FUNMUX 1 +#define PORTA_PIN11_ADC0_IN5 3 + +#define PORTA_PIN12_GPIO 0 +#define PORTA_PIN12_ADC0_IN4 3 + + +#define PORTB_PIN0_GPIO 0 +#define PORTB_PIN0_FUNMUX 1 +#define PORTB_PIN0_SD_DETECT 2 + +#define PORTB_PIN1_GPIO 0 +#define PORTB_PIN1_FUNMUX 1 +#define PORTB_PIN1_SD_CLK 2 + +#define PORTB_PIN2_GPIO 0 +#define PORTB_PIN2_FUNMUX 1 +#define PORTB_PIN2_SD_CMD 2 + +#define PORTB_PIN3_GPIO 0 +#define PORTB_PIN3_FUNMUX 1 +#define PORTB_PIN3_SD_D0 2 + +#define PORTB_PIN4_GPIO 0 +#define PORTB_PIN4_FUNMUX 1 +#define PORTB_PIN4_SD_D1 2 + +#define PORTB_PIN5_GPIO 0 +#define PORTB_PIN5_FUNMUX 1 +#define PORTB_PIN5_SD_D2 2 + +#define PORTB_PIN6_GPIO 0 +#define PORTB_PIN6_FUNMUX 1 +#define PORTB_PIN6_SD_D3 2 + +#define PORTB_PIN7_GPIO 0 +#define PORTB_PIN7_FUNMUX 1 +#define PORTB_PIN7_SD_D4 2 + +#define PORTB_PIN8_GPIO 0 +#define PORTB_PIN8_FUNMUX 1 +#define PORTB_PIN8_SD_D5 2 + +#define PORTB_PIN9_GPIO 0 +#define PORTB_PIN9_FUNMUX 1 +#define PORTB_PIN9_SD_D6 2 + +#define PORTB_PIN10_GPIO 0 +#define PORTB_PIN10_FUNMUX 1 +#define PORTB_PIN10_SD_D7 2 + +#define PORTB_PIN11_GPIO 0 +#define PORTB_PIN11_FUNMUX 1 + +#define PORTB_PIN12_GPIO 0 + + +#define PORTC_PIN0_GPIO 0 +#define PORTC_PIN0_FUNMUX 1 + +#define PORTC_PIN1_GPIO 0 +#define PORTC_PIN1_FUNMUX 1 + +#define PORTC_PIN2_GPIO 0 +#define PORTC_PIN2_FUNMUX 1 + +#define PORTC_PIN3_GPIO 0 +#define PORTC_PIN3_FUNMUX 1 + +#define PORTC_PIN4_GPIO 0 +#define PORTC_PIN4_FUNMUX 1 +#define PORTC_PIN4_ADC1_IN3 3 + +#define PORTC_PIN5_GPIO 0 +#define PORTC_PIN5_FUNMUX 1 +#define PORTC_PIN5_ADC1_IN2 3 + +#define PORTC_PIN6_GPIO 0 +#define PORTC_PIN6_FUNMUX 1 +#define PORTC_PIN6_ADC1_IN1 3 + +#define PORTC_PIN7_GPIO 0 +#define PORTC_PIN7_FUNMUX 1 +#define PORTC_PIN7_ADC1_IN0 3 + + +#define PORTM_PIN0_GPIO 0 +#define PORTM_PIN0_FUNMUX 1 +#define PORTM_PIN0_NORFL_D15 2 + +#define PORTM_PIN1_GPIO 0 +#define PORTM_PIN1_FUNMUX 1 +#define PORTM_PIN1_NORFL_D14 2 + +#define PORTM_PIN2_GPIO 0 +#define PORTM_PIN2_FUNMUX 1 +#define PORTM_PIN2_NORFL_D13 2 + +#define PORTM_PIN3_GPIO 0 +#define PORTM_PIN3_FUNMUX 1 +#define PORTM_PIN3_NORFL_D12 2 + +#define PORTM_PIN4_GPIO 0 +#define PORTM_PIN4_FUNMUX 1 +#define PORTM_PIN4_NORFL_D11 2 + +#define PORTM_PIN5_GPIO 0 +#define PORTM_PIN5_FUNMUX 1 +#define PORTM_PIN5_NORFL_D10 2 + +#define PORTM_PIN6_GPIO 0 +#define PORTM_PIN6_FUNMUX 1 +#define PORTM_PIN6_NORFL_D9 2 + +#define PORTM_PIN7_GPIO 0 +#define PORTM_PIN7_FUNMUX 1 +#define PORTM_PIN7_NORFL_D8 2 + +#define PORTM_PIN8_GPIO 0 +#define PORTM_PIN8_FUNMUX 1 +#define PORTM_PIN8_NORFL_D7 2 + +#define PORTM_PIN9_GPIO 0 +#define PORTM_PIN9_FUNMUX 1 +#define PORTM_PIN9_NORFL_D6 2 + +#define PORTM_PIN10_GPIO 0 +#define PORTM_PIN10_FUNMUX 1 +#define PORTM_PIN10_NORFL_D5 2 + +#define PORTM_PIN11_GPIO 0 +#define PORTM_PIN11_FUNMUX 1 +#define PORTM_PIN11_NORFL_D4 2 + +#define PORTM_PIN12_GPIO 0 +#define PORTM_PIN12_FUNMUX 1 +#define PORTM_PIN12_NORFL_D3 2 + +#define PORTM_PIN13_GPIO 0 +#define PORTM_PIN13_FUNMUX 1 +#define PORTM_PIN13_NORFL_D2 2 + +#define PORTM_PIN14_GPIO 0 +#define PORTM_PIN14_FUNMUX 1 +#define PORTM_PIN14_NORFL_D1 2 + +#define PORTM_PIN15_GPIO 0 +#define PORTM_PIN15_FUNMUX 1 +#define PORTM_PIN15_NORFL_D0 2 + +#define PORTM_PIN16_GPIO 0 +#define PORTM_PIN16_FUNMUX 1 +#define PORTM_PIN16_NORFL_OEN 2 + +#define PORTM_PIN17_GPIO 0 +#define PORTM_PIN17_FUNMUX 1 +#define PORTM_PIN17_NORFL_WEN 2 + +#define PORTM_PIN18_GPIO 0 +#define PORTM_PIN18_FUNMUX 1 +#define PORTM_PIN18_NORFL_CSN 2 + +#define PORTM_PIN19_GPIO 0 +#define PORTM_PIN19_FUNMUX 1 +#define PORTM_PIN19_SDRAM_CSN 2 + +#define PORTM_PIN20_GPIO 0 +#define PORTM_PIN20_FUNMUX 1 +#define PORTM_PIN20_SRAM_CSN 2 + +#define PORTM_PIN21_GPIO 0 +#define PORTM_PIN21_FUNMUX 1 +#define PORTM_PIN21_SDRAM_CKE 2 + + +#define PORTN_PIN0_GPIO 0 +#define PORTN_PIN0_FUNMUX 1 +#define PORTN_PIN0_LCD_D0 2 +#define PORTN_PIN0_ADC1_IN4 3 + +#define PORTN_PIN1_GPIO 0 +#define PORTN_PIN1_FUNMUX 1 +#define PORTN_PIN1_LCD_D1 2 +#define PORTN_PIN1_ADC1_IN5 3 + +#define PORTN_PIN2_GPIO 0 +#define PORTN_PIN2_FUNMUX 1 +#define PORTN_PIN2_LCD_D2 2 +#define PORTN_PIN2_ADC1_IN6 3 + +#define PORTN_PIN3_GPIO 0 +#define PORTN_PIN3_FUNMUX 1 +#define PORTN_PIN3_LCD_D3 2 + +#define PORTN_PIN4_GPIO 0 +#define PORTN_PIN4_FUNMUX 1 +#define PORTN_PIN4_LCD_D4 2 + +#define PORTN_PIN5_GPIO 0 +#define PORTN_PIN5_FUNMUX 1 +#define PORTN_PIN5_LCD_D5 2 + +#define PORTN_PIN6_GPIO 0 +#define PORTN_PIN6_FUNMUX 1 +#define PORTN_PIN6_LCD_D6 2 + +#define PORTN_PIN7_GPIO 0 +#define PORTN_PIN7_FUNMUX 1 +#define PORTN_PIN7_LCD_D7 2 + +#define PORTN_PIN8_GPIO 0 +#define PORTN_PIN8_FUNMUX 1 +#define PORTN_PIN8_LCD_D8 2 + +#define PORTN_PIN9_GPIO 0 +#define PORTN_PIN9_FUNMUX 1 +#define PORTN_PIN9_LCD_D9 2 + +#define PORTN_PIN10_GPIO 0 +#define PORTN_PIN10_FUNMUX 1 +#define PORTN_PIN10_LCD_D10 2 + +#define PORTN_PIN11_GPIO 0 +#define PORTN_PIN11_FUNMUX 1 +#define PORTN_PIN11_LCD_D11 2 + +#define PORTN_PIN12_GPIO 0 +#define PORTN_PIN12_FUNMUX 1 +#define PORTN_PIN12_LCD_D12 2 + +#define PORTN_PIN13_GPIO 0 +#define PORTN_PIN13_FUNMUX 1 +#define PORTN_PIN13_LCD_D13 2 + +#define PORTN_PIN14_GPIO 0 +#define PORTN_PIN14_FUNMUX 1 +#define PORTN_PIN14_LCD_D14 2 + +#define PORTN_PIN15_GPIO 0 +#define PORTN_PIN15_FUNMUX 1 +#define PORTN_PIN15_LCD_D15 2 + +#define PORTN_PIN16_GPIO 0 +#define PORTN_PIN16_FUNMUX 1 +#define PORTN_PIN16_LCD_RD 2 +#define PORTN_PIN16_LCD_DOTCK 2 + +#define PORTN_PIN17_GPIO 0 +#define PORTN_PIN17_FUNMUX 1 +#define PORTN_PIN17_LCD_CS 2 +#define PORTN_PIN17_LCD_VSYNC 2 + +#define PORTN_PIN18_GPIO 0 +#define PORTN_PIN18_LCD_RS 2 +#define PORTN_PIN18_LCD_DATEN 2 //Data Enable + +#define PORTN_PIN19_GPIO 0 +#define PORTN_PIN19_LCD_WR 2 +#define PORTN_PIN19_LCD_HSYNC 2 + + +#define PORTP_PIN0_GPIO 0 +#define PORTP_PIN0_FUNMUX 1 +#define PORTP_PIN0_NORFL_A0 2 + +#define PORTP_PIN1_GPIO 0 +#define PORTP_PIN1_FUNMUX 1 +#define PORTP_PIN1_NORFL_A1 2 + +#define PORTP_PIN2_GPIO 0 +#define PORTP_PIN2_FUNMUX 1 +#define PORTP_PIN2_NORFL_A2 2 +#define PORTP_PIN2_SD_D7 3 + +#define PORTP_PIN3_GPIO 0 +#define PORTP_PIN3_FUNMUX 1 +#define PORTP_PIN3_NORFL_A3 2 +#define PORTP_PIN3_SD_D6 3 + +#define PORTP_PIN4_GPIO 0 +#define PORTP_PIN4_FUNMUX 1 +#define PORTP_PIN4_NORFL_A4 2 +#define PORTP_PIN4_SD_D5 3 + +#define PORTP_PIN5_GPIO 0 +#define PORTP_PIN5_FUNMUX 1 +#define PORTP_PIN5_NORFL_A5 2 +#define PORTP_PIN5_SD_D4 3 + +#define PORTP_PIN6_GPIO 0 +#define PORTP_PIN6_FUNMUX 1 +#define PORTP_PIN6_NORFL_A6 2 +#define PORTP_PIN6_SD_D3 3 + +#define PORTP_PIN7_GPIO 0 +#define PORTP_PIN7_FUNMUX 1 +#define PORTP_PIN7_NORFL_A7 2 +#define PORTP_PIN7_SD_D2 3 + +#define PORTP_PIN8_GPIO 0 +#define PORTP_PIN8_FUNMUX 1 +#define PORTP_PIN8_NORFL_A8 2 +#define PORTP_PIN8_SD_D1 3 + +#define PORTP_PIN9_GPIO 0 +#define PORTP_PIN9_FUNMUX 1 +#define PORTP_PIN9_NORFL_A9 2 +#define PORTP_PIN9_SD_D0 3 + +#define PORTP_PIN10_GPIO 0 +#define PORTP_PIN10_FUNMUX 1 +#define PORTP_PIN10_NORFL_A10 2 +#define PORTP_PIN10_SD_CMD 3 + +#define PORTP_PIN11_GPIO 0 +#define PORTP_PIN11_FUNMUX 1 +#define PORTP_PIN11_NORFL_A11 2 +#define PORTP_PIN11_SD_CLK 3 + +#define PORTP_PIN12_GPIO 0 +#define PORTP_PIN12_FUNMUX 1 +#define PORTP_PIN12_NORFL_A12 2 +#define PORTP_PIN12_SD_DETECT 3 + +#define PORTP_PIN13_GPIO 0 +#define PORTP_PIN13_FUNMUX 1 +#define PORTP_PIN13_NORFL_A13 2 +#define PORTP_PIN13_SDRAM_CLK 2 + +#define PORTP_PIN14_GPIO 0 +#define PORTP_PIN14_FUNMUX 1 +#define PORTP_PIN14_NORFL_A14 2 +#define PORTP_PIN14_SDRAM_CAS 2 + +#define PORTP_PIN15_GPIO 0 +#define PORTP_PIN15_FUNMUX 1 +#define PORTP_PIN15_NORFL_A15 2 +#define PORTP_PIN15_SDRAM_RAS 2 + +#define PORTP_PIN16_GPIO 0 +#define PORTP_PIN16_FUNMUX 1 +#define PORTP_PIN16_NORFL_A16 2 +#define PORTP_PIN16_SDRAM_LDQ 2 + +#define PORTP_PIN17_GPIO 0 +#define PORTP_PIN17_FUNMUX 1 +#define PORTP_PIN17_NORFL_A17 2 +#define PORTP_PIN17_SDRAM_UDQ 2 + +#define PORTP_PIN18_GPIO 0 +#define PORTP_PIN18_FUNMUX 1 +#define PORTP_PIN18_NORFL_A18 2 + +#define PORTP_PIN19_GPIO 0 +#define PORTP_PIN19_FUNMUX 1 +#define PORTP_PIN19_NORFL_A19 2 + +#define PORTP_PIN20_GPIO 0 +#define PORTP_PIN20_FUNMUX 1 +#define PORTP_PIN20_NORFL_A20 2 +#define PORTP_PIN20_SDRAM_BA0 2 + +#define PORTP_PIN21_GPIO 0 +#define PORTP_PIN21_FUNMUX 1 +#define PORTP_PIN21_NORFL_A21 2 +#define PORTP_PIN21_SDRAM_BA1 2 + +#define PORTP_PIN22_GPIO 0 +#define PORTP_PIN22_FUNMUX 1 +#define PORTP_PIN22_NORFL_A22 2 + +#define PORTP_PIN23_GPIO 0 +#define PORTP_PIN23_FUNMUX 1 +#define PORTP_PIN23_NORFL_A23 2 + + + +/* ÏÂÃæºê¶¨ÒåµÄȡֵȫ²¿ÔÚÕýÈ·ÖµµÄ»ù´¡ÉÏ¡°¼Ó100¡±£¬ÒÔÇø·ÖÉÏÃæºê¶¨ÒåµÄÖµ£¬´Ó¶ø·½±ã¿âº¯ÊýµÄ±àд*/ +/* ÏÂÃæÕâЩֵÊÇżÊý±àºÅÒý½ÅµÄ¹¦ÄÜÈ¡Öµ£¬ÈçPIN0¡¢PIN2¡¢... */ +#define FUNMUX0_UART0_RXD 100 +#define FUNMUX0_UART1_RXD 101 +#define FUNMUX0_UART2_RXD 102 +#define FUNMUX0_UART3_RXD 103 +#define FUNMUX0_I2C0_SCL 105 +#define FUNMUX0_I2C1_SCL 106 +#define FUNMUX0_PWM0A_OUT 107 +#define FUNMUX0_PWM2A_OUT 108 +#define FUNMUX0_PWM4A_OUT 109 +#define FUNMUX0_PWM0B_OUT 110 +#define FUNMUX0_PWM2B_OUT 111 +#define FUNMUX0_PWM4B_OUT 112 +#define FUNMUX0_PWM_BREAK 113 +#define FUNMUX0_TIMR0_IN 114 +#define FUNMUX0_TIMR2_IN 115 +#define FUNMUX0_CAN_RX 116 +#define FUNMUX0_SPI0_SSEL 117 +#define FUNMUX0_SPI0_MOSI 118 +#define FUNMUX0_SPI1_SSEL 119 +#define FUNMUX0_SPI1_MOSI 120 +#define FUNMUX0_UART0_CTS 121 +#define FUNMUX0_UART1_CTS 122 +#define FUNMUX0_UART2_CTS 123 +#define FUNMUX0_UART3_CTS 124 + +/* ÏÂÃæÕâЩֵÊÇÆæÊý±àºÅÒý½ÅµÄ¹¦ÄÜÈ¡Öµ£¬ÈçPIN1¡¢PIN3¡¢... */ +#define FUNMUX1_UART0_TXD 100 +#define FUNMUX1_UART1_TXD 101 +#define FUNMUX1_UART2_TXD 102 +#define FUNMUX1_UART3_TXD 103 +#define FUNMUX1_I2C0_SDA 105 +#define FUNMUX1_I2C1_SDA 106 +#define FUNMUX1_PWM1A_OUT 107 +#define FUNMUX1_PWM3A_OUT 108 +#define FUNMUX1_PWM5A_OUT 109 +#define FUNMUX1_PWM1B_OUT 110 +#define FUNMUX1_PWM3B_OUT 111 +#define FUNMUX1_PWM5B_OUT 112 +#define FUNMUX1_PULSE_IN 113 +#define FUNMUX1_TIMR1_IN 114 +#define FUNMUX1_TIMR3_IN 115 +#define FUNMUX1_CAN_TX 116 +#define FUNMUX1_SPI0_SCLK 117 +#define FUNMUX1_SPI0_MISO 118 +#define FUNMUX1_SPI1_SCLK 119 +#define FUNMUX1_SPI1_MISO 120 +#define FUNMUX1_UART0_RTS 121 +#define FUNMUX1_UART1_RTS 122 +#define FUNMUX1_UART2_RTS 123 +#define FUNMUX1_UART3_RTS 124 + + +#endif //__SWM320_PORT_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c new file mode 100644 index 0000000000..454d19e197 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c @@ -0,0 +1,744 @@ +/****************************************************************************************************************************************** +* 文件å称: SWM320_pwm.c +* 功能说明: SWM320å•ç‰‡æœºçš„PWM功能驱动库 +* 技术支æŒ: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注æ„事项: +* 版本日期: V1.1.0 2017å¹´10月25æ—¥ +* å‡çº§è®°å½•: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_pwm.h" + +/****************************************************************************************************************************************** +* 函数å称: PWM_Init() +* 功能说明: PWMåˆå§‹åŒ– +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* PWM_InitStructure * initStruct 包å«PWM相关设定值的结构体 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void PWM_Init(PWM_TypeDef *PWMx, PWM_InitStructure *initStruct) +{ + uint32_t bit_offset = 0; + + SYS->CLKEN |= (0x01 << SYS_CLKEN_PWM_Pos); + + SYS->CLKDIV &= ~SYS_CLKDIV_PWM_Msk; + SYS->CLKDIV |= (initStruct->clk_div << SYS_CLKDIV_PWM_Pos); + + PWM_Stop(PWMx, 1, 1); //一些关键寄存器åªèƒ½åœ¨PWMåœæ­¢æ—¶è®¾ç½® + + PWMx->MODE = initStruct->mode; + + PWMx->PERA = initStruct->cycleA; + PWMx->HIGHA = initStruct->hdutyA; + PWMx->DZA = initStruct->deadzoneA; + + PWMx->PERB = initStruct->cycleB; + PWMx->HIGHB = initStruct->hdutyB; + PWMx->DZB = initStruct->deadzoneB; + + PWMx->INIOUT &= ~(PWM_INIOUT_PWMA_Msk | PWM_INIOUT_PWMB_Msk); + PWMx->INIOUT |= (initStruct->initLevelA << PWM_INIOUT_PWMA_Pos) | + (initStruct->initLevelB << PWM_INIOUT_PWMB_Pos); + + PWMG->IM = 0x00000000; + + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + bit_offset = 0; + break; + + case ((uint32_t)PWM1): + bit_offset = 2; + break; + + case ((uint32_t)PWM2): + bit_offset = 4; + break; + + case ((uint32_t)PWM3): + bit_offset = 6; + break; + + case ((uint32_t)PWM4): + bit_offset = 8; + break; + + case ((uint32_t)PWM5): + bit_offset = 10; + break; + } + + PWMG->IRS = ((0x01 << bit_offset) | (0x01 << (bit_offset + 1)) | (0x01 << (bit_offset + 12)) | (0x01 << (bit_offset + 13))); //清除中断标志 + PWMG->IE &= ~((0x01 << bit_offset) | (0x01 << (bit_offset + 1)) | (0x01 << (bit_offset + 12)) | (0x01 << (bit_offset + 13))); + PWMG->IE |= (initStruct->NCycleAIEn << bit_offset) | (initStruct->NCycleBIEn << (bit_offset + 1)) | + (initStruct->HEndAIEn << (bit_offset + 12)) | (initStruct->HEndBIEn << (bit_offset + 13)); + + if (initStruct->NCycleAIEn | initStruct->NCycleBIEn | initStruct->HEndAIEn | initStruct->HEndBIEn) + { + NVIC_EnableIRQ(PWM_IRQn); + } + else if ((PWMG->IE & (~((0x01 << bit_offset) | (0x01 << (bit_offset + 1)) | (0x01 << (bit_offset + 12)) | (0x01 << (bit_offset + 13))))) == 0) + { + NVIC_DisableIRQ(PWM_IRQn); + } +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_Start() +* 功能说明: å¯åŠ¨PWM，开始PWM输出 +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chA 0 通é“Aä¸å¯åŠ¨ 1 通é“Aå¯åŠ¨ +* uint32_t chB 0 通é“Bä¸å¯åŠ¨ 1 通é“Bå¯åŠ¨ +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void PWM_Start(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM0A_Pos) | (chB << PWMG_CHEN_PWM0B_Pos); + break; + + case ((uint32_t)PWM1): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM1A_Pos) | (chB << PWMG_CHEN_PWM1B_Pos); + break; + + case ((uint32_t)PWM2): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM2A_Pos) | (chB << PWMG_CHEN_PWM2B_Pos); + break; + + case ((uint32_t)PWM3): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM3A_Pos) | (chB << PWMG_CHEN_PWM3B_Pos); + break; + + case ((uint32_t)PWM4): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM4A_Pos) | (chB << PWMG_CHEN_PWM4B_Pos); + break; + + case ((uint32_t)PWM5): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM5A_Pos) | (chB << PWMG_CHEN_PWM5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_Stop() +* 功能说明: 关闭PWM，åœæ­¢PWM输出 +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chA 0 通é“Aä¸å…³é—­ 1 通é“A关闭 +* uint32_t chB 0 通é“Bä¸å…³é—­ 1 通é“B关闭 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void PWM_Stop(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM0A_Pos) | (chB << PWMG_CHEN_PWM0B_Pos)); + break; + + case ((uint32_t)PWM1): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM1A_Pos) | (chB << PWMG_CHEN_PWM1B_Pos)); + break; + + case ((uint32_t)PWM2): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM2A_Pos) | (chB << PWMG_CHEN_PWM2B_Pos)); + break; + + case ((uint32_t)PWM3): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM3A_Pos) | (chB << PWMG_CHEN_PWM3B_Pos)); + break; + + case ((uint32_t)PWM4): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM4A_Pos) | (chB << PWMG_CHEN_PWM4B_Pos)); + break; + + case ((uint32_t)PWM5): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM5A_Pos) | (chB << PWMG_CHEN_PWM5B_Pos)); + break; + } +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_SetCycle() +* 功能说明: 设置周期 +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chn 选择è¦è®¾ç½®å“ªä¸ªé€šé“，有效值：PWM_CH_Aã€PWM_CH_B +* uint16_t cycle è¦è®¾å®šçš„周期值 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void PWM_SetCycle(PWM_TypeDef *PWMx, uint32_t chn, uint16_t cycle) +{ + if (chn == PWM_CH_A) + PWMx->PERA = cycle; + else if (chn == PWM_CH_B) + PWMx->PERB = cycle; +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_GetCycle() +* 功能说明: 获å–周期 +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chn 选择è¦æŸ¥è¯¢å“ªä¸ªé€šé“，有效值：PWM_CH_Aã€PWM_CH_B +* 输 出: uint16_t 获å–到的周期值 +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint16_t PWM_GetCycle(PWM_TypeDef *PWMx, uint32_t chn) +{ + uint16_t cycle = 0; + + if (chn == PWM_CH_A) + cycle = PWMx->PERA; + else if (chn == PWM_CH_B) + cycle = PWMx->PERB; + + return cycle; +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_SetHDuty() +* 功能说明: 设置高电平时长 +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chn 选择è¦è®¾ç½®å“ªä¸ªé€šé“，有效值：PWM_CH_Aã€PWM_CH_B +* uint16_t hduty è¦è®¾å®šçš„高电平时长 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void PWM_SetHDuty(PWM_TypeDef *PWMx, uint32_t chn, uint16_t hduty) +{ + if (chn == PWM_CH_A) + PWMx->HIGHA = hduty; + else if (chn == PWM_CH_B) + PWMx->HIGHB = hduty; +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_GetHDuty() +* 功能说明: 获å–高电平时长 +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chn 选择è¦æŸ¥è¯¢å“ªä¸ªé€šé“，有效值：PWM_CH_Aã€PWM_CH_B +* 输 出: uint16_t 获å–到的高电平时长 +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint16_t PWM_GetHDuty(PWM_TypeDef *PWMx, uint32_t chn) +{ + uint16_t hduty = 0; + + if (chn == PWM_CH_A) + hduty = PWMx->HIGHA; + else if (chn == PWM_CH_B) + hduty = PWMx->HIGHB; + + return hduty; +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_SetDeadzone() +* 功能说明: 设置死区时长 +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chn 选择è¦è®¾ç½®å“ªä¸ªé€šé“，有效值：PWM_CH_Aã€PWM_CH_B +* uint8_t deadzone è¦è®¾å®šçš„死区时长 +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void PWM_SetDeadzone(PWM_TypeDef *PWMx, uint32_t chn, uint8_t deadzone) +{ + if (chn == PWM_CH_A) + PWMx->DZA = deadzone; + else if (chn == PWM_CH_B) + PWMx->DZB = deadzone; +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_GetDeadzone() +* 功能说明: 获å–死区时长 +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chn 选择è¦æŸ¥è¯¢å“ªä¸ªé€šé“，有效值：PWM_CH_Aã€PWM_CH_B +* 输 出: uint8_t 获å–到的死区时长 +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint8_t PWM_GetDeadzone(PWM_TypeDef *PWMx, uint32_t chn) +{ + uint8_t deadzone = 0; + + if (chn == PWM_CH_A) + deadzone = PWMx->DZA; + else if (chn == PWM_CH_B) + deadzone = PWMx->DZB; + + return deadzone; +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_IntNCycleEn() +* 功能说明: 新周期开始中断使能 +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chn 选择è¦è®¾ç½®å“ªä¸ªé€šé“，有效值：PWM_CH_Aã€PWM_CH_B +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void PWM_IntNCycleEn(PWM_TypeDef *PWMx, uint32_t chn) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_NEWP0A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_NEWP0B_Pos); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_NEWP1A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_NEWP1B_Pos); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_NEWP2A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_NEWP2B_Pos); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_NEWP3A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_NEWP3B_Pos); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_NEWP4A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_NEWP4B_Pos); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_NEWP5A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_NEWP5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_IntNCycleDis() +* 功能说明: 新周期开始中断ç¦èƒ½ +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chn 选择è¦è®¾ç½®å“ªä¸ªé€šé“，有效值：PWM_CH_Aã€PWM_CH_B +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void PWM_IntNCycleDis(PWM_TypeDef *PWMx, uint32_t chn) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP0A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP0B_Pos); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP1A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP1B_Pos); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP2A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP2B_Pos); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP3A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP3B_Pos); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP4A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP4B_Pos); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP5A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_IntNCycleClr() +* 功能说明: 新周期开始中断标志清除 +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chn 选择è¦è®¾ç½®å“ªä¸ªé€šé“，有效值：PWM_CH_Aã€PWM_CH_B +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void PWM_IntNCycleClr(PWM_TypeDef *PWMx, uint32_t chn) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_NEWP0A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_NEWP0B_Pos); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_NEWP1A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_NEWP1B_Pos); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_NEWP2A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_NEWP2B_Pos); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_NEWP3A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_NEWP3B_Pos); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_NEWP4A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_NEWP4B_Pos); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_NEWP5A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_NEWP5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_IntNCycleStat() +* 功能说明: 新周期开始中断是å¦å‘生 +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chn 选择è¦è®¾ç½®å“ªä¸ªé€šé“，有效值：PWM_CH_Aã€PWM_CH_B +* 输 出: uint32_t 1 新周期开始中断已å‘生 0 新周期开始中断未å‘生 +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t PWM_IntNCycleStat(PWM_TypeDef *PWMx, uint32_t chn) +{ + uint32_t int_stat = 0; + + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_NEWP0A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_NEWP0B_Msk); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_NEWP1A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_NEWP1B_Msk); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_NEWP2A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_NEWP2B_Msk); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_NEWP3A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_NEWP3B_Msk); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_NEWP4A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_NEWP4B_Msk); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_NEWP5A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_NEWP5B_Msk); + break; + } + + return int_stat; +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_IntHEndEn() +* 功能说明: 高电平结æŸä¸­æ–­ä½¿èƒ½ +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chn 选择è¦è®¾ç½®å“ªä¸ªé€šé“，有效值：PWM_CH_Aã€PWM_CH_B +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void PWM_IntHEndEn(PWM_TypeDef *PWMx, uint32_t chn) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_HEND0A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_HEND0B_Pos); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_HEND1A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_HEND1B_Pos); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_HEND2A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_HEND2B_Pos); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_HEND3A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_HEND3B_Pos); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_HEND4A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_HEND4B_Pos); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_HEND5A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_HEND5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_IntHEndDis() +* 功能说明: 高电平结æŸä¸­æ–­ç¦èƒ½ +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chn 选择è¦è®¾ç½®å“ªä¸ªé€šé“，有效值：PWM_CH_Aã€PWM_CH_B +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void PWM_IntHEndDis(PWM_TypeDef *PWMx, uint32_t chn) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_HEND0A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_HEND0B_Pos); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_HEND1A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_HEND1B_Pos); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_HEND2A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_HEND2B_Pos); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_HEND3A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_HEND3B_Pos); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_HEND4A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_HEND4B_Pos); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_HEND5A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_HEND5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_IntHEndClr() +* 功能说明: 高电平结æŸä¸­æ–­æ ‡å¿—清除 +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chn 选择è¦è®¾ç½®å“ªä¸ªé€šé“，有效值：PWM_CH_Aã€PWM_CH_B +* 输 出: æ—  +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +void PWM_IntHEndClr(PWM_TypeDef *PWMx, uint32_t chn) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_HEND0A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_HEND0B_Pos); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_HEND1A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_HEND1B_Pos); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_HEND2A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_HEND2B_Pos); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_HEND3A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_HEND3B_Pos); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_HEND4A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_HEND4B_Pos); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_HEND5A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_HEND5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* 函数å称: PWM_IntHEndStat() +* 功能说明: 高电平结æŸä¸­æ–­æ˜¯å¦å‘生 +* 输 å…¥: PWM_TypeDef * PWMx 指定è¦è¢«è®¾ç½®çš„PWM，有效值包括PWM0ã€PWM1ã€PWM2ã€PWM3ã€PWM4ã€PWM5 +* uint32_t chn 选择è¦è®¾ç½®å“ªä¸ªé€šé“，有效值：PWM_CH_Aã€PWM_CH_B +* 输 出: uint32_t 1 高电平结æŸä¸­æ–­å·²å‘生 0 高电平结æŸä¸­æ–­æœªå‘生 +* 注æ„事项: æ—  +******************************************************************************************************************************************/ +uint32_t PWM_IntHEndStat(PWM_TypeDef *PWMx, uint32_t chn) +{ + uint32_t int_stat = 0; + + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_HEND0A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_HEND0B_Msk); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_HEND1A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_HEND1B_Msk); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_HEND2A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_HEND2B_Msk); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_HEND3A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_HEND3B_Msk); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_HEND4A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_HEND4B_Msk); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_HEND5A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_HEND5B_Msk); + break; + } + + return int_stat; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.h new file mode 100644 index 0000000000..888e0c5e39 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.h @@ -0,0 +1,57 @@ +#ifndef __SWM320_PWM_H__ +#define __SWM320_PWM_H__ + +typedef struct +{ + uint8_t clk_div; //PWM_CLKDIV_1ã€PWM_CLKDIV_8 + + uint8_t mode; //PWM_MODE_INDEPã€PWM_MODE_COMPLã€PWM_MODE_INDEP_CALIGNã€PWM_MODE_COMPL_CALIGN + + uint16_t cycleA; //A路周期 + uint16_t hdutyA; //Aè·¯å ç©ºæ¯” + uint16_t deadzoneA; //A路死区时长，å–值0--1023 + uint8_t initLevelA; //Aè·¯åˆå§‹è¾“出电平，0 低电平 1 高电平 + + uint16_t cycleB; //B路周期 + uint16_t hdutyB; //Bè·¯å ç©ºæ¯” + uint16_t deadzoneB; //B路死区时长，å–值0--1023 + uint8_t initLevelB; //Bè·¯åˆå§‹è¾“出电平，0 低电平 1 高电平 + + uint8_t HEndAIEn; //A路高电平结æŸä¸­æ–­ä½¿èƒ½ + uint8_t NCycleAIEn; //A路新周期开始中断使能 + uint8_t HEndBIEn; //B路高电平结æŸä¸­æ–­ä½¿èƒ½ + uint8_t NCycleBIEn; //B路新周期开始中断使能 +} PWM_InitStructure; + +#define PWM_CLKDIV_1 0 +#define PWM_CLKDIV_8 1 + +#define PWM_MODE_INDEP 0 //A路和B路为两路独立输出 +#define PWM_MODE_COMPL 1 //A路和B路为一路互补输出 +#define PWM_MODE_INDEP_CALIGN 3 //A路和Bè·¯ä¸ºä¸¤è·¯ç‹¬ç«‹è¾“å‡ºï¼Œä¸­å¿ƒå¯¹é½ +#define PWM_MODE_COMPL_CALIGN 4 //A路和Bè·¯ä¸ºä¸€è·¯äº’è¡¥è¾“å‡ºï¼Œä¸­å¿ƒå¯¹é½ + +#define PWM_CH_A 0 +#define PWM_CH_B 1 + +void PWM_Init(PWM_TypeDef *PWMx, PWM_InitStructure *initStruct); //PWMåˆå§‹åŒ– +void PWM_Start(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB); //å¯åŠ¨PWM，开始PWM输出 +void PWM_Stop(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB); //关闭PWM，åœæ­¢PWM输出 + +void PWM_SetCycle(PWM_TypeDef *PWMx, uint32_t chn, uint16_t cycle); //设置周期 +uint16_t PWM_GetCycle(PWM_TypeDef *PWMx, uint32_t chn); //获å–周期 +void PWM_SetHDuty(PWM_TypeDef *PWMx, uint32_t chn, uint16_t hduty); //设置高电平时长 +uint16_t PWM_GetHDuty(PWM_TypeDef *PWMx, uint32_t chn); //获å–高电平时长 +void PWM_SetDeadzone(PWM_TypeDef *PWMx, uint32_t chn, uint8_t deadzone); //设置死区时长 +uint8_t PWM_GetDeadzone(PWM_TypeDef *PWMx, uint32_t chn); //获å–死区时长 + +void PWM_IntNCycleEn(PWM_TypeDef *PWMx, uint32_t chn); //新周期开始中断使能 +void PWM_IntNCycleDis(PWM_TypeDef *PWMx, uint32_t chn); //新周期开始中断ç¦èƒ½ +void PWM_IntNCycleClr(PWM_TypeDef *PWMx, uint32_t chn); //新周期开始中断标志清除 +uint32_t PWM_IntNCycleStat(PWM_TypeDef *PWMx, uint32_t chn); //新周期开始中断是å¦å‘生 +void PWM_IntHEndEn(PWM_TypeDef *PWMx, uint32_t chn); //高电平结æŸä¸­æ–­ä½¿èƒ½ +void PWM_IntHEndDis(PWM_TypeDef *PWMx, uint32_t chn); //高电平结æŸä¸­æ–­ç¦èƒ½ +void PWM_IntHEndClr(PWM_TypeDef *PWMx, uint32_t chn); //高电平结æŸä¸­æ–­æ ‡å¿—清除 +uint32_t PWM_IntHEndStat(PWM_TypeDef *PWMx, uint32_t chn); //高电平结æŸä¸­æ–­æ˜¯å¦å‘生 + +#endif //__SWM320_PWM_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c new file mode 100644 index 0000000000..60958799ed --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c @@ -0,0 +1,413 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_rtc.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄRTCÇý¶¯¿â +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_rtc.h" + + +static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date); +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_Init() +* ¹¦ÄÜ˵Ã÷: RTC³õʼ»¯ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬ÓÐЧֵ°üÀ¨RTC +* RTC_InitStructure * initStruct °üº¬RTCÏà¹ØÉ趨ֵµÄ½á¹¹Ìå +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct) +{ + SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos); + + SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); //RTCʹÓÃ32KHz RCʱÖÓ + + SYS->CLKEN |= (1 << SYS_CLKEN_RTC_Pos) | + ((uint32_t)1 << SYS_CLKEN_ALIVE_Pos); + + RTC_Stop(RTCx); + + while (RTCx->CFGABLE == 0); + + RTCx->MINSEC = (initStruct->Second << RTC_MINSEC_SEC_Pos) | + (initStruct->Minute << RTC_MINSEC_MIN_Pos); + + RTCx->DATHUR = (initStruct->Hour << RTC_DATHUR_HOUR_Pos) | + ((initStruct->Date - 1) << RTC_DATHUR_DATE_Pos); + + RTCx->MONDAY = (calcWeekDay(initStruct->Year, initStruct->Month, initStruct->Date) << RTC_MONDAY_DAY_Pos) | + ((initStruct->Month - 1) << RTC_MONDAY_MON_Pos); + + RTCx->YEAR = initStruct->Year - 1901; + + RTCx->LOAD = 1 << RTC_LOAD_TIME_Pos; + + RTCx->IF = 0x1F; + RTCx->IE = (initStruct->SecondIEn << RTC_IE_SEC_Pos) | + (initStruct->MinuteIEn << RTC_IE_MIN_Pos); + + if (initStruct->SecondIEn | initStruct->MinuteIEn) + { + NVIC_EnableIRQ(RTC_IRQn); + } + else + { + NVIC_DisableIRQ(RTC_IRQn); + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_Start() +* ¹¦ÄÜ˵Ã÷: Æô¶¯RTC +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_Start(RTC_TypeDef *RTCx) +{ + RTCx->EN = 1; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_Stop() +* ¹¦ÄÜ˵Ã÷: Í£Ö¹RTC +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_Stop(RTC_TypeDef *RTCx) +{ + RTCx->EN = 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_GetDateTime() +* ¹¦ÄÜ˵Ã÷: »ñÈ¡µ±Ç°µÄʱ¼äºÍÈÕÆÚ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬ÓÐЧֵ°üÀ¨RTC +* RTC_DateTime * dateTime »ñÈ¡µ½µÄʱ¼ä¡¢ÈÕÆÚÖµ´æÈë´ËÖ¸ÕëÖ¸ÏòµÄ½á¹¹Ìå +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime) +{ + dateTime->Year = RTCx->YEAR + 1901; + dateTime->Month = ((RTCx->MONDAY & RTC_MONDAY_MON_Msk) >> RTC_MONDAY_MON_Pos) + 1; + dateTime->Date = ((RTCx->DATHUR & RTC_DATHUR_DATE_Msk) >> RTC_DATHUR_DATE_Pos) + 1; + dateTime->Day = 1 << ((RTCx->MONDAY & RTC_MONDAY_DAY_Msk) >> RTC_MONDAY_DAY_Pos); + dateTime->Hour = (RTCx->DATHUR & RTC_DATHUR_HOUR_Msk) >> RTC_DATHUR_HOUR_Pos; + dateTime->Minute = (RTCx->MINSEC & RTC_MINSEC_MIN_Msk) >> RTC_MINSEC_MIN_Pos; + dateTime->Second = (RTCx->MINSEC & RTC_MINSEC_SEC_Msk) >> RTC_MINSEC_SEC_Pos; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_AlarmSetup() +* ¹¦ÄÜ˵Ã÷: RTCÄÖÖÓÉ趨 +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬ÓÐЧֵ°üÀ¨RTC +* RTC_AlarmStructure * alarmStruct °üº¬RTCÄÖÖÓÉ趨ֵµÄ½á¹¹Ìå +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_AlarmSetup(RTC_TypeDef *RTCx, RTC_AlarmStructure *alarmStruct) +{ + while (RTCx->CFGABLE == 0); + + RTCx->MINSECAL = (alarmStruct->Second << RTC_MINSECAL_SEC_Pos) | + (alarmStruct->Minute << RTC_MINSECAL_MIN_Pos); + + RTCx->DAYHURAL = (alarmStruct->Hour << RTC_DAYHURAL_HOUR_Pos) | + (alarmStruct->Days << RTC_DAYHURAL_SUN_Pos); + + RTCx->LOAD = 1 << RTC_LOAD_ALARM_Pos; + while (RTCx->LOAD & RTC_LOAD_ALARM_Msk); + + RTCx->IF = (1 << RTC_IF_ALARM_Pos); + RTCx->IE &= ~RTC_IE_ALARM_Msk; + RTCx->IE |= (alarmStruct->AlarmIEn << RTC_IE_ALARM_Pos); + + if (alarmStruct->AlarmIEn) NVIC_EnableIRQ(RTC_IRQn); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: calcWeekDay() +* ¹¦ÄÜ˵Ã÷: ¼ÆËãÖ¸¶¨Äê¡¢Ô¡¢ÈÕÊÇÐÇÆÚ¼¸ +* Êä Èë: uint32_t year Äê +* uint32_t month Ô +* uint32_t date ÈÕ +* Êä ³ö: uint32_t 0 ÐÇÆÚÈÕ 1 ÐÇÆÚÒ» ... ... 6 ÐÇÆÚÁù +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date) +{ + uint32_t i, cnt = 0; + const uint32_t daysOfMonth[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + + for (i = 1; i < month; i++) cnt += daysOfMonth[i]; + + cnt += date; + + if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && (month >= 3)) cnt += 1; + + cnt += (year - 1901) * 365; + + for (i = 1901; i < year; i++) + { + if ((i % 4 == 0) && ((i % 100 != 0) || (i % 400 == 0))) cnt += 1; + } + + return (cnt + 1) % 7; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntSecondEn() +* ¹¦ÄÜ˵Ã÷: ÃëÖжÏʹÄÜ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntSecondEn(RTC_TypeDef *RTCx) +{ + RTCx->IE |= (1 << RTC_IE_SEC_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntSecondDis() +* ¹¦ÄÜ˵Ã÷: ÃëÖжϽûÖ¹ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntSecondDis(RTC_TypeDef *RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_SEC_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntSecondClr() +* ¹¦ÄÜ˵Ã÷: ÃëÖжϱêÖ¾Çå³ý +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntSecondClr(RTC_TypeDef *RTCx) +{ + RTCx->IF = (1 << RTC_IF_SEC_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntSecondStat() +* ¹¦ÄÜ˵Ã÷: ÃëÖжÏ״̬ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: uint32_t 1 ÃëÖжϷ¢Éú 0 ÃëÖжÏδ·¢Éú +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t RTC_IntSecondStat(RTC_TypeDef *RTCx) +{ + return (RTCx->IF & RTC_IF_SEC_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntMinuteEn() +* ¹¦ÄÜ˵Ã÷: ·ÖÖжÏʹÄÜ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntMinuteEn(RTC_TypeDef *RTCx) +{ + RTCx->IE |= (1 << RTC_IE_MIN_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntMinuteDis() +* ¹¦ÄÜ˵Ã÷: ·ÖÖжϽûÖ¹ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntMinuteDis(RTC_TypeDef *RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_MIN_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntMinuteClr() +* ¹¦ÄÜ˵Ã÷: ·ÖÖжϱêÖ¾Çå³ý +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntMinuteClr(RTC_TypeDef *RTCx) +{ + RTCx->IF = (1 << RTC_IF_MIN_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntMinuteStat() +* ¹¦ÄÜ˵Ã÷: ·ÖÖжÏ״̬ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: uint32_t 1 ·ÖÖжϷ¢Éú 0 ·ÖÖжÏδ·¢Éú +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t RTC_IntMinuteStat(RTC_TypeDef *RTCx) +{ + return (RTCx->IF & RTC_IF_MIN_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntHourEn() +* ¹¦ÄÜ˵Ã÷: ʱÖжÏʹÄÜ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntHourEn(RTC_TypeDef *RTCx) +{ + RTCx->IE |= (1 << RTC_IE_HOUR_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntHourDis() +* ¹¦ÄÜ˵Ã÷: ʱÖжϽûÖ¹ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntHourDis(RTC_TypeDef *RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_HOUR_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntHourClr() +* ¹¦ÄÜ˵Ã÷: ʱÖжϱêÖ¾Çå³ý +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntHourClr(RTC_TypeDef *RTCx) +{ + RTCx->IF = (1 << RTC_IF_HOUR_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntHourStat() +* ¹¦ÄÜ˵Ã÷: ʱÖжÏ״̬ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: uint32_t 1 ʱÖжϷ¢Éú 0 ʱÖжÏδ·¢Éú +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t RTC_IntHourStat(RTC_TypeDef *RTCx) +{ + return (RTCx->IF & RTC_IF_HOUR_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntDateEn() +* ¹¦ÄÜ˵Ã÷: ÈÕÖжÏʹÄÜ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntDateEn(RTC_TypeDef *RTCx) +{ + RTCx->IE |= (1 << RTC_IE_DATE_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntDateDis() +* ¹¦ÄÜ˵Ã÷: ÈÕÖжϽûÖ¹ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntDateDis(RTC_TypeDef *RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_DATE_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntDateClr() +* ¹¦ÄÜ˵Ã÷: ÈÕÖжϱêÖ¾Çå³ý +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntDateClr(RTC_TypeDef *RTCx) +{ + RTCx->IF = (1 << RTC_IF_DATE_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntDateStat() +* ¹¦ÄÜ˵Ã÷: ÈÕÖжÏ״̬ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: uint32_t 1 ÈÕÖжϷ¢Éú 0 ÈÕÖжÏδ·¢Éú +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t RTC_IntDateStat(RTC_TypeDef *RTCx) +{ + return (RTCx->IF & RTC_IF_DATE_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntAlarmEn() +* ¹¦ÄÜ˵Ã÷: ÄÖÖÓÖжÏʹÄÜ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntAlarmEn(RTC_TypeDef *RTCx) +{ + RTCx->IE |= (1 << RTC_IE_ALARM_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntAlarmDis() +* ¹¦ÄÜ˵Ã÷: ÄÖÖÓÖжϽûÖ¹ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntAlarmDis(RTC_TypeDef *RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_ALARM_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntAlarmClr() +* ¹¦ÄÜ˵Ã÷: ÄÖÖÓÖжϱêÖ¾Çå³ý +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void RTC_IntAlarmClr(RTC_TypeDef *RTCx) +{ + RTCx->IF = (1 << RTC_IF_ALARM_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: RTC_IntAlarmStat() +* ¹¦ÄÜ˵Ã÷: ÄÖÖÓÖжÏ״̬ +* Êä Èë: RTC_TypeDef * RTCx Ö¸¶¨Òª±»ÉèÖõÄRTC£¬¿ÉÈ¡Öµ°üÀ¨RTC +* Êä ³ö: uint32_t 1 ÄÖÖÓÖжϷ¢Éú 0 ÄÖÖÓÖжÏδ·¢Éú +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t RTC_IntAlarmStat(RTC_TypeDef *RTCx) +{ + return (RTCx->IF & RTC_IF_ALARM_Msk) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h new file mode 100644 index 0000000000..8c5d6f5d63 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h @@ -0,0 +1,76 @@ +#ifndef __SWM320_RTC_H__ +#define __SWM320_RTC_H__ + + +#define RTC_SUN 0x01 +#define RTC_MON 0x02 +#define RTC_TUE 0x04 +#define RTC_WED 0x08 +#define RTC_THU 0x10 +#define RTC_FRI 0x20 +#define RTC_SAT 0x40 + + +typedef struct +{ + uint16_t Year; + uint8_t Month; + uint8_t Date; + uint8_t Hour; + uint8_t Minute; + uint8_t Second; + uint8_t SecondIEn; + uint8_t MinuteIEn; +} RTC_InitStructure; + +typedef struct +{ + uint8_t Days; //RTC_SUN¡¢RTC_MON¡¢RTC_TUE¡¢RTC_WED¡¢RTC_THU¡¢RTC_FRI¡¢RTC_SAT¼°Æä»òÔËËã×éºÏ + uint8_t Hour; + uint8_t Minute; + uint8_t Second; + uint8_t AlarmIEn; +} RTC_AlarmStructure; + +typedef struct +{ + uint16_t Year; + uint8_t Month; + uint8_t Date; + uint8_t Day; //RTC_SUN¡¢RTC_MON¡¢RTC_TUE¡¢RTC_WED¡¢RTC_THU¡¢RTC_FRI¡¢RTC_SAT + uint8_t Hour; + uint8_t Minute; + uint8_t Second; +} RTC_DateTime; + +void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct); +void RTC_Start(RTC_TypeDef *RTCx); +void RTC_Stop(RTC_TypeDef *RTCx); + +void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime); + +void RTC_AlarmSetup(RTC_TypeDef *RTCx, RTC_AlarmStructure *alarmStruct); + + +void RTC_IntSecondEn(RTC_TypeDef *RTCx); +void RTC_IntSecondDis(RTC_TypeDef *RTCx); +void RTC_IntSecondClr(RTC_TypeDef *RTCx); +uint32_t RTC_IntSecondStat(RTC_TypeDef *RTCx); +void RTC_IntMinuteEn(RTC_TypeDef *RTCx); +void RTC_IntMinuteDis(RTC_TypeDef *RTCx); +void RTC_IntMinuteClr(RTC_TypeDef *RTCx); +uint32_t RTC_IntMinuteStat(RTC_TypeDef *RTCx); +void RTC_IntHourEn(RTC_TypeDef *RTCx); +void RTC_IntHourDis(RTC_TypeDef *RTCx); +void RTC_IntHourClr(RTC_TypeDef *RTCx); +uint32_t RTC_IntHourStat(RTC_TypeDef *RTCx); +void RTC_IntDateEn(RTC_TypeDef *RTCx); +void RTC_IntDateDis(RTC_TypeDef *RTCx); +void RTC_IntDateClr(RTC_TypeDef *RTCx); +uint32_t RTC_IntDateStat(RTC_TypeDef *RTCx); +void RTC_IntAlarmEn(RTC_TypeDef *RTCx); +void RTC_IntAlarmDis(RTC_TypeDef *RTCx); +void RTC_IntAlarmClr(RTC_TypeDef *RTCx); +uint32_t RTC_IntAlarmStat(RTC_TypeDef *RTCx); + +#endif //__SWM320_RTC_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c new file mode 100644 index 0000000000..305ab42733 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c @@ -0,0 +1,436 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_sdio.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄSDIO½Ó¿ÚÇý¶¯¿â +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: ΪÁËͨÓÃÐÔ¡¢¼æÈÝÐÔ¡¢Ò×ÓÃÐÔ£¬Ö»Ö§³ÖÒÔ512×Ö½ÚΪµ¥Î»µÄ¶Áд +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_sdio.h" + + +SD_CardInfo SD_cardInfo; + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SDIO_Init() +* ¹¦ÄÜ˵Ã÷: SDIO¶ÁдSD¿¨³õʼ»¯£¬³õʼ»¯³É¸ßËÙ4Ïßģʽ¡¢¶ÁдÒÔ512×Ö½Ú´óС½øÐÐ +* Êä Èë: ÎÞ +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t SDIO_Init(void) +{ + uint32_t resp, resps[4]; + + SYS->CLKDIV &= ~SYS_CLKDIV_SDIO_Msk; + if (SystemCoreClock > 80000000) //SDIOʱÖÓÐèҪСÓÚ52MHz + SYS->CLKDIV |= (2 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 4 + else + SYS->CLKDIV |= (1 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 2 + + SYS->CLKEN |= (0x01 << SYS_CLKEN_SDIO_Pos); + + SDIO->CR2 = (1 << SDIO_CR2_RSTALL_Pos); + + SDIO->CR1 = (1 << SDIO_CR1_CDSRC_Pos) | + (0 << SDIO_CR1_8BIT_Pos) | + (0 << SDIO_CR1_4BIT_Pos) | + (1 << SDIO_CR1_PWRON_Pos) | + (7 << SDIO_CR1_VOLT_Pos); + + SDIO->CR2 = (1 << SDIO_CR2_CLKEN_Pos) | + (1 << SDIO_CR2_SDCLKEN_Pos) | + (calcSDCLKDiv(SD_CLK_400KHz) << SDIO_CR2_SDCLKDIV_Pos) | + (0xC << SDIO_CR2_TIMEOUT_Pos); + + while ((SDIO->CR2 & SDIO_CR2_CLKRDY_Msk) == 0); + + SDIO->IE = 0xFFFF01FF; + SDIO->IM = 0x00FF00FF; + + SDIO_SendCmd(SD_CMD_GO_IDLE_STATE, 0x00, SD_RESP_NO, 0, 0, 0); //CMD0: GO_IDLE_STATE + + + SDIO_SendCmd(SD_CMD_SEND_IF_COND, 0x1AA, SD_RESP_32b, &resp, 0, 0); //CMD8: SEND_IF_COND, ¼ì²â¹¤×÷µçѹ¡¢¼ì²âÊÇ·ñÖ§³ÖSD 2.0 + + if (resp == 0x1AA) SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; + else SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1; + + + do //ACMD41: SD_CMD_SD_APP_OP_COND + { + SDIO_SendCmd(SD_CMD_APP_CMD, 0x00, SD_RESP_32b, &resp, 0, 0); + + if (resp != 0x120) return SD_RES_ERR; //²»ÊÇSD¿¨£¬¿ÉÄÜÊÇMMC¿¨ + + if (SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0) + SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000 | 0x40000000, SD_RESP_32b, &resp, 0, 0); + else + SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000 | 0x00000000, SD_RESP_32b, &resp, 0, 0); + } + while (((resp >> 31) & 0x01) == 0); //ÉϵçûÍê³Éʱresp[31] == 0 + + if (((resp >> 30) & 0x01) == 1) SD_cardInfo.CardType = SDIO_HIGH_CAPACITY_SD_CARD; + + + SDIO_SendCmd(SD_CMD_ALL_SEND_CID, 0x00, SD_RESP_128b, resps, 0, 0); //CMD2: SD_CMD_ALL_SEND_CID£¬»ñÈ¡CID + + parseCID(resps); + + + SDIO_SendCmd(SD_CMD_SET_REL_ADDR, 0x00, SD_RESP_32b, &resp, 0, 0); //CMD3: SD_CMD_SET_REL_ADDR£¬ÉèÖÃRCA + + SD_cardInfo.RCA = resp >> 16; + + + SDIO_SendCmd(SD_CMD_SEND_CSD, SD_cardInfo.RCA << 16, SD_RESP_128b, resps, 0, 0); //CMD9: SD_CMD_SEND_CSD£¬»ñÈ¡CSD + + parseCSD(resps); + + if (SD_cardInfo.CardBlockSize < 0x200) return SD_RES_ERR; //±¾Çý¶¯Ö»Ö§³ÖÒÔ512×Ö½ÚΪµ¥Î»µÄ¶Áд£¬ËùÒÔ×î´ó¶Áдµ¥Î»±ØÐ벻СÓÚ512 + + + SDIO->CR2 &= ~(SDIO_CR2_SDCLKEN_Msk | SDIO_CR2_SDCLKDIV_Msk); + SDIO->CR2 |= (1 << SDIO_CR2_SDCLKEN_Pos) | + (calcSDCLKDiv(SD_CLK_20MHz) << SDIO_CR2_SDCLKDIV_Pos); //³õʼ»¯Íê³É£¬SDCLKÇл»µ½¸ßËÙ + + + SDIO_SendCmd(SD_CMD_SEL_DESEL_CARD, SD_cardInfo.RCA << 16, SD_RESP_32b_busy, &resp, 0, 0); //CMD7: Ñ¡Öп¨£¬´ÓStandyģʽ½øÈëTransferģʽ + + + SDIO_SendCmd(SD_CMD_APP_CMD, SD_cardInfo.RCA << 16, SD_RESP_32b, &resp, 0, 0); + + SDIO_SendCmd(SD_CMD_APP_SD_SET_BUSWIDTH, SD_BUSWIDTH_4b, SD_RESP_32b, &resp, 0, 0); //Çл»³É4λ×ÜÏßģʽ + + SDIO->CR1 |= (1 << SDIO_CR1_4BIT_Pos); + + + SDIO_SendCmd(SD_CMD_SET_BLOCKLEN, 512, SD_RESP_32b, &resp, 0, 0); //¹Ì¶¨¿é´óСλ512×Ö½Ú + + SDIO->BLK = 512; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SDIO_BlockWrite() +* ¹¦ÄÜ˵Ã÷: ÏòSD¿¨Ð´ÈëÊý¾Ý +* Êä Èë: uint32_t block_addr SD¿¨¿éµØÖ·£¬Ã¿¿é512×Ö½Ú +* uint32_t buff[] ҪдÈëµÄÊý¾Ý +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]) +{ + uint32_t i, resp, addr; + + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) addr = block_addr; + else addr = block_addr * 512; + + SDIO_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 1, 0); + + while ((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0); + SDIO->IF = SDIO_IF_BUFWRRDY_Msk; + + for (i = 0; i < 512 / 4; i++) SDIO->DATA = buff[i]; + + SDIO->IF = SDIO_IF_TRXDONE_Msk; //?? Õâ¸ö±ØÐëÓÐ + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0); + SDIO->IF = SDIO_IF_TRXDONE_Msk; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SDIO_BlockRead() +* ¹¦ÄÜ˵Ã÷: ´ÓSD¿¨¶Á³öÊý¾Ý +* Êä Èë: uint32_t block_addr SD¿¨¿éµØÖ·£¬Ã¿¿é512×Ö½Ú +* uint32_t buff[] ¶Á³öµÄÊý¾Ý +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]) +{ + uint32_t i, resp, addr; + + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) addr = block_addr; + else addr = block_addr * 512; + + SDIO_SendCmd(SD_CMD_READ_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 1, 1); + + while ((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0); + SDIO->IF = SDIO_IF_BUFRDRDY_Msk; + + for (i = 0; i < 512 / 4; i++) buff[i] = SDIO->DATA; + + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0); + SDIO->IF = SDIO_IF_TRXDONE_Msk; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SDIO_SendCmd() +* ¹¦ÄÜ˵Ã÷: SDIOÏòSD¿¨·¢ËÍÃüÁî +* Êä Èë: uint32_t cmd ÃüÁîË÷Òý +* uint32_t arg ÃüÁî²ÎÊý +* uint32_t resp_type ÏìÓ¦ÀàÐÍ£¬È¡ÖµSD_RESP_NO¡¢SD_RESP_32b¡¢SD_RESP_128b¡¢SD_RESP_32b_busy +* uint32_t *resp_data ÏìÓ¦ÄÚÈÝ +* uint32_t have_data ÊÇ·ñÓÐÊý¾Ý´«Êä +* uint32_t data_read 1 ¶ÁSD¿¨ 0 дSD¿¨ +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read) +{ + SDIO->ARG = arg; + SDIO->CMD = (cmd << SDIO_CMD_CMDINDX_Pos) | + (0 << SDIO_CMD_CMDTYPE_Pos) | + (have_data << SDIO_CMD_HAVEDATA_Pos) | + (0 << SDIO_CMD_IDXCHECK_Pos) | + (0 << SDIO_CMD_CRCCHECK_Pos) | + (resp_type << SDIO_CMD_RESPTYPE_Pos) | + (0 << SDIO_CMD_MULTBLK_Pos) | + (data_read << SDIO_CMD_DIRREAD_Pos) | + (0 << SDIO_CMD_BLKCNTEN_Pos); + + while ((SDIO->IF & SDIO_IF_CMDDONE_Msk) == 0); + SDIO->IF = SDIO_IF_CMDDONE_Msk; + + if (resp_type == SD_RESP_32b) + { + resp_data[0] = SDIO->RESP[0]; + } + else if (resp_type == SD_RESP_128b) + { + //¼Ä´æÆ÷Öн«CID/CSD[127-8]ÒÀ´Î´æ·ÅÔÚÁËRESP3-0[119-0]£¬×îµÍλµÄCRC±»¶ªµô + //¶Á³öÊý¾Ýʱµ÷ÕûÁË˳Ðò£¬½«CID/CSD[127-8]´æ·ÅÔÚresp_data0-3[127-8]£¬×îµÍ8λÌî³ä0x00 + resp_data[0] = (SDIO->RESP[3] << 8) + ((SDIO->RESP[2] >> 24) & 0xFF); + resp_data[1] = (SDIO->RESP[2] << 8) + ((SDIO->RESP[1] >> 24) & 0xFF); + resp_data[2] = (SDIO->RESP[1] << 8) + ((SDIO->RESP[0] >> 24) & 0xFF); + resp_data[3] = (SDIO->RESP[0] << 8) + 0x00; + } +} + + +void parseCID(uint32_t CID_Tab[4]) +{ + uint8_t tmp = 0; + + /*!< Byte 0 */ + tmp = (uint8_t)((CID_Tab[0] & 0xFF000000) >> 24); + SD_cardInfo.SD_cid.ManufacturerID = tmp; + + /*!< Byte 1 */ + tmp = (uint8_t)((CID_Tab[0] & 0x00FF0000) >> 16); + SD_cardInfo.SD_cid.OEM_AppliID = tmp << 8; + + /*!< Byte 2 */ + tmp = (uint8_t)((CID_Tab[0] & 0x000000FF00) >> 8); + SD_cardInfo.SD_cid.OEM_AppliID |= tmp; + + /*!< Byte 3 */ + tmp = (uint8_t)(CID_Tab[0] & 0x000000FF); + SD_cardInfo.SD_cid.ProdName1 = tmp << 24; + + /*!< Byte 4 */ + tmp = (uint8_t)((CID_Tab[1] & 0xFF000000) >> 24); + SD_cardInfo.SD_cid.ProdName1 |= tmp << 16; + + /*!< Byte 5 */ + tmp = (uint8_t)((CID_Tab[1] & 0x00FF0000) >> 16); + SD_cardInfo.SD_cid.ProdName1 |= tmp << 8; + + /*!< Byte 6 */ + tmp = (uint8_t)((CID_Tab[1] & 0x0000FF00) >> 8); + SD_cardInfo.SD_cid.ProdName1 |= tmp; + + /*!< Byte 7 */ + tmp = (uint8_t)(CID_Tab[1] & 0x000000FF); + SD_cardInfo.SD_cid.ProdName2 = tmp; + + /*!< Byte 8 */ + tmp = (uint8_t)((CID_Tab[2] & 0xFF000000) >> 24); + SD_cardInfo.SD_cid.ProdRev = tmp; + + /*!< Byte 9 */ + tmp = (uint8_t)((CID_Tab[2] & 0x00FF0000) >> 16); + SD_cardInfo.SD_cid.ProdSN = tmp << 24; + + /*!< Byte 10 */ + tmp = (uint8_t)((CID_Tab[2] & 0x0000FF00) >> 8); + SD_cardInfo.SD_cid.ProdSN |= tmp << 16; + + /*!< Byte 11 */ + tmp = (uint8_t)(CID_Tab[2] & 0x000000FF); + SD_cardInfo.SD_cid.ProdSN |= tmp << 8; + + /*!< Byte 12 */ + tmp = (uint8_t)((CID_Tab[3] & 0xFF000000) >> 24); + SD_cardInfo.SD_cid.ProdSN |= tmp; + + /*!< Byte 13 */ + tmp = (uint8_t)((CID_Tab[3] & 0x00FF0000) >> 16); + SD_cardInfo.SD_cid.Reserved1 |= (tmp & 0xF0) >> 4; + SD_cardInfo.SD_cid.ManufactDate = (tmp & 0x0F) << 8; + + /*!< Byte 14 */ + tmp = (uint8_t)((CID_Tab[3] & 0x0000FF00) >> 8); + SD_cardInfo.SD_cid.ManufactDate |= tmp; +} + +void parseCSD(uint32_t CSD_Tab[4]) +{ + uint8_t tmp = 0; + + /*!< Byte 0 */ + tmp = (uint8_t)((CSD_Tab[0] & 0xFF000000) >> 24); + SD_cardInfo.SD_csd.CSDStruct = (tmp & 0xC0) >> 6; + SD_cardInfo.SD_csd.SysSpecVersion = (tmp & 0x3C) >> 2; + SD_cardInfo.SD_csd.Reserved1 = tmp & 0x03; + + /*!< Byte 1 */ + tmp = (uint8_t)((CSD_Tab[0] & 0x00FF0000) >> 16); + SD_cardInfo.SD_csd.TAAC = tmp; + + /*!< Byte 2 */ + tmp = (uint8_t)((CSD_Tab[0] & 0x0000FF00) >> 8); + SD_cardInfo.SD_csd.NSAC = tmp; + + /*!< Byte 3 */ + tmp = (uint8_t)(CSD_Tab[0] & 0x000000FF); + SD_cardInfo.SD_csd.MaxBusClkFrec = tmp; + + /*!< Byte 4 */ + tmp = (uint8_t)((CSD_Tab[1] & 0xFF000000) >> 24); + SD_cardInfo.SD_csd.CardComdClasses = tmp << 4; + + /*!< Byte 5 */ + tmp = (uint8_t)((CSD_Tab[1] & 0x00FF0000) >> 16); + SD_cardInfo.SD_csd.CardComdClasses |= (tmp & 0xF0) >> 4; + SD_cardInfo.SD_csd.RdBlockLen = tmp & 0x0F; + + /*!< Byte 6 */ + tmp = (uint8_t)((CSD_Tab[1] & 0x0000FF00) >> 8); + SD_cardInfo.SD_csd.PartBlockRead = (tmp & 0x80) >> 7; + SD_cardInfo.SD_csd.WrBlockMisalign = (tmp & 0x40) >> 6; + SD_cardInfo.SD_csd.RdBlockMisalign = (tmp & 0x20) >> 5; + SD_cardInfo.SD_csd.DSRImpl = (tmp & 0x10) >> 4; + SD_cardInfo.SD_csd.Reserved2 = 0; /*!< Reserved */ + + if ((SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || + (SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0)) + { + SD_cardInfo.SD_csd.DeviceSize = (tmp & 0x03) << 10; + + /*!< Byte 7 */ + tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); + SD_cardInfo.SD_csd.DeviceSize |= (tmp) << 2; + + /*!< Byte 8 */ + tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); + SD_cardInfo.SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; + + SD_cardInfo.SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; + SD_cardInfo.SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); + + /*!< Byte 9 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); + SD_cardInfo.SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; + SD_cardInfo.SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; + SD_cardInfo.SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; + /*!< Byte 10 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); + SD_cardInfo.SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; + + SD_cardInfo.CardCapacity = (SD_cardInfo.SD_csd.DeviceSize + 1) ; + SD_cardInfo.CardCapacity *= (1 << (SD_cardInfo.SD_csd.DeviceSizeMul + 2)); + SD_cardInfo.CardBlockSize = 1 << (SD_cardInfo.SD_csd.RdBlockLen); + SD_cardInfo.CardCapacity *= SD_cardInfo.CardBlockSize; + } + else if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + /*!< Byte 7 */ + tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); + SD_cardInfo.SD_csd.DeviceSize = (tmp & 0x3F) << 16; + + /*!< Byte 8 */ + tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); + + SD_cardInfo.SD_csd.DeviceSize |= (tmp << 8); + + /*!< Byte 9 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); + + SD_cardInfo.SD_csd.DeviceSize |= (tmp); + + /*!< Byte 10 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); + + SD_cardInfo.CardCapacity = (SD_cardInfo.SD_csd.DeviceSize + 1) * 512 * 1024; + SD_cardInfo.CardBlockSize = 512; + } + + SD_cardInfo.SD_csd.EraseGrSize = (tmp & 0x40) >> 6; + SD_cardInfo.SD_csd.EraseGrMul = (tmp & 0x3F) << 1; + + /*!< Byte 11 */ + tmp = (uint8_t)(CSD_Tab[2] & 0x000000FF); + SD_cardInfo.SD_csd.EraseGrMul |= (tmp & 0x80) >> 7; + SD_cardInfo.SD_csd.WrProtectGrSize = (tmp & 0x7F); + + /*!< Byte 12 */ + tmp = (uint8_t)((CSD_Tab[3] & 0xFF000000) >> 24); + SD_cardInfo.SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; + SD_cardInfo.SD_csd.ManDeflECC = (tmp & 0x60) >> 5; + SD_cardInfo.SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; + SD_cardInfo.SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2; + + /*!< Byte 13 */ + tmp = (uint8_t)((CSD_Tab[3] & 0x00FF0000) >> 16); + SD_cardInfo.SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6; + SD_cardInfo.SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5; + SD_cardInfo.SD_csd.Reserved3 = 0; + SD_cardInfo.SD_csd.ContentProtectAppli = (tmp & 0x01); + + /*!< Byte 14 */ + tmp = (uint8_t)((CSD_Tab[3] & 0x0000FF00) >> 8); + SD_cardInfo.SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7; + SD_cardInfo.SD_csd.CopyFlag = (tmp & 0x40) >> 6; + SD_cardInfo.SD_csd.PermWrProtect = (tmp & 0x20) >> 5; + SD_cardInfo.SD_csd.TempWrProtect = (tmp & 0x10) >> 4; + SD_cardInfo.SD_csd.FileFormat = (tmp & 0x0C) >> 2; + SD_cardInfo.SD_csd.ECC = (tmp & 0x03); +} + +uint32_t calcSDCLKDiv(uint32_t freq_sel) +{ + uint32_t regdiv = 0; + uint32_t clkdiv = 0; + + if (((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos) == 1) + clkdiv = SystemCoreClock / 2 / ((freq_sel == SD_CLK_400KHz) ? 300000 : 15000000); + else if (((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos) == 2) + clkdiv = SystemCoreClock / 4 / ((freq_sel == SD_CLK_400KHz) ? 300000 : 15000000); + + if (clkdiv > 128) regdiv = 0x80; + else if (clkdiv > 64) regdiv = 0x40; + else if (clkdiv > 32) regdiv = 0x20; + else if (clkdiv > 16) regdiv = 0x10; + else if (clkdiv > 8) regdiv = 0x08; + else if (clkdiv > 4) regdiv = 0x04; + else if (clkdiv > 2) regdiv = 0x02; + else if (clkdiv > 1) regdiv = 0x01; + else regdiv = 0x00; + + return regdiv; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h new file mode 100644 index 0000000000..1df6602159 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h @@ -0,0 +1,139 @@ +#ifndef __SWM320_SDIO_H__ +#define __SWM320_SDIO_H__ + + +#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) +#define SD_CMD_SEND_OP_COND ((uint8_t)1) +#define SD_CMD_ALL_SEND_CID ((uint8_t)2) +#define SD_CMD_SET_REL_ADDR ((uint8_t)3) +#define SD_CMD_SET_DSR ((uint8_t)4) +#define SD_CMD_HS_SWITCH ((uint8_t)6) +#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) +#define SD_CMD_SEND_IF_COND ((uint8_t)8) +#define SD_CMD_SEND_CSD ((uint8_t)9) +#define SD_CMD_SEND_CID ((uint8_t)10) +#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) +#define SD_CMD_SEND_STATUS ((uint8_t)13) +#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) +#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) +#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) +#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) +#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) +#define SD_CMD_PROG_CID ((uint8_t)26) +#define SD_CMD_PROG_CSD ((uint8_t)27) +#define SD_CMD_APP_CMD ((uint8_t)55) + +/*Following commands are SD Card Specific commands. + SDIO_APP_CMD should be sent before sending these commands. */ +#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) +#define SD_CMD_SD_APP_STAUS ((uint8_t)13) +#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) +#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) +#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) +#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) +#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) +#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) + + +#define SD_RESP_NO 0 //0 ÎÞÏìÓ¦ +#define SD_RESP_32b 2 //2 32λÏìÓ¦ +#define SD_RESP_128b 1 //1 128λÏìÓ¦ +#define SD_RESP_32b_busy 3 //3 32λÏìÓ¦£¬check Busy after response + +#define SD_CLK_400KHz 0 +#define SD_CLK_20MHz 1 + +#define SD_BUSWIDTH_1b 0 +#define SD_BUSWIDTH_4b 2 + +#define SD_RES_OK 0 +#define SD_RES_ERR 1 + + +typedef struct +{ + __IO uint8_t CSDStruct; // CSD structure + __IO uint8_t SysSpecVersion; // System specification version + __IO uint8_t Reserved1; // Reserved + __IO uint8_t TAAC; // Data read access-time 1 + __IO uint8_t NSAC; // Data read access-time 2 in CLK cycles + __IO uint8_t MaxBusClkFrec; // Max. bus clock frequency + __IO uint16_t CardComdClasses; //< Card command classes + __IO uint8_t RdBlockLen; // Max. read data block length + __IO uint8_t PartBlockRead; // Partial blocks for read allowed + __IO uint8_t WrBlockMisalign; // Write block misalignment + __IO uint8_t RdBlockMisalign; // Read block misalignment + __IO uint8_t DSRImpl; // DSR implemented + __IO uint8_t Reserved2; // Reserved + __IO uint32_t DeviceSize; // Device Size + __IO uint8_t MaxRdCurrentVDDMin; // Max. read current @ VDD min + __IO uint8_t MaxRdCurrentVDDMax; // Max. read current @ VDD max + __IO uint8_t MaxWrCurrentVDDMin; // Max. write current @ VDD min + __IO uint8_t MaxWrCurrentVDDMax; // Max. write current @ VDD max + __IO uint8_t DeviceSizeMul; // Device size multiplier + __IO uint8_t EraseGrSize; // Erase group size + __IO uint8_t EraseGrMul; // Erase group size multiplier + __IO uint8_t WrProtectGrSize; // Write protect group size + __IO uint8_t WrProtectGrEnable; // Write protect group enable + __IO uint8_t ManDeflECC; // Manufacturer default ECC + __IO uint8_t WrSpeedFact; // Write speed factor + __IO uint8_t MaxWrBlockLen; // Max. write data block length + __IO uint8_t WriteBlockPaPartial; // Partial blocks for write allowed + __IO uint8_t Reserved3; // Reserded + __IO uint8_t ContentProtectAppli; // Content protection application + __IO uint8_t FileFormatGrouop; // File format group + __IO uint8_t CopyFlag; // Copy flag (OTP) + __IO uint8_t PermWrProtect; // Permanent write protection + __IO uint8_t TempWrProtect; // Temporary write protection + __IO uint8_t FileFormat; // File Format + __IO uint8_t ECC; // ECC code +} SD_CSD; + +typedef struct +{ + __IO uint8_t ManufacturerID; // ManufacturerID + __IO uint16_t OEM_AppliID; // OEM/Application ID + __IO uint32_t ProdName1; // Product Name part1 + __IO uint8_t ProdName2; // Product Name part2 + __IO uint8_t ProdRev; // Product Revision + __IO uint32_t ProdSN; // Product Serial Number + __IO uint8_t Reserved1; // Reserved1 + __IO uint16_t ManufactDate; // Manufacturing Date +} SD_CID; + + +#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) +#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) +#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) +#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003) +#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) +#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) +#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) +#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) + + +typedef struct +{ + SD_CSD SD_csd; + SD_CID SD_cid; + uint64_t CardCapacity; // Card Capacity + uint32_t CardBlockSize; // Card Block Size + uint16_t RCA; + uint8_t CardType; +} SD_CardInfo; + + +extern SD_CardInfo SD_cardInfo; + +uint32_t SDIO_Init(void); +void SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]); +void SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]); + +void SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read); + +void parseCID(uint32_t CID_Tab[4]); +void parseCSD(uint32_t CID_Tab[4]); + +uint32_t calcSDCLKDiv(uint32_t freq_sel); + +#endif //__SWM320_SDIO_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c new file mode 100644 index 0000000000..f07af4ee51 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c @@ -0,0 +1,58 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_sdram.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄSDRAMÇý¶¯³ÌÐò +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_sdram.h" + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SDRAM_Init() +* ¹¦ÄÜ˵Ã÷: SDRAM¿ØÖÆÆ÷³õʼ»¯ +* Êä Èë: SDRAM_InitStructure * initStruct °üº¬NOR Flash¿ØÖÆÆ÷Ïà¹ØÉ趨ֵµÄ½á¹¹Ìå +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SDRAM_Init(SDRAM_InitStructure *initStruct) +{ + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + + SYS->CLKDIV &= ~SYS_CLKDIV_SDRAM_Msk; + SYS->CLKDIV |= (1 << SYS_CLKDIV_SDRAM_Pos); //2·ÖƵ + + SDRAMC->CR0 = (2 << SDRAMC_CR0_BURSTLEN_Pos) | //2 Burst LengthΪ4 + (2 << SDRAMC_CR0_CASDELAY_Pos); + + SDRAMC->CR1 = (initStruct->CellSize << SDRAMC_CR1_CELLSIZE_Pos) | + ((initStruct->CellWidth == 16 ? 0 : 1) << SDRAMC_CR1_CELL32BIT_Pos) | + (initStruct->CellBank << SDRAMC_CR1_BANK_Pos) | + ((initStruct->DataWidth == 16 ? 0 : 1) << SDRAMC_CR1_32BIT_Pos) | + (7 << SDRAMC_CR1_TMRD_Pos) | + (3 << SDRAMC_CR1_TRRD_Pos) | + (7 << SDRAMC_CR1_TRAS_Pos) | + (8 << SDRAMC_CR1_TRC_Pos) | + (3 << SDRAMC_CR1_TRCD_Pos) | + (3 << SDRAMC_CR1_TRP_Pos); + + SDRAMC->LATCH = 0x02; + + SDRAMC->REFRESH = (1 << SDRAMC_REFRESH_EN_Pos) | + (0x0FA << SDRAMC_REFRESH_RATE_Pos); + + while (SDRAMC->REFDONE == 0); +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h new file mode 100644 index 0000000000..c10d82fc12 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h @@ -0,0 +1,23 @@ +#ifndef __SWM320_SDRAM_H__ +#define __SWM320_SDRAM_H__ + +typedef struct +{ + uint8_t DataWidth; // 16¡¢32 + + uint8_t CellSize; // SDRAM¿ÅÁ£µÄÈÝÁ¿ + uint8_t CellBank; // SDRAM¿ÅÁ£Óм¸¸öbank + uint8_t CellWidth; // SDRAM¿ÅÁ£µÄλ¿í 16¡¢32 +} SDRAM_InitStructure; + +#define SDRAM_CELLSIZE_16Mb 3 +#define SDRAM_CELLSIZE_64Mb 0 +#define SDRAM_CELLSIZE_128Mb 1 +#define SDRAM_CELLSIZE_256Mb 2 + +#define SDRAM_CELLBANK_2 0 +#define SDRAM_CELLBANK_4 1 + +void SDRAM_Init(SDRAM_InitStructure *initStruct); + +#endif //__SWM320_SDRAM_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c new file mode 100644 index 0000000000..6c88ada224 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c @@ -0,0 +1,447 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_spi.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄSPI¹¦ÄÜÇý¶¯¿â +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_spi.h" + + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_Init() +* ¹¦ÄÜ˵Ã÷: SPIͬ²½´®Ðнӿڳõʼ»¯£¬°üÀ¨Ö¡³¤¶ÈÉ趨¡¢Ê±ÐòÉ趨¡¢ËÙ¶ÈÉ趨¡¢ÖжÏÉ趨¡¢FIFO´¥·¢É趨 +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* SPI_InitStructure * initStruct °üº¬SPIÏà¹ØÉ趨ֵµÄ½á¹¹Ìå +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct) +{ + switch ((uint32_t)SPIx) + { + case ((uint32_t)SPI0): + SYS->CLKEN |= (0x01 << SYS_CLKEN_SPI0_Pos); + break; + + case ((uint32_t)SPI1): + SYS->CLKEN |= (0x01 << SYS_CLKEN_SPI0_Pos); //ÓëSPI0ʹÓÃͬһλʱÖÓʹÄÜ + break; + } + + SPI_Close(SPIx); //һЩ¹Ø¼ü¼Ä´æÆ÷Ö»ÄÜÔÚSPI¹Ø±ÕʱÉèÖà + + SPIx->CTRL &= ~(SPI_CTRL_FFS_Msk | SPI_CTRL_CPHA_Msk | SPI_CTRL_CPOL_Msk | + SPI_CTRL_SIZE_Msk | SPI_CTRL_MSTR_Msk | SPI_CTRL_CLKDIV_Msk | SPI_CTRL_SSN_H_Msk); + SPIx->CTRL |= (initStruct->FrameFormat << SPI_CTRL_FFS_Pos) | + (initStruct->SampleEdge << SPI_CTRL_CPHA_Pos) | + (initStruct->IdleLevel << SPI_CTRL_CPOL_Pos) | + ((initStruct->WordSize - 1) << SPI_CTRL_SIZE_Pos) | + (initStruct->Master << SPI_CTRL_MSTR_Pos) | + (initStruct->clkDiv << SPI_CTRL_CLKDIV_Pos) | + (0 << SPI_CTRL_SSN_H_Pos); + + SPIx->IF = (0x01 << SPI_IF_RFOVF_Pos); //Çå³ýÖжϱêÖ¾ + SPIx->IE &= ~(SPI_IE_RFHF_Msk | SPI_IE_TFHF_Msk | SPI_IE_FTC_Msk); + SPIx->IE |= (initStruct->RXHFullIEn << SPI_IE_RFHF_Pos) | + (initStruct->TXEmptyIEn << SPI_IE_TFHF_Pos) | + (initStruct->TXCompleteIEn << SPI_IE_FTC_Pos); + + switch ((uint32_t)SPIx) + { + case ((uint32_t)SPI0): + if (initStruct->RXHFullIEn | initStruct->TXEmptyIEn | initStruct->TXCompleteIEn) + { + NVIC_EnableIRQ(SPI0_IRQn); + } + else + { + NVIC_DisableIRQ(SPI0_IRQn); + } + break; + + case ((uint32_t)SPI1): + if (initStruct->RXHFullIEn | initStruct->TXEmptyIEn | initStruct->TXCompleteIEn) + { + NVIC_EnableIRQ(SPI1_IRQn); + } + else + { + NVIC_DisableIRQ(SPI1_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_Open() +* ¹¦ÄÜ˵Ã÷: SPI´ò¿ª£¬ÔÊÐíÊÕ·¢ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_Open(SPI_TypeDef *SPIx) +{ + SPIx->CTRL |= (0x01 << SPI_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_Close() +* ¹¦ÄÜ˵Ã÷: SPI¹Ø±Õ£¬½ûÖ¹ÊÕ·¢ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_Close(SPI_TypeDef *SPIx) +{ + SPIx->CTRL &= ~SPI_CTRL_EN_Msk; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_Read() +* ¹¦ÄÜ˵Ã÷: ¶ÁÈ¡Ò»¸öÊý¾Ý +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: uint32_t ¶ÁÈ¡µ½µÄÊý¾Ý +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t SPI_Read(SPI_TypeDef *SPIx) +{ + return SPIx->DATA; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_Write() +* ¹¦ÄÜ˵Ã÷: дÈëÒ»¸öÊý¾Ý +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* uint32_t ҪдÈëµÄÊý¾Ý +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_Write(SPI_TypeDef *SPIx, uint32_t data) +{ + SPIx->DATA = data; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_WriteWithWait() +* ¹¦ÄÜ˵Ã÷: дÈëÒ»¸öÊý¾Ý²¢µÈ´ýÊý¾ÝÍêÈ«·¢ËͳöÈ¥ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1¡¢SPI1 +* uint32_t ҪдÈëµÄÊý¾Ý +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_WriteWithWait(SPI_TypeDef *SPIx, uint32_t data) +{ + SPIx->STAT |= (1 << SPI_STAT_WTC_Pos); + + SPIx->DATA = data; + + while ((SPIx->STAT & SPI_STAT_WTC_Msk) == 0); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_ReadWrite() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍÒ»¸öÊý¾Ý£¬²¢·µ»Ø·¢Ë͹ý³ÌÖнÓÊÕµ½µÄ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* uint32_t data Òª·¢Ë͵ÄÊý¾Ý +* Êä ³ö: uint32_t ½ÓÊÕµ½µÄÊý¾Ý +* ×¢ÒâÊÂÏî: ¶ÔÓÚͬһ¸öSPIÄ£¿é£¬´Ëº¯Êý²»Ó¦ÓëSPI_Write()»ì×ÅÓã¬ÒòΪSPI_Write()²»Çå³ýSPI_STAT_RFNE״̬ +******************************************************************************************************************************************/ +uint32_t SPI_ReadWrite(SPI_TypeDef *SPIx, uint32_t data) +{ + SPIx->DATA = data; + while (!(SPIx->STAT & SPI_STAT_RFNE_Msk)); + + return SPIx->DATA; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_IsRXEmpty() +* ¹¦ÄÜ˵Ã÷: ½ÓÊÕFIFOÊÇ·ñ¿Õ£¬Èç¹û²»¿ÕÔò¿ÉÒÔ¼ÌÐøSPI_Read() +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: uint32_t 1 ½ÓÊÕFIFO¿Õ 0 ½ÓÊÕFIFO·Ç¿Õ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx) +{ + return (SPIx->STAT & SPI_STAT_RFNE_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_IsTXFull() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFOÊÇ·ñÂú£¬Èç¹û²»ÂúÔò¿ÉÒÔ¼ÌÐøSPI_Write() +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: uint32_t 1 ·¢ËÍFIFOÂú 0 ·¢ËÍFIFO²»Âú +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx) +{ + return (SPIx->STAT & SPI_STAT_TFNF_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_IsTXEmpty() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFOÊÇ·ñ¿Õ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: uint32_t 1 ·¢ËÍFIFO¿Õ 0 ·¢ËÍFIFO·Ç¿Õ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t SPI_IsTXEmpty(SPI_TypeDef *SPIx) +{ + return (SPIx->STAT & SPI_STAT_TFE_Msk) ? 1 : 0; +} + + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTRXHalfFullEn() +* ¹¦ÄÜ˵Ã÷: ½ÓÊÕFIFO°ëÂúÖжÏʹÄÜ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_INTRXHalfFullEn(SPI_TypeDef *SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_RFHF_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTRXHalfFullDis() +* ¹¦ÄÜ˵Ã÷: ½ÓÊÕFIFO°ëÂúÖжϽûÖ¹ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_INTRXHalfFullDis(SPI_TypeDef *SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_RFHF_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTRXHalfFullStat() +* ¹¦ÄÜ˵Ã÷: ½ÓÊÕFIFO°ëÂúÖжÏ״̬ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: uint32_t 1 ½ÓÊÕFIFO´ïµ½°ëÂú 0 ½ÓÊÕFIFOδ´ïµ½°ëÂú +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef *SPIx) +{ + return (SPIx->IF & SPI_IF_RFHF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTRXFullEn() +* ¹¦ÄÜ˵Ã÷: ½ÓÊÕFIFOÂúÖжÏʹÄÜ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_INTRXFullEn(SPI_TypeDef *SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_RFF_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTRXFullDis() +* ¹¦ÄÜ˵Ã÷: ½ÓÊÕFIFOÂúÖжϽûÖ¹ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_INTRXFullDis(SPI_TypeDef *SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_RFF_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTRXFullStat() +* ¹¦ÄÜ˵Ã÷: ½ÓÊÕFIFOÂúÖжÏ״̬ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: uint32_t 1 ½ÓÊÕFIFOÂú 0 ½ÓÊÕFIFOδÂú +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t SPI_INTRXFullStat(SPI_TypeDef *SPIx) +{ + return (SPIx->IF & SPI_IF_RFF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTRXOverflowEn() +* ¹¦ÄÜ˵Ã÷: ½ÓÊÕFIFOÒç³öÖжÏʹÄÜ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_INTRXOverflowEn(SPI_TypeDef *SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_RFOVF_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTRXOverflowDis() +* ¹¦ÄÜ˵Ã÷: ½ÓÊÕFIFOÒç³öÖжϽûÖ¹ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_INTRXOverflowDis(SPI_TypeDef *SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_RFOVF_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTRXOverflowClr() +* ¹¦ÄÜ˵Ã÷: ½ÓÊÕFIFOÒç³öÖжϱêÖ¾Çå³ý +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_INTRXOverflowClr(SPI_TypeDef *SPIx) +{ + SPIx->IF = (0x01 << SPI_IF_RFOVF_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTRXOverflowStat() +* ¹¦ÄÜ˵Ã÷: ½ÓÊÕFIFOÒç³öÖжÏ״̬ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: uint32_t 1 ½ÓÊÕFIFOÒç³ö 0 ½ÓÊÕFIFOδÒç³ö +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t SPI_INTRXOverflowStat(SPI_TypeDef *SPIx) +{ + return (SPIx->IF & SPI_IF_RFOVF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTTXHalfFullEn() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFO°ëÂúÖжÏʹÄÜ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_INTTXHalfFullEn(SPI_TypeDef *SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_TFHF_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTTXHalfFullDis() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFO°ëÂúÖжϽûÖ¹ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_INTTXHalfFullDis(SPI_TypeDef *SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_TFHF_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTTXHalfFullStat() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFO°ëÂúÖжÏ״̬ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: uint32_t 1 ·¢ËÍFIFO´ïµ½°ëÂú 0 ·¢ËÍFIFOδ´ïµ½°ëÂú +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef *SPIx) +{ + return (SPIx->IF & SPI_IF_TFHF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTTXEmptyEn() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFO¿ÕÖжÏʹÄÜ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_INTTXEmptyEn(SPI_TypeDef *SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_TFE_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTTXEmptyDis() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFO¿ÕÖжϽûÖ¹ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_INTTXEmptyDis(SPI_TypeDef *SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_TFE_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTTXEmptyStat() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFO¿ÕÖжÏ״̬ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: uint32_t 1 ·¢ËÍFIFO¿Õ 0 ·¢ËÍFIFO·Ç¿Õ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t SPI_INTTXEmptyStat(SPI_TypeDef *SPIx) +{ + return (SPIx->IF & SPI_IF_TFE_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTTXCompleteEn() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFO¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжÏʹÄÜ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_INTTXCompleteEn(SPI_TypeDef *SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_FTC_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTTXCompleteDis() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFO¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжϽûÖ¹ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_INTTXCompleteDis(SPI_TypeDef *SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_FTC_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTTXCompleteClr() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFO¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжÏ״̬Çå³ý +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void SPI_INTTXCompleteClr(SPI_TypeDef *SPIx) +{ + SPIx->IF = (1 << SPI_IF_FTC_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: SPI_INTTXCompleteStat() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFO¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжÏ״̬ +* Êä Èë: SPI_TypeDef * SPIx Ö¸¶¨Òª±»ÉèÖõÄSPI£¬ÓÐЧֵ°üÀ¨SPI0¡¢SPI1 +* Êä ³ö: uint32_t 1 ·¢ËÍFIFO¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿Õ 0 ·¢ËÍFIFO»ò·¢ËÍÒÆλ¼Ä´æÆ÷·Ç¿Õ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t SPI_INTTXCompleteStat(SPI_TypeDef *SPIx) +{ + return (SPIx->IF & SPI_IF_FTC_Msk) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h new file mode 100644 index 0000000000..3230c4a774 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h @@ -0,0 +1,75 @@ +#ifndef __SWM320_SPI_H__ +#define __SWM320_SPI_H__ + +typedef struct +{ + uint8_t FrameFormat; //Ö¡¸ñʽ£ºSPI_FORMAT_SPI¡¢SPI_FORMAT_TI_SSI + uint8_t SampleEdge; //ÔÚSPIÖ¡¸ñʽÏ£¬Ñ¡ÔñÊý¾Ý²ÉÑù±ßÑØ£ºSPI_FIRST_EDGE¡¢SPI_SECOND_EDGE + uint8_t IdleLevel; //ÔÚSPIÖ¡¸ñʽÏ£¬Ñ¡Ôñ¿ÕÏÐʱ£¨ÎÞÊý¾Ý´«Êäʱ£©Ê±ÖÓÏߵĵçƽ£ºSPI_LOW_LEVEL¡¢SPI_HIGH_LEVEL + uint8_t WordSize; //×Ö³¤¶È, ÓÐЧֵ4-16 + uint8_t Master; //1 Ö÷»úģʽ 0 ´Ó»úģʽ + uint8_t clkDiv; //SPI_CLK = SYS_CLK / clkDiv£¬ÓÐЧֵ£ºSPI_CLKDIV_4¡¢SPI_CLKDIV_8¡¢... ... ¡¢SPI_CLKDIV_512 + + uint8_t RXHFullIEn; //½ÓÊÕFIFO°ëÂúÖжÏʹÄÜ + uint8_t TXEmptyIEn; //·¢ËÍFIFO ¿ÕÖжÏʹÄÜ + uint8_t TXCompleteIEn; //·¢ËÍFIFO ¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжÏʹÄÜ +} SPI_InitStructure; + +#define SPI_FORMAT_SPI 0 //Motorola SPI ¸ñʽ +#define SPI_FORMAT_TI_SSI 1 //TI SSI ¸ñʽ + +#define SPI_FIRST_EDGE 0 //µÚÒ»¸öʱÖÓÑØ¿ªÊ¼²ÉÑù +#define SPI_SECOND_EDGE 1 //µÚ¶þ¸öʱÖÓÑØ¿ªÊ¼²ÉÑù + +#define SPI_LOW_LEVEL 0 //¿ÕÏÐʱʱÖÓÏß±£³ÖµÍµçƽ +#define SPI_HIGH_LEVEL 1 //¿ÕÏÐʱʱÖÓÏß±£³Ö¸ßµçƽ + +#define SPI_CLKDIV_4 0 +#define SPI_CLKDIV_8 1 +#define SPI_CLKDIV_16 2 +#define SPI_CLKDIV_32 3 +#define SPI_CLKDIV_64 4 +#define SPI_CLKDIV_128 5 +#define SPI_CLKDIV_256 6 +#define SPI_CLKDIV_512 7 + + + +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct); //SPI³õʼ»¯ +void SPI_Open(SPI_TypeDef *SPIx); //SPI´ò¿ª£¬ÔÊÐíÊÕ·¢ +void SPI_Close(SPI_TypeDef *SPIx); //SPI¹Ø±Õ£¬½ûÖ¹ÊÕ·¢ + +uint32_t SPI_Read(SPI_TypeDef *SPIx); +void SPI_Write(SPI_TypeDef *SPIx, uint32_t data); +void SPI_WriteWithWait(SPI_TypeDef *SPIx, uint32_t data); +uint32_t SPI_ReadWrite(SPI_TypeDef *SPIx, uint32_t data); + +uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx); //½ÓÊÕFIFOÊÇ·ñ¿Õ£¬Èç¹û²»¿ÕÔò¿ÉÒÔ¼ÌÐøSPI_Read() +uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx); //·¢ËÍFIFOÊÇ·ñÂú£¬Èç¹û²»ÂúÔò¿ÉÒÔ¼ÌÐøSPI_Write() +uint32_t SPI_IsTXEmpty(SPI_TypeDef *SPIx); //·¢ËÍFIFOÊÇ·ñ¿Õ + + +void SPI_INTRXHalfFullEn(SPI_TypeDef *SPIx); +void SPI_INTRXHalfFullDis(SPI_TypeDef *SPIx); +uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef *SPIx); +void SPI_INTRXFullEn(SPI_TypeDef *SPIx); +void SPI_INTRXFullDis(SPI_TypeDef *SPIx); +uint32_t SPI_INTRXFullStat(SPI_TypeDef *SPIx); +void SPI_INTRXOverflowEn(SPI_TypeDef *SPIx); +void SPI_INTRXOverflowDis(SPI_TypeDef *SPIx); +void SPI_INTRXOverflowClr(SPI_TypeDef *SPIx); +uint32_t SPI_INTRXOverflowStat(SPI_TypeDef *SPIx); + +void SPI_INTTXHalfFullEn(SPI_TypeDef *SPIx); +void SPI_INTTXHalfFullDis(SPI_TypeDef *SPIx); +uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef *SPIx); +void SPI_INTTXEmptyEn(SPI_TypeDef *SPIx); +void SPI_INTTXEmptyDis(SPI_TypeDef *SPIx); +uint32_t SPI_INTTXEmptyStat(SPI_TypeDef *SPIx); +void SPI_INTTXCompleteEn(SPI_TypeDef *SPIx); +void SPI_INTTXCompleteDis(SPI_TypeDef *SPIx); +void SPI_INTTXCompleteClr(SPI_TypeDef *SPIx); +uint32_t SPI_INTTXCompleteStat(SPI_TypeDef *SPIx); + + +#endif //__SWM320_SPI_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c new file mode 100644 index 0000000000..769cc2e779 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c @@ -0,0 +1,381 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_timr.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄ¼ÆÊýÆ÷/¶¨Ê±Æ÷¹¦ÄÜÇý¶¯¿â +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_timr.h" + + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: TIMR_Init() +* ¹¦ÄÜ˵Ã÷: TIMR¶¨Ê±Æ÷/¼ÆÊýÆ÷³õʼ»¯ +* Êä Èë: TIMR_TypeDef * TIMRx Ö¸¶¨Òª±»ÉèÖõĶ¨Ê±Æ÷£¬ÓÐЧֵ°üÀ¨TIMR0¡¢TIMR1¡¢TIMR2¡¢TIMR3¡¢TIMR4¡¢TIMR5 +* uint32_t mode TIMR_MODE_TIMER ¶¨Ê±Æ÷ģʽ TIMR_MODE_COUNTER ¼ÆÊýÆ÷ģʽ +* uint32_t period ¶¨Ê±/¼ÆÊýÖÜÆÚ +* uint32_t int_en ÖжÏʹÄÜ +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en) +{ + SYS->CLKEN |= (0x01 << SYS_CLKEN_TIMR_Pos); + + TIMR_Stop(TIMRx); //һЩ¹Ø¼ü¼Ä´æÆ÷Ö»ÄÜÔÚ¶¨Ê±Æ÷ֹͣʱÉèÖà + + TIMRx->CTRL &= ~TIMR_CTRL_CLKSRC_Msk; + TIMRx->CTRL |= mode << TIMR_CTRL_CLKSRC_Pos; + + TIMRx->LDVAL = period; + + switch ((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->IF = (1 << TIMRG_IF_TIMR0_Pos); //ʹÄÜÖжÏÇ°Çå³ýÖжϱêÖ¾ + TIMRG->IE &= ~TIMRG_IE_TIMR0_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR0_Pos); + + if (int_en) NVIC_EnableIRQ(TIMR0_IRQn); + break; + + case ((uint32_t)TIMR1): + TIMRG->IF = (1 << TIMRG_IF_TIMR1_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR1_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR1_Pos); + + if (int_en) NVIC_EnableIRQ(TIMR1_IRQn); + break; + + case ((uint32_t)TIMR2): + TIMRG->IF = (1 << TIMRG_IF_TIMR2_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR2_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR2_Pos); + + if (int_en) NVIC_EnableIRQ(TIMR2_IRQn); + break; + + case ((uint32_t)TIMR3): + TIMRG->IF = (1 << TIMRG_IF_TIMR3_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR3_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR3_Pos); + + if (int_en) NVIC_EnableIRQ(TIMR3_IRQn); + break; + + case ((uint32_t)TIMR4): + TIMRG->IF = (1 << TIMRG_IF_TIMR4_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR4_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR4_Pos); + + if (int_en) NVIC_EnableIRQ(TIMR4_IRQn); + break; + + case ((uint32_t)TIMR5): + TIMRG->IF = (1 << TIMRG_IF_TIMR5_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR5_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR5_Pos); + + if (int_en) NVIC_EnableIRQ(TIMR5_IRQn); + break; + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: TIMR_Start() +* ¹¦ÄÜ˵Ã÷: Æô¶¯¶¨Ê±Æ÷£¬´Ó³õʼֵ¿ªÊ¼¼Æʱ/¼ÆÊý +* Êä Èë: TIMR_TypeDef * TIMRx Ö¸¶¨Òª±»ÉèÖõĶ¨Ê±Æ÷£¬¿ÉÈ¡Öµ°üÀ¨TIMR0¡¢TIMR1¡¢TIMR2¡¢TIMR3¡¢TIMR4¡¢TIMR5 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void TIMR_Start(TIMR_TypeDef *TIMRx) +{ + TIMRx->CTRL |= TIMR_CTRL_EN_Msk; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: TIMR_Stop() +* ¹¦ÄÜ˵Ã÷: Í£Ö¹¶¨Ê±Æ÷ +* Êä Èë: TIMR_TypeDef * TIMRx Ö¸¶¨Òª±»ÉèÖõĶ¨Ê±Æ÷£¬¿ÉÈ¡Öµ°üÀ¨TIMR0¡¢TIMR1¡¢TIMR2¡¢TIMR3¡¢TIMR4¡¢TIMR5 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void TIMR_Stop(TIMR_TypeDef *TIMRx) +{ + TIMRx->CTRL &= ~TIMR_CTRL_EN_Msk; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: TIMR_Halt() +* ¹¦ÄÜ˵Ã÷: ÔÝÍ£¶¨Ê±Æ÷£¬¼ÆÊýÖµ±£³Ö²»±ä +* Êä Èë: TIMR_TypeDef * TIMRx Ö¸¶¨Òª±»ÉèÖõĶ¨Ê±Æ÷£¬¿ÉÈ¡Öµ°üÀ¨TIMR0¡¢TIMR1¡¢TIMR2¡¢TIMR3¡¢TIMR4¡¢TIMR5 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void TIMR_Halt(TIMR_TypeDef *TIMRx) +{ + switch ((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR0_Pos); + break; + + case ((uint32_t)TIMR1): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR1_Pos); + break; + + case ((uint32_t)TIMR2): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR2_Pos); + break; + + case ((uint32_t)TIMR3): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR3_Pos); + break; + + case ((uint32_t)TIMR4): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR4_Pos); + break; + + case ((uint32_t)TIMR5): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR5_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: TIMR_Resume() +* ¹¦ÄÜ˵Ã÷: »Ö¸´¶¨Ê±Æ÷£¬´ÓÔÝÍ£´¦¼ÌÐø¼ÆÊý +* Êä Èë: TIMR_TypeDef * TIMRx Ö¸¶¨Òª±»ÉèÖõĶ¨Ê±Æ÷£¬¿ÉÈ¡Öµ°üÀ¨TIMR0¡¢TIMR1¡¢TIMR2¡¢TIMR3¡¢TIMR4¡¢TIMR5 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void TIMR_Resume(TIMR_TypeDef *TIMRx) +{ + switch ((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR0_Pos); + break; + + case ((uint32_t)TIMR1): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR1_Pos); + break; + + case ((uint32_t)TIMR2): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR2_Pos); + break; + + case ((uint32_t)TIMR3): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR3_Pos); + break; + + case ((uint32_t)TIMR4): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR4_Pos); + break; + + case ((uint32_t)TIMR5): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR5_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: TIMR_SetPeriod() +* ¹¦ÄÜ˵Ã÷: ÉèÖö¨Ê±/¼ÆÊýÖÜÆÚ +* Êä Èë: TIMR_TypeDef * TIMRx Ö¸¶¨Òª±»ÉèÖõĶ¨Ê±Æ÷£¬¿ÉÈ¡Öµ°üÀ¨TIMR0¡¢TIMR1¡¢TIMR2¡¢TIMR3¡¢TIMR4¡¢TIMR5 +* uint32_t period ¶¨Ê±/¼ÆÊýÖÜÆÚ +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period) +{ + TIMRx->LDVAL = period; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: TIMR_GetPeriod() +* ¹¦ÄÜ˵Ã÷: »ñÈ¡¶¨Ê±/¼ÆÊýÖÜÆÚ +* Êä Èë: TIMR_TypeDef * TIMRx Ö¸¶¨Òª±»ÉèÖõĶ¨Ê±Æ÷£¬¿ÉÈ¡Öµ°üÀ¨TIMR0¡¢TIMR1¡¢TIMR2¡¢TIMR3¡¢TIMR4¡¢TIMR5 +* Êä ³ö: uint32_t µ±Ç°¶¨Ê±/¼ÆÊýÖÜÆÚ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx) +{ + return TIMRx->LDVAL; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: TIMR_GetCurValue() +* ¹¦ÄÜ˵Ã÷: »ñÈ¡µ±Ç°¼ÆÊýÖµ +* Êä Èë: TIMR_TypeDef * TIMRx Ö¸¶¨Òª±»ÉèÖõĶ¨Ê±Æ÷£¬¿ÉÈ¡Öµ°üÀ¨TIMR0¡¢TIMR1¡¢TIMR2¡¢TIMR3¡¢TIMR4¡¢TIMR5 +* Êä ³ö: uint32_t µ±Ç°¼ÆÊýÖµ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx) +{ + return TIMRx->CVAL; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: TIMR_INTEn() +* ¹¦ÄÜ˵Ã÷: ʹÄÜÖÐ¶Ï +* Êä Èë: TIMR_TypeDef * TIMRx Ö¸¶¨Òª±»ÉèÖõĶ¨Ê±Æ÷£¬¿ÉÈ¡Öµ°üÀ¨TIMR0¡¢TIMR1¡¢TIMR2¡¢TIMR3¡¢TIMR4¡¢TIMR5 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void TIMR_INTEn(TIMR_TypeDef *TIMRx) +{ + switch ((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR0_Pos); + NVIC_EnableIRQ(TIMR0_IRQn); + break; + + case ((uint32_t)TIMR1): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR1_Pos); + NVIC_EnableIRQ(TIMR1_IRQn); + break; + + case ((uint32_t)TIMR2): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR2_Pos); + NVIC_EnableIRQ(TIMR2_IRQn); + break; + + case ((uint32_t)TIMR3): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR3_Pos); + NVIC_EnableIRQ(TIMR3_IRQn); + break; + + case ((uint32_t)TIMR4): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR4_Pos); + NVIC_EnableIRQ(TIMR4_IRQn); + break; + + case ((uint32_t)TIMR5): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR5_Pos); + NVIC_EnableIRQ(TIMR5_IRQn); + break; + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: TIMR_INTDis() +* ¹¦ÄÜ˵Ã÷: ½ûÄÜÖÐ¶Ï +* Êä Èë: TIMR_TypeDef * TIMRx Ö¸¶¨Òª±»ÉèÖõĶ¨Ê±Æ÷£¬¿ÉÈ¡Öµ°üÀ¨TIMR0¡¢TIMR1¡¢TIMR2¡¢TIMR3¡¢TIMR4¡¢TIMR5 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void TIMR_INTDis(TIMR_TypeDef *TIMRx) +{ + switch ((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR0_Pos); + break; + + case ((uint32_t)TIMR1): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR1_Pos); + break; + + case ((uint32_t)TIMR2): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR2_Pos); + break; + + case ((uint32_t)TIMR3): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR3_Pos); + break; + + case ((uint32_t)TIMR4): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR4_Pos); + break; + + case ((uint32_t)TIMR5): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR5_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: TIMR_INTClr() +* ¹¦ÄÜ˵Ã÷: Çå³ýÖжϱêÖ¾ +* Êä Èë: TIMR_TypeDef * TIMRx Ö¸¶¨Òª±»ÉèÖõĶ¨Ê±Æ÷£¬¿ÉÈ¡Öµ°üÀ¨TIMR0¡¢TIMR1¡¢TIMR2¡¢TIMR3¡¢TIMR4¡¢TIMR5 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void TIMR_INTClr(TIMR_TypeDef *TIMRx) +{ + switch ((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR0_Pos); + break; + + case ((uint32_t)TIMR1): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR1_Pos); + break; + + case ((uint32_t)TIMR2): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR2_Pos); + break; + + case ((uint32_t)TIMR3): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR3_Pos); + break; + + case ((uint32_t)TIMR4): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR4_Pos); + break; + + case ((uint32_t)TIMR5): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR5_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: TIMR_INTStat() +* ¹¦ÄÜ˵Ã÷: »ñÈ¡ÖжÏ״̬ +* Êä Èë: TIMR_TypeDef * TIMRx Ö¸¶¨Òª±»ÉèÖõĶ¨Ê±Æ÷£¬¿ÉÈ¡Öµ°üÀ¨TIMR0¡¢TIMR1¡¢TIMR2¡¢TIMR3¡¢TIMR4¡¢TIMR5 +* Êä ³ö: uint32_t 0 TIMRxδ²úÉúÖÐ¶Ï 1 TIMRx²úÉúÁËÖÐ¶Ï +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx) +{ + switch ((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + return (TIMRG->IF & TIMRG_IF_TIMR0_Msk) ? 1 : 0; + + case ((uint32_t)TIMR1): + return (TIMRG->IF & TIMRG_IF_TIMR1_Msk) ? 1 : 0; + + case ((uint32_t)TIMR2): + return (TIMRG->IF & TIMRG_IF_TIMR2_Msk) ? 1 : 0; + + case ((uint32_t)TIMR3): + return (TIMRG->IF & TIMRG_IF_TIMR3_Msk) ? 1 : 0; + + case ((uint32_t)TIMR4): + return (TIMRG->IF & TIMRG_IF_TIMR4_Msk) ? 1 : 0; + + case ((uint32_t)TIMR5): + return (TIMRG->IF & TIMRG_IF_TIMR5_Msk) ? 1 : 0; + } + + return 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h new file mode 100644 index 0000000000..f92c0eaa73 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h @@ -0,0 +1,23 @@ +#ifndef __SWM320_TIMR_H__ +#define __SWM320_TIMR_H__ + +#define TIMR_MODE_TIMER 0 +#define TIMR_MODE_COUNTER 1 + +void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en); //¶¨Ê±Æ÷/¼ÆÊýÆ÷³õʼ»¯ +void TIMR_Start(TIMR_TypeDef *TIMRx); //Æô¶¯¶¨Ê±Æ÷£¬´Ó³õʼֵ¿ªÊ¼¼Æʱ/¼ÆÊý +void TIMR_Stop(TIMR_TypeDef *TIMRx); //Í£Ö¹¶¨Ê±Æ÷ +void TIMR_Halt(TIMR_TypeDef *TIMRx); //ÔÝÍ£¶¨Ê±Æ÷£¬¼ÆÊýÖµ±£³Ö²»±ä +void TIMR_Resume(TIMR_TypeDef *TIMRx); //»Ö¸´¶¨Ê±Æ÷£¬´ÓÔÝÍ£´¦¼ÌÐø¼ÆÊý + +void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period); //ÉèÖö¨Ê±/¼ÆÊýÖÜÆÚ +uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx); //»ñÈ¡¶¨Ê±/¼ÆÊýÖÜÆÚ +uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx); //»ñÈ¡µ±Ç°¼ÆÊýÖµ + +void TIMR_INTEn(TIMR_TypeDef *TIMRx); //ʹÄÜÖÐ¶Ï +void TIMR_INTDis(TIMR_TypeDef *TIMRx); //½ûÄÜÖÐ¶Ï +void TIMR_INTClr(TIMR_TypeDef *TIMRx); //Çå³ýÖжϱêÖ¾ +uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx); //»ñÈ¡ÖжÏ״̬ + + +#endif //__SWM320_TIMR_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c new file mode 100644 index 0000000000..46242efa01 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c @@ -0,0 +1,543 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_uart.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄUART´®¿Ú¹¦ÄÜÇý¶¯¿â +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: ûÓбàдLIN¹¦ÄÜÏà¹ØµÄº¯Êý +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_uart.h" + + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_Init() +* ¹¦ÄÜ˵Ã÷: UART´®¿Ú³õʼ»¯ +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* UART_InitStructure * initStruct °üº¬UART´®¿ÚÏà¹ØÉ趨ֵµÄ½á¹¹Ìå +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct) +{ + switch ((uint32_t)UARTx) + { + case ((uint32_t)UART0): + SYS->CLKEN |= (0x01 << SYS_CLKEN_UART0_Pos); + break; + + case ((uint32_t)UART1): + SYS->CLKEN |= (0x01 << SYS_CLKEN_UART1_Pos); + break; + + case ((uint32_t)UART2): + SYS->CLKEN |= (0x01 << SYS_CLKEN_UART2_Pos); + break; + + case ((uint32_t)UART3): + SYS->CLKEN |= (0x01 << SYS_CLKEN_UART3_Pos); + break; + } + + UART_Close(UARTx); //һЩ¹Ø¼ü¼Ä´æÆ÷Ö»ÄÜÔÚ´®¿Ú¹Ø±ÕʱÉèÖà + + UARTx->CTRL |= (0x01 << UART_CTRL_BAUDEN_Pos); + UARTx->BAUD &= ~UART_BAUD_BAUD_Msk; + UARTx->BAUD |= ((SystemCoreClock / 16 / initStruct->Baudrate - 1) << UART_BAUD_BAUD_Pos); + + UARTx->CTRL &= ~(UART_CTRL_DATA9b_Msk | UART_CTRL_PARITY_Msk | UART_CTRL_STOP2b_Msk); + UARTx->CTRL |= (initStruct->DataBits << UART_CTRL_DATA9b_Pos) | + (initStruct->Parity << UART_CTRL_PARITY_Pos) | + (initStruct->StopBits << UART_CTRL_STOP2b_Pos); + + UARTx->FIFO &= ~(UART_FIFO_RXTHR_Msk | UART_FIFO_TXTHR_Msk); + UARTx->FIFO |= (initStruct->RXThreshold << UART_FIFO_RXTHR_Pos) | + (initStruct->TXThreshold << UART_FIFO_TXTHR_Pos); + + UARTx->CTRL &= ~UART_CTRL_TOTIME_Msk; + UARTx->CTRL |= (initStruct->TimeoutTime << UART_CTRL_TOTIME_Pos); + + UARTx->CTRL &= ~(UART_CTRL_RXIE_Msk | UART_CTRL_TXIE_Msk | UART_CTRL_TOIE_Msk); + UARTx->CTRL |= (initStruct->RXThresholdIEn << UART_CTRL_RXIE_Pos) | + (initStruct->TXThresholdIEn << UART_CTRL_TXIE_Pos) | + (initStruct->TimeoutIEn << UART_CTRL_TOIE_Pos); + + switch ((uint32_t)UARTx) + { + case ((uint32_t)UART0): + if (initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn) + { + NVIC_EnableIRQ(UART0_IRQn); + } + else + { + NVIC_DisableIRQ(UART0_IRQn); + } + break; + + case ((uint32_t)UART1): + if (initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn) + { + NVIC_EnableIRQ(UART1_IRQn); + } + else + { + NVIC_DisableIRQ(UART1_IRQn); + } + break; + + case ((uint32_t)UART2): + if (initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn) + { + NVIC_EnableIRQ(UART2_IRQn); + } + else + { + NVIC_DisableIRQ(UART2_IRQn); + } + break; + + case ((uint32_t)UART3): + if (initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn) + { + NVIC_EnableIRQ(UART3_IRQn); + } + else + { + NVIC_DisableIRQ(UART3_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_Open() +* ¹¦ÄÜ˵Ã÷: UART´®¿Ú´ò¿ª +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_Open(UART_TypeDef *UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_Close() +* ¹¦ÄÜ˵Ã÷: UART´®¿Ú¹Ø±Õ +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_Close(UART_TypeDef *UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_WriteByte() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍÒ»¸ö×Ö½ÚÊý¾Ý +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬¿ÉÈ¡Öµ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3¡¢UART4 +* uint8_t data Òª·¢Ë͵Ä×Ö½Ú +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_WriteByte(UART_TypeDef *UARTx, uint8_t data) +{ + UARTx->DATA = data; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_ReadByte() +* ¹¦ÄÜ˵Ã÷: ¶ÁÈ¡Ò»¸ö×Ö½ÚÊý¾Ý£¬²¢Ö¸³öÊý¾ÝÊÇ·ñValid +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬¿ÉÈ¡Öµ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3¡¢UART4 +* uint32_t * data ½ÓÊÕµ½µÄÊý¾Ý +* Êä ³ö: uint32_t 0 ÎÞ´íÎó UART_ERR_PARITY ÆæżУÑé´íÎó +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data) +{ + uint32_t reg = UARTx->DATA; + + *data = (reg & UART_DATA_DATA_Msk); + + if (reg & UART_DATA_PAERR_Msk) return UART_ERR_PARITY; + + return 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_IsTXBusy() +* ¹¦ÄÜ˵Ã÷: UARTÊÇ·ñÕýÔÚ·¢ËÍÊý¾Ý +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: uint32_t 1 UARTÕýÔÚ·¢ËÍÊý¾Ý 0 Êý¾ÝÒÑ·¢Íê +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t UART_IsTXBusy(UART_TypeDef *UARTx) +{ + return (UARTx->CTRL & UART_CTRL_TXIDLE_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_IsRXFIFOEmpty() +* ¹¦ÄÜ˵Ã÷: ½ÓÊÕFIFOÊÇ·ñΪ¿Õ£¬Èç¹û²»¿ÕÔò˵Ã÷ÆäÖÐÓÐÊý¾Ý¿ÉÒÔ¶ÁÈ¡ +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: uint32_t 1 ½ÓÊÕFIFO¿Õ 0 ½ÓÊÕFIFO·Ç¿Õ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx) +{ + return (UARTx->CTRL & UART_CTRL_RXNE_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_IsTXFIFOFull() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFOÊÇ·ñΪÂú£¬Èç¹û²»ÂúÔò¿ÉÒÔ¼ÌÐøÏòÆäÖÐдÈëÊý¾Ý +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: uint32_t 1 ·¢ËÍFIFOÂú 0 ·¢ËÍFIFO²»Âú +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx) +{ + return (UARTx->CTRL & UART_CTRL_TXFF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_SetBaudrate() +* ¹¦ÄÜ˵Ã÷: ÉèÖò¨ÌØÂÊ +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* uint32_t baudrate ÒªÉèÖõIJ¨ÌØÂÊ +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ²»ÒªÔÚ´®¿Ú¹¤×÷ʱ¸ü¸Ä²¨ÌØÂÊ£¬Ê¹Óô˺¯ÊýÇ°ÇëÏȵ÷ÓÃUART_Close()¹Ø±Õ´®¿Ú +******************************************************************************************************************************************/ +void UART_SetBaudrate(UART_TypeDef *UARTx, uint32_t baudrate) +{ + UARTx->BAUD &= ~UART_BAUD_BAUD_Msk; + UARTx->BAUD |= ((SystemCoreClock / 16 / baudrate) << UART_BAUD_BAUD_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_GetBaudrate() +* ¹¦ÄÜ˵Ã÷: ²éѯ²¨ÌØÂÊ +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: uint32_t µ±Ç°²¨ÌØÂÊ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t UART_GetBaudrate(UART_TypeDef *UARTx) +{ + return (UARTx->BAUD & UART_BAUD_BAUD_Msk); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_CTSConfig() +* ¹¦ÄÜ˵Ã÷: UART CTSÁ÷¿ØÅäÖà +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* uint32_t enable 1 ʹÄÜCTSÁ÷¿Ø 0 ½ûÖ¹CTSÁ÷¿Ø +* uint32_t polarity 0 CTSÊäÈëΪµÍ±íʾ¿ÉÒÔ·¢ËÍÊý¾Ý 1 CTSÊäÈëΪ¸ß±íʾ¿ÉÒÔ·¢ËÍÊý¾Ý +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_CTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity) +{ + UARTx->CTSCR &= ~(UART_CTSCR_EN_Msk | UART_CTSCR_POL_Msk); + UARTx->CTSCR |= (enable << UART_CTSCR_EN_Pos) | + (polarity << UART_CTSCR_POL_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_CTSLineState() +* ¹¦ÄÜ˵Ã÷: UART CTSÏßµ±Ç°×´Ì¬ +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: uint32_t 0 CTSÏßµ±Ç°ÎªµÍµçƽ 1 CTSÏßµ±Ç°Îª¸ßµçƽ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t UART_CTSLineState(UART_TypeDef *UARTx) +{ + return (UARTx->CTSCR & UART_CTSCR_STAT_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_RTSConfig() +* ¹¦ÄÜ˵Ã÷: UART RTSÁ÷¿ØÅäÖà +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* uint32_t enable 1 ʹÄÜRTSÁ÷¿Ø 0 ½ûÖ¹RTSÁ÷¿Ø +* uint32_t polarity 0 RTSÊä³öµÍ±íʾ¿ÉÒÔ½ÓÊÕÊý¾Ý 1 RTSÊä³ö¸ß±íʾ¿ÉÒÔ½ÓÊÕÊý¾Ý +* uint32_t threshold RTSÁ÷¿ØµÄ´¥·¢ãÐÖµ£¬¿ÉÈ¡ÖµUART_RTS_1BYTE¡¢UART_RTS_2BYTE¡¢UART_RTS_4BYTE¡¢UART_RTS_6BYTE +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_RTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold) +{ + UARTx->RTSCR &= ~(UART_RTSCR_EN_Msk | UART_RTSCR_POL_Msk | UART_RTSCR_THR_Msk); + UARTx->RTSCR |= (enable << UART_RTSCR_EN_Pos) | + (polarity << UART_RTSCR_POL_Pos) | + (threshold << UART_RTSCR_THR_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_RTSLineState() +* ¹¦ÄÜ˵Ã÷: UART RTSÏßµ±Ç°×´Ì¬ +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: uint32_t 0 RTSÏßµ±Ç°ÎªµÍµçƽ 1 RTSÏßµ±Ç°Îª¸ßµçƽ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t UART_RTSLineState(UART_TypeDef *UARTx) +{ + return (UARTx->RTSCR & UART_RTSCR_STAT_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_LINConfig() +* ¹¦ÄÜ˵Ã÷: UART LIN¹¦ÄÜÅäÖà +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* uint32_t detectedIEn ¼ì²âµ½BreakÖжÏʹÄÜ +* uint32_t generatedIEn Break·¢ËÍÍê³ÉÖжÏʹÄÜ +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_LINConfig(UART_TypeDef *UARTx, uint32_t detectedIEn, uint32_t generatedIEn) +{ + UARTx->LINCR &= ~(UART_LINCR_BRKDETIE_Msk | UART_LINCR_GENBRKIE_Msk); + UARTx->LINCR |= (detectedIEn << UART_LINCR_BRKDETIE_Pos) | + (generatedIEn << UART_LINCR_GENBRKIE_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_LINGenerate() +* ¹¦ÄÜ˵Ã÷: UART LIN²úÉú/·¢ËÍBreak +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_LINGenerate(UART_TypeDef *UARTx) +{ + UARTx->LINCR |= (1 << UART_LINCR_GENBRK_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_LINIsDetected() +* ¹¦ÄÜ˵Ã÷: UART LINÊÇ·ñ¼ì²âµ½Break +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: uint32_t 1 ¼ì²âµ½LIN Break 0 δ¼ì²âµ½LIN Break +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t UART_LINIsDetected(UART_TypeDef *UARTx) +{ + return (UARTx->LINCR & UART_LINCR_BRKDETIE_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_LINIsGenerated() +* ¹¦ÄÜ˵Ã÷: UART LIN BreakÊÇ·ñ·¢ËÍÍê³É +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: uint32_t 1 LIN Break ·¢ËÍÍê³É 0 LIN Break·¢ËÍδÍê³É +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t UART_LINIsGenerated(UART_TypeDef *UARTx) +{ + return (UARTx->LINCR & UART_LINCR_GENBRKIF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_ABRStart() +* ¹¦ÄÜ˵Ã÷: UART ×Ô¶¯²¨ÌØÂʼì²â¿ªÊ¼ +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* uint32_t detectChar ÓÃÓÚ×Ô¶¯¼ì²â¡¢¼ÆË㲨ÌØÂʵļì²â×Ö·û +* 8λÊý¾Ýʱ¿ÉÈ¡Öµ£º0xFF¡¢0xFE¡¢0xF8¡¢0x80£¬·Ö±ð±íʾ·¢ËÍ·½±ØÐë·¢ËÍ0xFF¡¢0xFE¡¢0xF8¡¢0x80 +* 9λÊý¾Ýʱ¿ÉÈ¡Öµ£º0x1FF¡¢0x1FE¡¢0x1F8¡¢0x180£¬·Ö±ð±íʾ·¢ËÍ·½±ØÐë·¢ËÍ0x1FF¡¢0x1FE¡¢0x1F8¡¢0x180 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ×Ô¶¯²¨ÌØÂʼì²âʱ²»ÄÜ¿ªÆôÆæżУÑé +******************************************************************************************************************************************/ +void UART_ABRStart(UART_TypeDef *UARTx, uint32_t detectChar) +{ + uint32_t bits; + + if ((detectChar == 0xFF) || (detectChar == 0x1FF)) bits = 0; + else if ((detectChar == 0xFE) || (detectChar == 0x1FE)) bits = 1; + else if ((detectChar == 0xF8) || (detectChar == 0x1F8)) bits = 2; + else if ((detectChar == 0x80) || (detectChar == 0x180)) bits = 3; + else while (1); + + UARTx->BAUD &= ~(UART_BAUD_ABREN_Msk | UART_BAUD_ABRBIT_Msk); + UARTx->BAUD |= (1 << UART_BAUD_ABREN_Pos) | + (bits << UART_BAUD_ABRBIT_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_ABRIsDone() +* ¹¦ÄÜ˵Ã÷: UART ×Ô¶¯²¨ÌØÂÊÊÇ·ñÍê³É +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: uint32_t 0 δÍê³É UART_ABR_RES_OK ÒÑÍê³É£¬Çҳɹ¦ UART_ABR_RES_ERR ÒÑÍê³É£¬µ«Ê§°Ü¡¢³ö´í +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t UART_ABRIsDone(UART_TypeDef *UARTx) +{ + if (UARTx->BAUD & UART_BAUD_ABREN_Msk) + { + return 0; + } + else if (UARTx->BAUD & UART_BAUD_ABRERR_Msk) + { + return UART_ABR_RES_ERR; + } + else + { + return UART_ABR_RES_OK; + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_INTRXThresholdEn() +* ¹¦ÄÜ˵Ã÷: µ±RX FIFOÖÐÊý¾Ý¸öÊý >= RXThresholdʱ ´¥·¢ÖÐ¶Ï +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_INTRXThresholdEn(UART_TypeDef *UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_RXIE_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_INTRXThresholdDis() +* ¹¦ÄÜ˵Ã÷: µ±RX FIFOÖÐÊý¾Ý¸öÊý >= RXThresholdʱ ²»´¥·¢ÖÐ¶Ï +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_INTRXThresholdDis(UART_TypeDef *UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_RXIE_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_INTRXThresholdStat() +* ¹¦ÄÜ˵Ã÷: ÊÇ·ñRX FIFOÖÐÊý¾Ý¸öÊý >= RXThreshold +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: uint32_t 1 RX FIFOÖÐÊý¾Ý¸öÊý >= RXThreshold 0 RX FIFOÖÐÊý¾Ý¸öÊý < RXThreshold +* ×¢ÒâÊÂÏî: RXIF = RXTHRF & RXIE +******************************************************************************************************************************************/ +uint32_t UART_INTRXThresholdStat(UART_TypeDef *UARTx) +{ + return (UARTx->BAUD & UART_BAUD_RXIF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_INTTXThresholdEn() +* ¹¦ÄÜ˵Ã÷: µ±TX FIFOÖÐÊý¾Ý¸öÊý <= TXThresholdʱ ´¥·¢ÖÐ¶Ï +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_INTTXThresholdEn(UART_TypeDef *UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_TXIE_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_INTTXThresholdDis() +* ¹¦ÄÜ˵Ã÷: µ±TX FIFOÖÐÊý¾Ý¸öÊý <= TXThresholdʱ ²»´¥·¢ÖÐ¶Ï +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_INTTXThresholdDis(UART_TypeDef *UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_TXIE_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_INTTXThresholdStat() +* ¹¦ÄÜ˵Ã÷: ÊÇ·ñTX FIFOÖÐÊý¾Ý¸öÊý <= TXThreshold +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: uint32_t 1 TX FIFOÖÐÊý¾Ý¸öÊý <= TXThreshold 0 TX FIFOÖÐÊý¾Ý¸öÊý > TXThreshold +* ×¢ÒâÊÂÏî: TXIF = TXTHRF & TXIE +******************************************************************************************************************************************/ +uint32_t UART_INTTXThresholdStat(UART_TypeDef *UARTx) +{ + return (UARTx->BAUD & UART_BAUD_TXIF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_INTTimeoutEn() +* ¹¦ÄÜ˵Ã÷: ½ÓÊÕ·¢Éú³¬Ê±Ê± ´¥·¢ÖÐ¶Ï +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_INTTimeoutEn(UART_TypeDef *UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_TOIE_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_INTTimeoutDis() +* ¹¦ÄÜ˵Ã÷: ½ÓÊÕ·¢Éú³¬Ê±Ê± ²»´¥·¢ÖÐ¶Ï +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_INTTimeoutDis(UART_TypeDef *UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_TOIE_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_INTTimeoutStat() +* ¹¦ÄÜ˵Ã÷: ÊÇ·ñ·¢ÉúÁ˽ÓÊÕ³¬Ê±£¬¼´³¬¹ý TimeoutTime/(Baudrate/10) ÃëûÓÐÔÚRXÏßÉϽÓÊÕµ½Êý¾Ýʱ´¥·¢ÖÐ¶Ï +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: uint32_t 1 ·¢ÉúÁ˽ÓÊÕ³¬Ê± 0 δ·¢Éú½ÓÊÕ³¬Ê± +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t UART_INTTimeoutStat(UART_TypeDef *UARTx) +{ + return (UARTx->BAUD & UART_BAUD_TOIF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_INTTXDoneEn() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFO¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжÏʹÄÜ +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_INTTXDoneEn(UART_TypeDef *UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_TXDOIE_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_INTTXDoneDis() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFO¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжϽûÖ¹ +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void UART_INTTXDoneDis(UART_TypeDef *UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_TXDOIE_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: UART_INTTXDoneStat() +* ¹¦ÄÜ˵Ã÷: ·¢ËÍFIFO¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжÏ״̬ +* Êä Èë: UART_TypeDef * UARTx Ö¸¶¨Òª±»ÉèÖõÄUART´®¿Ú£¬ÓÐЧֵ°üÀ¨UART0¡¢UART1¡¢UART2¡¢UART3 +* Êä ³ö: uint32_t 1 ·¢ËÍFIFO¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿Õ 0 ·¢ËÍFIFO»ò·¢ËÍÒÆλ¼Ä´æÆ÷δ¿Õ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t UART_INTTXDoneStat(UART_TypeDef *UARTx) +{ + return (UARTx->BAUD & UART_BAUD_TXDOIF_Msk) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h new file mode 100644 index 0000000000..1bc2ad3edc --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h @@ -0,0 +1,95 @@ +#ifndef __SWM320_UART_H__ +#define __SWM320_UART_H__ + +typedef struct +{ + uint32_t Baudrate; + + uint8_t DataBits; //Êý¾ÝλλÊý£¬¿ÉÈ¡ÖµUART_DATA_8BIT¡¢UART_DATA_9BIT + + uint8_t Parity; //ÆæżУÑé룬¿ÉÈ¡ÖµUART_PARITY_NONE¡¢UART_PARITY_ODD¡¢UART_PARITY_EVEN¡¢UART_PARITY_ONE¡¢UART_PARITY_ZERO + + uint8_t StopBits; //ֹͣλλÊý£¬¿ÉÈ¡ÖµUART_STOP_1BIT¡¢UART_STOP_2BIT + + uint8_t RXThreshold; //È¡Öµ0--7 + uint8_t RXThresholdIEn; //µ±RX FIFOÖÐÊý¾Ý¸öÊý >= RXThresholdʱ´¥·¢ÖÐ¶Ï + + uint8_t TXThreshold; //È¡Öµ0--7 + uint8_t TXThresholdIEn; //µ±TX FIFOÖÐÊý¾Ý¸öÊý <= TXThresholdʱ´¥·¢ÖÐ¶Ï + + uint8_t TimeoutTime; //³¬Ê±Ê±³¤ = TimeoutTime/(Baudrate/10) Ãë + uint8_t TimeoutIEn; //³¬Ê±Öжϣ¬³¬¹ý TimeoutTime/(Baudrate/10) ÃëûÓÐÔÚRXÏßÉϽÓÊÕµ½Êý¾Ýʱ´¥·¢ÖÐ¶Ï +} UART_InitStructure; + + +#define UART_DATA_8BIT 0 +#define UART_DATA_9BIT 1 + +#define UART_PARITY_NONE 0 +#define UART_PARITY_ODD 1 +#define UART_PARITY_EVEN 3 +#define UART_PARITY_ONE 5 +#define UART_PARITY_ZERO 7 + +#define UART_STOP_1BIT 0 +#define UART_STOP_2BIT 1 + +#define UART_RTS_1BYTE 0 +#define UART_RTS_2BYTE 1 +#define UART_RTS_4BYTE 2 +#define UART_RTS_6BYTE 3 + +#define UART_ABR_RES_OK 1 +#define UART_ABR_RES_ERR 2 + +#define UART_ERR_FRAME 1 +#define UART_ERR_PARITY 2 +#define UART_ERR_NOISE 3 + + +void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct); //UART´®¿Ú³õʼ»¯ +void UART_Open(UART_TypeDef *UARTx); +void UART_Close(UART_TypeDef *UARTx); + +void UART_WriteByte(UART_TypeDef *UARTx, uint8_t data); //·¢ËÍÒ»¸ö×Ö½ÚÊý¾Ý +uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data); //¶ÁÈ¡Ò»¸ö×Ö½ÚÊý¾Ý£¬²¢Ö¸³öÊý¾ÝÊÇ·ñValid + +uint32_t UART_IsTXBusy(UART_TypeDef *UARTx); +uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx); //½ÓÊÕFIFOÊÇ·ñ¿Õ£¬Èç¹û²»¿ÕÔò¿ÉÒÔ¼ÌÐøUART_ReadByte() +uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx); //·¢ËÍFIFOÊÇ·ñÂú£¬Èç¹û²»ÂúÔò¿ÉÒÔ¼ÌÐøUART_WriteByte() + + +void UART_SetBaudrate(UART_TypeDef *UARTx, uint32_t baudrate); //ÉèÖò¨ÌØÂÊ +uint32_t UART_GetBaudrate(UART_TypeDef *UARTx); //»ñÈ¡µ±Ç°Ê¹ÓõIJ¨ÌØÂÊ + +void UART_CTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity); +uint32_t UART_CTSLineState(UART_TypeDef *UARTx); + +void UART_RTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold); +uint32_t UART_RTSLineState(UART_TypeDef *UARTx); + +void UART_LINConfig(UART_TypeDef *UARTx, uint32_t detectedIEn, uint32_t generatedIEn); +void UART_LINGenerate(UART_TypeDef *UARTx); +uint32_t UART_LINIsDetected(UART_TypeDef *UARTx); +uint32_t UART_LINIsGenerated(UART_TypeDef *UARTx); + +void UART_ABRStart(UART_TypeDef *UARTx, uint32_t detectChar); +uint32_t UART_ABRIsDone(UART_TypeDef *UARTx); + + +void UART_INTRXThresholdEn(UART_TypeDef *UARTx); +void UART_INTRXThresholdDis(UART_TypeDef *UARTx); +uint32_t UART_INTRXThresholdStat(UART_TypeDef *UARTx); +void UART_INTTXThresholdEn(UART_TypeDef *UARTx); +void UART_INTTXThresholdDis(UART_TypeDef *UARTx); +uint32_t UART_INTTXThresholdStat(UART_TypeDef *UARTx); +void UART_INTTimeoutEn(UART_TypeDef *UARTx); +void UART_INTTimeoutDis(UART_TypeDef *UARTx); +uint32_t UART_INTTimeoutStat(UART_TypeDef *UARTx); + +void UART_INTTXDoneEn(UART_TypeDef *UARTx); +void UART_INTTXDoneDis(UART_TypeDef *UARTx); +uint32_t UART_INTTXDoneStat(UART_TypeDef *UARTx); + + +#endif //__SWM320_UART_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c new file mode 100644 index 0000000000..04faf947d7 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c @@ -0,0 +1,126 @@ +/****************************************************************************************************************************************** +* ÎļþÃû³Æ: SWM320_wdt.c +* ¹¦ÄÜ˵Ã÷: SWM320µ¥Æ¬»úµÄWDT¿´ÃŹ·¹¦ÄÜÇý¶¯¿â +* ¼¼ÊõÖ§³Ö: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ×¢ÒâÊÂÏî: +* °æ±¾ÈÕÆÚ: V1.1.0 2017Äê10ÔÂ25ÈÕ +* Éý¼¶¼Ç¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_wdt.h" + + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: WDT_Init() +* ¹¦ÄÜ˵Ã÷: WDT¿´ÃŹ·³õʼ»¯ +* Êä Èë: WDT_TypeDef * WDTx Ö¸¶¨Òª±»ÉèÖõĿ´ÃŹ·£¬ÓÐЧֵ°üÀ¨WDT +* uint32_t peroid È¡Öµ0--4294967295£¬µ¥Î»Îªµ¥Æ¬»úϵͳʱÖÓÖÜÆÚ +* uint32_t mode WDT_MODE_RESET ³¬Ê±²úÉú¸´Î» WDT_MODE_INTERRUPT ³¬Ê±²úÉúÖÐ¶Ï +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ¸´Î»Ê¹ÄÜʱÖжϲ»Æð×÷Óã¬ÒòΪ¼ÆÊýÖÜÆÚ½áÊøʱоƬֱ½Ó¸´Î»ÁË£¬ÎÞ·¨ÏìÓ¦ÖÐ¶Ï +******************************************************************************************************************************************/ +void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode) +{ + SYS->CLKEN |= (0x01 << SYS_CLKEN_WDT_Pos); + + WDT_Stop(WDTx); //ÉèÖÃÇ°ÏÈ¹Ø±Õ + + WDTx->LOAD = peroid; + + if (mode == WDT_MODE_RESET) + { + NVIC_DisableIRQ(WDT_IRQn); + + WDTx->CR |= (1 << WDT_CR_RSTEN_Pos); + } + else //mode == WDT_MODE_INTERRUPT + { + NVIC_EnableIRQ(WDT_IRQn); + + WDTx->CR &= ~(1 << WDT_CR_RSTEN_Pos); + } +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: WDT_Start() +* ¹¦ÄÜ˵Ã÷: Æô¶¯Ö¸¶¨WDT£¬¿ªÊ¼µ¹¼Æʱ +* Êä Èë: WDT_TypeDef * WDTx Ö¸¶¨Òª±»ÉèÖõĿ´ÃŹ·£¬ÓÐЧֵ°üÀ¨WDT +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void WDT_Start(WDT_TypeDef *WDTx) +{ + WDTx->CR |= (0x01 << WDT_CR_EN_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: WDT_Stop() +* ¹¦ÄÜ˵Ã÷: ¹Ø±ÕÖ¸¶¨WDT£¬Í£Ö¹µ¹¼Æʱ +* Êä Èë: WDT_TypeDef * WDTx Ö¸¶¨Òª±»ÉèÖõĿ´ÃŹ·£¬ÓÐЧֵ°üÀ¨WDT +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void WDT_Stop(WDT_TypeDef *WDTx) +{ + WDTx->CR &= ~(0x01 << WDT_CR_EN_Pos); +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: WDT_Feed() +* ¹¦ÄÜ˵Ã÷: ι¹·£¬ÖØдÓ×°ÔØÖµ¿ªÊ¼µ¹¼Æʱ +* Êä Èë: WDT_TypeDef * WDTx Ö¸¶¨Òª±»ÉèÖõĿ´ÃŹ·£¬ÓÐЧֵ°üÀ¨WDT +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void WDT_Feed(WDT_TypeDef *WDTx) +{ + WDTx->FEED = 0x55; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: WDT_GetValue() +* ¹¦ÄÜ˵Ã÷: »ñÈ¡Ö¸¶¨¿´ÃŹ·¶¨Ê±Æ÷µÄµ±Ç°µ¹¼Æʱֵ +* Êä Èë: WDT_TypeDef * WDTx Ö¸¶¨Òª±»ÉèÖõĿ´ÃŹ·£¬ÓÐЧֵ°üÀ¨WDT +* Êä ³ö: int32_t ¿´ÃŹ·µ±Ç°¼ÆÊýÖµ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +int32_t WDT_GetValue(WDT_TypeDef *WDTx) +{ + return WDTx->VALUE; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: WDT_INTClr() +* ¹¦ÄÜ˵Ã÷: ÖжϱêÖ¾Çå³ý +* Êä Èë: WDT_TypeDef * WDTx Ö¸¶¨Òª±»ÉèÖõĿ´ÃŹ·£¬ÓÐЧֵ°üÀ¨WDT +* Êä ³ö: ÎÞ +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +void WDT_INTClr(WDT_TypeDef *WDTx) +{ + WDTx->IF = 1; +} + +/****************************************************************************************************************************************** +* º¯ÊýÃû³Æ: WDT_INTStat() +* ¹¦ÄÜ˵Ã÷: ÖжÏ״̬²éѯ +* Êä Èë: WDT_TypeDef * WDTx Ö¸¶¨Òª±»ÉèÖõĿ´ÃŹ·£¬ÓÐЧֵ°üÀ¨WDT +* Êä ³ö: int32_t 1 ·¢ÉúÖжÏÒç³ö 0 δ·¢ÉúÖжÏÒç³ö +* ×¢ÒâÊÂÏî: ÎÞ +******************************************************************************************************************************************/ +uint32_t WDT_INTStat(WDT_TypeDef *WDTx) +{ + return WDTx->IF; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h new file mode 100644 index 0000000000..fd435c170e --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h @@ -0,0 +1,19 @@ +#ifndef __SWM320_WDT_H__ +#define __SWM320_WDT_H__ + +#define WDT_MODE_RESET 0 +#define WDT_MODE_INTERRUPT 1 + +void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode); //WDT¿´ÃŹ·³õʼ»¯ +void WDT_Start(WDT_TypeDef *WDTx); //Æô¶¯Ö¸¶¨WDT£¬¿ªÊ¼µ¹¼Æʱ +void WDT_Stop(WDT_TypeDef *WDTx); //¹Ø±ÕÖ¸¶¨WDT£¬Í£Ö¹µ¹¼Æʱ + +void WDT_Feed(WDT_TypeDef *WDTx); //ι¹·£¬ÖØдÓ×°ÔØÖµ¿ªÊ¼µ¹¼Æʱ + +int32_t WDT_GetValue(WDT_TypeDef *WDTx); //»ñÈ¡Ö¸¶¨¿´ÃŹ·¶¨Ê±Æ÷µÄµ±Ç°µ¹¼Æʱֵ + + +void WDT_INTClr(WDT_TypeDef *WDTx); //ÖжϱêÖ¾Çå³ý +uint32_t WDT_INTStat(WDT_TypeDef *WDTx); //ÖжÏ״̬²éѯ + +#endif //__SWM320_WDT_H__ diff --git a/bsp/swm320-lq100/README.md b/bsp/swm320-lq100/README.md new file mode 100644 index 0000000000..99d45c461c --- /dev/null +++ b/bsp/swm320-lq100/README.md @@ -0,0 +1,126 @@ +# SWXT-LQ100-32102 V1.1 æ¿çº§æ”¯æŒåŒ… 说明 + +标签： SYNWITã€Cortex-M4ã€SWM320VET7ã€å›½äº§MCU + +--- + +## 1. 简介 + +本文档为 SWXT-LQ100-32102 V1.1 çš„ BSP(æ¿çº§æ”¯æŒåŒ…) 说明。 + +通过阅读本文档，开å‘者å¯ä»¥å¿«é€Ÿåœ°ä¸Šæ‰‹è¯¥ BSP，将 RT-Thread è¿è¡Œåœ¨å¼€å‘æ¿ä¸Šã€‚ + +### 1.1 å¼€å‘æ¿ä»‹ç» + +SWXT-LQ100-32102 V1.1 å¼€å‘æ¿ç”±åŽèŠ¯å¾®ç‰¹æ供，å¯æ»¡è¶³åŸºç¡€æµ‹è¯•åŠé«˜ç«¯å¼€å‘需求。 + +å¼€å‘æ¿å¤–观如下图所示： + +SWXT_LQ100-32102 V1.1 + +![SWXT-LQ100-32102](figures/SWXT-LQ100-32102.jpg "SWXT-LQ100-32102 V1.1") + +SWXT-LQ100-32102 V1.1 å¼€å‘æ¿æ¿è½½èµ„æºå¦‚下： + +- MCU：SWM320VET7-50 ARM 32-bit Cortex-M4，主频 120MHz，512KB FLASH ，128KB SRAM，2.2～3.6V +- 常用外设 + - LED：1 个，D2 红绿è“三色LED + - 按键：3 个，K1ã€K2ã€K3 + - Nor Flash S29GL128M + - SRAM IS62WV51216BLL +- 常用接å£ï¼šUSB打å°æŽ¥å£ï¼ŒTFT LCD接å£ï¼ŒSDå¡æŽ¥å£ +- 调试接å£ï¼šSWD + +更多详细信æ¯è¯·å’¨è¯¢[åŽèŠ¯å¾®ç‰¹æŠ€æœ¯æ”¯æŒ][5] + +### 1.2 MCU 简介 + +SWM320VET7 是 SYNWIT å…¬å¸çš„一款é¢å‘工业控制ã€ç™½è‰²å®¶ç”µã€ç”µæœºé©±åŠ¨ç­‰é¢†åŸŸçš„芯片。包括如下硬件特性： + +| 硬件 | æè¿° | +| -- | -- | +|芯片型å·| SWM320VET7 | +|CPU| ARM Cortex-M4 | +|主频| 120MHz | +|片内SRAM| 128KB | +|片内Flash| 512KB | + +## 2. 编译说明 + +本 BSP 为开å‘者æä¾› MDK5 工程。下é¢ä»¥ MDK5 å¼€å‘环境为例，介ç»å¦‚何将系统è¿è¡Œèµ·æ¥ã€‚ + +åŒå‡» project.uvprojx 文件，打开 MDK5 工程，编译并下载程åºåˆ°å¼€å‘æ¿ã€‚ + +> 工程默认é…置使用 Jlink 仿真器下载程åºï¼Œåœ¨é€šè¿‡ Jlink 连接开å‘æ¿åˆ° PC 的基础上，点击下载按钮å³å¯ä¸‹è½½ç¨‹åºåˆ°å¼€å‘æ¿ + +推è熟悉 RT_Thread 的用户使用[env工具][1]，å¯ä»¥åœ¨console下进入到 `bsp/swm320-lq100` 目录中，è¿è¡Œä»¥ä¸‹å‘½ä»¤ï¼š + +`scons --target=mdk5` + +æ¥ç¼–译这个æ¿çº§æ”¯æŒåŒ…。如果编译正确无误，会产生rtthread.elfã€rtthread.bin文件。其中 rtthread.bin å¯ä»¥çƒ§å†™åˆ°è®¾å¤‡ä¸­è¿›è¡Œè¿è¡Œã€‚ + +## 3. 烧写åŠæ‰§è¡Œ + +### 3.1 硬件连接 + +- 使用 USB B-Type æ•°æ®çº¿è¿žæŽ¥å¼€å‘æ¿åˆ° PC（注æ„：需è¦ä¸‹è½½å®‰è£…串å£é©±åŠ¨æ”¯æŒCH340芯片，使用 MDK5 需è¦å®‰è£… SWM320 相关的 pack）。 + + > USB B-Type æ•°æ®çº¿ç”¨äºŽä¸²å£é€šè®¯ï¼ŒåŒæ—¶ä¾›ç”µ + +- 使用 Jlink 连接开å‘æ¿åˆ° PC ï¼ˆéœ€è¦ Jlink 驱动） + +连接好串å£ï¼Œä½¿ç”¨115200-N-8-1çš„é…置方å¼è¿žæŽ¥åˆ°è®¾å¤‡ä¸Šã€‚串å£å¼•è„šæ˜¯ï¼š`[PA2/PA3]` + +当使用 [env工具][1] 正确编译产生出rtthread.bin映åƒæ–‡ä»¶åŽï¼Œå¯ä»¥ä½¿ç”¨ ISP çš„æ–¹å¼æ¥çƒ§å†™åˆ°è®¾å¤‡ä¸­ã€‚ + +**建议使用 keil 软件直接下载**。ISP 下载较å¤æ‚。 + +### 3.2 è¿è¡Œç»“æžœ + +如果编译 & 烧写无误，当å¤ä½è®¾å¤‡åŽï¼Œä¼šåœ¨ä¸²å£ä¸Šçœ‹åˆ°æ¿å­ä¸Šçš„è“色LEDé—ªçƒã€‚串å£æ‰“å°RT-Threadçš„å¯åŠ¨logoä¿¡æ¯ï¼š + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Dec 11 2018 + 2006 - 2018 Copyright by rt-thread team +msh /> +``` + +## 4. 驱动支æŒæƒ…况åŠè®¡åˆ’ + +|**æ¿è½½å¤–设** |**支æŒæƒ…况**|**备注** | +| ----------------- | :----------: | ----------------------- | +| Nor Flash | æ”¯æŒ | | +| SDIO TF å¡ | æš‚ä¸æ”¯æŒ | | +| SRAM | æ”¯æŒ | | +| TFT-LCD | æš‚ä¸æ”¯æŒ | å³å°†æ”¯æŒ | +|**片上外设** |**支æŒæƒ…况** |**备注** | +| GPIO | æ”¯æŒ | PIN：1...100 | +| UART | æ”¯æŒ | UART0 / UART1 / UART2 / UART3 | +| SPI | æ”¯æŒ | SPI0 / SPI1 | +| I2C | æ”¯æŒ | I2C0 IO模拟 | +| ADC | æš‚ä¸æ”¯æŒ | å³å°†æ”¯æŒ | +| PWM | æ”¯æŒ | PWM0 / PWM1 /PWM2 /PWM3 其余两个个åŽç»­è¡¥å…… | +| IWG | æ”¯æŒ | | +| TIMER | æš‚ä¸æ”¯æŒ | | +| RTC | æ”¯æŒ | | +| CAN | æš‚ä¸æ”¯æŒ | | +|**æ¿å¤–外设** |**支æŒæƒ…况**|**备注** | +| Arduino æ‰©å±•æŽ¥å£ | æš‚ä¸æ”¯æŒ | | + +## 5. è”ç³»äººä¿¡æ¯ + +维护人： + +-[Zohar_Lee](https://github.com/zohar123) email: lizhh@synwit.cn + +## 6. å‚考 + +- 芯片[SWM320系列 æ•°æ®æ‰‹å†Œ][4] + + [1]: https://www.rt-thread.org/page/download.html + [2]: http://www.synwit.cn/Public/Uploads/2018-11-05/5bdfea74d5712.pdf + [3]: http://www.synwit.cn/Public/Uploads/2018-11-01/5bdab8ad2e5b9.pdf + [4]: http://www.synwit.cn/Public/Uploads/2018-11-05/5bdff49b396d1.pdf + [5]: http://www.synwit.cn/support.html diff --git a/bsp/swm320-lq100/SConscript b/bsp/swm320-lq100/SConscript new file mode 100644 index 0000000000..1b1c7506a4 --- /dev/null +++ b/bsp/swm320-lq100/SConscript @@ -0,0 +1,11 @@ +from building import * + +cwd = GetCurrentDir() + +objs = [] +list = os.listdir(cwd) +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +Return('objs') diff --git a/bsp/swm320-lq100/SConstruct b/bsp/swm320-lq100/SConstruct new file mode 100644 index 0000000000..c848dd104e --- /dev/null +++ b/bsp/swm320-lq100/SConstruct @@ -0,0 +1,39 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/swm320-lq100/applications/SConscript b/bsp/swm320-lq100/applications/SConscript new file mode 100644 index 0000000000..6452d39145 --- /dev/null +++ b/bsp/swm320-lq100/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/swm320-lq100/applications/main.c b/bsp/swm320-lq100/applications/main.c new file mode 100644 index 0000000000..61d90bd901 --- /dev/null +++ b/bsp/swm320-lq100/applications/main.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#include +#include + +#define LED4_PIN 100 + +int main(void) +{ + /* user app entry */ + rt_pin_mode(LED4_PIN, PIN_MODE_OUTPUT); + while (1) + { + rt_pin_write(LED4_PIN, !rt_pin_read(LED4_PIN)); + rt_thread_mdelay(1000); + } + + return 0; +} diff --git a/bsp/swm320-lq100/drivers/Kconfig b/bsp/swm320-lq100/drivers/Kconfig new file mode 100644 index 0000000000..4d0d68d8eb --- /dev/null +++ b/bsp/swm320-lq100/drivers/Kconfig @@ -0,0 +1,154 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menu "UART Drivers" + + config BSP_USING_UART0 + bool "Enable UART0 PA2/3(R/T)" + select RT_USING_SERIAL + default y + + config BSP_USING_UART1 + bool "Enable UART1 PC2/3(R/T)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART2 + bool "Enable UART2 PC4/5(R/T)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART3 + bool "Enable UART3 PC6/7(R/T)" + select RT_USING_SERIAL + default n + + endmenu + + menu "SPI Drivers" + + config BSP_USING_SPI0 + bool "Enable SPI0 BUS PC4/5/6(C/O/I)" + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI1 + bool "Enable SPI1 BUS PM5/C2/C3(C/O/I)" + select RT_USING_SPI + select RT_USING_PIN + default n + + endmenu + + menu "I2C Drivers" + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS" + select RT_USING_I2C + select RT_USING_PIN + select RT_USING_I2C_BITOPS + default n + + if BSP_USING_I2C + + config BSP_I2C_SCL + int "I2C SCL Pin index" + default 98 + + config BSP_I2C_SDA + int "I2C SDA Pin index" + default 99 + + config BSP_I2C_BUS_NAME + string "i2c bus name" + default "i2c0" + + endif + + endmenu + + menu "PWM module" + + config BSP_USING_PWM0 + bool "Using PWM0 PA4/10(A/B)" + select RT_USING_PWM + default n + + config BSP_USING_PWM1 + bool "Using PWM1 PA5/9(A/B)" + select RT_USING_PWM + default n + + config BSP_USING_PWM2 + bool "Using PWM2 PP0/2(A/B)" + select RT_USING_PWM + default n + + config BSP_USING_PWM3 + bool "Using PWM3 PP1/3(A/B)" + select RT_USING_PWM + default n + + endmenu + + menu "RTC module" + comment "RTC SET" + + config BSP_USING_RTC + bool "Using RTC" + select RT_USING_RTC + default n + + endmenu + + config BSP_USING_WDT + + bool "Enable Watch Dog" + select RT_USING_WDT + default n + + endmenu + + menu "Onboard Peripheral Drivers" + + menuconfig BSP_USING_EXT_SRAM + bool "Enable external sram" + select RT_USING_MEMHEAP + select RT_USING_MEMHEAP_AS_HEAP + default n + + if BSP_USING_EXT_SRAM + config BSP_EXT_SRAM_SIZE + hex "external sram size" + default 0x100000 + endif + + menuconfig BSP_USING_NOR_FLASH + bool "Enable mtd nor flash" + select RT_USING_MTD_NOR + select PKG_USING_FTL_SRC + default n + + if BSP_USING_NOR_FLASH + config BSP_NOR_FLASH_SIZE + hex "mtd nor flash size" + default 0x1000000 + config BSP_NOR_FLASH_SECTOR_SIZE + hex "mtd nor flsah sector" + default 0x10000 + endif + + endmenu + + menu "Offboard Peripheral Drivers" + + endmenu + +endmenu diff --git a/bsp/swm320-lq100/drivers/SConscript b/bsp/swm320-lq100/drivers/SConscript new file mode 100644 index 0000000000..cb44d26f74 --- /dev/null +++ b/bsp/swm320-lq100/drivers/SConscript @@ -0,0 +1,52 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +""") + +# add gpio driver code +if GetDepend(['BSP_USING_GPIO']): + src += ['drv_gpio.c'] + +# add serial driver code +if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'): + src += ['drv_uart.c'] + +# add spi driver code +if GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1'): + src += ['drv_spi.c'] + +# add i2c driver code +if GetDepend(['BSP_USING_I2C']): + src += ['drv_i2c.c'] + +# add sram driver code +if GetDepend(['BSP_USING_EXT_SRAM']): + src += ['drv_sram.c'] + +# add nor flash driver code +if GetDepend(['BSP_USING_NOR_FLASH']): + src += ['drv_nor_flash.c'] + +# add pwm driver code +if GetDepend('BSP_USING_PWM0') or GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3'): + src += ['drv_pwm.c'] + +# add rtc driver code +if GetDepend(['BSP_USING_RTC']): + src += ['drv_rtc.c'] + +# add hwtimer driver code +if GetDepend(['BSP_USING_WDT']): + src += ['drv_iwg.c'] + +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/swm320-lq100/drivers/board.c b/bsp/swm320-lq100/drivers/board.c new file mode 100644 index 0000000000..36e6a8f4ea --- /dev/null +++ b/bsp/swm320-lq100/drivers/board.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#include +#if defined(BSP_USING_EXT_SRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) + static struct rt_memheap system_heap; +#endif +static void bsp_clock_config(void) +{ + SystemInit(); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + SysTick->CTRL |= 0x00000004UL; +} +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#ifdef BSP_USING_EXT_SRAM + extern int rt_hw_sram_init(void); +#endif +void rt_hw_board_init() +{ + bsp_clock_config(); + +#ifdef BSP_USING_EXT_SRAM + rt_hw_sram_init(); +#endif +#if defined(BSP_USING_EXT_SRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) + rt_system_heap_init((void *)EXT_SRAM_BEGIN, (void *)EXT_SRAM_END); + rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE); +#elif defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} diff --git a/bsp/swm320-lq100/drivers/board.h b/bsp/swm320-lq100/drivers/board.h new file mode 100644 index 0000000000..0a525be35b --- /dev/null +++ b/bsp/swm320-lq100/drivers/board.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#ifndef BOARD_H__ +#define BOARD_H__ +#include +#include +#define SRAM_BASE 0x20000000 +#define SRAM_SIZE 0x20000 + +#ifdef BSP_USING_EXT_SRAM + #define EXT_SRAM_BASE SRAMM_BASE + #define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE + #define EXT_SRAM_BEGIN EXT_SRAM_BASE + #define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE) +#endif + +#define SRAM_END (SRAM_BASE + SRAM_SIZE * 1024UL) +#ifdef __CC_ARM + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section = "HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN ((void *)&__bss_end) +#endif +#define HEAP_END SRAM_END +#define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN) +extern void rt_hw_board_init(void); +#endif diff --git a/bsp/swm320-lq100/drivers/drv_gpio.c b/bsp/swm320-lq100/drivers/drv_gpio.c new file mode 100644 index 0000000000..b6f7244a94 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_gpio.c @@ -0,0 +1,599 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee ä¿®å¤bug + */ + +#include +#include +#include +#include +#include +#include +#include + +typedef void (*pin_callback_t)(void *args); +struct pin +{ + uint32_t package_index; + const char *name; + GPIO_TypeDef *port; + uint32_t group_index; + IRQn_Type irq; + rt_uint32_t irq_mode; + pin_callback_t callback; + void *callback_args; +}; +typedef struct pin pin_t; + +#define SWM32_PIN(a, b, c, d) \ + { \ + a, #b, GPIO##c, d, GPIO##c##_IRQn \ + } +#define GPIO0 ((GPIO_TypeDef *)(0)) +#define GPIO0_IRQn (GPIOA0_IRQn) + +const static pin_t swm32_pin_map[] = +{ + SWM32_PIN(0, None, 0, 0), + SWM32_PIN(1, ADC0 CH3, 0, 0), + SWM32_PIN(2, ADC0 REFP, 0, 0), + SWM32_PIN(3, Cap0, 0, 0), + SWM32_PIN(4, B12, B, 12), + SWM32_PIN(5, RTC VDD, 0, 0), + SWM32_PIN(6, N14, N, 14), + SWM32_PIN(7, N13, N, 13), + SWM32_PIN(8, N12, N, 12), + SWM32_PIN(9, N11, N, 11), + SWM32_PIN(10, VDD 3.3V, 0, 0), + SWM32_PIN(11, VSS 3.3V, 0, 0), + SWM32_PIN(12, Cap 2, 0, 0), + SWM32_PIN(13, N9, N, 9), + SWM32_PIN(14, N10, N, 10), + SWM32_PIN(15, Cap 1, 0, 0), + SWM32_PIN(16, AVSS, 0, 0), + SWM32_PIN(17, AVDD, 0, 0), + SWM32_PIN(18, N2, N, 2), + SWM32_PIN(19, N1, N, 1), + SWM32_PIN(20, N0, N, 0), + SWM32_PIN(21, C4, C, 4), + SWM32_PIN(22, C5, C, 5), + SWM32_PIN(23, C6, C, 6), + SWM32_PIN(24, C7, C, 7), + SWM32_PIN(25, C2, C, 2), + SWM32_PIN(26, C3, C, 3), + SWM32_PIN(27, XHIN, 0, 0), + SWM32_PIN(28, XHOUT, 0, 0), + SWM32_PIN(29, RESET, 0, 0), + SWM32_PIN(30, M2, M, 2), + SWM32_PIN(31, M3, M, 3), + SWM32_PIN(32, M4, M, 4), + SWM32_PIN(33, M5, M, 5), + SWM32_PIN(34, M6, M, 6), + SWM32_PIN(35, M7, M, 7), + SWM32_PIN(36, M8, M, 8), + SWM32_PIN(37, M9, M, 9), + SWM32_PIN(38, M10, M, 10), + SWM32_PIN(39, M11, M, 11), + SWM32_PIN(40, M12, M, 12), + SWM32_PIN(41, M13, M, 13), + SWM32_PIN(42, M14, M, 14), + SWM32_PIN(43, M15, M, 15), + SWM32_PIN(44, M16, M, 16), + SWM32_PIN(45, M17, M, 17), + SWM32_PIN(46, M18, M, 18), + SWM32_PIN(47, M19, M, 19), + SWM32_PIN(48, M20, M, 20), + SWM32_PIN(49, M21, M, 21), + SWM32_PIN(50, VDDIO, 0, 0), + SWM32_PIN(51, M1, M, 1), + SWM32_PIN(52, M0, M, 0), + SWM32_PIN(53, P0, P, 0), + SWM32_PIN(54, P1, P, 1), + SWM32_PIN(55, P2, P, 2), + SWM32_PIN(56, P3, P, 3), + SWM32_PIN(57, P4, P, 4), + SWM32_PIN(58, P5, P, 5), + SWM32_PIN(59, P6, P, 6), + SWM32_PIN(60, P7, P, 7), + SWM32_PIN(61, P8, P, 8), + SWM32_PIN(62, P9, P, 9), + SWM32_PIN(63, P10, P, 10), + SWM32_PIN(64, P11, P, 11), + SWM32_PIN(65, P12, P, 12), + SWM32_PIN(66, P13, P, 13), + SWM32_PIN(67, P14, P, 14), + SWM32_PIN(68, P15, P, 15), + SWM32_PIN(69, P16, P, 16), + SWM32_PIN(70, P17, P, 17), + SWM32_PIN(71, P18, P, 18), + SWM32_PIN(72, P19, P, 19), + SWM32_PIN(73, P20, P, 20), + SWM32_PIN(74, P21, P, 21), + SWM32_PIN(75, P22, P, 22), + SWM32_PIN(76, P23, P, 23), + SWM32_PIN(77, B0, B, 0), + SWM32_PIN(78, A0, A, 0), + SWM32_PIN(79, A1, A, 1), + SWM32_PIN(80, A2, A, 2), + SWM32_PIN(81, A3, A, 3), + SWM32_PIN(82, A4, A, 4), + SWM32_PIN(83, A5, A, 5), + SWM32_PIN(84, VSSIO, 0, 0), + SWM32_PIN(85, C1, C, 1), + SWM32_PIN(86, N19, N, 19), + SWM32_PIN(87, N18, N, 18), + SWM32_PIN(88, N17, N, 17), + SWM32_PIN(89, N16, N, 16), + SWM32_PIN(90, N15, N, 15), + SWM32_PIN(91, N8, N, 8), + SWM32_PIN(92, N7, N, 7), + SWM32_PIN(93, N6, N, 6), + SWM32_PIN(94, N5, N, 5), + SWM32_PIN(95, N4, N, 4), + SWM32_PIN(96, N3, N, 3), + SWM32_PIN(97, A9, A, 9), + SWM32_PIN(98, A10, A, 10), + SWM32_PIN(99, A11, A, 11), + SWM32_PIN(100, A12, A, 12) +}; +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +static pin_t *get_pin(uint8_t pin) +{ + pin_t *index; + if (pin < ITEM_NUM(swm32_pin_map)) + { + index = (pin_t *)&swm32_pin_map[pin]; + if (index->port == GPIO0) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + return index; +}; + +static void swm320_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + pin_t *index; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + if (value) + { + GPIO_SetBit(index->port, index->group_index); + } + else + { + GPIO_ClrBit(index->port, index->group_index); + } +} + +static int swm320_pin_read(rt_device_t dev, rt_base_t pin) +{ + pin_t *index; + index = get_pin(pin); + if (index == RT_NULL) + { + return PIN_LOW; + } + return GPIO_GetBit(index->port, index->group_index); +} + +static void swm320_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + pin_t *index; + int dir = 0; + int pull_up = 0; + int pull_down = 0; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + /* Configure GPIO_InitStructure */ + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + dir = 1; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + dir = 0; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + dir = 0; + pull_up = 1; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + dir = 0; + pull_down = 1; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + dir = 1; + pull_up = 1; + } + GPIO_Init(index->port, index->group_index, dir, pull_up, pull_down); +} + +static rt_err_t swm320_pin_attach_irq(struct rt_device *device, + rt_int32_t pin, + rt_uint32_t mode, + pin_callback_t cb, + void *args) +{ + pin_t *index; + rt_base_t level; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + level = rt_hw_interrupt_disable(); + index->callback = cb; + index->callback_args = args; + index->irq_mode = mode; + + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +static rt_err_t swm320_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + pin_t *index; + rt_base_t level; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + level = rt_hw_interrupt_disable(); + index->callback = 0; + index->callback_args = 0; + index->irq_mode = 0; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +static rt_err_t swm320_pin_irq_enable(struct rt_device *device, + rt_base_t pin, + rt_uint32_t enabled) +{ + pin_t *index; + rt_base_t level = 0; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + if (enabled == PIN_IRQ_ENABLE) + { + + switch (index->irq_mode) + { + case PIN_IRQ_MODE_RISING: + GPIO_Init(index->port, index->group_index, 0, 0, 1); + EXTI_Init(index->port, index->group_index, EXTI_RISE_EDGE); + break; + case PIN_IRQ_MODE_FALLING: + GPIO_Init(index->port, index->group_index, 0, 1, 0); + EXTI_Init(index->port, index->group_index, EXTI_FALL_EDGE); + break; + case PIN_IRQ_MODE_RISING_FALLING: + GPIO_Init(index->port, index->group_index, 0, 1, 1); + EXTI_Init(index->port, index->group_index, EXTI_BOTH_EDGE); + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + GPIO_Init(index->port, index->group_index, 0, 0, 1); + EXTI_Init(index->port, index->group_index, EXTI_HIGH_LEVEL); + break; + case PIN_IRQ_MODE_LOW_LEVEL: + GPIO_Init(index->port, index->group_index, 0, 1, 0); + EXTI_Init(index->port, index->group_index, EXTI_LOW_LEVEL); + break; + default: + rt_hw_interrupt_enable(level); + return RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + NVIC_EnableIRQ(index->irq); + EXTI_Open(index->port, index->group_index); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + NVIC_DisableIRQ(index->irq); + EXTI_Close(index->port, index->group_index); + } + else + { + return RT_ENOSYS; + } + return RT_EOK; +} + +const static struct rt_pin_ops swm320_pin_ops = +{ + swm320_pin_mode, + swm320_pin_write, + swm320_pin_read, + swm320_pin_attach_irq, + swm320_pin_detach_irq, + swm320_pin_irq_enable +}; + +int rt_hw_pin_init(void) +{ + int result; + result = rt_device_pin_register("pin", &swm320_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +void GPIOA_Handler(void) +{ + static int gpio[24]; + int index = 0; + static int init = 0; + pin_t *pin; + /* enter interrupt */ + rt_interrupt_enter(); + if (init == 0) + { + init = 1; + for (pin = (pin_t *)&swm32_pin_map[1]; + pin->package_index < ITEM_NUM(swm32_pin_map); + pin++) + { + if (pin->port == GPIOA) + { + gpio[index] = pin->package_index; + index++; + RT_ASSERT(index <= 24) + } + } + } + for (index = 0; index < 24; index++) + { + pin = get_pin(gpio[index]); + if (index != RT_NULL) + { + if (EXTI_State(pin->port, pin->group_index)) + { + EXTI_Clear(pin->port, pin->group_index); + if (pin->callback) + { + pin->callback(pin->callback_args); + } + } + } + } + /* leave interrupt */ + rt_interrupt_leave(); +} + +void GPIOB_Handler(void) +{ + static int gpio[24]; + int index = 0; + static int init = 0; + pin_t *pin; + /* enter interrupt */ + rt_interrupt_enter(); + if (init == 0) + { + init = 1; + for (pin = (pin_t *)&swm32_pin_map[1]; + pin->package_index < ITEM_NUM(swm32_pin_map); + pin++) + { + if (pin->port == GPIOB) + { + gpio[index] = pin->package_index; + index++; + RT_ASSERT(index <= 24) + } + } + } + for (index = 0; index < 24; index++) + { + pin = get_pin(gpio[index]); + if (index != RT_NULL) + { + if (EXTI_State(pin->port, pin->group_index)) + { + EXTI_Clear(pin->port, pin->group_index); + if (pin->callback) + { + pin->callback(pin->callback_args); + } + } + } + } + /* leave interrupt */ + rt_interrupt_leave(); +} + +void GPIOC_Handler(void) +{ + static int gpio[24]; + int index = 0; + static int init = 0; + pin_t *pin; + /* enter interrupt */ + rt_interrupt_enter(); + if (init == 0) + { + init = 1; + for (pin = (pin_t *)&swm32_pin_map[1]; + pin->package_index < ITEM_NUM(swm32_pin_map); + pin++) + { + if (pin->port == GPIOC) + { + gpio[index] = pin->package_index; + index++; + RT_ASSERT(index <= 24) + } + } + } + for (index = 0; index < 24; index++) + { + pin = get_pin(gpio[index]); + if (index != RT_NULL) + { + if (EXTI_State(pin->port, pin->group_index)) + { + EXTI_Clear(pin->port, pin->group_index); + if (pin->callback) + { + pin->callback(pin->callback_args); + } + } + } + } + /* leave interrupt */ + rt_interrupt_leave(); +} + +void GPIOM_Handler(void) +{ + static int gpio[24]; + int index = 0; + static int init = 0; + pin_t *pin; + /* enter interrupt */ + rt_interrupt_enter(); + if (init == 0) + { + init = 1; + for (pin = (pin_t *)&swm32_pin_map[1]; + pin->package_index < ITEM_NUM(swm32_pin_map); + pin++) + { + if (pin->port == GPIOM) + { + gpio[index] = pin->package_index; + index++; + RT_ASSERT(index <= 24) + } + } + } + for (index = 0; index < 24; index++) + { + pin = get_pin(gpio[index]); + if (index != RT_NULL) + { + if (EXTI_State(pin->port, pin->group_index)) + { + EXTI_Clear(pin->port, pin->group_index); + if (pin->callback) + { + pin->callback(pin->callback_args); + } + } + } + } + /* leave interrupt */ + rt_interrupt_leave(); +} + +void GPION_Handler(void) +{ + static int gpio[24]; + int index = 0; + static int init = 0; + pin_t *pin; + /* enter interrupt */ + rt_interrupt_enter(); + if (init == 0) + { + init = 1; + for (pin = (pin_t *)&swm32_pin_map[1]; + pin->package_index < ITEM_NUM(swm32_pin_map); + pin++) + { + if (pin->port == GPION) + { + gpio[index] = pin->package_index; + index++; + RT_ASSERT(index <= 24) + } + } + } + for (index = 0; index < 24; index++) + { + pin = get_pin(gpio[index]); + if (index != RT_NULL) + { + if (EXTI_State(pin->port, pin->group_index)) + { + EXTI_Clear(pin->port, pin->group_index); + if (pin->callback) + { + pin->callback(pin->callback_args); + } + } + } + } + /* leave interrupt */ + rt_interrupt_leave(); +} + +void GPIOP_Handler(void) +{ + static int gpio[24]; + int index = 0; + static int init = 0; + pin_t *pin; + /* enter interrupt */ + rt_interrupt_enter(); + if (init == 0) + { + init = 1; + for (pin = (pin_t *)&swm32_pin_map[1]; + pin->package_index < ITEM_NUM(swm32_pin_map); + pin++) + { + if (pin->port == GPIOP) + { + gpio[index] = pin->package_index; + index++; + RT_ASSERT(index <= 24) + } + } + } + for (index = 0; index < 24; index++) + { + pin = get_pin(gpio[index]); + if (index != RT_NULL) + { + if (EXTI_State(pin->port, pin->group_index)) + { + EXTI_Clear(pin->port, pin->group_index); + if (pin->callback) + { + pin->callback(pin->callback_args); + } + } + } + } + /* leave interrupt */ + rt_interrupt_leave(); +} diff --git a/bsp/swm320-lq100/drivers/drv_gpio.h b/bsp/swm320-lq100/drivers/drv_gpio.h new file mode 100644 index 0000000000..4993272726 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_gpio.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_GPIO_H__ +#define DRV_GPIO_H__ + +int rt_hw_pin_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_i2c.c b/bsp/swm320-lq100/drivers/drv_i2c.c new file mode 100644 index 0000000000..322d735a68 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_i2c.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#include +#include +#include +#include + +static void drv_set_sda(void *data, rt_int32_t state) +{ + rt_pin_mode(BSP_I2C_SDA, PIN_MODE_OUTPUT); + rt_pin_write(BSP_I2C_SDA, state); +} + +static void drv_set_scl(void *data, rt_int32_t state) +{ + rt_pin_mode(BSP_I2C_SCL, PIN_MODE_OUTPUT); + rt_pin_write(BSP_I2C_SCL, state); +} + +static rt_int32_t drv_get_sda(void *data) +{ + rt_pin_mode(BSP_I2C_SDA, PIN_MODE_INPUT_PULLUP); + return rt_pin_read(BSP_I2C_SDA); +} + +static rt_int32_t drv_get_scl(void *data) +{ + rt_pin_mode(BSP_I2C_SCL, PIN_MODE_INPUT_PULLUP); + return rt_pin_read(BSP_I2C_SCL); +} + +static void drv_udelay(rt_uint32_t us) +{ + int i = (SystemCoreClock / 4000000 * us); + while (i) + { + i--; + } +} + +static const struct rt_i2c_bit_ops drv_bit_ops = +{ + RT_NULL, + drv_set_sda, + drv_set_scl, + drv_get_sda, + drv_get_scl, + drv_udelay, + 1, + 100 +}; + +int rt_hw_i2c_init(void) +{ + static struct rt_i2c_bus_device i2c2_bus; + rt_memset((void *)&i2c2_bus, 0, sizeof(struct rt_i2c_bus_device)); + i2c2_bus.priv = (void *)&drv_bit_ops; + rt_i2c_bit_add_bus(&i2c2_bus, BSP_I2C_BUS_NAME); + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); diff --git a/bsp/swm320-lq100/drivers/drv_i2c.h b/bsp/swm320-lq100/drivers/drv_i2c.h new file mode 100644 index 0000000000..01cbcd7669 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_i2c.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_I2C_H__ +#define DRV_I2C_H__ + +int rt_hw_i2c_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_iwg.c b/bsp/swm320-lq100/drivers/drv_iwg.c new file mode 100644 index 0000000000..c8cd408a08 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_iwg.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#include +#include "rtthread.h" +#include "rtdevice.h" + +static rt_err_t swm320_wdt_init(rt_watchdog_t *wdt) +{ + WDT_Init(WDT, SystemCoreClock / 2, WDT_MODE_INTERRUPT); + + return RT_EOK; +} + +static rt_err_t swm320_wdt_control(rt_watchdog_t *wdt, int cmd, void *arg) +{ + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + *(uint32_t *)arg = WDT->LOAD; + break; + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + WDT_Stop(WDT); + WDT->LOAD = SystemCoreClock / 1000 * (*(uint32_t *)arg); + break; + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + *(uint32_t *)arg = WDT_GetValue(WDT); + break; + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + WDT_Feed(WDT); + break; + case RT_DEVICE_CTRL_WDT_START: + WDT_Start(WDT); + break; + case RT_DEVICE_CTRL_WDT_STOP: + WDT_Stop(WDT); + break; + default: + break; + } + + return RT_EOK; +} + +rt_watchdog_t swm320_wdt; +const static struct rt_watchdog_ops swm320_wdt_ops = +{ + swm320_wdt_init, + swm320_wdt_control +}; + +int rt_hw_wdt_init(void) +{ + rt_err_t result = RT_EOK; + + swm320_wdt.ops = &swm320_wdt_ops; + + result = rt_hw_watchdog_register(&swm320_wdt, + "iwg", + RT_DEVICE_FLAG_RDWR, + WDT); + + return result; +} +INIT_BOARD_EXPORT(rt_hw_wdt_init); + +void WDT_Handler(void) +{ + WDT_INTClr(WDT); +} diff --git a/bsp/swm320-lq100/drivers/drv_iwg.h b/bsp/swm320-lq100/drivers/drv_iwg.h new file mode 100644 index 0000000000..f4e85df8a7 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_iwg.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_IWG_H__ +#define DRV_IWG_H__ + +int rt_hw_wdt_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_nor_flash.c b/bsp/swm320-lq100/drivers/drv_nor_flash.c new file mode 100644 index 0000000000..7acfc64088 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_nor_flash.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#include +#include +#include +#include +#include + +#define BLOCK_SIZE (64 * 1024) +#define FLASH_SIZE (BSP_NOR_FLASH_SIZE) +#define BLOCK_COUNTER (FLASH_SIZE / BLOCK_SIZE) + +static struct rt_mutex flash_lock; + +/* RT-Thread MTD device interface */ +static long swm320_read_id(struct rt_mtd_nor_device *device) +{ + return 0xdeadbeef; +} + +static rt_size_t swm320_read(struct rt_mtd_nor_device *device, + rt_off_t position, + rt_uint8_t *data, + rt_size_t size) +{ + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); + memcpy(data, ((const void *)(NORFLM_BASE + position)), size); + rt_mutex_release(&flash_lock); + return size; +} + +static rt_size_t swm320_write(struct rt_mtd_nor_device *device, + rt_off_t position, + const rt_uint8_t *data, + rt_size_t size) +{ + rt_size_t i; + const rt_uint16_t *hwdata = (const rt_uint16_t *)data; + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); + for (i = 0; i < size / 2; i++) + { + NORFL_Write(position, hwdata[i]); + position += 2; + } + rt_mutex_release(&flash_lock); + return size; +} + +static rt_err_t swm320_erase_block(struct rt_mtd_nor_device *device, + rt_off_t offset, + rt_uint32_t length) +{ + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); + NORFL_SectorErase(offset); + rt_mutex_release(&flash_lock); + return RT_EOK; +} + +const static struct rt_mtd_nor_driver_ops mtd_ops = +{ + swm320_read_id, + swm320_read, + swm320_write, + swm320_erase_block +}; + +static rt_err_t hw_init() +{ + NORFL_InitStructure NORFL_InitStruct; + PORT->PORTP_SEL0 = 0xAAAAAAAA; //PP0-23 => ADDR0-23 + PORT->PORTP_SEL1 = 0xAAAA; + + PORT->PORTM_SEL0 = 0xAAAAAAAA; //PM0-15 => DATA15-0 + PORT->PORTM_INEN = 0xFFFF; + + PORT->PORTM_SEL1 = 0x2AA; //PM16 => OEN, PM17 => WEN, PM18 => NORFL_CSN,PM19 => SDRAM_CSN, PM20 => SRAM_CSN, PM21 => SDRAM_CKE + + NORFL_InitStruct.DataWidth = 16; + NORFL_InitStruct.WELowPulseTime = 5; + NORFL_InitStruct.OEPreValidTime = 12; + NORFL_InitStruct.OperFinishIEn = 0; + NORFL_InitStruct.OperTimeoutIEn = 0; + NORFL_Init(&NORFL_InitStruct); + return RT_EOK; +} +static struct rt_mtd_nor_device mtd; +int rt_hw_norflash_init(void) +{ + hw_init(); + /* set page size and block size */ + mtd.block_size = BLOCK_SIZE; /* 64kByte */ + mtd.ops = &mtd_ops; + + /* initialize mutex */ + if (rt_mutex_init(&flash_lock, "nor", RT_IPC_FLAG_FIFO) != RT_EOK) + { + rt_kprintf("init sd lock mutex failed\n"); + return -RT_ERROR; + } + mtd.block_start = 0; + mtd.block_end = BLOCK_COUNTER; + + /* register MTD device */ + rt_mtd_nor_register_device("nor", &mtd); + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_norflash_init); + +#ifdef RT_USING_FINSH +#include +void nor_erase(void) +{ + NORFL_ChipErase(); +} +MSH_CMD_EXPORT(nor_erase, erase all block in SPI flash); +#endif diff --git a/bsp/swm320-lq100/drivers/drv_nor_flash.h b/bsp/swm320-lq100/drivers/drv_nor_flash.h new file mode 100644 index 0000000000..86260be87e --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_nor_flash.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_NOR_FLASH_H__ +#define DRV_NOR_FLASH_H__ + +int rt_hw_norflash_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_pwm.c b/bsp/swm320-lq100/drivers/drv_pwm.c new file mode 100644 index 0000000000..3d6f9203ef --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_pwm.c @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#include +#include +#include +#include + +#define SWM320_PWM_DEVICE(pwm) (struct swm320_pwm_dev *)(pwm) + +#define SWM320_PWM_TIMER_SET(time) ((time) / 1000.0 * 120) + +struct swm320_pwm_dev +{ + struct rt_device_pwm parent; + PWM_TypeDef *pwm_periph; +}; + +static rt_err_t swm320_pwm_enable(void *user_data, + struct rt_pwm_configuration *cfg, + rt_bool_t enable) +{ + rt_err_t ret = RT_EOK; + + if (RT_TRUE == enable) + { + if (2 == cfg->channel) + { + PWM_Start((PWM_TypeDef *)user_data, 1, 1); + } + if (1 == cfg->channel) + { + PWM_Start((PWM_TypeDef *)user_data, 0, 1); + } + if (0 == cfg->channel) + { + PWM_Start((PWM_TypeDef *)user_data, 1, 0); + } + if (3 == cfg->channel) + { + PWM_Start((PWM_TypeDef *)user_data, 0, 0); + } + } + else if (RT_FALSE == enable) + { + if (2 == cfg->channel) + { + PWM_Stop((PWM_TypeDef *)user_data, 1, 1); + } + if (1 == cfg->channel) + { + PWM_Stop((PWM_TypeDef *)user_data, 0, 1); + } + if (0 == cfg->channel) + { + PWM_Stop((PWM_TypeDef *)user_data, 1, 0); + } + if (3 == cfg->channel) + { + PWM_Stop((PWM_TypeDef *)user_data, 0, 0); + } + } + else + { + ret = RT_ERROR; + } + + return ret; +} + +static rt_err_t swm320_pwm_control(struct rt_device_pwm *device, + int cmd, + void *arg) +{ + rt_err_t ret = RT_EOK; + struct swm320_pwm_dev *pwm = SWM320_PWM_DEVICE(device->parent.user_data); + struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg; + + RT_ASSERT(pwm != RT_NULL); + + switch (cmd) + { + case PWM_CMD_ENABLE: + + ret = swm320_pwm_enable((void *)pwm->pwm_periph, cfg, RT_TRUE); + break; + case PWM_CMD_DISABLE: + + ret = swm320_pwm_enable((void *)pwm->pwm_periph, cfg, RT_FALSE); + break; + case PWM_CMD_SET: + PWM_SetHDuty(pwm->pwm_periph, + cfg->channel, + SWM320_PWM_TIMER_SET(cfg->pulse)); + PWM_SetCycle(pwm->pwm_periph, + cfg->channel, + SWM320_PWM_TIMER_SET(cfg->period)); + break; + case PWM_CMD_GET: + cfg->pulse = PWM_GetHDuty(pwm->pwm_periph, cfg->channel); + break; + default: + break; + } + + return ret; +} + +const static struct rt_pwm_ops swm320_pwm_ops = +{ + swm320_pwm_control +}; + +int rt_hw_pwm_init(void) +{ + rt_err_t ret = RT_EOK; + PWM_InitStructure PWM_initStruct; + + PWM_initStruct.clk_div = PWM_CLKDIV_1; /* F_PWM = 120M/1 = 120M */ + PWM_initStruct.mode = PWM_MODE_INDEP; /* A路和B路独立输出 */ + PWM_initStruct.cycleA = SWM320_PWM_TIMER_SET(1000); + PWM_initStruct.hdutyA = SWM320_PWM_TIMER_SET(500); + PWM_initStruct.initLevelA = 1; + PWM_initStruct.cycleB = SWM320_PWM_TIMER_SET(1000); + PWM_initStruct.hdutyB = SWM320_PWM_TIMER_SET(250); + PWM_initStruct.initLevelB = 1; + PWM_initStruct.HEndAIEn = 0; + PWM_initStruct.NCycleAIEn = 0; + PWM_initStruct.HEndBIEn = 0; + PWM_initStruct.NCycleBIEn = 0; + +#ifdef BSP_USING_PWM0 + static struct swm320_pwm_dev pwm_dev0; + pwm_dev0.pwm_periph = PWM0; + PWM_Init(pwm_dev0.pwm_periph, &PWM_initStruct); + PORT_Init(PORTA, PIN4, FUNMUX0_PWM0A_OUT, 0); + PORT_Init(PORTA, PIN10, FUNMUX0_PWM0B_OUT, 0); + ret = rt_device_pwm_register(&pwm_dev0.parent, + "pwm0", + &swm320_pwm_ops, + &pwm_dev0); + +#endif + +#ifdef BSP_USING_PWM1 + static struct swm320_pwm_dev pwm_dev1; + pwm_dev1.pwm_periph = PWM1; + PWM_Init(pwm_dev1.pwm_periph, &PWM_initStruct); + PORT_Init(PORTA, PIN5, FUNMUX1_PWM1A_OUT, 0); + PORT_Init(PORTA, PIN9, FUNMUX1_PWM1B_OUT, 0); + ret = rt_device_pwm_register(&pwm_dev1.parent, + "pwm1", + &swm320_pwm_ops, + &pwm_dev1); +#endif + +#ifdef BSP_USING_PWM2 + static struct swm320_pwm_dev pwm_dev2; + pwm_dev2.pwm_periph = PWM2; + PWM_Init(pwm_dev2.pwm_periph, &PWM_initStruct); + PORT_Init(PORTP, PIN0, FUNMUX0_PWM2A_OUT, 0); + PORT_Init(PORTP, PIN2, FUNMUX0_PWM2B_OUT, 0); + ret = rt_device_pwm_register(&pwm_dev2.parent, + "pwm2", + &swm320_pwm_ops, + &pwm_dev2); +#endif + +#ifdef BSP_USING_PWM3 + static struct swm320_pwm_dev pwm_dev3; + pwm_dev3.pwm_periph = PWM3; + PWM_Init(pwm_dev3.pwm_periph, &PWM_initStruct); + PORT_Init(PORTP, PIN1, FUNMUX1_PWM3A_OUT, 0); + PORT_Init(PORTP, PIN3, FUNMUX1_PWM3B_OUT, 0); + ret = rt_device_pwm_register(&pwm_dev3.parent, + "pwm3", + &swm320_pwm_ops, + &pwm_dev3); +#endif + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_pwm_init); diff --git a/bsp/swm320-lq100/drivers/drv_pwm.h b/bsp/swm320-lq100/drivers/drv_pwm.h new file mode 100644 index 0000000000..94bbf0c750 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_pwm.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_PWM_H__ +#define DRV_PWM_H__ + +int rt_hw_pwm_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_rtc.c b/bsp/swm320-lq100/drivers/drv_rtc.c new file mode 100644 index 0000000000..51597ba73d --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_rtc.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#include +#include +#include +#include +#include +#include + +/** + * This function will get the weed day from a date. + * + * @param year the year of time + * @param month the month of time + * @param date the date of time + * + * @return the week day 0 ~ 6 : sun ~ sat + * + * @note No + */ +static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date) +{ + uint32_t i, cnt = 0; + const uint32_t daysOfMonth[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + + for (i = 1; i < month; i++) + cnt += daysOfMonth[i]; + + cnt += date; + + if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && + (month >= 3)) + cnt += 1; + + cnt += (year - 1901) * 365; + + for (i = 1901; i < year; i++) + { + if ((i % 4 == 0) && ((i % 100 != 0) || (i % 400 == 0))) + cnt += 1; + } + + return (cnt + 1) % 7; +} + +static void RTC_SetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime) +{ + RTC_Stop(RTCx); + + while (RTCx->CFGABLE == 0); + + RTCx->MINSEC = (dateTime->Second << RTC_MINSEC_SEC_Pos) | + (dateTime->Minute << RTC_MINSEC_MIN_Pos); + + RTCx->DATHUR = (dateTime->Hour << RTC_DATHUR_HOUR_Pos) | + ((dateTime->Date - 1) << RTC_DATHUR_DATE_Pos); + + RTCx->MONDAY = (calcWeekDay(dateTime->Year, dateTime->Month, dateTime->Date) + << RTC_MONDAY_DAY_Pos) | + ((dateTime->Month - 1) << RTC_MONDAY_MON_Pos); + + RTCx->YEAR = dateTime->Year - 1901; + + RTCx->LOAD = 1 << RTC_LOAD_TIME_Pos; + + RTC_Start(RTC); +} + +static rt_err_t swm320_rtc_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t result = RT_EOK; + + struct tm time_temp; + struct tm *pNow; + RTC_DateTime dateTime; + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + RTC_GetDateTime(RTC, &dateTime); + time_temp.tm_sec = dateTime.Second; + time_temp.tm_min = dateTime.Minute; + time_temp.tm_hour = dateTime.Hour; + time_temp.tm_mday = dateTime.Date; + time_temp.tm_mon = dateTime.Month - 1; + time_temp.tm_year = dateTime.Year - 1900; + *((time_t *)args) = mktime(&time_temp); + break; + case RT_DEVICE_CTRL_RTC_SET_TIME: + rt_enter_critical(); + /* converts calendar time time into local time. */ + pNow = localtime((const time_t *)args); + /* copy the statically located variable */ + memcpy(&time_temp, pNow, sizeof(struct tm)); + /* unlock scheduler. */ + rt_exit_critical(); + + dateTime.Hour = time_temp.tm_hour; + dateTime.Minute = time_temp.tm_min; + dateTime.Second = time_temp.tm_sec; + dateTime.Year = time_temp.tm_year + 1900; + dateTime.Month = time_temp.tm_mon + 1; + dateTime.Date = time_temp.tm_mday; + RTC_SetDateTime(RTC, &dateTime); + break; + case RT_DEVICE_CTRL_RTC_GET_ALARM: + + break; + case RT_DEVICE_CTRL_RTC_SET_ALARM: + + break; + default: + break; + } + + return result; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops swm320_rtc_ops = +{ + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + swm320_rtc_control +}; +#endif + +int rt_hw_rtc_init(void) +{ + rt_err_t ret = RT_EOK; + static struct rt_device rtc_dev; + RTC_InitStructure RTC_initStruct; + + RTC_initStruct.Year = 2018; + RTC_initStruct.Month = 1; + RTC_initStruct.Date = 1; + RTC_initStruct.Hour = 12; + RTC_initStruct.Minute = 0; + RTC_initStruct.Second = 0; + RTC_initStruct.SecondIEn = 0; + RTC_initStruct.MinuteIEn = 0; + RTC_Init(RTC, &RTC_initStruct); + RTC_Start(RTC); + + rtc_dev.type = RT_Device_Class_RTC; + rtc_dev.rx_indicate = RT_NULL; + rtc_dev.tx_complete = RT_NULL; + +#ifdef RT_USING_DEVICE_OPS + rtc_dev.ops = &swm320_rtc_ops; +#else + rtc_dev.init = RT_NULL; + rtc_dev.open = RT_NULL; + rtc_dev.close = RT_NULL; + rtc_dev.read = RT_NULL; + rtc_dev.write = RT_NULL; + rtc_dev.control = swm320_rtc_control; +#endif + + rtc_dev.user_data = RTC; + + ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR); + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); diff --git a/bsp/swm320-lq100/drivers/drv_rtc.h b/bsp/swm320-lq100/drivers/drv_rtc.h new file mode 100644 index 0000000000..f72d3d3d94 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_rtc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_RTC_H__ +#define DRV_RTC_H__ + +int rt_hw_rtc_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_spi.c b/bsp/swm320-lq100/drivers/drv_spi.c new file mode 100644 index 0000000000..e766f0ea81 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_spi.c @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#include +#include +#include +#include +#include +#include + +#define SPIRXEVENT 0x01 +#define SPITXEVENT 0x02 +#define SPITIMEOUT 2 +#define SPICRCEN 0 + +struct swm320_spi +{ + SPI_TypeDef *swm320_spi; + struct rt_spi_configuration *cfg; +}; + +static rt_err_t swm320_spi_init(SPI_TypeDef *spix, + struct rt_spi_configuration *cfg) +{ + SPI_InitStructure SPI_initStruct; + if (cfg->mode & RT_SPI_SLAVE) + { + SPI_initStruct.Master = 0; + } + else + { + SPI_initStruct.Master = 1; + } + if (cfg->mode & RT_SPI_3WIRE) + { + return RT_EINVAL; + } + if (cfg->data_width == 8) + { + SPI_initStruct.WordSize = 8; + } + else if (cfg->data_width == 16) + { + SPI_initStruct.WordSize = 16; + } + else + { + return RT_EINVAL; + } + if (cfg->mode & RT_SPI_CPHA) + { + SPI_initStruct.SampleEdge = SPI_SECOND_EDGE; + } + else + { + SPI_initStruct.SampleEdge = SPI_FIRST_EDGE; + } + if (cfg->mode & RT_SPI_CPOL) + { + SPI_initStruct.IdleLevel = SPI_HIGH_LEVEL; + } + else + { + SPI_initStruct.IdleLevel = SPI_LOW_LEVEL; + } + if (cfg->max_hz >= SystemCoreClock / 4) + { + SPI_initStruct.clkDiv = SPI_CLKDIV_4; + } + else if (cfg->max_hz >= SystemCoreClock / 8) + { + SPI_initStruct.clkDiv = SPI_CLKDIV_8; + } + else if (cfg->max_hz >= SystemCoreClock / 16) + { + SPI_initStruct.clkDiv = SPI_CLKDIV_16; + } + else if (cfg->max_hz >= SystemCoreClock / 32) + { + SPI_initStruct.clkDiv = SPI_CLKDIV_32; + } + else if (cfg->max_hz >= SystemCoreClock / 64) + { + SPI_initStruct.clkDiv = SPI_CLKDIV_64; + } + else if (cfg->max_hz >= SystemCoreClock / 128) + { + SPI_initStruct.clkDiv = SPI_CLKDIV_128; + } + else if (cfg->max_hz >= SystemCoreClock / 256) + { + SPI_initStruct.clkDiv = SPI_CLKDIV_256; + } + else + { + /* min prescaler 512 */ + SPI_initStruct.clkDiv = SPI_CLKDIV_512; + } + SPI_initStruct.FrameFormat = SPI_FORMAT_SPI; + SPI_initStruct.RXHFullIEn = 0; + SPI_initStruct.TXEmptyIEn = 0; + SPI_initStruct.TXCompleteIEn = 0; + SPI_Init(spix, &SPI_initStruct); + SPI_Open(spix); + return RT_EOK; +} + +#define SPISTEP(datalen) (((datalen) == 8) ? 1 : 2) +#define SPISEND_1(reg, ptr, datalen) \ + do \ + { \ + if (datalen == 8) \ + { \ + (reg) = *(rt_uint8_t *)(ptr); \ + } \ + else \ + { \ + (reg) = *(rt_uint16_t *)(ptr); \ + } \ + } while (0) +#define SPIRECV_1(reg, ptr, datalen) \ + do \ + { \ + if (datalen == 8) \ + { \ + *(rt_uint8_t *)(ptr) = (reg); \ + } \ + else \ + { \ + *(rt_uint16_t *)(ptr) = reg; \ + } \ + } while (0) + +static rt_err_t spitxrx1b(struct swm320_spi *hspi, void *rcvb, const void *sndb) +{ + rt_uint32_t padrcv = 0; + rt_uint32_t padsnd = 0xFF; + if (!rcvb && !sndb) + { + return RT_ERROR; + } + if (!rcvb) + { + rcvb = &padrcv; + } + if (!sndb) + { + sndb = &padsnd; + } + while (SPI_IsTXFull(hspi->swm320_spi)); + SPISEND_1(hspi->swm320_spi->DATA, sndb, hspi->cfg->data_width); + while (SPI_IsRXEmpty(hspi->swm320_spi)); + SPIRECV_1(hspi->swm320_spi->DATA, rcvb, hspi->cfg->data_width); + return RT_EOK; +} + +static rt_uint32_t swm320_spi_xfer(struct rt_spi_device *device, + struct rt_spi_message *message) +{ + rt_err_t res; + struct swm320_spi *hspi = (struct swm320_spi *)device->bus->parent.user_data; + struct swm320_spi_cs *cs = device->parent.user_data; + const rt_uint8_t *sndb = message->send_buf; + rt_uint8_t *rcvb = message->recv_buf; + rt_int32_t length = message->length; + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + if (message->cs_take) + { + rt_pin_write(cs->pin, 0); + } + while (length) + { + res = spitxrx1b(hspi, rcvb, sndb); + if (rcvb) + { + rcvb += SPISTEP(hspi->cfg->data_width); + } + if (sndb) + { + sndb += SPISTEP(hspi->cfg->data_width); + } + if (res != RT_EOK) + { + break; + } + length--; + } + /* Wait until Busy flag is reset before disabling SPI */ + while (!SPI_IsTXEmpty(hspi->swm320_spi) && !SPI_IsRXEmpty(hspi->swm320_spi)); + if (message->cs_release) + { + rt_pin_write(cs->pin, 1); + } + return message->length - length; +} + +static rt_err_t swm320_spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + struct swm320_spi *hspi = (struct swm320_spi *)device->bus->parent.user_data; + hspi->cfg = configuration; + return swm320_spi_init(hspi->swm320_spi, configuration); +} +const static struct rt_spi_ops swm320_spi_ops = +{ + .configure = swm320_spi_configure, + .xfer = swm320_spi_xfer, +}; + +#ifdef BSP_USING_SPI0 + static struct rt_spi_bus swm320_spi_bus0; + static struct swm320_spi swm320_spi0; +#endif //BSP_USING_SPI0 + +#ifdef BSP_USING_SPI1 + static struct rt_spi_bus swm320_spi_bus1; + static struct swm320_spi swm320_spi1; +#endif //BSP_USING_SPI1 + +static int swm320_spi_register_bus(SPI_TypeDef *SPIx, const char *name) +{ + struct rt_spi_bus *spi_bus; + struct swm320_spi *swm320_spi; + if (SPIx == SPI0) + { + PORT_Init(PORTC, PIN5, FUNMUX1_SPI0_SCLK, 0); + PORT_Init(PORTC, PIN6, FUNMUX0_SPI0_MOSI, 0); + PORT_Init(PORTC, PIN7, FUNMUX1_SPI0_MISO, 1); + spi_bus = &swm320_spi_bus0; + swm320_spi = &swm320_spi0; + } + else if (SPIx == SPI1) + { + PORT_Init(PORTM, PIN5, FUNMUX1_SPI1_SCLK, 0); + PORT_Init(PORTC, PIN2, FUNMUX0_SPI1_MOSI, 0); + PORT_Init(PORTC, PIN3, FUNMUX1_SPI1_MISO, 1); + spi_bus = &swm320_spi_bus1; + swm320_spi = &swm320_spi1; + } + else + { + return -1; + } + swm320_spi->swm320_spi = SPIx; + spi_bus->parent.user_data = swm320_spi; + return rt_spi_bus_register(spi_bus, name, &swm320_spi_ops); +} + +//cannot be used before completion init +static rt_err_t swm320_spi_bus_attach_device(rt_uint32_t pin, + const char *bus_name, + const char *device_name) +{ + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + struct swm320_spi_cs *cs_pin = (struct swm320_spi_cs *)rt_malloc(sizeof(struct swm320_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + cs_pin->pin = pin; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, 1); + return rt_spi_bus_attach_device(spi_device, + device_name, + bus_name, + (void *)cs_pin); +} + +int rt_hw_spi_init(void) +{ + int result = 0; +#ifdef BSP_USING_SPI0 + result = swm320_spi_register_bus(SPI0, "spi0"); +#endif +#ifdef BSP_USING_SPI1 + result = swm320_spi_register_bus(SPI1, "spi1"); +#endif + return result; +} +INIT_BOARD_EXPORT(rt_hw_spi_init); diff --git a/bsp/swm320-lq100/drivers/drv_spi.h b/bsp/swm320-lq100/drivers/drv_spi.h new file mode 100644 index 0000000000..7e5366ab58 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_spi.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_SPI_H__ +#define DRV_SPI_H__ + +#include + +struct swm320_spi_cs +{ + rt_uint32_t pin; +}; + +//cannot be used before completion init +static rt_err_t swm320_spi_bus_attach_device(rt_uint32_t pin, + const char *bus_name, + const char *device_name); +int rt_hw_spi_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_sram.c b/bsp/swm320-lq100/drivers/drv_sram.c new file mode 100644 index 0000000000..8b9be8f0d4 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_sram.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#include +#include +#include +#include +#include + +int rt_hw_sram_init(void) +{ + int i; + PORT->PORTP_SEL0 = 0xAAAAAAAA; /* PP0-23 => ADDR0-23 */ + PORT->PORTP_SEL1 = 0xAAAA; + PORT->PORTM_SEL0 = 0xAAAAAAAA; /* PM0-15 => DATA15-0 */ + PORT->PORTM_INEN |= 0xFFFF; + PORT->PORTM_SEL1 = 0x2AA; /* PM16 => OENã€PM17 => WENã€PM18 => NORFL_CSNã€PM19 => SDRAM_CSNã€PM20 => SRAM_CSNã€PM21 => SDRAM_CKE */ + + /* é…ç½®SRAMå‰éœ€è¦åˆ·æ–°ä¸‹SDRAM控制器 */ + + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + + while (SDRAMC->REFDONE == 0) + ; + SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); + + for (i = 0; i < 1000; i++) + { + } + SYS->CLKEN &= ~(1 << SYS_CLKEN_SDRAM_Pos); + + SYS->CLKEN |= (1 << SYS_CLKEN_RAMC_Pos); + + SRAMC->CR = (9 << SRAMC_CR_RWTIME_Pos) | + (0 << SRAMC_CR_BYTEIF_Pos) | // 16ä½æŽ¥å£ + (0 << SRAMC_CR_HBLBDIS_Pos); // 使能字节ã€åŠå­—访问 + + return 0; +} diff --git a/bsp/swm320-lq100/drivers/drv_sram.h b/bsp/swm320-lq100/drivers/drv_sram.h new file mode 100644 index 0000000000..5f81319733 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_sram.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_SRAM_H__ +#define DRV_SRAM_H__ + +int rt_hw_sram_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_uart.c b/bsp/swm320-lq100/drivers/drv_uart.c new file mode 100644 index 0000000000..fe02c4da55 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_uart.c @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#include +#include +#include +#include +#include + +struct swm320_uart +{ + UART_TypeDef *uart; + IRQn_Type irq; +}; + +static rt_err_t swm320_uart_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + struct swm320_uart *uart; + UART_InitStructure UART_initStruct; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct swm320_uart *)serial->parent.user_data; + NVIC_DisableIRQ(uart->irq); + UART_initStruct.Baudrate = cfg->baud_rate; + UART_initStruct.RXThreshold = 1; + UART_initStruct.RXThresholdIEn = 1; + UART_initStruct.TXThresholdIEn = 0; + UART_initStruct.TimeoutTime = 10; + UART_initStruct.TimeoutIEn = 0; + switch (cfg->data_bits) + { + case DATA_BITS_9: + UART_initStruct.DataBits = UART_DATA_9BIT; + break; + default: + UART_initStruct.DataBits = UART_DATA_8BIT; + break; + } + switch (cfg->stop_bits) + { + case STOP_BITS_2: + UART_initStruct.StopBits = UART_STOP_2BIT; + break; + default: + UART_initStruct.StopBits = UART_STOP_1BIT; + break; + } + switch (cfg->parity) + { + case PARITY_ODD: + UART_initStruct.Parity = UART_PARITY_ODD; + break; + case PARITY_EVEN: + UART_initStruct.Parity = UART_PARITY_EVEN; + break; + default: + UART_initStruct.Parity = UART_PARITY_NONE; + break; + } + UART_Init(uart->uart, &UART_initStruct); + UART_Open(uart->uart); + return RT_EOK; +} + +static rt_err_t swm320_uart_control(struct rt_serial_device *serial, + int cmd, void *arg) +{ + struct swm320_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct swm320_uart *)serial->parent.user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + break; + } + return RT_EOK; +} + +static int swm320_uart_putc(struct rt_serial_device *serial, char c) +{ + struct swm320_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct swm320_uart *)serial->parent.user_data; + while (UART_IsTXBusy(uart->uart)); + uart->uart->DATA = c; + return 1; +} + +static int swm320_uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct swm320_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct swm320_uart *)serial->parent.user_data; + ch = -1; + if (UART_IsRXFIFOEmpty(uart->uart) == 0) + { + UART_ReadByte(uart->uart, (uint32_t *)&ch); + } + return ch; +} + +static const struct rt_uart_ops swm320_uart_ops = +{ + swm320_uart_configure, + swm320_uart_control, + swm320_uart_putc, + swm320_uart_getc, +}; + +#if defined(BSP_USING_UART0) +/* UART0 device driver structure */ +static struct swm320_uart uart0; +static struct rt_serial_device serial0; +void UART0_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver */ + if (UART_INTRXThresholdStat(uart0.uart) || UART_INTTimeoutStat(uart0.uart)) + { + rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +/* UART1 device driver structure */ +static struct swm320_uart uart1; +static struct rt_serial_device serial1; +void UART1_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver */ + if (UART_INTRXThresholdStat(uart1.uart) || UART_INTTimeoutStat(uart1.uart)) + { + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +/* UART2 device driver structure */ +static struct swm320_uart uart2; +static struct rt_serial_device serial2; +void UART2_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver */ + if (UART_INTRXThresholdStat(uart2.uart) || UART_INTTimeoutStat(uart2.uart)) + { + rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +/* UART3 device driver structure */ +static struct swm320_uart uart3; +static struct rt_serial_device serial3; +void UART3_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver */ + if (UART_INTRXThresholdStat(uart3.uart) || UART_INTTimeoutStat(uart3.uart)) + { + rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +int rt_hw_uart_init(void) +{ + struct swm320_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; +#ifdef BSP_USING_UART0 + PORT_Init(PORTA, PIN2, FUNMUX0_UART0_RXD, 1); + PORT_Init(PORTA, PIN3, FUNMUX1_UART0_TXD, 0); + uart = &uart0; + uart->uart = UART0; + uart->irq = UART0_IRQn; + serial0.ops = &swm320_uart_ops; + serial0.config = config; + /* register UART0 device */ + rt_hw_serial_register(&serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART0 */ +#ifdef BSP_USING_UART1 + PORT_Init(PORTC, PIN2, FUNMUX0_UART1_RXD, 1); + PORT_Init(PORTC, PIN3, FUNMUX1_UART1_TXD, 0); + uart = &uart1; + uart->uart = UART1; + uart->irq = UART1_IRQn; + serial1.ops = &swm320_uart_ops; + serial1.config = config; + /* register UART1 device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART1 */ +#ifdef BSP_USING_UART2 + PORT_Init(PORTC, PIN4, FUNMUX0_UART2_RXD, 1); + PORT_Init(PORTC, PIN5, FUNMUX1_UART2_TXD, 0); + uart = &uart2; + uart->uart = UART2; + uart->irq = UART2_IRQn; + serial2.ops = &swm320_uart_ops; + serial2.config = config; + /* register UART2 device */ + rt_hw_serial_register(&serial2, "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART2 */ +#ifdef BSP_USING_UART3 + PORT_Init(PORTC, PIN6, FUNMUX0_UART3_RXD, 1); + PORT_Init(PORTC, PIN7, FUNMUX1_UART3_TXD, 0); + uart = &uart3; + uart->uart = UART3; + uart->irq = UART3_IRQn; + serial3.ops = &swm320_uart_ops; + serial3.config = config; + /* register UART3 device */ + rt_hw_serial_register(&serial3, "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART3 */ + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/swm320-lq100/drivers/drv_uart.h b/bsp/swm320-lq100/drivers/drv_uart.h new file mode 100644 index 0000000000..67193a45d4 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/linker_scripts/link.icf b/bsp/swm320-lq100/drivers/linker_scripts/link.icf new file mode 100644 index 0000000000..4d4eb64623 --- /dev/null +++ b/bsp/swm320-lq100/drivers/linker_scripts/link.icf @@ -0,0 +1,62 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x0; +define symbol __ICFEDIT_region_IROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region EROM_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__] + | mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__] + | mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; +define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] + | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] + | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +do not initialize { section .noinit }; +initialize by copy { readwrite }; +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + // Required in a multi-threaded application + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in IROM_region { readonly }; +place in EROM_region { readonly section application_specific_ro }; +place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP }; +place in ERAM_region { readwrite section application_specific_rw }; \ No newline at end of file diff --git a/bsp/swm320-lq100/drivers/linker_scripts/link.lds b/bsp/swm320-lq100/drivers/linker_scripts/link.lds new file mode 100644 index 0000000000..2f6896cfb3 --- /dev/null +++ b/bsp/swm320-lq100/drivers/linker_scripts/link.lds @@ -0,0 +1,137 @@ +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 1024KB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info 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+ + + DeviceDrivers + 0 + 0 + 0 + 0 + + 7 + 55 + 1 + 0 + 0 + 0 + ..\..\components\drivers\hwtimer\hwtimer.c + hwtimer.c + 0 + 0 + + + 7 + 56 + 1 + 0 + 0 + 0 + ..\..\components\drivers\i2c\i2c_core.c + i2c_core.c + 0 + 0 + + + 7 + 57 + 1 + 0 + 0 + 0 + ..\..\components\drivers\i2c\i2c_dev.c + i2c_dev.c + 0 + 0 + + + 7 + 58 + 1 + 0 + 0 + 0 + ..\..\components\drivers\i2c\i2c-bit-ops.c + i2c-bit-ops.c + 0 + 0 + + + 7 + 59 + 1 + 0 + 0 + 0 + ..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 7 + 60 + 1 + 0 + 0 + 0 + ..\..\components\drivers\misc\rt_drv_pwm.c + rt_drv_pwm.c + 0 + 0 + + + 7 + 61 + 1 + 0 + 0 + 0 + ..\..\components\drivers\mtd\mtd_nor.c + mtd_nor.c + 0 + 0 + + + 7 + 62 + 1 + 0 + 0 + 0 + ..\..\components\drivers\rtc\rtc.c + rtc.c + 0 + 0 + + + 7 + 63 + 1 + 0 + 0 + 0 + ..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + 7 + 64 + 1 + 0 + 0 + 0 + ..\..\components\drivers\spi\spi_core.c + spi_core.c + 0 + 0 + + + 7 + 65 + 1 + 0 + 0 + 0 + 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..\..\components\finsh\finsh_var.c + finsh_var.c + 0 + 0 + + + 8 + 88 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_vm.c + finsh_vm.c + 0 + 0 + + + 8 + 89 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_token.c + finsh_token.c + 0 + 0 + + + + + libc + 0 + 0 + 0 + 0 + + 9 + 90 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\libc.c + libc.c + 0 + 0 + + + 9 + 91 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\mem_std.c + mem_std.c + 0 + 0 + + + 9 + 92 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\stdio.c + stdio.c + 0 + 0 + + + 9 + 93 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\stubs.c + stubs.c + 0 + 0 + + + 9 + 94 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\time.c + time.c + 0 + 0 + + + 9 + 95 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\common\gmtime_r.c + gmtime_r.c + 0 + 0 + + + + diff --git a/bsp/swm320-lq100/project.uvprojx b/bsp/swm320-lq100/project.uvprojx new file mode 100644 index 0000000000..a7f37e5187 --- /dev/null +++ b/bsp/swm320-lq100/project.uvprojx @@ -0,0 +1,980 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + SWM320xE + Synwit + Synwit.SWM32_DFP.1.6.8 + http://www.synwit.com/pack + IRAM(0x20000000,0x20000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)) + 0 + $$Device:SWM320xE$CSL\SWM320\CMSIS\DeviceSupport\SWM320.h + + + + + + + + + + $$Device:SWM320xE$SVD\SWM320.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output @H.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 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applications;.;drivers;Libraries\CMSIS\CoreSupport;Libraries\CMSIS\DeviceSupport;Libraries\SWM320_StdPeriph_Driver;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + + + Libraries + + + system_SWM320.c + 1 + Libraries\CMSIS\DeviceSupport\system_SWM320.c + + + SWM320_adc.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_adc.c + + + SWM320_can.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_can.c + + + SWM320_crc.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_crc.c + + + SWM320_dma.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_dma.c + + + SWM320_exti.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_exti.c + + + SWM320_flash.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_flash.c + + + SWM320_gpio.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_gpio.c + + + SWM320_i2c.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_i2c.c + + + SWM320_lcd.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_lcd.c + + + SWM320_norflash.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_norflash.c + + + SWM320_port.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_port.c + + + SWM320_pwm.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_pwm.c + + + SWM320_rtc.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_rtc.c + + + SWM320_sdio.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_sdio.c + + + SWM320_sdram.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_sdram.c + + + SWM320_spi.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_spi.c + + + SWM320_timr.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_timr.c + + + SWM320_uart.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_uart.c + + + SWM320_wdt.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_wdt.c + + + startup_SWM320.s + 2 + Libraries\CMSIS\DeviceSupport\startup\arm\startup_SWM320.s + + + + + Kernel + + + clock.c + 1 + ..\..\src\clock.c + + + components.c + 1 + ..\..\src\components.c + + + cpu.c + 1 + ..\..\src\cpu.c + + + device.c + 1 + ..\..\src\device.c + + + idle.c + 1 + ..\..\src\idle.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + irq.c + 1 + ..\..\src\irq.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + mem.c + 1 + ..\..\src\mem.c + + + memheap.c + 1 + ..\..\src\memheap.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + object.c + 1 + ..\..\src\object.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + signal.c + 1 + ..\..\src\signal.c + + + thread.c + 1 + ..\..\src\thread.c + + + timer.c + 1 + ..\..\src\timer.c + + + + + CORTEX-M4 + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m4\cpuport.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m4\context_rvds.S + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + + + Filesystem + + + dfs.c + 1 + ..\..\components\dfs\src\dfs.c + + + dfs_file.c + 1 + ..\..\components\dfs\src\dfs_file.c + + + dfs_fs.c + 1 + ..\..\components\dfs\src\dfs_fs.c + + + dfs_posix.c + 1 + ..\..\components\dfs\src\dfs_posix.c + + + devfs.c + 1 + ..\..\components\dfs\filesystems\devfs\devfs.c + + + dfs_elm.c + 1 + ..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + + ff.c + 1 + ..\..\components\dfs\filesystems\elmfat\ff.c + + + ccsbcs.c + 1 + ..\..\components\dfs\filesystems\elmfat\option\ccsbcs.c + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + hwtimer.c + 1 + ..\..\components\drivers\hwtimer\hwtimer.c + + + i2c_core.c + 1 + ..\..\components\drivers\i2c\i2c_core.c + + + i2c_dev.c + 1 + ..\..\components\drivers\i2c\i2c_dev.c + + + i2c-bit-ops.c + 1 + ..\..\components\drivers\i2c\i2c-bit-ops.c + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + rt_drv_pwm.c + 1 + ..\..\components\drivers\misc\rt_drv_pwm.c + + + mtd_nor.c + 1 + ..\..\components\drivers\mtd\mtd_nor.c + + + rtc.c + 1 + ..\..\components\drivers\rtc\rtc.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + spi_core.c + 1 + ..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\components\drivers\spi\spi_dev.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + watchdog.c + 1 + ..\..\components\drivers\watchdog\watchdog.c + + + + + finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + symbol.c + 1 + ..\..\components\finsh\symbol.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + msh_cmd.c + 1 + ..\..\components\finsh\msh_cmd.c + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + + + libc + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + stdio.c + 1 + ..\..\components\libc\compilers\armlibc\stdio.c + + + stubs.c + 1 + ..\..\components\libc\compilers\armlibc\stubs.c + + + time.c + 1 + ..\..\components\libc\compilers\armlibc\time.c + + + gmtime_r.c + 1 + ..\..\components\libc\compilers\common\gmtime_r.c + + + + + + + + + + + + + +     diff --git a/bsp/swm320-lq100/rtconfig.h b/bsp/swm320-lq100/rtconfig.h new file mode 100644 index 0000000000..cd9c43e33e --- /dev/null +++ b/bsp/swm320-lq100/rtconfig.h @@ -0,0 +1,212 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40000 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 8 +#define DFS_FILESYSTEM_TYPES_MAX 8 +#define DFS_FD_MAX 8 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 +#define RT_DFS_ELM_REENTRANT +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_USING_HWTIMER +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_PIN +#define RT_USING_PWM +#define RT_USING_MTD_NOR +#define RT_USING_RTC +#define RT_USING_SPI +#define RT_USING_WDT + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* sample package */ + +/* samples: kernel and components samples */ + + +/* example package: hello */ + +#define SOC_SWM320VET7 + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO + +/* UART Drivers */ + +#define BSP_USING_UART0 + +/* SPI Drivers */ + + +/* I2C Drivers */ + + +/* PWM module */ + + +/* RTC module */ + +/* RTC SET */ + + +/* Onboard Peripheral Drivers */ + + +/* Offboard Peripheral Drivers */ + + +#endif diff --git a/bsp/swm320-lq100/rtconfig.py b/bsp/swm320-lq100/rtconfig.py new file mode 100644 index 0000000000..d60feb85dc --- /dev/null +++ b/bsp/swm320-lq100/rtconfig.py @@ -0,0 +1,92 @@ +# BSP Note: For TI EK-TM4C1294XL Tiva C Series Connected LancuhPad (REV D) + +import os +import sys +# toolchains options +CROSS_TOOL = 'gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +# device options +ARCH = 'arm' +CPU = 'cortex-m4' +FPU = 'fpv4-sp-d16' +FLOAT_ABI = 'softfp' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = '/Users/zhangyihong/.env/gcc-arm-none-eabi-5_4-2016q3/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + print("Not support gcc now\n") + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=' + FPU + ' -mfloat-abi=' + \ + FLOAT_ABI + ' -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -std=c99' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/LIB' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/arm/armcc/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + print('Not Support iar now\n') + exit(0) diff --git a/bsp/swm320-lq100/template.uvoptx b/bsp/swm320-lq100/template.uvoptx new file mode 100644 index 0000000000..f15d96c406 --- /dev/null +++ b/bsp/swm320-lq100/template.uvoptx @@ -0,0 +1,177 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FN1 -FC1000 -FD20000000 -FF0SWM320xE -FL080000 -FS00 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM) + + + 0 + JL2CM3 + -U801000899 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8002 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN1 -FF0SWM320xE -FS00 -FL080000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + +     diff --git a/bsp/swm320-lq100/template.uvprojx b/bsp/swm320-lq100/template.uvprojx new file mode 100644 index 0000000000..2a630de8b0 --- /dev/null +++ b/bsp/swm320-lq100/template.uvprojx @@ -0,0 +1,389 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + rt-thread + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + SWM320xE + Synwit + Synwit.SWM32_DFP.1.6.8 + http://www.synwit.com/pack + IRAM(0x20000000,0x20000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)) + 0 + $$Device:SWM320xE$CSL\SWM320\CMSIS\DeviceSupport\SWM320.h + + + + + + + + + + $$Device:SWM320xE$SVD\SWM320.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output @H.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + + + + + + + + + + + + + + + +     -- GitLab