From f69bbfeead507a9274a09a6a1e6bb3391ba7faf9 Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Mon, 13 Feb 2023 17:39:22 +0700 Subject: [PATCH] fix usb_switch_to_cdc_jtag() not re-enable USB D+ before reset (#7828) --- cores/esp32/esp32-hal-tinyusb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cores/esp32/esp32-hal-tinyusb.c b/cores/esp32/esp32-hal-tinyusb.c index 8bf9932d2..5f6e552ee 100644 --- a/cores/esp32/esp32-hal-tinyusb.c +++ b/cores/esp32/esp32-hal-tinyusb.c @@ -40,6 +40,7 @@ #include "esp32s2/rom/usb/chip_usb_dw_wrapper.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "hal/usb_serial_jtag_ll.h" +#include "hal/usb_phy_ll.h" #include "esp32s3/rom/usb/usb_persist.h" #include "esp32s3/rom/usb/usb_dc.h" #include "esp32s3/rom/usb/chip_usb_dw_wrapper.h" @@ -415,6 +416,7 @@ static void usb_switch_to_cdc_jtag(){ digitalWrite(USBPHY_DP_NUM, LOW); // Initialize CDC+JTAG ISR to listen for BUS_RESET + usb_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG); usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_LL_INTR_MASK); usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_LL_INTR_MASK); usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_BUS_RESET); -- GitLab