diff --git a/projects/VeriSilicon/imports.yml b/projects/VeriSilicon/imports.yml
new file mode 100644
index 0000000000000000000000000000000000000000..0c4fa19e4058222a8ba1a55f637600144464461a
--- /dev/null
+++ b/projects/VeriSilicon/imports.yml
@@ -0,0 +1,53 @@
+---
+group:
+  name: 'VeriSilicon'
+  description: ''
+  projects:
+  - name: 'TIM-VX'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'tensorflow'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'tflite-vx-delegate'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'acuitylite'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'tvm'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'mlcommons-inference'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'ffmpeg'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'acuity-models'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'solios-x-device-plugin'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'vpe'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'acuity-dataset'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'caffe'
+    description: ''
+    mirrorRelease: false
+    topic: ''
\ No newline at end of file