diff --git a/libcpu/arm/cortex-m0/context_gcc.S b/libcpu/arm/cortex-m0/context_gcc.S
index 309ac04cb2b3c6e4907b41dd4579ae2cc3eb1298..fafdb0e744aa000546eaf4f4330035e709f2185b 100644
--- a/libcpu/arm/cortex-m0/context_gcc.S
+++ b/libcpu/arm/cortex-m0/context_gcc.S
@@ -22,7 +22,7 @@
     .thumb
     .text
 
-    .equ    SCB_VTOR, 0xE000ED04            /* Vector Table Offset Register */
+    .equ    SCB_VTOR, 0xE000ED08            /* Vector Table Offset Register */
     .equ    ICSR, 0xE000ED04                /* interrupt control state register */
     .equ    PENDSVSET_BIT, 0x10000000       /* value to trigger PendSV exception */
     
diff --git a/libcpu/arm/cortex-m3/context_gcc.S b/libcpu/arm/cortex-m3/context_gcc.S
index fad274aea825f45777c901433a022f6dc915ed26..c36ca9a7c3172638994edd9f3a37a490e92d04a9 100644
--- a/libcpu/arm/cortex-m3/context_gcc.S
+++ b/libcpu/arm/cortex-m3/context_gcc.S
@@ -22,7 +22,7 @@
     .thumb
     .text
 
-    .equ    SCB_VTOR, 0xE000ED04            /* Vector Table Offset Register */
+    .equ    SCB_VTOR, 0xE000ED08            /* Vector Table Offset Register */
     .equ    ICSR, 0xE000ED04                /* interrupt control state register */
     .equ    PENDSVSET_BIT, 0x10000000       /* value to trigger PendSV exception */
     
diff --git a/libcpu/arm/cortex-m4/context_gcc.S b/libcpu/arm/cortex-m4/context_gcc.S
index 2fe9747d6f55a6fc31be4eb0ed482500b8c1b1df..b66e2570513bb379ec6a2dbb310b9b41630872b0 100644
--- a/libcpu/arm/cortex-m4/context_gcc.S
+++ b/libcpu/arm/cortex-m4/context_gcc.S
@@ -24,7 +24,7 @@
 .thumb
 .text
 
-.equ    SCB_VTOR,           0xE000ED04              /* Vector Table Offset Register */
+.equ    SCB_VTOR,           0xE000ED08              /* Vector Table Offset Register */
 .equ    NVIC_INT_CTRL,      0xE000ED04              /* interrupt control state register */
 .equ    NVIC_SYSPRI2,       0xE000ED20              /* system priority register (2) */
 .equ    NVIC_PENDSV_PRI,    0x00FF0000              /* PendSV priority value (lowest) */