From a6fb066f90d1009ab32e981cf8e7d47d55bbc9e6 Mon Sep 17 00:00:00 2001 From: nhzlx Date: Sun, 14 Apr 2019 08:42:13 +0000 Subject: [PATCH] Cherry Pick : 16837 Support ShuffleNet and MobileNet-v2 Support ShuffleNet and MobileNet-v2, test=release/1.4 --- .../inference/anakin/convert/activation.cc | 51 +++++-------------- .../inference/anakin/convert/activation.h | 17 ++++++- .../anakin/convert/affine_channel.cc | 20 +------- .../inference/anakin/convert/batch_norm.cc | 16 +----- .../fluid/inference/anakin/convert/concat.cc | 20 +------- .../fluid/inference/anakin/convert/conv2d.cc | 20 +------- .../inference/anakin/convert/conv2d_fusion.cc | 20 +------- .../anakin/convert/density_prior_box.cc | 24 +-------- .../inference/anakin/convert/detection_out.cc | 20 +------- .../fluid/inference/anakin/convert/dropout.cc | 20 +------- .../inference/anakin/convert/elementwise.cc | 31 +---------- paddle/fluid/inference/anakin/convert/fc.cc | 39 +------------- .../fluid/inference/anakin/convert/flatten.cc | 20 +------- .../inference/anakin/convert/im2sequence.cc | 16 +----- .../inference/anakin/convert/op_converter.h | 50 +++++++++++------- .../fluid/inference/anakin/convert/pool2d.cc | 20 +------- paddle/fluid/inference/anakin/convert/relu.cc | 35 +------------ .../fluid/inference/anakin/convert/reshape.cc | 20 +------- .../inference/anakin/convert/roi_align.cc | 20 +------- .../fluid/inference/anakin/convert/scale.cc | 20 +------- .../fluid/inference/anakin/convert/softmax.cc | 21 +------- .../fluid/inference/anakin/convert/split.cc | 20 +------- paddle/fluid/inference/anakin/convert/sum.cc | 20 +------- .../anakin/convert/test_activation_op.cc | 38 ++++++++++++++ .../inference/anakin/convert/transpose.cc | 16 +----- paddle/fluid/inference/anakin/op_teller.cc | 2 + .../fluid/inference/api/analysis_predictor.cc | 2 + 27 files changed, 127 insertions(+), 491 deletions(-) diff --git a/paddle/fluid/inference/anakin/convert/activation.cc b/paddle/fluid/inference/anakin/convert/activation.cc index 6e52357483d..523571f1aa8 100644 --- a/paddle/fluid/inference/anakin/convert/activation.cc +++ b/paddle/fluid/inference/anakin/convert/activation.cc @@ -43,47 +43,22 @@ void ActivationOpConverter::operator()( auto output_name = op_desc.Output("Out").front(); this->engine_->AddOp(op_name, "Activation", {input_name}, {output_name}); this->engine_->AddOpAttr(op_name, "type", anakin_op_type_); + + if (op_type_ == "swish") { + float beta = boost::get(op_desc.GetAttr("beta")); + this->engine_->AddOpAttr(op_name, "clip_relu_num", beta); + } + if (op_type_ == "relu6") { + float threshold = boost::get(op_desc.GetAttr("threshold")); + this->engine_->AddOpAttr(op_name, "clip_relu_num", threshold); + } } } // namespace anakin } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using sigmoid_nv_fp32 = - ::paddle::inference::anakin::SigmoidOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using sigmoid_nv_int8 = - ::paddle::inference::anakin::SigmoidOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; -using tanh_nv_fp32 = - ::paddle::inference::anakin::TanhOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using tanh_nv_int8 = - ::paddle::inference::anakin::TanhOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; - -REGISTER_CUDA_ANAKIN_OP_CONVERTER(sigmoid, sigmoid_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(sigmoid, sigmoid_nv_int8); -REGISTER_CUDA_ANAKIN_OP_CONVERTER(tanh, tanh_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(tanh, tanh_nv_int8); -#endif - -using sigmoid_cpu_fp32 = - ::paddle::inference::anakin::SigmoidOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using sigmoid_cpu_int8 = - ::paddle::inference::anakin::SigmoidOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; -using tanh_cpu_fp32 = - ::paddle::inference::anakin::TanhOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using tanh_cpu_int8 = - ::paddle::inference::anakin::TanhOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; - -REGISTER_CPU_ANAKIN_OP_CONVERTER(sigmoid, sigmoid_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(sigmoid, sigmoid_cpu_int8); - -REGISTER_CPU_ANAKIN_OP_CONVERTER(tanh, tanh_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(tanh, tanh_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(sigmoid, SigmoidOpConverter); +REGISTER_ANAKIN_OP_CONVERTER(tanh, TanhOpConverter); +REGISTER_ANAKIN_OP_CONVERTER(swish, SwishOpConverter); +REGISTER_ANAKIN_OP_CONVERTER(relu6, Relu6OpConverter); diff --git a/paddle/fluid/inference/anakin/convert/activation.h b/paddle/fluid/inference/anakin/convert/activation.h index 021ec4c7fdf..a2475e492c4 100644 --- a/paddle/fluid/inference/anakin/convert/activation.h +++ b/paddle/fluid/inference/anakin/convert/activation.h @@ -37,7 +37,9 @@ class ActivationOpConverter : public AnakinOpConverter { std::string op_type_; std::string anakin_op_type_; std::map anakin_op_types_{{"tanh", "TanH"}, - {"sigmoid", "Sigmoid"}}; + {"sigmoid", "Sigmoid"}, + {"relu6", "ClippedRelu"}, + {"swish", "Swish"}}; }; template @@ -52,6 +54,19 @@ class SigmoidOpConverter : public ActivationOpConverter { SigmoidOpConverter() : ActivationOpConverter("sigmoid") {} }; + +template +class Relu6OpConverter : public ActivationOpConverter { + public: + Relu6OpConverter() : ActivationOpConverter("relu6") {} +}; + +template +class SwishOpConverter : public ActivationOpConverter { + public: + SwishOpConverter() : ActivationOpConverter("swish") {} +}; + } // namespace anakin } // namespace inference } // namespace paddle diff --git a/paddle/fluid/inference/anakin/convert/affine_channel.cc b/paddle/fluid/inference/anakin/convert/affine_channel.cc index a3abca0a84f..534e7dca81d 100644 --- a/paddle/fluid/inference/anakin/convert/affine_channel.cc +++ b/paddle/fluid/inference/anakin/convert/affine_channel.cc @@ -52,22 +52,4 @@ void AffineChannelOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using affine_channel_nv_fp32 = - ::paddle::inference::anakin::AffineChannelOpConverter< - ::anakin::saber::NV, ::anakin::Precision::FP32>; -using affine_channel_nv_int8 = - ::paddle::inference::anakin::AffineChannelOpConverter< - ::anakin::saber::NV, ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(affine_channel, affine_channel_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(affine_channel, affine_channel_nv_int8); -#endif - -using affine_channel_cpu_fp32 = - ::paddle::inference::anakin::AffineChannelOpConverter< - ::anakin::saber::X86, ::anakin::Precision::FP32>; -using affine_channel_cpu_int8 = - ::paddle::inference::anakin::AffineChannelOpConverter< - ::anakin::saber::X86, ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(affine_channel, affine_channel_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(affine_channel, affine_channel_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(affine_channel, AffineChannelOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/batch_norm.cc b/paddle/fluid/inference/anakin/convert/batch_norm.cc index fa7f3bd79f2..b41f5dc9252 100644 --- a/paddle/fluid/inference/anakin/convert/batch_norm.cc +++ b/paddle/fluid/inference/anakin/convert/batch_norm.cc @@ -82,18 +82,4 @@ void BatchNormOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using bn_nv_fp32 = ::paddle::inference::anakin::BatchNormOpConverter< - ::anakin::saber::NV, ::anakin::Precision::FP32>; -using bn_nv_int8 = ::paddle::inference::anakin::BatchNormOpConverter< - ::anakin::saber::NV, ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(batch_norm, bn_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(batch_norm, bn_nv_int8); -#endif - -using bn_cpu_fp32 = ::paddle::inference::anakin::BatchNormOpConverter< - ::anakin::saber::X86, ::anakin::Precision::FP32>; -using bn_cpu_int8 = ::paddle::inference::anakin::BatchNormOpConverter< - ::anakin::saber::X86, ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(batch_norm, bn_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(batch_norm, bn_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(batch_norm, BatchNormOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/concat.cc b/paddle/fluid/inference/anakin/convert/concat.cc index 6655c2f047a..584a82ead43 100644 --- a/paddle/fluid/inference/anakin/convert/concat.cc +++ b/paddle/fluid/inference/anakin/convert/concat.cc @@ -38,22 +38,4 @@ void ConcatOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using concat_nv_fp32 = - ::paddle::inference::anakin::ConcatOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using concat_nv_int8 = - ::paddle::inference::anakin::ConcatOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(concat, concat_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(concat, concat_nv_int8); - -#endif -using concat_cpu_fp32 = - ::paddle::inference::anakin::ConcatOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using concat_cpu_int8 = - ::paddle::inference::anakin::ConcatOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(concat, concat_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(concat, concat_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(concat, ConcatOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/conv2d.cc b/paddle/fluid/inference/anakin/convert/conv2d.cc index e2ea6290fab..70e0adf5ead 100644 --- a/paddle/fluid/inference/anakin/convert/conv2d.cc +++ b/paddle/fluid/inference/anakin/convert/conv2d.cc @@ -105,22 +105,4 @@ void Conv2dOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using conv2d_nv_fp32 = - ::paddle::inference::anakin::Conv2dOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using conv2d_nv_int8 = - ::paddle::inference::anakin::Conv2dOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(conv2d, conv2d_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(conv2d, conv2d_nv_int8); -#endif - -using conv2d_cpu_fp32 = - ::paddle::inference::anakin::Conv2dOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using conv2d_cpu_int8 = - ::paddle::inference::anakin::Conv2dOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(conv2d, conv2d_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(conv2d, conv2d_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(conv2d, Conv2dOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/conv2d_fusion.cc b/paddle/fluid/inference/anakin/convert/conv2d_fusion.cc index a557c35475d..a1568b8bdee 100644 --- a/paddle/fluid/inference/anakin/convert/conv2d_fusion.cc +++ b/paddle/fluid/inference/anakin/convert/conv2d_fusion.cc @@ -111,22 +111,4 @@ void Conv2dFusionOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using conv2d_fusion_nv_fp32 = - ::paddle::inference::anakin::Conv2dFusionOpConverter< - ::anakin::saber::NV, ::anakin::Precision::FP32>; -using conv2d_fusion_nv_int8 = - ::paddle::inference::anakin::Conv2dFusionOpConverter< - ::anakin::saber::NV, ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(conv2d_fusion, conv2d_fusion_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(conv2d_fusion, conv2d_fusion_nv_int8); -#endif -using conv2d_fusion_cpu_fp32 = - ::paddle::inference::anakin::Conv2dFusionOpConverter< - ::anakin::saber::X86, ::anakin::Precision::FP32>; -using conv2d_fusion_cpu_int8 = - ::paddle::inference::anakin::Conv2dFusionOpConverter< - ::anakin::saber::X86, ::anakin::Precision::INT8>; - -REGISTER_CPU_ANAKIN_OP_CONVERTER(conv2d_fusion, conv2d_fusion_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(conv2d_fusion, conv2d_fusion_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(conv2d_fusion, Conv2dFusionOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/density_prior_box.cc b/paddle/fluid/inference/anakin/convert/density_prior_box.cc index 92d147708bf..5bbaeb57a7d 100644 --- a/paddle/fluid/inference/anakin/convert/density_prior_box.cc +++ b/paddle/fluid/inference/anakin/convert/density_prior_box.cc @@ -108,25 +108,5 @@ void DensityPriorBoxOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using ds_pr_nv_fp32 = ::paddle::inference::anakin::DensityPriorBoxOpConverter< - ::anakin::saber::NV, ::anakin::Precision::FP32>; -using ds_pr_nv_int8 = ::paddle::inference::anakin::DensityPriorBoxOpConverter< - ::anakin::saber::NV, ::anakin::Precision::INT8>; - -REGISTER_CUDA_ANAKIN_OP_CONVERTER(density_prior_box, ds_pr_nv_fp32); -REGISTER_CUDA_ANAKIN_OP_CONVERTER(prior_box, ds_pr_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(density_prior_box, ds_pr_nv_int8); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(prior_box, ds_pr_nv_int8); -#endif - -using ds_pr_cpu_fp32 = ::paddle::inference::anakin::DensityPriorBoxOpConverter< - ::anakin::saber::X86, ::anakin::Precision::FP32>; -using ds_pr_cpu_int8 = ::paddle::inference::anakin::DensityPriorBoxOpConverter< - ::anakin::saber::X86, ::anakin::Precision::INT8>; - -REGISTER_CPU_ANAKIN_OP_CONVERTER(density_prior_box, ds_pr_cpu_fp32); -REGISTER_CPU_ANAKIN_OP_CONVERTER(prior_box, ds_pr_cpu_fp32); - -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(density_prior_box, ds_pr_cpu_int8); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(prior_box, ds_pr_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(density_prior_box, DensityPriorBoxOpConverter); +REGISTER_ANAKIN_OP_CONVERTER(prior_box, DensityPriorBoxOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/detection_out.cc b/paddle/fluid/inference/anakin/convert/detection_out.cc index c06a8860e16..73dd6f28325 100644 --- a/paddle/fluid/inference/anakin/convert/detection_out.cc +++ b/paddle/fluid/inference/anakin/convert/detection_out.cc @@ -66,22 +66,4 @@ void DetectionOutOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using detection_out_nv_fp32 = - ::paddle::inference::anakin::DetectionOutOpConverter< - ::anakin::saber::NV, ::anakin::Precision::FP32>; -using detection_out_nv_int8 = - ::paddle::inference::anakin::DetectionOutOpConverter< - ::anakin::saber::NV, ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(detection_out, detection_out_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(detection_out, detection_out_nv_int8); -#endif - -using detection_out_cpu_fp32 = - ::paddle::inference::anakin::DetectionOutOpConverter< - ::anakin::saber::X86, ::anakin::Precision::FP32>; -using detection_out_cpu_int8 = - ::paddle::inference::anakin::DetectionOutOpConverter< - ::anakin::saber::X86, ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(detection_out, detection_out_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(detection_out, detection_out_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(detection_out, DetectionOutOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/dropout.cc b/paddle/fluid/inference/anakin/convert/dropout.cc index 872ebaba3c0..6c5f80b5f8e 100644 --- a/paddle/fluid/inference/anakin/convert/dropout.cc +++ b/paddle/fluid/inference/anakin/convert/dropout.cc @@ -52,22 +52,4 @@ void DropoutOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using dropout_nv_fp32 = - ::paddle::inference::anakin::DropoutOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using dropout_nv_int8 = - ::paddle::inference::anakin::DropoutOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(dropout, dropout_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(dropout, dropout_nv_int8); -#endif - -using dropout_cpu_fp32 = - ::paddle::inference::anakin::DropoutOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using dropout_cpu_int8 = - ::paddle::inference::anakin::DropoutOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(dropout, dropout_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(dropout, dropout_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(dropout, DropoutOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/elementwise.cc b/paddle/fluid/inference/anakin/convert/elementwise.cc index e3ea6b2a97d..dd32baa0b90 100644 --- a/paddle/fluid/inference/anakin/convert/elementwise.cc +++ b/paddle/fluid/inference/anakin/convert/elementwise.cc @@ -71,32 +71,5 @@ void ElementwiseMulOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using elet_nv_fp32 = ::paddle::inference::anakin::ElementwiseAddOpConverter< - ::anakin::saber::NV, ::anakin::Precision::FP32>; -using elet_nv_int8 = ::paddle::inference::anakin::ElementwiseAddOpConverter< - ::anakin::saber::NV, ::anakin::Precision::INT8>; -using eletmul_nv_fp32 = ::paddle::inference::anakin::ElementwiseMulOpConverter< - ::anakin::saber::NV, ::anakin::Precision::FP32>; -using eletmul_nv_int8 = ::paddle::inference::anakin::ElementwiseMulOpConverter< - ::anakin::saber::NV, ::anakin::Precision::INT8>; - -REGISTER_CUDA_ANAKIN_OP_CONVERTER(elementwise_add, elet_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(elementwise_add, elet_nv_int8); -REGISTER_CUDA_ANAKIN_OP_CONVERTER(elementwise_mul, eletmul_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(elementwise_mul, eletmul_nv_int8); - -#endif -using elet_cpu_fp32 = ::paddle::inference::anakin::ElementwiseAddOpConverter< - ::anakin::saber::X86, ::anakin::Precision::FP32>; -using elet_cpu_int8 = ::paddle::inference::anakin::ElementwiseAddOpConverter< - ::anakin::saber::X86, ::anakin::Precision::INT8>; -using eletmul_cpu_fp32 = ::paddle::inference::anakin::ElementwiseMulOpConverter< - ::anakin::saber::X86, ::anakin::Precision::FP32>; -using eletmul_cpu_int8 = ::paddle::inference::anakin::ElementwiseMulOpConverter< - ::anakin::saber::X86, ::anakin::Precision::INT8>; - -REGISTER_CPU_ANAKIN_OP_CONVERTER(elementwise_add, elet_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(elementwise_add, elet_cpu_int8); -REGISTER_CPU_ANAKIN_OP_CONVERTER(elementwise_mul, eletmul_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(elementwise_mul, eletmul_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(elementwise_add, ElementwiseAddOpConverter); +REGISTER_ANAKIN_OP_CONVERTER(elementwise_mul, ElementwiseMulOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/fc.cc b/paddle/fluid/inference/anakin/convert/fc.cc index 04af3119922..0621e3377b3 100644 --- a/paddle/fluid/inference/anakin/convert/fc.cc +++ b/paddle/fluid/inference/anakin/convert/fc.cc @@ -117,40 +117,5 @@ void FcBaseOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using mul_nv_fp32 = - ::paddle::inference::anakin::MulOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using fc_nv_fp32 = - ::paddle::inference::anakin::FcOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using mul_nv_int8 = - ::paddle::inference::anakin::MulOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; -using fc_nv_int8 = - ::paddle::inference::anakin::FcOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; - -REGISTER_CUDA_ANAKIN_OP_CONVERTER(mul, mul_nv_fp32); -REGISTER_CUDA_ANAKIN_OP_CONVERTER(fc, fc_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(mul, mul_nv_int8); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(fc, fc_nv_int8); -#endif - -using mul_cpu_fp32 = - ::paddle::inference::anakin::MulOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using fc_cpu_fp32 = - ::paddle::inference::anakin::FcOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using mul_cpu_int8 = - ::paddle::inference::anakin::MulOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; -using fc_cpu_int8 = - ::paddle::inference::anakin::FcOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; - -REGISTER_CPU_ANAKIN_OP_CONVERTER(mul, mul_cpu_fp32); -REGISTER_CPU_ANAKIN_OP_CONVERTER(fc, fc_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(mul, mul_cpu_int8); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(fc, fc_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(mul, MulOpConverter); +REGISTER_ANAKIN_OP_CONVERTER(fc, FcOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/flatten.cc b/paddle/fluid/inference/anakin/convert/flatten.cc index 7ef9e11b091..7ce519a4de3 100644 --- a/paddle/fluid/inference/anakin/convert/flatten.cc +++ b/paddle/fluid/inference/anakin/convert/flatten.cc @@ -45,22 +45,4 @@ void FlattenOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using flatten_nv_fp32 = - ::paddle::inference::anakin::FlattenOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using flatten_nv_int8 = - ::paddle::inference::anakin::FlattenOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; - -REGISTER_CUDA_ANAKIN_OP_CONVERTER(flatten, flatten_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(flatten, flatten_nv_int8); -#endif -using flatten_cpu_fp32 = - ::paddle::inference::anakin::FlattenOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using flatten_cpu_int8 = - ::paddle::inference::anakin::FlattenOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(flatten, flatten_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(flatten, flatten_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(flatten, FlattenOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/im2sequence.cc b/paddle/fluid/inference/anakin/convert/im2sequence.cc index 37f3f425a4f..5a4e3e61c5e 100644 --- a/paddle/fluid/inference/anakin/convert/im2sequence.cc +++ b/paddle/fluid/inference/anakin/convert/im2sequence.cc @@ -55,18 +55,4 @@ void Im2SequenceConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using im2sequence_nv_fp32 = ::paddle::inference::anakin::Im2SequenceConverter< - ::anakin::saber::NV, ::anakin::Precision::FP32>; -using im2sequence_nv_int8 = ::paddle::inference::anakin::Im2SequenceConverter< - ::anakin::saber::NV, ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(im2sequence, im2sequence_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(im2sequence, im2sequence_nv_int8); -#endif - -using im2sequence_cpu_fp32 = ::paddle::inference::anakin::Im2SequenceConverter< - ::anakin::saber::X86, ::anakin::Precision::FP32>; -using im2sequence_cpu_int8 = ::paddle::inference::anakin::Im2SequenceConverter< - ::anakin::saber::X86, ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(im2sequence, im2sequence_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(im2sequence, im2sequence_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(im2sequence, Im2SequenceConverter); diff --git a/paddle/fluid/inference/anakin/convert/op_converter.h b/paddle/fluid/inference/anakin/convert/op_converter.h index 6ff49c4a820..a6ae51bd4b1 100644 --- a/paddle/fluid/inference/anakin/convert/op_converter.h +++ b/paddle/fluid/inference/anakin/convert/op_converter.h @@ -183,25 +183,37 @@ template class AnakinOpConverter<::anakin::saber::X86, return 0; \ } -#define REGISTER_CUDA_ANAKIN_OP_CONVERTER(op_type__, Converter__) \ - REGISTER_ANAKIN_OP_CONVERTER_BASE(op_type__, Converter__, CUDA, \ - ::anakin::saber::NV, FP32, \ - ::anakin::Precision::FP32) - -#define REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(op_type__, Converter__) \ - REGISTER_ANAKIN_OP_CONVERTER_BASE(op_type__, Converter__, CUDA, \ - ::anakin::saber::NV, INT8, \ - ::anakin::Precision::INT8) - -#define REGISTER_CPU_ANAKIN_OP_CONVERTER(op_type__, Converter__) \ - REGISTER_ANAKIN_OP_CONVERTER_BASE(op_type__, Converter__, CPU, \ - ::anakin::saber::X86, FP32, \ - ::anakin::Precision::FP32) - -#define REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(op_type__, Converter__) \ - REGISTER_ANAKIN_OP_CONVERTER_BASE(op_type__, Converter__, CPU, \ - ::anakin::saber::X86, INT8, \ - ::anakin::Precision::INT8) +#define WRAP(...) __VA_ARGS__ + +#define REGISTER_CUDA_ANAKIN_OP_CONVERTER(op_type__, Converter__, \ + precision_type__) \ + REGISTER_ANAKIN_OP_CONVERTER_BASE( \ + op_type__, \ + ::paddle::inference::anakin::Converter__, \ + CUDA, ::anakin::saber::NV, precision_type__, \ + ::anakin::Precision::precision_type__) + +#define REGISTER_CPU_ANAKIN_OP_CONVERTER(op_type__, Converter__, \ + precision_type__) \ + REGISTER_ANAKIN_OP_CONVERTER_BASE( \ + op_type__, \ + ::paddle::inference::anakin::Converter__, \ + CPU, ::anakin::saber::X86, precision_type__, \ + ::anakin::Precision::precision_type__) + +#ifdef PADDLE_WITH_CUDA +#define REGISTER_ANAKIN_OP_CONVERTER(op_type__, Converter__) \ + REGISTER_CUDA_ANAKIN_OP_CONVERTER(op_type__, Converter__, FP32); \ + REGISTER_CUDA_ANAKIN_OP_CONVERTER(op_type__, Converter__, INT8); \ + REGISTER_CPU_ANAKIN_OP_CONVERTER(op_type__, Converter__, FP32); \ + REGISTER_CPU_ANAKIN_OP_CONVERTER(op_type__, Converter__, INT8) +#else +#define REGISTER_ANAKIN_OP_CONVERTER(op_type__, Converter__) \ + REGISTER_CPU_ANAKIN_OP_CONVERTER(op_type__, Converter__, FP32); \ + REGISTER_CPU_ANAKIN_OP_CONVERTER(op_type__, Converter__, INT8) +#endif #define USE_ANAKIN_CONVERTER_BASE(op_type__, place_type__, precision_type__) \ extern int Touch_anakin_##op_type__##_##place_type__##_##precision_type__(); \ diff --git a/paddle/fluid/inference/anakin/convert/pool2d.cc b/paddle/fluid/inference/anakin/convert/pool2d.cc index 436741b43b7..11e7c717fd6 100644 --- a/paddle/fluid/inference/anakin/convert/pool2d.cc +++ b/paddle/fluid/inference/anakin/convert/pool2d.cc @@ -71,22 +71,4 @@ void Pool2dOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using pool2d_nv_float32 = - ::paddle::inference::anakin::Pool2dOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using pool2d_nv_int8 = - ::paddle::inference::anakin::Pool2dOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(pool2d, pool2d_nv_float32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(pool2d, pool2d_nv_int8); -#endif - -using pool2d_cpu_float32 = - ::paddle::inference::anakin::Pool2dOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using pool2d_cpu_int8 = - ::paddle::inference::anakin::Pool2dOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(pool2d, pool2d_cpu_float32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(pool2d, pool2d_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(pool2d, Pool2dOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/relu.cc b/paddle/fluid/inference/anakin/convert/relu.cc index 6d456ccfdcd..00853406634 100644 --- a/paddle/fluid/inference/anakin/convert/relu.cc +++ b/paddle/fluid/inference/anakin/convert/relu.cc @@ -57,36 +57,5 @@ void LeakyReluOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using relu_nv_fp32 = - ::paddle::inference::anakin::ReluOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using leaky_nv_fp32 = ::paddle::inference::anakin::LeakyReluOpConverter< - ::anakin::saber::NV, ::anakin::Precision::FP32>; -using relu_nv_int8 = - ::paddle::inference::anakin::ReluOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; -using leaky_nv_int8 = ::paddle::inference::anakin::LeakyReluOpConverter< - ::anakin::saber::NV, ::anakin::Precision::INT8>; - -REGISTER_CUDA_ANAKIN_OP_CONVERTER(relu, relu_nv_fp32); -REGISTER_CUDA_ANAKIN_OP_CONVERTER(leaky_relu, leaky_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(relu, relu_nv_int8); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(leaky_relu, leaky_nv_int8); - -#endif - -using relu_cpu_fp32 = - ::paddle::inference::anakin::ReluOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using leaky_cpu_fp32 = ::paddle::inference::anakin::LeakyReluOpConverter< - ::anakin::saber::X86, ::anakin::Precision::FP32>; -using relu_cpu_int8 = - ::paddle::inference::anakin::ReluOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; -using leaky_cpu_int8 = ::paddle::inference::anakin::LeakyReluOpConverter< - ::anakin::saber::X86, ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(relu, relu_cpu_fp32); -REGISTER_CPU_ANAKIN_OP_CONVERTER(leaky_relu, leaky_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(relu, relu_cpu_int8); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(leaky_relu, leaky_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(relu, ReluOpConverter); +REGISTER_ANAKIN_OP_CONVERTER(leaky_relu, LeakyReluOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/reshape.cc b/paddle/fluid/inference/anakin/convert/reshape.cc index b7b47e30b1c..d73736b7fec 100644 --- a/paddle/fluid/inference/anakin/convert/reshape.cc +++ b/paddle/fluid/inference/anakin/convert/reshape.cc @@ -46,22 +46,4 @@ void ReshapeOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using reshape_nv_fp32 = - ::paddle::inference::anakin::ReshapeOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using reshape_nv_int8 = - ::paddle::inference::anakin::ReshapeOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(reshape, reshape_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(reshape, reshape_nv_int8); -#endif - -using reshape_cpu_fp32 = - ::paddle::inference::anakin::ReshapeOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using reshape_cpu_int8 = - ::paddle::inference::anakin::ReshapeOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(reshape, reshape_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(reshape, reshape_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(reshape, ReshapeOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/roi_align.cc b/paddle/fluid/inference/anakin/convert/roi_align.cc index 68d3bffd89d..8702f638e10 100644 --- a/paddle/fluid/inference/anakin/convert/roi_align.cc +++ b/paddle/fluid/inference/anakin/convert/roi_align.cc @@ -51,22 +51,4 @@ void RoiAlignOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using roi_align_nv_fp32 = - ::paddle::inference::anakin::RoiAlignOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using roi_align_nv_int8 = - ::paddle::inference::anakin::RoiAlignOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(roi_align, roi_align_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(roi_align, roi_align_nv_int8); -#endif - -using roi_align_cpu_fp32 = - ::paddle::inference::anakin::RoiAlignOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using roi_align_cpu_int8 = - ::paddle::inference::anakin::RoiAlignOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(roi_align, roi_align_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(roi_align, roi_align_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(roi_align, RoiAlignOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/scale.cc b/paddle/fluid/inference/anakin/convert/scale.cc index cdfdf86a974..2559ec498c8 100644 --- a/paddle/fluid/inference/anakin/convert/scale.cc +++ b/paddle/fluid/inference/anakin/convert/scale.cc @@ -49,22 +49,4 @@ void ScaleOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using scale_nv_fp32 = - ::paddle::inference::anakin::ScaleOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using scale_nv_int8 = - ::paddle::inference::anakin::ScaleOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(scale, scale_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(scale, scale_nv_int8); -#endif - -using scale_cpu_fp32 = - ::paddle::inference::anakin::ScaleOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using scale_cpu_int8 = - ::paddle::inference::anakin::ScaleOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(scale, scale_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(scale, scale_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(scale, ScaleOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/softmax.cc b/paddle/fluid/inference/anakin/convert/softmax.cc index eb50e17e55f..a4dc5a9156b 100644 --- a/paddle/fluid/inference/anakin/convert/softmax.cc +++ b/paddle/fluid/inference/anakin/convert/softmax.cc @@ -44,23 +44,4 @@ void SoftMaxOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using sm_nv_fp32 = - ::paddle::inference::anakin::SoftMaxOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using sm_nv_int8 = - ::paddle::inference::anakin::SoftMaxOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; - -REGISTER_CUDA_ANAKIN_OP_CONVERTER(softmax, sm_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(softmax, sm_nv_int8); -#endif - -using sm_cpu_fp32 = - ::paddle::inference::anakin::SoftMaxOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using sm_cpu_int8 = - ::paddle::inference::anakin::SoftMaxOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(softmax, sm_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(softmax, sm_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(softmax, SoftMaxOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/split.cc b/paddle/fluid/inference/anakin/convert/split.cc index b84860220fb..e63edea94ae 100644 --- a/paddle/fluid/inference/anakin/convert/split.cc +++ b/paddle/fluid/inference/anakin/convert/split.cc @@ -55,23 +55,5 @@ void SplitOpConverter::operator()( } // namespace anakin } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using split_nv_fp32 = - ::paddle::inference::anakin::SplitOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using split_nv_int8 = - ::paddle::inference::anakin::SplitOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(split, split_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(split, split_nv_int8); -#endif -using split_cpu_fp32 = - ::paddle::inference::anakin::SplitOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using split_cpu_int8 = - ::paddle::inference::anakin::SplitOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; - -REGISTER_CPU_ANAKIN_OP_CONVERTER(split, split_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(split, split_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(split, SplitOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/sum.cc b/paddle/fluid/inference/anakin/convert/sum.cc index 2bc4d124c90..870c0793409 100644 --- a/paddle/fluid/inference/anakin/convert/sum.cc +++ b/paddle/fluid/inference/anakin/convert/sum.cc @@ -47,22 +47,4 @@ void SumOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using sum_nv_fp32 = - ::paddle::inference::anakin::SumOpConverter<::anakin::saber::NV, - ::anakin::Precision::FP32>; -using sum_nv_int8 = - ::paddle::inference::anakin::SumOpConverter<::anakin::saber::NV, - ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(sum, sum_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(sum, sum_nv_int8); -#endif - -using sum_cpu_fp32 = - ::paddle::inference::anakin::SumOpConverter<::anakin::saber::X86, - ::anakin::Precision::FP32>; -using sum_cpu_int8 = - ::paddle::inference::anakin::SumOpConverter<::anakin::saber::X86, - ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(sum, sum_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(sum, sum_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(sum, SumOpConverter); diff --git a/paddle/fluid/inference/anakin/convert/test_activation_op.cc b/paddle/fluid/inference/anakin/convert/test_activation_op.cc index 67d3222d985..4f898252d27 100644 --- a/paddle/fluid/inference/anakin/convert/test_activation_op.cc +++ b/paddle/fluid/inference/anakin/convert/test_activation_op.cc @@ -36,6 +36,14 @@ static void test_activation_op(const std::string& op_type, desc.SetInput("X", {"act-X"}); desc.SetOutput("Out", {"act-Out"}); + if (op_type == "swish") { + desc.SetAttr("beta", 1.0f); + } + + if (op_type == "relu6") { + desc.SetAttr("threshold", 6.0f); + } + LOG(INFO) << "set OP"; validator.SetOp(*desc.Proto()); LOG(INFO) << "execute"; @@ -55,6 +63,18 @@ TEST(tanh_op, gpu) { platform::CUDADeviceContext ctx(gpu_place); test_activation_op<::anakin::saber::NV>("tanh", ctx, true); } + +TEST(relu6_op, gpu) { + platform::CUDAPlace gpu_place(0); + platform::CUDADeviceContext ctx(gpu_place); + test_activation_op<::anakin::saber::NV>("relu6", ctx, true); +} + +TEST(swish_op, gpu) { + platform::CUDAPlace gpu_place(0); + platform::CUDADeviceContext ctx(gpu_place); + test_activation_op<::anakin::saber::NV>("swish", ctx, true); +} #endif /* @@ -69,6 +89,18 @@ TEST(tanh_op, cpu) { platform::CPUDeviceContext ctx(cpu_place); test_activation_op<::anakin::saber::X86>("tanh", ctx, false); } + +TEST(relu6_op, cpu) { + platform::CPUPlace cpu_place; + platform::CPUDeviceContext ctx(cpu_place); + test_activation_op<::anakin::saber::X86>("relu6", ctx, false); +} + +TEST(swish_op, cpu) { + platform::CPUPlace cpu_place; + platform::CPUDeviceContext ctx(cpu_place); + test_activation_op<::anakin::saber::X86>("swish", ctx, false); +} */ } // namespace anakin @@ -77,10 +109,16 @@ TEST(tanh_op, cpu) { USE_OP(sigmoid); USE_OP(tanh); +USE_OP(relu6); +USE_OP(swish); USE_CPU_ANAKIN_CONVERTER(sigmoid); USE_CPU_ANAKIN_CONVERTER(tanh); +USE_CPU_ANAKIN_CONVERTER(relu6); +USE_CPU_ANAKIN_CONVERTER(swish); #ifdef PADDLE_WITH_CUDA USE_ANAKIN_CONVERTER(sigmoid); USE_ANAKIN_CONVERTER(tanh); +USE_ANAKIN_CONVERTER(relu6); +USE_ANAKIN_CONVERTER(swish); #endif diff --git a/paddle/fluid/inference/anakin/convert/transpose.cc b/paddle/fluid/inference/anakin/convert/transpose.cc index 849bfc9ea3e..28071ca8449 100644 --- a/paddle/fluid/inference/anakin/convert/transpose.cc +++ b/paddle/fluid/inference/anakin/convert/transpose.cc @@ -49,18 +49,4 @@ void TransposeOpConverter::operator()( } // namespace inference } // namespace paddle -#ifdef PADDLE_WITH_CUDA -using transpose_nv_fp32 = ::paddle::inference::anakin::TransposeOpConverter< - ::anakin::saber::NV, ::anakin::Precision::FP32>; -using transpose_nv_int8 = ::paddle::inference::anakin::TransposeOpConverter< - ::anakin::saber::NV, ::anakin::Precision::INT8>; -REGISTER_CUDA_ANAKIN_OP_CONVERTER(transpose, transpose_nv_fp32); -REGISTER_CUDA_INT8_ANAKIN_OP_CONVERTER(transpose, transpose_nv_int8); -#endif - -using transpose_cpu_fp32 = ::paddle::inference::anakin::TransposeOpConverter< - ::anakin::saber::X86, ::anakin::Precision::FP32>; -using transpose_cpu_int8 = ::paddle::inference::anakin::TransposeOpConverter< - ::anakin::saber::X86, ::anakin::Precision::INT8>; -REGISTER_CPU_ANAKIN_OP_CONVERTER(transpose, transpose_cpu_fp32); -REGISTER_CPU_INT8_ANAKIN_OP_CONVERTER(transpose, transpose_cpu_int8); +REGISTER_ANAKIN_OP_CONVERTER(transpose, TransposeOpConverter); diff --git a/paddle/fluid/inference/anakin/op_teller.cc b/paddle/fluid/inference/anakin/op_teller.cc index 72064c1790d..6cad00f8ecf 100644 --- a/paddle/fluid/inference/anakin/op_teller.cc +++ b/paddle/fluid/inference/anakin/op_teller.cc @@ -46,6 +46,8 @@ struct SimpleOpTypeSetTeller : public Teller { teller_set.insert("prior_box"); teller_set.insert("leaky_relu"); teller_set.insert("affine_channel"); + teller_set.insert("relu6"); + teller_set.insert("swish"); } bool operator()(const std::string& op_type, diff --git a/paddle/fluid/inference/api/analysis_predictor.cc b/paddle/fluid/inference/api/analysis_predictor.cc index e1709fe2e67..7552a576a65 100644 --- a/paddle/fluid/inference/api/analysis_predictor.cc +++ b/paddle/fluid/inference/api/analysis_predictor.cc @@ -893,4 +893,6 @@ USE_ANAKIN_CONVERTER(sum); USE_ANAKIN_CONVERTER(prior_box); USE_ANAKIN_CONVERTER(leaky_relu); USE_ANAKIN_CONVERTER(affine_channel); +USE_ANAKIN_CONVERTER(relu6); +USE_ANAKIN_CONVERTER(swish); #endif -- GitLab