From 8f85fdfb77a98bc944523c43653fe78da9c2862d Mon Sep 17 00:00:00 2001 From: Jacek Czaja Date: Fri, 11 Feb 2022 18:52:08 +0100 Subject: [PATCH] - changes to UT testing onednn verbose --- .../tests/unittests/mkldnn/test_flags_mkldnn_ops_on_off.py | 6 +++--- .../fluid/tests/unittests/mkldnn/test_flags_use_mkldnn.py | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/python/paddle/fluid/tests/unittests/mkldnn/test_flags_mkldnn_ops_on_off.py b/python/paddle/fluid/tests/unittests/mkldnn/test_flags_mkldnn_ops_on_off.py index 084053acb8c..4e52b7b08cf 100644 --- a/python/paddle/fluid/tests/unittests/mkldnn/test_flags_mkldnn_ops_on_off.py +++ b/python/paddle/fluid/tests/unittests/mkldnn/test_flags_mkldnn_ops_on_off.py @@ -31,9 +31,9 @@ class TestFlagsUseMkldnn(unittest.TestCase): self.env[str("DNNL_VERBOSE")] = str("1") self.env[str("FLAGS_use_mkldnn")] = str("1") - self.relu_regex = b"^dnnl_verbose,exec,cpu,eltwise,.+alg:eltwise_relu alpha:0 beta:0,10x20x20" - self.ew_add_regex = b"^dnnl_verbose,exec,cpu,binary.+alg:binary_add,10x20x30:10x20x30" - self.matmul_regex = b"^dnnl_verbose,exec,cpu,matmul,.*10x20x30:10x30x20:10x20x20" + self.relu_regex = b"^onednn_verbose,exec,cpu,eltwise,.+alg:eltwise_relu alpha:0 beta:0,10x20x20" + self.ew_add_regex = b"^onednn_verbose,exec,cpu,binary.+alg:binary_add,10x20x30:10x20x30" + self.matmul_regex = b"^onednn_verbose,exec,cpu,matmul,.*10x20x30:10x30x20:10x20x20" def flags_use_mkl_dnn_common(self, e): cmd = self._python_interp diff --git a/python/paddle/fluid/tests/unittests/mkldnn/test_flags_use_mkldnn.py b/python/paddle/fluid/tests/unittests/mkldnn/test_flags_use_mkldnn.py index 3593c54a7f4..0974d6357fc 100644 --- a/python/paddle/fluid/tests/unittests/mkldnn/test_flags_use_mkldnn.py +++ b/python/paddle/fluid/tests/unittests/mkldnn/test_flags_use_mkldnn.py @@ -32,7 +32,7 @@ class TestFlagsUseMkldnn(unittest.TestCase): self.env[str("DNNL_VERBOSE")] = str("1") self.env[str("FLAGS_use_mkldnn")] = str("1") - self.relu_regex = b"^dnnl_verbose,exec,cpu,eltwise,.+alg:eltwise_relu alpha:0 beta:0,10x20x30" + self.relu_regex = b"^onednn_verbose,exec,cpu,eltwise,.+alg:eltwise_relu alpha:0 beta:0,10x20x30" def _print_when_false(self, cond, out, err): if not cond: -- GitLab