合并请求 · PaddlePaddle / Paddle-Lite

marker1-anchor update for FPGA V1 track

!1652 · opened 5月 22, 2019 by saxon_zh
- 已合并
- 0
更新于5月 22, 2019
fix cpu conv_add and conv_add_relu

!1654 · opened 5月 22, 2019 by saxon_zh
- 已合并
- 0
更新于5月 22, 2019
1. add optimize parameter to load function. 2. add transpose operatio…

!1651 · opened 5月 22, 2019 by saxon_zh
- 已合并
- 0
更新于5月 22, 2019
delete test commit, open openmp switch

!1650 · opened 5月 22, 2019 by saxon_zh
- 已合并
- 0
更新于5月 22, 2019
develop nearestinterp op fix bug in element add close #1647

!1648 · opened 5月 22, 2019 by saxon_zh
- 已合并
- 0
更新于5月 22, 2019
1. reshape output transpose should be 0, 1, 2, 3. 2.mps conv should b…

!1646 · opened 5月 22, 2019 by saxon_zh
- 已合并
- 0
更新于5月 22, 2019
add opencl Scale op

!1645 · opened 5月 22, 2019 by saxon_zh
- 已合并
- 0
更新于5月 22, 2019
1.add groups to conv3x3. 2.add original size to tensor and tenture an…

!1643 · opened 5月 21, 2019 by saxon_zh
- 已合并
- 0
更新于5月 21, 2019
Add leakyrelu arm cpu op close #1636

!1638 · opened 5月 21, 2019 by saxon_zh
- 已合并
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更新于5月 21, 2019
method to adjust texture transpose

!1642 · opened 5月 21, 2019 by saxon_zh
- 已合并
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更新于5月 21, 2019
add name protection for protobuf-c

!1641 · opened 5月 21, 2019 by saxon_zh
- 已合并
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更新于5月 21, 2019
1.check slice and nearest op result. 2.reshape output should have sam…

!1640 · opened 5月 21, 2019 by saxon_zh
- 已合并
- 0
更新于5月 21, 2019
opendevice bug fixed for FPGA V1 track

!1635 · opened 5月 20, 2019 by saxon_zh
- 已合并
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更新于5月 21, 2019
1.add flatten2, slice and nearest_interp op. 2.truncate tensor with m…

!1634 · opened 5月 20, 2019 by saxon_zh
- 已合并
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更新于5月 20, 2019
add exp, sigmoid and leaky_relu op

!1633 · opened 5月 20, 2019 by saxon_zh
- 已合并
- 0
更新于5月 20, 2019
1.parse tensor desc info from params file. 2.ensure tensor desc is co…

!1631 · opened 5月 18, 2019 by saxon_zh
- 已合并
- 0
更新于5月 18, 2019
fix memcpy size in opencl fetch kernel

!1630 · opened 5月 17, 2019 by saxon_zh
- 已合并
- 0
更新于5月 17, 2019
add notice for android gpu doc

!1627 · opened 5月 16, 2019 by saxon_zh
- 已合并
- 0
更新于5月 17, 2019
add reshape2, transpose2, relu6 and scale operator

!1628 · opened 5月 16, 2019 by saxon_zh
- 已合并
- 0
更新于5月 16, 2019
V1-dwconv relu bug for FPGA track

!1624 · opened 5月 15, 2019 by saxon_zh
- 已合并
- 0
更新于5月 16, 2019