[mobile][opencl] make model attr support issue more readable ,fastfail before cxxlib err ,test=mobile (#2697)

* [mobile][opencl]optimise log print , ues kNOLOG to close develop time logs ,test=mobile

* [mobile][opencl]optimise log print , ues kNOLOG to close develop time logs ,test=mobile

* [mobile][opencl]common deepwise conv,test=mobile

* [mobile][opencl]revert deepwise 3x3 for stable ,test = mobile

* [mobile][opencl]format convkernel.inc.cl with clang-format ,test = mobile

* [mobile][opencl] suite 1*X Y element_y ,test=mobile

* [mobile][opencl] add whole print method for cl_image ,test=mobile

[Mobile][ARM]Fix memory leaks when using input tensor created with external pointer in lod_mode. (#2681)

* [mobile] fix part package , opt log ,test=mobile

* fix code style ,test=mobile

* [mobile]code style ,test=mobile

* fix code style ,test=mobile

* [mobile]Add multi input interface in inference api.

* [Mobile]Open switch of mobile/test/CMakeLists.txt to build all test.

* [Mobile]Fix ci compile error.

* [Mobile]Change test_inference_api_v2 to test multi input and output.

* suite scale in nearest_interp_op ,test=mobile

* suite scale in nearest_interp_op && fix grid_sampler_kernel.cl ,test=mobile

* suite scale in nearest_interp_op && fix grid_sampler_kernel.cl && fix code style ,test=mobile

* develop expend op for erciyuan ,test=mobile

* develop expend op for erciyuan && code style ,test=mobile

* fix 1x1_wrapped crashed in huawei && reinit super image  . test = develop

* fix 1x1_wrapped crashed in huawei && reinit super image  . test = mobile

* update proposal and psroipool kernel file in FPGA V2 track

* update, test=develop

* update FPGA v2 pe cpp file and ew kernel files, test=develop

* fix a bug of sigmoid kernel in FPGA v2 track, test=develop

* fix bugs of concat, reshape and slice op and add usleep in fpga regpoll, test=develop

* add interupt clear operation before op compute in FPGA V2 track, test=develop

* fix a bug in ewadd in FPGA v2, test=mobile

fix bugs of concat, reshape and slice op and add usleep in fpga regpoll, test=develop，  close #2501 (#2502)

* update proposal and psroipool kernel file in FPGA V2 track

* update, test=develop

* update FPGA v2 pe cpp file and ew kernel files, test=develop

* fix a bug of sigmoid kernel in FPGA v2 track, test=develop

* fix bugs of concat, reshape and slice op and add usleep in fpga regpoll, test=develop

* add interupt clear operation before op compute in FPGA V2 track, test=develop

* fix “CL_INVALID_KERNEL_ARGS ” error， test=develop

* fix height = 1 error in superresolution model, test=develop

* fix error

* update proposal and psroipool kernel file in FPGA V2 track

* update, test=develop

* update FPGA v2 pe cpp file and ew kernel files, test=develop

* fix a bug of sigmoid kernel in FPGA v2 track, test=develop

* update proposal and psroipool kernel file in FPGA V2 track

* update, test=develop

* update FPGA v2 pe cpp file and ew kernel files, test=develop

optimise conv 1x1 ... ,test=develop (#2388)

update FPGA v2 kernel file including proposal， sigmoid and anchor generator, test=develop  Closes #2369 (#2370)

* update proposal and psroipool kernel file in FPGA V2 track

* update, test=develop

* add mem opt option for high api ,test = develop

* fix is_lod params && test-performance ,test=develop

* fix useless init emptyimage , test = develop

* add mem opt option for high api ,test = develop

* fix is_lod params && test-performance ,test=develop

* add GPU_CL for test_net_benchmark.

* test compile

* fix mobile build error

1. improve n-fold quantification algorithm by introducing a minimal size for each fold. 2. automatically search for best n for n-fold algorithm. (#2167)

* 1. add quantification_fold parameter. 2. support quantification test in run.py.

* implement n-fold quantification

* open cl mem optimise, split with cpu codes.
fix a bug when some memory is not equal 4 .

* open cl mem optimise, split with cpu codes.   fix a bug when some memory is not equal 4  fix bad des