Implement sequence_expand, sequence_pool, sequence_softmax and tanh op for CPU

Optimize int8/float 5x5 depthwise conv and 2x2 pooling, add aarch64 macros to make compilation no problem

Avoid memory leakage for FPGA track, close #1372

add dwconv compute function in FPGA and update some other files fixed#1368

modify ios interface

add fpga dwconv and reshape op and refactor code of fpga conv and dec… fixed#1366

reduce memory during initialization for FPGA track close #1364