diff --git a/src/fpga/api.cpp b/src/fpga/api.cpp
index 11b26fe6893dc24664b563f5a2212fae77926d5e..9d33c742e3a4bc76d1f2766a8b5476579ace2789 100644
--- a/src/fpga/api.cpp
+++ b/src/fpga/api.cpp
@@ -86,14 +86,14 @@ void fpga_copy(void *dest, const void *src, size_t num) {
 }
 
 int fpga_flush(void *address, size_t size) {
-  struct MemoryCacheArgs args;
+  struct MemoryCacheArgs args = {nullptr};
   args.address = address;
   args.size = size;
   return do_ioctl(IOCTL_MEMCACHE_FLUSH, &args);
 }
 
 int fpga_invalidate(void *address, size_t size) {
-  struct MemoryCacheArgs args;
+  struct MemoryCacheArgs args = {nullptr};
   args.address = address;
   args.size = size;
   return do_ioctl(IOCTL_MEMCACHE_INVAL, &args);
@@ -332,7 +332,7 @@ void format_concat_output(framework::Tensor *out, int height, int width,
 
   sum_cw = align_to_x(width * sum_channel, IMAGE_ALIGNMENT);
   auto data_ptr = fpga_malloc(height * sum_cw * sizeof(half));
-  auto ddim = framework::make_ddim({-1, sum_channel, height, width});
+  auto ddim = framework::make_ddim({1, sum_channel, height, width});
   out->Resize(ddim);
   out->reset_data_ptr(data_ptr);
 }
diff --git a/src/fpga/image.cpp b/src/fpga/image.cpp
index 0603d164dfa88eb5620ebf588c610ea25a78be5f..ad5053f9780895d94cc3095dc694e86dbbb1abac 100644
--- a/src/fpga/image.cpp
+++ b/src/fpga/image.cpp
@@ -74,15 +74,17 @@ void concat_images(int16_t **images_in, float **scales_in, void *image_out,
   int align_each_in_area_cw = 0;
   int align_each_out_area_cw_differ = 0;
   int tmp_channel = 0;
-  *scale_out = 0;
+  scale_out[0] = 0.0;
+  scale_out[1] = 0.0;
   for (i = 0; i < image_num; i++) {
     each_out_line_channel += channel_num[i];
-    *scale_out = std::max(*scale_out, scales_in[i][0]);
+    scale_out[0] = std::max(*scale_out, scales_in[i][0]);
     fpga_invalidate(images_in[i],
                     height *
                         align_to_x(channel_num[i] * width, IMAGE_ALIGNMENT) *
                         sizeof(int16_t));
   }
+  scale_out[1] = 1 / scale_out[0];
   align_each_out_area_cw =
       align_to_x(each_out_line_channel * width, IMAGE_ALIGNMENT);
   align_each_out_area_cw_differ =
diff --git a/src/operators/feed_op.h b/src/operators/feed_op.h
index b0585d5e8377fbd4a9bef46a9637c608b3ca4e37..2cc7fda7f8a6bb6f6856a937b9e14ab9792224e1 100644
--- a/src/operators/feed_op.h
+++ b/src/operators/feed_op.h
@@ -55,7 +55,7 @@ class FeedOp : public framework::OperatorBase<DeviceType> {
     Tensor *output = param_.Out();
     auto output_ptr = output->data<half>();
 
-    fpga::BypassArgs args;
+    fpga::BypassArgs args = {fpga::DATA_TYPE_FP32};
 
     args.input_data_type = fpga::DATA_TYPE_FP32;
     args.output_data_type = fpga::DATA_TYPE_FP16;
diff --git a/src/operators/kernel/fpga/concat_kernel.cpp b/src/operators/kernel/fpga/concat_kernel.cpp
index 9de1511746f70c225e2d978a43b43cb34ad9143f..86da2833ed6e1443707054896127e87c0ca297b9 100644
--- a/src/operators/kernel/fpga/concat_kernel.cpp
+++ b/src/operators/kernel/fpga/concat_kernel.cpp
@@ -43,7 +43,7 @@ bool ConcatKernel<FPGA, float>::Init(ConcatParam<FPGA> *param) {
   fpga::format_concat_output(out, (int)height, (int)width, (int)image_num,
                              channel_num);
 
-  fpga::ConcatArgs concatArgs;
+  fpga::ConcatArgs concatArgs = {0};
   concatArgs.image_num = (uint32_t)image_num;
   concatArgs.images_in = images_in;
   concatArgs.scales_in = scales_in;
diff --git a/src/operators/kernel/fpga/conv_add_bn_kernel.cpp b/src/operators/kernel/fpga/conv_add_bn_kernel.cpp
index 21a03bcc3aca243ce3f66bcda6119b63a742560a..671df76967b4537d111695cdbe091b9c7de2c5a2 100644
--- a/src/operators/kernel/fpga/conv_add_bn_kernel.cpp
+++ b/src/operators/kernel/fpga/conv_add_bn_kernel.cpp
@@ -66,7 +66,7 @@ bool ConvAddBNKernel<FPGA, float>::Init(FusionConvAddBNParam<FPGA> *param) {
   fpga::format_bias_scale_array(&bs_ptr, element_num_per_div, channel);
   fpga::format_fp16_ofm(out);
 
-  fpga::WrapperConvArgs conv_arg;
+  fpga::WrapperConvArgs conv_arg = {0};
   fpga::fill_conv_arg(&conv_arg, input, out, filter, relu_enabled,
                       param->Groups(), param->Strides()[0], param->Strides()[1],
                       param->Paddings()[0], param->Paddings()[1], bs_ptr);
diff --git a/src/operators/kernel/fpga/conv_add_bn_relu_kernel.cpp b/src/operators/kernel/fpga/conv_add_bn_relu_kernel.cpp
index 749e61f45d2865b7dd87be44339a4336a987f636..d435692db6b40568afc599733c2adb6b05b00ffa 100644
--- a/src/operators/kernel/fpga/conv_add_bn_relu_kernel.cpp
+++ b/src/operators/kernel/fpga/conv_add_bn_relu_kernel.cpp
@@ -64,7 +64,7 @@ bool ConvAddBNReluKernel<FPGA, float>::Init(
 
   fpga::format_fp16_ofm(out);
 
-  fpga::WrapperConvArgs conv_arg;
+  fpga::WrapperConvArgs conv_arg = {0};
   fpga::fill_conv_arg(&conv_arg, input, out, filter, relu_enabled,
                       param->Groups(), param->Strides()[0], param->Strides()[1],
                       param->Paddings()[0], param->Paddings()[1], bs_ptr);
diff --git a/src/operators/kernel/fpga/conv_add_relu_kernel.cpp b/src/operators/kernel/fpga/conv_add_relu_kernel.cpp
index 2570b80857d8b1d0c98828e0197ffe37afcf749f..32d90b36e4c14a60219a3779da03100651aa2f13 100644
--- a/src/operators/kernel/fpga/conv_add_relu_kernel.cpp
+++ b/src/operators/kernel/fpga/conv_add_relu_kernel.cpp
@@ -46,7 +46,7 @@ bool ConvAddReluKernel<FPGA, float>::Init(FusionConvAddReluParam<FPGA> *param) {
 
   fpga::format_fp16_ofm(out);
 
-  fpga::WrapperConvArgs conv_arg;
+  fpga::WrapperConvArgs conv_arg = {0};
   fpga::fill_conv_arg(&conv_arg, input, out, filter, relu_enabled,
                       param->Groups(), param->Strides()[0], param->Strides()[1],
                       param->Paddings()[0], param->Paddings()[1], bs_ptr);
diff --git a/src/operators/kernel/fpga/conv_bn_kernel.cpp b/src/operators/kernel/fpga/conv_bn_kernel.cpp
index 34954fd6d4a573321ef34b5c09567d90b4fc9022..4263c9c40491366813d3c9a5bf7dbc8ae976d39e 100644
--- a/src/operators/kernel/fpga/conv_bn_kernel.cpp
+++ b/src/operators/kernel/fpga/conv_bn_kernel.cpp
@@ -58,7 +58,7 @@ bool ConvBNKernel<FPGA, float>::Init(FusionConvBNParam<FPGA> *param) {
 
   fpga::format_fp16_ofm(out);
 
-  fpga::WrapperConvArgs conv_arg;
+  fpga::WrapperConvArgs conv_arg = {0};
   fpga::fill_conv_arg(&conv_arg, input, out, filter, relu_enabled,
                       param->Groups(), param->Strides()[0], param->Strides()[1],
                       param->Paddings()[0], param->Paddings()[1], bs_ptr);
diff --git a/src/operators/kernel/fpga/conv_bn_relu_kernel.cpp b/src/operators/kernel/fpga/conv_bn_relu_kernel.cpp
index 04d6892e3f4e526a5baa13cd86f8b2a4fe1de176..3d6e0faa5fe3d4ef3514bbe1679298b11d96727c 100644
--- a/src/operators/kernel/fpga/conv_bn_relu_kernel.cpp
+++ b/src/operators/kernel/fpga/conv_bn_relu_kernel.cpp
@@ -58,7 +58,7 @@ bool ConvBNReluKernel<FPGA, float>::Init(FusionConvBNReluParam<FPGA> *param) {
 
   fpga::format_fp16_ofm(out);
 
-  fpga::WrapperConvArgs conv_arg;
+  fpga::WrapperConvArgs conv_arg = {0};
   fpga::fill_conv_arg(&conv_arg, input, out, filter, relu_enabled,
                       param->Groups(), param->Strides()[0], param->Strides()[1],
                       param->Paddings()[0], param->Paddings()[1], bs_ptr);
diff --git a/src/operators/kernel/fpga/elementwise_add_relu_kernel.cpp b/src/operators/kernel/fpga/elementwise_add_relu_kernel.cpp
index a3314c1b2c2c3a3a79e582fe4c79d34f6eb5b47c..f0d8533641941fe43a6d06b49266ac06646a7b4d 100644
--- a/src/operators/kernel/fpga/elementwise_add_relu_kernel.cpp
+++ b/src/operators/kernel/fpga/elementwise_add_relu_kernel.cpp
@@ -30,7 +30,7 @@ bool ElementwiseAddReluKernel<FPGA, float>::Init(
   fpga::format_fp16_ofm(out);
   auto out_ptr = out->mutable_data<float>();
 
-  fpga::EWAddArgs ewaddArgs;
+  fpga::EWAddArgs ewaddArgs = {0};
   ewaddArgs.relu_enabled = relu_enabled;
   ewaddArgs.const0 = 1;
   ewaddArgs.const1 = 1;
diff --git a/src/operators/kernel/fpga/fc_relu_kernel.cpp b/src/operators/kernel/fpga/fc_relu_kernel.cpp
index 64aa255ff2308c91a71c6e6f018d2ba435f243df..38b39f982ce41c7d5a88b82f21e446b05c859a2c 100644
--- a/src/operators/kernel/fpga/fc_relu_kernel.cpp
+++ b/src/operators/kernel/fpga/fc_relu_kernel.cpp
@@ -51,7 +51,7 @@ bool FusionFcReluKernel<FPGA, float>::Init(FusionFcReluParam<FPGA> *param) {
   fpga::format_bias_scale_array(&bs_ptr, element_num_per_div, channel);
   fpga::format_fp16_ofm(out);
 
-  fpga::WrapperConvArgs conv_arg;
+  fpga::WrapperConvArgs conv_arg = {0};
   fpga::fill_conv_arg(&conv_arg, input_x, out, filter, relu_enabled, 1, 1, 1, 0,
                       0, bs_ptr);
   param->SetFpgaArgs(conv_arg);
diff --git a/src/operators/kernel/fpga/fusion_fc_kernel.cpp b/src/operators/kernel/fpga/fusion_fc_kernel.cpp
index 5930f3d4115a469a9e5515b007be090de7d0219c..6dee8ea6a7e1b26bec4ffd3ed324db4a4ac3be2d 100644
--- a/src/operators/kernel/fpga/fusion_fc_kernel.cpp
+++ b/src/operators/kernel/fpga/fusion_fc_kernel.cpp
@@ -52,7 +52,7 @@ bool FusionFcKernel<FPGA, float>::Init(FusionFcParam<FPGA> *param) {
   fpga::format_bias_scale_array(&bs_ptr, element_num_per_div, channel);
   fpga::format_fp16_ofm(out);
 
-  fpga::WrapperConvArgs conv_arg;
+  fpga::WrapperConvArgs conv_arg = {0};
   fpga::fill_conv_arg(&conv_arg, input_x, out, filter, relu_enabled, 1, 1, 1, 0,
                       0, bs_ptr);
   param->SetFpgaArgs(conv_arg);
diff --git a/src/operators/kernel/fpga/pool_kernel.cpp b/src/operators/kernel/fpga/pool_kernel.cpp
index 96599f3059f45fc8163e979da613360ab2f8c298..4dad2f789baeb6e381c66ed861b8a8360fa2996e 100644
--- a/src/operators/kernel/fpga/pool_kernel.cpp
+++ b/src/operators/kernel/fpga/pool_kernel.cpp
@@ -30,7 +30,7 @@ bool PoolKernel<FPGA, float>::Init(PoolParam<FPGA> *param) {
   vector<int> strides = param->Strides();
   vector<int> paddings = param->Paddings();
 
-  fpga::PoolingArgs poolArgs;
+  fpga::PoolingArgs poolArgs = {0};
   poolArgs.image.address = input_ptr;
   poolArgs.image.channels = (uint32_t)input->dims()[1];
   poolArgs.image.height = (uint32_t)input->dims()[2];
diff --git a/src/operators/kernel/fpga/softmax_kernel.cpp b/src/operators/kernel/fpga/softmax_kernel.cpp
index 0bc874c570248533447521d746dc653fc0e17114..79f1453fc8e77e35b52a5617064c164d93aa9207 100644
--- a/src/operators/kernel/fpga/softmax_kernel.cpp
+++ b/src/operators/kernel/fpga/softmax_kernel.cpp
@@ -29,7 +29,7 @@ bool SoftmaxKernel<FPGA, float>::Init(SoftmaxParam<FPGA> *param) {
   auto float_input = new Tensor(*input);
   fpga::format_fp32_ofm(float_input);
 
-  fpga::BypassArgs args;
+  fpga::BypassArgs args = {fpga::DATA_TYPE_FP16};
   args.input_layout_type = fpga::LAYOUT_HWC;
   args.output_layout_type = fpga::LAYOUT_CHW;
   args.input_data_type = fpga::DATA_TYPE_FP16;