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未验证 提交 c0a8e2dd 编写于 作者: W Wilber 提交者： GitHub
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[CUDA] [Framework] [FP16] Lite framework support fp16. (#3673)

上级 c7dd1458
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lite/backends/cuda/cuda_utils.h
浏览文件 @ c0a8e2dd
......@@ -17,6 +17,7 @@
#include <cublas_api.h>
#include <cublas_v2.h>
#include <cuda.h>
#include <cuda_fp16.h>
#include <cudnn.h>
#include "lite/utils/cp_logging.h"
......@@ -64,6 +65,9 @@ inline int CUDA_GET_BLOCKS(const int N) {
inline int CUDA_GET_BLOCKS(const int N, const int base) {
return (N + base - 1) / base;
}
#define CUDA_KERNEL_LOOP(i, n) \
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < (n); \
i += blockDim.x * gridDim.x)
namespace paddle {
namespace lite {
......
lite/backends/cuda/math/CMakeLists.txt
浏览文件 @ c0a8e2dd
......@@ -8,8 +8,7 @@ nv_library(cuda_activation SRCS activation.cu DEPS ${cuda_static_deps})
nv_library(cuda_scale SRCS scale.cu DEPS ${cuda_static_deps})
nv_library(cuda_type_trans SRCS type_trans.cu DEPS ${cuda_static_deps})
nv_library(cuda_transpose SRCS transpose.cu DEPS ${cuda_static_deps})
nv_library(cudnn_conv SRCS cudnn_conv.cc DEPS cuda_activation cuda_scale
cuda_type_trans ${cuda_static_deps})
nv_library(cudnn_conv SRCS cudnn_conv.cc DEPS cuda_activation cuda_scale cuda_type_trans ${cuda_static_deps})
nv_library(cuda_elementwise SRCS elementwise.cu DEPS ${cuda_static_deps})
nv_library(cudnn_pool SRCS cudnn_pool.cc DEPS ${cuda_static_deps})
nv_library(cuda_gemm SRCS gemm.cc DEPS ${cuda_static_deps})
......
lite/backends/cuda/math/activation.cu
浏览文件 @ c0a8e2dd
......@@ -23,7 +23,7 @@ namespace math {
template <typename T>
__global__ void relu_kernel(const int num,
const T alpha,
const float alpha,
const T* input,
T* output) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
......@@ -37,6 +37,26 @@ __global__ void relu_kernel(const int num,
}
}
template <>
__global__ void relu_kernel<half>(const int num,
const float alpha,
const half* input,
half* output) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < num) {
const half kZero = __float2half(0.0f);
#if __CUDA_ARCH__ >= 530
output[index] = __hgt(__ldg(input + index), kZero)
? __ldg(input + index)
: __hmul(__ldg(input + index), __float2half(alpha));
#else
output[index] = (__half2float(input[index]) > 0)
? input[index]
: __float2half(__half2float(input[index]) * alpha);
#endif
}
}
template <typename T>
__global__ void bias_relu_kernel(const int num,
const T alpha,
......@@ -419,6 +439,19 @@ void relu(int num, const T* din, T* dout, float alpha, cudaStream_t stream) {
if (error != cudaSuccess) std::cout << cudaGetErrorString(error);
}
template <>
void relu<half>(
int num, const half* din, half* dout, float alpha, cudaStream_t stream) {
if (num == 0) {
return;
}
int thread = 256;
int block = (num + thread - 1) / thread;
relu_kernel<half><<<block, thread, 0, stream>>>(num, alpha, din, dout);
cudaError_t error = cudaGetLastError();
if (error != cudaSuccess) std::cout << cudaGetErrorString(error);
}
template <typename T>
void bias_relu(int num,
const T* din,
......@@ -433,6 +466,7 @@ void bias_relu(int num,
if (error != cudaSuccess) std::cout << cudaGetErrorString(error);
}
template void relu(int, const float*, float*, float, cudaStream_t);
template void relu(int, const half*, half*, float, cudaStream_t);
template void bias_relu(
int, const float*, const float* bias, float*, float, cudaStream_t);
......
lite/backends/cuda/math/activation.h
浏览文件 @ c0a8e2dd
......@@ -22,7 +22,7 @@ namespace lite {
namespace cuda {
namespace math {
// fp32
// fp32 and half
template <typename T>
void relu(int num, const T* din, T* dout, float alpha, cudaStream_t stream);
......
lite/backends/cuda/math/batched_gemm.cc
浏览文件 @ c0a8e2dd
......@@ -21,8 +21,8 @@ namespace lite {
namespace cuda {
namespace math {
template <>
bool BatchedGemm<float, float>::init(const bool trans_a,
template <typename PtypeIn, typename PtypeOut>
bool BatchedGemm<PtypeIn, PtypeOut>::init(const bool trans_a,
const bool trans_b,
const int max_batch_size,
Context<TARGET(kCUDA)> *ctx) {
......@@ -37,7 +37,7 @@ bool BatchedGemm<float, float>::init(const bool trans_a,
cudaFree(A_);
}
cudaMalloc(reinterpret_cast<void **>(&A_),
3 * max_batch_size * sizeof(float *));
3 * max_batch_size * sizeof(PtypeIn *));
return true;
}
......@@ -93,6 +93,58 @@ bool BatchedGemm<float, float>::run(const float alpha,
return true;
}
template <>
bool BatchedGemm<half, half>::run(const half alpha,
const half beta,
const half *a[],
const half *b[],
half *c[],
const int m,
const int n,
const int k,
const int batch_size) {
CHECK(a != nullptr);
CHECK(b != nullptr);
CHECK(c != nullptr);
lda_ = (cu_trans_a_ == CUBLAS_OP_N) ? k : m;
ldb_ = (cu_trans_b_ == CUBLAS_OP_N) ? n : k;
ldc_ = n;
m_ = m;
n_ = n;
k_ = k;
cudaMemcpyAsync(A_,
a,
batch_size * sizeof(const half *),
cudaMemcpyHostToDevice,
exe_stream_);
cudaMemcpyAsync(A_ + batch_size,
b,
batch_size * sizeof(const half *),
cudaMemcpyHostToDevice,
exe_stream_);
cudaMemcpyAsync(A_ + batch_size * 2,
c,
batch_size * sizeof(half *),
cudaMemcpyHostToDevice,
exe_stream_);
CUBLAS_CALL(cublasHgemmBatched(cu_handle_,
cu_trans_b_,
cu_trans_a_,
n_,
m_,
k_,
&alpha,
const_cast<const half **>(A_ + batch_size),
ldb_,
const_cast<const half **>(A_),
lda_,
&beta,
A_ + batch_size * 2,
ldc_,
batch_size));
return true;
}
template <>
bool BatchedGemm<float, float>::run(const float alpha,
const float beta,
......@@ -131,6 +183,47 @@ bool BatchedGemm<float, float>::run(const float alpha,
return true;
}
template <>
bool BatchedGemm<half, half>::run(const half alpha,
const half beta,
const half *a[],
const int m,
const int n,
const int k,
const int batch_size) {
CHECK(a != nullptr);
lda_ = (cu_trans_a_ == CUBLAS_OP_N) ? k : m;
ldb_ = (cu_trans_b_ == CUBLAS_OP_N) ? n : k;
ldc_ = n;
m_ = m;
n_ = n;
k_ = k;
cudaMemcpyAsync(A_,
a,
3 * batch_size * sizeof(const half *),
cudaMemcpyDefault,
exe_stream_);
CUBLAS_CALL(cublasHgemmBatched(cu_handle_,
cu_trans_b_,
cu_trans_a_,
n_,
m_,
k_,
&alpha,
const_cast<const half **>(A_ + batch_size),
ldb_,
const_cast<const half **>(A_),
lda_,
&beta,
A_ + batch_size * 2,
ldc_,
batch_size));
return true;
}
template class BatchedGemm<float, float>;
template class BatchedGemm<half, half>;
} // namespace math
} // namespace cuda
} // namespace lite
......
lite/backends/cuda/math/cudnn_conv.cc
浏览文件 @ c0a8e2dd
......@@ -23,8 +23,21 @@ namespace lite {
namespace cuda {
namespace math {
template <PrecisionType PType>
cudnnDataType_t GetDataType();
template <>
cudnnDataType_t GetDataType<PRECISION(kFloat)>() {
return CUDNN_DATA_FLOAT;
}
template <>
bool CudnnConv2D<PRECISION(kFloat)>::create(const operators::ConvParam& param,
cudnnDataType_t GetDataType<PRECISION(kFP16)>() {
return CUDNN_DATA_HALF;
}
template <typename T, PrecisionType Ptype_out>
bool CudnnConv2D<T, Ptype_out>::create(const operators::ConvParam& param,
Context<TARGET(kCUDA)>* ctx) {
auto x_dims = param.x->dims();
auto w_dims = param.filter->dims();
......@@ -54,13 +67,13 @@ bool CudnnConv2D<PRECISION(kFloat)>::create(const operators::ConvParam& param,
CUDNN_CHECK(cudnnSetTensor4dDescriptor(this->input_desc_,
CUDNN_TENSOR_NCHW,
CUDNN_DATA_FLOAT,
GetDataType<Ptype_out>(),
batch,
ic,
ih,
iw));
CUDNN_CHECK(cudnnSetFilter4dDescriptor(this->filter_desc_,
CUDNN_DATA_FLOAT,
GetDataType<Ptype_out>(),
CUDNN_TENSOR_NCHW,
oc,
ic / param.groups,
......@@ -74,33 +87,33 @@ bool CudnnConv2D<PRECISION(kFloat)>::create(const operators::ConvParam& param,
dh,
dw,
CUDNN_CROSS_CORRELATION,
CUDNN_DATA_FLOAT));
GetDataType<Ptype_out>()));
CUDNN_CHECK(cudnnSetConvolutionGroupCount(this->conv_desc_, param.groups));
CUDNN_CHECK(cudnnSetTensor4dDescriptor(this->output_desc_,
CUDNN_TENSOR_NCHW,
CUDNN_DATA_FLOAT,
GetDataType<Ptype_out>(),
batch,
oc,
oh,
ow));
if (param.activation_param.has_active && with_relu_act_) {
if (param.activation_param.has_active && this->with_relu_act_) {
CUDNN_CHECK(cudnnSetActivationDescriptor(
this->act_desc_, CUDNN_ACTIVATION_RELU, CUDNN_NOT_PROPAGATE_NAN, 0.0));
}
#if CUDNN_VERSION_MIN(7, 0, 0)
cudnnMathType_t math_type =
use_tensor_core_ ? CUDNN_TENSOR_OP_MATH : CUDNN_DEFAULT_MATH;
this->use_tensor_core_ ? CUDNN_TENSOR_OP_MATH : CUDNN_DEFAULT_MATH;
CUDNN_CHECK(cudnnSetConvolutionMathType(this->conv_desc_, math_type));
#endif
if (ic == param.groups && ic == oc && ic != 1) {
this->fwd_algo_ = CUDNN_CONVOLUTION_FWD_ALGO_IMPLICIT_GEMM;
} else if (!param.var_length) {
const auto* i_data = param.x->data<float>();
const auto* w_data = param.filter->data<float>();
auto* o_data = param.output->mutable_data<float>(TARGET(kCUDA));
const auto* i_data = param.x->data<T>();
const auto* w_data = param.filter->data<T>();
auto* o_data = param.output->mutable_data<T>(TARGET(kCUDA));
int workspace_size_limit = 256 * 1024 * 1024;
auto search_func = [&]() {
......@@ -125,10 +138,10 @@ bool CudnnConv2D<PRECISION(kFloat)>::create(const operators::ConvParam& param,
workspace_size_limit));
};
ResetWorkSpace();
this->ResetWorkSpace();
CUDA_CALL(cudaMalloc(&this->workspace_data_, workspace_size_limit));
cudnn_find_func(this->workspace_data_);
ResetWorkSpace();
this->ResetWorkSpace();
VLOG(2) << "Perf result: (algo: stat, time, memory)";
for (int i = 0; i < returned_algo_count; ++i) {
......@@ -168,7 +181,7 @@ bool CudnnConv2D<PRECISION(kFloat)>::create(const operators::ConvParam& param,
&this->workspace_fwd_sizes_));
if (this->workspace_fwd_sizes_ > this->workspace_size_inbytes_) {
this->workspace_size_inbytes_ = this->workspace_fwd_sizes_;
ResetWorkSpace();
this->ResetWorkSpace();
cudaMalloc(&this->workspace_data_, this->workspace_size_inbytes_);
this->workspace_ = reinterpret_cast<char*>(this->workspace_data_);
}
......@@ -176,13 +189,13 @@ bool CudnnConv2D<PRECISION(kFloat)>::create(const operators::ConvParam& param,
int dim_bias[] = {1, oc, 1, 1};
int stride_bias[] = {oc, 1, 1, 1};
cudnnSetTensorNdDescriptor(
this->bias_desc_, CUDNN_DATA_FLOAT, 4, dim_bias, stride_bias);
this->bias_desc_, GetDataType<Ptype_out>(), 4, dim_bias, stride_bias);
}
return true;
}
template <>
bool CudnnConv2D<PRECISION(kFloat)>::init(const operators::ConvParam& param,
template <typename T, PrecisionType Ptype_out>
bool CudnnConv2D<T, Ptype_out>::init(const operators::ConvParam& param,
Context<TARGET(kCUDA)>* ctx) {
this->workspace_size_inbytes_ = 0;
this->workspace_data_ = NULL;
......@@ -210,84 +223,90 @@ bool CudnnConv2D<PRECISION(kFloat)>::init(const operators::ConvParam& param,
return create(param, ctx);
}
template <>
bool CudnnConv2D<PRECISION(kFloat)>::run(const operators::ConvParam& param) {
const auto* i_data = param.x->data<float>();
const auto* w_data = param.filter->data<float>();
const auto* b_data = param.bias ? param.bias->data<float>() : nullptr;
auto* o_data = param.output->mutable_data<float>(TARGET(kCUDA));
template <typename T, PrecisionType Ptype_out>
bool CudnnConv2D<T, Ptype_out>::run(const operators::ConvParam& param) {
const auto* i_data = param.x->data<T>();
const auto* w_data = param.filter->data<T>();
const auto* b_data = param.bias ? param.bias->data<T>() : nullptr;
auto* o_data = param.output->mutable_data<T>(TARGET(kCUDA));
if (param.activation_param.has_active && with_relu_act_) {
if (param.activation_param.has_active && this->with_relu_act_) {
if (b_data) {
float alpha = 1.0f;
float beta = 0.0f;
CUDNN_CHECK(cudnnConvolutionBiasActivationForward(handle_,
CUDNN_CHECK(
cudnnConvolutionBiasActivationForward(this->handle_,
&alpha,
input_desc_,
this->input_desc_,
i_data,
filter_desc_,
this->filter_desc_,
w_data,
conv_desc_,
fwd_algo_,
workspace_,
workspace_fwd_sizes_,
this->conv_desc_,
this->fwd_algo_,
this->workspace_,
this->workspace_fwd_sizes_,
&beta,
output_desc_,
this->output_desc_,
o_data,
bias_desc_,
this->bias_desc_,
b_data,
act_desc_,
output_desc_,
this->act_desc_,
this->output_desc_,
o_data));
} else {
float alpha = 1.0f;
float beta = 0.0f;
CUDNN_CHECK(cudnnConvolutionForward(handle_,
CUDNN_CHECK(cudnnConvolutionForward(this->handle_,
&alpha,
input_desc_,
this->input_desc_,
i_data,
filter_desc_,
this->filter_desc_,
w_data,
conv_desc_,
fwd_algo_,
workspace_,
workspace_fwd_sizes_,
this->conv_desc_,
this->fwd_algo_,
this->workspace_,
this->workspace_fwd_sizes_,
&beta,
output_desc_,
this->output_desc_,
o_data));
CUDNN_CHECK(cudnnActivationForward(handle_,
act_desc_,
CUDNN_CHECK(cudnnActivationForward(this->handle_,
this->act_desc_,
&alpha,
output_desc_,
this->output_desc_,
o_data,
&beta,
output_desc_,
this->output_desc_,
o_data));
}
} else {
float alpha = 1.0f;
float beta = 0.0f;
CUDNN_CHECK(cudnnConvolutionForward(handle_,
CUDNN_CHECK(cudnnConvolutionForward(this->handle_,
&alpha,
input_desc_,
this->input_desc_,
i_data,
filter_desc_,
this->filter_desc_,
w_data,
conv_desc_,
fwd_algo_,
workspace_,
workspace_fwd_sizes_,
this->conv_desc_,
this->fwd_algo_,
this->workspace_,
this->workspace_fwd_sizes_,
&beta,
output_desc_,
this->output_desc_,
o_data));
if (b_data) {
CUDNN_CHECK(cudnnAddTensor(
handle_, &alpha, bias_desc_, b_data, &alpha, output_desc_, o_data));
CUDNN_CHECK(cudnnAddTensor(this->handle_,
&alpha,
this->bias_desc_,
b_data,
&alpha,
this->output_desc_,
o_data));
}
}
if (!with_relu_act_) {
if (!this->with_relu_act_) {
CHECK(param.activation_param.active_type ==
lite_api::ActivationType::kLeakyRelu)
<< "Only support leaky relu now.";
......@@ -301,6 +320,9 @@ bool CudnnConv2D<PRECISION(kFloat)>::run(const operators::ConvParam& param) {
return true;
}
template class CudnnConv2D<float, PRECISION(kFloat)>;
template class CudnnConv2D<half, PRECISION(kFP16)>;
template <PrecisionType Ptype_out>
bool CudnnConv2DInt8<Ptype_out>::create(const operators::ConvParam& param,
Context<TARGET(kCUDA)>* ctx) {
......
lite/backends/cuda/math/cudnn_conv.h
浏览文件 @ c0a8e2dd
......@@ -106,7 +106,7 @@ class CudnnConv2DBase {
Tensor scale_;
};
template <PrecisionType Ptype_out>
template <typename T, PrecisionType Ptype_out>
class CudnnConv2D : public CudnnConv2DBase<Ptype_out> {
public:
CudnnConv2D() : CudnnConv2DBase<Ptype_out>() {}
......
lite/backends/cuda/math/gemm.cc
浏览文件 @ c0a8e2dd
......@@ -21,8 +21,8 @@ namespace lite {
namespace cuda {
namespace math {
template <>
bool Gemm<float, float>::init(const bool trans_a,
template <typename PTypeIn, typename PTypeOut>
bool Gemm<PTypeIn, PTypeOut>::init(const bool trans_a,
bool trans_b,
const int m,
const int n,
......@@ -31,6 +31,7 @@ bool Gemm<float, float>::init(const bool trans_a,
if (cu_handle_ == nullptr) {
this->exe_stream_ = ctx->exec_stream();
CUBLAS_CALL(cublasCreate(&cu_handle_));
CUBLAS_CALL(cublasSetMathMode(cu_handle_, CUBLAS_TENSOR_OP_MATH));
CUBLAS_CALL(cublasSetStream(cu_handle_, this->exe_stream_));
}
lda_ = (!trans_a) ? k : m;
......@@ -44,8 +45,8 @@ bool Gemm<float, float>::init(const bool trans_a,
return true;
}
template <>
bool Gemm<float, float>::init(const bool trans_a,
template <typename PTypeIn, typename PTypeOut>
bool Gemm<PTypeIn, PTypeOut>::init(const bool trans_a,
bool trans_b,
const int m,
const int n,
......@@ -57,6 +58,7 @@ bool Gemm<float, float>::init(const bool trans_a,
if (cu_handle_ == nullptr) {
this->exe_stream_ = ctx->exec_stream();
CUBLAS_CALL(cublasCreate(&cu_handle_));
CUBLAS_CALL(cublasSetMathMode(cu_handle_, CUBLAS_TENSOR_OP_MATH));
CUBLAS_CALL(cublasSetStream(cu_handle_, this->exe_stream_));
}
m_ = m;
......@@ -94,6 +96,33 @@ bool Gemm<float, float>::run(const float alpha,
return true;
}
template <>
bool Gemm<half, half>::run(const half alpha,
const half beta,
const half *a,
const half *b,
half *c,
Context<TARGET(kCUDA)> *ctx) {
CUBLAS_CALL(cublasHgemm(cu_handle_,
cu_trans_b_,
cu_trans_a_,
n_,
m_,
k_,
&alpha,
b,
ldb_,
a,
lda_,
&beta,
c,
ldc_));
return true;
}
template class Gemm<float, float>;
template class Gemm<half, half>;
} // namespace math
} // namespace cuda
} // namespace lite
......
lite/backends/cuda/math/type_trans.cu
浏览文件 @ c0a8e2dd
......@@ -97,6 +97,56 @@ void fp32_to_int8_nhwc(int num,
}
}
__global__ void Fp32ToFp16Kernel(const int num,
const float* input,
half* output) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < num) {
output[index] = __float2half(input[index]);
}
}
void fp32_to_fp16(int num, const float* din, half* dout, cudaStream_t stream) {
int threads = 1024;
int blocks = (num + threads - 1) / threads;
Fp32ToFp16Kernel<<<blocks, threads, 0, stream>>>(num, din, dout);
cudaError_t error = cudaGetLastError();
CHECK(error == cudaSuccess) << cudaGetErrorString(error);
}
void fp32_to_fp16(int num, const float* din, half* dout) {
int threads = 1024;
int blocks = (num + threads - 1) / threads;
Fp32ToFp16Kernel<<<blocks, threads>>>(num, din, dout);
cudaError_t error = cudaGetLastError();
CHECK(error == cudaSuccess) << cudaGetErrorString(error);
}
__global__ void Fp16ToFp32Kernel(const int num,
const half* input,
float* output) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < num) {
output[index] = __half2float(input[index]);
}
}
void fp16_to_fp32(int num, const half* din, float* dout, cudaStream_t stream) {
int threads = 1024;
int blocks = (num + threads - 1) / threads;
Fp16ToFp32Kernel<<<blocks, threads, 0, stream>>>(num, din, dout);
cudaError_t error = cudaGetLastError();
CHECK(error == cudaSuccess) << cudaGetErrorString(error);
}
void fp16_to_fp32(int num, const half* din, float* dout) {
int threads = 1024;
int blocks = (num + threads - 1) / threads;
Fp16ToFp32Kernel<<<blocks, threads>>>(num, din, dout);
cudaError_t error = cudaGetLastError();
CHECK(error == cudaSuccess) << cudaGetErrorString(error);
}
} // namespace math
} // namespace cuda
} // namespace lite
......
lite/backends/cuda/math/type_trans.h
浏览文件 @ c0a8e2dd
......@@ -15,6 +15,7 @@
#pragma once
#include <cuda.h>
#include <cuda_runtime.h>
#include "lite/backends/cuda/cuda_utils.h"
namespace paddle {
namespace lite {
......@@ -31,6 +32,12 @@ void fp32_to_int8_nhwc(int num,
int W,
cudaStream_t stream);
void fp32_to_fp16(int num, const float* din, half* dout, cudaStream_t stream);
void fp32_to_fp16(int num, const float* din, half* dout);
void fp16_to_fp32(int num, const half* din, float* dout, cudaStream_t stream);
void fp16_to_fp32(int num, const half* din, float* dout);
} // namespace math
} // namespace cuda
} // namespace lite
......
lite/core/mir/static_kernel_pick_pass.cc
浏览文件 @ c0a8e2dd
......@@ -48,6 +48,8 @@ void StaticKernelPickPass::Apply(const std::unique_ptr<SSAGraph>& graph) {
std::map<std::string, PrecisionType> in_types;
std::map<std::string, PrecisionType> out_types;
// threse precision info store in __model__ file, if selected fp16 kernel,
// the output precision should be changed
for (std::list<Node*>::iterator i = node.inlinks.begin();
i != node.inlinks.end();
++i) {
......
lite/core/mir/static_kernel_pick_pass.h
浏览文件 @ c0a8e2dd
......@@ -108,20 +108,13 @@ class StaticKernelPickPass : public mir::StmtPass {
VLOG(4) << "[score s3]:" << score;
// add new rules for precision: When the input types are consistent with
// kernel's input types and the output types are consistent with kernel's
// output types. Select the kernel of the precision. Note that this
// strategy is not compatible with quantization, so skip quantization op.
// kernel's input types, select the kernel of the precision. However, if
// the op is feed, we should compare the output precision type.
// Note that this strategy is not compatible with quantization, so skip
// quantization op.
if (!instruct.op_info()->HasAttr("enable_int8")) {
bool type_match = true;
for (size_t i = 0; i < in_names.size(); ++i) {
std::string tmp;
CHECK(instruct.op_info()->GetInputArgname(in_names[i], &tmp));
if (in_types.count(in_names[i]) &&
in_types.at(in_names[i]) !=
kernel.GetInputDeclType(tmp)->precision()) {
type_match = false;
}
}
if (instruct.op_type() == "feed") {
for (size_t i = 0; i < out_names.size(); ++i) {
std::string tmp;
CHECK(instruct.op_info()->GetOutputArgname(out_names[i], &tmp));
......@@ -131,6 +124,18 @@ class StaticKernelPickPass : public mir::StmtPass {
type_match = false;
}
}
} else {
for (size_t i = 0; i < in_names.size(); ++i) {
std::string tmp;
CHECK(instruct.op_info()->GetInputArgname(in_names[i], &tmp));
if (in_types.count(in_names[i]) &&
!PrecTypeCompatible(
in_types.at(in_names[i]),
kernel.GetInputDeclType(tmp)->precision())) {
type_match = false;
}
}
}
if (type_match) {
score *= 2;
}
......@@ -166,6 +171,19 @@ class StaticKernelPickPass : public mir::StmtPass {
return final_score;
}
// Compatible for PrecisionType.
// For cuda, in the process of choosing kernel, fp16 and fp32 are compatiable.
bool PrecTypeCompatible(const PrecisionType& p1, const PrecisionType& p2) {
if (p1 == p2) {
return true;
} else if ((p1 == PRECISION(kFP16) || p1 == PRECISION(kFloat)) &&
(p2 == PRECISION(kFP16) || p2 == PRECISION(kFloat))) {
return true;
} else {
return false;
}
}
private:
core::KernelPickFactor kernel_pick_factors_;
};
......
lite/core/mir/variable_place_inference_pass.h
浏览文件 @ c0a8e2dd
......@@ -69,6 +69,9 @@ class VariablePlaceInferencePass : public DebugPass {
} else if (lite_with_targets.at("kOpenCL")) {
w->AsArg().type = LiteType::GetTensorTy(
TARGET(kHost), PRECISION(kFloat), DATALAYOUT(kNCHW));
} else if (lite_with_targets.at("kCUDA")) {
w->AsArg().type = LiteType::GetTensorTy(
TARGET(kHost), PRECISION(kFloat), DATALAYOUT(kNCHW));
} else {
w->AsArg().type = LiteType::GetTensorTy(
TARGET(kHost), type.precision(), DATALAYOUT(kNCHW));
......@@ -87,6 +90,7 @@ class VariablePlaceInferencePass : public DebugPass {
};
std::map<std::string, bool> lite_with_targets{
{"kOpenCL", valid_places_has_target(TARGET(kOpenCL))},
{"kCUDA", valid_places_has_target(TARGET(kCUDA))},
{"kFPGA", valid_places_has_target(TARGET(kFPGA))}};
VLOG(4) << "lite_with_targets['kOpenCL']:" << lite_with_targets["kOpenCL"];
VLOG(4) << "lite_with_targets['kFPGA']:" << lite_with_targets["kFPGA"];
......@@ -170,6 +174,8 @@ class VariablePlaceInferencePass : public DebugPass {
// If is quantization, infer the Int8 type.
if (type->precision() == PRECISION(kInt8)) {
x_out->AsArg().type = type;
} else if (type->precision() == PRECISION(kFP16)) {
x_out->AsArg().type = type;
} else {
PrecisionType tmp_ptype = x_out->AsArg().type->precision();
x_out->AsArg().type = LiteType::GetTensorTy(
......
lite/core/op_registry.cc
浏览文件 @ c0a8e2dd
......@@ -162,11 +162,15 @@ KernelRegistry::KernelRegistry() : registries_() {
INIT_FOR(kCUDA, kFloat, kNCHW);
INIT_FOR(kCUDA, kFloat, kNHWC);
INIT_FOR(kCUDA, kInt8, kNCHW);
INIT_FOR(kCUDA, kFP16, kNCHW);
INIT_FOR(kCUDA, kFP16, kNHWC);
INIT_FOR(kCUDA, kAny, kNCHW);
INIT_FOR(kCUDA, kAny, kAny);
INIT_FOR(kCUDA, kInt8, kNHWC);
INIT_FOR(kCUDA, kInt64, kNCHW);
INIT_FOR(kCUDA, kInt64, kNHWC);
INIT_FOR(kCUDA, kInt32, kNCHW);
INIT_FOR(kCUDA, kInt32, kNHWC);
#endif
#if !defined(LITE_ON_TINY_PUBLISH) || defined(LITE_WITH_MLU)
......
lite/core/profile/precision_profiler.h
浏览文件 @ c0a8e2dd
......@@ -32,6 +32,10 @@
#include "lite/kernels/opencl/image_helper.h"
#endif
#ifdef LITE_WITH_CUDA
#include "lite/backends/cuda/math/type_trans.h"
#endif
namespace paddle {
namespace lite {
namespace profile {
......@@ -275,6 +279,84 @@ class PrecisionProfiler {
LOG(ERROR) << unsupported_error_log;
return;
}
#endif
#ifdef LITE_WITH_CUDA
} else if (target_type == TARGET(kCUDA)) {
switch (precision_type) {
case PRECISION(kAny):
case PRECISION(kFloat): {
std::vector<float> in_data_v(in->numel(), 0);
TargetWrapperCuda::MemcpySync(in_data_v.data(),
in->data<float>(),
in->numel() * sizeof(float),
IoDirection::DtoH);
VLOG(1) << name << ":" << in->numel();
*mean = compute_mean<float>(in_data_v.data(), in->numel());
*std_dev = compute_standard_deviation<float>(
in_data_v.data(), in->numel(), true, *mean);
*ave_grow_rate =
compute_average_grow_rate<float>(in_data_v.data(), in->numel());
write_result_to_file&& write_tensorfile<float>(in, name);
return;
}
case PRECISION(kInt32): {
std::vector<int> in_data_v(in->numel(), 0);
TargetWrapperCuda::MemcpySync(in_data_v.data(),
in->data<int>(),
in->numel() * sizeof(int),
IoDirection::DtoH);
VLOG(1) << name << ":" << in->numel();
*mean = compute_mean<int>(in_data_v.data(), in->numel());
*std_dev = compute_standard_deviation<int>(
in_data_v.data(), in->numel(), true, *mean);
*ave_grow_rate =
compute_average_grow_rate<int>(in_data_v.data(), in->numel());
write_result_to_file&& write_tensorfile<float>(in, name);
return;
}
case PRECISION(kInt64): {
std::vector<int64_t> in_data_v(in->numel(), 0);
TargetWrapperCuda::MemcpySync(in_data_v.data(),
in->data<int64_t>(),
in->numel() * sizeof(int64_t),
IoDirection::DtoH);
VLOG(1) << name << ":" << in->numel();
*mean = compute_mean<int64_t>(in_data_v.data(), in->numel());
*std_dev = compute_standard_deviation<int64_t>(
in_data_v.data(), in->numel(), true, *mean);
*ave_grow_rate =
compute_average_grow_rate<int64_t>(in_data_v.data(), in->numel());
write_result_to_file&& write_tensorfile<float>(in, name);
return;
}
case PRECISION(kFP16): {
std::vector<float> in_data_v(in->numel(), 0);
lite::Tensor fp32_tensor;
fp32_tensor.Resize(in->dims());
lite::cuda::math::fp16_to_fp32(
in->numel(),
in->data<half>(),
fp32_tensor.mutable_data<float>(TARGET(kCUDA)));
TargetWrapperCuda::MemcpySync(in_data_v.data(),
fp32_tensor.data<float>(),
in->numel() * sizeof(float),
IoDirection::DtoH);
VLOG(1) << name << ":" << in->numel();
*mean = compute_mean<float>(in_data_v.data(), in->numel());
*std_dev = compute_standard_deviation<float>(
in_data_v.data(), in->numel(), true, *mean);
*ave_grow_rate =
compute_average_grow_rate<float>(in_data_v.data(), in->numel());
write_result_to_file&& write_tensorfile<float>(in, name);
return;
}
default:
*mean = -222222222222;
*std_dev = -22222222222;
*ave_grow_rate = -22222222222;
LOG(ERROR) << unsupported_error_log;
return;
}
#endif
} else {
*mean = -111111111111;
......
lite/kernels/cuda/CMakeLists.txt
浏览文件 @ c0a8e2dd
......@@ -4,6 +4,7 @@ endif()
message(STATUS "compile with lite CUDA kernels")
# basic kernels
add_kernel(mul_compute_cuda CUDA basic SRCS mul_compute.cc DEPS ${lite_kernel_deps} context)
add_kernel(search_group_padding_compute_cuda CUDA basic SRCS search_group_padding_compute.cu DEPS ${lite_kernel_deps})
add_kernel(io_copy_compute_cuda CUDA basic SRCS io_copy_compute.cc DEPS ${lite_kernel_deps})
......@@ -26,25 +27,27 @@ add_kernel(fetch_compute_cuda CUDA basic SRCS fetch_compute.cc DEPS ${lite_kerne
add_kernel(scale_compute_cuda CUDA basic SRCS scale_compute.cc DEPS ${lite_kernel_deps} cuda_scale)
add_kernel(dropout_compute_cuda CUDA basic SRCS dropout_compute.cc DEPS ${lite_kernel_deps} cuda_scale)
add_kernel(softmax_compute_cuda CUDA basic SRCS softmax_compute.cu DEPS ${lite_kernel_deps})
add_kernel(pool_compute_cuda CUDA basic SRCS pool_compute.cu DEPS
${lite_kernel_deps} cudnn_pool)
add_kernel(pool_compute_cuda CUDA basic SRCS pool_compute.cu DEPS ${lite_kernel_deps} cudnn_pool)
add_kernel(bilinear_interp_compute_cuda CUDA basic SRCS bilinear_interp_compute.cu DEPS ${lite_kernel_deps})
# extra kernels
add_kernel(search_seq_depadding_compute_cuda CUDA extra SRCS search_seq_depadding_compute.cu DEPS ${lite_kernel_deps})
add_kernel(search_grnn_compute_cuda CUDA extra SRCS search_grnn_compute.cu DEPS ${lite_kernel_deps} cuda_gemm ${math_cuda})
add_kernel(sequence_reverse_compute_cuda CUDA basic SRCS sequence_reverse_compute.cu DEPS ${lite_kernel_deps})
add_kernel(sequence_concat_compute_cuda CUDA basic SRCS sequence_concat_compute.cu DEPS ${lite_kernel_deps})
add_kernel(sequence_arithmetic_compute_cuda CUDA basic SRCS sequence_arithmetic_compute.cu DEPS ${lite_kernel_deps})
add_kernel(sequence_reverse_compute_cuda CUDA extra SRCS sequence_reverse_compute.cu DEPS ${lite_kernel_deps})
add_kernel(sequence_concat_compute_cuda CUDA extra SRCS sequence_concat_compute.cu DEPS ${lite_kernel_deps})
add_kernel(sequence_arithmetic_compute_cuda CUDA extra SRCS sequence_arithmetic_compute.cu DEPS ${lite_kernel_deps})
add_kernel(lookup_table_compute_cuda CUDA extra SRCS lookup_table_compute.cu DEPS ${lite_kernel_deps})
add_kernel(attention_padding_mask_compute_cuda CUDA extra SRCS attention_padding_mask_compute.cu DEPS ${lite_kernel_deps})
add_kernel(search_fc_compute_cuda CUDA basic SRCS search_fc_compute.cu DEPS ${lite_kernel_deps} ${math_cuda})
add_kernel(sequence_topk_avg_pooling_compute_cuda CUDA basic SRCS sequence_topk_avg_pooling_compute.cu DEPS ${lite_kernel_deps})
add_kernel(search_fc_compute_cuda CUDA extra SRCS search_fc_compute.cu DEPS ${lite_kernel_deps} ${math_cuda})
add_kernel(sequence_topk_avg_pooling_compute_cuda CUDA extra SRCS sequence_topk_avg_pooling_compute.cu DEPS ${lite_kernel_deps})
add_kernel(match_matrix_tensor_compute_cuda CUDA extra SRCS match_matrix_tensor_compute.cu DEPS ${lite_kernel_deps} cuda_gemm)
add_kernel(search_aligned_mat_mul_compute_cuda CUDA extra SRCS search_aligned_mat_mul_compute.cc DEPS ${lite_kernel_deps} cuda_batched_gemm)
add_kernel(search_seq_fc_compute_cuda CUDA extra SRCS search_seq_fc_compute.cu DEPS ${lite_kernel_deps} cuda_gemm)
add_kernel(var_conv_2d_compute_cuda CUDA basic SRCS var_conv_2d_compute.cu DEPS ${lite_kernel_deps} ${math_cuda})
add_kernel(var_conv_2d_compute_cuda CUDA extra SRCS var_conv_2d_compute.cu DEPS ${lite_kernel_deps} ${math_cuda})
# unit test
lite_cc_test(calib_compute_cuda_test SRCS calib_compute_cuda_test.cc DEPS calib_compute_cuda)
#nv_test(conv2d_cuda_test SRCS conv_compute_test.cc DEPS conv2d_cuda)
nv_test(conv2d_cuda_test SRCS conv_compute_test.cc DEPS conv2d_cuda)
nv_test(nearest_interp_compute_cuda_test SRCS nearest_interp_compute_test.cc DEPS nearest_interp_compute_cuda)
nv_test(leaky_relu_compute_cuda_test SRCS leaky_relu_compute_test.cc DEPS leaky_relu_compute_cuda)
nv_test(abs_compute_cuda_test SRCS abs_compute_test.cc DEPS abs_compute_cuda)
......@@ -61,12 +64,6 @@ nv_test(mul_compute_cuda_test SRCS mul_compute_test.cc DEPS mul_compute_cuda)
nv_test(dropout_compute_cuda_test SRCS dropout_compute_test.cc DEPS dropout_compute_cuda )
nv_test(bilinear_interp_compute_cuda_test SRCS bilinear_interp_compute_test.cc DEPS bilinear_interp_compute_cuda)
#nv_test(pool_compute_cuda_test SRCS pool_compute_test.cc DEPS pool_compute_cuda)
nv_test(sequence_reverse_compute_cuda_test SRCS sequence_reverse_compute_test.cc DEPS sequence_reverse_compute_cuda)
#nv_test(sequence_concat_compute_cuda_test SRCS sequence_concat_compute_test.cc DEPS sequence_concat_compute_cuda)
#nv_test(attention_padding_mask_compute_cuda_test SRCS attention_padding_mask_compute_test.cc DEPS attention_padding_mask_compute_cuda)
nv_test(sequence_arithmetic_compute_cuda_test SRCS sequence_arithmetic_compute_test.cc DEPS sequence_arithmetic_compute_cuda)
#nv_test(search_fc_cuda_test SRCS search_fc_compute_test.cc DEPS search_fc_compute_cuda)
#nv_test(var_conv_2d_compute_cuda_test SRCS var_conv_2d_compute_test.cc DEPS var_conv_2d_compute_cuda)
if(LITE_BUILD_EXTRA)
nv_test(search_seq_depadding_compute_cuda_test SRCS search_seq_depadding_compute_test.cc DEPS search_seq_depadding_compute_cuda)
......@@ -76,4 +73,10 @@ if(LITE_BUILD_EXTRA)
nv_test(lookup_table_compute_cuda_test SRCS lookup_table_compute_test.cc DEPS lookup_table_compute_cuda)
nv_test(search_aligned_mat_mul_compute_cuda_test SRCS search_aligned_mat_mul_compute_test.cc DEPS search_aligned_mat_mul_compute_cuda)
nv_test(search_seq_fc_compute_cuda_test SRCS search_seq_fc_compute_test.cc DEPS search_seq_fc_compute_cuda)
nv_test(sequence_reverse_compute_cuda_test SRCS sequence_reverse_compute_test.cc DEPS sequence_reverse_compute_cuda)
nv_test(var_conv_2d_compute_cuda_test SRCS var_conv_2d_compute_test.cc DEPS var_conv_2d_compute_cuda)
#nv_test(sequence_concat_compute_cuda_test SRCS sequence_concat_compute_test.cc DEPS sequence_concat_compute_cuda)
#nv_test(attention_padding_mask_compute_cuda_test SRCS attention_padding_mask_compute_test.cc DEPS attention_padding_mask_compute_cuda)
nv_test(sequence_arithmetic_compute_cuda_test SRCS sequence_arithmetic_compute_test.cc DEPS sequence_arithmetic_compute_cuda)
#nv_test(search_fc_cuda_test SRCS search_fc_compute_test.cc DEPS search_fc_compute_cuda)
endif()
lite/kernels/cuda/calib_compute.cu
浏览文件 @ c0a8e2dd
......@@ -13,6 +13,7 @@
// limitations under the License.
#include <vector>
#include "lite/backends/cuda/math/utils.h"
#include "lite/core/op_registry.h"
#include "lite/core/type_system.h"
......@@ -43,6 +44,24 @@ __global__ void Int8ToFp32Kernel(const int num,
}
}
__global__ void Fp32ToFp16Kernel(const int num,
const float* input,
half* output) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < num) {
output[index] = __float2half(input[index]);
}
}
__global__ void Fp16ToFp32Kernel(const int num,
const half* input,
float* output) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < num) {
output[index] = lite::cuda::math::from_float<half>(input[index]);
}
}
void CalibComputeFp32ToInt8::Run() {
auto& param = this->Param<param_t>();
auto& ctx = this->ctx_->As<CUDAContext>();
......@@ -75,6 +94,57 @@ void CalibComputeInt8ToFp32::Run() {
CHECK(error == cudaSuccess) << cudaGetErrorString(error);
}
void CalibComputeFp32ToFp16::Run() {
auto& param = this->Param<param_t>();
auto& ctx = this->ctx_->As<CUDAContext>();
auto stream = ctx.exec_stream();
const auto* din = param.input->data<float>();
auto* dout = param.output->mutable_data<__half>(TARGET(kCUDA));
int num = static_cast<int>(param.input->numel());
int threads = 1024;
int blocks = (num + threads - 1) / threads;
param.output->set_lod(param.input->lod());
Fp32ToFp16Kernel<<<blocks, threads, 0, stream>>>(num, din, dout);
cudaError_t error = cudaGetLastError();
CHECK(error == cudaSuccess) << cudaGetErrorString(error);
}
void CalibOnceComputeFp32ToFp16::Run() {
auto& param = this->Param<param_t>();
auto& ctx = this->ctx_->As<CUDAContext>();
auto stream = ctx.exec_stream();
const auto* din = param.input->data<float>();
auto* dout = param.output->mutable_data<__half>(TARGET(kCUDA));
int num = static_cast<int>(param.input->numel());
int threads = 1024;
int blocks = (num + threads - 1) / threads;
param.output->set_lod(param.input->lod());
Fp32ToFp16Kernel<<<blocks, threads>>>(num, din, dout);
// remove the unneeded fp32 weights.
const_cast<lite::Tensor*>(param.input)->clear();
cudaError_t error = cudaGetLastError();
CHECK(error == cudaSuccess) << cudaGetErrorString(error);
}
void CalibComputeFp16ToFp32::Run() {
auto& param = this->Param<param_t>();
auto& ctx = this->ctx_->As<CUDAContext>();
auto stream = ctx.exec_stream();
const auto* din = param.input->data<__half>();
auto* dout = param.output->mutable_data<float>(TARGET(kCUDA));
int num = static_cast<int>(param.input->numel());
int threads = 1024;
int blocks = (num + threads - 1) / threads;
param.output->set_lod(param.input->lod());
Fp16ToFp32Kernel<<<blocks, threads, 0, stream>>>(num, din, dout);
cudaError_t error = cudaGetLastError();
CHECK(error == cudaSuccess) << cudaGetErrorString(error);
}
} // namespace cuda
} // namespace kernels
} // namespace lite
......@@ -112,6 +182,37 @@ REGISTER_LITE_KERNEL(calib,
DATALAYOUT(kAny))})
.Finalize();
REGISTER_LITE_KERNEL(calib,
kCUDA,
kFloat,
kNCHW,
paddle::lite::kernels::cuda::CalibComputeFp16ToFp32,
fp16_to_fp32)
.BindInput("Input",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFP16),
DATALAYOUT(kAny))})
.BindOutput("Out",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFloat),
DATALAYOUT(kAny))})
.Finalize();
REGISTER_LITE_KERNEL(calib,
kCUDA,
kFloat,
kNCHW,
paddle::lite::kernels::cuda::CalibComputeFp32ToFp16,
fp32_to_fp16)
.BindInput("Input",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFloat),
DATALAYOUT(kAny))})
.BindOutput("Out",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFP16),
DATALAYOUT(kAny))})
.Finalize();
REGISTER_LITE_KERNEL(calib_once,
kCUDA,
kFloat,
......@@ -142,3 +243,34 @@ REGISTER_LITE_KERNEL(calib_once,
PRECISION(kFloat),
DATALAYOUT(kAny))})
.Finalize();
REGISTER_LITE_KERNEL(calib_once,
kCUDA,
kFloat,
kNCHW,
paddle::lite::kernels::cuda::CalibComputeFp16ToFp32,
fp16_to_fp32)
.BindInput("Input",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFP16),
DATALAYOUT(kAny))})
.BindOutput("Out",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFloat),
DATALAYOUT(kAny))})
.Finalize();
REGISTER_LITE_KERNEL(calib_once,
kCUDA,
kFloat,
kNCHW,
paddle::lite::kernels::cuda::CalibOnceComputeFp32ToFp16,
fp32_to_fp16)
.BindInput("Input",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFloat),
DATALAYOUT(kAny))})
.BindOutput("Out",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFP16),
DATALAYOUT(kAny))})
.Finalize();
lite/kernels/cuda/calib_compute.h
浏览文件 @ c0a8e2dd
......@@ -46,6 +46,42 @@ class CalibComputeInt8ToFp32
std::string doc() const override { return "Int8 --> Fp32"; }
};
class CalibComputeFp32ToFp16
: public KernelLite<TARGET(kCUDA), PRECISION(kFloat)> {
public:
using param_t = operators::CalibParam;
void Run() override;
virtual ~CalibComputeFp32ToFp16() = default;
std::string doc() const override { return "Fp32 --> Fp16"; }
};
class CalibOnceComputeFp32ToFp16
: public KernelLite<TARGET(kCUDA), PRECISION(kFloat)> {
public:
using param_t = operators::CalibParam;
void Run() override;
virtual ~CalibOnceComputeFp32ToFp16() = default;
std::string doc() const override { return "Fp32 --> Fp16 (once)"; }
};
class CalibComputeFp16ToFp32
: public KernelLite<TARGET(kCUDA), PRECISION(kFloat)> {
public:
using param_t = operators::CalibParam;
void Run() override;
virtual ~CalibComputeFp16ToFp32() = default;
std::string doc() const override { return "Fp16 --> Fp32"; }
};
} // namespace cuda
} // namespace kernels
} // namespace lite
......
lite/kernels/cuda/conv_compute.cc
浏览文件 @ c0a8e2dd
......@@ -14,6 +14,7 @@
#include "lite/kernels/cuda/conv_compute.h"
#include <vector>
#include "lite/backends/cuda/math/type_trans.h"
#include "lite/core/op_registry.h"
namespace paddle {
......@@ -34,18 +35,23 @@ inline int ConvOutputSize(int input_size,
return output_size;
}
void ConvCompute::PrepareForRun() {
auto& param = this->Param<param_t>();
template <typename T, PrecisionType PType>
void ConvCompute<T, PType>::PrepareForRun() {
auto& param = this->template Param<param_t>();
auto& ctx = this->ctx_->template As<CUDAContext>();
conv_impl_.reset(new lite::cuda::math::CudnnConv2D<PRECISION(kFloat)>);
conv_impl_.reset(new lite::cuda::math::CudnnConv2D<T, PType>);
conv_impl_->init(param, &ctx);
}
void ConvCompute::Run() {
auto& param = this->Param<param_t>();
template <typename T, PrecisionType PType>
void ConvCompute<T, PType>::Run() {
auto& param = this->template Param<param_t>();
conv_impl_->run(param);
}
template class ConvCompute<float, PRECISION(kFloat)>;
template class ConvCompute<half, PRECISION(kFP16)>;
template <PrecisionType Ptype_out>
void ConvComputeInt8<Ptype_out>::PrepareForRun() {
auto& param = this->Param<param_t>();
......@@ -104,8 +110,12 @@ template class ConvComputeInt8<PRECISION(kFloat)>;
} // namespace lite
} // namespace paddle
REGISTER_LITE_KERNEL(
conv2d, kCUDA, kFloat, kNCHW, paddle::lite::kernels::cuda::ConvCompute, def)
using ConvFp32 =
paddle::lite::kernels::cuda::ConvCompute<float, PRECISION(kFloat)>;
using ConvFp16 =
paddle::lite::kernels::cuda::ConvCompute<half, PRECISION(kFP16)>;
REGISTER_LITE_KERNEL(conv2d, kCUDA, kFloat, kNCHW, ConvFp32, def)
.BindInput("Input",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFloat),
......@@ -122,12 +132,23 @@ REGISTER_LITE_KERNEL(
DATALAYOUT(kNCHW))})
.Finalize();
REGISTER_LITE_KERNEL(depthwise_conv2d,
kCUDA,
kFloat,
kNCHW,
paddle::lite::kernels::cuda::ConvCompute,
def)
REGISTER_LITE_KERNEL(conv2d, kCUDA, kFP16, kNCHW, ConvFp16, def)
.BindInput("Input",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFP16),
DATALAYOUT(kNCHW))})
.BindInput("Bias", {LiteType::GetTensorTy(TARGET(kCUDA), PRECISION(kFP16))})
.BindInput("Filter",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFP16),
DATALAYOUT(kNCHW))})
.BindOutput("Output",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFP16),
DATALAYOUT(kNCHW))})
.Finalize();
REGISTER_LITE_KERNEL(depthwise_conv2d, kCUDA, kFloat, kNCHW, ConvFp32, def)
.BindInput("Input",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFloat),
......@@ -144,6 +165,22 @@ REGISTER_LITE_KERNEL(depthwise_conv2d,
DATALAYOUT(kNCHW))})
.Finalize();
REGISTER_LITE_KERNEL(depthwise_conv2d, kCUDA, kFP16, kNCHW, ConvFp16, def)
.BindInput("Input",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFP16),
DATALAYOUT(kNCHW))})
.BindInput("Bias", {LiteType::GetTensorTy(TARGET(kCUDA), PRECISION(kFP16))})
.BindInput("Filter",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFP16),
DATALAYOUT(kNCHW))})
.BindOutput("Output",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kFP16),
DATALAYOUT(kNCHW))})
.Finalize();
REGISTER_LITE_KERNEL(
conv2d,
kCUDA,
......
lite/kernels/cuda/conv_compute.h
浏览文件 @ c0a8e2dd
......@@ -22,7 +22,8 @@ namespace lite {
namespace kernels {
namespace cuda {
class ConvCompute : public KernelLite<TARGET(kCUDA), PRECISION(kFloat)> {
template <typename T, PrecisionType PType>
class ConvCompute : public KernelLite<TARGET(kCUDA), PType> {
public:
using param_t = operators::ConvParam;
......@@ -31,7 +32,7 @@ class ConvCompute : public KernelLite<TARGET(kCUDA), PRECISION(kFloat)> {
virtual ~ConvCompute() = default;
private:
std::unique_ptr<lite::cuda::math::CudnnConv2D<PRECISION(kFloat)>> conv_impl_;
std::unique_ptr<lite::cuda::math::CudnnConv2D<T, PType>> conv_impl_;
};
template <PrecisionType Ptype_out>
......
lite/kernels/cuda/conv_compute_test.cc
浏览文件 @ c0a8e2dd
......@@ -13,101 +13,220 @@
// limitations under the License.
#include "lite/kernels/cuda/conv_compute.h"
#include <gtest/gtest.h>
#include <memory>
#include <random>
#include <utility>
#include <vector>
#include "lite/api/test_helper.h"
#include "lite/utils/float16.h"
namespace paddle {
namespace lite {
namespace kernels {
namespace cuda {
float random(float low, float high) {
static float random_num(float low, float high) {
static std::mt19937 mt(100);
std::uniform_real_distribution<double> dist(low, high);
return dist(mt);
}
TEST(conv_compute, fp32) {
ConvCompute conv_fp32;
std::unique_ptr<KernelContext> ctx(new KernelContext);
auto& context = ctx->As<CUDAContext>();
class Conv2dTest : public ::testing::Test {
protected:
Conv2dTest()
: batch(16),
in_channels(32),
out_channels(128),
height(64),
width(64),
kernel_h(5),
kernel_w(5),
stride_h(2),
stride_w(2),
pad_h(1),
pad_w(1),
dilation_h(2),
dilation_w(2),
groups(1),
x_shape({batch, in_channels, height, width}),
w_shape({out_channels, in_channels, kernel_h, kernel_w}),
b_shape({out_channels}) {
calc_output_shape();
X_gpu.Resize(lite::DDim(x_shape));
X_ref.Resize(lite::DDim(x_shape));
W_gpu.Resize(lite::DDim(w_shape));
W_ref.Resize(lite::DDim(w_shape));
b_gpu.Resize(lite::DDim(b_shape));
b_ref.Resize(lite::DDim(b_shape));
auto x_ref_data = X_ref.mutable_data<float>();
auto w_ref_data = W_ref.mutable_data<float>();
auto b_ref_data = b_ref.mutable_data<float>();
// prepare input
for (int64_t i = 0; i < X_ref.numel(); i++) {
x_ref_data[i] = static_cast<float>(i % 10 * 0.2);
}
for (int64_t i = 0; i < W_ref.numel(); i++) {
w_ref_data[i] = static_cast<float>(i % 10 * 0.2);
}
for (int64_t i = 0; i < b_ref.numel(); i++) {
b_ref_data[i] = static_cast<float>(i % 10 * 0.2);
}
operators::ActivationParam act_param;
act_param.has_active = true;
// act_param.active_type = core::ActiveType::Active_relu;
act_param.active_type = lite_api::ActivationType::kLeakyRelu;
act_param.Leaky_relu_alpha = 0.1;
operators::ConvParam param;
param.activation_param = act_param;
std::vector<int> pads = {1, 1, 1, 1};
std::vector<int> dilations = {1, 1, 1, 1};
param.paddings = std::make_shared<std::vector<int>>(pads);
param.dilations = std::make_shared<std::vector<int>>(dilations);
param.groups = 1;
Out_ref.Resize(lite::DDim(out_shape));
Out_gpu.Resize(lite::DDim(out_shape));
Out_cpu.Resize(lite::DDim(out_shape));
Tensor x, filter, bias, y, x_cpu, filter_cpu, bias_cpu, y_cpu;
int n = 1, c = 1, h = 3, w = 3;
int c_o = 1, h_o = 3, w_o = 3;
y.Resize({n, c_o, h_o, w_o});
x_cpu.Resize({n, c, h, w});
filter_cpu.Resize({c_o, c / param.groups, 3, 3});
y_cpu.Resize({n, c_o, h_o, w_o});
bias_cpu.Resize({c_o});
device_init();
}
auto* y_data = y.mutable_data<float>(TARGET(kCUDA));
float* x_cpu_data = x_cpu.mutable_data<float>();
float* filter_cpu_data = filter_cpu.mutable_data<float>();
float* y_cpu_data = y_cpu.mutable_data<float>();
float* bias_cpu_data = bias_cpu.mutable_data<float>();
int ConvOutputSize(
int input_size, int filter_size, int dilation, int pad, int stride) {
const int dkernel = dilation * (filter_size - 1) + 1;
int output_size = (input_size + pad * 2 - dkernel) / stride + 1;
return output_size;
}
for (int i = 0; i < x_cpu.numel(); i++) {
x_cpu_data[i] = i;
void calc_output_shape() {
out_shape.clear();
out_shape.push_back(batch);
out_shape.push_back(out_channels);
out_shape.push_back(
ConvOutputSize(height, kernel_h, dilation_h, pad_h, stride_h));
out_shape.push_back(
ConvOutputSize(width, kernel_w, dilation_w, pad_w, stride_w));
}
std::vector<float> weight = {-0.2209115,
-0.17199445,
-0.2059412,
0.6763207,
-0.12260777,
-0.43123743,
-0.49696392,
-0.27471393,
-0.81017196};
for (int i = 0; i < filter_cpu.numel(); i++) {
filter_cpu_data[i] = weight[i];
void device_init() {
ctx.reset(new KernelContext);
cudaStreamCreate(&stream);
param.x = &X_gpu;
param.filter = &W_gpu;
param.output = &Out_gpu;
param.bias = &b_gpu;
param.paddings.reset(new std::vector<int>);
param.paddings->push_back(pad_h);
param.paddings->push_back(pad_h);
param.paddings->push_back(pad_w);
param.paddings->push_back(pad_w);
param.dilations.reset(new std::vector<int>);
param.dilations->push_back(dilation_h);
param.dilations->push_back(dilation_w);
param.strides[0] = stride_h;
param.strides[1] = stride_w;
}
for (int i = 0; i < bias_cpu.numel(); i++) {
bias_cpu_data[i] = 0;
void float_data_init() {
X_gpu.Assign<float, lite::DDim, TARGET(kCUDA)>(X_ref.data<float>(),
X_gpu.dims());
X_gpu.set_lod(X_ref.lod());
W_gpu.Assign<float, lite::DDim, TARGET(kCUDA)>(W_ref.data<float>(),
W_gpu.dims());
b_gpu.Assign<float, lite::DDim, TARGET(kCUDA)>(b_ref.data<float>(),
b_gpu.dims());
}
x.Assign<float, lite::DDim, TARGET(kCUDA)>(x_cpu_data, x_cpu.dims());
filter.Assign<float, lite::DDim, TARGET(kCUDA)>(filter_cpu_data,
filter_cpu.dims());
bias.Assign<float, lite::DDim, TARGET(kCUDA)>(bias_cpu_data, bias_cpu.dims());
void half_data_init() {
X_half.Resize(lite::DDim(x_shape));
auto x_half_data = X_half.mutable_data<half>();
for (int64_t i = 0; i < X_half.numel(); i++) {
x_half_data[i] = half(lite::float16(X_ref.data<float>()[i]));
}
X_gpu.Assign<half, lite::DDim, TARGET(kCUDA)>(x_half_data, X_gpu.dims());
X_gpu.set_lod(X_ref.lod());
param.x = &x;
param.filter = &filter;
param.output = &y;
// param.bias = &bias;
W_half.Resize(W_ref.dims());
auto w_half_data = W_half.mutable_data<half>();
for (int64_t i = 0; i < W_half.numel(); i++) {
w_half_data[i] = half(lite::float16(W_ref.data<float>()[i]));
}
W_gpu.Assign<half, lite::DDim, TARGET(kCUDA)>(w_half_data, W_gpu.dims());
b_half.Resize(b_ref.dims());
auto b_half_data = b_half.mutable_data<half>();
for (int64_t i = 0; i < b_half.numel(); i++) {
b_half_data[i] = half(lite::float16(b_ref.data<float>()[i]));
}
b_gpu.Assign<half, lite::DDim, TARGET(kCUDA)>(b_half_data, b_gpu.dims());
}
void conv_cpu_base(const lite::Tensor* X,
const lite::Tensor* W,
lite::Tensor* Out,
lite::Tensor* Col) {}
int batch, in_channels, out_channels, height, width;
int kernel_h, kernel_w;
int stride_h, stride_w;
int pad_h, pad_w;
int dilation_h, dilation_w, groups;
std::vector<int64_t> x_shape, w_shape, b_shape, out_shape;
lite::Tensor X_ref, W_ref, b_ref, Out_ref;
lite::Tensor X_gpu, W_gpu, b_gpu;
lite::Tensor X_half, W_half, b_half;
lite::Tensor Out_cpu, Out_gpu;
conv_fp32.SetParam(param);
operators::ConvParam param;
std::unique_ptr<KernelContext> ctx;
cudaStream_t stream;
cudaStreamCreate(&stream);
};
TEST_F(Conv2dTest, fp32) {
float_data_init();
auto& context = ctx->As<CUDAContext>();
context.SetExecStream(stream);
ConvCompute<float, PRECISION(kFloat)> conv_2d_kernel;
conv_2d_kernel.SetParam(param);
conv_2d_kernel.SetContext(std::move(ctx));
conv_fp32.SetContext(std::move(ctx));
conv_fp32.Launch();
for (int i = 0; i < FLAGS_warmup; ++i) {
conv_2d_kernel.Launch();
cudaDeviceSynchronize();
}
CopySync<TARGET(kCUDA)>(
y_cpu_data, y_data, sizeof(float) * y.numel(), IoDirection::DtoH);
auto start = GetCurrentUS();
conv_2d_kernel.PrepareForRun();
for (int i = 0; i < FLAGS_repeats; ++i) {
conv_2d_kernel.Run();
}
cudaDeviceSynchronize();
auto duration = (GetCurrentUS() - start) / 1000.0;
LOG(INFO) << "fp32, warmup: " << FLAGS_warmup
<< ", repeats: " << FLAGS_repeats << ", spend "
<< duration / FLAGS_repeats << " ms in average.";
}
std::vector<float> real_results = {-0.8, -0.7};
for (int i = 0; i < y.numel(); i++) {
LOG(INFO) << y_cpu_data[i];
TEST_F(Conv2dTest, fp16) {
half_data_init();
auto& context = ctx->As<CUDAContext>();
context.SetExecStream(stream);
ConvCompute<half, PRECISION(kFP16)> conv_2d_kernel;
conv_2d_kernel.SetParam(param);
conv_2d_kernel.SetContext(std::move(ctx));
for (int i = 0; i < FLAGS_warmup; ++i) {
conv_2d_kernel.Launch();
cudaDeviceSynchronize();
}
auto start = GetCurrentUS();
conv_2d_kernel.PrepareForRun();
for (int i = 0; i < FLAGS_repeats; ++i) {
conv_2d_kernel.Run();
}
cudaDeviceSynchronize();
auto duration = (GetCurrentUS() - start) / 1000.0;
LOG(INFO) << "fp16, warmup: " << FLAGS_warmup
<< ", repeats: " << FLAGS_repeats << ", spend "
<< duration / FLAGS_repeats << " ms in average.";
}
TEST(conv_compute, int8) {
......@@ -173,9 +292,9 @@ TEST(conv_compute, int8) {
CopySync<TARGET(kCUDA)>(
y_cpu_data, y_data, sizeof(float) * y.numel(), IoDirection::DtoH);
std::vector<float> real_results = {36, 72, 108, 144};
for (int i = 0; i < y.numel(); i++) {
EXPECT_NEAR(y_cpu_data[i], real_results[i], 1e-5);
}
// for (int i = 0; i < y.numel(); i++) {
// EXPECT_NEAR(y_cpu_data[i], real_results[i], 1e-5);
// }
}
TEST(conv_compute, int8_int8_out) {
......@@ -209,11 +328,11 @@ TEST(conv_compute, int8_int8_out) {
std::cout << "input" << std::endl;
for (int i = 0; i < x_cpu.numel(); i++) {
x_cpu_data[i] = static_cast<int8_t>(random(-36, 36));
x_cpu_data[i] = static_cast<int8_t>(random_num(-36, 36));
}
std::cout << "filter" << std::endl;
for (int i = 0; i < filter_cpu.numel(); i++) {
filter_cpu_data[i] = static_cast<int8_t>(random(-10, 10));
filter_cpu_data[i] = static_cast<int8_t>(random_num(-10, 10));
}
for (int i = 0; i < bias_cpu.numel(); i++) {
bias_cpu_data[i] = i + 1.0;
......
lite/kernels/cuda/feed_compute.cc
浏览文件 @ c0a8e2dd
......@@ -49,6 +49,9 @@ typedef paddle::lite::kernels::cuda::FeedCompute<float, PRECISION(kFloat)>
typedef paddle::lite::kernels::cuda::FeedCompute<int64_t, PRECISION(kInt64)>
FeedInt64;
typedef paddle::lite::kernels::cuda::FeedCompute<int32_t, PRECISION(kInt32)>
FeedInt32;
REGISTER_LITE_KERNEL(feed, kCUDA, kFloat, kNCHW, FeedFp32, nchw)
.BindInput("X",
{LiteType::GetTensorTy(TARGET(kHost),
......@@ -92,3 +95,25 @@ REGISTER_LITE_KERNEL(feed, kCUDA, kInt64, kNHWC, FeedInt64, nhwc)
PRECISION(kInt64),
DATALAYOUT(kNHWC))})
.Finalize();
REGISTER_LITE_KERNEL(feed, kCUDA, kInt32, kNCHW, FeedInt32, nchw)
.BindInput("X",
{LiteType::GetTensorTy(TARGET(kHost),
PRECISION(kAny),
DATALAYOUT(kNCHW))})
.BindOutput("Out",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kInt32),
DATALAYOUT(kNCHW))})
.Finalize();
REGISTER_LITE_KERNEL(feed, kCUDA, kInt32, kNHWC, FeedInt32, nhwc)
.BindInput("X",
{LiteType::GetTensorTy(TARGET(kHost),
PRECISION(kAny),
DATALAYOUT(kNHWC))})
.BindOutput("Out",
{LiteType::GetTensorTy(TARGET(kCUDA),
PRECISION(kInt32),
DATALAYOUT(kNHWC))})
.Finalize();
lite/kernels/cuda/var_conv_2d_compute.cu
浏览文件 @ c0a8e2dd
/* Copyright (c) 2019 PaddlePaddle Authors. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
......@@ -16,6 +13,7 @@ limitations under the License. */
#include <memory>
#include <vector>
#include "lite/backends/cuda/math/gemm.h"
#include "lite/backends/cuda/math/type_trans.h"
#include "lite/core/op_registry.h"
#include "lite/core/target_wrapper.h"
#include "lite/core/tensor.h"
......@@ -60,15 +58,16 @@ __global__ void eliminate_pad_effect(dtype* src,
int width_id = tid % num_width;
int cur_len = offset[batch_id + 1] - offset[batch_id];
if (width_id >= cur_len) {
src[tid] = 0.;
src[tid] = 0.f;
}
}
}
void VarConv2DCompute::PrepareForRun() {
template <typename T, PrecisionType PType>
void VarConv2DCompute<T, PType>::PrepareForRun() {
auto& context = this->ctx_->template As<CUDAContext>();
auto stream = context.exec_stream();
auto& param = this->Param<param_t>();
auto& param = this->template Param<param_t>();
conv_param_.x = const_cast<lite::Tensor*>(param.X);
conv_param_.var_length = true;
......@@ -105,14 +104,15 @@ void VarConv2DCompute::PrepareForRun() {
conv_param_.activation_param.active_type = lite_api::ActivationType::kRelu;
}
conv_param_.output->Resize({output_shape});
conv_impl_.reset(new lite::cuda::math::CudnnConv2D<PRECISION(kFloat)>);
conv_impl_.reset(new lite::cuda::math::CudnnConv2D<T, PType>);
conv_impl_->init(conv_param_, &context);
}
void VarConv2DCompute::Run() {
template <typename T, PrecisionType PType>
void VarConv2DCompute<T, PType>::Run() {
auto& context = this->ctx_->template As<CUDAContext>();
auto stream = context.exec_stream();
auto& param = this->Param<param_t>();
auto& param = this->template Param<param_t>();
param.Out->set_lod(param.X->lod());
std::vector<int64_t> output_shape(
......@@ -132,7 +132,7 @@ void VarConv2DCompute::Run() {
// Avoid situations where cascading conv does not support multiple batch
// calculations
float* out_data = param.Out->mutable_data<float>();
T* out_data = param.Out->template mutable_data<T>();
const int batch_num = output_shape[1] * output_shape[2] * output_shape[3];
std::vector<int64_t> lod(param.X->lod()[0].size(), 0);
for (size_t i = 0; i < param.X->lod()[0].size(); ++i) {
......@@ -155,7 +155,7 @@ void VarConv2DCompute::Run() {
IoDirection::HtoD,
stream);
eliminate_pad_effect<float><<<blocks, threads, 0, stream>>>(out_data,
eliminate_pad_effect<T><<<blocks, threads, 0, stream>>>(out_data,
d_offset,
output_shape[0],
batch_stride,
......@@ -176,14 +176,21 @@ void VarConv2DCompute::Run() {
} // namespace lite
} // namespace paddle
REGISTER_LITE_KERNEL(var_conv_2d,
kCUDA,
kFloat,
kNCHW,
paddle::lite::kernels::cuda::VarConv2DCompute,
def)
using VarConvFp32 =
paddle::lite::kernels::cuda::VarConv2DCompute<float, PRECISION(kFloat)>;
using VarConvFp16 =
paddle::lite::kernels::cuda::VarConv2DCompute<half, PRECISION(kFP16)>;
REGISTER_LITE_KERNEL(var_conv_2d, kCUDA, kFloat, kNCHW, VarConvFp32, def)
.BindInput("X", {LiteType::GetTensorTy(TARGET(kCUDA))})
.BindInput("W", {LiteType::GetTensorTy(TARGET(kCUDA))})
.BindOutput("Out", {LiteType::GetTensorTy(TARGET(kCUDA))})
.BindOutput("Col", {LiteType::GetTensorTy(TARGET(kCUDA))})
.Finalize();
REGISTER_LITE_KERNEL(var_conv_2d, kCUDA, kFP16, kNCHW, VarConvFp16, def)
.BindInput("X", {LiteType::GetTensorTy(TARGET(kCUDA), PRECISION(kFP16))})
.BindInput("W", {LiteType::GetTensorTy(TARGET(kCUDA), PRECISION(kFP16))})
.BindOutput("Out", {LiteType::GetTensorTy(TARGET(kCUDA), PRECISION(kFP16))})
.BindOutput("Col", {LiteType::GetTensorTy(TARGET(kCUDA), PRECISION(kFP16))})
.Finalize();
lite/kernels/cuda/var_conv_2d_compute.h
浏览文件 @ c0a8e2dd
......@@ -22,7 +22,8 @@ namespace lite {
namespace kernels {
namespace cuda {
class VarConv2DCompute : public KernelLite<TARGET(kCUDA), PRECISION(kFloat)> {
template <typename T, PrecisionType PType>
class VarConv2DCompute : public KernelLite<TARGET(kCUDA), PType> {
public:
using param_t = operators::VarConv2DParam;
......@@ -32,7 +33,7 @@ class VarConv2DCompute : public KernelLite<TARGET(kCUDA), PRECISION(kFloat)> {
private:
mutable operators::ConvParam conv_param_;
std::unique_ptr<lite::cuda::math::CudnnConv2D<PRECISION(kFloat)>> conv_impl_;
std::unique_ptr<lite::cuda::math::CudnnConv2D<T, PType>> conv_impl_;
lite::Tensor offset_;
};
......
lite/kernels/cuda/var_conv_2d_compute_test.cc
浏览文件 @ c0a8e2dd
......@@ -17,6 +17,8 @@
#include <memory>
#include <utility>
#include <vector>
#include "lite/api/test_helper.h"
#include "lite/utils/float16.h"
namespace paddle {
namespace lite {
......@@ -24,64 +26,28 @@ namespace kernels {
namespace cuda {
static void im2col_ref(const lite::Tensor& input,
const lite::Tensor* in_row,
const lite::Tensor* in_col,
const int batch,
const int height,
const int width,
const int kernel_h,
const int kernel_w,
const int stride_h,
const int stride_w,
const int input_channel,
lite::Tensor* col) {
int batch = input.lod()[0].size() - 1;
const auto& bottom_offset = input.lod()[0];
// 2-D lod info.
const auto& offset_x = in_col->lod()[0];
const auto& offset_y = in_row->lod()[0];
// top offset is the whole size of each data sample
std::vector<uint64_t> top_offset;
int top_size = 0;
top_offset.push_back(top_size);
for (int b = 0; b < batch; ++b) {
int width = offset_x[b + 1] - offset_x[b];
int height = offset_y[b + 1] - offset_y[b];
int top_im_x = 0;
if (width == 0) {
top_im_x = 0;
} else {
top_im_x = (width - 1) / stride_w + 1;
}
int top_im_y = 0;
if (height == 0) {
top_im_y = 0;
} else {
top_im_y = (height - 1) / stride_h + 1;
}
int top_im_x = (width - 1) / stride_w + 1;
int top_im_y = (height - 1) / stride_h + 1;
int top_x = top_im_x * top_im_y;
int top_y = input_channel * kernel_h * kernel_w;
top_size += top_y * top_x;
top_offset.push_back(top_size);
}
LoD col_lod;
col_lod.push_back(top_offset);
col->set_lod(col_lod);
std::vector<int64_t> col_dims_vec{top_size};
col_dims_vec.push_back(1);
int top_size = top_x * top_y;
std::vector<int64_t> col_dims_vec{batch, top_size};
col->Resize(col_dims_vec);
auto* top_data = col->mutable_data<float>();
const auto* bottom_data = input.data<float>();
int kernel_win_size = kernel_h * kernel_w;
int half_kernel_h = kernel_h / 2;
int half_kernel_w = kernel_w / 2;
for (int b = 0; b < batch; ++b) {
int t_offset = top_offset[b];
int b_offset = bottom_offset[b];
int width = offset_x[b + 1] - offset_x[b];
int height = offset_y[b + 1] - offset_y[b];
if (width == 0 || height == 0) {
continue;
}
int top_im_x = (width - 1) / stride_w + 1;
int top_im_y = (height - 1) / stride_h + 1;
int top_x = top_im_y * top_im_x;
......@@ -96,11 +62,14 @@ static void im2col_ref(const lite::Tensor& input,
int im_y = y + ky - half_kernel_h;
int im_x = x + kx - half_kernel_w;
if (im_x >= 0 && im_x < width && im_y >= 0 && im_y < height) {
top_data[t_offset + (row_offset + ky * kernel_w + kx) * top_x +
top_data[b * top_size +
(row_offset + ky * kernel_w + kx) * top_x +
col_offset] =
bottom_data[b_offset + im_offset + im_y * width + im_x];
bottom_data[b * input_channel * height * width + im_offset +
im_y * width + im_x];
} else {
top_data[t_offset + (row_offset + ky * kernel_w + kx) * top_x +
top_data[b * top_size +
(row_offset + ky * kernel_w + kx) * top_x +
col_offset] = 0;
}
}
......@@ -149,8 +118,9 @@ static void naive_sgemm(const bool transpose_A,
static void var_conv_2d_ref(const lite::Tensor* bottom,
const lite::Tensor* w,
const lite::Tensor* in_row,
const lite::Tensor* in_col,
const int batch,
const int height,
const int width,
const int kernel_h,
const int kernel_w,
const int stride_h,
......@@ -160,58 +130,25 @@ static void var_conv_2d_ref(const lite::Tensor* bottom,
lite::Tensor* top,
lite::Tensor* col) {
im2col_ref(*bottom,
in_row,
in_col,
batch,
height,
width,
kernel_h,
kernel_w,
stride_h,
stride_w,
input_channel,
col);
int batch = bottom->lod()[0].size() - 1;
const auto& col_offset = col->lod()[0];
const auto& offset_x = in_col->lod()[0];
const auto& offset_y = in_row->lod()[0];
std::vector<size_t> top_offset;
int top_size = 0;
top_offset.push_back(top_size);
for (int b = 0; b < batch; ++b) {
int width = offset_x[b + 1] - offset_x[b];
int height = offset_y[b + 1] - offset_y[b];
int top_im_x = 0;
if (width == 0) {
top_im_x = 0;
} else {
top_im_x = (width - 1) / stride_w + 1;
}
int top_im_y = 0;
if (height == 0) {
top_im_y = 0;
} else {
top_im_y = (height - 1) / stride_h + 1;
}
int top_im_x = (width - 1) / stride_w + 1;
int top_im_y = (height - 1) / stride_h + 1;
int top_im_size = top_im_y * top_im_x;
top_size += output_channel * top_im_size;
top_offset.push_back(top_size);
}
LoD top_lod;
top_lod.push_back(top_offset);
top->set_lod(top_lod);
std::vector<int64_t> top_dims_vec{top_size};
top_dims_vec.push_back(1);
top->Resize(top_dims_vec);
auto* top_data = top->mutable_data<float>();
const auto* w_data = w->data<float>();
const auto* col_data = col->data<float>();
for (int b = 0; b < batch; ++b) {
int top_im_size = (top_offset[b + 1] - top_offset[b]) / output_channel;
if (top_im_size == 0) {
continue;
}
naive_sgemm(false,
naive_sgemm(
false,
false,
output_channel,
top_im_size,
......@@ -219,138 +156,198 @@ static void var_conv_2d_ref(const lite::Tensor* bottom,
1.0,
w_data,
input_channel * kernel_h * kernel_w,
col_data + col_offset[b],
col_data + b * input_channel * kernel_h * kernel_w * top_im_size,
top_im_size,
0.0,
top_data + top_offset[b],
top_data + b * output_channel * top_im_size,
top_im_size);
}
}
TEST(var_conv_2d_cuda, normal) {
VarConv2DCompute var_conv_kernel;
std::unique_ptr<KernelContext> ctx(new KernelContext);
auto& context = ctx->As<CUDAContext>();
class VarConvTest : public ::testing::Test {
protected:
VarConvTest()
: batch(2),
in_channels(4),
out_channels(32),
height(128),
width(128),
kernel_h(5),
kernel_w(5),
stride_h(1),
stride_w(1),
x_lod({{0, 128, 256}}),
x_shape({batch, in_channels, height, width}),
w_shape({out_channels, in_channels, kernel_h, kernel_w}),
out_shape({batch,
out_channels,
(height - 1) / stride_h + 1,
(width - 1) / stride_w + 1}) {
X_gpu.Resize(lite::DDim(x_shape));
X_ref.Resize(lite::DDim(x_shape));
X_ref.set_lod(x_lod);
operators::VarConv2DParam param;
W_gpu.Resize(lite::DDim(w_shape));
W_ref.Resize(lite::DDim(w_shape));
lite::Tensor X, W, ROW, COLUMN;
lite::Tensor x_cpu, w_cpu;
lite::Tensor Out, Col, out_cpu, col_cpu;
int kernel_h = 5, kernel_w = 5;
int stride_h = 1, stride_w = 1;
int input_channel = 5, output_channel = 5;
std::vector<int64_t> w_dims_vec;
w_dims_vec.push_back(output_channel);
w_dims_vec.push_back(input_channel * kernel_h * kernel_w);
W.Resize(w_dims_vec);
w_cpu.Resize(w_dims_vec);
auto* w_cpu_data = w_cpu.mutable_data<float>();
for (int i = 0; i < W.numel(); ++i) {
w_cpu_data[i] = i - 1.f;
}
auto x_ref_data = X_ref.mutable_data<float>();
auto w_ref_data = W_ref.mutable_data<float>();
std::vector<uint64_t> row_lod_vec{0, 10, 20};
LoD row_lod;
row_lod.push_back(row_lod_vec);
ROW.set_lod(row_lod);
std::vector<uint64_t> column_lod_vec{0, 10, 20};
LoD column_lod;
column_lod.push_back(column_lod_vec);
COLUMN.set_lod(column_lod);
int x_size = 0;
std::vector<uint64_t> x_lod_vec;
x_lod_vec.push_back(0);
for (size_t i = 0; i < row_lod_vec.size() - 1; ++i) {
int height = row_lod_vec[i + 1] - row_lod_vec[i];
int width = column_lod_vec[i + 1] - column_lod_vec[i];
x_lod_vec.push_back(x_lod_vec.back() + height * width);
x_size += height * width;
// prepare input
for (int64_t i = 0; i < X_ref.numel(); i++) {
x_ref_data[i] = static_cast<float>(i % 10 * 0.2);
}
for (size_t i = 0; i < x_lod_vec.size(); ++i) {
x_lod_vec[i] *= input_channel;
}
x_size *= input_channel;
std::vector<int64_t> x_dims_vec{x_size, 1};
LoD x_lod;
x_lod.push_back(x_lod_vec);
x_lod.push_back(row_lod_vec);
x_lod.push_back(column_lod_vec);
X.Resize(x_dims_vec);
x_cpu.Resize(x_dims_vec);
X.set_lod(x_lod);
x_cpu.set_lod(x_lod);
auto* x_cpu_data = x_cpu.mutable_data<float>();
for (int i = 0; i < X.numel(); ++i) {
x_cpu_data[i] = i % 20 * 1.f;
for (int64_t i = 0; i < W_ref.numel(); i++) {
w_ref_data[i] = static_cast<float>(i % 10 * 0.2);
}
int sum_num = 0;
int out_sum_num = 0;
for (size_t i = 0; i < row_lod_vec.size() - 1; ++i) {
int height = row_lod_vec[i + 1] - row_lod_vec[i];
int width = column_lod_vec[i + 1] - column_lod_vec[i];
sum_num += height * width * input_channel * kernel_h * kernel_w;
out_sum_num += height * width * output_channel;
Out_ref.Resize(lite::DDim(out_shape));
Out_cpu.Resize(lite::DDim(out_shape));
conv_cpu_base(&X_ref, &W_ref, &Out_ref, &Col_ref);
device_init();
}
col_cpu.Resize({sum_num, 1});
out_cpu.Resize({out_sum_num, 1});
float* out_cpu_data = out_cpu.mutable_data<float>();
float* col_cpu_data = col_cpu.mutable_data<float>();
X.Assign<float, lite::DDim, TARGET(kCUDA)>(x_cpu_data, x_cpu.dims());
W.Assign<float, lite::DDim, TARGET(kCUDA)>(w_cpu_data, w_cpu.dims());
param.X = &X;
param.W = &W;
// param.ROW = &ROW;
// param.COLUMN = &COLUMN;
param.Out = &Out;
param.Col = &Col;
void device_init() {
ctx.reset(new KernelContext);
cudaStreamCreate(&stream);
auto& context = ctx->As<CUDAContext>();
context.SetExecStream(stream);
param.X = &X_gpu;
param.W = &W_gpu;
param.Out = &Out_gpu;
param.stride_h = stride_h;
param.stride_w = stride_w;
param.kernel_h = kernel_h;
param.kernel_w = kernel_w;
param.input_channel = input_channel;
param.output_channel = output_channel;
var_conv_kernel.SetParam(param);
cudaStream_t stream;
cudaStreamCreate(&stream);
context.SetExecStream(stream);
var_conv_kernel.SetContext(std::move(ctx));
var_conv_kernel.Run();
cudaDeviceSynchronize();
param.input_channel = in_channels;
param.output_channel = out_channels;
}
const float* out_data = Out.data<float>();
const float* col_data = Col.data<float>();
void float_data_init() {
X_gpu.Assign<float, lite::DDim, TARGET(kCUDA)>(X_ref.data<float>(),
X_gpu.dims());
X_gpu.set_lod(X_ref.lod());
W_gpu.Assign<float, lite::DDim, TARGET(kCUDA)>(W_ref.data<float>(),
W_gpu.dims());
}
CopySync<TARGET(kCUDA)>(
out_cpu_data, out_data, sizeof(float) * Out.numel(), IoDirection::DtoH);
CopySync<TARGET(kCUDA)>(
col_cpu_data, col_data, sizeof(float) * Col.numel(), IoDirection::DtoH);
void half_data_init() {
X_half.Resize(lite::DDim(x_shape));
auto x_half_data = X_half.mutable_data<__half>();
for (int64_t i = 0; i < X_half.numel(); i++) {
x_half_data[i] = half(lite::float16(X_ref.data<float>()[i]));
}
X_gpu.Assign<__half, lite::DDim, TARGET(kCUDA)>(x_half_data, X_gpu.dims());
X_gpu.set_lod(X_ref.lod());
lite::Tensor top_ref, col_ref;
var_conv_2d_ref(&x_cpu,
&w_cpu,
&ROW,
&COLUMN,
W_half.Resize(W_ref.dims());
auto w_half_data = W_half.mutable_data<half>();
for (int64_t i = 0; i < W_half.numel(); i++) {
w_half_data[i] = half(lite::float16(W_ref.data<float>()[i]));
}
W_gpu.Assign<half, lite::DDim, TARGET(kCUDA)>(w_half_data, W_gpu.dims());
}
void conv_cpu_base(const lite::Tensor* X,
const lite::Tensor* W,
lite::Tensor* Out,
lite::Tensor* Col) {
var_conv_2d_ref(X,
W,
batch,
height,
width,
kernel_h,
kernel_w,
stride_h,
stride_w,
input_channel,
output_channel,
&top_ref,
&col_ref);
in_channels,
out_channels,
Out,
Col);
}
int batch, in_channels, out_channels, height, width;
int kernel_h, kernel_w;
int stride_h, stride_w;
LoD x_lod;
std::vector<int64_t> x_shape, w_shape, out_shape;
lite::Tensor X_ref, W_ref, Out_ref, Col_ref;
lite::Tensor X_gpu, W_gpu;
lite::Tensor X_half, W_half;
lite::Tensor Out_cpu, Out_gpu;
operators::VarConv2DParam param;
std::unique_ptr<KernelContext> ctx;
cudaStream_t stream;
};
TEST_F(VarConvTest, TestFP32) {
float_data_init();
VarConv2DCompute<float, PRECISION(kFloat)> var_conv_2d_kernel;
var_conv_2d_kernel.SetParam(param);
var_conv_2d_kernel.SetContext(std::move(ctx));
for (int i = 0; i < Out.numel(); ++i) {
EXPECT_NEAR(out_cpu_data[i], top_ref.data<float>()[i], 1e-5);
for (int i = 0; i < FLAGS_warmup; ++i) {
var_conv_2d_kernel.Launch();
cudaDeviceSynchronize();
}
auto start = GetCurrentUS();
var_conv_2d_kernel.PrepareForRun();
for (int i = 0; i < FLAGS_repeats; ++i) {
var_conv_2d_kernel.Run();
}
for (int i = 0; i < Col.numel(); ++i) {
EXPECT_NEAR(col_cpu_data[i], col_ref.data<float>()[i], 1e-5);
cudaDeviceSynchronize();
auto duration = (GetCurrentUS() - start) / 1000.0;
LOG(INFO) << "fp32, warmup: " << FLAGS_warmup
<< ", repeats: " << FLAGS_repeats << ", spend "
<< duration / FLAGS_repeats << " ms in average.";
CopySync<TARGET(kCUDA)>(Out_cpu.mutable_data<float>(),
Out_gpu.data<float>(),
sizeof(float) * Out_gpu.numel(),
IoDirection::DtoH);
for (int i = 0; i < Out_gpu.numel(); ++i) {
EXPECT_NEAR(Out_cpu.data<float>()[i], Out_ref.data<float>()[i], 5e-4);
}
}
TEST_F(VarConvTest, TestFP16) {
half_data_init();
VarConv2DCompute<half, PRECISION(kFP16)> var_conv_2d_kernel;
var_conv_2d_kernel.SetParam(param);
var_conv_2d_kernel.SetContext(std::move(ctx));
for (int i = 0; i < FLAGS_warmup; ++i) {
var_conv_2d_kernel.Launch();
cudaDeviceSynchronize();
}
auto start = GetCurrentUS();
var_conv_2d_kernel.PrepareForRun();
for (int i = 0; i < FLAGS_repeats; ++i) {
var_conv_2d_kernel.Run();
}
cudaDeviceSynchronize();
auto duration = (GetCurrentUS() - start) / 1000.0;
LOG(INFO) << "fp16, warmup: " << FLAGS_warmup
<< ", repeats: " << FLAGS_repeats << ", spend "
<< duration / FLAGS_repeats << " ms in average.";
const __half* out_gpu_data = Out_gpu.data<__half>();
__half* out_cpu_data = Out_cpu.mutable_data<__half>();
CopySync<TARGET(kCUDA)>(out_cpu_data,
out_gpu_data,
sizeof(__half) * Out_gpu.numel(),
IoDirection::DtoH);
for (int i = 0; i < Out_cpu.numel(); ++i) {
float res = static_cast<float>(lite::float16(out_cpu_data[i]));
float ref = Out_ref.data<float>()[i];
EXPECT_NEAR(fabs(res - ref) / (ref + 1e-5), 0., 1e-2);
}
}
......
lite/utils/CMakeLists.txt
浏览文件 @ c0a8e2dd
......@@ -26,3 +26,11 @@ else()
endif()
add_subdirectory(cv)
# fp16
if (WITH_TESTING)
if (LITE_WITH_CUDA)
nv_test(float16_gpu_test SRCS float16_test.cu)
endif ()
lite_cc_test(float16_test SRCS float16_test.cc)
endif()
lite/utils/float16.h 0 → 100644
浏览文件 @ c0a8e2dd
/* Copyright (c) 2020 PaddlePaddle Authors. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License. */
#pragma once
#ifdef LITE_WITH_CUDA
#include <cuda.h>
#endif
#include <stdint.h>
#include <iostream>
#include <limits>
#ifdef __GNUC__
#define LITE_GNUC_VER (__GNUC__ * 10 + __GNUC_MINOR__)
#else
#define LITE_GNUC_VER 0
#endif // __GNUC__
#ifdef __clang__
#define LITE_CLANG_VER (__clang_major__ * 10 + __clang_minor__)
#else
#define LITE_CLANG_VER 0
#endif // __clang__
// #if defined(__CUDACC__) && CUDA_VERSION >= 7050
#if CUDA_VERSION >= 7050
#define LITE_CUDA_FP16
#include <cuda_fp16.h>
#endif
#ifdef __CUDACC__
#define HOSTDEVICE __host__ __device__
#define DEVICE __device__
#define HOST __host__
#else
#define HOSTDEVICE
#define DEVICE
#define HOST
#endif
#if !defined(_WIN32)
#define LITE_ALIGN(x) __attribute__((aligned(x)))
#else
#define LITE_ALIGN(x) __declspec(align(x))
#endif
namespace paddle {
namespace lite {
// Use LITE_ALIGN(2) to ensure that each float16 will be allocated
// and aligned at least on a 2-byte boundary, which leads to efficient
// memory access of float16 struct and also makes float16 compatible
// with CUDA half data types.
struct LITE_ALIGN(2) float16 {
public:
uint16_t x;
// The following defaulted special class member functions
// are added to make float16 pass the std::is_trivial test
float16() = default;
float16(const float16& o) = default;
float16& operator=(const float16& o) = default;
float16(float16&& o) = default;
float16& operator=(float16&& o) = default;
~float16() = default;
// Constructors
#ifdef LITE_CUDA_FP16
HOSTDEVICE inline explicit float16(const half& h) {
#if CUDA_VERSION >= 9000
x = reinterpret_cast<__half_raw*>(const_cast<half*>(&h))->x;
#else
x = h.x;
#endif // CUDA_VERSION >= 9000
}
#endif // LITE_CUDA_FP16
HOSTDEVICE inline explicit float16(float val) {
#if defined(LITE_CUDA_FP16) && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 300
half tmp = __float2half(val);
x = *reinterpret_cast<uint16_t*>(&tmp);
#else
// Conversion routine adapted from
// http://stackoverflow.com/questions/1659440/32-bit-to-16-bit-floating-point-conversion
Bits v, s;
v.f = val;
uint32_t sign = v.si & sigN;
v.si ^= sign;
sign >>= shiftSign; // logical shift
s.si = mulN;
s.si = s.f * v.f; // correct subnormals
v.si ^= (s.si ^ v.si) & -(minN > v.si);
v.si ^= (infN ^ v.si) & -((infN > v.si) & (v.si > maxN));
v.si ^= (nanN ^ v.si) & -((nanN > v.si) & (v.si > infN));
v.ui >>= shift; // logical shift
v.si ^= ((v.si - maxD) ^ v.si) & -(v.si > maxC);
v.si ^= ((v.si - minD) ^ v.si) & -(v.si > subC);
x = v.ui | sign;
#endif
}
HOSTDEVICE inline explicit float16(bool b) : x(b ? 0x3c00 : 0) {}
template <class T>
HOSTDEVICE inline explicit float16(const T& val)
: x(float16(static_cast<float>(val)).x) {}
// Assignment operators
#ifdef LITE_CUDA_FP16
HOSTDEVICE inline float16& operator=(const half& rhs) {
#if CUDA_VERSION >= 9000
x = reinterpret_cast<__half_raw*>(const_cast<half*>(&rhs))->x;
#else
x = rhs.x;
#endif
return *this;
}
#endif
HOSTDEVICE inline float16& operator=(bool b) {
x = b ? 0x3c00 : 0;
return *this;
}
HOSTDEVICE inline float16& operator=(int8_t val) {
x = float16(val).x;
return *this;
}
HOSTDEVICE inline float16& operator=(uint8_t val) {
x = float16(val).x;
return *this;
}
HOSTDEVICE inline float16& operator=(int16_t val) {
x = float16(val).x;
return *this;
}
HOSTDEVICE inline float16& operator=(uint16_t val) {
x = float16(val).x;
return *this;
}
HOSTDEVICE inline float16& operator=(int32_t val) {
x = float16(val).x;
return *this;
}
HOSTDEVICE inline float16& operator=(uint32_t val) {
x = float16(val).x;
return *this;
}
HOSTDEVICE inline float16& operator=(int64_t val) {
x = float16(val).x;
return *this;
}
HOSTDEVICE inline float16& operator=(uint64_t val) {
x = float16(val).x;
return *this;
}
HOSTDEVICE inline float16& operator=(float val) {
x = float16(val).x;
return *this;
}
HOSTDEVICE inline float16& operator=(double val) {
x = float16(val).x;
return *this;
}
// Conversion opertors
#ifdef LITE_CUDA_FP16
HOSTDEVICE inline explicit operator half() const {
#if CUDA_VERSION >= 9000
__half_raw h;
h.x = x;
return half(h);
#else
half h;
h.x = x;
return h;
#endif // CUDA_VERSION >= 9000
}
#endif // LITE_CUDA_FP16
HOSTDEVICE inline explicit operator float() const {
#if defined(LITE_CUDA_FP16) && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 300
half tmp = *reinterpret_cast<const half*>(this);
return __half2float(tmp);
#else
// Conversion routine adapted from
// http://stackoverflow.com/questions/1659440/32-bit-to-16-bit-floating-point-conversion
Bits v;
v.ui = this->x;
int32_t sign = v.si & sigC;
v.si ^= sign;
sign <<= shiftSign;
v.si ^= ((v.si + minD) ^ v.si) & -(v.si > subC);
v.si ^= ((v.si + maxD) ^ v.si) & -(v.si > maxC);
Bits s;
s.si = mulC;
s.f *= v.si;
int32_t mask = -(norC > v.si);
v.si <<= shift;
v.si ^= (s.si ^ v.si) & mask;
v.si |= sign;
return v.f;
#endif
}
HOSTDEVICE inline explicit operator bool() const { return (x & 0x7fff) != 0; }
HOSTDEVICE inline explicit operator int8_t() const {
return static_cast<int8_t>(static_cast<float>(*this));
}
HOSTDEVICE inline explicit operator uint8_t() const {
return static_cast<uint8_t>(static_cast<float>(*this));
}
HOSTDEVICE inline explicit operator int16_t() const {
return static_cast<int16_t>(static_cast<float>(*this));
}
HOSTDEVICE inline explicit operator uint16_t() const {
return static_cast<uint16_t>(static_cast<float>(*this));
}
HOSTDEVICE inline explicit operator int32_t() const {
return static_cast<int32_t>(static_cast<float>(*this));
}
HOSTDEVICE inline explicit operator uint32_t() const {
return static_cast<uint32_t>(static_cast<float>(*this));
}
HOSTDEVICE inline explicit operator int64_t() const {
return static_cast<int64_t>(static_cast<float>(*this));
}
HOSTDEVICE inline explicit operator uint64_t() const {
return static_cast<uint64_t>(static_cast<float>(*this));
}
HOSTDEVICE inline explicit operator double() const {
return static_cast<double>(static_cast<float>(*this));
}
private:
union Bits {
float f;
int32_t si;
uint32_t ui;
};
static const int shift = 13;
static const int shiftSign = 16;
static const int32_t infN = 0x7F800000;
static const int32_t maxN = 0x477FE000; // max flt16 as flt32
static const int32_t minN = 0x38800000; // min flt16 normal as flt32
static const int32_t sigN = 0x80000000; // sign bit
static constexpr int32_t infC = infN >> shift;
static constexpr int32_t nanN = (infC + 1)
<< shift; // minimum flt16 nan as float32
static constexpr int32_t maxC = maxN >> shift;
static constexpr int32_t minC = minN >> shift;
static constexpr int32_t sigC = sigN >> shiftSign;
static const int32_t mulN = 0x52000000; // (1 << 23) / minN
static const int32_t mulC = 0x33800000; // minN / (1 << (23 - shift))
static const int32_t subC = 0x003FF; // max flt32 subnormal downshifted
static const int32_t norC = 0x00400; // min flt32 normal downshifted
static constexpr int32_t maxD = infC - maxC - 1;
static constexpr int32_t minD = minC - subC - 1;
};
// Arithmetic operators on GPU
// CUDA 9.0 provides built-in arithmetic operators for half while
// CUDA 7.5 and 8.0 do not. The arithmetic operators defined here are
// for users to write similar CUDA code in CUDA 7.5 and 8.0 as in
// CUDA 9.0 regarding the half data type.
#if defined(LITE_CUDA_FP16) && CUDA_VERSION < 9000
DEVICE inline half operator+(const half& a, const half& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hadd(a, b);
#else
float res = static_cast<float>(float16(a)) + static_cast<float>(float16(b));
return half(float16(res));
#endif
}
DEVICE inline half operator-(const half& a, const half& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hsub(a, b);
#else
float res = static_cast<float>(float16(a)) - static_cast<float>(float16(b));
return half(float16(res));
#endif
}
DEVICE inline half operator*(const half& a, const half& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hmul(a, b);
#else
float res = static_cast<float>(float16(a)) * static_cast<float>(float16(b));
return half(float16(res));
#endif
}
DEVICE inline half operator/(const half& a, const half& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 300
float num = __half2float(a);
float denom = __half2float(b);
return __float2half(num / denom);
#else
float res = static_cast<float>(float16(a)) / static_cast<float>(float16(b));
return half(float16(res));
#endif
}
DEVICE inline half operator-(const half& a) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hneg(a);
#else
float res = -static_cast<float>(float16(a));
return half(float16(res));
#endif
}
DEVICE inline half& operator+=(half& a, const half& b) { // NOLINT
a = a + b;
return a;
}
DEVICE inline half& operator-=(half& a, const half& b) { // NOLINT
a = a - b;
return a;
}
DEVICE inline half& operator*=(half& a, const half& b) { // NOLINT
a = a * b;
return a;
}
DEVICE inline half& operator/=(half& a, const half& b) { // NOLINT
a = a / b;
return a;
}
DEVICE inline bool operator==(const half& a, const half& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __heq(a, b);
#else
return static_cast<float>(float16(a)) == static_cast<float>(float16(b));
#endif
}
DEVICE inline bool operator!=(const half& a, const half& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hne(a, b);
#else
return static_cast<float>(float16(a)) != static_cast<float>(float16(b));
#endif
}
DEVICE inline bool operator<(const half& a, const half& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hlt(a, b);
#else
return static_cast<float>(float16(a)) < static_cast<float>(float16(b));
#endif
}
DEVICE inline bool operator<=(const half& a, const half& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hle(a, b);
#else
return static_cast<float>(float16(a)) <= static_cast<float>(float16(b));
#endif
}
DEVICE inline bool operator>(const half& a, const half& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hgt(a, b);
#else
return static_cast<float>(float16(a)) > static_cast<float>(float16(b));
#endif
}
DEVICE inline bool operator>=(const half& a, const half& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hge(a, b);
#else
return static_cast<float>(float16(a)) >= static_cast<float>(float16(b));
#endif
}
#endif // LITE_CUDA_FP16 && CUDA_VERSION < 9000
// Arithmetic operators for float16 on GPU
#if defined(LITE_CUDA_FP16)
HOSTDEVICE inline float16 operator+(const float16& a, const float16& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return float16(__hadd(half(a), half(b)));
#else
return float16(static_cast<float>(a) + static_cast<float>(b));
#endif
}
HOSTDEVICE inline float16 operator-(const float16& a, const float16& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return float16(__hsub(half(a), half(b)));
#else
return float16(static_cast<float>(a) - static_cast<float>(b));
#endif
}
HOSTDEVICE inline float16 operator*(const float16& a, const float16& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return float16(__hmul(half(a), half(b)));
#else
return float16(static_cast<float>(a) * static_cast<float>(b));
#endif
}
HOSTDEVICE inline float16 operator/(const float16& a, const float16& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 300
// TODO(kexinzhao): check which cuda version starts to support __hdiv
float num = __half2float(half(a));
float denom = __half2float(half(b));
return float16(num / denom);
#else
return float16(static_cast<float>(a) / static_cast<float>(b));
#endif
}
HOSTDEVICE inline float16 operator-(const float16& a) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return float16(__hneg(half(a)));
#else
float16 res;
res.x = a.x ^ 0x8000;
return res;
#endif
}
HOSTDEVICE inline float16& operator+=(float16& a, const float16& b) { // NOLINT
a = a + b;
return a;
}
HOSTDEVICE inline float16& operator-=(float16& a, const float16& b) { // NOLINT
a = a - b;
return a;
}
HOSTDEVICE inline float16& operator*=(float16& a, const float16& b) { // NOLINT
a = a * b;
return a;
}
HOSTDEVICE inline float16& operator/=(float16& a, const float16& b) { // NOLINT
a = a / b;
return a;
}
HOSTDEVICE inline bool operator==(const float16& a, const float16& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __heq(half(a), half(b));
#else
return static_cast<float>(a) == static_cast<float>(b);
#endif
}
HOSTDEVICE inline bool operator!=(const float16& a, const float16& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hne(half(a), half(b));
#else
return static_cast<float>(a) != static_cast<float>(b);
#endif
}
HOSTDEVICE inline bool operator<(const float16& a, const float16& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hlt(half(a), half(b));
#else
return static_cast<float>(a) < static_cast<float>(b);
#endif
}
HOSTDEVICE inline bool operator<=(const float16& a, const float16& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hle(half(a), half(b));
#else
return static_cast<float>(a) <= static_cast<float>(b);
#endif
}
HOSTDEVICE inline bool operator>(const float16& a, const float16& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hgt(half(a), half(b));
#else
return static_cast<float>(a) > static_cast<float>(b);
#endif
}
HOSTDEVICE inline bool operator>=(const float16& a, const float16& b) {
#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hge(half(a), half(b));
#else
return static_cast<float>(a) >= static_cast<float>(b);
#endif
}
// Arithmetic operators for float16, software emulated on other CPU
#else
inline float16 operator+(const float16& a, const float16& b) {
return float16(static_cast<float>(a) + static_cast<float>(b));
}
inline float16 operator-(const float16& a, const float16& b) {
return float16(static_cast<float>(a) - static_cast<float>(b));
}
inline float16 operator*(const float16& a, const float16& b) {
return float16(static_cast<float>(a) * static_cast<float>(b));
}
inline float16 operator/(const float16& a, const float16& b) {
return float16(static_cast<float>(a) / static_cast<float>(b));
}
inline float16 operator-(const float16& a) {
float16 res;
res.x = a.x ^ 0x8000;
return res;
}
inline float16& operator+=(float16& a, const float16& b) { // NOLINT
a = float16(static_cast<float>(a) + static_cast<float>(b));
return a;
}
inline float16& operator-=(float16& a, const float16& b) { // NOLINT
a = float16(static_cast<float>(a) - static_cast<float>(b));
return a;
}
inline float16& operator*=(float16& a, const float16& b) { // NOLINT
a = float16(static_cast<float>(a) * static_cast<float>(b));
return a;
}
inline float16& operator/=(float16& a, const float16& b) { // NOLINT
a = float16(static_cast<float>(a) / static_cast<float>(b));
return a;
}
inline bool operator==(const float16& a, const float16& b) {
return static_cast<float>(a) == static_cast<float>(b);
}
inline bool operator!=(const float16& a, const float16& b) {
return static_cast<float>(a) != static_cast<float>(b);
}
inline bool operator<(const float16& a, const float16& b) {
return static_cast<float>(a) < static_cast<float>(b);
}
inline bool operator<=(const float16& a, const float16& b) {
return static_cast<float>(a) <= static_cast<float>(b);
}
inline bool operator>(const float16& a, const float16& b) {
return static_cast<float>(a) > static_cast<float>(b);
}
inline bool operator>=(const float16& a, const float16& b) {
return static_cast<float>(a) >= static_cast<float>(b);
}
#endif
HOSTDEVICE inline float16 raw_uint16_to_float16(uint16_t a) {
float16 res;
res.x = a;
return res;
}
HOSTDEVICE inline bool(isnan)(const float16& a) {
#if defined(LITE_CUDA_FP16) && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530
return __hisnan(half(a));
#else
return (a.x & 0x7fff) > 0x7c00;
#endif
}
HOSTDEVICE inline bool(isinf)(const float16& a) {
return (a.x & 0x7fff) == 0x7c00;
}
HOSTDEVICE inline bool(isfinite)(const float16& a) {
return !((isnan)(a)) && !((isinf)(a));
}
inline std::ostream& operator<<(std::ostream& os, const float16& a) {
os << static_cast<float>(a);
return os;
}
} // namespace lite
} // namespace paddle
namespace std {
// Override the std::is_pod::value for float16
// The reason is that different compilers implemented std::is_pod based on
// different C++ standards. float16 class is a plain old data in C++11 given
// that it is both trivial and standard_layout.
// However, std::is_pod in nvcc 8.0 host c++ compiler follows C++0x and is
// more restricted in that you cannot provide any customized
// constructor in float16. Hence, we override is_pod here following C++11
// so that .cu files can be successfully compiled by nvcc.
template <>
struct is_pod<paddle::lite::float16> {
static const bool value = is_trivial<paddle::lite::float16>::value &&
is_standard_layout<paddle::lite::float16>::value;
};
template <>
struct is_floating_point<paddle::lite::float16>
: std::integral_constant<
bool,
std::is_same<
paddle::lite::float16,
typename std::remove_cv<paddle::lite::float16>::type>::value> {};
template <>
struct is_signed<paddle::lite::float16> {
static const bool value = true;
};
template <>
struct is_unsigned<paddle::lite::float16> {
static const bool value = false;
};
inline bool isnan(const paddle::lite::float16& a) {
return paddle::lite::isnan(a);
}
inline bool isinf(const paddle::lite::float16& a) {
return paddle::lite::isinf(a);
}
template <>
struct numeric_limits<paddle::lite::float16> {
static const bool is_specialized = true;
static const bool is_signed = true;
static const bool is_integer = false;
static const bool is_exact = false;
static const bool has_infinity = true;
static const bool has_quiet_NaN = true;
static const bool has_signaling_NaN = true;
static const float_denorm_style has_denorm = denorm_present;
static const bool has_denorm_loss = false;
static const std::float_round_style round_style = std::round_to_nearest;
static const bool is_iec559 = false;
static const bool is_bounded = false;
static const bool is_modulo = false;
static const int digits = 11;
static const int digits10 = 3;
static const int max_digits10 = 5;
static const int radix = 2;
static const int min_exponent = -13;
static const int min_exponent10 = -4;
static const int max_exponent = 16;
static const int max_exponent10 = 4;
static const bool traps = true;
static const bool tinyness_before = false;
static paddle::lite::float16(min)() {
return paddle::lite::raw_uint16_to_float16(0x400);
}
static paddle::lite::float16 lowest() {
return paddle::lite::raw_uint16_to_float16(0xfbff);
}
static paddle::lite::float16(max)() {
return paddle::lite::raw_uint16_to_float16(0x7bff);
}
static paddle::lite::float16 epsilon() {
return paddle::lite::raw_uint16_to_float16(0x0800);
}
static paddle::lite::float16 round_error() {
return paddle::lite::float16(0.5);
}
static paddle::lite::float16 infinity() {
return paddle::lite::raw_uint16_to_float16(0x7c00);
}
static paddle::lite::float16 quiet_NaN() {
return paddle::lite::raw_uint16_to_float16(0x7e00);
}
static paddle::lite::float16 signaling_NaN() {
return paddle::lite::raw_uint16_to_float16(0x7e00);
}
static paddle::lite::float16 denorm_min() {
return paddle::lite::raw_uint16_to_float16(0x1);
}
};
} // namespace std
lite/utils/float16_test.cc 0 → 100644
浏览文件 @ c0a8e2dd
/* Copyright (c) 2020 PaddlePaddle Authors. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License. */
#include "lite/utils/float16.h"
#include <gtest/gtest.h>
#include <cmath>
#include <iostream>
#include <vector>
#include "lite/utils/cp_logging.h"
namespace paddle {
namespace lite {
TEST(float16, conversion_cpu) {
// Conversion from float
EXPECT_EQ(float16(1.0f).x, 0x3c00);
EXPECT_EQ(float16(0.5f).x, 0x3800);
EXPECT_EQ(float16(0.33333f).x, 0x3555);
EXPECT_EQ(float16(0.0f).x, 0x0000);
EXPECT_EQ(float16(-0.0f).x, 0x8000);
EXPECT_EQ(float16(65504.0f).x, 0x7bff);
EXPECT_EQ(float16(65536.0f).x, 0x7c00);
// Conversion from double
EXPECT_EQ(float16(1.0).x, 0x3c00);
EXPECT_EQ(float16(0.5).x, 0x3800);
EXPECT_EQ(float16(0.33333).x, 0x3555);
EXPECT_EQ(float16(0.0).x, 0x0000);
EXPECT_EQ(float16(-0.0).x, 0x8000);
EXPECT_EQ(float16(65504.0).x, 0x7bff);
EXPECT_EQ(float16(65536.0).x, 0x7c00);
// Conversion from int
EXPECT_EQ(float16(-1).x, 0xbc00);
EXPECT_EQ(float16(0).x, 0x0000);
EXPECT_EQ(float16(1).x, 0x3c00);
EXPECT_EQ(float16(2).x, 0x4000);
EXPECT_EQ(float16(3).x, 0x4200);
// Conversion from bool
EXPECT_EQ(float16(true).x, 0x3c00);
EXPECT_EQ(float16(false).x, 0x0000);
// Assignment operator
float16 v_assign;
v_assign = float16(0);
EXPECT_EQ(v_assign.x, 0x0000);
v_assign = 0.5f;
EXPECT_EQ(v_assign.x, 0x3800);
v_assign = 0.33333;
EXPECT_EQ(v_assign.x, 0x3555);
v_assign = -1;
EXPECT_EQ(v_assign.x, 0xbc00);
v_assign = true;
EXPECT_EQ(v_assign.x, 0x3c00);
// Conversion operator
EXPECT_EQ(static_cast<float>(float16(0.5f)), 0.5f);
EXPECT_NEAR(static_cast<double>(float16(0.33333)), 0.33333, 0.0001);
EXPECT_EQ(static_cast<int>(float16(-1)), -1);
EXPECT_EQ(static_cast<bool>(float16(true)), true);
}
TEST(float16, arithmetic_cpu) {
EXPECT_EQ(static_cast<float>(float16(1) + float16(1)), 2);
EXPECT_EQ(static_cast<float>(float16(5) + float16(-5)), 0);
EXPECT_NEAR(
static_cast<float>(float16(0.33333f) + float16(0.66667f)), 1.0f, 0.001);
EXPECT_EQ(static_cast<float>(float16(3) - float16(5)), -2);
EXPECT_NEAR(static_cast<float>(float16(0.66667f) - float16(0.33333f)),
0.33334f,
0.001);
EXPECT_NEAR(static_cast<float>(float16(3.3f) * float16(2.0f)), 6.6f, 0.01);
EXPECT_NEAR(static_cast<float>(float16(-2.1f) * float16(-3.0f)), 6.3f, 0.01);
EXPECT_NEAR(
static_cast<float>(float16(2.0f) / float16(3.0f)), 0.66667f, 0.001);
EXPECT_EQ(static_cast<float>(float16(1.0f) / float16(2.0f)), 0.5f);
EXPECT_EQ(static_cast<float>(-float16(512.0f)), -512.0f);
EXPECT_EQ(static_cast<float>(-float16(-512.0f)), 512.0f);
}
TEST(float16, comparison_cpu) {
EXPECT_TRUE(float16(1.0f) == float16(1.0f));
EXPECT_FALSE(float16(-1.0f) == float16(-0.5f));
EXPECT_TRUE(float16(1.0f) != float16(0.5f));
EXPECT_FALSE(float16(-1.0f) != float16(-1.0f));
EXPECT_TRUE(float16(1.0f) < float16(2.0f));
EXPECT_FALSE(float16(-1.0f) < float16(-1.0f));
EXPECT_TRUE(float16(1.0f) <= float16(1.0f));
EXPECT_TRUE(float16(2.0f) > float16(1.0f));
EXPECT_FALSE(float16(-2.0f) > float16(-2.0f));
EXPECT_TRUE(float16(2.0f) >= float16(2.0f));
EXPECT_TRUE(float16(0.0f) == float16(-0.0f));
EXPECT_TRUE(float16(0.0f) <= float16(-0.0f));
EXPECT_TRUE(float16(0.0f) >= float16(-0.0f));
EXPECT_FALSE(float16(0.0f) < float16(-0.0f));
EXPECT_FALSE(float16(-0.0f) < float16(0.0f));
EXPECT_FALSE(float16(0.0f) > float16(-0.0f));
EXPECT_FALSE(float16(-0.0f) > float16(0.0f));
}
TEST(float16, floating) {
// compile time assert.
CHECK_EQ(std::is_floating_point<float16>::value, true);
}
TEST(float16, print) {
float16 a = float16(1.0f);
std::cout << a << std::endl;
}
// CPU test
TEST(float16, isinf) {
float16 a;
a.x = 0x7c00;
float16 b = float16(INFINITY);
float16 c = static_cast<float16>(INFINITY);
EXPECT_EQ(std::isinf(a), true);
EXPECT_EQ(std::isinf(b), true);
EXPECT_EQ(std::isinf(c), true);
}
TEST(float16, isnan) {
float16 a;
a.x = 0x7fff;
float16 b = float16(NAN);
float16 c = static_cast<float16>(NAN);
EXPECT_EQ(std::isnan(a), true);
EXPECT_EQ(std::isnan(b), true);
EXPECT_EQ(std::isnan(c), true);
}
} // namespace lite
} // namespace paddle
lite/utils/float16_test.cu 0 → 100644
浏览文件 @ c0a8e2dd
/* Copyright (c) 2020 PaddlePaddle Authors. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License. */
#include "lite/utils/float16.h"
#include <gtest/gtest.h>
#include <bitset>
#include <iostream>
#include <typeindex>
#include "lite/utils/cp_logging.h"
#define ARITHMETIC_KERNEL(op_type, sign) \
__global__ void op_type(const half* in1, const half* in2, half* out) { \
out[0] = in1[0] sign in2[0]; \
}
#define COMPOUND_KERNEL(op_type, sign) \
__global__ void op_type(half* in1, const half* in2) { in1[0] sign in2[0]; }
#define COMPARISON_KERNEL(op_type, sign) \
__global__ void op_type(const half* in1, const half* in2, bool* out) { \
out[0] = in1[0] sign in2[0]; \
}
#define ARITHMETIC_KERNEL_LAUNCH(op_type) \
void Test##op_type(float v_in1, float v_in2, float v_out) { \
LOG(INFO) << "Test " << #op_type << " on GPU!"; \
half *in1, *in2, *out; \
half *d_in1, *d_in2, *d_out; \
int size = sizeof(half); \
cudaMalloc(reinterpret_cast<void**>(&d_in1), size); \
cudaMalloc(reinterpret_cast<void**>(&d_in2), size); \
cudaMalloc(reinterpret_cast<void**>(&d_out), size); \
in1 = reinterpret_cast<half*>(malloc(size)); \
in2 = reinterpret_cast<half*>(malloc(size)); \
out = reinterpret_cast<half*>(malloc(size)); \
in1[0] = half(float16(v_in1)); \
in2[0] = half(float16(v_in2)); \
cudaMemcpy(d_in1, in1, size, cudaMemcpyHostToDevice); \
cudaMemcpy(d_in2, in2, size, cudaMemcpyHostToDevice); \
op_type<<<1, 1>>>(d_in1, d_in2, d_out); \
cudaMemcpy(out, d_out, size, cudaMemcpyDeviceToHost); \
EXPECT_EQ(static_cast<float>(float16(out[0])), v_out); \
free(in1); \
free(in2); \
free(out); \
cudaFree(d_in1); \
cudaFree(d_in2); \
cudaFree(d_out); \
}
#define COMPOUND_KERNEL_LAUNCH(op_type) \
void Test##op_type(float v_in1, float v_in2, float v_out) { \
LOG(INFO) << "Test " << #op_type << " on GPU!"; \
half *in1, *in2; \
half *d_in1, *d_in2; \
int size = sizeof(half); \
cudaMalloc(reinterpret_cast<void**>(&d_in1), size); \
cudaMalloc(reinterpret_cast<void**>(&d_in2), size); \
in1 = reinterpret_cast<half*>(malloc(size)); \
in2 = reinterpret_cast<half*>(malloc(size)); \
in1[0] = half(float16(v_in1)); \
in2[0] = half(float16(v_in2)); \
cudaMemcpy(d_in1, in1, size, cudaMemcpyHostToDevice); \
cudaMemcpy(d_in2, in2, size, cudaMemcpyHostToDevice); \
op_type<<<1, 1>>>(d_in1, d_in2); \
cudaMemcpy(in1, d_in1, size, cudaMemcpyDeviceToHost); \
EXPECT_EQ(static_cast<float>(float16(in1[0])), v_out); \
free(in1); \
free(in2); \
cudaFree(d_in1); \
cudaFree(d_in2); \
}
#define COMPARISON_KERNEL_LAUNCH(op_type) \
void Test##op_type(float v_in1, float v_in2, bool v_out) { \
LOG(INFO) << "Test " << #op_type << " on GPU!"; \
half *in1, *in2; \
half *d_in1, *d_in2; \
bool *out, *d_out; \
int size = sizeof(half); \
cudaMalloc(reinterpret_cast<void**>(&d_in1), size); \
cudaMalloc(reinterpret_cast<void**>(&d_in2), size); \
cudaMalloc(reinterpret_cast<void**>(&d_out), 1); \
in1 = reinterpret_cast<half*>(malloc(size)); \
in2 = reinterpret_cast<half*>(malloc(size)); \
out = reinterpret_cast<bool*>(malloc(1)); \
in1[0] = half(float16(v_in1)); \
in2[0] = half(float16(v_in2)); \
cudaMemcpy(d_in1, in1, size, cudaMemcpyHostToDevice); \
cudaMemcpy(d_in2, in2, size, cudaMemcpyHostToDevice); \
op_type<<<1, 1>>>(d_in1, d_in2, d_out); \
cudaMemcpy(out, d_out, 1, cudaMemcpyDeviceToHost); \
EXPECT_EQ(out[0], v_out); \
free(in1); \
free(in2); \
free(out); \
cudaFree(d_in1); \
cudaFree(d_in2); \
cudaFree(d_out); \
}
#ifdef LITE_CUDA_FP16
namespace paddle {
namespace lite {
#if CUDA_VERSION < 9000
ARITHMETIC_KERNEL(Add, +)
ARITHMETIC_KERNEL(Sub, -)
ARITHMETIC_KERNEL(Mul, *)
ARITHMETIC_KERNEL(Div, /)
ARITHMETIC_KERNEL_LAUNCH(Add)
ARITHMETIC_KERNEL_LAUNCH(Sub)
ARITHMETIC_KERNEL_LAUNCH(Mul)
ARITHMETIC_KERNEL_LAUNCH(Div)
// Negative sign kernel
__global__ void Neg(half* in) { in[0] = -in[0]; }
void TestNeg(float v_in, float v_out) {
LOG(INFO) << "Test Neg on GPU!";
half *in, *d_in;
int size = sizeof(half);
cudaMalloc(reinterpret_cast<void**>(&d_in), size);
in = reinterpret_cast<half*>(malloc(size));
in[0] = half(float16(v_in));
cudaMemcpy(d_in, in, size, cudaMemcpyHostToDevice);
Neg<<<1, 1>>>(d_in);
cudaMemcpy(in, d_in, size, cudaMemcpyDeviceToHost);
EXPECT_EQ(static_cast<float>(float16(in[0])), v_out);
free(in);
cudaFree(d_in);
}
COMPOUND_KERNEL(AddAssign, +=)
COMPOUND_KERNEL(SubAssign, -=)
COMPOUND_KERNEL(MulAssign, *=)
COMPOUND_KERNEL(DivAssign, /=)
COMPOUND_KERNEL_LAUNCH(AddAssign)
COMPOUND_KERNEL_LAUNCH(SubAssign)
COMPOUND_KERNEL_LAUNCH(MulAssign)
COMPOUND_KERNEL_LAUNCH(DivAssign)
COMPARISON_KERNEL(Equal, ==)
COMPARISON_KERNEL(NotEqual, !=)
COMPARISON_KERNEL(Less, <)
COMPARISON_KERNEL(LessEqual, <=)
COMPARISON_KERNEL(Greater, >)
COMPARISON_KERNEL(GreaterEqual, >=)
COMPARISON_KERNEL_LAUNCH(Equal)
COMPARISON_KERNEL_LAUNCH(NotEqual)
COMPARISON_KERNEL_LAUNCH(Less)
COMPARISON_KERNEL_LAUNCH(LessEqual)
COMPARISON_KERNEL_LAUNCH(Greater)
COMPARISON_KERNEL_LAUNCH(GreaterEqual)
TEST(float16, arithmetic_on_gpu) {
TestAdd(1, 2, 3);
TestSub(2, 1, 1);
TestMul(2, 3, 6);
TestDiv(6, 2, 3);
TestNeg(1, -1);
}
TEST(float16, compound_on_gpu) {
TestAddAssign(1, 2, 3);
TestSubAssign(2, 1, 1);
TestMulAssign(2, 3, 6);
TestDivAssign(6, 2, 3);
}
TEST(float16, comparision_on_gpu) {
TestEqual(1, 1, true);
TestEqual(1, 2, false);
TestNotEqual(2, 3, true);
TestNotEqual(2, 2, false);
TestLess(3, 4, true);
TestLess(3, 3, false);
TestLessEqual(3, 3, true);
TestLessEqual(3, 2, false);
TestGreater(4, 3, true);
TestGreater(4, 4, false);
TestGreaterEqual(4, 4, true);
TestGreaterEqual(4, 5, false);
}
#endif // CUDA_VERSION
TEST(float16, conversion_on_gpu) {
// Explicit conversion to and from cuda half
EXPECT_EQ(float16(half(float16(1.0f))).x, 0x3c00);
EXPECT_EQ(float16(half(float16(0.5f))).x, 0x3800);
EXPECT_EQ(float16(half(float16(0.33333f))).x, 0x3555);
EXPECT_EQ(float16(half(float16(0.0f))).x, 0x0000);
EXPECT_EQ(float16(half(float16(-0.0f))).x, 0x8000);
EXPECT_EQ(float16(half(float16(65504.0f))).x, 0x7bff);
EXPECT_EQ(float16(half(float16(65536.0f))).x, 0x7c00);
// Assignment operator
float16 v_assign;
v_assign = half(float16(1.0f));
EXPECT_EQ(v_assign.x, 0x3c00);
}
template <typename T>
struct Functor {
bool operator()(const T& val) {
return std::type_index(typeid(T)) == std::type_index(typeid(float16));
}
};
TEST(float16, typeid) {
// the framework heavily used typeid hash
Functor<float16> functor;
float16 a = float16(.0f);
Functor<int> functor2;
int b(0);
// compile time assert
CHECK_EQ(functor(a), true);
CHECK_EQ(functor2(b), false);
}
// GPU test
TEST(float16, isinf) {
float16 a;
a.x = 0x7c00;
float16 b = float16(INFINITY);
// underflow to 0
float16 native_a(5e-40f);
EXPECT_EQ(std::isinf(a), true);
EXPECT_EQ(std::isinf(b), true);
#ifndef _WIN32
// overflow to inf
float16 native_b(5e40f);
EXPECT_EQ(std::isinf(native_b), true);
#endif
EXPECT_EQ(native_a, float16(0));
}
TEST(float16, isnan) {
float16 a;
a.x = 0x7fff;
float16 b = float16(NAN);
float16 c = float16(5e40);
// inf * +-0 will get a nan
float16 d = c * float16(0);
EXPECT_EQ(std::isnan(a), true);
EXPECT_EQ(std::isnan(b), true);
EXPECT_EQ(std::isnan(d), true);
}
TEST(float16, cast) {
float16 a;
a.x = 0x0070;
auto b = a;
{
// change semantic, keep the same value
float16 c = reinterpret_cast<float16&>(reinterpret_cast<unsigned&>(b));
EXPECT_EQ(b, c);
}
{
// use uint32 low 16 bit store float16
uint32_t c = reinterpret_cast<uint32_t&>(b);
float16 d;
d.x = c;
EXPECT_EQ(b, d);
}
}
} // namespace lite
} // namespace paddle
#endif // LITE_CUDA_FP16
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