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Paddle-Lite
未验证 提交 9e38adc8 编写于 作者: H HappyAngel 提交者： GitHub
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[arm] improve con3x3_dw (#4063) 


* optimize conv_dw profiler

* fix build conv_dw_3x3s1 bug

* update conv_dw_3x3s2

* fxi foormat test=develop
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lite/backends/arm/math/conv3x3s1p01_depthwise_fp32.cc
浏览文件 @ 9e38adc8
...@@ -20,10 +20,11 @@ namespace lite { ...@@ -20,10 +20,11 @@ namespace lite {
namespace arm { namespace arm {
namespace math { namespace math {
void conv_depthwise_3x3s1p0_bias(float *dout, void conv_depthwise_3x3s1p1_bias_relu6(float *dout,
const float *din, const float *din,
const float *weights, const float *weights,
const float *bias, const float *bias,
const float *six,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -31,13 +32,13 @@ void conv_depthwise_3x3s1p0_bias(float *dout, ...@@ -31,13 +32,13 @@ void conv_depthwise_3x3s1p0_bias(float *dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext *ctx); ARMContext *ctx);
void conv_depthwise_3x3s1p0_bias_s(float *dout, void conv_depthwise_3x3s1p1_bias_s_relu6(float *dout,
const float *din, const float *din,
const float *weights, const float *weights,
const float *bias, const float *bias,
const float *six,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -45,13 +46,13 @@ void conv_depthwise_3x3s1p0_bias_s(float *dout, ...@@ -45,13 +46,13 @@ void conv_depthwise_3x3s1p0_bias_s(float *dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext *ctx); ARMContext *ctx);
void conv_depthwise_3x3s1p1_bias(float *dout, void conv_depthwise_3x3s1p0_bias_relu6(float *dout,
const float *din, const float *din,
const float *weights, const float *weights,
const float *bias, const float *bias,
const float *six,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -59,13 +60,69 @@ void conv_depthwise_3x3s1p1_bias(float *dout, ...@@ -59,13 +60,69 @@ void conv_depthwise_3x3s1p1_bias(float *dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext *ctx); ARMContext *ctx);
void conv_depthwise_3x3s1p1_bias_s(float *dout, void conv_depthwise_3x3s1p0_bias_s_relu6(float *dout,
const float *din, const float *din,
const float *weights, const float *weights,
const float *bias, const float *bias,
const float *six,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext *ctx);
void conv_depthwise_3x3s1p1_bias_leakyRelu(float *dout,
const float *din,
const float *weights,
const float *bias,
const float *scale,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext *ctx);
void conv_depthwise_3x3s1p1_bias_s_leakyRelu(float *dout,
const float *din,
const float *weights,
const float *bias,
const float *scale,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext *ctx);
void conv_depthwise_3x3s1p0_bias_leakyRelu(float *dout,
const float *din,
const float *weights,
const float *bias,
const float *scale,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext *ctx);
void conv_depthwise_3x3s1p0_bias_s_leakyRelu(float *dout,
const float *din,
const float *weights,
const float *bias,
const float *scale,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -73,7 +130,6 @@ void conv_depthwise_3x3s1p1_bias_s(float *dout, ...@@ -73,7 +130,6 @@ void conv_depthwise_3x3s1p1_bias_s(float *dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext *ctx); ARMContext *ctx);
void conv_depthwise_3x3s1_fp32(const float *din, void conv_depthwise_3x3s1_fp32(const float *din,
...@@ -92,22 +148,85 @@ void conv_depthwise_3x3s1_fp32(const float *din, ...@@ -92,22 +148,85 @@ void conv_depthwise_3x3s1_fp32(const float *din,
const operators::ActivationParam act_param, const operators::ActivationParam act_param,
ARMContext *ctx) { ARMContext *ctx) {
bool has_active = act_param.has_active; bool has_active = act_param.has_active;
bool flag_relu = false; auto act_type = act_param.active_type;
bool relu6 = false; float tmp = act_param.Relu_clipped_coef;
float ss = act_param.Leaky_relu_alpha;
float vsix[4] = {tmp, tmp, tmp, tmp};
float vscale[4] = {ss, ss, ss, ss};
if (has_active) { if (has_active) {
if (act_param.active_type == lite_api::ActivationType::kRelu) { switch (act_type) {
flag_relu = true; case lite_api::ActivationType::kRelu:
if (pad == 0) {
if (w_in > 5) {
conv_depthwise_3x3s1p0_bias_relu(dout,
din,
weights,
bias,
flag_bias,
true,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
} else {
conv_depthwise_3x3s1p0_bias_s_relu(dout,
din,
weights,
bias,
flag_bias,
true,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
}
}
if (pad == 1) {
if (w_in > 4) {
conv_depthwise_3x3s1p1_bias_relu(dout,
din,
weights,
bias,
flag_bias,
true,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
} else { } else {
relu6 = true; conv_depthwise_3x3s1p1_bias_s_relu(dout,
din,
weights,
bias,
flag_bias,
true,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
} }
} }
break;
case lite_api::ActivationType::kRelu6:
if (pad == 0) { if (pad == 0) {
if (w_in > 5) { if (w_in > 5) {
if (relu6) { conv_depthwise_3x3s1p0_bias_relu6(dout,
conv_depthwise_3x3s1p0_bias(dout,
din, din,
weights, weights,
bias, bias,
vsix,
flag_bias, flag_bias,
num, num,
ch_in, ch_in,
...@@ -115,15 +234,14 @@ void conv_depthwise_3x3s1_fp32(const float *din, ...@@ -115,15 +234,14 @@ void conv_depthwise_3x3s1_fp32(const float *din,
w_in, w_in,
h_out, h_out,
w_out, w_out,
act_param,
ctx); ctx);
} else { } else {
conv_depthwise_3x3s1p0_bias_relu(dout, conv_depthwise_3x3s1p0_bias_s_relu6(dout,
din, din,
weights, weights,
bias, bias,
vsix,
flag_bias, flag_bias,
flag_relu,
num, num,
ch_in, ch_in,
h_in, h_in,
...@@ -132,12 +250,14 @@ void conv_depthwise_3x3s1_fp32(const float *din, ...@@ -132,12 +250,14 @@ void conv_depthwise_3x3s1_fp32(const float *din,
w_out, w_out,
ctx); ctx);
} }
} else { }
if (relu6) { if (pad == 1) {
conv_depthwise_3x3s1p0_bias_s(dout, if (w_in > 4) {
conv_depthwise_3x3s1p1_bias_relu6(dout,
din, din,
weights, weights,
bias, bias,
vsix,
flag_bias, flag_bias,
num, num,
ch_in, ch_in,
...@@ -145,15 +265,14 @@ void conv_depthwise_3x3s1_fp32(const float *din, ...@@ -145,15 +265,14 @@ void conv_depthwise_3x3s1_fp32(const float *din,
w_in, w_in,
h_out, h_out,
w_out, w_out,
act_param,
ctx); ctx);
} else { } else {
conv_depthwise_3x3s1p0_bias_s_relu(dout, conv_depthwise_3x3s1p1_bias_s_relu6(dout,
din, din,
weights, weights,
bias, bias,
vsix,
flag_bias, flag_bias,
flag_relu,
num, num,
ch_in, ch_in,
h_in, h_in,
...@@ -163,14 +282,46 @@ void conv_depthwise_3x3s1_fp32(const float *din, ...@@ -163,14 +282,46 @@ void conv_depthwise_3x3s1_fp32(const float *din,
ctx); ctx);
} }
} }
break;
case lite_api::ActivationType::kLeakyRelu:
if (pad == 0) {
if (w_in > 5) {
conv_depthwise_3x3s1p0_bias_leakyRelu(dout,
din,
weights,
bias,
vscale,
flag_bias,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
} else {
conv_depthwise_3x3s1p0_bias_s_leakyRelu(dout,
din,
weights,
bias,
vscale,
flag_bias,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
}
} }
if (pad == 1) { if (pad == 1) {
if (w_in > 4) { if (w_in > 4) {
if (relu6) { conv_depthwise_3x3s1p1_bias_leakyRelu(dout,
conv_depthwise_3x3s1p1_bias(dout,
din, din,
weights, weights,
bias, bias,
vscale,
flag_bias, flag_bias,
num, num,
ch_in, ch_in,
...@@ -178,15 +329,14 @@ void conv_depthwise_3x3s1_fp32(const float *din, ...@@ -178,15 +329,14 @@ void conv_depthwise_3x3s1_fp32(const float *din,
w_in, w_in,
h_out, h_out,
w_out, w_out,
act_param,
ctx); ctx);
} else { } else {
conv_depthwise_3x3s1p1_bias_relu(dout, conv_depthwise_3x3s1p1_bias_s_leakyRelu(dout,
din, din,
weights, weights,
bias, bias,
vscale,
flag_bias, flag_bias,
flag_relu,
num, num,
ch_in, ch_in,
h_in, h_in,
...@@ -195,28 +345,66 @@ void conv_depthwise_3x3s1_fp32(const float *din, ...@@ -195,28 +345,66 @@ void conv_depthwise_3x3s1_fp32(const float *din,
w_out, w_out,
ctx); ctx);
} }
}
break;
default:
LOG(FATAL) << "this act_type: " << static_cast<int>(act_type)
<< " fuse not support";
}
} else { } else {
if (relu6) { if (pad == 0) {
conv_depthwise_3x3s1p1_bias_s(dout, if (w_in > 5) {
conv_depthwise_3x3s1p0_bias_no_relu(dout,
din, din,
weights, weights,
bias, bias,
flag_bias, flag_bias,
false,
num, num,
ch_in, ch_in,
h_in, h_in,
w_in, w_in,
h_out, h_out,
w_out, w_out,
act_param,
ctx); ctx);
} else { } else {
conv_depthwise_3x3s1p1_bias_s_relu(dout, conv_depthwise_3x3s1p0_bias_s_no_relu(dout,
din,
weights,
bias,
flag_bias,
false,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
}
}
if (pad == 1) {
if (w_in > 4) {
conv_depthwise_3x3s1p1_bias_no_relu(dout,
din,
weights,
bias,
flag_bias,
false,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
} else {
conv_depthwise_3x3s1p1_bias_s_no_relu(dout,
din, din,
weights, weights,
bias, bias,
flag_bias, flag_bias,
flag_relu, false,
num, num,
ch_in, ch_in,
h_in, h_in,
...@@ -1978,82 +2166,169 @@ void conv_depthwise_3x3s1_fp32(const float *din, ...@@ -1978,82 +2166,169 @@ void conv_depthwise_3x3s1_fp32(const float *din,
#endif #endif
void conv_depthwise_3x3s1p1_bias_relu6(float *dout,
const float *din,
const float *weights,
const float *bias,
const float *six,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext *ctx) {
//! pad is done implicit
const float zero[8] = {0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f};
//! for 4x6 convolution window
const unsigned int right_pad_idx[8] = {5, 4, 3, 2, 1, 0, 0, 0};
float *zero_ptr = ctx->workspace_data<float>();
memset(zero_ptr, 0, w_in * sizeof(float));
float *write_ptr = zero_ptr + w_in;
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
int w_stride = 9;
int tile_w = w_out >> 2;
int remain = w_out % 4;
int cnt_col = tile_w - 1;
unsigned int size_pad_right = (unsigned int)(5 + (tile_w << 2) - w_in);
const unsigned int remian_idx[4] = {0, 1, 2, 3};
if (remain == 0 && size_pad_right == 5) {
size_pad_right = 1;
cnt_col -= 1;
remain = 4;
} else if (remain == 0 && size_pad_right == 6) {
size_pad_right = 2;
cnt_col -= 1;
remain = 4;
}
uint32x4_t vmask_rp1 =
vcgeq_u32(vld1q_u32(right_pad_idx), vdupq_n_u32(size_pad_right));
uint32x4_t vmask_rp2 =
vcgeq_u32(vld1q_u32(right_pad_idx + 4), vdupq_n_u32(size_pad_right));
uint32x4_t vmask_result =
vcgtq_u32(vdupq_n_u32(remain), vld1q_u32(remian_idx));
unsigned int vmask[8];
vst1q_u32(vmask, vmask_rp1);
vst1q_u32(vmask + 4, vmask_rp2);
unsigned int rmask[4];
vst1q_u32(rmask, vmask_result);
float32x4_t vzero = vdupq_n_f32(0.f);
#ifdef __aarch64__ #ifdef __aarch64__
void act_switch_3x3s1p1(const float *din_ptr0, float32x4_t vsix = vld1q_f32(six);
const float *din_ptr1, #endif
const float *din_ptr2, for (int n = 0; n < num; ++n) {
const float *din_ptr3, const float *din_batch = din + n * ch_in * size_in_channel;
const float *din_ptr4, float *dout_batch = dout + n * ch_in * size_out_channel;
const float *din_ptr5, #pragma omp parallel for
float *doutr0, for (int c = 0; c < ch_in; c++) {
float *doutr1, float *dout_ptr = dout_batch + c * size_out_channel;
float *doutr2,
float *doutr3, const float *din_ch_ptr = din_batch + c * size_in_channel;
float32x4_t wr0,
float32x4_t wr1, float bias_val = flag_bias ? bias[c] : 0.f;
float32x4_t wr2, float vbias[4] = {bias_val, bias_val, bias_val, bias_val};
unsigned int *vmask,
unsigned int *rmask, const float *wei_ptr = weights + c * w_stride;
float32x4_t vzero,
float *vbias, float32x4_t wr0 = vld1q_f32(wei_ptr);
int cnt, float32x4_t wr1 = vld1q_f32(wei_ptr + 3);
const operators::ActivationParam act_param) { float32x4_t wr2 = vld1q_f32(wei_ptr + 6);
float32x4_t vsix = vdupq_n_f32(act_param.Relu_clipped_coef);
float32x4_t vscale = vdupq_n_f32(act_param.Leaky_relu_alpha); float *doutr0 = dout_ptr;
float *doutr1 = doutr0 + w_out;
switch (act_param.active_type) { float *doutr2 = doutr1 + w_out;
case lite_api::ActivationType::kRelu: float *doutr3 = doutr2 + w_out;
asm volatile(INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1_RELU MID_COMPUTE_S1
MID_RESULT_S1_RELU RIGHT_COMPUTE_S1 RIGHT_RESULT_S1_RELU const float *dr0 = din_ch_ptr;
: [cnt] "+r"(cnt), const float *dr1 = dr0 + w_in;
[din_ptr0] "+r"(din_ptr0), const float *dr2 = dr1 + w_in;
[din_ptr1] "+r"(din_ptr1), const float *dr3 = dr2 + w_in;
[din_ptr2] "+r"(din_ptr2), const float *dr4 = dr3 + w_in;
[din_ptr3] "+r"(din_ptr3), const float *dr5 = dr4 + w_in;
[din_ptr4] "+r"(din_ptr4),
[din_ptr5] "+r"(din_ptr5), const float *din_ptr0 = dr0;
[doutr0] "+r"(doutr0), const float *din_ptr1 = dr1;
[doutr1] "+r"(doutr1), const float *din_ptr2 = dr2;
[doutr2] "+r"(doutr2), const float *din_ptr3 = dr3;
[doutr3] "+r"(doutr3) const float *din_ptr4 = dr4;
: [w0] "w"(wr0), const float *din_ptr5 = dr5;
[w1] "w"(wr1), float *ptr_zero = const_cast<float *>(zero);
[w2] "w"(wr2), #ifdef __aarch64__
[bias_val] "r"(vbias), for (int i = 0; i < h_out; i += 4) {
[vmask] "r"(vmask), //! process top pad pad_h = 1
[rmask] "r"(rmask), din_ptr0 = dr0;
[vzero] "w"(vzero) din_ptr1 = dr1;
: "cc", din_ptr2 = dr2;
"memory", din_ptr3 = dr3;
"v0", din_ptr4 = dr4;
"v1", din_ptr5 = dr5;
"v2",
"v3", doutr0 = dout_ptr;
"v4", doutr1 = doutr0 + w_out;
"v5", doutr2 = doutr1 + w_out;
"v6", doutr3 = doutr2 + w_out;
"v7", if (i == 0) {
"v8", din_ptr0 = zero_ptr;
"v9", din_ptr1 = dr0;
"v10", din_ptr2 = dr1;
"v11", din_ptr3 = dr2;
"v12", din_ptr4 = dr3;
"v13", din_ptr5 = dr4;
"v14", dr0 = dr3;
"v15", dr1 = dr4;
"v16", dr2 = dr5;
"v17", } else {
"v18", dr0 = dr4;
"v19", dr1 = dr5;
"v20", dr2 = dr1 + w_in;
"v21", }
"v22", dr3 = dr2 + w_in;
"v23", dr4 = dr3 + w_in;
"v24", dr5 = dr4 + w_in;
"v25");
//! process bottom pad
if (i + 5 > h_in) {
switch (i + 5 - h_in) {
case 5:
din_ptr1 = zero_ptr;
case 4:
din_ptr2 = zero_ptr;
case 3:
din_ptr3 = zero_ptr;
case 2:
din_ptr4 = zero_ptr;
case 1:
din_ptr5 = zero_ptr;
default:
break; break;
case lite_api::ActivationType::kRelu6: }
/* 0 <= din <= 6 */ }
//! process bottom remain
if (i + 4 > h_out) {
switch (i + 4 - h_out) {
case 3:
doutr1 = write_ptr;
case 2:
doutr2 = write_ptr;
case 1:
doutr3 = write_ptr;
default:
break;
}
}
int cnt = cnt_col;
asm volatile( asm volatile(
INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1_RELU6 MID_COMPUTE_S1 INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1_RELU6 MID_COMPUTE_S1
MID_RESULT_S1_RELU6 RIGHT_COMPUTE_S1 RIGHT_RESULT_S1_RELU6 MID_RESULT_S1_RELU6 RIGHT_COMPUTE_S1 RIGHT_RESULT_S1_RELU6
...@@ -2104,90 +2379,57 @@ void act_switch_3x3s1p1(const float *din_ptr0, ...@@ -2104,90 +2379,57 @@ void act_switch_3x3s1p1(const float *din_ptr0,
"v23", "v23",
"v24", "v24",
"v25"); "v25");
break; dout_ptr = dout_ptr + 4 * w_out;
case lite_api::ActivationType::kLeakyRelu:
/*din = din >= 0 ? din : din * scale*/
asm volatile(INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1_LEAKY_RELU
MID_COMPUTE_S1 MID_RESULT_S1_LEAKY_RELU RIGHT_COMPUTE_S1
RIGHT_RESULT_S1_LEAKY_RELU
: [cnt] "+r"(cnt),
[din_ptr0] "+r"(din_ptr0),
[din_ptr1] "+r"(din_ptr1),
[din_ptr2] "+r"(din_ptr2),
[din_ptr3] "+r"(din_ptr3),
[din_ptr4] "+r"(din_ptr4),
[din_ptr5] "+r"(din_ptr5),
[doutr0] "+r"(doutr0),
[doutr1] "+r"(doutr1),
[doutr2] "+r"(doutr2),
[doutr3] "+r"(doutr3)
: [w0] "w"(wr0),
[w1] "w"(wr1),
[w2] "w"(wr2),
[vscale] "w"(vscale),
[bias_val] "r"(vbias),
[vmask] "r"(vmask),
[rmask] "r"(rmask),
[vzero] "w"(vzero)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21",
"v22",
"v23",
"v24",
"v25");
break;
default:
LOG(FATAL) << "this act_type: " << static_cast<int>(act_param.active_type)
<< " fuse not support";
} }
}
#else #else
void act_switch_3x3s1p1(const float *din_ptr0, for (int i = 0; i < h_out; i += 2) {
const float *din_ptr1, //! process top pad pad_h = 1
const float *din_ptr2, din_ptr0 = dr0;
const float *din_ptr3, din_ptr1 = dr1;
float *doutr0, din_ptr2 = dr2;
float *doutr1, din_ptr3 = dr3;
float32x4_t wr0,
float32x4_t wr1,
float32x4_t wr2,
unsigned int *vmask_ptr,
unsigned int *rmask_ptr,
float32x4_t vzero,
float bias_val,
int cnt,
const operators::ActivationParam act_param) {
float tmp = act_param.Relu_clipped_coef;
float ss = act_param.Leaky_relu_alpha;
float vsix[4] = {tmp, tmp, tmp, tmp};
float vscale[4] = {ss, ss, ss, ss};
switch (act_param.active_type) { doutr0 = dout_ptr;
case lite_api::ActivationType::kRelu: doutr1 = dout_ptr + w_out;
asm volatile(INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1_RELU MID_COMPUTE_S1
MID_RESULT_S1_RELU RIGHT_COMPUTE_S1 RIGHT_RESULT_S1_RELU if (i == 0) {
din_ptr0 = zero_ptr;
din_ptr1 = dr0;
din_ptr2 = dr1;
din_ptr3 = dr2;
dr0 = dr1;
dr1 = dr2;
dr2 = dr3;
dr3 = dr2 + w_in;
} else {
dr0 = dr2;
dr1 = dr3;
dr2 = dr1 + w_in;
dr3 = dr2 + w_in;
}
//! process bottom pad
if (i + 3 > h_in) {
switch (i + 3 - h_in) {
case 3:
din_ptr1 = zero_ptr;
case 2:
din_ptr2 = zero_ptr;
case 1:
din_ptr3 = zero_ptr;
default:
break;
}
}
//! process bottom remain
if (i + 2 > h_out) {
doutr1 = write_ptr;
}
int cnt = cnt_col;
unsigned int *rmask_ptr = rmask;
unsigned int *vmask_ptr = vmask;
asm volatile(
INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1_RELU6 MID_COMPUTE_S1
MID_RESULT_S1_RELU6 RIGHT_COMPUTE_S1 RIGHT_RESULT_S1_RELU6
: [dout_ptr1] "+r"(doutr0), : [dout_ptr1] "+r"(doutr0),
[dout_ptr2] "+r"(doutr1), [dout_ptr2] "+r"(doutr1),
[din0_ptr] "+r"(din_ptr0), [din0_ptr] "+r"(din_ptr0),
...@@ -2201,6 +2443,7 @@ void act_switch_3x3s1p1(const float *din_ptr0, ...@@ -2201,6 +2443,7 @@ void act_switch_3x3s1p1(const float *din_ptr0,
[wr1] "w"(wr1), [wr1] "w"(wr1),
[wr2] "w"(wr2), [wr2] "w"(wr2),
[bias_val] "r"(bias_val), [bias_val] "r"(bias_val),
[six_ptr] "r"(six),
[vzero] "w"(vzero) [vzero] "w"(vzero)
: "cc", : "cc",
"memory", "memory",
...@@ -2216,91 +2459,18 @@ void act_switch_3x3s1p1(const float *din_ptr0, ...@@ -2216,91 +2459,18 @@ void act_switch_3x3s1p1(const float *din_ptr0,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
break; dout_ptr += 2 * w_out;
case lite_api::ActivationType::kRelu6: } //! end of processing mid rows
/* 0 <= din <= 6 */ #endif
asm volatile( }
INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1_RELU6 MID_COMPUTE_S1
MID_RESULT_S1_RELU6 RIGHT_COMPUTE_S1 RIGHT_RESULT_S1_RELU6
: [dout_ptr1] "+r"(doutr0),
[dout_ptr2] "+r"(doutr1),
[din0_ptr] "+r"(din_ptr0),
[din1_ptr] "+r"(din_ptr1),
[din2_ptr] "+r"(din_ptr2),
[din3_ptr] "+r"(din_ptr3),
[cnt] "+r"(cnt),
[rmask] "+r"(rmask_ptr),
[vmask] "+r"(vmask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[bias_val] "r"(bias_val),
[six_ptr] "r"(vsix),
[vzero] "w"(vzero)
: "cc",
"memory",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
break;
case lite_api::ActivationType::kLeakyRelu:
/*din = din >= 0 ? din : din * scale*/
asm volatile(INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1_LEAKY_RELU
MID_COMPUTE_S1 MID_RESULT_S1_LEAKY_RELU RIGHT_COMPUTE_S1
RIGHT_RESULT_S1_LEAKY_RELU
: [dout_ptr1] "+r"(doutr0),
[dout_ptr2] "+r"(doutr1),
[din0_ptr] "+r"(din_ptr0),
[din1_ptr] "+r"(din_ptr1),
[din2_ptr] "+r"(din_ptr2),
[din3_ptr] "+r"(din_ptr3),
[cnt] "+r"(cnt),
[rmask] "+r"(rmask_ptr),
[vmask] "+r"(vmask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[bias_val] "r"(bias_val),
[scale_ptr] "r"(vscale),
[vzero] "w"(vzero)
: "cc",
"memory",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
break;
default:
LOG(FATAL) << "this act_type: " << static_cast<int>(act_param.active_type)
<< " fuse not support";
} }
} }
#endif
/** void conv_depthwise_3x3s1p1_bias_leakyRelu(float *dout,
* \brief depthwise convolution, kernel size 3x3, stride 1, pad 1, with bias,
* width > 4
*/
void conv_depthwise_3x3s1p1_bias(float *dout,
const float *din, const float *din,
const float *weights, const float *weights,
const float *bias, const float *bias,
const float *scale,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -2308,7 +2478,6 @@ void conv_depthwise_3x3s1p1_bias(float *dout, ...@@ -2308,7 +2478,6 @@ void conv_depthwise_3x3s1p1_bias(float *dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext *ctx) { ARMContext *ctx) {
//! pad is done implicit //! pad is done implicit
const float zero[8] = {0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f}; const float zero[8] = {0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f};
...@@ -2355,7 +2524,9 @@ void conv_depthwise_3x3s1p1_bias(float *dout, ...@@ -2355,7 +2524,9 @@ void conv_depthwise_3x3s1p1_bias(float *dout,
vst1q_u32(rmask, vmask_result); vst1q_u32(rmask, vmask_result);
float32x4_t vzero = vdupq_n_f32(0.f); float32x4_t vzero = vdupq_n_f32(0.f);
#ifdef __aarch64__
float32x4_t vscale = vld1q_f32(scale);
#endif
for (int n = 0; n < num; ++n) { for (int n = 0; n < num; ++n) {
const float *din_batch = din + n * ch_in * size_in_channel; const float *din_batch = din + n * ch_in * size_in_channel;
float *dout_batch = dout + n * ch_in * size_out_channel; float *dout_batch = dout + n * ch_in * size_out_channel;
...@@ -2458,25 +2629,56 @@ void conv_depthwise_3x3s1p1_bias(float *dout, ...@@ -2458,25 +2629,56 @@ void conv_depthwise_3x3s1p1_bias(float *dout,
} }
int cnt = cnt_col; int cnt = cnt_col;
act_switch_3x3s1p1(din_ptr0, asm volatile(INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1_LEAKY_RELU
din_ptr1, MID_COMPUTE_S1 MID_RESULT_S1_LEAKY_RELU
din_ptr2, RIGHT_COMPUTE_S1 RIGHT_RESULT_S1_LEAKY_RELU
din_ptr3, : [cnt] "+r"(cnt),
din_ptr4, [din_ptr0] "+r"(din_ptr0),
din_ptr5, [din_ptr1] "+r"(din_ptr1),
doutr0, [din_ptr2] "+r"(din_ptr2),
doutr1, [din_ptr3] "+r"(din_ptr3),
doutr2, [din_ptr4] "+r"(din_ptr4),
doutr3, [din_ptr5] "+r"(din_ptr5),
wr0, [doutr0] "+r"(doutr0),
wr1, [doutr1] "+r"(doutr1),
wr2, [doutr2] "+r"(doutr2),
vmask, [doutr3] "+r"(doutr3)
rmask, : [w0] "w"(wr0),
vzero, [w1] "w"(wr1),
vbias, [w2] "w"(wr2),
cnt, [vscale] "w"(vscale),
act_param); [bias_val] "r"(vbias),
[vmask] "r"(vmask),
[rmask] "r"(rmask),
[vzero] "w"(vzero)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21",
"v22",
"v23",
"v24",
"v25");
dout_ptr = dout_ptr + 4 * w_out; dout_ptr = dout_ptr + 4 * w_out;
} }
#else #else
...@@ -2525,100 +2727,28 @@ void conv_depthwise_3x3s1p1_bias(float *dout, ...@@ -2525,100 +2727,28 @@ void conv_depthwise_3x3s1p1_bias(float *dout,
int cnt = cnt_col; int cnt = cnt_col;
unsigned int *rmask_ptr = rmask; unsigned int *rmask_ptr = rmask;
unsigned int *vmask_ptr = vmask; unsigned int *vmask_ptr = vmask;
act_switch_3x3s1p1(din_ptr0, asm volatile(INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1_LEAKY_RELU
din_ptr1, MID_COMPUTE_S1 MID_RESULT_S1_LEAKY_RELU
din_ptr2, RIGHT_COMPUTE_S1 RIGHT_RESULT_S1_LEAKY_RELU
din_ptr3, : [dout_ptr1] "+r"(doutr0),
doutr0, [dout_ptr2] "+r"(doutr1),
doutr1, [din0_ptr] "+r"(din_ptr0),
wr0, [din1_ptr] "+r"(din_ptr1),
wr1, [din2_ptr] "+r"(din_ptr2),
wr2, [din3_ptr] "+r"(din_ptr3),
vmask_ptr, [cnt] "+r"(cnt),
rmask_ptr, [rmask] "+r"(rmask_ptr),
vzero, [vmask] "+r"(vmask_ptr)
bias_val,
cnt,
act_param);
dout_ptr += 2 * w_out;
} //! end of processing mid rows
#endif
}
}
}
void act_switch_3x3s1p1_s(const float *din_ptr0,
const float *din_ptr1,
const float *din_ptr2,
const float *din_ptr3,
float *doutr0,
float *doutr1,
float32x4_t wr0,
float32x4_t wr1,
float32x4_t wr2,
uint32x4_t vmask_rp,
float32x4_t vzero,
float32x4_t wbias,
const operators::ActivationParam act_param) {
#ifdef __aarch64__
float32x4_t vsix = vdupq_n_f32(act_param.Relu_clipped_coef);
float32x4_t vscale = vdupq_n_f32(act_param.Leaky_relu_alpha);
#else
float tmp = act_param.Relu_clipped_coef;
float ss = act_param.Leaky_relu_alpha;
float vsix[4] = {tmp, tmp, tmp, tmp};
float vscale[4] = {ss, ss, ss, ss};
#endif
switch (act_param.active_type) {
case lite_api::ActivationType::kRelu:
#ifdef __aarch64__
asm volatile(COMPUTE_S_S1 RESULT_S_S1_RELU
: [din0] "+r"(din_ptr0),
[din1] "+r"(din_ptr1),
[din2] "+r"(din_ptr2),
[din3] "+r"(din_ptr3)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[vzero] "w"(vzero),
[mask] "w"(vmask_rp),
[bias] "w"(wbias),
[out1] "r"(doutr0),
[out2] "r"(doutr1)
: "v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17");
break;
#else
asm volatile(COMPUTE_S_S1 RESULT_S_S1_RELU
: [din0] "+r"(din_ptr0),
[din1] "+r"(din_ptr1),
[din2] "+r"(din_ptr2),
[din3] "+r"(din_ptr3)
: [wr0] "w"(wr0), : [wr0] "w"(wr0),
[wr1] "w"(wr1), [wr1] "w"(wr1),
[wr2] "w"(wr2), [wr2] "w"(wr2),
[vzero] "w"(vzero), [bias_val] "r"(bias_val),
[mask] "w"(vmask_rp), [scale_ptr] "r"(scale),
[bias] "w"(wbias), [vzero] "w"(vzero)
[out1] "r"(doutr0),
[out2] "r"(doutr1)
: "cc", : "cc",
"memory", "memory",
"q4",
"q5",
"q6", "q6",
"q7", "q7",
"q8", "q8",
...@@ -2629,77 +2759,104 @@ void act_switch_3x3s1p1_s(const float *din_ptr0, ...@@ -2629,77 +2759,104 @@ void act_switch_3x3s1p1_s(const float *din_ptr0,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
break; dout_ptr += 2 * w_out;
} //! end of processing mid rows
#endif #endif
case lite_api::ActivationType::kRelu6: }
/* 0 <= din <= 6 */ }
}
void conv_depthwise_3x3s1p1_bias_s_relu6(float *dout,
const float *din,
const float *weights,
const float *bias,
const float *six,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext *ctx) {
const int right_pad_idx[4] = {3, 2, 1, 0};
const float zero[4] = {0.f, 0.f, 0.f, 0.f};
float32x4_t vzero = vdupq_n_f32(0.f);
uint32x4_t vmask_rp =
vcgeq_s32(vld1q_s32(right_pad_idx), vdupq_n_s32(4 - w_in));
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
#ifdef __aarch64__ #ifdef __aarch64__
asm volatile(COMPUTE_S_S1 RESULT_S_S1_RELU6 float32x4_t vsix = vld1q_f32(six);
: [din0] "+r"(din_ptr0),
[din1] "+r"(din_ptr1),
[din2] "+r"(din_ptr2),
[din3] "+r"(din_ptr3)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[vzero] "w"(vzero),
[mask] "w"(vmask_rp),
[bias] "w"(wbias),
[vsix] "w"(vsix),
[out1] "r"(doutr0),
[out2] "r"(doutr1)
: "v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17");
break;
#else
asm volatile(COMPUTE_S_S1 RESULT_S_S1_RELU6
: [din0] "+r"(din_ptr0),
[din1] "+r"(din_ptr1),
[din2] "+r"(din_ptr2),
[din3] "+r"(din_ptr3)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[vzero] "w"(vzero),
[mask] "w"(vmask_rp),
[bias] "w"(wbias),
[six_ptr] "r"(vsix),
[out1] "r"(doutr0),
[out2] "r"(doutr1)
: "cc",
"memory",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
break;
#endif #endif
case lite_api::ActivationType::kLeakyRelu: for (int n = 0; n < num; ++n) {
/*din = din >= 0 ? din : din * scale*/ const float *din_batch = din + n * ch_in * size_in_channel;
float *dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int i = 0; i < ch_in; ++i) {
float *dout_channel = dout_batch + i * size_out_channel;
const float *din_channel = din_batch + i * size_in_channel;
const float *weight_ptr = weights + i * 9;
float32x4_t wr0 = vld1q_f32(weight_ptr);
float32x4_t wr1 = vld1q_f32(weight_ptr + 3);
float32x4_t wr2 = vld1q_f32(weight_ptr + 6);
float32x4_t wbias;
if (flag_bias) {
wbias = vdupq_n_f32(bias[i]);
} else {
wbias = vdupq_n_f32(0.f);
}
float out_buf1[4];
float out_buf2[4];
float trash_buf[4];
float *doutr0 = dout_channel;
float *doutr1 = dout_channel + w_out;
const float *dr0 = din_channel;
const float *dr1 = dr0 + w_in;
const float *dr2 = dr1 + w_in;
const float *dr3 = dr2 + w_in;
for (int j = 0; j < h_out; j += 2) {
const float *din_ptr0 = dr0;
const float *din_ptr1 = dr1;
const float *din_ptr2 = dr2;
const float *din_ptr3 = dr3;
if (j == 0) {
din_ptr0 = zero;
din_ptr1 = dr0;
din_ptr2 = dr1;
din_ptr3 = dr2;
dr0 = dr1;
dr1 = dr2;
} else {
dr0 = dr2;
dr1 = dr3;
}
dr2 = dr1 + w_in;
dr3 = dr2 + w_in;
//! process bottom pad
if (j + 3 > h_in) {
switch (j + 3 - h_in) {
case 3:
din_ptr1 = zero;
case 2:
din_ptr2 = zero;
case 1:
din_ptr3 = zero;
default:
break;
}
}
//! process bottom remain
if (j + 2 > h_out) {
doutr1 = trash_buf;
}
#ifdef __aarch64__ #ifdef __aarch64__
asm volatile(COMPUTE_S_S1 RESULT_S_S1_LEAKY_RELU asm volatile(COMPUTE_S_S1 RESULT_S_S1_RELU6
: [din0] "+r"(din_ptr0), : [din0] "+r"(din_ptr0),
[din1] "+r"(din_ptr1), [din1] "+r"(din_ptr1),
[din2] "+r"(din_ptr2), [din2] "+r"(din_ptr2),
...@@ -2710,7 +2867,7 @@ void act_switch_3x3s1p1_s(const float *din_ptr0, ...@@ -2710,7 +2867,7 @@ void act_switch_3x3s1p1_s(const float *din_ptr0,
[vzero] "w"(vzero), [vzero] "w"(vzero),
[mask] "w"(vmask_rp), [mask] "w"(vmask_rp),
[bias] "w"(wbias), [bias] "w"(wbias),
[vscale] "w"(vscale), [vsix] "w"(vsix),
[out1] "r"(doutr0), [out1] "r"(doutr0),
[out2] "r"(doutr1) [out2] "r"(doutr1)
: "v0", : "v0",
...@@ -2730,13 +2887,9 @@ void act_switch_3x3s1p1_s(const float *din_ptr0, ...@@ -2730,13 +2887,9 @@ void act_switch_3x3s1p1_s(const float *din_ptr0,
"v14", "v14",
"v15", "v15",
"v16", "v16",
"v17", "v17");
"v18",
"v19",
"v20");
break;
#else #else
asm volatile(COMPUTE_S_S1 RESULT_S_S1_LEAKY_RELU asm volatile(COMPUTE_S_S1 RESULT_S_S1_RELU6
: [din0] "+r"(din_ptr0), : [din0] "+r"(din_ptr0),
[din1] "+r"(din_ptr1), [din1] "+r"(din_ptr1),
[din2] "+r"(din_ptr2), [din2] "+r"(din_ptr2),
...@@ -2747,7 +2900,7 @@ void act_switch_3x3s1p1_s(const float *din_ptr0, ...@@ -2747,7 +2900,7 @@ void act_switch_3x3s1p1_s(const float *din_ptr0,
[vzero] "w"(vzero), [vzero] "w"(vzero),
[mask] "w"(vmask_rp), [mask] "w"(vmask_rp),
[bias] "w"(wbias), [bias] "w"(wbias),
[scale_ptr] "r"(vscale), [six_ptr] "r"(six),
[out1] "r"(doutr0), [out1] "r"(doutr0),
[out2] "r"(doutr1) [out2] "r"(doutr1)
: "cc", : "cc",
...@@ -2762,21 +2915,23 @@ void act_switch_3x3s1p1_s(const float *din_ptr0, ...@@ -2762,21 +2915,23 @@ void act_switch_3x3s1p1_s(const float *din_ptr0,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
break;
#endif #endif
default: for (int w = 0; w < w_out; ++w) {
LOG(FATAL) << "this act_type: " << static_cast<int>(act_param.active_type) *doutr0++ = out_buf1[w];
<< " fuse not support"; *doutr1++ = out_buf2[w];
} }
doutr0 = doutr1;
doutr1 += w_out;
} // end of processing heights
} // end of processing channels
} // end of processing batchs
} }
/**
* \brief depthwise convolution, kernel size 3x3, stride 1, pad 1, with bias, void conv_depthwise_3x3s1p1_bias_s_leakyRelu(float *dout,
* width <= 4
*/
void conv_depthwise_3x3s1p1_bias_s(float *dout,
const float *din, const float *din,
const float *weights, const float *weights,
const float *bias, const float *bias,
const float *scale,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -2784,11 +2939,7 @@ void conv_depthwise_3x3s1p1_bias_s(float *dout, ...@@ -2784,11 +2939,7 @@ void conv_depthwise_3x3s1p1_bias_s(float *dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext *ctx) { ARMContext *ctx) {
//! 3x3s1 convolution, implemented by direct algorithm
//! pad is done implicit
//! for 4x6 convolution window
const int right_pad_idx[4] = {3, 2, 1, 0}; const int right_pad_idx[4] = {3, 2, 1, 0};
const float zero[4] = {0.f, 0.f, 0.f, 0.f}; const float zero[4] = {0.f, 0.f, 0.f, 0.f};
...@@ -2797,6 +2948,9 @@ void conv_depthwise_3x3s1p1_bias_s(float *dout, ...@@ -2797,6 +2948,9 @@ void conv_depthwise_3x3s1p1_bias_s(float *dout,
vcgeq_s32(vld1q_s32(right_pad_idx), vdupq_n_s32(4 - w_in)); vcgeq_s32(vld1q_s32(right_pad_idx), vdupq_n_s32(4 - w_in));
int size_in_channel = w_in * h_in; int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out; int size_out_channel = w_out * h_out;
#ifdef __aarch64__
float32x4_t vscale = vld1q_f32(scale);
#endif
for (int n = 0; n < num; ++n) { for (int n = 0; n < num; ++n) {
const float *din_batch = din + n * ch_in * size_in_channel; const float *din_batch = din + n * ch_in * size_in_channel;
float *dout_batch = dout + n * ch_in * size_out_channel; float *dout_batch = dout + n * ch_in * size_out_channel;
...@@ -2862,90 +3016,22 @@ void conv_depthwise_3x3s1p1_bias_s(float *dout, ...@@ -2862,90 +3016,22 @@ void conv_depthwise_3x3s1p1_bias_s(float *dout,
if (j + 2 > h_out) { if (j + 2 > h_out) {
doutr1 = trash_buf; doutr1 = trash_buf;
} }
act_switch_3x3s1p1_s(dr0_ptr,
dr1_ptr,
dr2_ptr,
dr3_ptr,
out_buf1,
out_buf2,
wr0,
wr1,
wr2,
vmask_rp,
vzero,
wbias,
act_param);
for (int w = 0; w < w_out; ++w) {
*doutr0++ = out_buf1[w];
*doutr1++ = out_buf2[w];
}
doutr0 = doutr1;
doutr1 += w_out;
} // end of processing heights
} // end of processing channels
} // end of processing batchs
}
#ifdef __aarch64__ #ifdef __aarch64__
void act_switch_3x3s1p0(const float *din_ptr0, asm volatile(COMPUTE_S_S1 RESULT_S_S1_LEAKY_RELU
const float *din_ptr1, : [din0] "+r"(dr0_ptr),
const float *din_ptr2, [din1] "+r"(dr1_ptr),
const float *din_ptr3, [din2] "+r"(dr2_ptr),
const float *din_ptr4, [din3] "+r"(dr3_ptr)
const float *din_ptr5, : [wr0] "w"(wr0),
float *doutr0, [wr1] "w"(wr1),
float *doutr1, [wr2] "w"(wr2),
float *doutr2,
float *doutr3,
float32x4_t wr0,
float32x4_t wr1,
float32x4_t wr2,
unsigned int *vmask,
unsigned int *rmask,
float32x4_t vzero,
float *vbias,
int cnt,
int remain,
const operators::ActivationParam act_param) {
float32x4_t vsix = vdupq_n_f32(act_param.Relu_clipped_coef);
float32x4_t vscale = vdupq_n_f32(act_param.Leaky_relu_alpha);
switch (act_param.active_type) {
case lite_api::ActivationType::kRelu:
asm volatile(
INIT_S1
"ld1 {v8.4s}, [%[din_ptr4]], #16 \n" /*vld1q_f32(din_ptr0)*/
"ld1 {v10.4s}, [%[din_ptr5]], #16 \n" /*vld1q_f32(din_ptr0)*/
"ext v16.16b, v0.16b, v1.16b, #4 \n" /* v16 = 1234 */
"ext v17.16b, v0.16b, v1.16b, #8 \n" /* v17 = 2345 */
"ld1 {v9.4s}, [%[din_ptr4]] \n" /*vld1q_f32(din_ptr0)*/
"ld1 {v11.4s}, [%[din_ptr5]] \n" /*vld1q_f32(din_ptr0)*/
MID_COMPUTE_S1 MID_RESULT_S1_RELU
"cmp %w[remain], #1 \n"
"blt 0f \n" RIGHT_COMPUTE_S1
RIGHT_RESULT_S1_RELU "0: \n"
: [cnt] "+r"(cnt),
[din_ptr0] "+r"(din_ptr0),
[din_ptr1] "+r"(din_ptr1),
[din_ptr2] "+r"(din_ptr2),
[din_ptr3] "+r"(din_ptr3),
[din_ptr4] "+r"(din_ptr4),
[din_ptr5] "+r"(din_ptr5),
[doutr0] "+r"(doutr0),
[doutr1] "+r"(doutr1),
[doutr2] "+r"(doutr2),
[doutr3] "+r"(doutr3)
: [w0] "w"(wr0),
[w1] "w"(wr1),
[w2] "w"(wr2),
[bias_val] "r"(vbias),
[vmask] "r"(vmask),
[rmask] "r"(rmask),
[vzero] "w"(vzero), [vzero] "w"(vzero),
[remain] "r"(remain) [mask] "w"(vmask_rp),
: "cc", [bias] "w"(wbias),
"memory", [vscale] "w"(vscale),
"v0", [out1] "r"(doutr0),
[out2] "r"(doutr1)
: "v0",
"v1", "v1",
"v2", "v2",
"v3", "v3",
...@@ -2962,18 +3048,196 @@ void act_switch_3x3s1p0(const float *din_ptr0, ...@@ -2962,18 +3048,196 @@ void act_switch_3x3s1p0(const float *din_ptr0,
"v14", "v14",
"v15", "v15",
"v16", "v16",
"v17", "v17");
"v18", #else
"v19", asm volatile(COMPUTE_S_S1 RESULT_S_S1_LEAKY_RELU
"v20", : [din0] "+r"(dr0_ptr),
"v21", [din1] "+r"(dr1_ptr),
"v22", [din2] "+r"(dr2_ptr),
"v23", [din3] "+r"(dr3_ptr)
"v24", : [wr0] "w"(wr0),
"v25"); [wr1] "w"(wr1),
[wr2] "w"(wr2),
[vzero] "w"(vzero),
[mask] "w"(vmask_rp),
[bias] "w"(wbias),
[scale_ptr] "r"(scale),
[out1] "r"(doutr0),
[out2] "r"(doutr1)
: "cc",
"memory",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
#endif
for (int w = 0; w < w_out; ++w) {
*doutr0++ = out_buf1[w];
*doutr1++ = out_buf2[w];
}
doutr0 = doutr1;
doutr1 += w_out;
} // end of processing heights
} // end of processing channels
} // end of processing batchs
}
void conv_depthwise_3x3s1p0_bias_relu6(float *dout,
const float *din,
const float *weights,
const float *bias,
const float *six,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext *ctx) {
//! pad is done implicit
const float zero[8] = {0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f};
//! for 4x6 convolution window
const unsigned int right_pad_idx[8] = {5, 4, 3, 2, 1, 0, 0, 0};
float *zero_ptr = ctx->workspace_data<float>();
memset(zero_ptr, 0, w_in * sizeof(float));
float *write_ptr = zero_ptr + w_in;
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
int w_stride = 9;
int tile_w = w_out >> 2;
int remain = w_out % 4;
unsigned int size_pad_right = (unsigned int)(6 + (tile_w << 2) - w_in);
const int remian_idx[4] = {0, 1, 2, 3};
#ifdef __aarch64__
float32x4_t vsix = vld1q_f32(six);
#endif
if (remain == 0 && size_pad_right == 6) { // w_in == w_out and w_out % 4 == 0
tile_w -= 1;
remain = 4;
size_pad_right = 2;
}
uint32x4_t vmask_rp1 =
vcgeq_u32(vld1q_u32(right_pad_idx), vdupq_n_u32(size_pad_right));
uint32x4_t vmask_rp2 =
vcgeq_u32(vld1q_u32(right_pad_idx + 4), vdupq_n_u32(size_pad_right));
uint32x4_t vmask_result =
vcgtq_s32(vdupq_n_s32(remain), vld1q_s32(remian_idx));
unsigned int vmask[8];
vst1q_u32(vmask, vmask_rp1);
vst1q_u32(vmask + 4, vmask_rp2);
unsigned int rmask[4];
vst1q_u32(rmask, vmask_result);
float32x4_t vzero = vdupq_n_f32(0.f);
for (int n = 0; n < num; ++n) {
const float *din_batch = din + n * ch_in * size_in_channel;
float *dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int c = 0; c < ch_in; c++) {
float *dout_ptr = dout_batch + c * size_out_channel;
const float *din_ch_ptr = din_batch + c * size_in_channel;
float bias_val = flag_bias ? bias[c] : 0.f;
float vbias[4] = {bias_val, bias_val, bias_val, bias_val};
const float *wei_ptr = weights + c * w_stride;
float32x4_t wr0 = vld1q_f32(wei_ptr);
float32x4_t wr1 = vld1q_f32(wei_ptr + 3);
float32x4_t wr2 = vld1q_f32(wei_ptr + 6);
float *doutr0 = dout_ptr;
float *doutr1 = doutr0 + w_out;
float *doutr2 = doutr1 + w_out;
float *doutr3 = doutr2 + w_out;
const float *dr0 = din_ch_ptr;
const float *dr1 = dr0 + w_in;
const float *dr2 = dr1 + w_in;
const float *dr3 = dr2 + w_in;
const float *dr4 = dr3 + w_in;
const float *dr5 = dr4 + w_in;
const float *din_ptr0 = dr0;
const float *din_ptr1 = dr1;
const float *din_ptr2 = dr2;
const float *din_ptr3 = dr3;
const float *din_ptr4 = dr4;
const float *din_ptr5 = dr5;
float *ptr_zero = const_cast<float *>(zero);
#ifdef __aarch64__
for (int i = 0; i < h_out; i += 4) {
//! process top pad pad_h = 1
din_ptr0 = dr0;
din_ptr1 = dr1;
din_ptr2 = dr2;
din_ptr3 = dr3;
din_ptr4 = dr4;
din_ptr5 = dr5;
doutr0 = dout_ptr;
doutr1 = doutr0 + w_out;
doutr2 = doutr1 + w_out;
doutr3 = doutr2 + w_out;
dr0 = dr4;
dr1 = dr5;
dr2 = dr1 + w_in;
dr3 = dr2 + w_in;
dr4 = dr3 + w_in;
dr5 = dr4 + w_in;
//! process bottom pad
if (i + 5 >= h_in) {
switch (i + 5 - h_in) {
case 4:
din_ptr1 = zero_ptr;
case 3:
din_ptr2 = zero_ptr;
case 2:
din_ptr3 = zero_ptr;
case 1:
din_ptr4 = zero_ptr;
case 0:
din_ptr5 = zero_ptr;
default:
break; break;
case lite_api::ActivationType::kRelu6: }
/* 0 <= din <= 6 */ }
//! process bottom remain
if (i + 4 > h_out) {
switch (i + 4 - h_out) {
case 3:
doutr1 = write_ptr;
case 2:
doutr2 = write_ptr;
case 1:
doutr3 = write_ptr;
default:
break;
}
}
int cnt = tile_w;
asm volatile( asm volatile(
INIT_S1 INIT_S1
"ld1 {v8.4s}, [%[din_ptr4]], #16 \n" /*vld1q_f32(din_ptr0)*/ "ld1 {v8.4s}, [%[din_ptr4]], #16 \n" /*vld1q_f32(din_ptr0)*/
...@@ -3033,98 +3297,42 @@ void act_switch_3x3s1p0(const float *din_ptr0, ...@@ -3033,98 +3297,42 @@ void act_switch_3x3s1p0(const float *din_ptr0,
"v23", "v23",
"v24", "v24",
"v25"); "v25");
break; dout_ptr = dout_ptr + 4 * w_out;
case lite_api::ActivationType::kLeakyRelu:
/*din = din >= 0 ? din : din * scale*/
asm volatile(
INIT_S1
"ld1 {v8.4s}, [%[din_ptr4]], #16 \n" /*vld1q_f32(din_ptr0)*/
"ld1 {v10.4s}, [%[din_ptr5]], #16 \n" /*vld1q_f32(din_ptr0)*/
"ext v16.16b, v0.16b, v1.16b, #4 \n" /* v16 = 1234 */
"ext v17.16b, v0.16b, v1.16b, #8 \n" /* v17 = 2345 */
"ld1 {v9.4s}, [%[din_ptr4]] \n" /*vld1q_f32(din_ptr0)*/
"ld1 {v11.4s}, [%[din_ptr5]] \n" /*vld1q_f32(din_ptr0)*/
MID_COMPUTE_S1 MID_RESULT_S1_LEAKY_RELU
"cmp %w[remain], #1 \n"
"blt 0f \n" RIGHT_COMPUTE_S1
RIGHT_RESULT_S1_LEAKY_RELU "0: \n"
: [cnt] "+r"(cnt),
[din_ptr0] "+r"(din_ptr0),
[din_ptr1] "+r"(din_ptr1),
[din_ptr2] "+r"(din_ptr2),
[din_ptr3] "+r"(din_ptr3),
[din_ptr4] "+r"(din_ptr4),
[din_ptr5] "+r"(din_ptr5),
[doutr0] "+r"(doutr0),
[doutr1] "+r"(doutr1),
[doutr2] "+r"(doutr2),
[doutr3] "+r"(doutr3)
: [w0] "w"(wr0),
[w1] "w"(wr1),
[w2] "w"(wr2),
[vscale] "w"(vscale),
[bias_val] "r"(vbias),
[vmask] "r"(vmask),
[rmask] "r"(rmask),
[remain] "r"(remain)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21",
"v22",
"v23",
"v24",
"v25");
break;
default:
LOG(FATAL) << "this act_type: " << static_cast<int>(act_param.active_type)
<< " fuse not support";
} }
}
#else #else
void act_switch_3x3s1p0(const float *din_ptr0, for (int i = 0; i < h_out; i += 2) {
const float *din_ptr1, din_ptr0 = dr0;
const float *din_ptr2, din_ptr1 = dr1;
const float *din_ptr3, din_ptr2 = dr2;
float *doutr0, din_ptr3 = dr3;
float *doutr1,
float32x4_t wr0,
float32x4_t wr1,
float32x4_t wr2,
unsigned int *vmask_ptr,
unsigned int *rmask_ptr,
float32x4_t vzero,
float bias_val,
int cnt,
int remain,
const operators::ActivationParam act_param) {
float tmp = act_param.Relu_clipped_coef;
float ss = act_param.Leaky_relu_alpha;
float vsix[4] = {tmp, tmp, tmp, tmp};
float vscale[4] = {ss, ss, ss, ss};
switch (act_param.active_type) { doutr0 = dout_ptr;
case lite_api::ActivationType::kRelu: doutr1 = dout_ptr + w_out;
dr0 = dr2;
dr1 = dr3;
dr2 = dr1 + w_in;
dr3 = dr2 + w_in;
//! process bottom pad
if (i + 4 > h_in) {
switch (i + 4 - h_in) {
case 3:
din_ptr1 = zero_ptr;
case 2:
din_ptr2 = zero_ptr;
case 1:
din_ptr3 = zero_ptr;
default:
break;
}
}
//! process bottom remain
if (i + 2 > h_out) {
doutr1 = write_ptr;
}
int cnt = tile_w;
unsigned int *rmask_ptr = rmask;
unsigned int *vmask_ptr = vmask;
asm volatile(INIT_S1 asm volatile(INIT_S1
"sub %[din0_ptr], #8 @ 0pad + 2 float data overlap\n" "sub %[din0_ptr], #8 @ 0pad + 2 float data overlap\n"
"sub %[din1_ptr], #8 @ 0pad + 2 float data overlap\n" "sub %[din1_ptr], #8 @ 0pad + 2 float data overlap\n"
...@@ -3132,10 +3340,10 @@ void act_switch_3x3s1p0(const float *din_ptr0, ...@@ -3132,10 +3340,10 @@ void act_switch_3x3s1p0(const float *din_ptr0,
"sub %[din3_ptr], #8 @ 0pad + 2 float data overlap\n" "sub %[din3_ptr], #8 @ 0pad + 2 float data overlap\n"
"vext.32 q6, q8, q9, #1 @ 0012\n" "vext.32 q6, q8, q9, #1 @ 0012\n"
"vext.32 q7, q8, q9, #2 @ 1234\n" MID_COMPUTE_S1 "vext.32 q7, q8, q9, #2 @ 1234\n" MID_COMPUTE_S1
MID_RESULT_S1_RELU MID_RESULT_S1_RELU6
"cmp %[remain], #1 \n" "cmp %[remain], #1 \n"
"blt 0f \n" RIGHT_COMPUTE_S1 "blt 0f \n" RIGHT_COMPUTE_S1
RIGHT_RESULT_S1_RELU "0: \n" RIGHT_RESULT_S1_RELU6 "0: \n"
: [dout_ptr1] "+r"(doutr0), : [dout_ptr1] "+r"(doutr0),
[dout_ptr2] "+r"(doutr1), [dout_ptr2] "+r"(doutr1),
[din0_ptr] "+r"(din_ptr0), [din0_ptr] "+r"(din_ptr0),
...@@ -3148,6 +3356,7 @@ void act_switch_3x3s1p0(const float *din_ptr0, ...@@ -3148,6 +3356,7 @@ void act_switch_3x3s1p0(const float *din_ptr0,
: [wr0] "w"(wr0), : [wr0] "w"(wr0),
[wr1] "w"(wr1), [wr1] "w"(wr1),
[wr2] "w"(wr2), [wr2] "w"(wr2),
[six_ptr] "r"(six),
[bias_val] "r"(bias_val), [bias_val] "r"(bias_val),
[vzero] "w"(vzero), [vzero] "w"(vzero),
[remain] "r"(remain) [remain] "r"(remain)
...@@ -3165,81 +3374,146 @@ void act_switch_3x3s1p0(const float *din_ptr0, ...@@ -3165,81 +3374,146 @@ void act_switch_3x3s1p0(const float *din_ptr0,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
dout_ptr += 2 * w_out;
} //! end of processing mid rows
#endif
}
}
}
void conv_depthwise_3x3s1p0_bias_s_relu6(float *dout,
const float *din,
const float *weights,
const float *bias,
const float *six,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext *ctx) {
const int right_pad_idx[8] = {5, 4, 3, 2, 1, 0, 0, 0};
const float zero_ptr[4] = {0.f, 0.f, 0.f, 0.f};
float32x4_t vzero = vdupq_n_f32(0.f);
uint32x4_t vmask_rp1 =
vcgeq_s32(vld1q_s32(right_pad_idx), vdupq_n_s32(6 - w_in));
uint32x4_t vmask_rp2 =
vcgeq_s32(vld1q_s32(right_pad_idx + 4), vdupq_n_s32(6 - w_in));
#ifdef __aarch64__
float32x4_t vsix = vld1q_f32(six);
#endif
unsigned int vmask[8];
vst1q_u32(vmask, vmask_rp1);
vst1q_u32(vmask + 4, vmask_rp2);
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
for (int n = 0; n < num; ++n) {
const float *din_batch = din + n * ch_in * size_in_channel;
float *dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int i = 0; i < ch_in; ++i) {
float *dout_channel = dout_batch + i * size_out_channel;
const float *din_channel = din_batch + i * size_in_channel;
const float *weight_ptr = weights + i * 9;
float32x4_t wr0 = vld1q_f32(weight_ptr);
float32x4_t wr1 = vld1q_f32(weight_ptr + 3);
float32x4_t wr2 = vld1q_f32(weight_ptr + 6);
float32x4_t wbias;
float bias_val = 0.f;
if (flag_bias) {
wbias = vdupq_n_f32(bias[i]);
bias_val = bias[i];
} else {
wbias = vdupq_n_f32(0.f);
}
float out_buf1[4];
float out_buf2[4];
float trash_buf[4];
float *doutr0 = dout_channel;
float *doutr1 = dout_channel + w_out;
for (int j = 0; j < h_out; j += 2) {
const float *dr0 = din_channel + j * w_in;
const float *dr1 = dr0 + w_in;
const float *dr2 = dr1 + w_in;
const float *dr3 = dr2 + w_in;
doutr0 = dout_channel + j * w_out;
doutr1 = doutr0 + w_out;
if (j + 4 > h_in) {
switch (j + 4 - h_in) {
case 3:
dr1 = zero_ptr;
case 2:
dr2 = zero_ptr;
case 1:
dr3 = zero_ptr;
default:
break; break;
case lite_api::ActivationType::kRelu6: }
/* 0 <= din <= 6 */ }
asm volatile(INIT_S1 if (j + 2 > h_out) {
"sub %[din0_ptr], #8 @ 0pad + 2 float data overlap\n" doutr1 = trash_buf;
"sub %[din1_ptr], #8 @ 0pad + 2 float data overlap\n" }
"sub %[din2_ptr], #8 @ 0pad + 2 float data overlap\n" unsigned int *vmask_ptr = vmask;
"sub %[din3_ptr], #8 @ 0pad + 2 float data overlap\n" #ifdef __aarch64__
"vext.32 q6, q8, q9, #1 @ 0012\n" asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1_RELU6
"vext.32 q7, q8, q9, #2 @ 1234\n" MID_COMPUTE_S1 : [din0] "+r"(dr0),
MID_RESULT_S1_RELU6 [din1] "+r"(dr1),
"cmp %[remain], #1 \n" [din2] "+r"(dr2),
"blt 0f \n" RIGHT_COMPUTE_S1 [din3] "+r"(dr3)
RIGHT_RESULT_S1_RELU6 "0: \n" : [wr0] "w"(wr0),
: [dout_ptr1] "+r"(doutr0), [wr1] "w"(wr1),
[dout_ptr2] "+r"(doutr1), [wr2] "w"(wr2),
[din0_ptr] "+r"(din_ptr0), [vbias] "w"(wbias),
[din1_ptr] "+r"(din_ptr1), [mask1] "w"(vmask_rp1),
[din2_ptr] "+r"(din_ptr2), [mask2] "w"(vmask_rp2),
[din3_ptr] "+r"(din_ptr3), [vzero] "w"(vzero),
[cnt] "+r"(cnt), [vsix] "w"(vsix),
[rmask] "+r"(rmask_ptr), [out1] "r"(doutr0),
[out2] "r"(doutr1)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15");
#else
asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1_RELU6
: [din0] "+r"(dr0),
[din1] "+r"(dr1),
[din2] "+r"(dr2),
[din3] "+r"(dr3),
[vmask] "+r"(vmask_ptr) [vmask] "+r"(vmask_ptr)
: [wr0] "w"(wr0), : [wr0] "w"(wr0),
[wr1] "w"(wr1), [wr1] "w"(wr1),
[wr2] "w"(wr2), [wr2] "w"(wr2),
[six_ptr] "r"(vsix),
[bias_val] "r"(bias_val),
[vzero] "w"(vzero), [vzero] "w"(vzero),
[remain] "r"(remain) [six_ptr] "r"(six),
: "cc",
"memory",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
break;
case lite_api::ActivationType::kLeakyRelu:
/*din = din >= 0 ? din : din * scale*/
asm volatile(INIT_S1
"sub %[din0_ptr], #8 @ 0pad + 2 float data overlap\n"
"sub %[din1_ptr], #8 @ 0pad + 2 float data overlap\n"
"sub %[din2_ptr], #8 @ 0pad + 2 float data overlap\n"
"sub %[din3_ptr], #8 @ 0pad + 2 float data overlap\n"
"vext.32 q6, q8, q9, #1 @ 0012\n"
"vext.32 q7, q8, q9, #2 @ 1234\n" MID_COMPUTE_S1
MID_RESULT_S1_LEAKY_RELU
"cmp %[remain], #1 \n"
"blt 0f \n" RIGHT_COMPUTE_S1
RIGHT_RESULT_S1_LEAKY_RELU
"0: \n"
: [dout_ptr1] "+r"(doutr0),
[dout_ptr2] "+r"(doutr1),
[din0_ptr] "+r"(din_ptr0),
[din1_ptr] "+r"(din_ptr1),
[din2_ptr] "+r"(din_ptr2),
[din3_ptr] "+r"(din_ptr3),
[cnt] "+r"(cnt),
[rmask] "+r"(rmask_ptr),
[vmask] "+r"(vmask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[scale_ptr] "r"(vscale),
[bias_val] "r"(bias_val), [bias_val] "r"(bias_val),
[vzero] "w"(vzero), [out1] "r"(doutr0),
[remain] "r"(remain) [out2] "r"(doutr1)
: "cc", : "cc",
"memory", "memory",
"q4", "q4",
...@@ -3254,21 +3528,21 @@ void act_switch_3x3s1p0(const float *din_ptr0, ...@@ -3254,21 +3528,21 @@ void act_switch_3x3s1p0(const float *din_ptr0,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
break; #endif
default: for (int w = 0; w < w_out; ++w) {
LOG(FATAL) << "this act_type: " << static_cast<int>(act_param.active_type) *doutr0++ = out_buf1[w];
<< " fuse not support"; *doutr1++ = out_buf2[w];
} }
} // end of processing heights
} // end of processing channels
} // end of processing batchs
} }
#endif
/** void conv_depthwise_3x3s1p0_bias_leakyRelu(float *dout,
* \brief depthwise convolution, kernel size 3x3, stride 1, pad 1, with bias,
* width > 4
*/
void conv_depthwise_3x3s1p0_bias(float *dout,
const float *din, const float *din,
const float *weights, const float *weights,
const float *bias, const float *bias,
const float *scale,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -3276,7 +3550,6 @@ void conv_depthwise_3x3s1p0_bias(float *dout, ...@@ -3276,7 +3550,6 @@ void conv_depthwise_3x3s1p0_bias(float *dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext *ctx) { ARMContext *ctx) {
//! pad is done implicit //! pad is done implicit
const float zero[8] = {0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f}; const float zero[8] = {0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f};
...@@ -3297,6 +3570,10 @@ void conv_depthwise_3x3s1p0_bias(float *dout, ...@@ -3297,6 +3570,10 @@ void conv_depthwise_3x3s1p0_bias(float *dout,
unsigned int size_pad_right = (unsigned int)(6 + (tile_w << 2) - w_in); unsigned int size_pad_right = (unsigned int)(6 + (tile_w << 2) - w_in);
const int remian_idx[4] = {0, 1, 2, 3}; const int remian_idx[4] = {0, 1, 2, 3};
#ifdef __aarch64__
float32x4_t vscale = vld1q_f32(scale);
#endif
if (remain == 0 && size_pad_right == 6) { // w_in == w_out and w_out % 4 == 0 if (remain == 0 && size_pad_right == 6) { // w_in == w_out and w_out % 4 == 0
tile_w -= 1; tile_w -= 1;
remain = 4; remain = 4;
...@@ -3372,300 +3649,76 @@ void conv_depthwise_3x3s1p0_bias(float *dout, ...@@ -3372,300 +3649,76 @@ void conv_depthwise_3x3s1p0_bias(float *dout,
doutr2 = doutr1 + w_out; doutr2 = doutr1 + w_out;
doutr3 = doutr2 + w_out; doutr3 = doutr2 + w_out;
dr0 = dr4; dr0 = dr4;
dr1 = dr5; dr1 = dr5;
dr2 = dr1 + w_in; dr2 = dr1 + w_in;
dr3 = dr2 + w_in; dr3 = dr2 + w_in;
dr4 = dr3 + w_in; dr4 = dr3 + w_in;
dr5 = dr4 + w_in; dr5 = dr4 + w_in;
//! process bottom pad //! process bottom pad
if (i + 5 >= h_in) { if (i + 5 >= h_in) {
switch (i + 5 - h_in) { switch (i + 5 - h_in) {
case 4: case 4:
din_ptr1 = zero_ptr; din_ptr1 = zero_ptr;
case 3: case 3:
din_ptr2 = zero_ptr; din_ptr2 = zero_ptr;
case 2: case 2:
din_ptr3 = zero_ptr; din_ptr3 = zero_ptr;
case 1: case 1:
din_ptr4 = zero_ptr; din_ptr4 = zero_ptr;
case 0: case 0:
din_ptr5 = zero_ptr; din_ptr5 = zero_ptr;
default: default:
break;
}
}
//! process bottom remain
if (i + 4 > h_out) {
switch (i + 4 - h_out) {
case 3:
doutr1 = write_ptr;
case 2:
doutr2 = write_ptr;
case 1:
doutr3 = write_ptr;
default:
break;
}
}
int cnt = tile_w;
act_switch_3x3s1p0(din_ptr0,
din_ptr1,
din_ptr2,
din_ptr3,
din_ptr4,
din_ptr5,
doutr0,
doutr1,
doutr2,
doutr3,
wr0,
wr1,
wr2,
vmask,
rmask,
vzero,
vbias,
cnt,
remain,
act_param);
dout_ptr = dout_ptr + 4 * w_out;
}
#else
for (int i = 0; i < h_out; i += 2) {
din_ptr0 = dr0;
din_ptr1 = dr1;
din_ptr2 = dr2;
din_ptr3 = dr3;
doutr0 = dout_ptr;
doutr1 = dout_ptr + w_out;
dr0 = dr2;
dr1 = dr3;
dr2 = dr1 + w_in;
dr3 = dr2 + w_in;
//! process bottom pad
if (i + 4 > h_in) {
switch (i + 4 - h_in) {
case 3:
din_ptr1 = zero_ptr;
case 2:
din_ptr2 = zero_ptr;
case 1:
din_ptr3 = zero_ptr;
default:
break;
}
}
//! process bottom remain
if (i + 2 > h_out) {
doutr1 = write_ptr;
}
int cnt = tile_w;
unsigned int *rmask_ptr = rmask;
unsigned int *vmask_ptr = vmask;
act_switch_3x3s1p0(din_ptr0,
din_ptr1,
din_ptr2,
din_ptr3,
doutr0,
doutr1,
wr0,
wr1,
wr2,
vmask_ptr,
rmask_ptr,
vzero,
bias_val,
cnt,
remain,
act_param);
dout_ptr += 2 * w_out;
} //! end of processing mid rows
#endif
}
}
}
void act_switch_3x3s1p0_s(const float *din_ptr0,
const float *din_ptr1,
const float *din_ptr2,
const float *din_ptr3,
float *doutr0,
float *doutr1,
float32x4_t wr0,
float32x4_t wr1,
float32x4_t wr2,
uint32x4_t vmask_rp1,
uint32x4_t vmask_rp2,
float32x4_t vzero,
float32x4_t wbias,
unsigned int *vmask_ptr,
float bias_val,
const operators::ActivationParam act_param) {
#ifdef __aarch64__
float32x4_t vsix = vdupq_n_f32(act_param.Relu_clipped_coef);
float32x4_t vscale = vdupq_n_f32(act_param.Leaky_relu_alpha);
#else
float tmp = act_param.Relu_clipped_coef;
float ss = act_param.Leaky_relu_alpha;
float vsix[4] = {tmp, tmp, tmp, tmp};
float vscale[4] = {ss, ss, ss, ss};
#endif
switch (act_param.active_type) {
case lite_api::ActivationType::kRelu:
#ifdef __aarch64__
asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1_RELU
: [din0] "+r"(din_ptr0),
[din1] "+r"(din_ptr1),
[din2] "+r"(din_ptr2),
[din3] "+r"(din_ptr3)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[vbias] "w"(wbias),
[mask1] "w"(vmask_rp1),
[mask2] "w"(vmask_rp2),
[vzero] "w"(vzero),
[out1] "r"(doutr0),
[out2] "r"(doutr1)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15");
break;
#else
asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1_RELU
: [din0] "+r"(din_ptr0),
[din1] "+r"(din_ptr1),
[din2] "+r"(din_ptr2),
[din3] "+r"(din_ptr3),
[vmask] "+r"(vmask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[vzero] "w"(vzero),
[bias_val] "r"(bias_val),
[out1] "r"(doutr0),
[out2] "r"(doutr1)
: "cc",
"memory",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
break;
#endif
case lite_api::ActivationType::kRelu6:
/* 0 <= din <= 6 */
#ifdef __aarch64__
asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1_RELU6
: [din0] "+r"(din_ptr0),
[din1] "+r"(din_ptr1),
[din2] "+r"(din_ptr2),
[din3] "+r"(din_ptr3)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[vbias] "w"(wbias),
[mask1] "w"(vmask_rp1),
[mask2] "w"(vmask_rp2),
[vzero] "w"(vzero),
[vsix] "w"(vsix),
[out1] "r"(doutr0),
[out2] "r"(doutr1)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15");
break; break;
#else }
asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1_RELU6 }
: [din0] "+r"(din_ptr0), //! process bottom remain
[din1] "+r"(din_ptr1), if (i + 4 > h_out) {
[din2] "+r"(din_ptr2), switch (i + 4 - h_out) {
[din3] "+r"(din_ptr3), case 3:
[vmask] "+r"(vmask_ptr) doutr1 = write_ptr;
: [wr0] "w"(wr0), case 2:
[wr1] "w"(wr1), doutr2 = write_ptr;
[wr2] "w"(wr2), case 1:
[vzero] "w"(vzero), doutr3 = write_ptr;
[six_ptr] "r"(vsix), default:
[bias_val] "r"(bias_val),
[out1] "r"(doutr0),
[out2] "r"(doutr1)
: "cc",
"memory",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
break; break;
#endif }
case lite_api::ActivationType::kLeakyRelu: }
/*din = din >= 0 ? din : din * scale*/
#ifdef __aarch64__ int cnt = tile_w;
asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1_LEAKY_RELU asm volatile(
: [din0] "+r"(din_ptr0), INIT_S1
[din1] "+r"(din_ptr1), "ld1 {v8.4s}, [%[din_ptr4]], #16 \n" /*vld1q_f32(din_ptr0)*/
[din2] "+r"(din_ptr2), "ld1 {v10.4s}, [%[din_ptr5]], #16 \n" /*vld1q_f32(din_ptr0)*/
[din3] "+r"(din_ptr3) "ext v16.16b, v0.16b, v1.16b, #4 \n" /* v16 = 1234 */
: [wr0] "w"(wr0), "ext v17.16b, v0.16b, v1.16b, #8 \n" /* v17 = 2345 */
[wr1] "w"(wr1), "ld1 {v9.4s}, [%[din_ptr4]] \n" /*vld1q_f32(din_ptr0)*/
[wr2] "w"(wr2), "ld1 {v11.4s}, [%[din_ptr5]] \n" /*vld1q_f32(din_ptr0)*/
[vbias] "w"(wbias), MID_COMPUTE_S1 MID_RESULT_S1_LEAKY_RELU
[mask1] "w"(vmask_rp1), "cmp %w[remain], #1 \n"
[mask2] "w"(vmask_rp2), "blt 0f \n" RIGHT_COMPUTE_S1
[vzero] "w"(vzero), RIGHT_RESULT_S1_LEAKY_RELU "0: \n"
: [cnt] "+r"(cnt),
[din_ptr0] "+r"(din_ptr0),
[din_ptr1] "+r"(din_ptr1),
[din_ptr2] "+r"(din_ptr2),
[din_ptr3] "+r"(din_ptr3),
[din_ptr4] "+r"(din_ptr4),
[din_ptr5] "+r"(din_ptr5),
[doutr0] "+r"(doutr0),
[doutr1] "+r"(doutr1),
[doutr2] "+r"(doutr2),
[doutr3] "+r"(doutr3)
: [w0] "w"(wr0),
[w1] "w"(wr1),
[w2] "w"(wr2),
[vscale] "w"(vscale), [vscale] "w"(vscale),
[out1] "r"(doutr0), [bias_val] "r"(vbias),
[out2] "r"(doutr1) [vmask] "r"(vmask),
[rmask] "r"(rmask),
[remain] "r"(remain)
: "cc", : "cc",
"memory", "memory",
"v0", "v0",
...@@ -3683,23 +3736,81 @@ void act_switch_3x3s1p0_s(const float *din_ptr0, ...@@ -3683,23 +3736,81 @@ void act_switch_3x3s1p0_s(const float *din_ptr0,
"v12", "v12",
"v13", "v13",
"v14", "v14",
"v15"); "v15",
break; "v16",
"v17",
"v18",
"v19",
"v20",
"v21",
"v22",
"v23",
"v24",
"v25");
dout_ptr = dout_ptr + 4 * w_out;
}
#else #else
asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1_LEAKY_RELU for (int i = 0; i < h_out; i += 2) {
: [din0] "+r"(din_ptr0), din_ptr0 = dr0;
[din1] "+r"(din_ptr1), din_ptr1 = dr1;
[din2] "+r"(din_ptr2), din_ptr2 = dr2;
[din3] "+r"(din_ptr3), din_ptr3 = dr3;
doutr0 = dout_ptr;
doutr1 = dout_ptr + w_out;
dr0 = dr2;
dr1 = dr3;
dr2 = dr1 + w_in;
dr3 = dr2 + w_in;
//! process bottom pad
if (i + 4 > h_in) {
switch (i + 4 - h_in) {
case 3:
din_ptr1 = zero_ptr;
case 2:
din_ptr2 = zero_ptr;
case 1:
din_ptr3 = zero_ptr;
default:
break;
}
}
//! process bottom remain
if (i + 2 > h_out) {
doutr1 = write_ptr;
}
int cnt = tile_w;
unsigned int *rmask_ptr = rmask;
unsigned int *vmask_ptr = vmask;
asm volatile(INIT_S1
"sub %[din0_ptr], #8 @ 0pad + 2 float data overlap\n"
"sub %[din1_ptr], #8 @ 0pad + 2 float data overlap\n"
"sub %[din2_ptr], #8 @ 0pad + 2 float data overlap\n"
"sub %[din3_ptr], #8 @ 0pad + 2 float data overlap\n"
"vext.32 q6, q8, q9, #1 @ 0012\n"
"vext.32 q7, q8, q9, #2 @ 1234\n" MID_COMPUTE_S1
MID_RESULT_S1_LEAKY_RELU
"cmp %[remain], #1 \n"
"blt 0f \n" RIGHT_COMPUTE_S1
RIGHT_RESULT_S1_LEAKY_RELU
"0: \n"
: [dout_ptr1] "+r"(doutr0),
[dout_ptr2] "+r"(doutr1),
[din0_ptr] "+r"(din_ptr0),
[din1_ptr] "+r"(din_ptr1),
[din2_ptr] "+r"(din_ptr2),
[din3_ptr] "+r"(din_ptr3),
[cnt] "+r"(cnt),
[rmask] "+r"(rmask_ptr),
[vmask] "+r"(vmask_ptr) [vmask] "+r"(vmask_ptr)
: [wr0] "w"(wr0), : [wr0] "w"(wr0),
[wr1] "w"(wr1), [wr1] "w"(wr1),
[wr2] "w"(wr2), [wr2] "w"(wr2),
[vzero] "w"(vzero), [scale_ptr] "r"(scale),
[scale_ptr] "r"(vscale),
[bias_val] "r"(bias_val), [bias_val] "r"(bias_val),
[out1] "r"(doutr0), [vzero] "w"(vzero),
[out2] "r"(doutr1) [remain] "r"(remain)
: "cc", : "cc",
"memory", "memory",
"q4", "q4",
...@@ -3714,21 +3825,18 @@ void act_switch_3x3s1p0_s(const float *din_ptr0, ...@@ -3714,21 +3825,18 @@ void act_switch_3x3s1p0_s(const float *din_ptr0,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
break; dout_ptr += 2 * w_out;
} //! end of processing mid rows
#endif #endif
default: }
LOG(FATAL) << "this act_type: " << static_cast<int>(act_param.active_type)
<< " fuse not support";
} }
} }
/**
* \brief depthwise convolution, kernel size 3x3, stride 1, pad 1, with bias, void conv_depthwise_3x3s1p0_bias_s_leakyRelu(float *dout,
* width <= 4
*/
void conv_depthwise_3x3s1p0_bias_s(float *dout,
const float *din, const float *din,
const float *weights, const float *weights,
const float *bias, const float *bias,
const float *scale,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -3736,11 +3844,7 @@ void conv_depthwise_3x3s1p0_bias_s(float *dout, ...@@ -3736,11 +3844,7 @@ void conv_depthwise_3x3s1p0_bias_s(float *dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext *ctx) { ARMContext *ctx) {
//! 3x3s1 convolution, implemented by direct algorithm
//! pad is done implicit
//! for 4x6 convolution window
const int right_pad_idx[8] = {5, 4, 3, 2, 1, 0, 0, 0}; const int right_pad_idx[8] = {5, 4, 3, 2, 1, 0, 0, 0};
const float zero_ptr[4] = {0.f, 0.f, 0.f, 0.f}; const float zero_ptr[4] = {0.f, 0.f, 0.f, 0.f};
...@@ -3750,6 +3854,10 @@ void conv_depthwise_3x3s1p0_bias_s(float *dout, ...@@ -3750,6 +3854,10 @@ void conv_depthwise_3x3s1p0_bias_s(float *dout,
uint32x4_t vmask_rp2 = uint32x4_t vmask_rp2 =
vcgeq_s32(vld1q_s32(right_pad_idx + 4), vdupq_n_s32(6 - w_in)); vcgeq_s32(vld1q_s32(right_pad_idx + 4), vdupq_n_s32(6 - w_in));
#ifdef __aarch64__
float32x4_t vscale = vld1q_f32(scale);
#endif
unsigned int vmask[8]; unsigned int vmask[8];
vst1q_u32(vmask, vmask_rp1); vst1q_u32(vmask, vmask_rp1);
vst1q_u32(vmask + 4, vmask_rp2); vst1q_u32(vmask + 4, vmask_rp2);
...@@ -3808,22 +3916,70 @@ void conv_depthwise_3x3s1p0_bias_s(float *dout, ...@@ -3808,22 +3916,70 @@ void conv_depthwise_3x3s1p0_bias_s(float *dout,
doutr1 = trash_buf; doutr1 = trash_buf;
} }
unsigned int *vmask_ptr = vmask; unsigned int *vmask_ptr = vmask;
act_switch_3x3s1p0_s(dr0, #ifdef __aarch64__
dr1, asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1_LEAKY_RELU
dr2, : [din0] "+r"(dr0),
dr3, [din1] "+r"(dr1),
out_buf1, [din2] "+r"(dr2),
out_buf2, [din3] "+r"(dr3)
wr0, : [wr0] "w"(wr0),
wr1, [wr1] "w"(wr1),
wr2, [wr2] "w"(wr2),
vmask_rp1, [vbias] "w"(wbias),
vmask_rp2, [mask1] "w"(vmask_rp1),
vzero, [mask2] "w"(vmask_rp2),
wbias, [vzero] "w"(vzero),
vmask_ptr, [vscale] "w"(vscale),
bias_val, [out1] "r"(doutr0),
act_param); [out2] "r"(doutr1)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15");
#else
asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1_LEAKY_RELU
: [din0] "+r"(dr0),
[din1] "+r"(dr1),
[din2] "+r"(dr2),
[din3] "+r"(dr3),
[vmask] "+r"(vmask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[vzero] "w"(vzero),
[scale_ptr] "r"(scale),
[bias_val] "r"(bias_val),
[out1] "r"(doutr0),
[out2] "r"(doutr1)
: "cc",
"memory",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
#endif
for (int w = 0; w < w_out; ++w) { for (int w = 0; w < w_out; ++w) {
*doutr0++ = out_buf1[w]; *doutr0++ = out_buf1[w];
*doutr1++ = out_buf2[w]; *doutr1++ = out_buf2[w];
......
lite/backends/arm/math/conv3x3s1p01_depthwise_fp32_relu.cc
浏览文件 @ 9e38adc8
...@@ -1202,7 +1202,7 @@ namespace math { ...@@ -1202,7 +1202,7 @@ namespace math {
* \brief depthwise convolution, kernel size 3x3, stride 1, pad 1, with bias, * \brief depthwise convolution, kernel size 3x3, stride 1, pad 1, with bias,
* width > 4 * width > 4
*/ */
void conv_depthwise_3x3s1p1_bias_relu(float *dout, void conv_depthwise_3x3s1p1_bias_no_relu(float *dout,
const float *din, const float *din,
const float *weights, const float *weights,
const float *bias, const float *bias,
...@@ -1363,10 +1363,8 @@ void conv_depthwise_3x3s1p1_bias_relu(float *dout, ...@@ -1363,10 +1363,8 @@ void conv_depthwise_3x3s1p1_bias_relu(float *dout,
} }
int cnt = cnt_col; int cnt = cnt_col;
if (flag_relu) { asm volatile(INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1 MID_COMPUTE_S1
asm volatile( MID_RESULT_S1 RIGHT_COMPUTE_S1 RIGHT_RESULT_S1
INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1_RELU MID_COMPUTE_S1
MID_RESULT_S1_RELU RIGHT_COMPUTE_S1 RIGHT_RESULT_S1_RELU
: [cnt] "+r"(cnt), : [cnt] "+r"(cnt),
[din_ptr0] "+r"(din_ptr0), [din_ptr0] "+r"(din_ptr0),
[din_ptr1] "+r"(din_ptr1), [din_ptr1] "+r"(din_ptr1),
...@@ -1413,9 +1411,256 @@ void conv_depthwise_3x3s1p1_bias_relu(float *dout, ...@@ -1413,9 +1411,256 @@ void conv_depthwise_3x3s1p1_bias_relu(float *dout,
"v23", "v23",
"v24", "v24",
"v25"); "v25");
dout_ptr = dout_ptr + 4 * w_out;
}
#else
for (int i = 0; i < h_in; i += 2) {
//! process top pad pad_h = 1
din_ptr0 = dr0;
din_ptr1 = dr1;
din_ptr2 = dr2;
din_ptr3 = dr3;
doutr0 = dout_ptr;
doutr1 = dout_ptr + w_out;
// unsigned int* rst_mask = rmask;
if (i == 0) {
din_ptr0 = zero_ptr;
din_ptr1 = dr0;
din_ptr2 = dr1;
din_ptr3 = dr2;
dr0 = dr1;
dr1 = dr2;
dr2 = dr3;
dr3 = dr2 + w_in;
} else { } else {
dr0 = dr2;
dr1 = dr3;
dr2 = dr1 + w_in;
dr3 = dr2 + w_in;
}
//! process bottom pad
if (i + 3 > h_in) {
switch (i + 3 - h_in) {
case 3:
din_ptr1 = zero_ptr;
case 2:
din_ptr2 = zero_ptr;
case 1:
din_ptr3 = zero_ptr;
default:
break;
}
}
//! process bottom remain
if (i + 2 > h_out) {
doutr1 = write_ptr;
}
int cnt = cnt_col;
unsigned int *rmask_ptr = rmask;
unsigned int *vmask_ptr = vmask;
asm volatile(INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1 MID_COMPUTE_S1 asm volatile(INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1 MID_COMPUTE_S1
MID_RESULT_S1 RIGHT_COMPUTE_S1 RIGHT_RESULT_S1 MID_RESULT_S1 RIGHT_COMPUTE_S1 RIGHT_RESULT_S1
: [dout_ptr1] "+r"(doutr0),
[dout_ptr2] "+r"(doutr1),
[din0_ptr] "+r"(din_ptr0),
[din1_ptr] "+r"(din_ptr1),
[din2_ptr] "+r"(din_ptr2),
[din3_ptr] "+r"(din_ptr3),
[cnt] "+r"(cnt),
[rmask] "+r"(rmask_ptr),
[vmask] "+r"(vmask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[bias_val] "r"(bias_val),
[vzero] "w"(vzero)
: "cc",
"memory",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
dout_ptr += 2 * w_out;
} //! end of processing mid rows
#endif
}
}
}
void conv_depthwise_3x3s1p1_bias_relu(float *dout,
const float *din,
const float *weights,
const float *bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext *ctx) {
//! pad is done implicit
const float zero[8] = {0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f};
//! for 4x6 convolution window
const unsigned int right_pad_idx[8] = {5, 4, 3, 2, 1, 0, 0, 0};
float *zero_ptr = ctx->workspace_data<float>();
memset(zero_ptr, 0, w_in * sizeof(float));
float *write_ptr = zero_ptr + w_in;
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
int w_stride = 9;
int tile_w = w_out >> 2;
int remain = w_out % 4;
int cnt_col = tile_w - 1;
unsigned int size_pad_right = (unsigned int)(5 + (tile_w << 2) - w_in);
const unsigned int remian_idx[4] = {0, 1, 2, 3};
if (remain == 0 && size_pad_right == 5) {
size_pad_right = 1;
cnt_col -= 1;
remain = 4;
} else if (remain == 0 && size_pad_right == 6) {
size_pad_right = 2;
cnt_col -= 1;
remain = 4;
}
uint32x4_t vmask_rp1 =
vcgeq_u32(vld1q_u32(right_pad_idx), vdupq_n_u32(size_pad_right));
uint32x4_t vmask_rp2 =
vcgeq_u32(vld1q_u32(right_pad_idx + 4), vdupq_n_u32(size_pad_right));
uint32x4_t vmask_result =
vcgtq_u32(vdupq_n_u32(remain), vld1q_u32(remian_idx));
unsigned int vmask[8];
vst1q_u32(vmask, vmask_rp1);
vst1q_u32(vmask + 4, vmask_rp2);
unsigned int rmask[4];
vst1q_u32(rmask, vmask_result);
float32x4_t vzero = vdupq_n_f32(0.f);
for (int n = 0; n < num; ++n) {
const float *din_batch = din + n * ch_in * size_in_channel;
float *dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int c = 0; c < ch_in; c++) {
float *dout_ptr = dout_batch + c * size_out_channel;
const float *din_ch_ptr = din_batch + c * size_in_channel;
float bias_val = flag_bias ? bias[c] : 0.f;
float vbias[4] = {bias_val, bias_val, bias_val, bias_val};
const float *wei_ptr = weights + c * w_stride;
float32x4_t wr0 = vld1q_f32(wei_ptr);
float32x4_t wr1 = vld1q_f32(wei_ptr + 3);
float32x4_t wr2 = vld1q_f32(wei_ptr + 6);
float *doutr0 = dout_ptr;
float *doutr1 = doutr0 + w_out;
float *doutr2 = doutr1 + w_out;
float *doutr3 = doutr2 + w_out;
const float *dr0 = din_ch_ptr;
const float *dr1 = dr0 + w_in;
const float *dr2 = dr1 + w_in;
const float *dr3 = dr2 + w_in;
const float *dr4 = dr3 + w_in;
const float *dr5 = dr4 + w_in;
const float *din_ptr0 = dr0;
const float *din_ptr1 = dr1;
const float *din_ptr2 = dr2;
const float *din_ptr3 = dr3;
const float *din_ptr4 = dr4;
const float *din_ptr5 = dr5;
float *ptr_zero = const_cast<float *>(zero);
#ifdef __aarch64__
for (int i = 0; i < h_in; i += 4) {
//! process top pad pad_h = 1
din_ptr0 = dr0;
din_ptr1 = dr1;
din_ptr2 = dr2;
din_ptr3 = dr3;
din_ptr4 = dr4;
din_ptr5 = dr5;
doutr0 = dout_ptr;
doutr1 = doutr0 + w_out;
doutr2 = doutr1 + w_out;
doutr3 = doutr2 + w_out;
if (i == 0) {
din_ptr0 = zero_ptr;
din_ptr1 = dr0;
din_ptr2 = dr1;
din_ptr3 = dr2;
din_ptr4 = dr3;
din_ptr5 = dr4;
dr0 = dr3;
dr1 = dr4;
dr2 = dr5;
} else {
dr0 = dr4;
dr1 = dr5;
dr2 = dr1 + w_in;
}
dr3 = dr2 + w_in;
dr4 = dr3 + w_in;
dr5 = dr4 + w_in;
//! process bottom pad
if (i + 5 > h_in) {
switch (i + 5 - h_in) {
case 5:
din_ptr1 = zero_ptr;
case 4:
din_ptr2 = zero_ptr;
case 3:
din_ptr3 = zero_ptr;
case 2:
din_ptr4 = zero_ptr;
case 1:
din_ptr5 = zero_ptr;
default:
break;
}
}
//! process bottom remain
if (i + 4 > h_out) {
switch (i + 4 - h_out) {
case 3:
doutr1 = write_ptr;
case 2:
doutr2 = write_ptr;
case 1:
doutr3 = write_ptr;
default:
break;
}
}
int cnt = cnt_col;
asm volatile(
INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1_RELU MID_COMPUTE_S1
MID_RESULT_S1_RELU RIGHT_COMPUTE_S1 RIGHT_RESULT_S1_RELU
: [cnt] "+r"(cnt), : [cnt] "+r"(cnt),
[din_ptr0] "+r"(din_ptr0), [din_ptr0] "+r"(din_ptr0),
[din_ptr1] "+r"(din_ptr1), [din_ptr1] "+r"(din_ptr1),
...@@ -1462,7 +1707,6 @@ void conv_depthwise_3x3s1p1_bias_relu(float *dout, ...@@ -1462,7 +1707,6 @@ void conv_depthwise_3x3s1p1_bias_relu(float *dout,
"v23", "v23",
"v24", "v24",
"v25"); "v25");
}
dout_ptr = dout_ptr + 4 * w_out; dout_ptr = dout_ptr + 4 * w_out;
} }
#else #else
...@@ -1512,7 +1756,6 @@ void conv_depthwise_3x3s1p1_bias_relu(float *dout, ...@@ -1512,7 +1756,6 @@ void conv_depthwise_3x3s1p1_bias_relu(float *dout,
int cnt = cnt_col; int cnt = cnt_col;
unsigned int *rmask_ptr = rmask; unsigned int *rmask_ptr = rmask;
unsigned int *vmask_ptr = vmask; unsigned int *vmask_ptr = vmask;
if (flag_relu) {
asm volatile( asm volatile(
INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1_RELU MID_COMPUTE_S1 INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1_RELU MID_COMPUTE_S1
MID_RESULT_S1_RELU RIGHT_COMPUTE_S1 RIGHT_RESULT_S1_RELU MID_RESULT_S1_RELU RIGHT_COMPUTE_S1 RIGHT_RESULT_S1_RELU
...@@ -1544,38 +1787,6 @@ void conv_depthwise_3x3s1p1_bias_relu(float *dout, ...@@ -1544,38 +1787,6 @@ void conv_depthwise_3x3s1p1_bias_relu(float *dout,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
} else {
asm volatile(INIT_S1 LEFT_COMPUTE_S1 LEFT_RESULT_S1 MID_COMPUTE_S1
MID_RESULT_S1 RIGHT_COMPUTE_S1 RIGHT_RESULT_S1
: [dout_ptr1] "+r"(doutr0),
[dout_ptr2] "+r"(doutr1),
[din0_ptr] "+r"(din_ptr0),
[din1_ptr] "+r"(din_ptr1),
[din2_ptr] "+r"(din_ptr2),
[din3_ptr] "+r"(din_ptr3),
[cnt] "+r"(cnt),
[rmask] "+r"(rmask_ptr),
[vmask] "+r"(vmask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[bias_val] "r"(bias_val),
[vzero] "w"(vzero)
: "cc",
"memory",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
}
dout_ptr += 2 * w_out; dout_ptr += 2 * w_out;
} //! end of processing mid rows } //! end of processing mid rows
#endif #endif
...@@ -1587,7 +1798,7 @@ void conv_depthwise_3x3s1p1_bias_relu(float *dout, ...@@ -1587,7 +1798,7 @@ void conv_depthwise_3x3s1p1_bias_relu(float *dout,
* \brief depthwise convolution, kernel size 3x3, stride 1, pad 1, with bias, * \brief depthwise convolution, kernel size 3x3, stride 1, pad 1, with bias,
* width <= 4 * width <= 4
*/ */
void conv_depthwise_3x3s1p1_bias_s_relu(float *dout, void conv_depthwise_3x3s1p1_bias_s_no_relu(float *dout,
const float *din, const float *din,
const float *weights, const float *weights,
const float *bias, const float *bias,
...@@ -1660,8 +1871,7 @@ void conv_depthwise_3x3s1p1_bias_s_relu(float *dout, ...@@ -1660,8 +1871,7 @@ void conv_depthwise_3x3s1p1_bias_s_relu(float *dout,
break; break;
} }
#ifdef __aarch64__ #ifdef __aarch64__
if (flag_relu) { asm volatile(COMPUTE_S_S1 RESULT_S_S1
asm volatile(COMPUTE_S_S1 RESULT_S_S1_RELU
: [din0] "+r"(dr0), : [din0] "+r"(dr0),
[din1] "+r"(dr1), [din1] "+r"(dr1),
[din2] "+r"(dr2), [din2] "+r"(dr2),
...@@ -1692,8 +1902,119 @@ void conv_depthwise_3x3s1p1_bias_s_relu(float *dout, ...@@ -1692,8 +1902,119 @@ void conv_depthwise_3x3s1p1_bias_s_relu(float *dout,
"v15", "v15",
"v16", "v16",
"v17"); "v17");
} else { #else
asm volatile(COMPUTE_S_S1 RESULT_S_S1 asm volatile(COMPUTE_S_S1 RESULT_S_S1
: [din0] "+r"(dr0),
[din1] "+r"(dr1),
[din2] "+r"(dr2),
[din3] "+r"(dr3)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[vzero] "w"(vzero),
[mask] "w"(vmask_rp),
[bias] "w"(wbias),
[out1] "r"(out_buf1),
[out2] "r"(out_buf2)
: "cc",
"memory",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
#endif
for (int w = 0; w < w_out; ++w) {
*doutr0++ = out_buf1[w];
*doutr1++ = out_buf2[w];
}
doutr0 = doutr1;
doutr1 += w_out;
hs += 2;
he += 2;
} // end of processing heights
} // end of processing channels
} // end of processing batchs
}
void conv_depthwise_3x3s1p1_bias_s_relu(float *dout,
const float *din,
const float *weights,
const float *bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext *ctx) {
//! 3x3s1 convolution, implemented by direct algorithm
//! pad is done implicit
//! for 4x6 convolution window
const int right_pad_idx[4] = {3, 2, 1, 0};
const float zero[4] = {0.f, 0.f, 0.f, 0.f};
float32x4_t vzero = vdupq_n_f32(0.f);
uint32x4_t vmask_rp =
vcgeq_s32(vld1q_s32(right_pad_idx), vdupq_n_s32(4 - w_in));
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
for (int n = 0; n < num; ++n) {
const float *din_batch = din + n * ch_in * size_in_channel;
float *dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int i = 0; i < ch_in; ++i) {
float *dout_channel = dout_batch + i * size_out_channel;
const float *din_channel = din_batch + i * size_in_channel;
const float *weight_ptr = weights + i * 9;
float32x4_t wr0 = vld1q_f32(weight_ptr);
float32x4_t wr1 = vld1q_f32(weight_ptr + 3);
float32x4_t wr2 = vld1q_f32(weight_ptr + 6);
float32x4_t wbias;
if (flag_bias) {
wbias = vdupq_n_f32(bias[i]);
} else {
wbias = vdupq_n_f32(0.f);
}
int hs = -1;
int he = 3;
float out_buf1[4];
float out_buf2[4];
float trash_buf[4];
int h_cnt = (h_out + 1) >> 1;
float *doutr0 = dout_channel;
float *doutr1 = dout_channel + w_out;
for (int j = 0; j < h_cnt; ++j) {
const float *dr0 = din_channel + hs * w_in;
const float *dr1 = dr0 + w_in;
const float *dr2 = dr1 + w_in;
const float *dr3 = dr2 + w_in;
if (hs == -1) {
dr0 = zero;
}
switch (he - h_in) {
case 2:
dr2 = zero;
doutr1 = trash_buf;
case 1:
dr3 = zero;
default:
break;
}
#ifdef __aarch64__
asm volatile(COMPUTE_S_S1 RESULT_S_S1_RELU
: [din0] "+r"(dr0), : [din0] "+r"(dr0),
[din1] "+r"(dr1), [din1] "+r"(dr1),
[din2] "+r"(dr2), [din2] "+r"(dr2),
...@@ -1724,9 +2045,7 @@ void conv_depthwise_3x3s1p1_bias_s_relu(float *dout, ...@@ -1724,9 +2045,7 @@ void conv_depthwise_3x3s1p1_bias_s_relu(float *dout,
"v15", "v15",
"v16", "v16",
"v17"); "v17");
}
#else #else
if (flag_relu) {
asm volatile(COMPUTE_S_S1 RESULT_S_S1_RELU asm volatile(COMPUTE_S_S1 RESULT_S_S1_RELU
: [din0] "+r"(dr0), : [din0] "+r"(dr0),
[din1] "+r"(dr1), [din1] "+r"(dr1),
...@@ -1752,33 +2071,6 @@ void conv_depthwise_3x3s1p1_bias_s_relu(float *dout, ...@@ -1752,33 +2071,6 @@ void conv_depthwise_3x3s1p1_bias_s_relu(float *dout,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
} else {
asm volatile(COMPUTE_S_S1 RESULT_S_S1
: [din0] "+r"(dr0),
[din1] "+r"(dr1),
[din2] "+r"(dr2),
[din3] "+r"(dr3)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[vzero] "w"(vzero),
[mask] "w"(vmask_rp),
[bias] "w"(wbias),
[out1] "r"(out_buf1),
[out2] "r"(out_buf2)
: "cc",
"memory",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
}
#endif #endif
for (int w = 0; w < w_out; ++w) { for (int w = 0; w < w_out; ++w) {
*doutr0++ = out_buf1[w]; *doutr0++ = out_buf1[w];
...@@ -1797,7 +2089,7 @@ void conv_depthwise_3x3s1p1_bias_s_relu(float *dout, ...@@ -1797,7 +2089,7 @@ void conv_depthwise_3x3s1p1_bias_s_relu(float *dout,
* \brief depthwise convolution, kernel size 3x3, stride 1, pad 1, with bias, * \brief depthwise convolution, kernel size 3x3, stride 1, pad 1, with bias,
* width > 4 * width > 4
*/ */
void conv_depthwise_3x3s1p0_bias_relu(float *dout, void conv_depthwise_3x3s1p0_bias_no_relu(float *dout,
const float *din, const float *din,
const float *weights, const float *weights,
const float *bias, const float *bias,
...@@ -1937,67 +2229,6 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout, ...@@ -1937,67 +2229,6 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout,
} }
int cnt = tile_w; int cnt = tile_w;
if (flag_relu) {
asm volatile(
INIT_S1
"ld1 {v8.4s}, [%[din_ptr4]], #16 \n" /*vld1q_f32(din_ptr0)*/
"ld1 {v10.4s}, [%[din_ptr5]], #16 \n" /*vld1q_f32(din_ptr0)*/
"ext v16.16b, v0.16b, v1.16b, #4 \n" /* v16 = 1234 */
"ext v17.16b, v0.16b, v1.16b, #8 \n" /* v17 = 2345 */
"ld1 {v9.4s}, [%[din_ptr4]] \n" /*vld1q_f32(din_ptr0)*/
"ld1 {v11.4s}, [%[din_ptr5]] \n" /*vld1q_f32(din_ptr0)*/
MID_COMPUTE_S1 MID_RESULT_S1_RELU
"cmp %w[remain], #1 \n"
"blt 0f \n" RIGHT_COMPUTE_S1
RIGHT_RESULT_S1_RELU "0: \n"
: [cnt] "+r"(cnt),
[din_ptr0] "+r"(din_ptr0),
[din_ptr1] "+r"(din_ptr1),
[din_ptr2] "+r"(din_ptr2),
[din_ptr3] "+r"(din_ptr3),
[din_ptr4] "+r"(din_ptr4),
[din_ptr5] "+r"(din_ptr5),
[doutr0] "+r"(doutr0),
[doutr1] "+r"(doutr1),
[doutr2] "+r"(doutr2),
[doutr3] "+r"(doutr3)
: [w0] "w"(wr0),
[w1] "w"(wr1),
[w2] "w"(wr2),
[bias_val] "r"(vbias),
[vmask] "r"(vmask),
[rmask] "r"(rmask),
[vzero] "w"(vzero),
[remain] "r"(remain)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21",
"v22",
"v23",
"v24",
"v25");
} else {
asm volatile( asm volatile(
INIT_S1 INIT_S1
"ld1 {v8.4s}, [%[din_ptr4]], #16 \n" /*vld1q_f32(din_ptr0)*/ "ld1 {v8.4s}, [%[din_ptr4]], #16 \n" /*vld1q_f32(din_ptr0)*/
...@@ -2008,8 +2239,8 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout, ...@@ -2008,8 +2239,8 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout,
"ld1 {v11.4s}, [%[din_ptr5]] \n" /*vld1q_f32(din_ptr0)*/ "ld1 {v11.4s}, [%[din_ptr5]] \n" /*vld1q_f32(din_ptr0)*/
MID_COMPUTE_S1 MID_RESULT_S1 MID_COMPUTE_S1 MID_RESULT_S1
"cmp %w[remain], #1 \n" "cmp %w[remain], #1 \n"
"blt 0f \n" RIGHT_COMPUTE_S1 "blt 0f \n" RIGHT_COMPUTE_S1 RIGHT_RESULT_S1
RIGHT_RESULT_S1 "0: \n" "0: \n"
: [cnt] "+r"(cnt), : [cnt] "+r"(cnt),
[din_ptr0] "+r"(din_ptr0), [din_ptr0] "+r"(din_ptr0),
[din_ptr1] "+r"(din_ptr1), [din_ptr1] "+r"(din_ptr1),
...@@ -2057,7 +2288,6 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout, ...@@ -2057,7 +2288,6 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout,
"v23", "v23",
"v24", "v24",
"v25"); "v25");
}
dout_ptr = dout_ptr + 4 * w_out; dout_ptr = dout_ptr + 4 * w_out;
} }
#else #else
...@@ -2096,18 +2326,17 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout, ...@@ -2096,18 +2326,17 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout,
int cnt = tile_w; int cnt = tile_w;
unsigned int *rmask_ptr = rmask; unsigned int *rmask_ptr = rmask;
unsigned int *vmask_ptr = vmask; unsigned int *vmask_ptr = vmask;
if (flag_relu) { asm volatile(
asm volatile(INIT_S1 INIT_S1
"sub %[din0_ptr], #8 @ 0pad + 2 float data overlap\n" "sub %[din0_ptr], #8 @ 0pad + 2 float data overlap\n"
"sub %[din1_ptr], #8 @ 0pad + 2 float data overlap\n" "sub %[din1_ptr], #8 @ 0pad + 2 float data overlap\n"
"sub %[din2_ptr], #8 @ 0pad + 2 float data overlap\n" "sub %[din2_ptr], #8 @ 0pad + 2 float data overlap\n"
"sub %[din3_ptr], #8 @ 0pad + 2 float data overlap\n" "sub %[din3_ptr], #8 @ 0pad + 2 float data overlap\n"
"vext.32 q6, q8, q9, #1 @ 0012\n" "vext.32 q6, q8, q9, #1 @ 0012\n"
"vext.32 q7, q8, q9, #2 @ 1234\n" MID_COMPUTE_S1 "vext.32 q7, q8, q9, #2 @ 1234\n" MID_COMPUTE_S1 MID_RESULT_S1
MID_RESULT_S1_RELU
"cmp %[remain], #1 \n" "cmp %[remain], #1 \n"
"blt 0f \n" RIGHT_COMPUTE_S1 "blt 0f \n" RIGHT_COMPUTE_S1 RIGHT_RESULT_S1
RIGHT_RESULT_S1_RELU "0: \n" "0: \n"
: [dout_ptr1] "+r"(doutr0), : [dout_ptr1] "+r"(doutr0),
[dout_ptr2] "+r"(doutr1), [dout_ptr2] "+r"(doutr1),
[din0_ptr] "+r"(din_ptr0), [din0_ptr] "+r"(din_ptr0),
...@@ -2137,20 +2366,263 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout, ...@@ -2137,20 +2366,263 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
} else { dout_ptr += 2 * w_out;
asm volatile(INIT_S1 } //! end of processing mid rows
"sub %[din0_ptr], #8 @ 0pad + 2 float data overlap\n" #endif
"sub %[din1_ptr], #8 @ 0pad + 2 float data overlap\n" }
"sub %[din2_ptr], #8 @ 0pad + 2 float data overlap\n" }
"sub %[din3_ptr], #8 @ 0pad + 2 float data overlap\n" }
"vext.32 q6, q8, q9, #1 @ 0012\n"
"vext.32 q7, q8, q9, #2 @ 1234\n" MID_COMPUTE_S1 void conv_depthwise_3x3s1p0_bias_relu(float *dout,
MID_RESULT_S1 const float *din,
"cmp %[remain], #1 \n" const float *weights,
"blt 0f \n" RIGHT_COMPUTE_S1 const float *bias,
RIGHT_RESULT_S1 "0: \n" bool flag_bias,
: [dout_ptr1] "+r"(doutr0), bool flag_relu,
[dout_ptr2] "+r"(doutr1), const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext *ctx) {
//! pad is done implicit
const float zero[8] = {0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f};
//! for 4x6 convolution window
const unsigned int right_pad_idx[8] = {5, 4, 3, 2, 1, 0, 0, 0};
float *zero_ptr = ctx->workspace_data<float>();
memset(zero_ptr, 0, w_in * sizeof(float));
float *write_ptr = zero_ptr + w_in;
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
int w_stride = 9;
int tile_w = w_out >> 2;
int remain = w_out % 4;
unsigned int size_pad_right = (unsigned int)(6 + (tile_w << 2) - w_in);
const int remian_idx[4] = {0, 1, 2, 3};
uint32x4_t vmask_rp1 =
vcgeq_u32(vld1q_u32(right_pad_idx), vdupq_n_u32(size_pad_right));
uint32x4_t vmask_rp2 =
vcgeq_u32(vld1q_u32(right_pad_idx + 4), vdupq_n_u32(size_pad_right));
uint32x4_t vmask_result =
vcgtq_s32(vdupq_n_s32(remain), vld1q_s32(remian_idx));
unsigned int vmask[8];
vst1q_u32(vmask, vmask_rp1);
vst1q_u32(vmask + 4, vmask_rp2);
unsigned int rmask[4];
vst1q_u32(rmask, vmask_result);
float32x4_t vzero = vdupq_n_f32(0.f);
for (int n = 0; n < num; ++n) {
const float *din_batch = din + n * ch_in * size_in_channel;
float *dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int c = 0; c < ch_in; c++) {
float *dout_ptr = dout_batch + c * size_out_channel;
const float *din_ch_ptr = din_batch + c * size_in_channel;
float bias_val = flag_bias ? bias[c] : 0.f;
float vbias[4] = {bias_val, bias_val, bias_val, bias_val};
const float *wei_ptr = weights + c * w_stride;
float32x4_t wr0 = vld1q_f32(wei_ptr);
float32x4_t wr1 = vld1q_f32(wei_ptr + 3);
float32x4_t wr2 = vld1q_f32(wei_ptr + 6);
float *doutr0 = dout_ptr;
float *doutr1 = doutr0 + w_out;
float *doutr2 = doutr1 + w_out;
float *doutr3 = doutr2 + w_out;
const float *dr0 = din_ch_ptr;
const float *dr1 = dr0 + w_in;
const float *dr2 = dr1 + w_in;
const float *dr3 = dr2 + w_in;
const float *dr4 = dr3 + w_in;
const float *dr5 = dr4 + w_in;
const float *din_ptr0 = dr0;
const float *din_ptr1 = dr1;
const float *din_ptr2 = dr2;
const float *din_ptr3 = dr3;
const float *din_ptr4 = dr4;
const float *din_ptr5 = dr5;
float *ptr_zero = const_cast<float *>(zero);
#ifdef __aarch64__
for (int i = 0; i < h_out; i += 4) {
//! process top pad pad_h = 1
din_ptr0 = dr0;
din_ptr1 = dr1;
din_ptr2 = dr2;
din_ptr3 = dr3;
din_ptr4 = dr4;
din_ptr5 = dr5;
doutr0 = dout_ptr;
doutr1 = doutr0 + w_out;
doutr2 = doutr1 + w_out;
doutr3 = doutr2 + w_out;
dr0 = dr4;
dr1 = dr5;
dr2 = dr1 + w_in;
dr3 = dr2 + w_in;
dr4 = dr3 + w_in;
dr5 = dr4 + w_in;
//! process bottom pad
if (i + 5 >= h_in) {
switch (i + 5 - h_in) {
case 4:
din_ptr1 = zero_ptr;
case 3:
din_ptr2 = zero_ptr;
case 2:
din_ptr3 = zero_ptr;
case 1:
din_ptr4 = zero_ptr;
case 0:
din_ptr5 = zero_ptr;
default:
break;
}
}
//! process bottom remain
if (i + 4 > h_out) {
switch (i + 4 - h_out) {
case 3:
doutr1 = write_ptr;
case 2:
doutr2 = write_ptr;
case 1:
doutr3 = write_ptr;
default:
break;
}
}
int cnt = tile_w;
asm volatile(
INIT_S1
"ld1 {v8.4s}, [%[din_ptr4]], #16 \n" /*vld1q_f32(din_ptr0)*/
"ld1 {v10.4s}, [%[din_ptr5]], #16 \n" /*vld1q_f32(din_ptr0)*/
"ext v16.16b, v0.16b, v1.16b, #4 \n" /* v16 = 1234 */
"ext v17.16b, v0.16b, v1.16b, #8 \n" /* v17 = 2345 */
"ld1 {v9.4s}, [%[din_ptr4]] \n" /*vld1q_f32(din_ptr0)*/
"ld1 {v11.4s}, [%[din_ptr5]] \n" /*vld1q_f32(din_ptr0)*/
MID_COMPUTE_S1 MID_RESULT_S1_RELU
"cmp %w[remain], #1 \n"
"blt 0f \n" RIGHT_COMPUTE_S1
RIGHT_RESULT_S1_RELU "0: \n"
: [cnt] "+r"(cnt),
[din_ptr0] "+r"(din_ptr0),
[din_ptr1] "+r"(din_ptr1),
[din_ptr2] "+r"(din_ptr2),
[din_ptr3] "+r"(din_ptr3),
[din_ptr4] "+r"(din_ptr4),
[din_ptr5] "+r"(din_ptr5),
[doutr0] "+r"(doutr0),
[doutr1] "+r"(doutr1),
[doutr2] "+r"(doutr2),
[doutr3] "+r"(doutr3)
: [w0] "w"(wr0),
[w1] "w"(wr1),
[w2] "w"(wr2),
[bias_val] "r"(vbias),
[vmask] "r"(vmask),
[rmask] "r"(rmask),
[vzero] "w"(vzero),
[remain] "r"(remain)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21",
"v22",
"v23",
"v24",
"v25");
dout_ptr = dout_ptr + 4 * w_out;
}
#else
for (int i = 0; i < h_out; i += 2) {
din_ptr0 = dr0;
din_ptr1 = dr1;
din_ptr2 = dr2;
din_ptr3 = dr3;
doutr0 = dout_ptr;
doutr1 = dout_ptr + w_out;
dr0 = dr2;
dr1 = dr3;
dr2 = dr1 + w_in;
dr3 = dr2 + w_in;
//! process bottom pad
if (i + 3 >= h_in) {
switch (i + 3 - h_in) {
case 3:
din_ptr1 = zero_ptr;
case 2:
din_ptr2 = zero_ptr;
case 1:
din_ptr3 = zero_ptr;
case 0:
din_ptr3 = zero_ptr;
default:
break;
}
}
//! process bottom remain
if (i + 2 > h_out) {
doutr1 = write_ptr;
}
int cnt = tile_w;
unsigned int *rmask_ptr = rmask;
unsigned int *vmask_ptr = vmask;
asm volatile(INIT_S1
"sub %[din0_ptr], #8 @ 0pad + 2 float data overlap\n"
"sub %[din1_ptr], #8 @ 0pad + 2 float data overlap\n"
"sub %[din2_ptr], #8 @ 0pad + 2 float data overlap\n"
"sub %[din3_ptr], #8 @ 0pad + 2 float data overlap\n"
"vext.32 q6, q8, q9, #1 @ 0012\n"
"vext.32 q7, q8, q9, #2 @ 1234\n" MID_COMPUTE_S1
MID_RESULT_S1_RELU
"cmp %[remain], #1 \n"
"blt 0f \n" RIGHT_COMPUTE_S1
RIGHT_RESULT_S1_RELU "0: \n"
: [dout_ptr1] "+r"(doutr0),
[dout_ptr2] "+r"(doutr1),
[din0_ptr] "+r"(din_ptr0), [din0_ptr] "+r"(din_ptr0),
[din1_ptr] "+r"(din_ptr1), [din1_ptr] "+r"(din_ptr1),
[din2_ptr] "+r"(din_ptr2), [din2_ptr] "+r"(din_ptr2),
...@@ -2178,7 +2650,6 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout, ...@@ -2178,7 +2650,6 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
}
dout_ptr += 2 * w_out; dout_ptr += 2 * w_out;
} //! end of processing mid rows } //! end of processing mid rows
#endif #endif
...@@ -2189,7 +2660,7 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout, ...@@ -2189,7 +2660,7 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout,
* \brief depthwise convolution, kernel size 3x3, stride 1, pad 1, with bias, * \brief depthwise convolution, kernel size 3x3, stride 1, pad 1, with bias,
* width <= 4 * width <= 4
*/ */
void conv_depthwise_3x3s1p0_bias_s_relu(float *dout, void conv_depthwise_3x3s1p0_bias_s_no_relu(float *dout,
const float *din, const float *din,
const float *weights, const float *weights,
const float *bias, const float *bias,
...@@ -2276,8 +2747,7 @@ void conv_depthwise_3x3s1p0_bias_s_relu(float *dout, ...@@ -2276,8 +2747,7 @@ void conv_depthwise_3x3s1p0_bias_s_relu(float *dout,
} }
} }
#ifdef __aarch64__ #ifdef __aarch64__
if (flag_relu) { asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1
asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1_RELU
: [din0] "+r"(dr0), : [din0] "+r"(dr0),
[din1] "+r"(dr1), [din1] "+r"(dr1),
[din2] "+r"(dr2), [din2] "+r"(dr2),
...@@ -2309,8 +2779,134 @@ void conv_depthwise_3x3s1p0_bias_s_relu(float *dout, ...@@ -2309,8 +2779,134 @@ void conv_depthwise_3x3s1p0_bias_s_relu(float *dout,
"v13", "v13",
"v14", "v14",
"v15"); "v15");
} else { #else
unsigned int *vmask_ptr = vmask;
float bias_val = flag_bias ? bias[i] : 0.f;
asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1 asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1
: [din0] "+r"(dr0),
[din1] "+r"(dr1),
[din2] "+r"(dr2),
[din3] "+r"(dr3),
[vmask] "+r"(vmask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[vzero] "w"(vzero),
[bias_val] "r"(bias_val),
[out1] "r"(out_buf1),
[out2] "r"(out_buf2)
: "cc",
"memory",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
#endif
for (int w = 0; w < w_out; ++w) {
*doutr0++ = out_buf1[w];
*doutr1++ = out_buf2[w];
}
} // end of processing heights
} // end of processing channels
} // end of processing batchs
}
void conv_depthwise_3x3s1p0_bias_s_relu(float *dout,
const float *din,
const float *weights,
const float *bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext *ctx) {
//! 3x3s1 convolution, implemented by direct algorithm
//! pad is done implicit
//! for 4x6 convolution window
const int right_pad_idx[8] = {5, 4, 3, 2, 1, 0, 0, 0};
const float zero_ptr[4] = {0.f, 0.f, 0.f, 0.f};
float32x4_t vzero = vdupq_n_f32(0.f);
uint32x4_t vmask_rp1 =
vcgeq_s32(vld1q_s32(right_pad_idx), vdupq_n_s32(6 - w_in));
uint32x4_t vmask_rp2 =
vcgeq_s32(vld1q_s32(right_pad_idx + 4), vdupq_n_s32(6 - w_in));
unsigned int vmask[8];
vst1q_u32(vmask, vmask_rp1);
vst1q_u32(vmask + 4, vmask_rp2);
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
for (int n = 0; n < num; ++n) {
const float *din_batch = din + n * ch_in * size_in_channel;
float *dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int i = 0; i < ch_in; ++i) {
float *dout_channel = dout_batch + i * size_out_channel;
const float *din_channel = din_batch + i * size_in_channel;
const float *weight_ptr = weights + i * 9;
float32x4_t wr0 = vld1q_f32(weight_ptr);
float32x4_t wr1 = vld1q_f32(weight_ptr + 3);
float32x4_t wr2 = vld1q_f32(weight_ptr + 6);
#ifdef __aarch64__
float32x4_t wbias;
if (flag_bias) {
wbias = vdupq_n_f32(bias[i]);
} else {
wbias = vdupq_n_f32(0.f);
}
#endif // __aarch64__
float out_buf1[4];
float out_buf2[4];
float trash_buf[4];
float *doutr0 = dout_channel;
float *doutr1 = dout_channel + w_out;
for (int j = 0; j < h_out; j += 2) {
const float *dr0 = din_channel + j * w_in;
const float *dr1 = dr0 + w_in;
const float *dr2 = dr1 + w_in;
const float *dr3 = dr2 + w_in;
doutr0 = dout_channel + j * w_out;
doutr1 = doutr0 + w_out;
if (j + 3 >= h_in) {
switch (j + 3 - h_in) {
case 3:
dr1 = zero_ptr;
case 2:
dr2 = zero_ptr;
case 1:
dr3 = zero_ptr;
doutr1 = trash_buf;
case 0:
dr3 = zero_ptr;
if (j + 2 > h_out) {
doutr1 = trash_buf;
}
default:
break;
}
}
#ifdef __aarch64__
asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1_RELU
: [din0] "+r"(dr0), : [din0] "+r"(dr0),
[din1] "+r"(dr1), [din1] "+r"(dr1),
[din2] "+r"(dr2), [din2] "+r"(dr2),
...@@ -2342,11 +2938,9 @@ void conv_depthwise_3x3s1p0_bias_s_relu(float *dout, ...@@ -2342,11 +2938,9 @@ void conv_depthwise_3x3s1p0_bias_s_relu(float *dout,
"v13", "v13",
"v14", "v14",
"v15"); "v15");
}
#else #else
unsigned int *vmask_ptr = vmask; unsigned int *vmask_ptr = vmask;
float bias_val = flag_bias ? bias[i] : 0.f; float bias_val = flag_bias ? bias[i] : 0.f;
if (flag_relu) {
asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1_RELU asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1_RELU
: [din0] "+r"(dr0), : [din0] "+r"(dr0),
[din1] "+r"(dr1), [din1] "+r"(dr1),
...@@ -2374,35 +2968,6 @@ void conv_depthwise_3x3s1p0_bias_s_relu(float *dout, ...@@ -2374,35 +2968,6 @@ void conv_depthwise_3x3s1p0_bias_s_relu(float *dout,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
} else {
asm volatile(COMPUTE_S_S1_P0 RESULT_S_S1
: [din0] "+r"(dr0),
[din1] "+r"(dr1),
[din2] "+r"(dr2),
[din3] "+r"(dr3),
[vmask] "+r"(vmask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[vzero] "w"(vzero),
[bias_val] "r"(bias_val),
[out1] "r"(out_buf1),
[out2] "r"(out_buf2)
: "cc",
"memory",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
}
#endif #endif
for (int w = 0; w < w_out; ++w) { for (int w = 0; w < w_out; ++w) {
*doutr0++ = out_buf1[w]; *doutr0++ = out_buf1[w];
......
lite/backends/arm/math/conv3x3s2p01_depthwise_fp32.cc
浏览文件 @ 9e38adc8
...@@ -20,10 +20,11 @@ namespace paddle { ...@@ -20,10 +20,11 @@ namespace paddle {
namespace lite { namespace lite {
namespace arm { namespace arm {
namespace math { namespace math {
void conv_depthwise_3x3s2p0_bias(float* dout, void conv_depthwise_3x3s2p0_bias_relu6(float* dout,
const float* din, const float* din,
const float* weights, const float* weights,
const float* bias, const float* bias,
const float* six,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -31,13 +32,13 @@ void conv_depthwise_3x3s2p0_bias(float* dout, ...@@ -31,13 +32,13 @@ void conv_depthwise_3x3s2p0_bias(float* dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext* ctx); ARMContext* ctx);
void conv_depthwise_3x3s2p0_bias_s(float* dout, void conv_depthwise_3x3s2p0_bias_leakyRelu(float* dout,
const float* din, const float* din,
const float* weights, const float* weights,
const float* bias, const float* bias,
const float* scale,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -45,13 +46,13 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout, ...@@ -45,13 +46,13 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext* ctx); ARMContext* ctx);
void conv_depthwise_3x3s2p1_bias(float* dout, void conv_depthwise_3x3s2p0_bias_s_relu6(float* dout,
const float* din, const float* din,
const float* weights, const float* weights,
const float* bias, const float* bias,
const float* six,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -59,13 +60,69 @@ void conv_depthwise_3x3s2p1_bias(float* dout, ...@@ -59,13 +60,69 @@ void conv_depthwise_3x3s2p1_bias(float* dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext* ctx); ARMContext* ctx);
void conv_depthwise_3x3s2p1_bias_s(float* dout, void conv_depthwise_3x3s2p0_bias_s_leakyRelu(float* dout,
const float* din, const float* din,
const float* weights, const float* weights,
const float* bias, const float* bias,
const float* scale,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx);
void conv_depthwise_3x3s2p1_bias_relu6(float* dout,
const float* din,
const float* weights,
const float* bias,
const float* six,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx);
void conv_depthwise_3x3s2p1_bias_leakyRelu(float* dout,
const float* din,
const float* weights,
const float* bias,
const float* scale,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx);
void conv_depthwise_3x3s2p1_bias_s_relu6(float* dout,
const float* din,
const float* weights,
const float* bias,
const float* six,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx);
void conv_depthwise_3x3s2p1_bias_s_leakyRelu(float* dout,
const float* din,
const float* weights,
const float* bias,
const float* scale,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -73,7 +130,6 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout, ...@@ -73,7 +130,6 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext* ctx); ARMContext* ctx);
void conv_depthwise_3x3s2_fp32(const float* din, void conv_depthwise_3x3s2_fp32(const float* din,
...@@ -92,22 +148,85 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -92,22 +148,85 @@ void conv_depthwise_3x3s2_fp32(const float* din,
const operators::ActivationParam act_param, const operators::ActivationParam act_param,
ARMContext* ctx) { ARMContext* ctx) {
bool has_active = act_param.has_active; bool has_active = act_param.has_active;
bool flag_relu = false; auto act_type = act_param.active_type;
bool relu6 = false; float tmp = act_param.Relu_clipped_coef;
float ss = act_param.Leaky_relu_alpha;
float vsix[4] = {tmp, tmp, tmp, tmp};
float vscale[4] = {ss, ss, ss, ss};
if (has_active) { if (has_active) {
if (act_param.active_type == lite_api::ActivationType::kRelu) { switch (act_type) {
flag_relu = true; case lite_api::ActivationType::kRelu:
if (pad == 0) {
if (w_in > 8) {
conv_depthwise_3x3s2p0_bias_relu(dout,
din,
weights,
bias,
flag_bias,
true,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
} else {
conv_depthwise_3x3s2p0_bias_s_relu(dout,
din,
weights,
bias,
flag_bias,
true,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
}
}
if (pad == 1) {
if (w_in > 7) {
conv_depthwise_3x3s2p1_bias_relu(dout,
din,
weights,
bias,
flag_bias,
true,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
} else { } else {
relu6 = true; conv_depthwise_3x3s2p1_bias_s_relu(dout,
din,
weights,
bias,
flag_bias,
true,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
} }
} }
break;
case lite_api::ActivationType::kRelu6:
if (pad == 0) { if (pad == 0) {
if (w_in > 8) { if (w_in > 8) {
if (relu6) { conv_depthwise_3x3s2p0_bias_relu6(dout,
conv_depthwise_3x3s2p0_bias(dout,
din, din,
weights, weights,
bias, bias,
vsix,
flag_bias, flag_bias,
num, num,
ch_in, ch_in,
...@@ -115,15 +234,14 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -115,15 +234,14 @@ void conv_depthwise_3x3s2_fp32(const float* din,
w_in, w_in,
h_out, h_out,
w_out, w_out,
act_param,
ctx); ctx);
} else { } else {
conv_depthwise_3x3s2p0_bias_relu(dout, conv_depthwise_3x3s2p0_bias_s_relu6(dout,
din, din,
weights, weights,
bias, bias,
vsix,
flag_bias, flag_bias,
flag_relu,
num, num,
ch_in, ch_in,
h_in, h_in,
...@@ -132,12 +250,14 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -132,12 +250,14 @@ void conv_depthwise_3x3s2_fp32(const float* din,
w_out, w_out,
ctx); ctx);
} }
} else { }
if (relu6) { if (pad == 1) {
conv_depthwise_3x3s2p0_bias_s(dout, if (w_in > 7) {
conv_depthwise_3x3s2p1_bias_relu6(dout,
din, din,
weights, weights,
bias, bias,
vsix,
flag_bias, flag_bias,
num, num,
ch_in, ch_in,
...@@ -145,15 +265,14 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -145,15 +265,14 @@ void conv_depthwise_3x3s2_fp32(const float* din,
w_in, w_in,
h_out, h_out,
w_out, w_out,
act_param,
ctx); ctx);
} else { } else {
conv_depthwise_3x3s2p0_bias_s_relu(dout, conv_depthwise_3x3s2p1_bias_s_relu6(dout,
din, din,
weights, weights,
bias, bias,
vsix,
flag_bias, flag_bias,
flag_relu,
num, num,
ch_in, ch_in,
h_in, h_in,
...@@ -163,14 +282,46 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -163,14 +282,46 @@ void conv_depthwise_3x3s2_fp32(const float* din,
ctx); ctx);
} }
} }
break;
case lite_api::ActivationType::kLeakyRelu:
if (pad == 0) {
if (w_in > 8) {
conv_depthwise_3x3s2p0_bias_leakyRelu(dout,
din,
weights,
bias,
vscale,
flag_bias,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
} else {
conv_depthwise_3x3s2p0_bias_s_leakyRelu(dout,
din,
weights,
bias,
vscale,
flag_bias,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
}
} }
if (pad == 1) { if (pad == 1) {
if (w_in > 7) { if (w_in > 7) {
if (relu6) { conv_depthwise_3x3s2p1_bias_leakyRelu(dout,
conv_depthwise_3x3s2p1_bias(dout,
din, din,
weights, weights,
bias, bias,
vscale,
flag_bias, flag_bias,
num, num,
ch_in, ch_in,
...@@ -178,15 +329,14 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -178,15 +329,14 @@ void conv_depthwise_3x3s2_fp32(const float* din,
w_in, w_in,
h_out, h_out,
w_out, w_out,
act_param,
ctx); ctx);
} else { } else {
conv_depthwise_3x3s2p1_bias_relu(dout, conv_depthwise_3x3s2p1_bias_s_leakyRelu(dout,
din, din,
weights, weights,
bias, bias,
vscale,
flag_bias, flag_bias,
flag_relu,
num, num,
ch_in, ch_in,
h_in, h_in,
...@@ -195,28 +345,66 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -195,28 +345,66 @@ void conv_depthwise_3x3s2_fp32(const float* din,
w_out, w_out,
ctx); ctx);
} }
}
break;
default:
LOG(FATAL) << "this act_type: " << static_cast<int>(act_type)
<< " fuse not support";
}
} else { } else {
if (relu6) { if (pad == 0) {
conv_depthwise_3x3s2p1_bias_s(dout, if (w_in > 8) {
conv_depthwise_3x3s2p0_bias_no_relu(dout,
din, din,
weights, weights,
bias, bias,
flag_bias, flag_bias,
false,
num, num,
ch_in, ch_in,
h_in, h_in,
w_in, w_in,
h_out, h_out,
w_out, w_out,
act_param,
ctx); ctx);
} else { } else {
conv_depthwise_3x3s2p1_bias_s_relu(dout, conv_depthwise_3x3s2p0_bias_s_no_relu(dout,
din,
weights,
bias,
flag_bias,
false,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
}
}
if (pad == 1) {
if (w_in > 7) {
conv_depthwise_3x3s2p1_bias_no_relu(dout,
din,
weights,
bias,
flag_bias,
false,
num,
ch_in,
h_in,
w_in,
h_out,
w_out,
ctx);
} else {
conv_depthwise_3x3s2p1_bias_s_no_relu(dout,
din, din,
weights, weights,
bias, bias,
flag_bias, flag_bias,
flag_relu, false,
num, num,
ch_in, ch_in,
h_in, h_in,
...@@ -228,6 +416,7 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -228,6 +416,7 @@ void conv_depthwise_3x3s2_fp32(const float* din,
} }
} }
} }
// clang-format off
#ifdef __aarch64__ #ifdef __aarch64__
#define INIT_S2 \ #define INIT_S2 \
"prfm pldl1keep, [%[inptr0]] \n" \ "prfm pldl1keep, [%[inptr0]] \n" \
...@@ -746,6 +935,18 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -746,6 +935,18 @@ void conv_depthwise_3x3s2_fp32(const float* din,
"fmax v4.4s, v4.4s, v9.4s \n" \ "fmax v4.4s, v4.4s, v9.4s \n" \
\ \
"st1 {v4.4s}, [%[out]] \n" "st1 {v4.4s}, [%[out]] \n"
#define RESULT_S_S2_RELU6 \
"fadd v4.4s, v4.4s, %[bias].4s \n" \
"fmax v4.4s, v4.4s, v9.4s \n" \
"fmin v4.4s, v4.4s, %[vsix].4s \n" \
\
"st1 {v4.4s}, [%[out]] \n"
#define RESULT_S_S2_LEAKY_RELU \
"fadd v4.4s, v4.4s, %[bias].4s \n" \
"fcmge v11.4s, v4.4s, %[vzero].4s \n"/* vcgeq_u32 */\
"fmul v12.4s, v4.4s, %[vscale].4s \n"\
"bif v4.16b, v12.16b, v11.16b \n" /* choose*/ \
"st1 {v4.4s}, [%[out]] \n"
#define COMPUTE_S_S2_P0 \ #define COMPUTE_S_S2_P0 \
"movi v9.4s, #0 \n" \ "movi v9.4s, #0 \n" \
"ld1 {v6.4s, v7.4s}, [%[mask_ptr]], #32 \n" \ "ld1 {v6.4s, v7.4s}, [%[mask_ptr]], #32 \n" \
...@@ -785,6 +986,15 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -785,6 +986,15 @@ void conv_depthwise_3x3s2_fp32(const float* din,
#define RESULT_S_S2_P0_RELU \ #define RESULT_S_S2_P0_RELU \
"fmax v4.4s, v4.4s, v9.4s \n" \ "fmax v4.4s, v4.4s, v9.4s \n" \
"st1 {v4.4s}, [%[out]] \n" "st1 {v4.4s}, [%[out]] \n"
#define RESULT_S_S2_P0_RELU6 \
"fmax v4.4s, v4.4s, v9.4s \n" \
"fmin v4.4s, v4.4s, %[vsix].4s \n" \
"st1 {v4.4s}, [%[out]] \n"
#define RESULT_S_S2_P0_LEAKY_RELU \
"fcmge v11.4s, v4.4s, %[vzero].4s \n"/* vcgeq_u32 */\
"fmul v12.4s, v4.4s, %[vscale].4s \n"\
"bif v4.16b, v12.16b, v11.16b \n" /* choose*/ \
"st1 {v4.4s}, [%[out]] \n"
#else #else
#define INIT_S2 \ #define INIT_S2 \
...@@ -822,12 +1032,11 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -822,12 +1032,11 @@ void conv_depthwise_3x3s2_fp32(const float* din,
"vmla.f32 q5, q15, %f[wr2][0] @ mul weight 1, out1\n" \ "vmla.f32 q5, q15, %f[wr2][0] @ mul weight 1, out1\n" \
"vmla.f32 q3, q8, %e[wr2][0] @ mul weight 1, out1\n" \ "vmla.f32 q3, q8, %e[wr2][0] @ mul weight 1, out1\n" \
\ \
"vld2.32 {d28-d31}, [%[din2_ptr]]! @ load din r1\n" \ "vld2.32 {d28-d31}, [%[din2_ptr]]! @ load din r1\n"
\
"vadd.f32 q3, q3, q4 @ add \n" \
"vadd.f32 q3, q3, q5 @ add \n"
#define LEFT_RESULT_S2 \ #define LEFT_RESULT_S2 \
"vadd.f32 q3, q3, q4 @ add \n"\
"vadd.f32 q3, q3, q5 @ add \n"\
"vst1.32 {d6-d7}, [%[outptr]]! \n" \ "vst1.32 {d6-d7}, [%[outptr]]! \n" \
"cmp %[cnt], #1 \n" \ "cmp %[cnt], #1 \n" \
"blt 1f \n" "blt 1f \n"
...@@ -860,12 +1069,11 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -860,12 +1069,11 @@ void conv_depthwise_3x3s2_fp32(const float* din,
"vmla.f32 q5, q15, %e[wr2][1] @ mul weight 2, out0\n" \ "vmla.f32 q5, q15, %e[wr2][1] @ mul weight 2, out0\n" \
"vmla.f32 q3, q6, %f[wr2][0] @ mul weight 2, out0\n" \ "vmla.f32 q3, q6, %f[wr2][0] @ mul weight 2, out0\n" \
\ \
"vld2.32 {d28-d31}, [%[din2_ptr]]! @ load din r2\n" \ "vld2.32 {d28-d31}, [%[din2_ptr]]! @ load din r2\n"
\
"vadd.f32 q3, q3, q4 @ add \n" \
"vadd.f32 q3, q3, q5 @ add \n"
#define MID_RESULT_S2 \ #define MID_RESULT_S2 \
"vadd.f32 q3, q3, q4 @ add \n"\
"vadd.f32 q3, q3, q5 @ add \n"\
"subs %[cnt], #1 \n" \ "subs %[cnt], #1 \n" \
\ \
"vst1.32 {d6-d7}, [%[outptr]]! \n" \ "vst1.32 {d6-d7}, [%[outptr]]! \n" \
...@@ -910,36 +1118,104 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -910,36 +1118,104 @@ void conv_depthwise_3x3s2_fp32(const float* din,
\ \
"vmla.f32 q4, q14, %e[wr2][0] @ mul weight 2, out0\n" \ "vmla.f32 q4, q14, %e[wr2][0] @ mul weight 2, out0\n" \
"vmla.f32 q5, q15, %e[wr2][1] @ mul weight 2, out0\n" \ "vmla.f32 q5, q15, %e[wr2][1] @ mul weight 2, out0\n" \
"vmla.f32 q3, q6, %f[wr2][0] @ mul weight 2, out0\n" \ "vmla.f32 q3, q6, %f[wr2][0] @ mul weight 2, out0\n"
\
"vadd.f32 q3, q3, q4 @ add \n" \
"vadd.f32 q3, q3, q5 @ add \n"
#define RIGHT_RESULT_S2 \ #define RIGHT_RESULT_S2 \
"vadd.f32 q3, q3, q4 @ add \n" \
"vadd.f32 q3, q3, q5 @ add \n" \
"vbif.f32 q3, q10, q11 @ write mask\n" \ "vbif.f32 q3, q10, q11 @ write mask\n" \
\ \
"vst1.32 {d6-d7}, [%[outptr]]! \n" \ "vst1.32 {d6-d7}, [%[outptr]]! \n" \
"3: \n" "3: \n"
#define LEFT_RESULT_S2_RELU \ #define LEFT_RESULT_S2_RELU \
"vmax.f32 q3, q3, q9 @ relu \n" \ "vadd.f32 q3, q3, q4 @ add \n"\
"vst1.32 {d6-d7}, [%[outptr]]! \n" \ "vadd.f32 q3, q3, q5 @ add \n"\
"cmp %[cnt], #1 \n" \ "vmax.f32 q3, q3, q9 \n"\
"cmp %[cnt], #1 \n"\
"vst1.32 {d6-d7}, [%[outptr]]! \n"\
"blt 1f \n"
#define LEFT_RESULT_S2_RELU6 \
"vadd.f32 q3, q3, q4 @ add \n"\
"vld1.f32 {d12-d13}, [%[six_ptr]] @ load six \n"\
"vadd.f32 q3, q3, q5 @ add \n"\
"vmax.f32 q3, q3, q9 @ relu \n"\
"cmp %[cnt], #1 \n"\
"vmin.f32 q3, q3, q6 @ relu \n"\
"vst1.32 {d6-d7}, [%[outptr]]! \n"\
"blt 1f \n"
#define LEFT_RESULT_S2_LEAKY_RELU \
"vadd.f32 q3, q3, q4 \n"\
"vld1.f32 {d12-d13}, [%[scale_ptr]] \n"\
"vadd.f32 q3, q3, q5 \n"\
"vcge.f32 q7, q3, q9 \n"\
"vmul.f32 q8, q3, q6 \n"\
"cmp %[cnt], #1 \n"\
"vbif q3, q8, q7 @ choose \n"\
"vst1.32 {d6-d7}, [%[outptr]]! \n"\
"blt 1f \n" "blt 1f \n"
#define MID_RESULT_S2_RELU \ #define MID_RESULT_S2_RELU \
"vmax.f32 q3, q3, q9 @ relu \n" \ "vadd.f32 q3, q3, q4 @ add \n"\
"subs %[cnt], #1 \n" \ "vadd.f32 q3, q3, q5 @ add \n"\
"subs %[cnt], #1 \n"\
"vmax.f32 q3, q3, q9 @ relu \n"\
\ \
"vst1.32 {d6-d7}, [%[outptr]]! \n" \ "vst1.32 {d6-d7}, [%[outptr]]! \n"\
"bne 2b \n"
#define MID_RESULT_S2_RELU6 \
"vadd.f32 q3, q3, q4 @ add \n"\
"vld1.f32 {d12-d13}, [%[six_ptr]] @ load six \n"\
"vadd.f32 q3, q3, q5 @ add \n"\
"vmax.f32 q3, q3, q9 @ relu \n"\
"subs %[cnt], #1 \n"\
"vmin.f32 q3, q3, q6 @ relu \n"\
\
"vst1.32 {d6-d7}, [%[outptr]]! \n"\
"bne 2b \n"
#define MID_RESULT_S2_LEAKY_RELU \
"vadd.f32 q3, q3, q4 @ add \n"\
"vld1.f32 {d12-d13}, [%[scale_ptr]] \n"\
"vadd.f32 q3, q3, q5 @ add \n"\
"vcge.f32 q7, q3, q9 \n"\
"vmul.f32 q8, q3, q6 \n"\
"subs %[cnt], #1 \n"\
"vbif q3, q8, q7 @ choose \n"\
\
"vst1.32 {d6-d7}, [%[outptr]]! \n"\
"bne 2b \n" "bne 2b \n"
#define RIGHT_RESULT_S2_RELU \ #define RIGHT_RESULT_S2_RELU \
"vmax.f32 q3, q3, q9 @ relu \n" \ "vadd.f32 q3, q3, q4 @ add \n"\
"vbif.f32 q3, q10, q11 @ write mask\n" \ "vadd.f32 q3, q3, q5 @ add \n"\
"vmax.f32 q3, q3, q9 @ relu\n"\
"vbif.f32 q3, q10, q11 @ write mask\n"\
\ \
"vst1.32 {d6-d7}, [%[outptr]]! \n" \ "vst1.32 {d6-d7}, [%[outptr]]! \n"\
"3: \n" "3: \n"
#define RIGHT_RESULT_S2_RELU6 \
"vadd.f32 q3, q3, q4 @ add \n"\
"vld1.f32 {d12-d13}, [%[six_ptr]] @ load six \n"\
"vadd.f32 q3, q3, q5 @ add \n"\
"vmax.f32 q3, q3, q9 @ relu\n"\
"vmin.f32 q3, q3, q6 @ relu \n"\
\
"vbif.f32 q3, q10, q11 @ write mask\n"\
\
"vst1.32 {d6-d7}, [%[outptr]]! \n"\
"3: \n"
#define RIGHT_RESULT_S2_LEAKY_RELU \
"vadd.f32 q3, q3, q4 @ add \n"\
"vld1.f32 {d12-d13}, [%[scale_ptr]] \n"\
"vadd.f32 q3, q3, q5 @ add \n"\
"vcge.f32 q7, q3, q9 \n"\
"vmul.f32 q8, q3, q6 \n"\
"vbif q3, q8, q7 @ choose \n"\
"vbif.f32 q3, q10, q11 @ write mask\n"\
\
"vst1.32 {d6-d7}, [%[outptr]]! \n"\
"3: \n"
#define COMPUTE_S_S2 \ #define COMPUTE_S_S2 \
"vmov.u32 q9, #0 \n" \ "vmov.u32 q9, #0 \n" \
"vld1.f32 {d12-d15}, [%[mask_ptr]]! @ load mask\n" \ "vld1.f32 {d12-d15}, [%[mask_ptr]]! @ load mask\n" \
...@@ -976,17 +1252,36 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -976,17 +1252,36 @@ void conv_depthwise_3x3s2_fp32(const float* din,
\ \
"vmla.f32 q4, q14, %e[wr2][1] @ mul weight 2, out0\n" \ "vmla.f32 q4, q14, %e[wr2][1] @ mul weight 2, out0\n" \
"vmla.f32 q5, q15, %f[wr2][0] @ mul weight 2, out0\n" \ "vmla.f32 q5, q15, %f[wr2][0] @ mul weight 2, out0\n" \
"vmla.f32 q3, q8, %e[wr2][0] @ mul weight 2, out0\n" \ "vmla.f32 q3, q8, %e[wr2][0] @ mul weight 2, out0\n"
\
"vadd.f32 q3, q3, q4 @ add \n" \
"vadd.f32 q3, q3, q5 @ add \n"
#define RESULT_S_S2 "vst1.32 {d6-d7}, [%[out]] \n" #define RESULT_S_S2 \
"vadd.f32 q3, q3, q4 @ add \n"\
"vadd.f32 q3, q3, q5 @ add \n"\
"vst1.32 {d6-d7}, [%[out]] \n"
#define RESULT_S_S2_RELU \ #define RESULT_S_S2_RELU \
"vmax.f32 q3, q3, q9 @ relu\n" \ "vadd.f32 q3, q3, q4 @ add \n"\
"vadd.f32 q3, q3, q5 @ add \n"\
"vmax.f32 q3, q3, q9 @ relu\n"\
\ \
"vst1.32 {d6-d7}, [%[out]] \n" "vst1.32 {d6-d7}, [%[out]] \n"
#define RESULT_S_S2_RELU6 \
"vadd.f32 q3, q3, q4 @ add \n"\
"vld1.f32 {d12-d13}, [%[six_ptr]] @ load six \n"\
"vadd.f32 q3, q3, q5 @ add \n"\
"vmax.f32 q3, q3, q9 @ relu\n"\
"vmin.f32 q3, q3, q6 @ relu\n"\
\
"vst1.32 {d6-d7}, [%[out]] \n"
#define RESULT_S_S2_LEAKY_RELU \
"vadd.f32 q3, q3, q4 @ add \n"\
"vld1.f32 {d12-d13}, [%[scale_ptr]] \n"\
"vadd.f32 q3, q3, q5 @ add \n"\
"vcge.f32 q7, q3, q9 \n"\
"vmul.f32 q8, q3, q6 \n"\
"vbif q3, q8, q7 @ choose \n"\
\
"vst1.32 {d6-d7}, [%[out]] \n"
#define COMPUTE_S_S2_P0 \ #define COMPUTE_S_S2_P0 \
"vmov.u32 q9, #0 \n" \ "vmov.u32 q9, #0 \n" \
"vld1.f32 {d12-d15}, [%[mask_ptr]] @ load mask\n" \ "vld1.f32 {d12-d15}, [%[mask_ptr]] @ load mask\n" \
...@@ -1023,198 +1318,44 @@ void conv_depthwise_3x3s2_fp32(const float* din, ...@@ -1023,198 +1318,44 @@ void conv_depthwise_3x3s2_fp32(const float* din,
\ \
"vmla.f32 q4, q14, %e[wr2][0] @ mul weight 2, out0\n" \ "vmla.f32 q4, q14, %e[wr2][0] @ mul weight 2, out0\n" \
"vmla.f32 q5, q15, %e[wr2][1] @ mul weight 2, out0\n" \ "vmla.f32 q5, q15, %e[wr2][1] @ mul weight 2, out0\n" \
"vmla.f32 q3, q8, %f[wr2][0] @ mul weight 2, out0\n" \ "vmla.f32 q3, q8, %f[wr2][0] @ mul weight 2, out0\n"
\
"vadd.f32 q3, q3, q4 @ add \n" \
"vadd.f32 q3, q3, q5 @ add \n"
#define RESULT_S_S2_P0 "vst1.32 {d6-d7}, [%[out]] \n" #define RESULT_S_S2_P0 \
"vadd.f32 q3, q3, q4 @ add \n" \
"vadd.f32 q3, q3, q5 @ add \n" \
"vst1.32 {d6-d7}, [%[out]] \n"
#define RESULT_S_S2_P0_RELU \ #define RESULT_S_S2_P0_RELU \
"vadd.f32 q3, q3, q4 @ add \n" \
"vadd.f32 q3, q3, q5 @ add \n" \
"vmax.f32 q3, q3, q9 @ relu \n" \ "vmax.f32 q3, q3, q9 @ relu \n" \
"vst1.32 {d6-d7}, [%[out]] \n" "vst1.32 {d6-d7}, [%[out]] \n"
#define RESULT_S_S2_P0_RELU6 \
"vadd.f32 q3, q3, q4 @ add \n" \
"vld1.f32 {d12-d13}, [%[six_ptr]] @ load six \n" \
"vadd.f32 q3, q3, q5 @ add \n" \
"vmax.f32 q3, q3, q9 @ relu\n" \
"vmin.f32 q3, q3, q6 @ relu\n" \
"vst1.32 {d6-d7}, [%[out]] \n"
#define RESULT_S_S2_P0_LEAKY_RELU \
"vadd.f32 q3, q3, q4 @ add \n" \
"vld1.f32 {d12-d13}, [%[scale_ptr]] @ load six \n" \
"vadd.f32 q3, q3, q5 @ add \n" \
"vcge.f32 q7, q3, q9 \n" \
"vmul.f32 q8, q3, q6 \n" \
"vbif q3, q8, q7 @ choose \n" \
"vst1.32 {d6-d7}, [%[out]] \n"
#endif #endif
#ifdef __aarch64__ // clang-format on
void act_switch_3x3s2p1(const float* din0_ptr,
const float* din1_ptr,
const float* din2_ptr,
const float* din3_ptr,
const float* din4_ptr,
float* doutr0_ptr,
float* doutr1_ptr,
float32x4_t wr0,
float32x4_t wr1,
float32x4_t wr2,
uint32x4_t vmask_rp1,
uint32x4_t vmask_rp2,
uint32x4_t wmask,
float32x4_t wbias,
float32x4_t vzero,
int cnt,
int cnt_remain,
const operators::ActivationParam act_param) {
float tmp = act_param.Relu_clipped_coef;
float ss = act_param.Leaky_relu_alpha;
float vsix[4] = {tmp, tmp, tmp, tmp};
float vscale[4] = {ss, ss, ss, ss};
switch (act_param.active_type) {
case lite_api::ActivationType::kRelu:
asm volatile(INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2_RELU MID_COMPUTE_S2
MID_RESULT_S2_RELU RIGHT_COMPUTE_S2 RIGHT_RESULT_S2_RELU
: [inptr0] "+r"(din0_ptr),
[inptr1] "+r"(din1_ptr),
[inptr2] "+r"(din2_ptr),
[inptr3] "+r"(din3_ptr),
[inptr4] "+r"(din4_ptr),
[outptr0] "+r"(doutr0_ptr),
[outptr1] "+r"(doutr1_ptr),
[cnt] "+r"(cnt)
: [vzero] "w"(vzero),
[w0] "w"(wr0),
[w1] "w"(wr1),
[w2] "w"(wr2),
[remain] "r"(cnt_remain),
[mask1] "w"(vmask_rp1),
[mask2] "w"(vmask_rp2),
[wmask] "w"(wmask),
[vbias] "w"(wbias)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21");
break;
case lite_api::ActivationType::kRelu6:
/* 0 <= din <= 6 */
asm volatile(
INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2_RELU6 MID_COMPUTE_S2
MID_RESULT_S2_RELU6 RIGHT_COMPUTE_S2 RIGHT_RESULT_S2_RELU6
: [inptr0] "+r"(din0_ptr),
[inptr1] "+r"(din1_ptr),
[inptr2] "+r"(din2_ptr),
[inptr3] "+r"(din3_ptr),
[inptr4] "+r"(din4_ptr),
[outptr0] "+r"(doutr0_ptr),
[outptr1] "+r"(doutr1_ptr),
[cnt] "+r"(cnt)
: [vzero] "w"(vzero),
[w0] "w"(wr0),
[w1] "w"(wr1),
[w2] "w"(wr2),
[remain] "r"(cnt_remain),
[six_ptr] "r"(vsix),
[mask1] "w"(vmask_rp1),
[mask2] "w"(vmask_rp2),
[wmask] "w"(wmask),
[vbias] "w"(wbias)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21",
"v22");
break;
case lite_api::ActivationType::kLeakyRelu:
/*din = din >= 0 ? din : din * scale*/
asm volatile(INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2_LEAKY_RELU
MID_COMPUTE_S2 MID_RESULT_S2_LEAKY_RELU RIGHT_COMPUTE_S2
RIGHT_RESULT_S2_LEAKY_RELU
: [inptr0] "+r"(din0_ptr),
[inptr1] "+r"(din1_ptr),
[inptr2] "+r"(din2_ptr),
[inptr3] "+r"(din3_ptr),
[inptr4] "+r"(din4_ptr),
[outptr0] "+r"(doutr0_ptr),
[outptr1] "+r"(doutr1_ptr),
[cnt] "+r"(cnt)
: [vzero] "w"(vzero),
[w0] "w"(wr0),
[w1] "w"(wr1),
[w2] "w"(wr2),
[remain] "r"(cnt_remain),
[scale_ptr] "r"(vscale),
[mask1] "w"(vmask_rp1),
[mask2] "w"(vmask_rp2),
[wmask] "w"(wmask),
[vbias] "w"(wbias)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21",
"v22");
break;
default:
LOG(FATAL) << "this act_type: " << static_cast<int>(act_param.active_type)
<< " fuse not support";
}
}
#endif
/** /**
* \brief depthwise convolution kernel 3x3, stride 2 * \brief depthwise convolution kernel 3x3, stride 2
* w_in > 7 * w_in > 7
*/ */
void conv_depthwise_3x3s2p1_bias(float* dout, void conv_depthwise_3x3s2p1_bias_relu6(float* dout,
const float* din, const float* din,
const float* weights, const float* weights,
const float* bias, const float* bias,
const float* six,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -1222,7 +1363,6 @@ void conv_depthwise_3x3s2p1_bias(float* dout, ...@@ -1222,7 +1363,6 @@ void conv_depthwise_3x3s2p1_bias(float* dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext* ctx) { ARMContext* ctx) {
int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7}; int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7};
int out_pad_idx[4] = {0, 1, 2, 3}; int out_pad_idx[4] = {0, 1, 2, 3};
...@@ -1350,24 +1490,52 @@ void conv_depthwise_3x3s2p1_bias(float* dout, ...@@ -1350,24 +1490,52 @@ void conv_depthwise_3x3s2p1_bias(float* dout,
doutr1_ptr = write_ptr; doutr1_ptr = write_ptr;
} }
int cnt = cnt_col; int cnt = cnt_col;
act_switch_3x3s2p1(din0_ptr, asm volatile(
din1_ptr, INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2_RELU6 MID_COMPUTE_S2
din2_ptr, MID_RESULT_S2_RELU6 RIGHT_COMPUTE_S2 RIGHT_RESULT_S2_RELU6
din3_ptr, : [inptr0] "+r"(din0_ptr),
din4_ptr, [inptr1] "+r"(din1_ptr),
doutr0_ptr, [inptr2] "+r"(din2_ptr),
doutr1_ptr, [inptr3] "+r"(din3_ptr),
wr0, [inptr4] "+r"(din4_ptr),
wr1, [outptr0] "+r"(doutr0_ptr),
wr2, [outptr1] "+r"(doutr1_ptr),
vmask_rp1, [cnt] "+r"(cnt)
vmask_rp2, : [vzero] "w"(vzero),
wmask, [w0] "w"(wr0),
wbias, [w1] "w"(wr1),
vzero, [w2] "w"(wr2),
cnt, [remain] "r"(cnt_remain),
cnt_remain, [six_ptr] "r"(six),
act_param); [mask1] "w"(vmask_rp1),
[mask2] "w"(vmask_rp2),
[wmask] "w"(wmask),
[vbias] "w"(wbias)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21",
"v22");
doutr0 = doutr0 + 2 * w_out; doutr0 = doutr0 + 2 * w_out;
} }
#else #else
...@@ -1404,8 +1572,9 @@ void conv_depthwise_3x3s2p1_bias(float* dout, ...@@ -1404,8 +1572,9 @@ void conv_depthwise_3x3s2p1_bias(float* dout,
} }
int cnt = cnt_col; int cnt = cnt_col;
unsigned int* mask_ptr = dmask; unsigned int* mask_ptr = dmask;
asm volatile(INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2 MID_COMPUTE_S2 asm volatile(
MID_RESULT_S2 RIGHT_COMPUTE_S2 RIGHT_RESULT_S2 INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2_RELU6 MID_COMPUTE_S2
MID_RESULT_S2_RELU6 RIGHT_COMPUTE_S2 RIGHT_RESULT_S2_RELU6
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr), [din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr), [din2_ptr] "+r"(din2_ptr),
...@@ -1416,6 +1585,7 @@ void conv_depthwise_3x3s2p1_bias(float* dout, ...@@ -1416,6 +1585,7 @@ void conv_depthwise_3x3s2p1_bias(float* dout,
[wr0] "w"(wr0), [wr0] "w"(wr0),
[wr1] "w"(wr1), [wr1] "w"(wr1),
[wr2] "w"(wr2), [wr2] "w"(wr2),
[six_ptr] "r"(six),
[bias] "r"(bias_c) [bias] "r"(bias_c)
: "cc", : "cc",
"memory", "memory",
...@@ -1432,24 +1602,17 @@ void conv_depthwise_3x3s2p1_bias(float* dout, ...@@ -1432,24 +1602,17 @@ void conv_depthwise_3x3s2p1_bias(float* dout,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
// do act
if (act_param.has_active) {
act_switch_process(doutr0, doutr0, w_out, &act_param);
}
doutr0 = doutr0 + w_out; doutr0 = doutr0 + w_out;
} }
#endif #endif
} }
} }
} }
void conv_depthwise_3x3s2p1_bias_leakyRelu(float* dout,
/**
* \brief depthwise convolution kernel 3x3, stride 2, width <= 4
*/
void conv_depthwise_3x3s2p1_bias_s(float* dout,
const float* din, const float* din,
const float* weights, const float* weights,
const float* bias, const float* bias,
const float* scale,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -1457,23 +1620,41 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout, ...@@ -1457,23 +1620,41 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext* ctx) { ARMContext* ctx) {
int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7}; int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7};
int out_pad_idx[4] = {0, 1, 2, 3}; int out_pad_idx[4] = {0, 1, 2, 3};
float zeros[8] = {0.0f}; int size_pad_bottom = h_out * 2 - h_in;
uint32x4_t vmask_rp1 = int tile_w = w_out >> 2;
vcgtq_s32(vdupq_n_s32(w_in), vld1q_s32(right_pad_idx)); // 0 2 4 6 int cnt_remain = w_out % 4;
uint32x4_t vmask_rp2 = unsigned int size_right_remain = (unsigned int)(7 + (tile_w << 3) - w_in);
vcgtq_s32(vdupq_n_s32(w_in), vld1q_s32(right_pad_idx + 4)); // 1 3 5 7 size_right_remain = 8 - size_right_remain;
if (cnt_remain == 0 && size_right_remain == 0) {
cnt_remain = 4;
tile_w -= 1;
size_right_remain = 8;
}
int cnt_col = tile_w - 1;
uint32x4_t vmask_rp1 = vcgtq_s32(vdupq_n_s32(size_right_remain),
vld1q_s32(right_pad_idx)); // 0 2 4 6
uint32x4_t vmask_rp2 = vcgtq_s32(vdupq_n_s32(size_right_remain),
vld1q_s32(right_pad_idx + 4)); // 1 3 5 7
uint32x4_t wmask =
vcgtq_s32(vdupq_n_s32(cnt_remain), vld1q_s32(out_pad_idx)); // 0 1 2 3
int size_in_channel = w_in * h_in; int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out; int size_out_channel = w_out * h_out;
unsigned int dmask[8]; float* zero_ptr = ctx->workspace_data<float>();
memset(zero_ptr, 0, w_in * sizeof(float));
float* write_ptr = zero_ptr + w_in;
unsigned int dmask[12];
vst1q_u32(dmask, vmask_rp1); vst1q_u32(dmask, vmask_rp1);
vst1q_u32(dmask + 4, vmask_rp2); vst1q_u32(dmask + 4, vmask_rp2);
vst1q_u32(dmask + 8, wmask);
for (int n = 0; n < num; ++n) { for (int n = 0; n < num; ++n) {
const float* din_batch = din + n * ch_in * size_in_channel; const float* din_batch = din + n * ch_in * size_in_channel;
...@@ -1488,32 +1669,406 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout, ...@@ -1488,32 +1669,406 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout,
float32x4_t wr1 = vld1q_f32(weight_ptr + 3); float32x4_t wr1 = vld1q_f32(weight_ptr + 3);
float32x4_t wr2 = vld1q_f32(weight_ptr + 6); float32x4_t wr2 = vld1q_f32(weight_ptr + 6);
float32x4_t vzero = vdupq_n_f32(0.f);
#ifdef __aarch64__
float32x4_t wbias;
if (flag_bias) {
wbias = vdupq_n_f32(bias[i]);
} else {
wbias = vdupq_n_f32(0.f);
}
#else
float bias_c = 0.f; float bias_c = 0.f;
if (flag_bias) { if (flag_bias) {
bias_c = bias[i]; bias_c = bias[i];
} }
float32x4_t vbias = vdupq_n_f32(bias_c); #endif // __aarch64__
int hs = -1;
int he = 2; const float* dr0 = din_channel;
float out_buf[4];
for (int j = 0; j < h_out; ++j) {
const float* dr0 = din_channel + hs * w_in;
const float* dr1 = dr0 + w_in; const float* dr1 = dr0 + w_in;
const float* dr2 = dr1 + w_in; const float* dr2 = dr1 + w_in;
if (hs == -1) { const float* dr3 = dr2 + w_in;
dr0 = zeros; const float* dr4 = dr3 + w_in;
}
if (he > h_in) {
dr2 = zeros;
}
const float* din0_ptr = dr0; const float* din0_ptr = dr0;
const float* din1_ptr = dr1; const float* din1_ptr = dr1;
const float* din2_ptr = dr2; const float* din2_ptr = dr2;
const float* din3_ptr = dr3;
const float* din4_ptr = dr4;
float* doutr0 = dout_channel;
float* doutr0_ptr = nullptr;
float* doutr1_ptr = nullptr;
unsigned int* mask_ptr = dmask;
#ifdef __aarch64__ #ifdef __aarch64__
asm volatile(COMPUTE_S_S2 RESULT_S_S2 for (int i = 0; i < h_out; i += 2) {
din0_ptr = dr0;
din1_ptr = dr1;
din2_ptr = dr2;
din3_ptr = dr3;
din4_ptr = dr4;
doutr0_ptr = doutr0;
doutr1_ptr = doutr0 + w_out;
if (i == 0) {
din0_ptr = zero_ptr;
din1_ptr = dr0;
din2_ptr = dr1;
din3_ptr = dr2;
din4_ptr = dr3;
dr0 = dr3;
dr1 = dr4;
} else {
dr0 = dr4;
dr1 = dr0 + w_in;
}
dr2 = dr1 + w_in;
dr3 = dr2 + w_in;
dr4 = dr3 + w_in;
//! process bottom pad
if (i * 2 + 4 > h_in) {
switch (i * 2 + 4 - h_in) {
case 4:
din1_ptr = zero_ptr;
case 3:
din2_ptr = zero_ptr;
case 2:
din3_ptr = zero_ptr;
case 1:
din4_ptr = zero_ptr;
default:
break;
}
}
//! process output pad
if (i + 2 > h_out) {
doutr1_ptr = write_ptr;
}
int cnt = cnt_col;
asm volatile(INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2_LEAKY_RELU
MID_COMPUTE_S2 MID_RESULT_S2_LEAKY_RELU
RIGHT_COMPUTE_S2 RIGHT_RESULT_S2_LEAKY_RELU
: [inptr0] "+r"(din0_ptr),
[inptr1] "+r"(din1_ptr),
[inptr2] "+r"(din2_ptr),
[inptr3] "+r"(din3_ptr),
[inptr4] "+r"(din4_ptr),
[outptr0] "+r"(doutr0_ptr),
[outptr1] "+r"(doutr1_ptr),
[cnt] "+r"(cnt)
: [vzero] "w"(vzero),
[w0] "w"(wr0),
[w1] "w"(wr1),
[w2] "w"(wr2),
[remain] "r"(cnt_remain),
[scale_ptr] "r"(scale),
[mask1] "w"(vmask_rp1),
[mask2] "w"(vmask_rp2),
[wmask] "w"(wmask),
[vbias] "w"(wbias)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21",
"v22");
doutr0 = doutr0 + 2 * w_out;
}
#else
for (int i = 0; i < h_out; i++) {
din0_ptr = dr0;
din1_ptr = dr1;
din2_ptr = dr2;
doutr0_ptr = doutr0;
if (i == 0) {
din0_ptr = zero_ptr;
din1_ptr = dr0;
din2_ptr = dr1;
dr0 = dr1;
dr1 = dr2;
dr2 = dr1 + w_in;
} else {
dr0 = dr2;
dr1 = dr0 + w_in;
dr2 = dr1 + w_in;
}
//! process bottom pad
if (i * 2 + 2 > h_in) {
switch (i * 2 + 2 - h_in) {
case 2:
din1_ptr = zero_ptr;
case 1:
din2_ptr = zero_ptr;
default:
break;
}
}
int cnt = cnt_col;
unsigned int* mask_ptr = dmask;
asm volatile(INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2_LEAKY_RELU
MID_COMPUTE_S2 MID_RESULT_S2_LEAKY_RELU
RIGHT_COMPUTE_S2 RIGHT_RESULT_S2_LEAKY_RELU
: [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr),
[outptr] "+r"(doutr0_ptr),
[cnt] "+r"(cnt),
[mask_ptr] "+r"(mask_ptr)
: [remain] "r"(cnt_remain),
[wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[scale_ptr] "r"(scale),
[bias] "r"(bias_c)
: "cc",
"memory",
"q3",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
doutr0 = doutr0 + w_out;
}
#endif
}
}
}
/**
* \brief depthwise convolution kernel 3x3, stride 2, width <= 4
*/
void conv_depthwise_3x3s2p1_bias_s_relu6(float* dout,
const float* din,
const float* weights,
const float* bias,
const float* six,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx) {
int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7};
int out_pad_idx[4] = {0, 1, 2, 3};
float zeros[8] = {0.0f};
uint32x4_t vmask_rp1 =
vcgtq_s32(vdupq_n_s32(w_in), vld1q_s32(right_pad_idx)); // 0 2 4 6
uint32x4_t vmask_rp2 =
vcgtq_s32(vdupq_n_s32(w_in), vld1q_s32(right_pad_idx + 4)); // 1 3 5 7
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
unsigned int dmask[8];
vst1q_u32(dmask, vmask_rp1);
vst1q_u32(dmask + 4, vmask_rp2);
#ifdef __aarch64__
float32x4_t vsix = vld1q_f32(six);
#endif
for (int n = 0; n < num; ++n) {
const float* din_batch = din + n * ch_in * size_in_channel;
float* dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int i = 0; i < ch_in; ++i) {
const float* din_channel = din_batch + i * size_in_channel;
float* dout_channel = dout_batch + i * size_out_channel;
const float* weight_ptr = weights + i * 9;
float32x4_t wr0 = vld1q_f32(weight_ptr);
float32x4_t wr1 = vld1q_f32(weight_ptr + 3);
float32x4_t wr2 = vld1q_f32(weight_ptr + 6);
float bias_c = 0.f;
if (flag_bias) {
bias_c = bias[i];
}
float32x4_t vbias = vdupq_n_f32(bias_c);
int hs = -1;
int he = 2;
float out_buf[4];
for (int j = 0; j < h_out; ++j) {
const float* dr0 = din_channel + hs * w_in;
const float* dr1 = dr0 + w_in;
const float* dr2 = dr1 + w_in;
if (hs == -1) {
dr0 = zeros;
}
if (he > h_in) {
dr2 = zeros;
}
const float* din0_ptr = dr0;
const float* din1_ptr = dr1;
const float* din2_ptr = dr2;
unsigned int* mask_ptr = dmask;
#ifdef __aarch64__
asm volatile(COMPUTE_S_S2 RESULT_S_S2_RELU6
: [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr),
[mask_ptr] "+r"(mask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[bias] "w"(vbias),
[vsix] "w"(vsix),
[out] "r"(out_buf)
: "v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15");
#else
asm volatile(COMPUTE_S_S2 RESULT_S_S2_RELU6
: [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr),
[mask_ptr] "+r"(mask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[bias] "r"(bias_c),
[six_ptr] "r"(six),
[out] "r"(out_buf)
: "cc",
"memory",
"q3",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
#endif
for (int w = 0; w < w_out; ++w) {
*dout_channel++ = out_buf[w];
}
hs += 2;
he += 2;
}
}
}
}
void conv_depthwise_3x3s2p1_bias_s_leakyRelu(float* dout,
const float* din,
const float* weights,
const float* bias,
const float* scale,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx) {
int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7};
int out_pad_idx[4] = {0, 1, 2, 3};
float zeros[8] = {0.0f};
uint32x4_t vmask_rp1 =
vcgtq_s32(vdupq_n_s32(w_in), vld1q_s32(right_pad_idx)); // 0 2 4 6
uint32x4_t vmask_rp2 =
vcgtq_s32(vdupq_n_s32(w_in), vld1q_s32(right_pad_idx + 4)); // 1 3 5 7
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
unsigned int dmask[8];
vst1q_u32(dmask, vmask_rp1);
vst1q_u32(dmask + 4, vmask_rp2);
#ifdef __aarch64__
float32x4_t vscale = vld1q_f32(scale);
float32x4_t vzero = vdupq_n_f32(0.f);
#endif
for (int n = 0; n < num; ++n) {
const float* din_batch = din + n * ch_in * size_in_channel;
float* dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int i = 0; i < ch_in; ++i) {
const float* din_channel = din_batch + i * size_in_channel;
float* dout_channel = dout_batch + i * size_out_channel;
const float* weight_ptr = weights + i * 9;
float32x4_t wr0 = vld1q_f32(weight_ptr);
float32x4_t wr1 = vld1q_f32(weight_ptr + 3);
float32x4_t wr2 = vld1q_f32(weight_ptr + 6);
float bias_c = 0.f;
if (flag_bias) {
bias_c = bias[i];
}
float32x4_t vbias = vdupq_n_f32(bias_c);
int hs = -1;
int he = 2;
float out_buf[4];
for (int j = 0; j < h_out; ++j) {
const float* dr0 = din_channel + hs * w_in;
const float* dr1 = dr0 + w_in;
const float* dr2 = dr1 + w_in;
if (hs == -1) {
dr0 = zeros;
}
if (he > h_in) {
dr2 = zeros;
}
const float* din0_ptr = dr0;
const float* din1_ptr = dr1;
const float* din2_ptr = dr2;
unsigned int* mask_ptr = dmask;
#ifdef __aarch64__
asm volatile(COMPUTE_S_S2 RESULT_S_S2_LEAKY_RELU
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr), [din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr), [din2_ptr] "+r"(din2_ptr),
...@@ -1522,6 +2077,8 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout, ...@@ -1522,6 +2077,8 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout,
[wr1] "w"(wr1), [wr1] "w"(wr1),
[wr2] "w"(wr2), [wr2] "w"(wr2),
[bias] "w"(vbias), [bias] "w"(vbias),
[vzero] "w"(vzero),
[vscale] "w"(vscale),
[out] "r"(out_buf) [out] "r"(out_buf)
: "v4", : "v4",
"v5", "v5",
...@@ -1536,7 +2093,7 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout, ...@@ -1536,7 +2093,7 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout,
"v14", "v14",
"v15"); "v15");
#else #else
asm volatile(COMPUTE_S_S2 RESULT_S_S2 asm volatile(COMPUTE_S_S2 RESULT_S_S2_LEAKY_RELU
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr), [din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr), [din2_ptr] "+r"(din2_ptr),
...@@ -1545,6 +2102,7 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout, ...@@ -1545,6 +2102,7 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout,
[wr1] "w"(wr1), [wr1] "w"(wr1),
[wr2] "w"(wr2), [wr2] "w"(wr2),
[bias] "r"(bias_c), [bias] "r"(bias_c),
[scale_ptr] "r"(scale),
[out] "r"(out_buf) [out] "r"(out_buf)
: "cc", : "cc",
"memory", "memory",
...@@ -1562,10 +2120,6 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout, ...@@ -1562,10 +2120,6 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout,
"q14", "q14",
"q15"); "q15");
#endif #endif
// do act
if (act_param.has_active) {
act_switch_process(out_buf, out_buf, w_out, &act_param);
}
for (int w = 0; w < w_out; ++w) { for (int w = 0; w < w_out; ++w) {
*dout_channel++ = out_buf[w]; *dout_channel++ = out_buf[w];
} }
...@@ -1575,90 +2129,141 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout, ...@@ -1575,90 +2129,141 @@ void conv_depthwise_3x3s2p1_bias_s(float* dout,
} }
} }
} }
/**
* \brief depthwise convolution kernel 3x3, stride 2
*/
// w_in > 7
void conv_depthwise_3x3s2p0_bias_relu6(float* dout,
const float* din,
const float* weights,
const float* bias,
const float* six,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx) {
int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7};
int out_pad_idx[4] = {0, 1, 2, 3};
int tile_w = w_out >> 2;
int cnt_remain = w_out % 4;
unsigned int size_right_remain = (unsigned int)(8 + (tile_w << 3) - w_in);
size_right_remain = 8 - size_right_remain;
if (cnt_remain == 0 && size_right_remain == 0) {
cnt_remain = 4;
tile_w -= 1;
size_right_remain = 8;
}
uint32x4_t vmask_rp1 = vcgtq_s32(vdupq_n_s32(size_right_remain),
vld1q_s32(right_pad_idx)); // 0 2 4 6
uint32x4_t vmask_rp2 = vcgtq_s32(vdupq_n_s32(size_right_remain),
vld1q_s32(right_pad_idx + 4)); // 1 3 5 7
uint32x4_t wmask =
vcgtq_s32(vdupq_n_s32(cnt_remain), vld1q_s32(out_pad_idx)); // 0 1 2 3
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
float* zero_ptr = ctx->workspace_data<float>();
memset(zero_ptr, 0, w_in * sizeof(float));
float* write_ptr = zero_ptr + w_in;
unsigned int dmask[12];
vst1q_u32(dmask, vmask_rp1);
vst1q_u32(dmask + 4, vmask_rp2);
vst1q_u32(dmask + 8, wmask);
for (int n = 0; n < num; ++n) {
const float* din_batch = din + n * ch_in * size_in_channel;
float* dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int i = 0; i < ch_in; ++i) {
const float* din_channel = din_batch + i * size_in_channel;
float* dout_channel = dout_batch + i * size_out_channel;
const float* weight_ptr = weights + i * 9;
float32x4_t wr0 = vld1q_f32(weight_ptr);
float32x4_t wr1 = vld1q_f32(weight_ptr + 3);
float32x4_t wr2 = vld1q_f32(weight_ptr + 6);
float32x4_t vzero = vdupq_n_f32(0.f);
#ifdef __aarch64__ #ifdef __aarch64__
void act_switch_3x3s2p0(const float* din0_ptr, float32x4_t wbias;
const float* din1_ptr, if (flag_bias) {
const float* din2_ptr, wbias = vdupq_n_f32(bias[i]);
const float* din3_ptr, } else {
const float* din4_ptr, wbias = vdupq_n_f32(0.f);
float* doutr0_ptr, }
float* doutr1_ptr, #else
float32x4_t wr0, float bias_c = 0.f;
float32x4_t wr1, if (flag_bias) {
float32x4_t wr2, bias_c = bias[i];
uint32x4_t vmask_rp1, }
uint32x4_t vmask_rp2, #endif // __aarch64__
uint32x4_t wmask,
float32x4_t wbias,
float32x4_t vzero,
int cnt,
int cnt_remain,
const operators::ActivationParam act_param) {
float tmp = act_param.Relu_clipped_coef;
float ss = act_param.Leaky_relu_alpha;
float vsix[4] = {tmp, tmp, tmp, tmp};
float vscale[4] = {ss, ss, ss, ss};
switch (act_param.active_type) { const float* dr0 = din_channel;
case lite_api::ActivationType::kRelu: const float* dr1 = dr0 + w_in;
asm volatile( const float* dr2 = dr1 + w_in;
INIT_S2 const float* dr3 = dr2 + w_in;
"ld1 {v15.4s}, [%[inptr0]] \n" const float* dr4 = dr3 + w_in;
"ld1 {v18.4s}, [%[inptr1]] \n"
"ld1 {v19.4s}, [%[inptr2]] \n" const float* din0_ptr = dr0;
"ld1 {v20.4s}, [%[inptr3]] \n" const float* din1_ptr = dr1;
"ld1 {v21.4s}, [%[inptr4]] \n" const float* din2_ptr = dr2;
"ext v10.16b, v0.16b, v15.16b, #4 \n" // v10 = {2,4,6,8} const float* din3_ptr = dr3;
MID_COMPUTE_S2 MID_RESULT_S2_RELU const float* din4_ptr = dr4;
"cmp %w[remain], #1 \n"
"blt 4f \n" RIGHT_COMPUTE_S2 float* doutr0 = dout_channel;
RIGHT_RESULT_S2_RELU float* doutr0_ptr = nullptr;
"4: \n" float* doutr1_ptr = nullptr;
: [inptr0] "+r"(din0_ptr),
[inptr1] "+r"(din1_ptr), #ifdef __aarch64__
[inptr2] "+r"(din2_ptr), for (int i = 0; i < h_out; i += 2) {
[inptr3] "+r"(din3_ptr), din0_ptr = dr0;
[inptr4] "+r"(din4_ptr), din1_ptr = dr1;
[outptr0] "+r"(doutr0_ptr), din2_ptr = dr2;
[outptr1] "+r"(doutr1_ptr), din3_ptr = dr3;
[cnt] "+r"(cnt) din4_ptr = dr4;
: [vzero] "w"(vzero),
[w0] "w"(wr0), doutr0_ptr = doutr0;
[w1] "w"(wr1), doutr1_ptr = doutr0 + w_out;
[w2] "w"(wr2),
[remain] "r"(cnt_remain), dr0 = dr4;
[mask1] "w"(vmask_rp1), dr1 = dr0 + w_in;
[mask2] "w"(vmask_rp2), dr2 = dr1 + w_in;
[wmask] "w"(wmask), dr3 = dr2 + w_in;
[vbias] "w"(wbias) dr4 = dr3 + w_in;
: "cc",
"memory", //! process bottom pad
"v0", if (i * 2 + 5 > h_in) {
"v1", switch (i * 2 + 5 - h_in) {
"v2", case 4:
"v3", din1_ptr = zero_ptr;
"v4", case 3:
"v5", din2_ptr = zero_ptr;
"v6", case 2:
"v7", din3_ptr = zero_ptr;
"v8", case 1:
"v9", din4_ptr = zero_ptr;
"v10", case 0:
"v11", din4_ptr = zero_ptr;
"v12", default:
"v13",
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21");
break; break;
case lite_api::ActivationType::kRelu6: }
/* 0 <= din <= 6 */ }
//! process output pad
if (i + 2 > h_out) {
doutr1_ptr = write_ptr;
}
int cnt = tile_w;
asm volatile( asm volatile(
INIT_S2 INIT_S2
"ld1 {v15.4s}, [%[inptr0]] \n" "ld1 {v15.4s}, [%[inptr0]] \n"
...@@ -1686,7 +2291,7 @@ void act_switch_3x3s2p0(const float* din0_ptr, ...@@ -1686,7 +2291,7 @@ void act_switch_3x3s2p0(const float* din0_ptr,
[w1] "w"(wr1), [w1] "w"(wr1),
[w2] "w"(wr2), [w2] "w"(wr2),
[remain] "r"(cnt_remain), [remain] "r"(cnt_remain),
[six_ptr] "r"(vsix), [six_ptr] "r"(six),
[mask1] "w"(vmask_rp1), [mask1] "w"(vmask_rp1),
[mask2] "w"(vmask_rp2), [mask2] "w"(vmask_rp2),
[wmask] "w"(wmask), [wmask] "w"(wmask),
...@@ -1716,81 +2321,74 @@ void act_switch_3x3s2p0(const float* din0_ptr, ...@@ -1716,81 +2321,74 @@ void act_switch_3x3s2p0(const float* din0_ptr,
"v20", "v20",
"v21", "v21",
"v22"); "v22");
doutr0 = doutr0 + 2 * w_out;
}
#else
for (int i = 0; i < h_out; i++) {
din0_ptr = dr0;
din1_ptr = dr1;
din2_ptr = dr2;
doutr0_ptr = doutr0;
dr0 = dr2;
dr1 = dr0 + w_in;
dr2 = dr1 + w_in;
//! process bottom pad
if (i * 2 + 3 > h_in) {
switch (i * 2 + 3 - h_in) {
case 2:
din1_ptr = zero_ptr;
case 1:
din2_ptr = zero_ptr;
default:
break; break;
case lite_api::ActivationType::kLeakyRelu: }
/*din = din >= 0 ? din : din * scale*/ }
asm volatile( int cnt = tile_w;
INIT_S2 unsigned int* mask_ptr = dmask;
"ld1 {v15.4s}, [%[inptr0]] \n" asm volatile(INIT_S2 MID_COMPUTE_S2 MID_RESULT_S2_RELU6 RIGHT_COMPUTE_S2
"ld1 {v18.4s}, [%[inptr1]] \n" RIGHT_RESULT_S2_RELU6
"ld1 {v19.4s}, [%[inptr2]] \n" : [din0_ptr] "+r"(din0_ptr),
"ld1 {v20.4s}, [%[inptr3]] \n" [din1_ptr] "+r"(din1_ptr),
"ld1 {v21.4s}, [%[inptr4]] \n" [din2_ptr] "+r"(din2_ptr),
"ext v10.16b, v0.16b, v15.16b, #4 \n" // v10 = {2,4,6,8} [outptr] "+r"(doutr0_ptr),
"ld1 {v22.4s}, [%[scale_ptr]] \n" MID_COMPUTE_S2 [cnt] "+r"(cnt),
MID_RESULT_S2_LEAKY_RELU [mask_ptr] "+r"(mask_ptr)
"cmp %w[remain], #1 \n" : [remain] "r"(cnt_remain),
"blt 4f \n" RIGHT_COMPUTE_S2 [six_ptr] "r"(six),
RIGHT_RESULT_S2_LEAKY_RELU [wr0] "w"(wr0),
"4: \n" [wr1] "w"(wr1),
: [inptr0] "+r"(din0_ptr), [wr2] "w"(wr2),
[inptr1] "+r"(din1_ptr), [bias] "r"(bias_c)
[inptr2] "+r"(din2_ptr),
[inptr3] "+r"(din3_ptr),
[inptr4] "+r"(din4_ptr),
[outptr0] "+r"(doutr0_ptr),
[outptr1] "+r"(doutr1_ptr),
[cnt] "+r"(cnt)
: [vzero] "w"(vzero),
[w0] "w"(wr0),
[w1] "w"(wr1),
[w2] "w"(wr2),
[remain] "r"(cnt_remain),
[scale_ptr] "r"(vscale),
[mask1] "w"(vmask_rp1),
[mask2] "w"(vmask_rp2),
[wmask] "w"(wmask),
[vbias] "w"(wbias)
: "cc", : "cc",
"memory", "memory",
"v0", "q3",
"v1", "q4",
"v2", "q5",
"v3", "q6",
"v4", "q7",
"v5", "q8",
"v6", "q9",
"v7", "q10",
"v8", "q11",
"v9", "q12",
"v10", "q13",
"v11", "q14",
"v12", "q15");
"v13", doutr0 = doutr0 + w_out;
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21",
"v22");
break;
default:
LOG(FATAL) << "this act_type: " << static_cast<int>(act_param.active_type)
<< " fuse not support";
} }
}
#endif #endif
/** }
* \brief depthwise convolution kernel 3x3, stride 2 }
*/ }
// w_in > 7
void conv_depthwise_3x3s2p0_bias(float* dout, void conv_depthwise_3x3s2p0_bias_leakyRelu(float* dout,
const float* din, const float* din,
const float* weights, const float* weights,
const float* bias, const float* bias,
const float* scale,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -1798,7 +2396,6 @@ void conv_depthwise_3x3s2p0_bias(float* dout, ...@@ -1798,7 +2396,6 @@ void conv_depthwise_3x3s2p0_bias(float* dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext* ctx) { ARMContext* ctx) {
int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7}; int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7};
int out_pad_idx[4] = {0, 1, 2, 3}; int out_pad_idx[4] = {0, 1, 2, 3};
...@@ -1918,24 +2515,63 @@ void conv_depthwise_3x3s2p0_bias(float* dout, ...@@ -1918,24 +2515,63 @@ void conv_depthwise_3x3s2p0_bias(float* dout,
doutr1_ptr = write_ptr; doutr1_ptr = write_ptr;
} }
int cnt = tile_w; int cnt = tile_w;
act_switch_3x3s2p0(din0_ptr, asm volatile(
din1_ptr, INIT_S2
din2_ptr, "ld1 {v15.4s}, [%[inptr0]] \n"
din3_ptr, "ld1 {v18.4s}, [%[inptr1]] \n"
din4_ptr, "ld1 {v19.4s}, [%[inptr2]] \n"
doutr0_ptr, "ld1 {v20.4s}, [%[inptr3]] \n"
doutr1_ptr, "ld1 {v21.4s}, [%[inptr4]] \n"
wr0, "ext v10.16b, v0.16b, v15.16b, #4 \n" // v10 = {2,4,6,8}
wr1, "ld1 {v22.4s}, [%[scale_ptr]] \n" MID_COMPUTE_S2
wr2, MID_RESULT_S2_LEAKY_RELU
vmask_rp1, "cmp %w[remain], #1 \n"
vmask_rp2, "blt 4f \n" RIGHT_COMPUTE_S2
wmask, RIGHT_RESULT_S2_LEAKY_RELU
wbias, "4: \n"
vzero, : [inptr0] "+r"(din0_ptr),
cnt, [inptr1] "+r"(din1_ptr),
cnt_remain, [inptr2] "+r"(din2_ptr),
act_param); [inptr3] "+r"(din3_ptr),
[inptr4] "+r"(din4_ptr),
[outptr0] "+r"(doutr0_ptr),
[outptr1] "+r"(doutr1_ptr),
[cnt] "+r"(cnt)
: [vzero] "w"(vzero),
[w0] "w"(wr0),
[w1] "w"(wr1),
[w2] "w"(wr2),
[remain] "r"(cnt_remain),
[scale_ptr] "r"(scale),
[mask1] "w"(vmask_rp1),
[mask2] "w"(vmask_rp2),
[wmask] "w"(wmask),
[vbias] "w"(wbias)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21",
"v22");
doutr0 = doutr0 + 2 * w_out; doutr0 = doutr0 + 2 * w_out;
} }
#else #else
...@@ -1963,8 +2599,8 @@ void conv_depthwise_3x3s2p0_bias(float* dout, ...@@ -1963,8 +2599,8 @@ void conv_depthwise_3x3s2p0_bias(float* dout,
} }
int cnt = tile_w; int cnt = tile_w;
unsigned int* mask_ptr = dmask; unsigned int* mask_ptr = dmask;
asm volatile(INIT_S2 MID_COMPUTE_S2 MID_RESULT_S2 RIGHT_COMPUTE_S2 asm volatile(INIT_S2 MID_COMPUTE_S2 MID_RESULT_S2_LEAKY_RELU
RIGHT_RESULT_S2 RIGHT_COMPUTE_S2 RIGHT_RESULT_S2_LEAKY_RELU
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr), [din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr), [din2_ptr] "+r"(din2_ptr),
...@@ -1972,6 +2608,7 @@ void conv_depthwise_3x3s2p0_bias(float* dout, ...@@ -1972,6 +2608,7 @@ void conv_depthwise_3x3s2p0_bias(float* dout,
[cnt] "+r"(cnt), [cnt] "+r"(cnt),
[mask_ptr] "+r"(mask_ptr) [mask_ptr] "+r"(mask_ptr)
: [remain] "r"(cnt_remain), : [remain] "r"(cnt_remain),
[scale_ptr] "r"(scale),
[wr0] "w"(wr0), [wr0] "w"(wr0),
[wr1] "w"(wr1), [wr1] "w"(wr1),
[wr2] "w"(wr2), [wr2] "w"(wr2),
...@@ -1991,9 +2628,6 @@ void conv_depthwise_3x3s2p0_bias(float* dout, ...@@ -1991,9 +2628,6 @@ void conv_depthwise_3x3s2p0_bias(float* dout,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
if (act_param.has_active) {
act_switch_process(doutr0, doutr0, w_out, &act_param);
}
doutr0 = doutr0 + w_out; doutr0 = doutr0 + w_out;
} }
#endif #endif
...@@ -2004,10 +2638,11 @@ void conv_depthwise_3x3s2p0_bias(float* dout, ...@@ -2004,10 +2638,11 @@ void conv_depthwise_3x3s2p0_bias(float* dout,
/** /**
* \brief depthwise convolution kernel 3x3, stride 2, width <= 4 * \brief depthwise convolution kernel 3x3, stride 2, width <= 4
*/ */
void conv_depthwise_3x3s2p0_bias_s(float* dout, void conv_depthwise_3x3s2p0_bias_s_relu6(float* dout,
const float* din, const float* din,
const float* weights, const float* weights,
const float* bias, const float* bias,
const float* six,
bool flag_bias, bool flag_bias,
const int num, const int num,
const int ch_in, const int ch_in,
...@@ -2015,7 +2650,6 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout, ...@@ -2015,7 +2650,6 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout,
const int w_in, const int w_in,
const int h_out, const int h_out,
const int w_out, const int w_out,
const operators::ActivationParam act_param,
ARMContext* ctx) { ARMContext* ctx) {
int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7}; int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7};
int out_pad_idx[4] = {0, 1, 2, 3}; int out_pad_idx[4] = {0, 1, 2, 3};
...@@ -2033,6 +2667,10 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout, ...@@ -2033,6 +2667,10 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout,
unsigned int dmask[8]; unsigned int dmask[8];
vst1q_u32(dmask, vmask_rp1); vst1q_u32(dmask, vmask_rp1);
vst1q_u32(dmask + 4, vmask_rp2); vst1q_u32(dmask + 4, vmask_rp2);
#ifdef __aarch64__
float32x4_t vsix = vld1q_f32(six);
float32x4_t vzero = vdupq_n_f32(0.f);
#endif
for (int n = 0; n < num; ++n) { for (int n = 0; n < num; ++n) {
const float* din_batch = din + n * ch_in * size_in_channel; const float* din_batch = din + n * ch_in * size_in_channel;
...@@ -2077,7 +2715,7 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout, ...@@ -2077,7 +2715,7 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout,
unsigned int* mask_ptr = dmask; unsigned int* mask_ptr = dmask;
#ifdef __aarch64__ #ifdef __aarch64__
asm volatile(COMPUTE_S_S2_P0 RESULT_S_S2_P0 asm volatile(COMPUTE_S_S2_P0 RESULT_S_S2_P0_RELU6
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr), [din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr), [din2_ptr] "+r"(din2_ptr),
...@@ -2086,6 +2724,8 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout, ...@@ -2086,6 +2724,8 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout,
[wr1] "w"(wr1), [wr1] "w"(wr1),
[wr2] "w"(wr2), [wr2] "w"(wr2),
[bias] "w"(vbias), [bias] "w"(vbias),
[vzero] "w"(vzero),
[vsix] "w"(vsix),
[out] "r"(out_buf) [out] "r"(out_buf)
: "cc", : "cc",
"memory", "memory",
...@@ -2104,7 +2744,7 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout, ...@@ -2104,7 +2744,7 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout,
"v16"); "v16");
#else #else
asm volatile(COMPUTE_S_S2_P0 RESULT_S_S2_P0 asm volatile(COMPUTE_S_S2_P0 RESULT_S_S2_P0_RELU6
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr), [din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr) [din2_ptr] "+r"(din2_ptr)
...@@ -2113,6 +2753,7 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout, ...@@ -2113,6 +2753,7 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout,
[wr2] "w"(wr2), [wr2] "w"(wr2),
[bias] "r"(bias_c), [bias] "r"(bias_c),
[out] "r"(out_buf), [out] "r"(out_buf),
[six_ptr] "r"(six),
[mask_ptr] "r"(dmask) [mask_ptr] "r"(dmask)
: "cc", : "cc",
"memory", "memory",
...@@ -2130,9 +2771,145 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout, ...@@ -2130,9 +2771,145 @@ void conv_depthwise_3x3s2p0_bias_s(float* dout,
"q14", "q14",
"q15"); "q15");
#endif #endif
if (act_param.has_active) { for (int w = 0; w < w_out; ++w) {
act_switch_process(out_buf, out_buf, w_out, &act_param); *dout_channel++ = out_buf[w];
}
}
}
}
}
void conv_depthwise_3x3s2p0_bias_s_leakyRelu(float* dout,
const float* din,
const float* weights,
const float* bias,
const float* scale,
bool flag_bias,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx) {
int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7};
int out_pad_idx[4] = {0, 1, 2, 3};
float zeros[8] = {0.0f};
const float zero_ptr[4] = {0.f, 0.f, 0.f, 0.f};
uint32x4_t vmask_rp1 =
vcgtq_s32(vdupq_n_s32(w_in), vld1q_s32(right_pad_idx)); // 0 2 4 6
uint32x4_t vmask_rp2 =
vcgtq_s32(vdupq_n_s32(w_in), vld1q_s32(right_pad_idx + 4)); // 1 3 5 7
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
unsigned int dmask[8];
vst1q_u32(dmask, vmask_rp1);
vst1q_u32(dmask + 4, vmask_rp2);
#ifdef __aarch64__
float32x4_t vscale = vld1q_f32(scale);
float32x4_t vzero = vdupq_n_f32(0.f);
#endif
for (int n = 0; n < num; ++n) {
const float* din_batch = din + n * ch_in * size_in_channel;
float* dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int i = 0; i < ch_in; ++i) {
const float* din_channel = din_batch + i * size_in_channel;
float* dout_channel = dout_batch + i * size_out_channel;
const float* weight_ptr = weights + i * 9;
float32x4_t wr0 = vld1q_f32(weight_ptr);
float32x4_t wr1 = vld1q_f32(weight_ptr + 3);
float32x4_t wr2 = vld1q_f32(weight_ptr + 6);
float bias_c = 0.f;
if (flag_bias) {
bias_c = bias[i];
}
float32x4_t vbias = vdupq_n_f32(bias_c);
float out_buf[4];
const float* dr0 = din_channel;
const float* dr1 = dr0 + w_in;
const float* dr2 = dr1 + w_in;
for (int j = 0; j < h_out; j++) {
const float* din0_ptr = dr0;
const float* din1_ptr = dr1;
const float* din2_ptr = dr2;
if (j * 2 + 2 >= h_in) {
switch (j + 2 - h_in) {
case 1:
din1_ptr = zero_ptr;
case 0:
din2_ptr = zero_ptr;
default:
break;
}
} }
dr0 = dr2;
dr1 = dr0 + w_in;
dr2 = dr1 + w_in;
unsigned int* mask_ptr = dmask;
#ifdef __aarch64__
asm volatile(COMPUTE_S_S2_P0 RESULT_S_S2_P0_LEAKY_RELU
: [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr),
[mask_ptr] "+r"(mask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[bias] "w"(vbias),
[vzero] "w"(vzero),
[vscale] "w"(vscale),
[out] "r"(out_buf)
: "cc",
"memory",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16");
#else
asm volatile(COMPUTE_S_S2_P0 RESULT_S_S2_P0_LEAKY_RELU
: [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[bias] "r"(bias_c),
[out] "r"(out_buf),
[scale_ptr] "r"(scale),
[mask_ptr] "r"(dmask)
: "cc",
"memory",
"q3",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
#endif
for (int w = 0; w < w_out; ++w) { for (int w = 0; w < w_out; ++w) {
*dout_channel++ = out_buf[w]; *dout_channel++ = out_buf[w];
} }
......
lite/backends/arm/math/conv3x3s2p01_depthwise_fp32_relu.cc
浏览文件 @ 9e38adc8
...@@ -20,6 +20,7 @@ namespace lite { ...@@ -20,6 +20,7 @@ namespace lite {
namespace arm { namespace arm {
namespace math { namespace math {
// clang-format off
#ifdef __aarch64__ #ifdef __aarch64__
#define INIT_S2 \ #define INIT_S2 \
"prfm pldl1keep, [%[inptr0]] \n" \ "prfm pldl1keep, [%[inptr0]] \n" \
...@@ -683,6 +684,7 @@ namespace math { ...@@ -683,6 +684,7 @@ namespace math {
"vst1.32 {d6-d7}, [%[out]] \n" "vst1.32 {d6-d7}, [%[out]] \n"
#endif #endif
// clang-format on
/** /**
* \brief depthwise convolution kernel 3x3, stride 2 * \brief depthwise convolution kernel 3x3, stride 2
...@@ -825,7 +827,6 @@ void conv_depthwise_3x3s2p1_bias_relu(float* dout, ...@@ -825,7 +827,6 @@ void conv_depthwise_3x3s2p1_bias_relu(float* dout,
doutr1_ptr = write_ptr; doutr1_ptr = write_ptr;
} }
int cnt = cnt_col; int cnt = cnt_col;
if (flag_relu) {
asm volatile( asm volatile(
INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2_RELU MID_COMPUTE_S2 INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2_RELU MID_COMPUTE_S2
MID_RESULT_S2_RELU RIGHT_COMPUTE_S2 RIGHT_RESULT_S2_RELU MID_RESULT_S2_RELU RIGHT_COMPUTE_S2 RIGHT_RESULT_S2_RELU
...@@ -870,7 +871,215 @@ void conv_depthwise_3x3s2p1_bias_relu(float* dout, ...@@ -870,7 +871,215 @@ void conv_depthwise_3x3s2p1_bias_relu(float* dout,
"v19", "v19",
"v20", "v20",
"v21"); "v21");
doutr0 = doutr0 + 2 * w_out;
}
#else
for (int i = 0; i < h_in; i += 2) {
din0_ptr = dr0;
din1_ptr = dr1;
din2_ptr = dr2;
doutr0_ptr = doutr0;
if (i == 0) {
din0_ptr = zero_ptr;
din1_ptr = dr0;
din2_ptr = dr1;
dr0 = dr1;
dr1 = dr2;
dr2 = dr1 + w_in;
} else {
dr0 = dr2;
dr1 = dr0 + w_in;
dr2 = dr1 + w_in;
}
//! process bottom pad
if (i + 2 > h_in) {
switch (i + 2 - h_in) {
case 2:
din1_ptr = zero_ptr;
case 1:
din2_ptr = zero_ptr;
default:
break;
}
}
int cnt = cnt_col;
unsigned int* mask_ptr = dmask;
asm volatile(
INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2_RELU MID_COMPUTE_S2
MID_RESULT_S2_RELU RIGHT_COMPUTE_S2 RIGHT_RESULT_S2_RELU
: [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr),
[outptr] "+r"(doutr0_ptr),
[cnt] "+r"(cnt),
[mask_ptr] "+r"(mask_ptr)
: [remain] "r"(cnt_remain),
[wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[bias] "r"(bias_c)
: "cc",
"memory",
"q3",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
doutr0 = doutr0 + w_out;
}
#endif
}
}
}
void conv_depthwise_3x3s2p1_bias_no_relu(float* dout,
const float* din,
const float* weights,
const float* bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx) {
int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7};
int out_pad_idx[4] = {0, 1, 2, 3};
int size_pad_bottom = h_out * 2 - h_in;
int cnt_col = (w_out >> 2) - 2;
int size_right_remain = w_in - (7 + cnt_col * 8);
if (size_right_remain >= 9) {
cnt_col++;
size_right_remain -= 8;
}
int cnt_remain = (size_right_remain == 8) ? 4 : (w_out % 4); //
int size_right_pad = w_out * 2 - w_in;
uint32x4_t vmask_rp1 = vcgtq_s32(vdupq_n_s32(size_right_remain),
vld1q_s32(right_pad_idx)); // 0 2 4 6
uint32x4_t vmask_rp2 = vcgtq_s32(vdupq_n_s32(size_right_remain),
vld1q_s32(right_pad_idx + 4)); // 1 3 5 7
uint32x4_t wmask =
vcgtq_s32(vdupq_n_s32(cnt_remain), vld1q_s32(out_pad_idx)); // 0 1 2 3
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
float* zero_ptr = ctx->workspace_data<float>();
memset(zero_ptr, 0, w_in * sizeof(float));
float* write_ptr = zero_ptr + w_in;
unsigned int dmask[12];
vst1q_u32(dmask, vmask_rp1);
vst1q_u32(dmask + 4, vmask_rp2);
vst1q_u32(dmask + 8, wmask);
for (int n = 0; n < num; ++n) {
const float* din_batch = din + n * ch_in * size_in_channel;
float* dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int i = 0; i < ch_in; ++i) {
const float* din_channel = din_batch + i * size_in_channel;
float* dout_channel = dout_batch + i * size_out_channel;
const float* weight_ptr = weights + i * 9;
float32x4_t wr0 = vld1q_f32(weight_ptr);
float32x4_t wr1 = vld1q_f32(weight_ptr + 3);
float32x4_t wr2 = vld1q_f32(weight_ptr + 6);
float32x4_t vzero = vdupq_n_f32(0.f);
#ifdef __aarch64__
float32x4_t wbias;
if (flag_bias) {
wbias = vdupq_n_f32(bias[i]);
} else {
wbias = vdupq_n_f32(0.f);
}
#else
float bias_c = 0.f;
if (flag_bias) {
bias_c = bias[i];
}
#endif // __aarch64__
const float* dr0 = din_channel;
const float* dr1 = dr0 + w_in;
const float* dr2 = dr1 + w_in;
const float* dr3 = dr2 + w_in;
const float* dr4 = dr3 + w_in;
const float* din0_ptr = dr0;
const float* din1_ptr = dr1;
const float* din2_ptr = dr2;
const float* din3_ptr = dr3;
const float* din4_ptr = dr4;
float* doutr0 = dout_channel;
float* doutr0_ptr = nullptr;
float* doutr1_ptr = nullptr;
#ifdef __aarch64__
for (int i = 0; i < h_in; i += 4) {
din0_ptr = dr0;
din1_ptr = dr1;
din2_ptr = dr2;
din3_ptr = dr3;
din4_ptr = dr4;
doutr0_ptr = doutr0;
doutr1_ptr = doutr0 + w_out;
if (i == 0) {
din0_ptr = zero_ptr;
din1_ptr = dr0;
din2_ptr = dr1;
din3_ptr = dr2;
din4_ptr = dr3;
dr0 = dr3;
dr1 = dr4;
} else { } else {
dr0 = dr4;
dr1 = dr0 + w_in;
}
dr2 = dr1 + w_in;
dr3 = dr2 + w_in;
dr4 = dr3 + w_in;
//! process bottom pad
if (i + 4 > h_in) {
switch (i + 4 - h_in) {
case 4:
din1_ptr = zero_ptr;
case 3:
din2_ptr = zero_ptr;
case 2:
din3_ptr = zero_ptr;
case 1:
din4_ptr = zero_ptr;
default:
break;
}
}
//! process output pad
if (i / 2 + 2 > h_out) {
doutr1_ptr = write_ptr;
}
int cnt = cnt_col;
asm volatile(INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2 MID_COMPUTE_S2 asm volatile(INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2 MID_COMPUTE_S2
MID_RESULT_S2 RIGHT_COMPUTE_S2 RIGHT_RESULT_S2 MID_RESULT_S2 RIGHT_COMPUTE_S2 RIGHT_RESULT_S2
: [inptr0] "+r"(din0_ptr), : [inptr0] "+r"(din0_ptr),
...@@ -914,7 +1123,6 @@ void conv_depthwise_3x3s2p1_bias_relu(float* dout, ...@@ -914,7 +1123,6 @@ void conv_depthwise_3x3s2p1_bias_relu(float* dout,
"v19", "v19",
"v20", "v20",
"v21"); "v21");
}
doutr0 = doutr0 + 2 * w_out; doutr0 = doutr0 + 2 * w_out;
} }
#else #else
...@@ -951,37 +1159,6 @@ void conv_depthwise_3x3s2p1_bias_relu(float* dout, ...@@ -951,37 +1159,6 @@ void conv_depthwise_3x3s2p1_bias_relu(float* dout,
} }
int cnt = cnt_col; int cnt = cnt_col;
unsigned int* mask_ptr = dmask; unsigned int* mask_ptr = dmask;
if (flag_relu) {
asm volatile(
INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2_RELU MID_COMPUTE_S2
MID_RESULT_S2_RELU RIGHT_COMPUTE_S2 RIGHT_RESULT_S2_RELU
: [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr),
[outptr] "+r"(doutr0_ptr),
[cnt] "+r"(cnt),
[mask_ptr] "+r"(mask_ptr)
: [remain] "r"(cnt_remain),
[wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[bias] "r"(bias_c)
: "cc",
"memory",
"q3",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
} else {
asm volatile(INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2 MID_COMPUTE_S2 asm volatile(INIT_S2 LEFT_COMPUTE_S2 LEFT_RESULT_S2 MID_COMPUTE_S2
MID_RESULT_S2 RIGHT_COMPUTE_S2 RIGHT_RESULT_S2 MID_RESULT_S2 RIGHT_COMPUTE_S2 RIGHT_RESULT_S2
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
...@@ -1010,7 +1187,6 @@ void conv_depthwise_3x3s2p1_bias_relu(float* dout, ...@@ -1010,7 +1187,6 @@ void conv_depthwise_3x3s2p1_bias_relu(float* dout,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
}
doutr0 = doutr0 + w_out; doutr0 = doutr0 + w_out;
} }
#endif #endif
...@@ -1088,7 +1264,6 @@ void conv_depthwise_3x3s2p1_bias_s_relu(float* dout, ...@@ -1088,7 +1264,6 @@ void conv_depthwise_3x3s2p1_bias_s_relu(float* dout,
unsigned int* mask_ptr = dmask; unsigned int* mask_ptr = dmask;
#ifdef __aarch64__ #ifdef __aarch64__
if (flag_relu) {
asm volatile(COMPUTE_S_S2 RESULT_S_S2_RELU asm volatile(COMPUTE_S_S2 RESULT_S_S2_RELU
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr), [din1_ptr] "+r"(din1_ptr),
...@@ -1111,8 +1286,8 @@ void conv_depthwise_3x3s2p1_bias_s_relu(float* dout, ...@@ -1111,8 +1286,8 @@ void conv_depthwise_3x3s2p1_bias_s_relu(float* dout,
"v13", "v13",
"v14", "v14",
"v15"); "v15");
} else { #else
asm volatile(COMPUTE_S_S2 RESULT_S_S2 asm volatile(COMPUTE_S_S2 RESULT_S_S2_RELU
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr), [din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr), [din2_ptr] "+r"(din2_ptr),
...@@ -1120,24 +1295,124 @@ void conv_depthwise_3x3s2p1_bias_s_relu(float* dout, ...@@ -1120,24 +1295,124 @@ void conv_depthwise_3x3s2p1_bias_s_relu(float* dout,
: [wr0] "w"(wr0), : [wr0] "w"(wr0),
[wr1] "w"(wr1), [wr1] "w"(wr1),
[wr2] "w"(wr2), [wr2] "w"(wr2),
[bias] "w"(vbias), [bias] "r"(bias_c),
[out] "r"(out_buf) [out] "r"(out_buf)
: "v4", : "cc",
"v5", "memory",
"v6", "q3",
"v7", "q4",
"v8", "q5",
"v9", "q6",
"v10", "q7",
"v11", "q8",
"v12", "q9",
"v13", "q10",
"v14", "q11",
"v15"); "q12",
"q13",
"q14",
"q15");
#endif
for (int w = 0; w < w_out; ++w) {
*dout_channel++ = out_buf[w];
}
hs += 2;
he += 2;
}
}
} }
}
void conv_depthwise_3x3s2p1_bias_s_no_relu(float* dout,
const float* din,
const float* weights,
const float* bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx) {
int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7};
int out_pad_idx[4] = {0, 1, 2, 3};
float zeros[8] = {0.0f};
uint32x4_t vmask_rp1 =
vcgtq_s32(vdupq_n_s32(w_in), vld1q_s32(right_pad_idx)); // 0 2 4 6
uint32x4_t vmask_rp2 =
vcgtq_s32(vdupq_n_s32(w_in), vld1q_s32(right_pad_idx + 4)); // 1 3 5 7
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
unsigned int dmask[8];
vst1q_u32(dmask, vmask_rp1);
vst1q_u32(dmask + 4, vmask_rp2);
for (int n = 0; n < num; ++n) {
const float* din_batch = din + n * ch_in * size_in_channel;
float* dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int i = 0; i < ch_in; ++i) {
const float* din_channel = din_batch + i * size_in_channel;
float* dout_channel = dout_batch + i * size_out_channel;
const float* weight_ptr = weights + i * 9;
float32x4_t wr0 = vld1q_f32(weight_ptr);
float32x4_t wr1 = vld1q_f32(weight_ptr + 3);
float32x4_t wr2 = vld1q_f32(weight_ptr + 6);
float bias_c = 0.f;
if (flag_bias) {
bias_c = bias[i];
}
float32x4_t vbias = vdupq_n_f32(bias_c);
int hs = -1;
int he = 2;
float out_buf[4];
for (int j = 0; j < h_out; ++j) {
const float* dr0 = din_channel + hs * w_in;
const float* dr1 = dr0 + w_in;
const float* dr2 = dr1 + w_in;
if (hs == -1) {
dr0 = zeros;
}
if (he > h_in) {
dr2 = zeros;
}
const float* din0_ptr = dr0;
const float* din1_ptr = dr1;
const float* din2_ptr = dr2;
unsigned int* mask_ptr = dmask;
#ifdef __aarch64__
asm volatile(COMPUTE_S_S2 RESULT_S_S2
: [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr),
[mask_ptr] "+r"(mask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[bias] "w"(vbias),
[out] "r"(out_buf)
: "v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15");
#else #else
if (flag_relu) { asm volatile(COMPUTE_S_S2 RESULT_S_S2
asm volatile(COMPUTE_S_S2 RESULT_S_S2_RELU
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr), [din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr), [din2_ptr] "+r"(din2_ptr),
...@@ -1162,17 +1437,245 @@ void conv_depthwise_3x3s2p1_bias_s_relu(float* dout, ...@@ -1162,17 +1437,245 @@ void conv_depthwise_3x3s2p1_bias_s_relu(float* dout,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
#endif
for (int w = 0; w < w_out; ++w) {
*dout_channel++ = out_buf[w];
}
hs += 2;
he += 2;
}
}
}
}
/**
* \brief depthwise convolution kernel 3x3, stride 2
*/
// w_in > 7
void conv_depthwise_3x3s2p0_bias_relu(float* dout,
const float* din,
const float* weights,
const float* bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx) {
int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7};
int out_pad_idx[4] = {0, 1, 2, 3};
int tile_w = w_out >> 2;
int cnt_remain = w_out % 4;
unsigned int size_right_remain = (unsigned int)(8 + (tile_w << 3) - w_in);
size_right_remain = 8 - size_right_remain;
if (cnt_remain == 0 && size_right_remain == 0) {
cnt_remain = 4;
tile_w -= 1;
size_right_remain = 8;
}
uint32x4_t vmask_rp1 = vcgtq_s32(vdupq_n_s32(size_right_remain),
vld1q_s32(right_pad_idx)); // 0 2 4 6
uint32x4_t vmask_rp2 = vcgtq_s32(vdupq_n_s32(size_right_remain),
vld1q_s32(right_pad_idx + 4)); // 1 3 5 7
uint32x4_t wmask =
vcgtq_s32(vdupq_n_s32(cnt_remain), vld1q_s32(out_pad_idx)); // 0 1 2 3
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
float* zero_ptr = ctx->workspace_data<float>();
memset(zero_ptr, 0, w_in * sizeof(float));
float* write_ptr = zero_ptr + w_in;
unsigned int dmask[12];
vst1q_u32(dmask, vmask_rp1);
vst1q_u32(dmask + 4, vmask_rp2);
vst1q_u32(dmask + 8, wmask);
for (int n = 0; n < num; ++n) {
const float* din_batch = din + n * ch_in * size_in_channel;
float* dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int i = 0; i < ch_in; ++i) {
const float* din_channel = din_batch + i * size_in_channel;
float* dout_channel = dout_batch + i * size_out_channel;
const float* weight_ptr = weights + i * 9;
float32x4_t wr0 = vld1q_f32(weight_ptr);
float32x4_t wr1 = vld1q_f32(weight_ptr + 3);
float32x4_t wr2 = vld1q_f32(weight_ptr + 6);
float32x4_t vzero = vdupq_n_f32(0.f);
#ifdef __aarch64__
float32x4_t wbias;
if (flag_bias) {
wbias = vdupq_n_f32(bias[i]);
} else { } else {
asm volatile(COMPUTE_S_S2 RESULT_S_S2 wbias = vdupq_n_f32(0.f);
}
#else
float bias_c = 0.f;
if (flag_bias) {
bias_c = bias[i];
}
#endif // __aarch64__
const float* dr0 = din_channel;
const float* dr1 = dr0 + w_in;
const float* dr2 = dr1 + w_in;
const float* dr3 = dr2 + w_in;
const float* dr4 = dr3 + w_in;
const float* din0_ptr = dr0;
const float* din1_ptr = dr1;
const float* din2_ptr = dr2;
const float* din3_ptr = dr3;
const float* din4_ptr = dr4;
float* doutr0 = dout_channel;
float* doutr0_ptr = nullptr;
float* doutr1_ptr = nullptr;
#ifdef __aarch64__
for (int i = 0; i < h_out; i += 2) {
din0_ptr = dr0;
din1_ptr = dr1;
din2_ptr = dr2;
din3_ptr = dr3;
din4_ptr = dr4;
doutr0_ptr = doutr0;
doutr1_ptr = doutr0 + w_out;
dr0 = dr4;
dr1 = dr0 + w_in;
dr2 = dr1 + w_in;
dr3 = dr2 + w_in;
dr4 = dr3 + w_in;
//! process bottom pad
if (i * 2 + 5 > h_in) {
switch (i * 2 + 5 - h_in) {
case 4:
din1_ptr = zero_ptr;
case 3:
din2_ptr = zero_ptr;
case 2:
din3_ptr = zero_ptr;
case 1:
din4_ptr = zero_ptr;
case 0:
din4_ptr = zero_ptr;
default:
break;
}
}
//! process output pad
if (i + 2 > h_out) {
doutr1_ptr = write_ptr;
}
int cnt = tile_w;
asm volatile(
INIT_S2
"ld1 {v15.4s}, [%[inptr0]] \n"
"ld1 {v18.4s}, [%[inptr1]] \n"
"ld1 {v19.4s}, [%[inptr2]] \n"
"ld1 {v20.4s}, [%[inptr3]] \n"
"ld1 {v21.4s}, [%[inptr4]] \n"
"ext v10.16b, v0.16b, v15.16b, #4 \n" // v10 = {2,4,6,8}
MID_COMPUTE_S2 MID_RESULT_S2_RELU
"cmp %w[remain], #1 \n"
"blt 4f \n" RIGHT_COMPUTE_S2
RIGHT_RESULT_S2_RELU
"4: \n"
: [inptr0] "+r"(din0_ptr),
[inptr1] "+r"(din1_ptr),
[inptr2] "+r"(din2_ptr),
[inptr3] "+r"(din3_ptr),
[inptr4] "+r"(din4_ptr),
[outptr0] "+r"(doutr0_ptr),
[outptr1] "+r"(doutr1_ptr),
[cnt] "+r"(cnt)
: [vzero] "w"(vzero),
[w0] "w"(wr0),
[w1] "w"(wr1),
[w2] "w"(wr2),
[remain] "r"(cnt_remain),
[mask1] "w"(vmask_rp1),
[mask2] "w"(vmask_rp2),
[wmask] "w"(wmask),
[vbias] "w"(wbias)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21");
doutr0 = doutr0 + 2 * w_out;
}
#else
for (int i = 0; i < h_out; i++) {
din0_ptr = dr0;
din1_ptr = dr1;
din2_ptr = dr2;
doutr0_ptr = doutr0;
dr0 = dr2;
dr1 = dr0 + w_in;
dr2 = dr1 + w_in;
//! process bottom pad
if (i * 2 + 3 > h_in) {
switch (i * 2 + 3 - h_in) {
case 2:
din1_ptr = zero_ptr;
case 1:
din2_ptr = zero_ptr;
default:
break;
}
}
int cnt = tile_w;
unsigned int* mask_ptr = dmask;
asm volatile(INIT_S2 MID_COMPUTE_S2 MID_RESULT_S2_RELU RIGHT_COMPUTE_S2
RIGHT_RESULT_S2_RELU
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr), [din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr), [din2_ptr] "+r"(din2_ptr),
[outptr] "+r"(doutr0_ptr),
[cnt] "+r"(cnt),
[mask_ptr] "+r"(mask_ptr) [mask_ptr] "+r"(mask_ptr)
: [wr0] "w"(wr0), : [remain] "r"(cnt_remain),
[wr0] "w"(wr0),
[wr1] "w"(wr1), [wr1] "w"(wr1),
[wr2] "w"(wr2), [wr2] "w"(wr2),
[bias] "r"(bias_c), [bias] "r"(bias_c)
[out] "r"(out_buf)
: "cc", : "cc",
"memory", "memory",
"q3", "q3",
...@@ -1188,23 +1691,13 @@ void conv_depthwise_3x3s2p1_bias_s_relu(float* dout, ...@@ -1188,23 +1691,13 @@ void conv_depthwise_3x3s2p1_bias_s_relu(float* dout,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
doutr0 = doutr0 + w_out;
} }
#endif #endif
for (int w = 0; w < w_out; ++w) {
*dout_channel++ = out_buf[w];
}
hs += 2;
he += 2;
}
} }
} }
} }
void conv_depthwise_3x3s2p0_bias_no_relu(float* dout,
/**
* \brief depthwise convolution kernel 3x3, stride 2
*/
// w_in > 7
void conv_depthwise_3x3s2p0_bias_relu(float* dout,
const float* din, const float* din,
const float* weights, const float* weights,
const float* bias, const float* bias,
...@@ -1334,62 +1827,6 @@ void conv_depthwise_3x3s2p0_bias_relu(float* dout, ...@@ -1334,62 +1827,6 @@ void conv_depthwise_3x3s2p0_bias_relu(float* dout,
doutr1_ptr = write_ptr; doutr1_ptr = write_ptr;
} }
int cnt = tile_w; int cnt = tile_w;
if (flag_relu) {
asm volatile(
INIT_S2
"ld1 {v15.4s}, [%[inptr0]] \n"
"ld1 {v18.4s}, [%[inptr1]] \n"
"ld1 {v19.4s}, [%[inptr2]] \n"
"ld1 {v20.4s}, [%[inptr3]] \n"
"ld1 {v21.4s}, [%[inptr4]] \n"
"ext v10.16b, v0.16b, v15.16b, #4 \n" // v10 = {2,4,6,8}
MID_COMPUTE_S2 MID_RESULT_S2_RELU
"cmp %w[remain], #1 \n"
"blt 4f \n" RIGHT_COMPUTE_S2
RIGHT_RESULT_S2_RELU
"4: \n"
: [inptr0] "+r"(din0_ptr),
[inptr1] "+r"(din1_ptr),
[inptr2] "+r"(din2_ptr),
[inptr3] "+r"(din3_ptr),
[inptr4] "+r"(din4_ptr),
[outptr0] "+r"(doutr0_ptr),
[outptr1] "+r"(doutr1_ptr),
[cnt] "+r"(cnt)
: [vzero] "w"(vzero),
[w0] "w"(wr0),
[w1] "w"(wr1),
[w2] "w"(wr2),
[remain] "r"(cnt_remain),
[mask1] "w"(vmask_rp1),
[mask2] "w"(vmask_rp2),
[wmask] "w"(wmask),
[vbias] "w"(wbias)
: "cc",
"memory",
"v0",
"v1",
"v2",
"v3",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16",
"v17",
"v18",
"v19",
"v20",
"v21");
} else {
asm volatile( asm volatile(
INIT_S2 INIT_S2
"ld1 {v15.4s}, [%[inptr0]] \n" "ld1 {v15.4s}, [%[inptr0]] \n"
...@@ -1401,8 +1838,7 @@ void conv_depthwise_3x3s2p0_bias_relu(float* dout, ...@@ -1401,8 +1838,7 @@ void conv_depthwise_3x3s2p0_bias_relu(float* dout,
MID_COMPUTE_S2 MID_RESULT_S2 MID_COMPUTE_S2 MID_RESULT_S2
"cmp %w[remain], #1 \n" "cmp %w[remain], #1 \n"
"blt 4f \n" RIGHT_COMPUTE_S2 "blt 4f \n" RIGHT_COMPUTE_S2
RIGHT_RESULT_S2 RIGHT_RESULT_S2 "4: \n"
"4: \n"
: [inptr0] "+r"(din0_ptr), : [inptr0] "+r"(din0_ptr),
[inptr1] "+r"(din1_ptr), [inptr1] "+r"(din1_ptr),
[inptr2] "+r"(din2_ptr), [inptr2] "+r"(din2_ptr),
...@@ -1444,7 +1880,6 @@ void conv_depthwise_3x3s2p0_bias_relu(float* dout, ...@@ -1444,7 +1880,6 @@ void conv_depthwise_3x3s2p0_bias_relu(float* dout,
"v19", "v19",
"v20", "v20",
"v21"); "v21");
}
doutr0 = doutr0 + 2 * w_out; doutr0 = doutr0 + 2 * w_out;
} }
#else #else
...@@ -1472,36 +1907,6 @@ void conv_depthwise_3x3s2p0_bias_relu(float* dout, ...@@ -1472,36 +1907,6 @@ void conv_depthwise_3x3s2p0_bias_relu(float* dout,
} }
int cnt = tile_w; int cnt = tile_w;
unsigned int* mask_ptr = dmask; unsigned int* mask_ptr = dmask;
if (flag_relu) {
asm volatile(INIT_S2 MID_COMPUTE_S2 MID_RESULT_S2_RELU
RIGHT_COMPUTE_S2 RIGHT_RESULT_S2_RELU
: [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr),
[outptr] "+r"(doutr0_ptr),
[cnt] "+r"(cnt),
[mask_ptr] "+r"(mask_ptr)
: [remain] "r"(cnt_remain),
[wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[bias] "r"(bias_c)
: "cc",
"memory",
"q3",
"q4",
"q5",
"q6",
"q7",
"q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15");
} else {
asm volatile(INIT_S2 MID_COMPUTE_S2 MID_RESULT_S2 RIGHT_COMPUTE_S2 asm volatile(INIT_S2 MID_COMPUTE_S2 MID_RESULT_S2 RIGHT_COMPUTE_S2
RIGHT_RESULT_S2 RIGHT_RESULT_S2
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
...@@ -1530,14 +1935,12 @@ void conv_depthwise_3x3s2p0_bias_relu(float* dout, ...@@ -1530,14 +1935,12 @@ void conv_depthwise_3x3s2p0_bias_relu(float* dout,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
}
doutr0 = doutr0 + w_out; doutr0 = doutr0 + w_out;
} }
#endif #endif
} }
} }
} }
/** /**
* \brief depthwise convolution kernel 3x3, stride 2, width <= 4 * \brief depthwise convolution kernel 3x3, stride 2, width <= 4
*/ */
...@@ -1614,7 +2017,6 @@ void conv_depthwise_3x3s2p0_bias_s_relu(float* dout, ...@@ -1614,7 +2017,6 @@ void conv_depthwise_3x3s2p0_bias_s_relu(float* dout,
unsigned int* mask_ptr = dmask; unsigned int* mask_ptr = dmask;
#ifdef __aarch64__ #ifdef __aarch64__
if (flag_relu) {
asm volatile(COMPUTE_S_S2_P0 RESULT_S_S2_P0_RELU asm volatile(COMPUTE_S_S2_P0 RESULT_S_S2_P0_RELU
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr), [din1_ptr] "+r"(din1_ptr),
...@@ -1640,35 +2042,7 @@ void conv_depthwise_3x3s2p0_bias_s_relu(float* dout, ...@@ -1640,35 +2042,7 @@ void conv_depthwise_3x3s2p0_bias_s_relu(float* dout,
"v14", "v14",
"v15", "v15",
"v16"); "v16");
} else {
asm volatile(COMPUTE_S_S2_P0 RESULT_S_S2_P0
: [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr),
[mask_ptr] "+r"(mask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[bias] "w"(vbias),
[out] "r"(out_buf)
: "cc",
"memory",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16");
}
#else #else
if (flag_relu) {
asm volatile(COMPUTE_S_S2_P0 RESULT_S_S2_P0_RELU asm volatile(COMPUTE_S_S2_P0 RESULT_S_S2_P0_RELU
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr), [din1_ptr] "+r"(din1_ptr),
...@@ -1694,7 +2068,113 @@ void conv_depthwise_3x3s2p0_bias_s_relu(float* dout, ...@@ -1694,7 +2068,113 @@ void conv_depthwise_3x3s2p0_bias_s_relu(float* dout,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
} else { #endif
for (int w = 0; w < w_out; ++w) {
*dout_channel++ = out_buf[w];
}
}
}
}
}
void conv_depthwise_3x3s2p0_bias_s_no_relu(float* dout,
const float* din,
const float* weights,
const float* bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx) {
int right_pad_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7};
int out_pad_idx[4] = {0, 1, 2, 3};
float zeros[8] = {0.0f};
const float zero_ptr[4] = {0.f, 0.f, 0.f, 0.f};
uint32x4_t vmask_rp1 =
vcgtq_s32(vdupq_n_s32(w_in), vld1q_s32(right_pad_idx)); // 0 2 4 6
uint32x4_t vmask_rp2 =
vcgtq_s32(vdupq_n_s32(w_in), vld1q_s32(right_pad_idx + 4)); // 1 3 5 7
int size_in_channel = w_in * h_in;
int size_out_channel = w_out * h_out;
unsigned int dmask[8];
vst1q_u32(dmask, vmask_rp1);
vst1q_u32(dmask + 4, vmask_rp2);
for (int n = 0; n < num; ++n) {
const float* din_batch = din + n * ch_in * size_in_channel;
float* dout_batch = dout + n * ch_in * size_out_channel;
#pragma omp parallel for
for (int i = 0; i < ch_in; ++i) {
const float* din_channel = din_batch + i * size_in_channel;
float* dout_channel = dout_batch + i * size_out_channel;
const float* weight_ptr = weights + i * 9;
float32x4_t wr0 = vld1q_f32(weight_ptr);
float32x4_t wr1 = vld1q_f32(weight_ptr + 3);
float32x4_t wr2 = vld1q_f32(weight_ptr + 6);
float bias_c = 0.f;
if (flag_bias) {
bias_c = bias[i];
}
float32x4_t vbias = vdupq_n_f32(bias_c);
float out_buf[4];
const float* dr0 = din_channel;
const float* dr1 = dr0 + w_in;
const float* dr2 = dr1 + w_in;
for (int j = 0; j < h_out; j++) {
const float* din0_ptr = dr0;
const float* din1_ptr = dr1;
const float* din2_ptr = dr2;
if (j * 2 + 2 >= h_in) {
switch (j + 2 - h_in) {
case 1:
din1_ptr = zero_ptr;
case 0:
din2_ptr = zero_ptr;
default:
break;
}
}
dr0 = dr2;
dr1 = dr0 + w_in;
dr2 = dr1 + w_in;
unsigned int* mask_ptr = dmask;
#ifdef __aarch64__
asm volatile(COMPUTE_S_S2_P0 RESULT_S_S2_P0
: [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr),
[din2_ptr] "+r"(din2_ptr),
[mask_ptr] "+r"(mask_ptr)
: [wr0] "w"(wr0),
[wr1] "w"(wr1),
[wr2] "w"(wr2),
[bias] "w"(vbias),
[out] "r"(out_buf)
: "cc",
"memory",
"v4",
"v5",
"v6",
"v7",
"v8",
"v9",
"v10",
"v11",
"v12",
"v13",
"v14",
"v15",
"v16");
#else
asm volatile(COMPUTE_S_S2_P0 RESULT_S_S2_P0 asm volatile(COMPUTE_S_S2_P0 RESULT_S_S2_P0
: [din0_ptr] "+r"(din0_ptr), : [din0_ptr] "+r"(din0_ptr),
[din1_ptr] "+r"(din1_ptr), [din1_ptr] "+r"(din1_ptr),
...@@ -1720,7 +2200,6 @@ void conv_depthwise_3x3s2p0_bias_s_relu(float* dout, ...@@ -1720,7 +2200,6 @@ void conv_depthwise_3x3s2p0_bias_s_relu(float* dout,
"q13", "q13",
"q14", "q14",
"q15"); "q15");
}
#endif #endif
for (int w = 0; w < w_out; ++w) { for (int w = 0; w < w_out; ++w) {
*dout_channel++ = out_buf[w]; *dout_channel++ = out_buf[w];
......
lite/backends/arm/math/conv_depthwise.h
浏览文件 @ 9e38adc8
...@@ -323,6 +323,118 @@ void conv_depthwise_3x3s2p1_bias_s_relu(float* dout, ...@@ -323,6 +323,118 @@ void conv_depthwise_3x3s2p1_bias_s_relu(float* dout,
const int w_out, const int w_out,
ARMContext* ctx); ARMContext* ctx);
void conv_depthwise_3x3s1p0_bias_no_relu(float* dout,
const float* din,
const float* weights,
const float* bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx);
void conv_depthwise_3x3s1p0_bias_s_no_relu(float* dout,
const float* din,
const float* weights,
const float* bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx);
void conv_depthwise_3x3s1p1_bias_no_relu(float* dout,
const float* din,
const float* weights,
const float* bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx);
void conv_depthwise_3x3s1p1_bias_s_no_relu(float* dout,
const float* din,
const float* weights,
const float* bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx);
void conv_depthwise_3x3s2p0_bias_no_relu(float* dout,
const float* din,
const float* weights,
const float* bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx);
void conv_depthwise_3x3s2p0_bias_s_no_relu(float* dout,
const float* din,
const float* weights,
const float* bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx);
void conv_depthwise_3x3s2p1_bias_no_relu(float* dout,
const float* din,
const float* weights,
const float* bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx);
void conv_depthwise_3x3s2p1_bias_s_no_relu(float* dout,
const float* din,
const float* weights,
const float* bias,
bool flag_bias,
bool flag_relu,
const int num,
const int ch_in,
const int h_in,
const int w_in,
const int h_out,
const int w_out,
ARMContext* ctx);
} // namespace math } // namespace math
} // namespace arm } // namespace arm
} // namespace lite } // namespace lite
......
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