From 9c15846aeb65b92988cee4e63164792420ef1787 Mon Sep 17 00:00:00 2001
From: chonwhite <arthurbrown@163.com>
Date: Wed, 25 Dec 2019 12:16:17 +0800
Subject: [PATCH] attention works

---
 lite/backends/fpga/KD/debugger.hpp        | 2 +-
 lite/backends/fpga/KD/pes/conv_pe.hpp     | 1 +
 lite/core/mir/ssa_graph.cc                | 4 ++++
 lite/core/mir/type_target_cast_pass.cc    | 2 ++
 lite/core/optimizer.h                     | 2 ++
 lite/kernels/arm/fill_constant_compute.cc | 2 +-
 6 files changed, 11 insertions(+), 2 deletions(-)
 mode change 100644 => 100755 lite/core/mir/ssa_graph.cc

diff --git a/lite/backends/fpga/KD/debugger.hpp b/lite/backends/fpga/KD/debugger.hpp
index 5aa6511cdf..81ae57fc88 100755
--- a/lite/backends/fpga/KD/debugger.hpp
+++ b/lite/backends/fpga/KD/debugger.hpp
@@ -33,7 +33,7 @@ class Debugger {
 
   void registerOutput(std::string op_type, zynqmp::Tensor* tensor) {
     if (op_config[op_type]) {
-      tensor->saveToFile(op_type, true);
+      // tensor->saveToFile(op_type, true);
     }
   }
 
diff --git a/lite/backends/fpga/KD/pes/conv_pe.hpp b/lite/backends/fpga/KD/pes/conv_pe.hpp
index f274ccab0b..59cb0d5d5a 100755
--- a/lite/backends/fpga/KD/pes/conv_pe.hpp
+++ b/lite/backends/fpga/KD/pes/conv_pe.hpp
@@ -60,6 +60,7 @@ class ConvPE : public PE {
 
     if (param_.filter->shape().width() == 1 &&
         param_.filter->shape().height() == 1) {  // NOLINT
+      // use_cpu_ = true;
     }
     if (!use_cpu_) {  // NOLINT
       // param_.filter->releaseData();
diff --git a/lite/core/mir/ssa_graph.cc b/lite/core/mir/ssa_graph.cc
old mode 100644
new mode 100755
index 2b5b65ce59..0d4c642877
--- a/lite/core/mir/ssa_graph.cc
+++ b/lite/core/mir/ssa_graph.cc
@@ -140,10 +140,12 @@ void SSAGraph::Build(const Program &program,
         arg_node->AsArg(name, node_storage_.size() - 1);
         arg_update_node_map_[name] = arg_node;
       }
+      /*
       if (var_types.count(name) && !arg_node->arg()->type) {
         arg_node->arg()->type = LiteType::GetTensorTy(
             TARGET(kUnk), var_types[name], DATALAYOUT(kUnk));
       }
+      */
       if (is_weights(name)) arg_node->AsArg().is_weight = true;
       CHECK(arg_node->IsRoleSet());
       DirectedLink(arg_node, op_node);
@@ -153,10 +155,12 @@ void SSAGraph::Build(const Program &program,
       auto *arg_node = &node_storage_.back();
       arg_node->AsArg(name, node_storage_.size() - 1);
       arg_update_node_map_[name] = arg_node;
+      /*
       if (var_types.count(name) && !arg_node->arg()->type) {
         arg_node->arg()->type = LiteType::GetTensorTy(
             TARGET(kUnk), var_types[name], DATALAYOUT(kUnk));
       }
+      */
 
       if (is_weights(name)) arg_node->AsArg().is_weight = true;
       CHECK(arg_node->IsRoleSet());
diff --git a/lite/core/mir/type_target_cast_pass.cc b/lite/core/mir/type_target_cast_pass.cc
index 17a327f253..98e11298e9 100755
--- a/lite/core/mir/type_target_cast_pass.cc
+++ b/lite/core/mir/type_target_cast_pass.cc
@@ -119,8 +119,10 @@ void TypeTargetTransformPass::AddIoCopyInst(
     // to.target()
     // The precision and layout should be equal to from.precision(),
     // from.layout()
+    #ifndef LITE_WITH_FPGA
     io_copy_output_arg->AsArg().type =
         LiteType::GetTensorTy(to.target(), from.precision(), from.layout());
+    #endif
     auto* io_copy_inst = graph->NewInstructNode();
 
     bool in_persist = in->AsArg().is_weight || in->AsArg().is_persist;
diff --git a/lite/core/optimizer.h b/lite/core/optimizer.h
index 00e9e07749..26ea72cb25 100755
--- a/lite/core/optimizer.h
+++ b/lite/core/optimizer.h
@@ -107,7 +107,9 @@ class Optimizer {
 
            "runtime_context_assign_pass",
            "argument_type_display_pass",
+#ifndef LITE_WITH_FPGA
            "memory_optimize_pass",
+#endif
            "npu_subgraph_pass",
            "xpu_subgraph_pass"}};
       RunPasses(passes_local);
diff --git a/lite/kernels/arm/fill_constant_compute.cc b/lite/kernels/arm/fill_constant_compute.cc
index badd3f9028..4b6571fe1c 100755
--- a/lite/kernels/arm/fill_constant_compute.cc
+++ b/lite/kernels/arm/fill_constant_compute.cc
@@ -133,7 +133,7 @@ REGISTER_LITE_KERNEL(fill_constant,
                {LiteType::GetTensorTy(TARGET(kARM), PRECISION(kInt32))})
     .BindInput("ShapeTensorList",
                {LiteType::GetTensorTy(TARGET(kARM), PRECISION(kInt32))})
-    .BindOutput("Out", {LiteType::GetTensorTy(TARGET(kARM), PRECISION(kAny))})
+    .BindOutput("Out", {LiteType::GetTensorTy(TARGET(kARM))})
     .Finalize();
 
 REGISTER_LITE_KERNEL(fill_constant_batch_size_like,
-- 
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