Merge pull request #1533 from qnqinan/develop

clean interrupt signal at the beginning of bypass in FPGA track fixed#1531

src/fpga/V1/pe.cpp

@@ -13,6 +13,7 @@ See the License for the specific language governing permissions and
 limitations under the License. */
 
 #include "fpga/common/pe.h"
+#include "common/enforce.h"
 #include "common/types.h"
 #include "fpga/V1/filter.h"
 #include "fpga/V1/image.h"
@@ -296,6 +297,7 @@ int ComputeBasicConv(const struct ConvArgs &args) {
     g_fpgainfo.pe_data->pes[PE_IDX_CONV]->status = ERROR;
     ret = -EIO;
     DLOG << "Conv Wait Irq Timeout!";
+    PADDLE_MOBILE_ENFORCE(0, "Conv Wait Irq Timeout");
   }
   output_scale = reg_readq(REG_SCALE_PARAMETER);
   output_scale = (output_scale << 32) | (output_scale >> 32);
@@ -447,6 +449,7 @@ int ComputeFpgaPool(const struct PoolingArgs &args) {
     g_fpgainfo.pe_data->pes[PE_IDX_POOLING]->status = ERROR;
     ret = -EIO;
     DLOG << "Pooling Wait Irq Timeout!";
+    PADDLE_MOBILE_ENFORCE(0, "Pooling Wait Irq Timeout!");
   }
   DLOG << "after reg poll";
 
@@ -529,6 +532,7 @@ int ComputeFpgaEWAdd(const struct EWAddArgs &args) {
     g_fpgainfo.pe_data->pes[PE_IDX_EW]->status = ERROR;
     ret = -EIO;
     DLOG << "EW Wait Irq Timeout!";
+    PADDLE_MOBILE_ENFORCE(0, "EW Wait Irq Timeout!");
   }
 
   output_scale = reg_readq(REG_SCALE_PARAMETER);
@@ -561,6 +565,7 @@ int PerformBypass(const struct BypassArgs &args) {
        << "   out_scale_address:" << args.output.scale_address;
 #endif
 #ifdef PADDLE_MOBILE_ZU5
+  uint64_t bypass_interrupt = reg_readq(REG_INTERRUPT);
   uint64_t output_scale = 0;
   uint64_t timer_cnt = 0;
   uint64_t cmd = 0;
@@ -666,12 +671,12 @@ int PerformBypass(const struct BypassArgs &args) {
   reg_writeq(output_address_phy, REG_CONVERT_DST_ADDR);
   reg_writeq(datalen, REG_CONVERT_LENGTH);
   reg_writeq(cmd, REG_CONVERT_CMD);
-
   DLOG << "before reg poll";
   if (0 != fpga_regpoll(REG_INTERRUPT, INTERRUPT_BYPASS, PE_IRQ_TIMEOUT)) {
     g_fpgainfo.pe_data->pes[PE_IDX_BYPASS]->status = ERROR;
     ret = -EIO;
     DLOG << "BYPASS Wait Irq Timeout!";
+    PADDLE_MOBILE_ENFORCE(0, "BYPASS Wait Irq Timeout!");
   }
   DLOG << "after reg poll";
 
@@ -1052,6 +1057,7 @@ int ComputeDWConv(const struct DWconvArgs &args) {
     g_fpgainfo.pe_data->pes[PE_IDX_POOLING]->status = ERROR;
     ret = -EIO;
     DLOG << "Pooling Wait Irq Timeout!";
+    PADDLE_MOBILE_ENFORCE(0, "DWConv Wait Irq Timeout");
   }
   DLOG << "after reg poll";
 

src/fpga/common/driver.cpp

@@ -51,11 +51,7 @@ int open_memdevice() {
   return g_fpgainfo.fd_mem;
 }
 
-void pl_reset() {
-  // DLOG << "PL RESET";
-
-  usleep(100 * 1000);
-}
+void pl_reset() { usleep(100 * 1000); }
 
 void setup_pe(struct pe_data_s *pe_data, struct fpga_pe *pe,
               char const *type_name, int pe_idx) {
@@ -77,7 +73,7 @@ void pl_init() {
 
   pe_data = (struct pe_data_s *)malloc(sizeof(struct pe_data_s));
   if (pe_data == nullptr) {
-    DLOG << "pe_data malloc error!";
+    std::cout << "pe_data malloc error!" << std::endl;
     return;
   }
   memset(pe_data, 0, sizeof(struct pe_data_s));
@@ -165,7 +161,7 @@ uint64_t vaddr_to_paddr_driver(void *address) {
   if (iter != g_fpgainfo.fpga_vaddr2paddr_map.end()) {
     paddr = iter->second;
   } else {
-    DLOG << "Invalid pointer: " << address;
+    std::cout << "Invalid pointer: " << address << std::endl;
   }
 
   return paddr;
@@ -191,7 +187,7 @@ void *fpga_reg_free(void *ptr) {
     g_fpgainfo.fpga_addr2size_map.erase(iter);
     munmap(ptr, size);
   } else {
-    DLOG << "Invalid pointer" << ptr;
+    std::cout << "Invalid pointer" << ptr << std::endl;
   }
 }
 
@@ -205,9 +201,6 @@ void *fpga_malloc_driver(size_t size) {
   int i = 0;
   struct MemoryVM2PHYArgs args;
   struct MemoryCacheArgs args_c;
-
-  // memory_request(g_fpgainfo.memory_info, size, &phy_addr);
-
   ret = mmap64(nullptr, size, PROT_READ | PROT_WRITE, MAP_SHARED,
                g_fpgainfo.fd_mem, FPGA_MEM_PHY_ADDR);
   PADDLE_MOBILE_ENFORCE(ret != (void *)-1, "Should not be -1");
@@ -233,16 +226,12 @@ void fpga_free_driver(void *ptr) {
     size = iter->second;
     g_fpgainfo.fpga_addr2size_map.erase(iter);
     munmap(ptr, size);
-
-    // p_addr = vaddr_to_paddr_driver(ptr);
-    // pos = (p_addr - g_fpgainfo.memory_info->mem_start) / FPGA_PAGE_SIZE;
-
     auto iter = g_fpgainfo.fpga_vaddr2paddr_map.find(ptr);
     if (iter != g_fpgainfo.fpga_vaddr2paddr_map.end()) {
       g_fpgainfo.fpga_vaddr2paddr_map.erase(iter);
     }
   } else {
-    DLOG << "Invalid pointer" << ptr;
+    std::cout << "Invalid pointer" << ptr << std::endl;
   }
 }
 
@@ -295,10 +284,7 @@ int open_device_driver() {
 
   g_fpgainfo.FpgaRegVirAddr =
       (uint64_t *)fpga_reg_malloc(FPGA_REG_SIZE);  // NOLINT
-  // fpga_memory_add();
-
   pl_init();
-
   return ret;
 }
 
@@ -306,7 +292,6 @@ int close_device_driver() {
   pl_destroy();
   fpga_reg_free(g_fpgainfo.FpgaRegVirAddr);
   memory_release(g_fpgainfo.memory_info);
-
   return 0;
 }