diff --git a/src/common/types.cpp b/src/common/types.cpp
index 2f366eb9e5a10ea11e3153e6e32b18204c6dd9cd..b6387503856f438acd74b8d147da13a2b009f2a1 100644
--- a/src/common/types.cpp
+++ b/src/common/types.cpp
@@ -81,8 +81,8 @@ std::unordered_map<
         {G_OP_TYPE_FUSION_CONV_ADD_RELU, {{"Input"}, {"Out"}}},
         {G_OP_TYPE_IM2SEQUENCE, {{"X"}, {"Out"}}},
         {G_OP_TYPE_DROPOUT, {{"X"}, {"Out"}}},
-        {G_OP_TYPE_FUSION_CONV_ADD_BN, {{"Input"}, {"Out"}}},
-        {G_OP_TYPE_FUSION_POOL_BN, {{"X"}, {"Out"}}},
+        {G_OP_TYPE_FUSION_CONV_ADD_BN, {{"Input"}, {"Y"}}},
+        {G_OP_TYPE_FUSION_POOL_BN, {{"X"}, {"Y"}}},
         {G_OP_TYPE_FUSION_ELEMENTWISE_ADD_RELU, {{"X", "Y"}, {"Out"}}},
         {G_OP_TYPE_FUSION_FC_RELU, {{"X", "Y", "Z"}, {"Out"}}},
         {G_OP_TYPE_REGION, {{"X"}, {"Out"}}}};
diff --git a/src/operators/kernel/fpga/elementwise_add_relu_kernel.cpp b/src/operators/kernel/fpga/elementwise_add_relu_kernel.cpp
index d56929f1b12c1061a2cb08001b48c74da9214a27..fffd182bacacadfb3d0716eec6dc37e56d4b5069 100644
--- a/src/operators/kernel/fpga/elementwise_add_relu_kernel.cpp
+++ b/src/operators/kernel/fpga/elementwise_add_relu_kernel.cpp
@@ -29,25 +29,28 @@ bool ElementwiseAddReluKernel<FPGA, float>::Init(
   auto input_x_ptr = input_x->data<float>();
   auto input_y_ptr = input_y->data<float>();
   auto out_ptr = out->data<float>();
+
   fpga::EWAddArgs ewaddArgs;
   ewaddArgs.relu_enabled = relu_enabled;
   ewaddArgs.const0 = 1;
   ewaddArgs.const1 = 1;
   ewaddArgs.image0.address = (void *)input_x_ptr;
   ewaddArgs.image0.channels = input_x->dims()[1];
-  ewaddArgs.image0.scale_address = nullptr;  // ew has scale attribute??
+  ewaddArgs.image0.scale_address =
+      input_x->fpga_args().scale_pointer();  // ew has scale attribute??
   ewaddArgs.image0.height = input_x->dims()[2];
   ewaddArgs.image0.width = input_x->dims()[3];
   ewaddArgs.image0.pad_height = 1;
   ewaddArgs.image0.pad_width = 1;
   ewaddArgs.image1.address = (void *)input_y_ptr;
   ewaddArgs.image1.channels = input_y->dims()[1];
-  ewaddArgs.image1.scale_address = nullptr;  // ew has scale attribute??
+  ewaddArgs.image1.scale_address =
+      input_y->fpga_args().scale_pointer();  // ew has scale attribute??
   ewaddArgs.image1.height = input_y->dims()[2];
   ewaddArgs.image1.width = input_y->dims()[3];
   ewaddArgs.image1.pad_height = 1;
   ewaddArgs.image1.pad_width = 1;
-  ewaddArgs.output.scale_address = nullptr;
+  ewaddArgs.output.scale_address = out->fpga_args().scale_pointer();
   ewaddArgs.output.address = (void *)out_ptr;
   param->SetFpgaArgs(ewaddArgs);
   return true;
diff --git a/src/operators/kernel/fpga/fc_relu_kernel.cpp b/src/operators/kernel/fpga/fc_relu_kernel.cpp
index 85d68163d71e713963e4148e57468a7da8d3271f..61d94f9231459c8f945834b68899b3447eecc1aa 100644
--- a/src/operators/kernel/fpga/fc_relu_kernel.cpp
+++ b/src/operators/kernel/fpga/fc_relu_kernel.cpp
@@ -31,13 +31,22 @@ bool FusionFcReluKernel<FPGA, float>::Init(FusionFcReluParam *param) {
   Tensor *out = param->Out();
   auto out_ptr = out->mutable_data<float>();
 
+  PADDLE_MOBILE_ENFORCE(input_x->dims()[1] == input_z->dims()[0],
+                        "Image channel should be equal to bias number");
+  int channel = input_x->dims()[1];
+  float *bs_ptr = (float *)fpga::fpga_malloc(2 * channel * sizeof(float));
+  for (int i = 0; i < channel; i++) {
+    bs_ptr[i * 2] = 1;
+    bs_ptr[i * 2 + 1] = input_z_ptr[i];
+  }
+
   fpga::ConvArgs convArgs;
   convArgs.relu_enabled = relu_enabled;
   convArgs.bias_address = (void *)input_z_ptr;
   convArgs.filter_address = (void *)input_y_ptr;
   convArgs.filter_num = out->dims()[1];
   convArgs.group_num = 1;
-  convArgs.bn.enabled = bn_enabled;
+  convArgs.sb_address = (void *)bs_ptr;
   convArgs.kernel.stride_w = 1;
   convArgs.kernel.stride_h = 1;
   convArgs.kernel.height = input_x->dims()[2];
@@ -48,9 +57,11 @@ bool FusionFcReluKernel<FPGA, float>::Init(FusionFcReluParam *param) {
   convArgs.image.width = input_x->dims()[3];
   convArgs.image.pad_height = 1;
   convArgs.image.pad_width = 1;
-  convArgs.image.scale_address = nullptr;  // fc input has scale attribute??
+  convArgs.image.scale_address =
+      input_x->fpga_args().scale_pointer();  // fc input has scale attribute??
   convArgs.output.address = (void *)out_ptr;
-  convArgs.output.scale_address = nullptr;  // fc output has scale attribute??
+  convArgs.output.scale_address =
+      out->fpga_args().scale_pointer();  // fc output has scale attribute??
   param->SetFpgaArgs(convArgs);
 
   return true;
diff --git a/src/operators/kernel/fpga/fusion_fc_kernel.cpp b/src/operators/kernel/fpga/fusion_fc_kernel.cpp
index ecfb07f13cf801963a4d6bb98be65c08102bdf96..06939a242f6e579f833e0c83f49ab8d6afd751e6 100644
--- a/src/operators/kernel/fpga/fusion_fc_kernel.cpp
+++ b/src/operators/kernel/fpga/fusion_fc_kernel.cpp
@@ -31,13 +31,22 @@ bool FusionFcKernel<FPGA, float>::Init(FusionFcParam *param) {
   Tensor *out = param->Out();
   auto out_ptr = out->mutable_data<float>();
 
+  PADDLE_MOBILE_ENFORCE(input_x->dims()[1] == input_z->dims()[0],
+                        "Image channel should be equal to bias number");
+  int channel = input_x->dims()[1];
+  float *bs_ptr = (float *)fpga::fpga_malloc(2 * channel * sizeof(float));
+  for (int i = 0; i < channel; i++) {
+    bs_ptr[i * 2] = 1;
+    bs_ptr[i * 2 + 1] = input_z_ptr[i];
+  }
+
   fpga::ConvArgs convArgs;
   convArgs.relu_enabled = relu_enabled;
   convArgs.bias_address = (void *)input_z_ptr;
   convArgs.filter_address = (void *)input_y_ptr;
   convArgs.filter_num = out->dims()[1];
   convArgs.group_num = 1;
-  convArgs.bn.enabled = bn_enabled;
+  convArgs.sb_address = (void *)bs_ptr;
   convArgs.kernel.stride_w = 1;
   convArgs.kernel.stride_h = 1;
   convArgs.kernel.height = input_x->dims()[2];
@@ -48,9 +57,11 @@ bool FusionFcKernel<FPGA, float>::Init(FusionFcParam *param) {
   convArgs.image.width = input_x->dims()[3];
   convArgs.image.pad_height = 1;
   convArgs.image.pad_width = 1;
-  convArgs.image.scale_address = nullptr;  // fc input has scale attribute??
+  convArgs.image.scale_address =
+      input_x->fpga_args().scale_pointer();  // fc input has scale attribute??
   convArgs.output.address = (void *)out_ptr;
-  convArgs.output.scale_address = nullptr;  // fc output has scale attribute??
+  convArgs.output.scale_address =
+      out->fpga_args().scale_pointer();  // fc output has scale attribute??
   param->SetFpgaArgs(convArgs);
   return true;
 }
diff --git a/src/operators/kernel/fpga/pool_kernel.cpp b/src/operators/kernel/fpga/pool_kernel.cpp
index 9a4988b7003e2663b35f62f27158bdb94c14e48a..287f849e2df0ed0976413e88b0ea8fb7c8d838aa 100644
--- a/src/operators/kernel/fpga/pool_kernel.cpp
+++ b/src/operators/kernel/fpga/pool_kernel.cpp
@@ -29,6 +29,7 @@ bool PoolKernel<FPGA, float>::Init(PoolParam *param) {
   vector<int> ksize = param->Ksize();
   vector<int> strides = param->Strides();
   vector<int> paddings = param->Paddings();
+
   fpga::PoolingArgs poolArgs;
   poolArgs.image.address = (void *)input_ptr;
   poolArgs.image.channels = input->dims()[1];