From 43e040dc4ef2ea0dea6976b2b62a71459e1fa0a6 Mon Sep 17 00:00:00 2001
From: jameswu2014 <545426914@qq.com>
Date: Thu, 16 May 2019 09:58:05 +0800
Subject: [PATCH] V1-dwconv  relu bug for FPGA track (#1624)

* V2-conv-hellocase pass & V1 verify-pass

* V1 paralvl equal to 2

* softmax channel =2 bug

* softmaxbug update2

* io update2

* V1-dwconv relu bug
---
 src/fpga/V1/pe.cpp | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/fpga/V1/pe.cpp b/src/fpga/V1/pe.cpp
index 19bbcd22d3..fef971a348 100644
--- a/src/fpga/V1/pe.cpp
+++ b/src/fpga/V1/pe.cpp
@@ -1000,14 +1000,34 @@ int ComputeDWConv(const struct DWconvArgs &args) {
   uint64_t image_padleft_skipwindow =
       (image_skip_window << 32) | image_pad_left;
 
+  uint64_t reg_ActivationArgs = 0;
+  // active function:{none,leakeyrelu,sigmoid,tanh}
+  ActivationArgs active_args;
+  // active_args.activation_type = LEAKYRELU;
+
+  active_args.activation_type = args.output.activation.activation_type;
+
+  active_args.leaky_relu_negative_slope =
+      args.output.activation.leaky_relu_negative_slope;
+
+  reg_ActivationArgs = (uint64_t(active_args.activation_type) << 32) |
+                       active_args.leaky_relu_negative_slope;
+
+  DLOG << "   activation_type:" << active_args.activation_type
+       << "   leaky_relu_negative_slope:"
+       << active_args.leaky_relu_negative_slope;
+  DLOG << "   reg_ActivationArgs:" << reg_ActivationArgs;
+
   pthread_mutex_lock(&g_fpgainfo.pe_data->mutex);
   if (ERROR == g_fpgainfo.pe_data->pes[PE_IDX_POOLING]->status) {
     ret = -EIO;
-    DLOG << "Conv Status Error!";
+    DLOG << "DWConv Status Error!";
     pthread_mutex_unlock(&g_fpgainfo.pe_data->mutex);
     return ret;
   }
 
+  reg_writeq(reg_ActivationArgs,
+             REG_ACTIVATION_MODE_AND_LEAKY_RELU_FACTOR);  // active functoion
   /*restart scale*/
   reg_writeq(output_scale, REG_SCALE_PARAMETER);
 
-- 
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