diff --git a/lite/backends/fpga/KD/debugger.hpp b/lite/backends/fpga/KD/debugger.hpp
index 81ae57fc88b25dd907c21efab7f79dfe7e524d98..9b1189c407d6d601bb3e5ba8172b1455f04710fd 100755
--- a/lite/backends/fpga/KD/debugger.hpp
+++ b/lite/backends/fpga/KD/debugger.hpp
@@ -33,7 +33,7 @@ class Debugger {
 
   void registerOutput(std::string op_type, zynqmp::Tensor* tensor) {
     if (op_config[op_type]) {
-      // tensor->saveToFile(op_type, true);
+      tensor->saveToFile(op_type, true);
     }
   }
 
@@ -43,6 +43,8 @@ class Debugger {
     op_config["concat"] = true;
     op_config["pooling"] = true;
     op_config["conv"] = true;
+    op_config["dwconv"] = true;
+    op_config["ew_add"] = true;
     op_config["crop"] = true;
     op_config["feed"] = true;
     op_config["mul"] = true;
diff --git a/lite/core/mir/fusion/quant_dequant_op_fuser.cc b/lite/core/mir/fusion/quant_dequant_op_fuser.cc
old mode 100644
new mode 100755
index 9c5bb24d88f5ee53cc8405adf022e9bc34e85132..93753a0123dbbd875113f393766e559481007d99
--- a/lite/core/mir/fusion/quant_dequant_op_fuser.cc
+++ b/lite/core/mir/fusion/quant_dequant_op_fuser.cc
@@ -214,7 +214,9 @@ void DequantOpFuser::InsertNewNode(SSAGraph* graph,
   for (int i = 0; i < weight_scale_size; i++) {
     weight_scale.push_back(whole_weight_scale);
   }
+  #ifndef LITE_WITH_FPGA
   op_desc.SetAttr("enable_int8", true);
+  #endif
   if (quantized_op->stmt()->op_info()->HasAttr("input_scale")) {
     op_desc.SetAttr("input_scale", input_scale);
   }
diff --git a/lite/core/mir/static_kernel_pick_pass.cc b/lite/core/mir/static_kernel_pick_pass.cc
old mode 100644
new mode 100755
diff --git a/lite/kernels/fpga/conv_compute.cc b/lite/kernels/fpga/conv_compute.cc
index a5a7c3b92f8ce01dacfc0518d0763cdb642bd838..66b3b51d38fe0316490017231a2840ec97ff5b15 100755
--- a/lite/kernels/fpga/conv_compute.cc
+++ b/lite/kernels/fpga/conv_compute.cc
@@ -76,6 +76,10 @@ void ConvCompute::Run() {
   if (param.x->ZynqTensor()->shape().channel() != 1 &&
       param.groups == param.x->ZynqTensor()->shape().channel()) {
     dw_conv_pe_.dispatch();
+#ifdef FPGA_PRINT_TENSOR
+    zynqmp::DepthwiseConvParam& dwconv_param = dw_conv_pe_.param();
+    Debugger::get_instance().registerOutput("dwconv", dwconv_param.output);
+#endif
   } else {
     conv_pe_.dispatch();
 #ifdef FPGA_PRINT_TENSOR
@@ -103,3 +107,17 @@ REGISTER_LITE_KERNEL(
                                        PRECISION(kFP16),
                                        DATALAYOUT(kNHWC))})
     .Finalize();
+
+REGISTER_LITE_KERNEL(
+    depthwise_conv2d, kFPGA, kFP16, kNHWC, paddle::lite::kernels::fpga::ConvCompute, def)
+    .BindInput("Input",
+               {LiteType::GetTensorTy(TARGET(kFPGA),
+                                      PRECISION(kFP16),
+                                      DATALAYOUT(kNHWC))})
+    .BindInput("Bias", {LiteType::GetTensorTy(TARGET(kARM))})
+    .BindInput("Filter", {LiteType::GetTensorTy(TARGET(kARM))})
+    .BindOutput("Output",
+                {LiteType::GetTensorTy(TARGET(kFPGA),
+                                       PRECISION(kFP16),
+                                       DATALAYOUT(kNHWC))})
+    .Finalize();
diff --git a/lite/operators/concat_op.cc b/lite/operators/concat_op.cc
old mode 100644
new mode 100755
diff --git a/lite/operators/conv_op.cc b/lite/operators/conv_op.cc
old mode 100644
new mode 100755