diff --git a/src/fpga/api/fpga_api.h b/src/fpga/api/fpga_api.h
index 2dfc285af4506c055f6780d7b3d393433c0904a8..947544c745b4c783175f6b129a9cf6f23007dd7e 100644
--- a/src/fpga/api/fpga_api.h
+++ b/src/fpga/api/fpga_api.h
@@ -14,6 +14,7 @@ limitations under the License. */
 
 #pragma once
 
+#include <stdint.h>
 #include <cstddef>
 #include <iostream>
 #include <limits>
@@ -28,22 +29,22 @@ namespace api {
 int open_device();
 int close_device();
 
-void *fpga_malloc(size_t size);
-void fpga_free(void *ptr);
-void fpga_copy(void *dst, const void *src, size_t num);
+void* fpga_malloc(size_t size);
+void fpga_free(void* ptr);
+void fpga_copy(void* dst, const void* src, size_t num);
 
 struct FpgaVersionArgs {
-  void *buf;
+  void* buf;
 };
 
 struct MemoryToPhysicalArgs {
-  const void *src;
+  const void* src;
   uint64_t physical;
 };
 
 struct MemoryCopyArgs {
-  void *src;
-  void *dst;
+  void* src;
+  void* dst;
   size_t size;
 };
 
@@ -51,33 +52,68 @@ struct FpgaQuantArgs {
   float scale;
 };
 
-struct FpgaBNArgs {};
+struct FpgaBNArgs {
+  bool enabled = false;
+  void* bias_addr;
+  void* scale_addr;
+};
+
+struct FpgaKernelArgs {
+  uint32_t width;
+  uint32_t height;
+  uint32_t stride_h;
+  uint32_t stride_w;
+}
+
+struct FpgaImageArgs {
+  uint32_t width;
+  uint32_t height;
+  uint32_t channels;
+  uint32_t pad_h;
+  uint32_t pad_w;
+}
 
 struct FpgaConvArgs {
-  bool enable_BN = false;
-  bool enable_Relu = false;
-  struct FpgaBNParam bn_parm;
+  bool relu_enabled;
+  struct FpgaBNArgs BNargs;
+  void* image_addr;
+  void* filter_addr;
+  void* bias_addr;
+  void* output_addr;
+  float quant_scale;
+  struct FpgaImageArgs image;
+  uint32_t filter_num;
+  uint32_t group_num;
+
+  struct FpgaKernelArgs kernel;
 };
 
 struct FpgaPoolArgs {
-  bool enable_BN = false;
-  struct FpgaBNParam bn_parm;
+  void* image_addr;
+  void* output_addr;
+  struct FpgaImageArgs image;
+  struct FpgaKernelArgs kernel;
 };
 
-struct FpgaEWAddArgs {  // only support X + Y
-  bool enable_Relu = false;
+struct FpgaEWAddArgs {
+  bool relu_enabled;
+  void* image0_addr;
+  void* image1_addr;
+  void* result_addr;
+  uint32_t const0;
+  uint32_t const1;
+  uint32_t data_len;  // aligned element count
 };
 
-int ComputeFpgaConv(struct FpgaConvArgs);
-int ComputeFpgaPool(struct FpgaPoolArgs);
-int ComputeFpgaEWAdd(struct FpgaEWAddArgs);
+int ComputeFpgaConv(struct FpgaConvArgs args);
+int ComputeFpgaPool(struct FpgaPoolArgs args);
+int ComputeFpgaEWAdd(struct FpgaEWAddArgs args);
 
-#define IOCTL_FPGA_MAGIC 'FPGA'
+#define IOCTL_FPGA_MAGIC 'CNN'
 #define IOCTL_VERSION _IOW(IOCTL_FPGA_MAGIC, 1, struct FpgaVersionArgs)
 #define IOCTL_GET_QUANT _IOW(IOCTL_FPGA_MAGIC, 2, struct FpgaQuantArgs)
-#define IOCTL_SET_QUANT _IOW(IOCTL_FPGA_MAGIC, 3, struct FpgaArgs)
+#define IOCTL_SET_QUANT _IOW(IOCTL_FPGA_MAGIC, 3, struct FpgaQuantArgs)
 #define IOCTL_MEM_COPY _IOW(IOCTL_FPGA_MAGIC, 11, struct MemoryCopyArgs)
-#define IOCTL_MEM_TOPHY _IOW(IOCTL_FPGA_MAGIC, 12, struct MemoryToPhysicalArgs)
 #define IOCTL_CONFIG_CONV _IOW(IOCTL_FPGA_MAGIC, 21, struct FpgaConvArgs)
 #define IOCTL_CONFIG_POOLING _IOW(IOCTL_FPGA_MAGIC, 22, struct FpgaPoolArgs)
 #define IOCTL_CONFIG_EW _IOW(IOCTL_FPGA_MAGIC, 23, struct FpgaEWAddArgs)