test=develop

lite/backends/arm/math/conv3x3s1p01_depthwise_fp32_relu.cc

@@ -2326,7 +2326,8 @@ void conv_depthwise_3x3s1p0_bias_no_relu(float *dout,
         int cnt = tile_w;
         unsigned int *rmask_ptr = rmask;
         unsigned int *vmask_ptr = vmask;
-        asm volatile(INIT_S1
+        asm volatile(
+            INIT_S1
             "sub %[din0_ptr], #8 @ 0pad + 2 float data overlap\n"
             "sub %[din1_ptr], #8 @ 0pad + 2 float data overlap\n"
             "sub %[din2_ptr], #8 @ 0pad + 2 float data overlap\n"
@@ -2609,16 +2610,17 @@ void conv_depthwise_3x3s1p0_bias_relu(float *dout,
         int cnt = tile_w;
         unsigned int *rmask_ptr = rmask;
         unsigned int *vmask_ptr = vmask;
-        asm volatile(
-            INIT_S1
+        asm volatile(INIT_S1
                      "sub %[din0_ptr], #8 @ 0pad + 2 float data overlap\n"
                      "sub %[din1_ptr], #8 @ 0pad + 2 float data overlap\n"
                      "sub %[din2_ptr], #8 @ 0pad + 2 float data overlap\n"
                      "sub %[din3_ptr], #8 @ 0pad + 2 float data overlap\n"
                      "vext.32  q6, q8, q9, #1     @ 0012\n"
-            "vext.32  q7, q8, q9, #2     @ 1234\n" MID_COMPUTE_S1 MID_RESULT_S1_RELU
+                     "vext.32  q7, q8, q9, #2     @ 1234\n" MID_COMPUTE_S1
+                     MID_RESULT_S1_RELU
                      "cmp  %[remain], #1             \n"
-            "blt 0f                         \n" RIGHT_COMPUTE_S1 RIGHT_RESULT_S1_RELU
+                     "blt 0f                         \n" RIGHT_COMPUTE_S1
+                         RIGHT_RESULT_S1_RELU
                      "0:                         \n"
                      : [dout_ptr1] "+r"(doutr0),
                        [dout_ptr2] "+r"(doutr1),