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体验新版 GitCode,发现更多精彩内容 >>
提交
f3e0de60
编写于
6月 04, 2003
作者:
W
wdenk
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
* Patch by Denis Peter, 04 June 2003:
add support for the MIP405T board
上级
682011ff
变更
12
显示空白变更内容
内联
并排
Showing
12 changed file
with
275 addition
and
96 deletion
+275
-96
CHANGELOG
CHANGELOG
+3
-0
MAKEALL
MAKEALL
+3
-3
Makefile
Makefile
+5
-0
board/mpl/common/common_util.c
board/mpl/common/common_util.c
+20
-2
board/mpl/common/pci_parts.h
board/mpl/common/pci_parts.h
+6
-0
board/mpl/mip405/init.S
board/mpl/mip405/init.S
+48
-2
board/mpl/mip405/mip405.c
board/mpl/mip405/mip405.c
+133
-76
board/mpl/mip405/u-boot.lds
board/mpl/mip405/u-boot.lds
+4
-0
cpu/ppc4xx/405gp_pci.c
cpu/ppc4xx/405gp_pci.c
+3
-3
cpu/ppc4xx/resetvec.S
cpu/ppc4xx/resetvec.S
+5
-2
include/configs/MIP405.h
include/configs/MIP405.h
+43
-7
include/configs/PIP405.h
include/configs/PIP405.h
+2
-1
未找到文件。
CHANGELOG
浏览文件 @
f3e0de60
...
...
@@ -2,6 +2,9 @@
Changes since U-Boot 0.3.1:
======================================================================
* Patch by Denis Peter, 04 June 2003:
add support for the MIP405T board
* Patches by Udi Finkelstein, 2 June 2003:
- Added support for custom keyboards, initialized by defining a
board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
...
...
MAKEALL
浏览文件 @
f3e0de60
...
...
@@ -48,9 +48,9 @@ LIST_4xx=" \
CANBT CPCI405 CPCI4052 CPCI405AB
\
CPCI440 CPCIISER4 CRAYL1 DASA_SIM
\
DU405 EBONY ERIC MIP405
\
M
L2 OCRTC ORSG PCI405
\
PIP405 PMC405 W7OLMC W7OLMG
\
WALNUT405
\
M
IP405T ML2 OCRTC ORSG
\
PCI405 PIP405 PMC405 W7OLMC
\
W7OLMG
WALNUT405
\
"
#########################################################################
...
...
Makefile
浏览文件 @
f3e0de60
...
...
@@ -449,6 +449,11 @@ ERIC_config:unconfig
MIP405_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx mip405 mpl
MIP405T_config
:
unconfig
@
echo
"#define CONFIG_MIP405T"
>
include/config.h
@
echo
"Enable subset config for MIP405T"
@
./mkconfig
-a
MIP405 ppc ppc4xx mip405 mpl
ML2_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx ml2
...
...
board/mpl/common/common_util.c
浏览文件 @
f3e0de60
...
...
@@ -59,6 +59,7 @@ int mpl_prg(unsigned long src,unsigned long size)
flash_info_t
*
info
;
int
i
,
rc
;
#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
char
*
copystr
=
(
char
*
)
src
;
unsigned
long
*
magic
=
(
unsigned
long
*
)
src
;
#endif
...
...
@@ -69,7 +70,24 @@ int mpl_prg(unsigned long src,unsigned long size)
printf
(
"Bad Magic number
\n
"
);
return
-
1
;
}
/* some more checks before we delete the Flash... */
/* Checking the ISO_STRING prevents to program a
* wrong Firmware Image into the flash.
*/
i
=
4
;
/* skip Magic number */
while
(
1
)
{
if
(
strncmp
(
&
copystr
[
i
],
"MEV-"
,
4
)
==
0
)
break
;
if
(
i
++>=
0x100
)
{
printf
(
"Firmware Image for unknown Target
\n
"
);
return
-
1
;
}
}
/* we have the ISO STRING, check */
if
(
strncmp
(
&
copystr
[
i
],
CONFIG_ISO_STRING
,
sizeof
(
CONFIG_ISO_STRING
)
-
1
)
!=
0
)
{
printf
(
"Wrong Firmware Image: %s
\n
"
,
&
copystr
[
i
]);
return
-
1
;
}
start
=
0
-
size
;
for
(
i
=
info
->
sector_count
-
1
;
i
>
0
;
i
--
)
{
...
...
board/mpl/common/pci_parts.h
浏览文件 @
f3e0de60
...
...
@@ -108,17 +108,23 @@ static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
/* PIIX4 IDE Controller Function 1 */
static
struct
pci_pip405_config_entry
piix4_ide_cntrl_f1
[]
=
{
{
PCI_COMMAND
,
0x0001
,
2
},
/* enable IO access */
#if !defined(CONFIG_MIP405T)
{
PCI_CFG_PIIX4_IDETIM
,
0x80008000
,
4
},
/* enable Both IDE channels */
#else
{
PCI_CFG_PIIX4_IDETIM
,
0x80000000
,
4
},
/* enable IDE channel0 */
#endif
{
}
/* end of device table */
};
/* PIIX4 USB Controller Function 2 */
static
struct
pci_pip405_config_entry
piix4_usb_cntrl_f2
[]
=
{
#if !defined(CONFIG_MIP405T)
{
PCI_INTERRUPT_LINE
,
31
,
1
},
/* Int vector = 31 */
{
PCI_BASE_ADDRESS_4
,
0x0000E001
,
4
},
/* Set IO Address to 0xe000 to 0xe01F */
{
PCI_LATENCY_TIMER
,
0x80
,
1
},
/* Latency Timer 0x80 */
{
0xC0
,
0x2000
,
2
},
/* Legacy support */
{
PCI_COMMAND
,
0x0005
,
2
},
/* enable IO access and Master */
#endif
{
}
/* end of device table */
};
...
...
board/mpl/mip405/init.S
浏览文件 @
f3e0de60
...
...
@@ -53,6 +53,10 @@
.
globl
ext_bus_cntlr_init
ext_bus_cntlr_init
:
mflr
r4
/*
save
link
register
*/
mfdcr
r3
,
strap
/*
get
strapping
reg
*/
andi
.
r0
,
r3
,
PSR_ROM_LOC
/*
mask
out
irrelevant
bits
*/
bnelr
/*
jump
back
if
PCI
boot
*/
bl
..
getAddr
..
getAddr
:
mflr
r3
/*
get
address
of
..
getAddr
*/
...
...
@@ -200,3 +204,45 @@ sdram_init:
blr
#if defined(CONFIG_BOOT_PCI)
.
section
.
bootpg
,
"ax"
.
globl
_start_pci
/*******************************************
*/
_start_pci
:
/
*
first
handle
errata
#
68
/
PCI_18
*/
iccci
r0
,
r0
/*
invalidate
I
-
cache
*/
lis
r31
,
0
mticcr
r31
/*
ICCR
=
0
(
all
uncachable
)
*/
isync
mfccr0
r28
/*
set
CCR0
[
24
]
=
1
*/
ori
r28
,
r28
,
0x0080
mtccr0
r28
/
*
setup
PMM0MA
(
0xEF400004
)
and
PMM0PCIHA
(
0xEF40000C
)
*/
lis
r28
,
0xEF40
addi
r28
,
r28
,
0x0004
stw
r31
,
0x0C
(
r28
)
/*
clear
PMM0PCIHA
*/
lis
r29
,
0xFFF8
/*
open
512
kByte
*/
addi
r29
,
r29
,
0x0001
/*
and
enable
this
region
*/
stwbrx
r29
,
r0
,
r28
/*
write
PMM0MA
*/
lis
r28
,
0xEEC0
/*
address
of
PCIC0_CFGADDR
*/
addi
r29
,
r28
,
4
/*
add
4
to
r29
->
PCIC0_CFGDATA
*/
lis
r31
,
0x8000
/*
set
en
bit
bus
0
*/
ori
r31
,
r31
,
0x304C
/*
device
6
func
0
reg
4
C
(
XBCS
register
)
*/
stwbrx
r31
,
r0
,
r28
/*
write
it
*/
lwbrx
r31
,
r0
,
r29
/*
load
XBCS
register
*/
oris
r31
,
r31
,
0x02C4
/*
clear
BIOSCS
WPE
,
set
lower
,
extended
and
1
M
extended
BIOS
enable
*/
stwbrx
r31
,
r0
,
r29
/*
write
back
XBCS
register
*/
nop
nop
b
_start
/*
normal
start
*/
#endif
board/mpl/mip405/mip405.c
浏览文件 @
f3e0de60
...
...
@@ -73,7 +73,7 @@ extern block_dev_desc_t * scsi_get_dev(int dev);
extern
block_dev_desc_t
*
ide_get_dev
(
int
dev
);
#undef SDRAM_DEBUG
#define ENABLE_ECC
/* for ecc boards */
#define FALSE 0
#define TRUE 1
...
...
@@ -108,7 +108,27 @@ typedef struct {
unsigned
char
sz
;
/* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
unsigned
char
ecc
;
/* if true, ecc is enabled */
}
sdram_t
;
#if defined(CONFIG_MIP405T)
const
sdram_t
sdram_table
[]
=
{
{
0x01
,
/* MIP405T Rev A, 64MByte -1 Board */
3
,
/* Case Latenty = 3 */
3
,
/* trp 20ns / 7.5 ns datain[27] */
3
,
/* trcd 20ns /7.5 ns (datain[29]) */
6
,
/* tras 44ns /7.5 ns (datain[30]) */
4
,
/* tcpt 44 - 20ns = 24ns */
3
,
/* Address Mode = 3 (13x9x4) */
4
,
/* size value (64MByte) */
0
},
/* ECC disabled */
{
0xff
,
/* terminator */
0xff
,
0xff
,
0xff
,
0xff
,
0xff
,
0xff
,
0xff
}
};
#else
const
sdram_t
sdram_table
[]
=
{
{
0x0f
,
/* Rev A, 128MByte -1 Board */
3
,
/* Case Latenty = 3 */
...
...
@@ -155,7 +175,7 @@ const sdram_t sdram_table[] = {
0xff
,
0xff
}
};
#endif
/*CONFIG_MIP405T */
void
SDRAM_err
(
const
char
*
s
)
{
#ifndef SDRAM_DEBUG
...
...
@@ -222,17 +242,54 @@ int init_sdram (void)
tctp_clocks
;
unsigned
char
cal_val
;
unsigned
char
bc
;
unsigned
long
pbcr
,
sdram_tim
,
sdram_bank
;
unsigned
long
*
p
;
unsigned
long
sdram_tim
,
sdram_bank
;
i2c_init
(
CFG_I2C_SPEED
,
CFG_I2C_SLAVE
);
/*i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);*/
(
void
)
get_clocks
();
gd
->
baudrate
=
9600
;
serial_init
();
/* set up the pld */
mtdcr
(
ebccfga
,
pb7ap
);
mtdcr
(
ebccfgd
,
PLD_AP
);
mtdcr
(
ebccfga
,
pb7cr
);
mtdcr
(
ebccfgd
,
PLD_CR
);
/* THIS IS OBSOLETE */
/* set up the board rev reg*/
mtdcr
(
ebccfga
,
pb5ap
);
mtdcr
(
ebccfgd
,
BOARD_AP
);
mtdcr
(
ebccfga
,
pb5cr
);
mtdcr
(
ebccfgd
,
BOARD_CR
);
#ifdef SDRAM_DEBUG
/* get all informations from PLD */
serial_puts
(
"
\n
PLD Part 0x"
);
bc
=
in8
(
PLD_PART_REG
);
write_hex
(
bc
);
serial_puts
(
"
\n
PLD Vers 0x"
);
bc
=
in8
(
PLD_VERS_REG
);
write_hex
(
bc
);
serial_puts
(
"
\n
Board Rev 0x"
);
bc
=
in8
(
PLD_BOARD_CFG_REG
);
write_hex
(
bc
);
serial_puts
(
"
\n
"
);
#endif
/* check board */
bc
=
in8
(
PLD_PART_REG
);
#if defined(CONFIG_MIP405T)
if
((
bc
&
0x80
)
==
0
)
SDRAM_err
(
"U-Boot configured for a MIP405T not for a MIP405!!!
\n
"
);
#else
if
((
bc
&
0x80
)
==
0x80
)
SDRAM_err
(
"U-Boot configured for a MIP405 not for a MIP405T!!!
\n
"
);
#endif
#if !defined(CONFIG_MIP405T)
/* since the ECC initialisation needs some time,
* we show that we're alive
*/
serial_puts
(
"
\n
Initializing SDRAM, Please stand by"
);
/* set-up the chipselect machine */
mtdcr
(
ebccfga
,
pb0cr
);
/* get cs0 config reg */
pbcr
=
mfdcr
(
ebccfgd
);
if
((
pbcr
&
0x00002000
)
==
0
)
{
tmp
=
mfdcr
(
ebccfgd
);
if
((
tmp
&
0x00002000
)
==
0
)
{
/* MPS Boot, set up the flash */
mtdcr
(
ebccfga
,
pb1ap
);
mtdcr
(
ebccfgd
,
FLASH_AP
);
...
...
@@ -254,30 +311,8 @@ int init_sdram (void)
mtdcr
(
ebccfgd
,
UART1_AP
);
mtdcr
(
ebccfga
,
pb3cr
);
mtdcr
(
ebccfgd
,
UART1_CR
);
/* set up the pld */
mtdcr
(
ebccfga
,
pb7ap
);
mtdcr
(
ebccfgd
,
PLD_AP
);
mtdcr
(
ebccfga
,
pb7cr
);
mtdcr
(
ebccfgd
,
PLD_CR
);
/* set up the board rev reg */
mtdcr
(
ebccfga
,
pb5ap
);
mtdcr
(
ebccfgd
,
BOARD_AP
);
mtdcr
(
ebccfga
,
pb5cr
);
mtdcr
(
ebccfgd
,
BOARD_CR
);
#ifdef SDRAM_DEBUG
out8
(
PER_BOARD_ADDR
,
0
);
bc
=
in8
(
PER_BOARD_ADDR
);
serial_puts
(
"
\n
Board Rev: "
);
write_hex
(
bc
);
serial_puts
(
" (PLD="
);
bc
=
in8
(
PLD_BOARD_CFG_REG
);
write_hex
(
bc
);
serial_puts
(
")
\n
"
);
#endif
bc
=
get_board_revcfg
(
);
bc
=
in8
(
PLD_BOARD_CFG_REG
);
#ifdef SDRAM_DEBUG
serial_puts
(
"
\n
start SDRAM Setup
\n
"
);
serial_puts
(
"
\n
Board Rev: "
);
...
...
@@ -367,9 +402,10 @@ int init_sdram (void)
mtdcr
(
memcfga
,
mem_rtr
);
mtdcr
(
memcfgd
,
tmp
);
/* enable ECC if used */
#if
1
#if
defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
if
(
sdram_table
[
i
].
ecc
)
{
/* disable checking for all banks */
unsigned
long
*
p
;
#ifdef SDRAM_DEBUG
serial_puts
(
"disable ECC.. "
);
#endif
...
...
@@ -398,8 +434,6 @@ int init_sdram (void)
*
p
++
=
0L
;
if
(
!
((
unsigned
long
)
p
%
0x00800000
))
/* every 8MByte */
serial_puts
(
"."
);
}
/* enable bank 0 */
serial_puts
(
"."
);
...
...
@@ -501,47 +535,69 @@ void ide_set_reset (int idereset)
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*/
int
checkboard
(
void
)
void
get_pcbrev_var
(
unsigned
char
*
pcbrev
,
unsigned
char
*
var
)
{
unsigned
char
s
[
50
];
unsigned
char
bc
,
var
,
rc
;
#if !defined(CONFIG_MIP405T)
unsigned
char
bc
,
rc
,
tmp
;
int
i
;
backup_t
*
b
=
(
backup_t
*
)
s
;
puts
(
"Board: "
);
bc
=
get_board_revcfg
();
var
=
~
bc
;
var
&=
0xf
;
bc
=
in8
(
PLD_BOARD_CFG_REG
);
tmp
=
~
bc
;
tmp
&=
0xf
;
rc
=
0
;
for
(
i
=
0
;
i
<
4
;
i
++
)
{
rc
<<=
1
;
rc
+=
(
var
&
0x1
);
var
>>=
1
;
rc
+=
(
tmp
&
0x1
);
tmp
>>=
1
;
}
rc
++
;
if
((((
bc
>>
4
)
&
0xf
)
==
0x1
)
/* Rev B PCB with */
&&
(
rc
==
0x1
))
/* Population Option 1 is a -3 */
rc
=
3
;
*
pcbrev
=
(
bc
>>
4
)
&
0xf
;
*
var
=
rc
;
#else
unsigned
char
bc
;
bc
=
in8
(
PLD_BOARD_CFG_REG
);
*
pcbrev
=
(
bc
>>
4
)
&
0xf
;
*
var
=
bc
&
0xf
;
#endif
}
/*
* Check Board Identity:
*/
/* serial String: "MIP405_1000" OR "MIP405T_1000" */
#if !defined(CONFIG_MIP405T)
#define BOARD_NAME "MIP405"
#else
#define BOARD_NAME "MIP405T"
#endif
int
checkboard
(
void
)
{
unsigned
char
s
[
50
];
unsigned
char
bc
,
var
;
int
i
;
backup_t
*
b
=
(
backup_t
*
)
s
;
puts
(
"Board: "
);
get_pcbrev_var
(
&
bc
,
&
var
);
i
=
getenv_r
(
"serial#"
,
s
,
32
);
if
((
i
==
0
)
||
strncmp
(
s
,
"MIP405"
,
6
))
{
if
((
i
==
0
)
||
strncmp
(
s
,
BOARD_NAME
,
sizeof
(
BOARD_NAME
)
))
{
get_backup_values
(
b
);
if
(
strncmp
(
b
->
signature
,
"MPL
\0
"
,
4
)
!=
0
)
{
puts
(
"### No HW ID - assuming
MIP405"
);
printf
(
"-%d Rev %c"
,
rc
,
'A'
+
((
bc
>>
4
)
&
0xf
)
);
puts
(
"### No HW ID - assuming
"
BOARD_NAME
);
printf
(
"-%d Rev %c"
,
var
,
'A'
+
bc
);
}
else
{
b
->
serial_name
[
6
]
=
0
;
printf
(
"%s-%d Rev %c SN: %s"
,
b
->
serial_name
,
rc
,
'A'
+
((
bc
>>
4
)
&
0xf
),
&
b
->
serial_name
[
7
]);
b
->
serial_name
[
sizeof
(
BOARD_NAME
)
-
1
]
=
0
;
printf
(
"%s-%d Rev %c SN: %s"
,
b
->
serial_name
,
var
,
'A'
+
bc
,
&
b
->
serial_name
[
sizeof
(
BOARD_NAME
)
]);
}
}
else
{
s
[
6
]
=
0
;
printf
(
"%s-%d Rev %c SN: %s"
,
s
,
rc
,
'A'
+
((
bc
>>
4
)
&
0xf
)
,
&
s
[
7
]);
s
[
sizeof
(
BOARD_NAME
)
-
1
]
=
0
;
printf
(
"%s-%d Rev %c SN: %s"
,
s
,
var
,
'A'
+
bc
,
&
s
[
sizeof
(
BOARD_NAME
)
]);
}
bc
=
in8
(
PLD_EXT_CONF_REG
);
printf
(
" Boot Config: 0x%x
\n
"
,
bc
);
...
...
@@ -613,30 +669,23 @@ static int test_dram (unsigned long ramsize)
int
misc_init_r
(
void
)
{
/* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
if
(
mfdcr
(
strap
)
&
PSR_ROM_LOC
)
mtspr
(
ccr0
,
(
mfspr
(
ccr0
)
&
~
0x80
));
return
(
0
);
}
void
print_mip405_rev
(
void
)
{
unsigned
char
part
,
vers
,
cfg
,
rev
;
cfg
=
get_board_revcfg
();
vers
=
cfg
;
vers
&=
0xf
;
rev
=
(((
vers
&
0x1
)
?
0x8
:
0
)
|
((
vers
&
0x2
)
?
0x4
:
0
)
|
((
vers
&
0x4
)
?
0x2
:
0
)
|
((
vers
&
0x8
)
?
0x1
:
0
));
vers
=
16
-
rev
;
rev
=
vers
;
if
((
rev
==
1
)
&&
((
cfg
>>
4
)
==
1
))
/* Rev B PCB and -1 is a -3 */
rev
=
3
;
unsigned
char
part
,
vers
,
pcbrev
,
var
;
get_pcbrev_var
(
&
pcbrev
,
&
var
);
part
=
in8
(
PLD_PART_REG
);
vers
=
in8
(
PLD_VERS_REG
);
printf
(
"Rev:
MIP405-%d Rev %c PLD
%d Vers %d
\n
"
,
rev
,
((
cfg
>>
4
)
&
0xf
)
+
'A'
,
part
,
vers
);
printf
(
"Rev:
"
BOARD_NAME
"-%d Rev %c PLD
%d Vers %d
\n
"
,
var
,
pcbrev
+
'A'
,
part
&
0x7F
,
vers
);
}
extern
void
mem_test_reloc
(
void
);
...
...
@@ -683,24 +732,32 @@ void print_mip405_info (void)
com_mode
=
in8
(
PLD_COM_MODE_REG
);
ext
=
in8
(
PLD_EXT_CONF_REG
);
printf
(
"PLD Part %d version %d
\n
"
,
part
,
vers
);
printf
(
"PLD Part %d version %d
\n
"
,
part
&
0x7F
,
vers
);
printf
(
"Board Revision %c
\n
"
,
((
cfg
>>
4
)
&
0xf
)
+
'A'
);
printf
(
"Population Options %d %d %d %d
\n
"
,
(
cfg
)
&
0x1
,
(
cfg
>>
1
)
&
0x1
,
(
cfg
>>
2
)
&
0x1
,
(
cfg
>>
3
)
&
0x1
);
printf
(
"User LED %s
\n
"
,
(
com_mode
&
0x4
)
?
"on"
:
"off"
);
printf
(
"UART Clocks %d
\n
"
,
(
com_mode
>>
4
)
&
0x3
);
printf
(
"Test ist %x
\n
"
,
com_mode
);
#if !defined(CONFIG_MIP405T)
printf
(
"User Config Switch %d %d %d %d %d %d %d %d
\n
"
,
(
ext
)
&
0x1
,
(
ext
>>
1
)
&
0x1
,
(
ext
>>
2
)
&
0x1
,
(
ext
>>
3
)
&
0x1
,
(
ext
>>
4
)
&
0x1
,
(
ext
>>
5
)
&
0x1
,
(
ext
>>
6
)
&
0x1
,
(
ext
>>
7
)
&
0x1
);
printf
(
"SER1 uses handshakes %s
\n
"
,
(
ext
&
0x80
)
?
"DTR/DSR"
:
"RTS/CTS"
);
#else
printf
(
"User Config Switch %d %d %d %d %d %d %d %d %d
\n
"
,
(
ext
)
&
0x1
,
(
ext
>>
1
)
&
0x1
,
(
ext
>>
2
)
&
0x1
,
(
ext
>>
3
)
&
0x1
,
(
ext
>>
4
)
&
0x1
,
(
ext
>>
5
)
&
0x1
,
(
ext
>>
6
)
&
0x1
,(
ext
>>
7
)
&
0x1
,(
ext
>>
8
)
&
0x1
);
#endif
printf
(
"IDE Reset %s
\n
"
,
(
ext
&
0x01
)
?
"asserted"
:
"not asserted"
);
printf
(
"IRQs:
\n
"
);
printf
(
" PIIX INTR: %s
\n
"
,
(
irq_reg
&
0x80
)
?
"inactive"
:
"active"
);
#if !defined(CONFIG_MIP405T)
printf
(
" UART0 IRQ: %s
\n
"
,
(
irq_reg
&
0x40
)
?
"inactive"
:
"active"
);
printf
(
" UART1 IRQ: %s
\n
"
,
(
irq_reg
&
0x20
)
?
"inactive"
:
"active"
);
#endif
printf
(
" PIIX SMI: %s
\n
"
,
(
irq_reg
&
0x10
)
?
"inactive"
:
"active"
);
printf
(
" PIIX INIT: %s
\n
"
,
(
irq_reg
&
0x8
)
?
"inactive"
:
"active"
);
printf
(
" PIIX NMI: %s
\n
"
,
(
irq_reg
&
0x4
)
?
"inactive"
:
"active"
);
...
...
board/mpl/mip405/u-boot.lds
浏览文件 @
f3e0de60
...
...
@@ -31,6 +31,10 @@ SECTIONS
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
board/mpl/mip405/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
...
...
cpu/ppc4xx/405gp_pci.c
浏览文件 @
f3e0de60
...
...
@@ -177,7 +177,7 @@ void pci_405gp_init(struct pci_controller *hose)
* PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
* Use byte reversed out routines to handle endianess.
*--------------------------------------------------------------------------*/
out32r
(
PMM0MA
,
pmmma
[
0
]);
/* ensure disabled b4 setting PMM0LA
*/
out32r
(
PMM0MA
,
(
pmmma
[
0
]
&~
0x1
));
/* disable, configure PMMxLA, PMMxPCILA first
*/
out32r
(
PMM0LA
,
pmmla
[
0
]);
out32r
(
PMM0PCILA
,
pmmpcila
[
0
]);
out32r
(
PMM0PCIHA
,
pmmpciha
[
0
]);
...
...
@@ -186,7 +186,7 @@ void pci_405gp_init(struct pci_controller *hose)
/*--------------------------------------------------------------------------+
* PMM1 is not used. Initialize them to zero.
*--------------------------------------------------------------------------*/
out32r
(
PMM1MA
,
pmmma
[
1
]);
/* ensure disabled b4 setting PMM2LA */
out32r
(
PMM1MA
,
(
pmmma
[
1
]
&~
0x1
));
out32r
(
PMM1LA
,
pmmla
[
1
]);
out32r
(
PMM1PCILA
,
pmmpcila
[
1
]);
out32r
(
PMM1PCIHA
,
pmmpciha
[
1
]);
...
...
@@ -195,7 +195,7 @@ void pci_405gp_init(struct pci_controller *hose)
/*--------------------------------------------------------------------------+
* PMM2 is not used. Initialize them to zero.
*--------------------------------------------------------------------------*/
out32r
(
PMM2MA
,
pmmma
[
2
]);
/* ensure disabled b4 setting PMM2LA */
out32r
(
PMM2MA
,
(
pmmma
[
2
]
&~
0x1
));
out32r
(
PMM2LA
,
pmmla
[
2
]);
out32r
(
PMM2PCILA
,
pmmpcila
[
2
]);
out32r
(
PMM2PCIHA
,
pmmpciha
[
2
]);
...
...
cpu/ppc4xx/resetvec.S
浏览文件 @
f3e0de60
/*
Copyright
MontaVista
Software
Incorporated
,
2000
*/
#include <config.h>
.
section
.
resetvec
,
"ax"
#if defined(CONFIG_440)
b
_start_440
#else
#if defined(CONFIG_BOOT_PCI) && defined(CONFIG_MIP405)
b
_start_pci
#else
b
_start
#endif
#endif
include/configs/MIP405.h
浏览文件 @
f3e0de60
...
...
@@ -35,6 +35,16 @@
#define CONFIG_405GP 1
/* This is a PPC405 CPU */
#define CONFIG_4xx 1
/* ...member of PPC4xx family */
#define CONFIG_MIP405 1
/* ...on a MIP405 board */
/***********************************************************
* Note that it may also be a MIP405T board which is a subset of the
* MIP405
***********************************************************/
/***********************************************************
* WARNING:
* CONFIG_BOOT_PCI is only used for first boot-up and should
* NOT be enabled for production bootloader
***********************************************************/
/*#define CONFIG_BOOT_PCI 1*/
/***********************************************************
* Clock
***********************************************************/
...
...
@@ -43,7 +53,7 @@
/***********************************************************
* Command definitions
***********************************************************/
#define
CONFIG_COMMANDS
\
#define
MIP405_COMMON_CMDS
\
(CONFIG_CMD_DFL | \
CFG_CMD_IDE | \
CFG_CMD_DHCP | \
...
...
@@ -56,12 +66,21 @@
CFG_CMD_REGINFO | \
CFG_CMD_DATE | \
CFG_CMD_ELF | \
CFG_CMD_USB | \
CFG_CMD_MII | \
CFG_CMD_DOC | \
CFG_CMD_SAVES | \
CFG_CMD_BSP )
#if defined(CONFIG_MIP405T)
#define CONFIG_COMMANDS \
MIP405_COMMON_CMDS
#else
#define CONFIG_COMMANDS \
(MIP405_COMMON_CMDS | \
CFG_CMD_USB | \
CFG_CMD_DOC )
#endif
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
...
...
@@ -97,9 +116,9 @@
* Definitions for Serial Presence Detect EEPROM address
* (to get SDRAM settings)
***************************************************************/
#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
/*
#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
#define SDRAM_EEPROM_READ_ADDRESS 0xA1
*/
/**************************************************************
* Environment definitions
**************************************************************/
...
...
@@ -287,7 +306,12 @@
/************************************************************
* IDE/ATA stuff
************************************************************/
#if defined(CONFIG_MIP405T)
#define CFG_IDE_MAXBUS 1
/* MIP405T has only one IDE bus */
#else
#define CFG_IDE_MAXBUS 2
/* max. 2 IDE busses */
#endif
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2)
/* max. 2 drives per IDE bus */
#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS
/* base address */
...
...
@@ -351,13 +375,14 @@
/************************************************************
* USB support EXPERIMENTAL
************************************************************/
#if !defined(CONFIG_MIP405T)
#define CONFIG_USB_UHCI
#define CONFIG_USB_KEYBOARD
#define CONFIG_USB_STORAGE
/* Enable needed helper functions */
#define CFG_DEVICE_DEREGISTER
/* needs device_deregister */
#endif
/************************************************************
* Debug support
************************************************************/
...
...
@@ -369,8 +394,19 @@
/************************************************************
* Ident
************************************************************/
#define VERSION_TAG "released"
#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, MEV-10072-001 " VERSION_TAG
#if !defined(CONFIG_MIP405T)
#define CONFIG_ISO_STRING "MEV-10072-001"
#else
#define CONFIG_ISO_STRING "MEV-10082-001"
#endif
#if !defined(CONFIG_BOOT_PCI)
#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
#else
#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
#endif
#endif
/* __CONFIG_H */
include/configs/PIP405.h
浏览文件 @
f3e0de60
...
...
@@ -368,7 +368,8 @@
* Ident
************************************************************/
#define VERSION_TAG "released"
#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, MEV-10066-001 " VERSION_TAG
#define CONFIG_ISO_STRING "MEV-10066-001"
#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
#endif
/* __CONFIG_H */
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