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体验新版 GitCode,发现更多精彩内容 >>
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c7e1a43d
编写于
5月 21, 2010
作者:
K
Kumar Gala
浏览文件
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电子邮件补丁
差异文件
ppc/85xx: Convert MPC8536DS to using board common ICS307 code
Signed-off-by:
N
Kumar Gala
<
galak@kernel.crashing.org
>
上级
509c4c4c
变更
3
显示空白变更内容
内联
并排
Showing
3 changed file
with
6 addition
and
157 deletion
+6
-157
board/freescale/common/Makefile
board/freescale/common/Makefile
+1
-0
board/freescale/mpc8536ds/mpc8536ds.c
board/freescale/mpc8536ds/mpc8536ds.c
+0
-148
include/configs/MPC8536DS.h
include/configs/MPC8536DS.h
+5
-9
未找到文件。
board/freescale/common/Makefile
浏览文件 @
c7e1a43d
...
...
@@ -42,6 +42,7 @@ COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
COBJS-$(CONFIG_MPC8548CDS)
+=
cds_pci_ft.o
COBJS-$(CONFIG_MPC8555CDS)
+=
cds_pci_ft.o
COBJS-$(CONFIG_MPC8536DS)
+=
ics307_clk.o
COBJS-$(CONFIG_MPC8572DS)
+=
ics307_clk.o
COBJS-$(CONFIG_P1022DS)
+=
ics307_clk.o
COBJS-$(CONFIG_P2020DS)
+=
ics307_clk.o
...
...
board/freescale/mpc8536ds/mpc8536ds.c
浏览文件 @
c7e1a43d
...
...
@@ -350,154 +350,6 @@ int board_early_init_r(void)
return
0
;
}
#ifdef CONFIG_GET_CLK_FROM_ICS307
/* decode S[0-2] to Output Divider (OD) */
static
unsigned
char
ics307_S_to_OD
[]
=
{
10
,
2
,
8
,
4
,
5
,
7
,
3
,
6
};
/* Calculate frequency being generated by ICS307-02 clock chip based upon
* the control bytes being programmed into it. */
/* XXX: This function should probably go into a common library */
static
unsigned
long
ics307_clk_freq
(
unsigned
char
cw0
,
unsigned
char
cw1
,
unsigned
char
cw2
)
{
const
unsigned
long
long
InputFrequency
=
CONFIG_ICS307_REFCLK_HZ
;
unsigned
long
VDW
=
((
cw1
<<
1
)
&
0x1FE
)
+
((
cw2
>>
7
)
&
1
);
unsigned
long
RDW
=
cw2
&
0x7F
;
unsigned
long
OD
=
ics307_S_to_OD
[
cw0
&
0x7
];
unsigned
long
freq
;
/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
/* cw0: C1 C0 TTL F1 F0 S2 S1 S0
* cw1: V8 V7 V6 V5 V4 V3 V2 V1
* cw2: V0 R6 R5 R4 R3 R2 R1 R0
*
* R6:R0 = Reference Divider Word (RDW)
* V8:V0 = VCO Divider Word (VDW)
* S2:S0 = Output Divider Select (OD)
* F1:F0 = Function of CLK2 Output
* TTL = duty cycle
* C1:C0 = internal load capacitance for cyrstal
*/
/* Adding 1 to get a "nicely" rounded number, but this needs
* more tweaking to get a "properly" rounded number. */
freq
=
1
+
(
InputFrequency
*
2
*
(
VDW
+
8
)
/
((
RDW
+
2
)
*
OD
));
debug
(
"ICS307: CW[0-2]: %02X %02X %02X => %u Hz
\n
"
,
cw0
,
cw1
,
cw2
,
freq
);
return
freq
;
}
unsigned
long
get_board_sys_clk
(
ulong
dummy
)
{
u8
*
pixis_base
=
(
u8
*
)
PIXIS_BASE
;
return
ics307_clk_freq
(
in_8
(
pixis_base
+
PIXIS_VSYSCLK0
),
in_8
(
pixis_base
+
PIXIS_VSYSCLK1
),
in_8
(
pixis_base
+
PIXIS_VSYSCLK2
)
);
}
unsigned
long
get_board_ddr_clk
(
ulong
dummy
)
{
u8
*
pixis_base
=
(
u8
*
)
PIXIS_BASE
;
return
ics307_clk_freq
(
in_8
(
pixis_base
+
PIXIS_VDDRCLK0
),
in_8
(
pixis_base
+
PIXIS_VDDRCLK1
),
in_8
(
pixis_base
+
PIXIS_VDDRCLK2
)
);
}
#else
unsigned
long
get_board_sys_clk
(
ulong
dummy
)
{
u8
i
;
ulong
val
=
0
;
u8
*
pixis_base
=
(
u8
*
)
PIXIS_BASE
;
i
=
in_8
(
pixis_base
+
PIXIS_SPD
);
i
&=
0x07
;
switch
(
i
)
{
case
0
:
val
=
33333333
;
break
;
case
1
:
val
=
40000000
;
break
;
case
2
:
val
=
50000000
;
break
;
case
3
:
val
=
66666666
;
break
;
case
4
:
val
=
83333333
;
break
;
case
5
:
val
=
100000000
;
break
;
case
6
:
val
=
133333333
;
break
;
case
7
:
val
=
166666666
;
break
;
}
return
val
;
}
unsigned
long
get_board_ddr_clk
(
ulong
dummy
)
{
u8
i
;
ulong
val
=
0
;
u8
*
pixis_base
=
(
u8
*
)
PIXIS_BASE
;
i
=
in_8
(
pixis_base
+
PIXIS_SPD
);
i
&=
0x38
;
i
>>=
3
;
switch
(
i
)
{
case
0
:
val
=
33333333
;
break
;
case
1
:
val
=
40000000
;
break
;
case
2
:
val
=
50000000
;
break
;
case
3
:
val
=
66666666
;
break
;
case
4
:
val
=
83333333
;
break
;
case
5
:
val
=
100000000
;
break
;
case
6
:
val
=
133333333
;
break
;
case
7
:
val
=
166666666
;
break
;
}
return
val
;
}
#endif
int
board_eth_init
(
bd_t
*
bis
)
{
#ifdef CONFIG_TSEC_ENET
...
...
include/configs/MPC8536DS.h
浏览文件 @
c7e1a43d
/*
* Copyright 200
8-2009
Freescale Semiconductor, Inc.
* Copyright 200
7-2009,2010
Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
...
...
@@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_MK_36BIT
#define CONFIG_PHYS_64BIT 1
#endif
...
...
@@ -70,15 +72,9 @@
#define CONFIG_TSEC_ENET
/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#ifndef __ASSEMBLY__
extern
unsigned
long
get_board_sys_clk
(
unsigned
long
dummy
);
extern
unsigned
long
get_board_ddr_clk
(
unsigned
long
dummy
);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
/* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
/* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define CONFIG_ICS307_REFCLK_HZ 33333000
/* ICS307 clock chip ref freq */
#define CONFIG_GET_CLK_FROM_ICS307
/* decode sysclk and ddrclk freq
from ICS307 instead of switches */
/*
* These can be toggled for performance analysis, otherwise use default.
...
...
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