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c5d11e79
编写于
8月 26, 2008
作者:
W
Wolfgang Denk
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'master' of
git://git.denx.de/u-boot-mpc83xx
上级
b4e07520
1a9eeb78
变更
19
显示空白变更内容
内联
并排
Showing
19 changed file
with
273 addition
and
354 deletion
+273
-354
Makefile
Makefile
+2
-2
board/freescale/mpc8315erdb/mpc8315erdb.c
board/freescale/mpc8315erdb/mpc8315erdb.c
+37
-2
board/freescale/mpc8349emds/mpc8349emds.c
board/freescale/mpc8349emds/mpc8349emds.c
+9
-0
board/freescale/mpc8349emds/pci.c
board/freescale/mpc8349emds/pci.c
+103
-311
board/matrix_vision/mvblm7/Makefile
board/matrix_vision/mvblm7/Makefile
+0
-0
board/matrix_vision/mvblm7/config.mk
board/matrix_vision/mvblm7/config.mk
+0
-0
board/matrix_vision/mvblm7/fpga.c
board/matrix_vision/mvblm7/fpga.c
+0
-0
board/matrix_vision/mvblm7/fpga.h
board/matrix_vision/mvblm7/fpga.h
+0
-0
board/matrix_vision/mvblm7/mvblm7.c
board/matrix_vision/mvblm7/mvblm7.c
+0
-0
board/matrix_vision/mvblm7/mvblm7.h
board/matrix_vision/mvblm7/mvblm7.h
+0
-0
board/matrix_vision/mvblm7/mvblm7_autoscript
board/matrix_vision/mvblm7/mvblm7_autoscript
+8
-2
board/matrix_vision/mvblm7/pci.c
board/matrix_vision/mvblm7/pci.c
+0
-0
common/fdt_support.c
common/fdt_support.c
+23
-7
cpu/mpc83xx/pci.c
cpu/mpc83xx/pci.c
+26
-0
include/asm-ppc/immap_83xx.h
include/asm-ppc/immap_83xx.h
+3
-1
include/configs/MPC8315ERDB.h
include/configs/MPC8315ERDB.h
+2
-0
include/configs/MPC8349EMDS.h
include/configs/MPC8349EMDS.h
+24
-2
include/configs/MVBLM7.h
include/configs/MVBLM7.h
+29
-27
include/mpc83xx.h
include/mpc83xx.h
+7
-0
未找到文件。
Makefile
浏览文件 @
c5d11e79
...
@@ -2065,7 +2065,7 @@ MPC8313ERDB_NAND_66_config: unconfig
...
@@ -2065,7 +2065,7 @@ MPC8313ERDB_NAND_66_config: unconfig
fi
;
\
fi
;
\
if
[
"
$(
findstring
_NAND_,
$@
)
"
]
;
then
\
if
[
"
$(
findstring
_NAND_,
$@
)
"
]
;
then
\
$(XECHO)
-n
"...NAND..."
;
\
$(XECHO)
-n
"...NAND..."
;
\
echo
"TEXT_BASE = 0x00100000"
>
$(obj)
/
board/freescale/mpc8313erdb/config.tmp
;
\
echo
"TEXT_BASE = 0x00100000"
>
$(obj)
board/freescale/mpc8313erdb/config.tmp
;
\
echo
"#define CONFIG_NAND_U_BOOT"
>>
$(obj)
include/config.h
;
\
echo
"#define CONFIG_NAND_U_BOOT"
>>
$(obj)
include/config.h
;
\
fi
;
fi
;
@
$(MKCONFIG)
-a
MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
@
$(MKCONFIG)
-a
MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
...
@@ -2180,7 +2180,7 @@ MPC837XERDB_config: unconfig
...
@@ -2180,7 +2180,7 @@ MPC837XERDB_config: unconfig
@
$(MKCONFIG)
-a
MPC837XERDB ppc mpc83xx mpc837xerdb freescale
@
$(MKCONFIG)
-a
MPC837XERDB ppc mpc83xx mpc837xerdb freescale
MVBLM7_config
:
unconfig
MVBLM7_config
:
unconfig
@
$(MKCONFIG)
$
(
@:_config
=)
ppc mpc83xx mvblm7
@
$(MKCONFIG)
$
(
@:_config
=)
ppc mpc83xx mvblm7
matrix_vision
sbc8349_config
:
unconfig
sbc8349_config
:
unconfig
@
$(MKCONFIG)
$
(
@:_config
=)
ppc mpc83xx sbc8349
@
$(MKCONFIG)
$
(
@:_config
=)
ppc mpc83xx sbc8349
...
...
board/freescale/mpc8315erdb/mpc8315erdb.c
浏览文件 @
c5d11e79
...
@@ -25,9 +25,8 @@
...
@@ -25,9 +25,8 @@
#include <common.h>
#include <common.h>
#include <i2c.h>
#include <i2c.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <libfdt.h>
#
endif
#
include <fdt_support.h>
#include <pci.h>
#include <pci.h>
#include <mpc83xx.h>
#include <mpc83xx.h>
...
@@ -122,11 +121,47 @@ void pci_init_board(void)
...
@@ -122,11 +121,47 @@ void pci_init_board(void)
}
}
#if defined(CONFIG_OF_BOARD_SETUP)
#if defined(CONFIG_OF_BOARD_SETUP)
void
fdt_tsec1_fixup
(
void
*
fdt
,
bd_t
*
bd
)
{
char
*
mpc8315erdb
=
getenv
(
"mpc8315erdb"
);
const
char
disabled
[]
=
"disabled"
;
const
char
*
path
;
int
ret
;
if
(
!
mpc8315erdb
)
return
;
if
(
!
strcmp
(
mpc8315erdb
,
"tsec1"
))
{
return
;
}
else
if
(
strcmp
(
mpc8315erdb
,
"ulpi"
))
{
printf
(
"WARNING: wrong `mpc8315erdb' environment "
"variable specified: `%s'. Should be `ulpi' "
"or `tsec1'.
\n
"
,
mpc8315erdb
);
return
;
}
ret
=
fdt_path_offset
(
fdt
,
"/aliases"
);
if
(
ret
<
0
)
{
printf
(
"WARNING: can't find /aliases node
\n
"
);
return
;
}
path
=
fdt_getprop
(
fdt
,
ret
,
"ethernet0"
,
NULL
);
if
(
!
path
)
{
printf
(
"WARNING: can't find ethernet0 alias
\n
"
);
return
;
}
do_fixup_by_path
(
fdt
,
path
,
"status"
,
disabled
,
sizeof
(
disabled
),
1
);
}
void
ft_board_setup
(
void
*
blob
,
bd_t
*
bd
)
void
ft_board_setup
(
void
*
blob
,
bd_t
*
bd
)
{
{
ft_cpu_setup
(
blob
,
bd
);
ft_cpu_setup
(
blob
,
bd
);
#ifdef CONFIG_PCI
#ifdef CONFIG_PCI
ft_pci_setup
(
blob
,
bd
);
ft_pci_setup
(
blob
,
bd
);
#endif
#endif
fdt_fixup_dr_usb
(
blob
,
bd
);
fdt_tsec1_fixup
(
blob
,
bd
);
}
}
#endif
#endif
board/freescale/mpc8349emds/mpc8349emds.c
浏览文件 @
c5d11e79
...
@@ -165,6 +165,15 @@ int fixed_sdram(void)
...
@@ -165,6 +165,15 @@ int fixed_sdram(void)
int
checkboard
(
void
)
int
checkboard
(
void
)
{
{
/*
* Warning: do not read the BCSR registers here
*
* There is a timing bug in the 8349E and 8349EA BCSR code
* version 1.2 (read from BCSR 11) that will cause the CFI
* flash initialization code to overwrite BCSR 0, disabling
* the serial ports and gigabit ethernet
*/
puts
(
"Board: Freescale MPC8349EMDS
\n
"
);
puts
(
"Board: Freescale MPC8349EMDS
\n
"
);
return
0
;
return
0
;
}
}
...
...
board/freescale/mpc8349emds/pci.c
浏览文件 @
c5d11e79
...
@@ -20,58 +20,63 @@
...
@@ -20,58 +20,63 @@
*/
*/
#include <asm/mmu.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
#include <common.h>
#include <
asm/global_data
.h>
#include <
mpc83xx
.h>
#include <pci.h>
#include <pci.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <i2c.h>
#if defined(CONFIG_OF_LIBFDT)
#include <asm/fsl_i2c.h>
#include <libfdt.h>
#include <fdt_support.h>
#endif
DECLARE_GLOBAL_DATA_PTR
;
DECLARE_GLOBAL_DATA_PTR
;
#ifdef CONFIG_PCI
#ifdef CONFIG_PCI
/* System RAM mapped to PCI space */
static
struct
pci_region
pci1_regions
[]
=
{
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
{
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
bus_start:
CFG_PCI1_MEM_BASE
,
phys_start:
CFG_PCI1_MEM_PHYS
,
#ifndef CONFIG_PCI_PNP
size:
CFG_PCI1_MEM_SIZE
,
static
struct
pci_config_table
pci_mpc8349emds_config_table
[]
=
{
flags:
PCI_REGION_MEM
|
PCI_REGION_PREFETCH
{
PCI_ANY_ID
,
PCI_ANY_ID
,
PCI_ANY_ID
,
PCI_ANY_ID
,
},
PCI_IDSEL_NUMBER
,
PCI_ANY_ID
,
{
pci_cfgfunc_config_device
,
{
PCI_ENET0_IOADDR
,
bus_start:
CFG_PCI1_IO_BASE
,
PCI_ENET0_MEMADDR
,
phys_start:
CFG_PCI1_IO_PHYS
,
PCI_COMMAND_MEMORY
|
PCI_COMMAND_MASTER
size:
CFG_PCI1_IO_SIZE
,
}
flags:
PCI_REGION_IO
},
{
bus_start:
CFG_PCI1_MMIO_BASE
,
phys_start:
CFG_PCI1_MMIO_PHYS
,
size:
CFG_PCI1_MMIO_SIZE
,
flags:
PCI_REGION_MEM
},
},
{}
};
};
#endif
static
struct
pci_controller
pci_hose
[]
=
{
#ifdef CONFIG_MPC83XX_PCI2
static
struct
pci_region
pci2_regions
[]
=
{
{
{
#ifndef CONFIG_PCI_PNP
bus_start:
CFG_PCI2_MEM_BASE
,
config_table:
pci_mpc8349emds_config_table
,
phys_start:
CFG_PCI2_MEM_PHYS
,
#endif
size:
CFG_PCI2_MEM_SIZE
,
flags:
PCI_REGION_MEM
|
PCI_REGION_PREFETCH
},
},
{
{
#ifndef CONFIG_PCI_PNP
bus_start:
CFG_PCI2_IO_BASE
,
config_table:
pci_mpc8349emds_config_table
,
phys_start:
CFG_PCI2_IO_PHYS
,
#endif
size:
CFG_PCI2_IO_SIZE
,
}
flags:
PCI_REGION_IO
},
{
bus_start:
CFG_PCI2_MMIO_BASE
,
phys_start:
CFG_PCI2_MMIO_PHYS
,
size:
CFG_PCI2_MMIO_SIZE
,
flags:
PCI_REGION_MEM
},
};
};
#endif
/**************************************************************************
#ifndef CONFIG_PCISLAVE
*
void
pib_init
(
void
)
* pib_init() -- initialize the PCA9555PW IO expander on the PIB board
*
*/
void
pib_init
(
void
)
{
{
u8
val8
,
orig_i2c_bus
;
u8
val8
,
orig_i2c_bus
;
/*
/*
...
@@ -128,299 +133,86 @@ pib_init(void)
...
@@ -128,299 +133,86 @@ pib_init(void)
i2c_set_bus_num
(
orig_i2c_bus
);
i2c_set_bus_num
(
orig_i2c_bus
);
}
}
/**************************************************************************
void
pci_init_board
(
void
)
* pci_init_board()
*
* NOTICE: PCI2 is not currently supported
*
*/
void
pci_init_board
(
void
)
{
{
volatile
immap_t
*
immr
;
volatile
immap_t
*
immr
=
(
volatile
immap_t
*
)
CFG_IMMR
;
volatile
clk83xx_t
*
clk
;
volatile
clk83xx_t
*
clk
=
(
volatile
clk83xx_t
*
)
&
immr
->
clk
;
volatile
law83xx_t
*
pci_law
;
volatile
law83xx_t
*
pci_law
=
immr
->
sysconf
.
pcilaw
;
volatile
pot83xx_t
*
pci_pot
;
#ifndef CONFIG_MPC83XX_PCI2
volatile
pcictrl83xx_t
*
pci_ctrl
;
struct
pci_region
*
reg
[]
=
{
pci1_regions
};
volatile
pciconf83xx_t
*
pci_conf
;
#else
u16
reg16
;
struct
pci_region
*
reg
[]
=
{
pci1_regions
,
pci2_regions
};
u32
reg32
;
#endif
u32
dev
;
struct
pci_controller
*
hose
;
immr
=
(
immap_t
*
)
CFG_IMMR
;
clk
=
(
clk83xx_t
*
)
&
immr
->
clk
;
pci_law
=
immr
->
sysconf
.
pcilaw
;
pci_pot
=
immr
->
ios
.
pot
;
pci_ctrl
=
immr
->
pci_ctrl
;
pci_conf
=
immr
->
pci_conf
;
hose
=
&
pci_hose
[
0
];
/* initialize the PCA9555PW IO expander on the PIB board */
pib_init
();
pib_init
();
/*
/* Enable all 8 PCI_CLK_OUTPUTS */
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
*/
reg32
=
clk
->
occr
;
udelay
(
2000
);
clk
->
occr
=
0xff000000
;
clk
->
occr
=
0xff000000
;
udelay
(
2000
);
udelay
(
2000
);
/*
/* Configure PCI Local Access Windows */
* Release PCI RST Output signal
*/
pci_ctrl
[
0
].
gcr
=
0
;
udelay
(
2000
);
pci_ctrl
[
0
].
gcr
=
1
;
#ifdef CONFIG_MPC83XX_PCI2
pci_ctrl
[
1
].
gcr
=
0
;
udelay
(
2000
);
pci_ctrl
[
1
].
gcr
=
1
;
#endif
/* We need to wait at least a 1sec based on PCI specs */
{
int
i
;
for
(
i
=
0
;
i
<
1000
;
++
i
)
udelay
(
1000
);
}
/*
* Configure PCI Local Access Windows
*/
pci_law
[
0
].
bar
=
CFG_PCI1_MEM_PHYS
&
LAWBAR_BAR
;
pci_law
[
0
].
bar
=
CFG_PCI1_MEM_PHYS
&
LAWBAR_BAR
;
pci_law
[
0
].
ar
=
LAWAR_EN
|
LAWAR_SIZE_1G
;
pci_law
[
0
].
ar
=
LAWAR_EN
|
LAWAR_SIZE_1G
;
pci_law
[
1
].
bar
=
CFG_PCI1_IO_PHYS
&
LAWBAR_BAR
;
pci_law
[
1
].
bar
=
CFG_PCI1_IO_PHYS
&
LAWBAR_BAR
;
pci_law
[
1
].
ar
=
LAWAR_EN
|
LAWAR_SIZE_4M
;
pci_law
[
1
].
ar
=
LAWAR_EN
|
LAWAR_SIZE_4M
;
/*
udelay
(
2000
);
* Configure PCI Outbound Translation Windows
*/
/* PCI1 mem space - prefetch */
pci_pot
[
0
].
potar
=
(
CFG_PCI1_MEM_BASE
>>
12
)
&
POTAR_TA_MASK
;
pci_pot
[
0
].
pobar
=
(
CFG_PCI1_MEM_PHYS
>>
12
)
&
POBAR_BA_MASK
;
pci_pot
[
0
].
pocmr
=
POCMR_EN
|
POCMR_PREFETCH_EN
|
(
POCMR_CM_256M
&
POCMR_CM_MASK
);
/* PCI1 IO space */
pci_pot
[
1
].
potar
=
(
CFG_PCI1_IO_BASE
>>
12
)
&
POTAR_TA_MASK
;
pci_pot
[
1
].
pobar
=
(
CFG_PCI1_IO_PHYS
>>
12
)
&
POBAR_BA_MASK
;
pci_pot
[
1
].
pocmr
=
POCMR_EN
|
POCMR_IO
|
(
POCMR_CM_1M
&
POCMR_CM_MASK
);
/* PCI1 mmio - non-prefetch mem space */
pci_pot
[
2
].
potar
=
(
CFG_PCI1_MMIO_BASE
>>
12
)
&
POTAR_TA_MASK
;
pci_pot
[
2
].
pobar
=
(
CFG_PCI1_MMIO_PHYS
>>
12
)
&
POBAR_BA_MASK
;
pci_pot
[
2
].
pocmr
=
POCMR_EN
|
(
POCMR_CM_256M
&
POCMR_CM_MASK
);
/*
* Configure PCI Inbound Translation Windows
*/
/* we need RAM mapped to PCI space for the devices to
* access main memory */
pci_ctrl
[
0
].
pitar1
=
0x0
;
pci_ctrl
[
0
].
pibar1
=
0x0
;
pci_ctrl
[
0
].
piebar1
=
0x0
;
pci_ctrl
[
0
].
piwar1
=
PIWAR_EN
|
PIWAR_PF
|
PIWAR_RTT_SNOOP
|
PIWAR_WTT_SNOOP
|
(
__ilog2
(
gd
->
ram_size
)
-
1
);
hose
->
first_busno
=
0
;
hose
->
last_busno
=
0xff
;
/* PCI memory prefetch space */
pci_set_region
(
hose
->
regions
+
0
,
CFG_PCI1_MEM_BASE
,
CFG_PCI1_MEM_PHYS
,
CFG_PCI1_MEM_SIZE
,
PCI_REGION_MEM
|
PCI_REGION_PREFETCH
);
/* PCI memory space */
pci_set_region
(
hose
->
regions
+
1
,
CFG_PCI1_MMIO_BASE
,
CFG_PCI1_MMIO_PHYS
,
CFG_PCI1_MMIO_SIZE
,
PCI_REGION_MEM
);
/* PCI IO space */
pci_set_region
(
hose
->
regions
+
2
,
CFG_PCI1_IO_BASE
,
CFG_PCI1_IO_PHYS
,
CFG_PCI1_IO_SIZE
,
PCI_REGION_IO
);
/* System memory space */
pci_set_region
(
hose
->
regions
+
3
,
CONFIG_PCI_SYS_MEM_BUS
,
CONFIG_PCI_SYS_MEM_PHYS
,
gd
->
ram_size
,
PCI_REGION_MEM
|
PCI_REGION_MEMORY
);
hose
->
region_count
=
4
;
pci_setup_indirect
(
hose
,
(
CFG_IMMR
+
0x8300
),
(
CFG_IMMR
+
0x8304
));
pci_register_hose
(
hose
);
/*
* Write to Command register
*/
reg16
=
0xff
;
dev
=
PCI_BDF
(
hose
->
first_busno
,
0
,
0
);
pci_hose_read_config_word
(
hose
,
dev
,
PCI_COMMAND
,
&
reg16
);
reg16
|=
PCI_COMMAND_SERR
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
;
pci_hose_write_config_word
(
hose
,
dev
,
PCI_COMMAND
,
reg16
);
/*
* Clear non-reserved bits in status register.
*/
pci_hose_write_config_word
(
hose
,
dev
,
PCI_STATUS
,
0xffff
);
pci_hose_write_config_byte
(
hose
,
dev
,
PCI_LATENCY_TIMER
,
0x80
);
pci_hose_write_config_byte
(
hose
,
dev
,
PCI_CACHE_LINE_SIZE
,
0x08
);
#ifdef CONFIG_PCI_SCAN_SHOW
#ifndef CONFIG_MPC83XX_PCI2
printf
(
"PCI: Bus Dev VenId DevId Class Int
\n
"
);
mpc83xx_pci_init
(
1
,
reg
,
0
);
#else
mpc83xx_pci_init
(
2
,
reg
,
0
);
#endif
#endif
/*
}
* Hose scan.
*/
hose
->
last_busno
=
pci_hose_scan
(
hose
);
#ifdef CONFIG_MPC83XX_PCI2
hose
=
&
pci_hose
[
1
];
/*
* Configure PCI Outbound Translation Windows
*/
/* PCI2 mem space - prefetch */
pci_pot
[
3
].
potar
=
(
CFG_PCI2_MEM_BASE
>>
12
)
&
POTAR_TA_MASK
;
pci_pot
[
3
].
pobar
=
(
CFG_PCI2_MEM_PHYS
>>
12
)
&
POBAR_BA_MASK
;
pci_pot
[
3
].
pocmr
=
POCMR_EN
|
POCMR_PCI2
|
POCMR_PREFETCH_EN
|
(
POCMR_CM_256M
&
POCMR_CM_MASK
);
/* PCI2 IO space */
pci_pot
[
4
].
potar
=
(
CFG_PCI2_IO_BASE
>>
12
)
&
POTAR_TA_MASK
;
pci_pot
[
4
].
pobar
=
(
CFG_PCI2_IO_PHYS
>>
12
)
&
POBAR_BA_MASK
;
pci_pot
[
4
].
pocmr
=
POCMR_EN
|
POCMR_PCI2
|
POCMR_IO
|
(
POCMR_CM_1M
&
POCMR_CM_MASK
);
/* PCI2 mmio - non-prefetch mem space */
pci_pot
[
5
].
potar
=
(
CFG_PCI2_MMIO_BASE
>>
12
)
&
POTAR_TA_MASK
;
pci_pot
[
5
].
pobar
=
(
CFG_PCI2_MMIO_PHYS
>>
12
)
&
POBAR_BA_MASK
;
pci_pot
[
5
].
pocmr
=
POCMR_EN
|
POCMR_PCI2
|
(
POCMR_CM_256M
&
POCMR_CM_MASK
);
/*
* Configure PCI Inbound Translation Windows
*/
/* we need RAM mapped to PCI space for the devices to
* access main memory */
pci_ctrl
[
1
].
pitar1
=
0x0
;
pci_ctrl
[
1
].
pibar1
=
0x0
;
pci_ctrl
[
1
].
piebar1
=
0x0
;
pci_ctrl
[
1
].
piwar1
=
PIWAR_EN
|
PIWAR_PF
|
PIWAR_RTT_SNOOP
|
PIWAR_WTT_SNOOP
|
(
__ilog2
(
gd
->
ram_size
)
-
1
);
hose
->
first_busno
=
pci_hose
[
0
].
last_busno
+
1
;
hose
->
last_busno
=
0xff
;
/* PCI memory prefetch space */
pci_set_region
(
hose
->
regions
+
0
,
CFG_PCI2_MEM_BASE
,
CFG_PCI2_MEM_PHYS
,
CFG_PCI2_MEM_SIZE
,
PCI_REGION_MEM
|
PCI_REGION_PREFETCH
);
/* PCI memory space */
pci_set_region
(
hose
->
regions
+
1
,
CFG_PCI2_MMIO_BASE
,
CFG_PCI2_MMIO_PHYS
,
CFG_PCI2_MMIO_SIZE
,
PCI_REGION_MEM
);
/* PCI IO space */
pci_set_region
(
hose
->
regions
+
2
,
CFG_PCI2_IO_BASE
,
CFG_PCI2_IO_PHYS
,
CFG_PCI2_IO_SIZE
,
PCI_REGION_IO
);
/* System memory space */
pci_set_region
(
hose
->
regions
+
3
,
CONFIG_PCI_SYS_MEM_BUS
,
CONFIG_PCI_SYS_MEM_PHYS
,
gd
->
ram_size
,
PCI_REGION_MEM
|
PCI_REGION_MEMORY
);
hose
->
region_count
=
4
;
pci_setup_indirect
(
hose
,
#else
(
CFG_IMMR
+
0x8380
),
void
pci_init_board
(
void
)
(
CFG_IMMR
+
0x8384
));
{
volatile
immap_t
*
immr
=
(
volatile
immap_t
*
)
CFG_IMMR
;
volatile
clk83xx_t
*
clk
=
(
volatile
clk83xx_t
*
)
&
immr
->
clk
;
volatile
law83xx_t
*
pci_law
=
immr
->
sysconf
.
pcilaw
;
volatile
pcictrl83xx_t
*
pci_ctrl
=
&
immr
->
pci_ctrl
[
0
];
struct
pci_region
*
reg
[]
=
{
pci1_regions
};
pci_register_hose
(
hose
);
/* Enable all 8 PCI_CLK_OUTPUTS */
clk
->
occr
=
0xff000000
;
udelay
(
2000
);
/*
/* Configure PCI Local Access Windows */
* Write to Command register
pci_law
[
0
].
bar
=
CFG_PCI1_MEM_PHYS
&
LAWBAR_BAR
;
*/
pci_law
[
0
].
ar
=
LAWAR_EN
|
LAWAR_SIZE_1G
;
reg16
=
0xff
;
dev
=
PCI_BDF
(
hose
->
first_busno
,
0
,
0
);
pci_hose_read_config_word
(
hose
,
dev
,
PCI_COMMAND
,
&
reg16
);
reg16
|=
PCI_COMMAND_SERR
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
;
pci_hose_write_config_word
(
hose
,
dev
,
PCI_COMMAND
,
reg16
);
/*
pci_law
[
1
].
bar
=
CFG_PCI1_IO_PHYS
&
LAWBAR_BAR
;
* Clear non-reserved bits in status register.
pci_law
[
1
].
ar
=
LAWAR_EN
|
LAWAR_SIZE_4M
;
*/
pci_hose_write_config_word
(
hose
,
dev
,
PCI_STATUS
,
0xffff
);
pci_hose_write_config_byte
(
hose
,
dev
,
PCI_LATENCY_TIMER
,
0x80
);
pci_hose_write_config_byte
(
hose
,
dev
,
PCI_CACHE_LINE_SIZE
,
0x08
);
/*
udelay
(
2000
);
* Hose scan.
*/
hose
->
last_busno
=
pci_hose_scan
(
hose
);
#endif
mpc83xx_pci_init
(
1
,
reg
,
0
);
/* Configure PCI Inbound Translation Windows (3 1MB windows) */
pci_ctrl
->
pitar0
=
0x0
;
pci_ctrl
->
pibar0
=
0x0
;
pci_ctrl
->
piwar0
=
PIWAR_EN
|
PIWAR_PF
|
PIWAR_RTT_SNOOP
|
PIWAR_WTT_SNOOP
|
PIWAR_IWS_1M
;
pci_ctrl
->
pitar1
=
0x0
;
pci_ctrl
->
pibar1
=
0x0
;
pci_ctrl
->
piebar1
=
0x0
;
pci_ctrl
->
piwar1
=
PIWAR_EN
|
PIWAR_PF
|
PIWAR_RTT_SNOOP
|
PIWAR_WTT_SNOOP
|
PIWAR_IWS_1M
;
pci_ctrl
->
pitar2
=
0x0
;
pci_ctrl
->
pibar2
=
0x0
;
pci_ctrl
->
piebar2
=
0x0
;
pci_ctrl
->
piwar2
=
PIWAR_EN
|
PIWAR_PF
|
PIWAR_RTT_SNOOP
|
PIWAR_WTT_SNOOP
|
PIWAR_IWS_1M
;
/* Unlock the configuration bit */
mpc83xx_pcislave_unlock
(
0
);
printf
(
"PCI: Agent mode enabled
\n
"
);
}
}
#endif
/* CONFIG_PCISLAVE */
#if defined(CONFIG_OF_LIBFDT)
void
ft_pci_setup
(
void
*
blob
,
bd_t
*
bd
)
{
int
nodeoffset
;
int
tmp
[
2
];
const
char
*
path
;
nodeoffset
=
fdt_path_offset
(
blob
,
"/aliases"
);
if
(
nodeoffset
>=
0
)
{
path
=
fdt_getprop
(
blob
,
nodeoffset
,
"pci0"
,
NULL
);
if
(
path
)
{
tmp
[
0
]
=
cpu_to_be32
(
pci_hose
[
0
].
first_busno
);
tmp
[
1
]
=
cpu_to_be32
(
pci_hose
[
0
].
last_busno
);
do_fixup_by_path
(
blob
,
path
,
"bus-range"
,
&
tmp
,
sizeof
(
tmp
),
1
);
tmp
[
0
]
=
cpu_to_be32
(
gd
->
pci_clk
);
do_fixup_by_path
(
blob
,
path
,
"clock-frequency"
,
&
tmp
,
sizeof
(
tmp
[
0
]),
1
);
}
#ifdef CONFIG_MPC83XX_PCI2
path
=
fdt_getprop
(
blob
,
nodeoffset
,
"pci1"
,
NULL
);
if
(
path
)
{
tmp
[
0
]
=
cpu_to_be32
(
pci_hose
[
0
].
first_busno
);
tmp
[
1
]
=
cpu_to_be32
(
pci_hose
[
0
].
last_busno
);
do_fixup_by_path
(
blob
,
path
,
"bus-range"
,
&
tmp
,
sizeof
(
tmp
),
1
);
tmp
[
0
]
=
cpu_to_be32
(
gd
->
pci_clk
);
do_fixup_by_path
(
blob
,
path
,
"clock-frequency"
,
&
tmp
,
sizeof
(
tmp
[
0
]),
1
);
}
#endif
}
}
#endif
/* CONFIG_OF_LIBFDT */
#endif
/* CONFIG_PCI */
#endif
/* CONFIG_PCI */
board/mvblm7/Makefile
→
board/m
atrix_vision/m
vblm7/Makefile
浏览文件 @
c5d11e79
文件已移动
board/mvblm7/config.mk
→
board/m
atrix_vision/m
vblm7/config.mk
浏览文件 @
c5d11e79
文件已移动
board/mvblm7/fpga.c
→
board/m
atrix_vision/m
vblm7/fpga.c
浏览文件 @
c5d11e79
文件已移动
board/mvblm7/fpga.h
→
board/m
atrix_vision/m
vblm7/fpga.h
浏览文件 @
c5d11e79
文件已移动
board/mvblm7/mvblm7.c
→
board/m
atrix_vision/m
vblm7/mvblm7.c
浏览文件 @
c5d11e79
文件已移动
board/mvblm7/mvblm7.h
→
board/m
atrix_vision/m
vblm7/mvblm7.h
浏览文件 @
c5d11e79
文件已移动
board/mvblm7/mvblm7_autoscript
→
board/m
atrix_vision/m
vblm7/mvblm7_autoscript
浏览文件 @
c5d11e79
...
@@ -5,11 +5,17 @@ setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
...
@@ -5,11 +5,17 @@ setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
setenv ramkernel setenv kernel_boot \${loadaddr}
setenv ramkernel setenv kernel_boot \${loadaddr}
setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
setenv bootfromflash run flashkernel cpird ramparam bootdtb
setenv bootfromflash run flashkernel cpird ramparam
addcons
bootdtb
setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
if test ${console} = yes;
then
setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8
else
setenv addcons setenv bootargs \${bootargs} console=tty0
fi
setenv set_static_ip setenv ipaddr \${static_ipaddr}
setenv set_static_ip setenv ipaddr \${static_ipaddr}
setenv set_static_nm setenv netmask \${static_netmask}
setenv set_static_nm setenv netmask \${static_netmask}
setenv set_static_gw setenv gatewayip \${static_gateway}
setenv set_static_gw setenv gatewayip \${static_gateway}
...
@@ -24,7 +30,7 @@ then
...
@@ -24,7 +30,7 @@ then
then
then
echo "=== bootp succeeded -> netboot ==="
echo "=== bootp succeeded -> netboot ==="
run set_ip
run set_ip
run getdtb rundtb bootfromnet ramparam bootdtb
run getdtb rundtb bootfromnet ramparam
addcons
bootdtb
else
else
echo "=== netboot failed ==="
echo "=== netboot failed ==="
fi
fi
...
...
board/mvblm7/pci.c
→
board/m
atrix_vision/m
vblm7/pci.c
浏览文件 @
c5d11e79
文件已移动
common/fdt_support.c
浏览文件 @
c5d11e79
...
@@ -408,24 +408,40 @@ void fdt_fixup_ethernet(void *fdt)
...
@@ -408,24 +408,40 @@ void fdt_fixup_ethernet(void *fdt)
void
fdt_fixup_dr_usb
(
void
*
blob
,
bd_t
*
bd
)
void
fdt_fixup_dr_usb
(
void
*
blob
,
bd_t
*
bd
)
{
{
char
*
mode
;
char
*
mode
;
char
*
type
;
const
char
*
compat
=
"fsl-usb2-dr"
;
const
char
*
compat
=
"fsl-usb2-dr"
;
const
char
*
prop
=
"dr_mode"
;
const
char
*
prop_mode
=
"dr_mode"
;
const
char
*
prop_type
=
"phy_type"
;
int
node_offset
;
int
node_offset
;
int
err
;
int
err
;
mode
=
getenv
(
"usb_dr_mode"
);
mode
=
getenv
(
"usb_dr_mode"
);
if
(
!
mode
)
type
=
getenv
(
"usb_phy_type"
);
if
(
!
mode
&&
!
type
)
return
;
return
;
node_offset
=
fdt_node_offset_by_compatible
(
blob
,
0
,
compat
);
node_offset
=
fdt_node_offset_by_compatible
(
blob
,
0
,
compat
);
if
(
node_offset
<
0
)
if
(
node_offset
<
0
)
{
printf
(
"WARNING: could not find compatible node %s: %s.
\n
"
,
printf
(
"WARNING: could not find compatible node %s: %s.
\n
"
,
compat
,
fdt_strerror
(
node_offset
));
compat
,
fdt_strerror
(
node_offset
));
return
;
}
err
=
fdt_setprop
(
blob
,
node_offset
,
prop
,
mode
,
strlen
(
mode
)
+
1
);
if
(
mode
)
{
err
=
fdt_setprop
(
blob
,
node_offset
,
prop_mode
,
mode
,
strlen
(
mode
)
+
1
);
if
(
err
<
0
)
if
(
err
<
0
)
printf
(
"WARNING: could not set %s for %s: %s.
\n
"
,
printf
(
"WARNING: could not set %s for %s: %s.
\n
"
,
prop
,
compat
,
fdt_strerror
(
err
));
prop_mode
,
compat
,
fdt_strerror
(
err
));
}
if
(
type
)
{
err
=
fdt_setprop
(
blob
,
node_offset
,
prop_type
,
type
,
strlen
(
type
)
+
1
);
if
(
err
<
0
)
printf
(
"WARNING: could not set %s for %s: %s.
\n
"
,
prop_type
,
compat
,
fdt_strerror
(
err
));
}
}
}
#endif
/* CONFIG_HAS_FSL_DR_USB */
#endif
/* CONFIG_HAS_FSL_DR_USB */
...
...
cpu/mpc83xx/pci.c
浏览文件 @
c5d11e79
...
@@ -167,6 +167,32 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
...
@@ -167,6 +167,32 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
pci_init_bus
(
i
,
reg
[
i
]);
pci_init_bus
(
i
,
reg
[
i
]);
}
}
#ifdef CONFIG_PCISLAVE
#define PCI_FUNCTION_CONFIG 0x44
#define PCI_FUNCTION_CFG_LOCK 0x20
/*
* Unlock the configuration bit so that the host system can begin booting
*
* This should be used after you have:
* 1) Called mpc83xx_pci_init()
* 2) Set up your inbound translation windows to the appropriate size
*/
void
mpc83xx_pcislave_unlock
(
int
bus
)
{
struct
pci_controller
*
hose
=
&
pci_hose
[
bus
];
u32
dev
;
u16
reg16
;
/* Unlock configuration lock in PCI function configuration register */
dev
=
PCI_BDF
(
hose
->
first_busno
,
0
,
0
);
pci_hose_read_config_word
(
hose
,
dev
,
PCI_FUNCTION_CONFIG
,
&
reg16
);
reg16
&=
~
(
PCI_FUNCTION_CFG_LOCK
);
pci_hose_write_config_word
(
hose
,
dev
,
PCI_FUNCTION_CONFIG
,
reg16
);
}
#endif
#if defined(CONFIG_OF_LIBFDT)
#if defined(CONFIG_OF_LIBFDT)
void
ft_pci_setup
(
void
*
blob
,
bd_t
*
bd
)
void
ft_pci_setup
(
void
*
blob
,
bd_t
*
bd
)
{
{
...
...
include/asm-ppc/immap_83xx.h
浏览文件 @
c5d11e79
...
@@ -61,7 +61,9 @@ typedef struct sysconf83xx {
...
@@ -61,7 +61,9 @@ typedef struct sysconf83xx {
u32
spcr
;
/* System Priority Configuration Register */
u32
spcr
;
/* System Priority Configuration Register */
u32
sicrl
;
/* System I/O Configuration Register Low */
u32
sicrl
;
/* System I/O Configuration Register Low */
u32
sicrh
;
/* System I/O Configuration Register High */
u32
sicrh
;
/* System I/O Configuration Register High */
u8
res6
[
0x0C
];
u8
res6
[
0x04
];
u32
sidcr0
;
/* System I/O Delay Configuration Register 0 */
u32
sidcr1
;
/* System I/O Delay Configuration Register 1 */
u32
ddrcdr
;
/* DDR Control Driver Register */
u32
ddrcdr
;
/* DDR Control Driver Register */
u32
ddrdsr
;
/* DDR Debug Status Register */
u32
ddrdsr
;
/* DDR Debug Status Register */
u32
obir
;
/* Output Buffer Impedance Register */
u32
obir
;
/* Output Buffer Impedance Register */
...
...
include/configs/MPC8315ERDB.h
浏览文件 @
c5d11e79
...
@@ -321,6 +321,8 @@
...
@@ -321,6 +321,8 @@
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_MULTI 1
#endif
#endif
#define CONFIG_HAS_FSL_DR_USB
/*
/*
* TSEC
* TSEC
*/
*/
...
...
include/configs/MPC8349EMDS.h
浏览文件 @
c5d11e79
...
@@ -48,6 +48,11 @@
...
@@ -48,6 +48,11 @@
#define CONFIG_83XX_CLKIN 33000000
/* in Hz */
#define CONFIG_83XX_CLKIN 33000000
/* in Hz */
#endif
#endif
#ifdef CONFIG_PCISLAVE
#define CONFIG_PCI
#define CONFIG_83XX_PCICLK 66666666
/* in Hz */
#endif
/* CONFIG_PCISLAVE */
#ifndef CONFIG_SYS_CLK_FREQ
#ifndef CONFIG_SYS_CLK_FREQ
#ifdef PCI_66M
#ifdef PCI_66M
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_SYS_CLK_FREQ 66000000
...
@@ -406,6 +411,8 @@
...
@@ -406,6 +411,8 @@
#define CONFIG_NET_MULTI
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP
/* do pci plug-and-play */
#define CONFIG_PCI_PNP
/* do pci plug-and-play */
#define CONFIG_83XX_GENERIC_PCI
#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_TULIP
...
@@ -417,7 +424,7 @@
...
@@ -417,7 +424,7 @@
#endif
#endif
#undef CONFIG_PCI_SCAN_SHOW
/* show pci devices on startup */
#undef CONFIG_PCI_SCAN_SHOW
/* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1
057
/* Motorola
*/
#define CFG_PCI_SUBSYS_VENDORID 0x1
957
/* Freescale
*/
#endif
/* CONFIG_PCI */
#endif
/* CONFIG_PCI */
...
@@ -573,6 +580,20 @@
...
@@ -573,6 +580,20 @@
HRCWL_CORE_TO_CSB_1X1)
HRCWL_CORE_TO_CSB_1X1)
#endif
#endif
#ifdef CONFIG_PCISLAVE
#define CFG_HRCW_HIGH (\
HRCWH_PCI_AGENT |\
HRCWH_64_BIT_PCI |\
HRCWH_PCI1_ARBITER_DISABLE |\
HRCWH_PCI2_ARBITER_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII )
#else
#if defined(PCI_64BIT)
#if defined(PCI_64BIT)
#define CFG_HRCW_HIGH (\
#define CFG_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_PCI_HOST |\
...
@@ -599,7 +620,8 @@
...
@@ -599,7 +620,8 @@
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII )
HRCWH_TSEC2M_IN_GMII )
#endif
#endif
/* PCI_64BIT */
#endif
/* CONFIG_PCISLAVE */
/*
/*
* System performance
* System performance
...
...
include/configs/MVBLM7.h
浏览文件 @
c5d11e79
...
@@ -406,22 +406,22 @@
...
@@ -406,22 +406,22 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY 1000
#define CONFIG_RESET_TO_RETRY 1000
#define MV_CI
"mvBL-M7"
#define MV_CI
mvBL-M7
#define MV_VCI
"mvBL-M7"
#define MV_VCI
mvBL-M7
#define MV_FPGA_DATA
"0xfff80000"
#define MV_FPGA_DATA
0xfff80000
#define MV_FPGA_SIZE
"0x76ca2"
#define MV_FPGA_SIZE
0x00076ca2
#define MV_KERNEL_ADDR
"0xff810000"
#define MV_KERNEL_ADDR
0xff810000
#define MV_INITRD_ADDR
"0xffc00000"
#define MV_INITRD_ADDR
0xffb00000
#define MV_AUTOSCR_ADDR
"0xff804000"
#define MV_AUTOSCR_ADDR
0xff804000
#define MV_AUTOSCR_ADDR2
"0xff806000"
#define MV_AUTOSCR_ADDR2
0xff806000
#define MV_DTB_ADDR
"0xff808000"
#define MV_DTB_ADDR
0xff808000
#define MV_INITRD_LENGTH
"0x00300000"
#define MV_INITRD_LENGTH
0x00400000
#define CONFIG_SHOW_BOOT_PROGRESS 1
#define CONFIG_SHOW_BOOT_PROGRESS 1
#define MV_KERNEL_ADDR_RAM
"0x00100000"
#define MV_KERNEL_ADDR_RAM
0x00100000
#define MV_DTB_ADDR_RAM
"0x00600000"
#define MV_DTB_ADDR_RAM
0x00600000
#define MV_INITRD_ADDR_RAM
"0x01000000"
#define MV_INITRD_ADDR_RAM
0x01000000
#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \
#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \
then autoscr ${autoscr_addr}; \
then autoscr ${autoscr_addr}; \
...
@@ -431,25 +431,26 @@
...
@@ -431,25 +431,26 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0" \
"console_nr=0\0" \
"baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
"stdin=serial\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"stderr=serial\0" \
"fpga=0\0" \
"fpga=0\0" \
"fpgadata=" M
V_FPGA_DATA "\0"
\
"fpgadata=" M
K_STR(MV_FPGA_DATA) "\0"
\
"fpgadatasize=" M
V_FPGA_SIZE "\0"
\
"fpgadatasize=" M
K_STR(MV_FPGA_SIZE) "\0"
\
"autoscr_addr=" M
V_AUTOSCR_ADDR "\0"
\
"autoscr_addr=" M
K_STR(MV_AUTOSCR_ADDR) "\0"
\
"autoscr_addr2=" M
V_AUTOSCR_ADDR2 "\0"
\
"autoscr_addr2=" M
K_STR(MV_AUTOSCR_ADDR2) "\0"
\
"mv_kernel_addr=" M
V_KERNEL_ADDR "\0"
\
"mv_kernel_addr=" M
K_STR(MV_KERNEL_ADDR) "\0"
\
"mv_kernel_addr_ram=" M
V_KERNEL_ADDR_RAM "\0"
\
"mv_kernel_addr_ram=" M
K_STR(MV_KERNEL_ADDR_RAM) "\0"
\
"mv_initrd_addr=" M
V_INITRD_ADDR "\0"
\
"mv_initrd_addr=" M
K_STR(MV_INITRD_ADDR) "\0"
\
"mv_initrd_addr_ram=" M
V_INITRD_ADDR_RAM "\0"
\
"mv_initrd_addr_ram=" M
K_STR(MV_INITRD_ADDR_RAM) "\0"
\
"mv_initrd_length=" M
V_INITRD_LENGTH "\0"
\
"mv_initrd_length=" M
K_STR(MV_INITRD_LENGTH) "\0"
\
"mv_dtb_addr=" M
V_DTB_ADDR "\0"
\
"mv_dtb_addr=" M
K_STR(MV_DTB_ADDR) "\0"
\
"mv_dtb_addr_ram=" M
V_DTB_ADDR_RAM "\0"
\
"mv_dtb_addr_ram=" M
K_STR(MV_DTB_ADDR_RAM) "\0"
\
"dtb_name=" M
V_DTB_NAME "\0"
\
"dtb_name=" M
K_STR(MV_DTB_NAME) "\0"
\
"mv_version=" U_BOOT_VERSION "\0" \
"mv_version=" U_BOOT_VERSION "\0" \
"dhcp_client_id=" M
V_CI "\0"
\
"dhcp_client_id=" M
K_STR(MV_CI) "\0"
\
"dhcp_vendor-class-identifier=" M
V_VCI "\0"
\
"dhcp_vendor-class-identifier=" M
K_STR(MV_VCI) "\0"
\
"netretry=no\0" \
"netretry=no\0" \
"use_static_ipaddr=no\0" \
"use_static_ipaddr=no\0" \
"static_ipaddr=192.168.90.10\0" \
"static_ipaddr=192.168.90.10\0" \
...
@@ -470,6 +471,7 @@
...
@@ -470,6 +471,7 @@
"gevss_debug=0\0" \
"gevss_debug=0\0" \
"watchdog=0\0" \
"watchdog=0\0" \
"usb_dr_mode=host\0" \
"usb_dr_mode=host\0" \
"sensor_cnt=2\0" \
""
""
#define CONFIG_FPGA_COUNT 1
#define CONFIG_FPGA_COUNT 1
...
...
include/mpc83xx.h
浏览文件 @
c5d11e79
...
@@ -350,7 +350,9 @@
...
@@ -350,7 +350,9 @@
/* ATR - Arbiter Timers Register
/* ATR - Arbiter Timers Register
*/
*/
#define ATR_DTO 0x00FF0000
/* Data time out */
#define ATR_DTO 0x00FF0000
/* Data time out */
#define ATR_DTO_SHIFT 16
#define ATR_ATO 0x000000FF
/* Address time out */
#define ATR_ATO 0x000000FF
/* Address time out */
#define ATR_ATO_SHIFT 0
/* AER - Arbiter Event Register
/* AER - Arbiter Event Register
*/
*/
...
@@ -364,10 +366,15 @@
...
@@ -364,10 +366,15 @@
/* AEATR - Arbiter Event Address Register
/* AEATR - Arbiter Event Address Register
*/
*/
#define AEATR_EVENT 0x07000000
/* Event type */
#define AEATR_EVENT 0x07000000
/* Event type */
#define AEATR_EVENT_SHIFT 24
#define AEATR_MSTR_ID 0x001F0000
/* Master Id */
#define AEATR_MSTR_ID 0x001F0000
/* Master Id */
#define AEATR_MSTR_ID_SHIFT 16
#define AEATR_TBST 0x00000800
/* Transfer burst */
#define AEATR_TBST 0x00000800
/* Transfer burst */
#define AEATR_TBST_SHIFT 11
#define AEATR_TSIZE 0x00000700
/* Transfer Size */
#define AEATR_TSIZE 0x00000700
/* Transfer Size */
#define AEATR_TSIZE_SHIFT 8
#define AEATR_TTYPE 0x0000001F
/* Transfer Type */
#define AEATR_TTYPE 0x0000001F
/* Transfer Type */
#define AEATR_TTYPE_SHIFT 0
/* HRCWL - Hard Reset Configuration Word Low
/* HRCWL - Hard Reset Configuration Word Low
*/
*/
...
...
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