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体验新版 GitCode,发现更多精彩内容 >>
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c3fafecf
编写于
3月 14, 2005
作者:
W
wdenk
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电子邮件补丁
差异文件
Patch by Detlev Zundel, 14 Mar 2005:
NC650: changed NAND flash addressing to using UPMB
上级
a0bdf49e
变更
3
显示空白变更内容
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并排
Showing
3 changed file
with
51 addition
and
6 deletion
+51
-6
CHANGELOG
CHANGELOG
+6
-3
board/nc650/nc650.c
board/nc650/nc650.c
+36
-0
include/configs/NC650.h
include/configs/NC650.h
+9
-3
未找到文件。
CHANGELOG
浏览文件 @
c3fafecf
...
@@ -2,7 +2,10 @@
...
@@ -2,7 +2,10 @@
Changes for U-Boot 1.1.3:
Changes for U-Boot 1.1.3:
======================================================================
======================================================================
* Patch by Stefan Roese, 14 March 2005:
* Patch by Detlev Zundel, 14 Mar 2005:
NC650: changed NAND flash addressing to using UPMB
* Patch by Stefan Roese, 14 Mar 2005:
Update for esd voh405 fpga image
Update for esd voh405 fpga image
* INKA4x0: Allow initialization of LCD backlight dimming from
* INKA4x0: Allow initialization of LCD backlight dimming from
...
@@ -10,7 +13,7 @@ Changes for U-Boot 1.1.3:
...
@@ -10,7 +13,7 @@ Changes for U-Boot 1.1.3:
* Add port initialization for digital I/O on INKA4x0
* Add port initialization for digital I/O on INKA4x0
* Patch by Stefan Roese, 01 Mar
ch
2005:
* Patch by Stefan Roese, 01 Mar 2005:
Update for esd boards dp405 and hub405
Update for esd boards dp405 and hub405
* Fix get_partition_info() parameter error in all other calls
* Fix get_partition_info() parameter error in all other calls
...
@@ -18,7 +21,7 @@ Changes for U-Boot 1.1.3:
...
@@ -18,7 +21,7 @@ Changes for U-Boot 1.1.3:
* Enable USB and IDE support for INKA4x0 board
* Enable USB and IDE support for INKA4x0 board
* Patch by Andrew Dyer, 28 Feb
ruary
2005:
* Patch by Andrew Dyer, 28 Feb 2005:
fix ext2load passing an incorrect pointer to get_partition_info()
fix ext2load passing an incorrect pointer to get_partition_info()
resulting in load failure for devices other than 0
resulting in load failure for devices other than 0
...
...
board/nc650/nc650.c
浏览文件 @
c3fafecf
...
@@ -70,6 +70,36 @@ const uint sdram_table[] = {
...
@@ -70,6 +70,36 @@ const uint sdram_table[] = {
0x7ffffc07
,
_not_used_
,
_not_used_
,
_not_used_
0x7ffffc07
,
_not_used_
,
_not_used_
,
_not_used_
};
};
const
uint
nand_flash_table
[]
=
{
/* single read. (offset 0 in upm RAM) */
0x0ff3fc04
,
0x0ff3fc04
,
0x0ff3fc04
,
0x0ffffc04
,
0xfffffc00
,
0xfffffc05
,
0xfffffc05
,
0xfffffc05
,
/* burst read. (offset 8 in upm RAM) */
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
/* single write. (offset 18 in upm RAM) */
0x00fffc04
,
0x00fffc04
,
0x00fffc04
,
0x0ffffc04
,
0x0ffffc84
,
0x0ffffc84
,
0xfffffc00
,
0xfffffc05
,
/* burst write. (offset 20 in upm RAM) */
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
/* refresh. (offset 30 in upm RAM) */
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
/* exception. (offset 3c in upm RAM) */
0xffffcc05
,
0xffffcc05
,
0xffffcc05
,
0xffffcc05
};
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
/*
/*
...
@@ -182,6 +212,12 @@ long int initdram (int board_type)
...
@@ -182,6 +212,12 @@ long int initdram (int board_type)
udelay
(
10000
);
udelay
(
10000
);
/* Configure UPMB for NAND flash access */
upmconfig
(
UPMB
,
(
uint
*
)
nand_flash_table
,
sizeof
(
nand_flash_table
)
/
sizeof
(
uint
));
memctl
->
memc_mbmr
=
CFG_MBMR_NAND
;
return
(
size_b0
);
return
(
size_b0
);
}
}
...
...
include/configs/NC650.h
浏览文件 @
c3fafecf
...
@@ -309,7 +309,7 @@
...
@@ -309,7 +309,7 @@
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
/*
/*
* BR2 and OR2 (NAND Flash)
* BR2 and OR2 (NAND Flash)
- now addressed through UPMB
*/
*/
#define CFG_NAND_BASE 0x50000000
#define CFG_NAND_BASE 0x50000000
#define CFG_NAND_SIZE 0x04000000
#define CFG_NAND_SIZE 0x04000000
...
@@ -317,8 +317,8 @@
...
@@ -317,8 +317,8 @@
#define CFG_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
#define CFG_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
#define CFG_BR2_PRELIM ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_
V
)
#define CFG_BR2_PRELIM ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_
MS_UPMB | BR_V
)
#define CFG_OR2_PRELIM (((-CFG_NAND_SIZE) & OR_AM_MSK) |
CFG_OR_TIMING_NAND)
#define CFG_OR2_PRELIM (((-CFG_NAND_SIZE) & OR_AM_MSK) |
OR_BI )
/*
/*
* BR3 and OR3 (SDRAM)
* BR3 and OR3 (SDRAM)
...
@@ -382,6 +382,12 @@
...
@@ -382,6 +382,12 @@
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/*
* MBMR settings for NAND flash
*/
#define CFG_MBMR_NAND ( MBMR_WLFB_5X )
/*
/*
* Internal Definitions
* Internal Definitions
*
*
...
...
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