diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 802cd2efb0fbe4ab05214342def17f6d045bc2f6..c6c8f60c309fce5ab99726fe91d205fe84b4a196 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -215,7 +215,7 @@ static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, if (mode & SPI_CS_HIGH) ss_pol = 1; - if (!(mode & SPI_CPOL)) + if (mode & SPI_CPOL) sclkpol = 1; if (mode & SPI_CPHA) @@ -412,7 +412,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (mode & SPI_CPHA) ctrl_reg |= MXC_CSPICTRL_PHA; - if (!(mode & SPI_CPOL)) + if (mode & SPI_CPOL) ctrl_reg |= MXC_CSPICTRL_POL; if (mode & SPI_CS_HIGH) ctrl_reg |= MXC_CSPICTRL_SSPOL; diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 49048563cb5cd5a9a9475471cc76288c1d761b30..88c62d11e1bf85ce84a04fe5e3db057b0be5ee7c 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -66,13 +66,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index dedecd7fb6a2eee2a2b32d4880eeb522f20885d1..57955dfc3b09ffb6fbd5ea29da66bd27a513f5b7 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -63,13 +63,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 0414cc37a7a94388950b576b9d4ddd47bd20c655..4b4fb1a06a3f7cfc168b695dad7610bf9168125e 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -67,13 +67,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 2 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 86a4731a691a80f1f0e9622fbe2a6d4dd79c5974..8864f3ab780ba2c7b1649383af3dafe00f83586e 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -73,7 +73,7 @@ #define CONFIG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 2500000 -#define CONFIG_FSL_PMIC_MODE (SPI_CPOL | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) /* * MMC Configs diff --git a/include/configs/qong.h b/include/configs/qong.h index 7cd955826df4ded9faff14bb16c502e0299740d2..cbb53dd3d2820b67e35fe3511fe128ffa478d411 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -56,14 +56,14 @@ #define CONFIG_MXC_SPI #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 100000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) /* FPGA */ #define CONFIG_QONG_FPGA 1