From 916d9f099edcb2a020ec3f291f0fa0e6fab0f9a5 Mon Sep 17 00:00:00 2001 From: Yuan Yao Date: Wed, 8 Jun 2016 18:24:52 +0800 Subject: [PATCH] armv8: ls2080aqds: Select QSPI CLK div via SCFG QSPI module output SCLK divisor value is configured through SCFG. Signed-off-by: Yuan Yao Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + board/freescale/ls2080aqds/ls2080aqds.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index c6b9f1336b..f75bd391e3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -140,6 +140,7 @@ /* Supplemental Configuration */ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 +#define SCFG_QSPICLKCTLR 0x10 #define TP_ITYP_AV 0x00000001 /* Initiator available */ #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 897793d85b..b60206b4e4 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -26,6 +26,7 @@ #define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a +#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27) #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) @@ -219,6 +220,10 @@ int board_init(void) int board_early_init_f(void) { fsl_lsch3_early_init_f(); +#ifdef CONFIG_FSL_QSPI + /* input clk: 1/2 platform clk, output: input/20 */ + out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20); +#endif return 0; } -- GitLab