diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 26f1e92ee4a7127be7d2d3075cb468e5a71bc90c..8c137f590cd91e3907686f8d6cf91ab040928e6c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -28,14 +28,16 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5422-odroidxu3.dtb dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rk3036-sdk.dtb \ rk3288-firefly.dtb \ - rk3288-jerry.dtb \ + rk3288-veyron-jerry.dtb \ + rk3288-veyron-mickey.dtb \ + rk3288-veyron-minnie.dtb \ rk3288-rock2-square.dtb \ rk3288-evb.dtb \ rk3288-fennec.dtb \ rk3288-miniarm.dtb \ rk3288-popmetal.dtb \ - rk3036-sdk.dtb \ rk3399-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-odroidc2.dtb diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts index 1c9ddf985610790de2add1ba24d71e9157811fc7..bdc7b980b0dec844165f1acb1ab96adfa7b38b1a 100644 --- a/arch/arm/dts/rk3036-sdk.dts +++ b/arch/arm/dts/rk3036-sdk.dts @@ -16,10 +16,25 @@ stdout-path = &uart2; }; - usb_control { - compatible = "rockchip,rk3036-usb-control"; - host_drv_gpio = <&gpio2 23 GPIO_ACTIVE_LOW>; - otg_drv_gpio = <&gpio0 26 GPIO_ACTIVE_LOW>; + vcc5v0_otg: vcc5v0-otg-drv { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host: vcc5v0-host-drv { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; }; }; @@ -42,3 +57,17 @@ &usb_otg { status = "okay"; }; + +&pinctrl { + usb_otg { + otg_vbus_drv: host-vbus-drv { + rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/dts/rk3288-veyron-chromebook.dtsi index bbbc2f408d632a6d6e3d65ea2903bece8db1ddf3..f88a8680bfa5afdcf06ff3438df94139e155a900 100644 --- a/arch/arm/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/dts/rk3288-veyron-chromebook.dtsi @@ -13,6 +13,8 @@ / { aliases { i2c20 = &i2c_tunnel; + video0 = &vopl; + video1 = &vopb; }; gpio_keys: gpio-keys { diff --git a/arch/arm/dts/rk3288-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts similarity index 92% rename from arch/arm/dts/rk3288-jerry.dts rename to arch/arm/dts/rk3288-veyron-jerry.dts index 2aa3b9f97149a5ae36a4f4381ef027d70d6e8361..8aab607cc527dc1f140cb960e3ebdb65602ece61 100644 --- a/arch/arm/dts/rk3288-jerry.dts +++ b/arch/arm/dts/rk3288-veyron-jerry.dts @@ -55,6 +55,17 @@ }; }; +&dmc { + rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; + &gpio_keys { power { gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; @@ -108,11 +119,6 @@ pinctrl-0 = <&vcc50_hdmi_en>; }; -&vopb { - /* Disable this so that we use vopl */ - status = "disabled"; -}; - &edp { pinctrl-names = "default"; pinctrl-0 = <&edp_hpd>; diff --git a/arch/arm/dts/rk3288-veyron-mickey.dts b/arch/arm/dts/rk3288-veyron-mickey.dts new file mode 100644 index 0000000000000000000000000000000000000000..e0dc3620618bf1afae94ceaf9c075f88b2d3aa46 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-mickey.dts @@ -0,0 +1,277 @@ +/* + * Google Veyron Mickey Rev 0 board device tree source + * + * Copyright 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" + +/ { + model = "Google Mickey"; + compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", + "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", + "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", + "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", + "google,veyron-mickey-rev0", "google,veyron-mickey", + "google,veyron", "rockchip,rk3288"; + + vcc_5v: vcc-5v { + vin-supply = <&vcc33_sys>; + }; + + vcc33_io: vcc33_io { + compatible = "regulator-fixed"; + regulator-name = "vcc33_io"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc33_sys>; + }; +}; + +&cpu_thermal { + /delete-node/ trips; + /delete-node/ cooling-maps; + + trips { + cpu_alert_almost_warm: cpu_alert_almost_warm { + temperature = <63000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_warm: cpu_alert_warm { + temperature = <65000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_almost_hot: cpu_alert_almost_hot { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_hot: cpu_alert_hot { + temperature = <82000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_hotter: cpu_alert_hotter { + temperature = <84000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_very_hot: cpu_alert_very_hot { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* + * After 1st level, throttle the CPU down to as low as 1.4 GHz + * and don't let the GPU go faster than 400 MHz. Note that we + * won't throttle the GPU lower than 400 MHz due to CPU + * heat--we'll let the GPU do the rest itself. + */ + cpu_warm_limit_cpu { + trip = <&cpu_alert_warm>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT 4>; + }; + + /* + * Add some discrete steps to help throttling system deal + * with the fact that there are two passive cooling devices: + * the CPU and the GPU. + * + * - 1.2 GHz - 1.0 GHz (almost hot) + * - 800 MHz (hot) + * - 800 MHz - 696 MHz (hotter) + * - 696 MHz - min (very hot) + * + * Note: + * - 800 MHz appears to be a "sweet spot" for me. I can run + * some pretty serious workload here and be happy. + * - After 696 MHz we stop lowering voltage, so throttling + * past there is less effective. + */ + cpu_almost_hot_limit_cpu { + trip = <&cpu_alert_almost_hot>; + cooling-device = + <&cpu0 5 6>; + }; + cpu_hot_limit_cpu { + trip = <&cpu_alert_hot>; + cooling-device = + <&cpu0 7 7>; + }; + cpu_hotter_limit_cpu { + trip = <&cpu_alert_hotter>; + cooling-device = + <&cpu0 7 8>; + }; + cpu_very_hot_limit_cpu { + trip = <&cpu_alert_very_hot>; + cooling-device = + <&cpu0 8 THERMAL_NO_LIMIT>; + }; + }; +}; + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x2>; + rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>; +}; + +&emmc { + /delete-property/mmc-hs200-1_8v; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c4 { + status = "disabled"; +}; + +&i2s { + status = "okay"; + clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>, + <&gpio7 15 GPIO_ACTIVE_HIGH>; + + /delete-property/ vcc6-supply; + /delete-property/ vcc12-supply; + + vcc11-supply = <&vcc33_sys>; + + regulators { + /* vcc33_io is sourced directly from vcc33_sys */ + /delete-node/ LDO_REG1; + /delete-node/ LDO_REG7; + + /* This is not a pwren anymore, but the real power supply */ + vdd10_lcd: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-suspend-mem-disabled; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-suspend-mem-disabled; + }; + }; +}; + +&pinctrl { + hdmi { + power_hdmi_on: power-hdmi-on { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&sdmmc { + status = "disabled"; +}; + +&sdio0 { + status = "disabled"; +}; + +&sdmmc { + status = "disabled"; +}; + +&spi0 { + status = "disabled"; +}; + +&usb_host0_ehci { + status = "disabled"; +}; + +&usb_host1 { + status = "disabled"; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&power_hdmi_on>; +}; diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts new file mode 100644 index 0000000000000000000000000000000000000000..0a2915fba096f1e8cb9e6bf59670a51a4547abd4 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-minnie.dts @@ -0,0 +1,301 @@ +/* + * Google Veyron Minnie Rev 0+ board device tree source + * + * Copyright 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" + +/ { + model = "Google Minnie"; + compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", + "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", + "google,veyron-minnie-rev0", "google,veyron-minnie", + "google,veyron", "rockchip,rk3288"; + + backlight_regulator: backlight-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwr_en>; + regulator-name = "backlight_regulator"; + vin-supply = <&vcc33_sys>; + startup-delay-us = <15000>; + }; + + panel_regulator: panel-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_h>; + regulator-name = "panel_regulator"; + startup-delay-us = <100000>; + vin-supply = <&vcc33_sys>; + }; + + vcc18_lcd: vcc18-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_1v8_disp_en>; + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc18_wl>; + }; +}; + +&backlight { + /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ + brightness-levels = < + 0 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + power-supply = <&backlight_regulator>; +}; + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x1>; + rockchip,sdram-params = <0x20d266a4 0x5b6 6 533000000 6 13 0>; +}; + +&emmc { + /delete-property/mmc-hs200-1_8v; +}; + +&gpio_keys { + pinctrl-0 = <&pwr_key_h &ap_lid_int_l &volum_down_l &volum_up_l>; + + volum_down { + label = "Volum_down"; + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <100>; + }; + + volum_up { + label = "Volum_up"; + gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <100>; + }; +}; + +&i2c_tunnel { + battery: bq27500@55 { + compatible = "ti,bq27500"; + reg = <0x55>; + }; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&gpio2>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int &touch_rst>; + reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + vcc33-supply = <&vcc33_touch>; + vccio-supply = <&vcc33_touch>; + }; +}; + +&panel { + compatible = "auo,b101ean01", "simple-panel"; + power-supply= <&panel_regulator>; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + + regulators { + vcc33_touch: LDO_REG2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_touch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v_touch: SWITCH_REG2 { + regulator-name = "vcc5v_touch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&sdmmc { + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + &sdmmc_bus4>; +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + volum_down_l: volum-down-l { + rockchip,pins = <5 11 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + volum_up_l: volum-up-l { + rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + prochot { + gpio_prochot: gpio-prochot { + rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touchscreen { + touch_int: touch-int { + rockchip,pins = <2 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_rst: touch-rst { + rockchip,pins = <2 15 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index 2ffe39cbf710331a699232249fbb2a860a071077..a31405875036d471c71b50521a93790c8c9d2b16 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -245,14 +245,6 @@ 533000 1150000 666000 1200000 >; - rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; }; &efuse { diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 8a5d62a73539a078bfc242517b60fb8bebf65560..5c4a4c229176d43bddb9ac103eaa670fbbc707dc 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -21,7 +21,7 @@ config ROCKCHIP_RK3288 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two video interfaces supporting HDMI and eDP, several DDR3 options and video codec support. Peripherals include Gigabit Ethernet, - USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs. + USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. config ROCKCHIP_RK3399 bool "Support Rockchip RK3399" diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 0f40351769e658c18e2934d6f276797cf7764d2d..930939ad24c4bc9a3b97850f3db32959819290ea 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -64,6 +64,10 @@ u32 spl_boot_device(void) } fallback: +#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ + defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ + defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) + return BOOT_DEVICE_SPI; #endif return BOOT_DEVICE_MMC1; } diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index baf9522bcdd87a0ddc5e2bcd144beb83e588c764..bca6075c2c3380c9cd9f118b0b68436c0d18c846 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -56,6 +58,39 @@ int board_late_init(void) return rk_board_late_init(); } +#ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +static int veyron_init(void) +{ + struct udevice *dev; + struct clk clk; + int ret; + + ret = regulator_get_by_platname("vdd_arm", &dev); + if (ret) + return ret; + + /* Slowly raise to max CPU voltage to prevent overshoot */ + ret = regulator_set_value(dev, 1200000); + if (ret) + return ret; + udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ + ret = regulator_set_value(dev, 1400000); + if (ret) + return ret; + udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ + + ret = rockchip_get_clk(&clk.dev); + if (ret) + return ret; + clk.id = PLL_APLL; + ret = clk_set_rate(&clk, 1800000000); + if (IS_ERR_VALUE(ret)) + return ret; + + return 0; +} +#endif + int board_init(void) { #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM @@ -87,6 +122,15 @@ err: return -1; #else + int ret; + + /* We do some SoC one time setting here */ + if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { + ret = veyron_init(); + if (ret) + return ret; + } + return 0; #endif } diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index c53d2e203377a1e2fa812cd572fbbb78c9ec3466..223ae41dd473c3ca9348c3be3ae2d3c49be1451f 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -49,6 +49,25 @@ config TARGET_CHROMEBOOK_JERRY WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions. +config TARGET_CHROMEBIT_MICKEY + bool "Google/Rockchip Veyron-Mickey Chromebit" + help + Mickey is a small RK3288-based device with one USB 3.0 port, HDMI + and WiFi. It has a separate power port and is designed to connect + to the HDMI input of a monitor or TV. It has no internal battery. + Typically a USB hub or wireless keyboard/touchpad is used to get + keyboard and mouse access. + +config TARGET_CHROMEBOOK_MINNIE + bool "Google/Rockchip Veyron-Minnie Chromebook" + help + Jerry is a RK3288-based convertible clamshell device with 2 USB 3.0 + ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card, + HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS + EC (Cortex-M3) to provide access to the keyboard and battery + functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of + internal MMC. The product name is ASUS Chromebook Flip. + config TARGET_ROCK2 bool "Radxa Rock 2" help @@ -88,7 +107,7 @@ source "board/chipspark/popmetal_rk3288/Kconfig" source "board/firefly/firefly-rk3288/Kconfig" -source "board/google/chromebook_jerry/Kconfig" +source "board/google/veyron/Kconfig" source "board/radxa/rock2/Kconfig" diff --git a/board/google/chromebook_jerry/Kconfig b/board/google/chromebook_jerry/Kconfig deleted file mode 100644 index 36405138b5740631266d9ecc2cff4cd6839cfa2e..0000000000000000000000000000000000000000 --- a/board/google/chromebook_jerry/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_CHROMEBOOK_JERRY - -config SYS_BOARD - default "chromebook_jerry" - -config SYS_VENDOR - default "google" - -config SYS_CONFIG_NAME - default "chromebook_jerry" - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - -endif diff --git a/board/google/chromebook_jerry/MAINTAINERS b/board/google/chromebook_jerry/MAINTAINERS deleted file mode 100644 index b01b6cd41949462b0a42000fa9988386a3669bce..0000000000000000000000000000000000000000 --- a/board/google/chromebook_jerry/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CHROMEBOOK JERRY BOARD -M: Simon Glass -S: Maintained -F: board/google/chromebook_jerry/ -F: include/configs/chromebook_jerry.h -F: configs/chromebook_jerry_defconfig diff --git a/board/google/chromebook_jerry/jerry.c b/board/google/chromebook_jerry/jerry.c deleted file mode 100644 index 5119e954550d301a931ef8b393e7a1e95e566d70..0000000000000000000000000000000000000000 --- a/board/google/chromebook_jerry/jerry.c +++ /dev/null @@ -1,7 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..770e9aad2819ee61ed641451b910516f08fc841c --- /dev/null +++ b/board/google/veyron/Kconfig @@ -0,0 +1,47 @@ +if TARGET_CHROMEBOOK_JERRY + +config SYS_BOARD + default "veyron" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "veyron" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif + +if TARGET_CHROMEBIT_MICKEY + +config SYS_BOARD + default "veyron" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "veyron" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif + +if TARGET_CHROMEBOOK_MINNIE + +config SYS_BOARD + default "veyron" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "veyron" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/google/veyron/MAINTAINERS b/board/google/veyron/MAINTAINERS new file mode 100644 index 0000000000000000000000000000000000000000..d582cb00e2b2d1cd01fd4198664ab5e2d73f931d --- /dev/null +++ b/board/google/veyron/MAINTAINERS @@ -0,0 +1,20 @@ +CHROMEBOOK JERRY BOARD +M: Simon Glass +S: Maintained +F: board/google/veyron/ +F: include/configs/veyron.h +F: configs/chromebook_jerry_defconfig + +CHROMEBIT MICKEY BOARD +M: Simon Glass +S: Maintained +F: board/google/veyron/ +F: include/configs/veyron.h +F: configs/chromebit_mickey_defconfig + +CHROMEBIT MINNIE BOARD +M: Simon Glass +S: Maintained +F: board/google/veyron/ +F: include/configs/veyron.h +F: configs/chromebit_minnie_defconfig diff --git a/board/google/chromebook_jerry/Makefile b/board/google/veyron/Makefile similarity index 81% rename from board/google/chromebook_jerry/Makefile rename to board/google/veyron/Makefile index d29a063dcdd16fa73254cd5920d58f5c48480810..98683579dbea9a3d8d17f1d8bd0b4c4fa62c994e 100644 --- a/board/google/chromebook_jerry/Makefile +++ b/board/google/veyron/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += jerry.o +obj-y += veyron.o diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c new file mode 100644 index 0000000000000000000000000000000000000000..20297e1c0f4a07b127f1d417f86be95983a6367a --- /dev/null +++ b/board/google/veyron/veyron.c @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* + * We should increase the DDR voltage to 1.2V using the PWM regulator. + * There is a U-Boot driver for this but it may need to add support for the + * 'voltage-table' property. + */ diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index c6e6cd3e0b29120b0f32ee83ea2e85cbcd21c58d..c437f1be0b328444665ad19d62b36db149ebd786 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -71,5 +71,5 @@ void dram_init_banksize(void) { /* Reserve 0x200000 for ATF bl31 */ gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = 0x80000000; + gd->bd->bi_dram[0].size = 0x7e000000; } diff --git a/cmd/regulator.c b/cmd/regulator.c index bfea6e04b6746dbb5d8efaa26073761ad9d390f9..2ef5bc9a828967f913b3d13a16f62f05342ff839 100644 --- a/cmd/regulator.c +++ b/cmd/regulator.c @@ -292,7 +292,10 @@ static int do_value(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return CMD_RET_FAILURE; } - ret = regulator_set_value(dev, value); + if (!force) + ret = regulator_set_value(dev, value); + else + ret = regulator_set_value_force(dev, value); if (ret) { printf("Regulator: %s - can't set the Voltage!\n", uc_pdata->name); diff --git a/common/stdio.c b/common/stdio.c index 8e4a9beef4542dab055489c31589a0f4c64b3707..4d300175301877c1aeeb438fc67ccb3389fedceb 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -151,9 +151,10 @@ static int stdio_probe_device(const char *name, enum uclass_id id, *sdevp = NULL; seq = trailing_strtoln(name, NULL); if (seq == -1) + seq = 0; + ret = uclass_get_device_by_seq(id, seq, &dev); + if (ret == -ENODEV) ret = uclass_first_device_err(id, &dev); - else - ret = uclass_get_device_by_seq(id, seq, &dev); if (ret) { debug("No %s device for seq %d (%s)\n", uclass_get_name(id), seq, name); @@ -173,12 +174,12 @@ static int stdio_probe_device(const char *name, enum uclass_id id, } #endif -struct stdio_dev* stdio_get_by_name(const char *name) +struct stdio_dev *stdio_get_by_name(const char *name) { struct list_head *pos; struct stdio_dev *sdev; - if(!name) + if (!name) return NULL; list_for_each(pos, &(devs.list)) { diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..b1189075d9d695e510427cbbf6f2b2d73d5f1cba --- /dev/null +++ b/configs/chromebit_mickey_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_ROCKCHIP_RK3288=y +CONFIG_TARGET_CHROMEBIT_MICKEY=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DM_KEYBOARD=y +CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CMD_CROS_EC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_ROCKCHIP_DWMMC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_ROCKCHIP_RK3288_PINCTRL=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_RK808=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK808=y +CONFIG_DM_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_ROCKCHIP_SERIAL=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y +CONFIG_SPL_OF_PLATDATA=y +# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 876adc46715858043ccea17c6ab64b1a242e6ce5..46df1a66251176c57cea27ccaea95b1741511d8b 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -1,16 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_MMC_SUPPORT is not set -CONFIG_SPL_POWER_SUPPORT=y CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_CHROMEBOOK_JERRY=y -CONFIG_ROCKCHIP_FAST_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x80000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry" +CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry" CONFIG_SILENT_CONSOLE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y @@ -36,7 +33,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -71,6 +68,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y +CONFIG_ROCKCHIP_SERIAL=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_DM_VIDEO=y @@ -80,3 +78,5 @@ CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y +CONFIG_SPL_OF_PLATDATA=y +# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..6aced140e2f06dadcfe8966da8ff9fe1e9e533c4 --- /dev/null +++ b/configs/chromebook_minnie_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_ROCKCHIP_RK3288=y +CONFIG_TARGET_CHROMEBOOK_MINNIE=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie" +CONFIG_SILENT_CONSOLE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEYBOARD=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_ROCKCHIP_DWMMC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_ROCKCHIP_RK3288_PINCTRL=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_RK808=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK808=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_ROCKCHIP_SERIAL=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_CONSOLE_SCROLL_LINES=10 +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y +CONFIG_SPL_OF_PLATDATA=y +# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index e3edeb7517d2589b20f92a682c854543ff25c98d..40a8295417873b58c18d6e247aad153e7dc46dcd 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -24,6 +24,7 @@ CONFIG_ROCKCHIP_DWMMC=y CONFIG_ROCKCHIP_SDHCI=y CONFIG_PINCTRL=y CONFIG_ROCKCHIP_RK3399_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 424cdab5693afdc71b612662548970d48d7eb2bb..631d1f5498ec86b500b5d0bb01f8ea2b87fe224a 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -32,7 +32,11 @@ CONFIG_LED=y CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y CONFIG_ROCKCHIP_RK3036_PINCTRL=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y CONFIG_SYSRESET=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index ed97e87a959bfbdc936d438e7dd3d9c2336389e5..d15504c3aaebda86250b56233d7871a8249bc061 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -691,6 +691,13 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); switch (clk->id) { + case PLL_APLL: + /* We only support a fixed rate here */ + if (rate != 1800000000) + return -EINVAL; + rk3288_clk_configure_cpu(priv->cru, priv->grf); + new_rate = rate; + break; case CLK_DDR: new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); break; diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 2576c2cd3d96bf9304b910c342c68c77ab88eed6..94c0b0063d1a833b30557fcb0f35ed53d9496f66 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -1138,7 +1138,7 @@ int spi_flash_scan(struct spi_flash *flash) return ret; #endif -#if CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ret = spi_flash_decode_fdt(gd->fdt_blob, flash); if (ret) { debug("SF: FDT decode error\n"); diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 4434e36312ac9f9f322bcf364b523e82494290ac..52a107036325e2fb31d150e7fd3890d3f72432df 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -39,6 +39,27 @@ int regulator_get_value(struct udevice *dev) } int regulator_set_value(struct udevice *dev, int uV) +{ + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + if (uc_pdata->min_uV != -ENODATA && uV < uc_pdata->min_uV) + return -EINVAL; + if (uc_pdata->max_uV != -ENODATA && uV > uc_pdata->max_uV) + return -EINVAL; + + if (!ops || !ops->set_value) + return -ENOSYS; + + return ops->set_value(dev, uV); +} + +/* + * To be called with at most caution as there is no check + * before setting the actual voltage value. + */ +int regulator_set_value_force(struct udevice *dev, int uV) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); @@ -61,6 +82,13 @@ int regulator_get_current(struct udevice *dev) int regulator_set_current(struct udevice *dev, int uA) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + if (uc_pdata->min_uA != -ENODATA && uA < uc_pdata->min_uA) + return -EINVAL; + if (uc_pdata->max_uA != -ENODATA && uA > uc_pdata->max_uA) + return -EINVAL; if (!ops || !ops->set_current) return -ENOSYS; diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 105ee4a3ba59882c29f353c137316a5e027d1539..15cf0bda202a72b7257e27a5eff97bdd8250485f 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +28,9 @@ DECLARE_GLOBAL_DATA_PTR; #define DEBUG_RK_SPI 0 struct rockchip_spi_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3288_spi of_plat; +#endif s32 frequency; /* Default clock frequency, -1 for none */ fdt_addr_t base; uint deactivate_delay_us; /* Delay to wait after deactivate */ @@ -106,6 +110,14 @@ static void spi_cs_activate(struct udevice *dev, uint cs) struct rockchip_spi_priv *priv = dev_get_priv(bus); struct rockchip_spi *regs = priv->regs; + /* If it's too soon to do another transaction, wait */ + if (plat->deactivate_delay_us && priv->last_transaction_us) { + ulong delay_us; /* The delay completed so far */ + delay_us = timer_get_us() - priv->last_transaction_us; + if (delay_us < plat->deactivate_delay_us) + udelay(plat->deactivate_delay_us - delay_us); + } + debug("activate cs%u\n", cs); writel(1 << cs, ®s->ser); if (plat->activate_delay_us) @@ -127,9 +139,29 @@ static void spi_cs_deactivate(struct udevice *dev, uint cs) priv->last_transaction_us = timer_get_us(); } +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_platdata(struct udevice *dev) +{ + struct rockchip_spi_platdata *plat = dev->platdata; + struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat; + struct rockchip_spi_priv *priv = dev_get_priv(dev); + int ret; + + plat->base = dtplat->reg[0]; + plat->frequency = 20000000; + ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); + if (ret < 0) + return ret; + dev->req_seq = 0; + + return 0; +} +#endif + static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) { - struct rockchip_spi_platdata *plat = bus->platdata; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rockchip_spi_platdata *plat = dev_get_platdata(bus); struct rockchip_spi_priv *priv = dev_get_priv(bus); const void *blob = gd->fdt_blob; int node = bus->of_offset; @@ -153,6 +185,7 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", __func__, (uint)plat->base, plat->frequency, plat->deactivate_delay_us); +#endif return 0; } @@ -164,6 +197,11 @@ static int rockchip_spi_probe(struct udevice *bus) int ret; debug("%s: probe\n", __func__); +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = conv_of_platdata(bus); + if (ret) + return ret; +#endif priv->regs = (struct rockchip_spi *)plat->base; priv->last_transaction_us = timer_get_us(); @@ -369,7 +407,11 @@ static const struct udevice_id rockchip_spi_ids[] = { }; U_BOOT_DRIVER(rockchip_spi) = { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + .name = "rockchip_rk3288_spi", +#else .name = "rockchip_spi", +#endif .id = UCLASS_SPI, .of_match = rockchip_spi_ids, .ops = &rockchip_spi_ops, diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index d9c49e4e8c208a5f8474427726c53a89871cf976..f59a70173c41ace0b05c6ae805657f26c11bb496 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -108,6 +108,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, return dm_spi_xfer(slave->dev, bitlen, dout, din, flags); } +#if !CONFIG_IS_ENABLED(OF_PLATDATA) static int spi_child_post_bind(struct udevice *dev) { struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); @@ -117,14 +118,16 @@ static int spi_child_post_bind(struct udevice *dev) return spi_slave_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat); } +#endif static int spi_post_probe(struct udevice *bus) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct dm_spi_bus *spi = dev_get_uclass_priv(bus); spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset, "spi-max-frequency", 0); - +#endif #if defined(CONFIG_NEEDS_MANUAL_RELOC) struct dm_spi_ops *ops = spi_get_ops(bus); @@ -274,7 +277,11 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, bool created = false; int ret; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = uclass_first_device_err(UCLASS_SPI, &bus); +#else ret = uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus); +#endif if (ret) { printf("Invalid bus %d (err=%d)\n", busnum, ret); return ret; @@ -290,8 +297,11 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, debug("%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n", __func__, dev_name, busnum, cs, drv_name); ret = device_bind_driver(bus, drv_name, dev_name, &dev); - if (ret) + if (ret) { + debug("%s: Unable to bind driver (ret=%d)\n", __func__, + ret); return ret; + } plat = dev_get_parent_platdata(dev); plat->cs = cs; plat->max_hz = speed; @@ -436,14 +446,18 @@ UCLASS_DRIVER(spi) = { .id = UCLASS_SPI, .name = "spi", .flags = DM_UC_FLAG_SEQ_ALIAS, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) .post_bind = dm_scan_fdt_dev, +#endif .post_probe = spi_post_probe, .child_pre_probe = spi_child_pre_probe, .per_device_auto_alloc_size = sizeof(struct dm_spi_bus), .per_child_auto_alloc_size = sizeof(struct spi_slave), .per_child_platdata_auto_alloc_size = sizeof(struct dm_spi_slave_platdata), +#if !CONFIG_IS_ENABLED(OF_PLATDATA) .child_post_bind = spi_child_post_bind, +#endif }; UCLASS_DRIVER(spi_generic) = { diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c index e4763de73df5e312ee810eeda9edb8d066176bd9..e752eb07c4d6ea761c455a3acf80024a293766ba 100644 --- a/drivers/video/display-uclass.c +++ b/drivers/video/display-uclass.c @@ -23,10 +23,19 @@ int display_enable(struct udevice *dev, int panel_bpp, const struct display_timing *timing) { struct dm_display_ops *ops = display_get_ops(dev); + struct display_plat *disp_uc_plat; + int ret; if (!ops || !ops->enable) return -ENOSYS; - return ops->enable(dev, panel_bpp, timing); + ret = ops->enable(dev, panel_bpp, timing); + if (ret) + return ret; + + disp_uc_plat = dev_get_uclass_platdata(dev); + disp_uc_plat->in_use = true; + + return 0; } int display_read_timing(struct udevice *dev, struct display_timing *timing) @@ -48,6 +57,13 @@ int display_read_timing(struct udevice *dev, struct display_timing *timing) return edid_get_timing(buf, ret, timing, &panel_bits_per_colour); } +bool display_in_use(struct udevice *dev) +{ + struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev); + + return disp_uc_plat->in_use; +} + UCLASS_DRIVER(display) = { .id = UCLASS_DISPLAY, .name = "display", diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index 7976c5e26376985633dca22ece6f7f47df5ae47b..032b1de103d8cd9a09868d7cc96b9c3c0038e777 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -132,8 +132,8 @@ static const u32 csc_coeff_default[3][4] = { static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, u32 cts) { - u8 cts3; - u8 n3; + uint cts3; + uint n3; /* first set ncts_atomic_write (if present) */ n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE; @@ -199,7 +199,7 @@ static void hdmi_audio_set_samplerate(struct rk3288_hdmi *regs, u32 pixel_clk) static void hdmi_video_sample(struct rk3288_hdmi *regs) { u32 color_format = 0x01; - u8 val; + uint val; val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & @@ -256,7 +256,7 @@ static void hdmi_video_packetize(struct rk3288_hdmi *regs) u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT; u32 color_depth = 0; - u8 val, vp_conf; + uint val, vp_conf; /* set the packetizer registers */ val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & @@ -297,7 +297,7 @@ static void hdmi_video_packetize(struct rk3288_hdmi *regs) output_select); } -static inline void hdmi_phy_test_clear(struct rk3288_hdmi *regs, u8 bit) +static inline void hdmi_phy_test_clear(struct rk3288_hdmi *regs, uint bit) { clrsetbits_le32(®s->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK, bit << HDMI_PHY_TST0_TSTCLR_OFFSET); @@ -382,7 +382,7 @@ static void hdmi_phy_sel_interface_control(struct rk3288_hdmi *regs, static int hdmi_phy_configure(struct rk3288_hdmi *regs, u32 mpixelclock) { ulong start; - u8 i, val; + uint i, val; writel(HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, ®s->mc_flowctrl); @@ -481,8 +481,8 @@ static int hdmi_phy_init(struct rk3288_hdmi *regs, uint mpixelclock) static void hdmi_av_composer(struct rk3288_hdmi *regs, const struct display_timing *edid) { - u8 mdataenablepolarity = 1; - u8 inv_val; + bool mdataenablepolarity = true; + uint inv_val; uint hbl; uint vbl; @@ -553,7 +553,7 @@ static void hdmi_av_composer(struct rk3288_hdmi *regs, /* hdmi initialization step b.4 */ static void hdmi_enable_video_path(struct rk3288_hdmi *regs) { - u8 clkdis; + uint clkdis; /* control period minimum duration */ writel(12, ®s->fc_ctrldur); @@ -580,7 +580,7 @@ static void hdmi_enable_video_path(struct rk3288_hdmi *regs) /* workaround to clear the overflow condition */ static void hdmi_clear_overflow(struct rk3288_hdmi *regs) { - u8 val, count; + uint val, count; /* tmds software reset */ writel((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, ®s->mc_swrstz); @@ -614,7 +614,7 @@ static void hdmi_audio_fifo_reset(struct rk3288_hdmi *regs) static void hdmi_init_interrupt(struct rk3288_hdmi *regs) { - u8 ih_mute; + uint ih_mute; /* * boot up defaults are: @@ -650,11 +650,11 @@ static void hdmi_init_interrupt(struct rk3288_hdmi *regs) writel(HDMI_IH_PHY_STAT0_HPD, ®s->ih_phy_stat0); } -static u8 hdmi_get_plug_in_status(struct rk3288_hdmi *regs) +static int hdmi_get_plug_in_status(struct rk3288_hdmi *regs) { - u8 val = readl(®s->phy_stat0) & HDMI_PHY_HPD; + uint val = readl(®s->phy_stat0) & HDMI_PHY_HPD; - return !!(val); + return !!val; } static int hdmi_wait_for_hpd(struct rk3288_hdmi *regs) @@ -753,7 +753,7 @@ static int hdmi_read_edid(struct rk3288_hdmi *regs, int block, u8 *buff) return edid_read_err; } -static u8 pre_buf[] = { +static const u8 pre_buf[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00, 0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78, @@ -899,7 +899,8 @@ static int rk_hdmi_probe(struct udevice *dev) rk_setreg(&priv->grf->soc_con6, 1 << 15); /* hdmi data from vop id */ - rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 4) : (1 << 4)); + rk_clrsetreg(&priv->grf->soc_con6, 1 << 4, + (vop_id == 1) ? (1 << 4) : 0); ret = hdmi_wait_for_hpd(priv->regs); if (ret < 0) { diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index c6d88d9225d7c9fa66cf46208b7eb85e01b09d50..eab548699f74e1830966ebf08fa799c18a04c82f 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -195,7 +195,6 @@ int rk_display_init(struct udevice *dev, ulong fbbase, struct udevice *disp; int ret, remote, i, offset; struct display_plat *disp_uc_plat; - struct udevice *dev_clk; struct clk clk; vop_id = fdtdec_get_int(blob, ep_node, "reg", -1); @@ -222,6 +221,11 @@ int rk_display_init(struct udevice *dev, ulong fbbase, disp_uc_plat = dev_get_uclass_platdata(disp); debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat); + if (display_in_use(disp)) { + debug(" - device in use\n"); + return -EBUSY; + } + disp_uc_plat->source_id = remote_vop_id; disp_uc_plat->src_dev = dev; @@ -238,11 +242,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase, return ret; } - ret = rockchip_get_clk(&dev_clk); - if (!ret) { - clk.id = DCLK_VOP0 + remote_vop_id; - ret = clk_request(dev_clk, &clk); - } + ret = clk_get_by_index(dev, 1, &clk); if (!ret) ret = clk_set_rate(&clk, timing.pixelclock.typ); if (ret) { @@ -316,6 +316,10 @@ static int rk_vop_probe(struct udevice *dev) /* * Try all the ports until we find one that works. In practice this * tries EDP first if available, then HDMI. + * + * Note that rockchip_vop_set_clk() always uses NPLL as the source + * clock so it is currently not possible to use more than one display + * device simultaneously. */ port = fdt_subnode_offset(blob, dev->of_offset, "port"); if (port < 0) diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 11ca7937dc817ed8c40c392182aa8bd38d4f5b8f..3036e3a1f25f054617bbf5852f762268bf72027e 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -117,7 +117,8 @@ void video_sync(struct udevice *vid) if (priv->flush_dcache) { flush_dcache_range((ulong)priv->fb, - (ulong)priv->fb + priv->fb_size); + ALIGN((ulong)priv->fb + priv->fb_size, + CONFIG_SYS_CACHELINE_SIZE)); } #elif defined(CONFIG_VIDEO_SANDBOX_SDL) struct video_priv *priv = dev_get_uclass_priv(vid); diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 4eef3f8cc6e8ac11eb03e05a9dd4ced960208840..92be29e7bbaa8696b66e37b65a78103ccb064be7 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -79,6 +79,13 @@ #define CONFIG_G_DNL_VENDOR_NUM 0x2207 #define CONFIG_G_DNL_PRODUCT_NUM 0x310a +/* usb host */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX +#endif #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "pxefile_addr_r=0x60100000\0" \ diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 7ca1696a1630ad288d5f1ecc3fe1233be99015ef..9ec71c4baaae588c23410ea04b398ffe992be82c 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -27,7 +27,7 @@ "name=reserved2,size=4M,uuid=${uuid_gpt_reserved2};" \ "name=loader2,size=4MB,uuid=${uuid_gpt_loader2};" \ "name=atf,size=4M,uuid=${uuid_gpt_atf};" \ - "name=boot,size=128M,bootable,uuid=${uuid_gpt_boot};" \ + "name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \ "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \ #endif diff --git a/include/configs/chromebook_jerry.h b/include/configs/veyron.h similarity index 100% rename from include/configs/chromebook_jerry.h rename to include/configs/veyron.h diff --git a/include/display.h b/include/display.h index b1c476628b4f9aa0cb882e435f0535a681a92df3..d0a08d4aaa8f6e35b0891c776eeec161a95d5354 100644 --- a/include/display.h +++ b/include/display.h @@ -16,10 +16,12 @@ struct display_timing; * @source_id: ID for the source of the display data, typically a video * controller * @src_dev: Source device providing the video + * @in_use: Display is being used */ struct display_plat { int source_id; struct udevice *src_dev; + bool in_use; }; /** @@ -41,6 +43,14 @@ int display_read_timing(struct udevice *dev, struct display_timing *timing); int display_enable(struct udevice *dev, int panel_bpp, const struct display_timing *timing); +/** + * display_in_use() - Check if a display is in use by any device + * + * @return true if the device is in use (display_enable() has been called + * successfully), else false + */ +bool display_in_use(struct udevice *dev); + struct dm_display_ops { /** * read_timing() - Read information directly diff --git a/include/power/regulator.h b/include/power/regulator.h index f47ab6740bdd6951056184b755831efe956d6ea6..1a8e5753d789f1cd786b0ad7e5564334bca460d4 100644 --- a/include/power/regulator.h +++ b/include/power/regulator.h @@ -260,6 +260,16 @@ int regulator_get_value(struct udevice *dev); */ int regulator_set_value(struct udevice *dev, int uV); +/** + * regulator_set_value_force: set the microvoltage value of a given regulator + * without any min-,max condition check + * + * @dev - pointer to the regulator device + * @uV - the output value to set [micro Volts] + * @return - 0 on success or -errno val if fails + */ +int regulator_set_value_force(struct udevice *dev, int uV); + /** * regulator_get_current: get microampere value of a given regulator *