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体验新版 GitCode,发现更多精彩内容 >>
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87e06627
编写于
3月 16, 2007
作者:
W
Wolfgang Denk
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差异文件
Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx
上级
a7090b99
8423e5e3
变更
3
显示空白变更内容
内联
并排
Showing
3 changed file
with
28 addition
and
65 deletion
+28
-65
board/amcc/ebony/init.S
board/amcc/ebony/init.S
+19
-58
include/configs/PCI405.h
include/configs/PCI405.h
+6
-5
include/configs/ebony.h
include/configs/ebony.h
+3
-2
未找到文件。
board/amcc/ebony/init.S
浏览文件 @
87e06627
...
...
@@ -22,53 +22,7 @@
#include <ppc_asm.tmpl>
#include <config.h>
/*
General
*/
#define TLB_VALID 0x00000200
/*
Supported
page
sizes
*/
#define SZ_1K 0x00000000
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
/*
Storage
attributes
*/
#define SA_W 0x00000800 /* Write-through */
#define SA_I 0x00000400 /* Caching inhibited */
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
/*
Access
control
*/
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
/*
Some
handy
macros
*/
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
#define TLB2(a) ( (a)&0x00000fbf )
#define tlbtab_start\
mflr
r1
;\
bl
0
f
;
#define tlbtab_end\
.
long
0
,
0
,
0
; \
0
:
mflr
r0
; \
mtlr
r1
; \
blr
;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.
long
TLB0
(
epn
,
sz
),
TLB1
(
rpn
,
erpn
),
TLB2
(
attr
)
#include <asm-ppc/mmu.h>
/**************************************************************************
*
TLB
TABLE
...
...
@@ -86,11 +40,18 @@
tlbtab
:
tlbtab_start
tlbentry
(
0xf0000000
,
SZ_256M
,
0xf0000000
,
1
,
AC_R|AC_W|AC_X|SA_G|SA_I
)
tlbentry
(
CFG_PERIPHERAL_BASE
,
SZ_256M
,
0x40000000
,
1
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_ISRAM_BASE
,
SZ_4K
,
0x80000000
,
0
,
AC_R|AC_W|AC_X
)
tlbentry
(
CFG_ISRAM_BASE
+
0x1000
,
SZ_4K
,
0x80001000
,
0
,
AC_R|AC_W|AC_X
)
tlbentry
(
CFG_SDRAM_BASE
,
SZ_256M
,
0x00000000
,
0
,
AC_R|AC_W|AC_X|SA_G|SA_I
)
tlbentry
(
CFG_PCI_BASE
,
SZ_256M
,
0x00000000
,
2
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCI_MEMBASE
,
SZ_256M
,
0x00000000
,
3
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(0
xf0000000
,
SZ_256M
,
0xf0000000
,
1
,
AC_R|AC_W|AC_X|SA_G|SA_I
)
/
*
*
TLB
entries
for
SDRAM
are
not
needed
on
this
platform
.
*
They
are
dynamically
generated
in
the
SPD
DDR
(
2
)
detection
*
routine
.
*/
tlbentry
(
CFG_PERIPHERAL_BASE
,
SZ_256M
,
0x40000000
,
1
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_ISRAM_BASE
,
SZ_4K
,
0x80000000
,
0
,
AC_R|AC_W|AC_X
)
tlbentry
(
CFG_ISRAM_BASE
+
0x1000
,
SZ_4K
,
0x80001000
,
0
,
AC_R|AC_W|AC_X
)
tlbentry
(
CFG_PCI_BASE
,
SZ_256M
,
0x00000000
,
2
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbentry
(
CFG_PCI_MEMBASE
,
SZ_256M
,
0x00000000
,
3
,
AC_R|AC_W|SA_G
|
SA_I
)
tlbtab_end
include/configs/PCI405.h
浏览文件 @
87e06627
/*
* (C) Copyright 2007
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
*
* (C) Copyright 2001-2004
* Stefan Roese,
esd gmbh germany, stefan.roese@esd-electronics.com
* Stefan Roese,
DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
...
...
@@ -32,8 +35,6 @@
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_IDENT_STRING " $Name: esd_PCI405_05_07_28 $"
#define CONFIG_405GP 1
/* This is a PPC405 CPU */
#define CONFIG_4xx 1
/* ...member of PPC4xx family */
#define CONFIG_PCI405 1
/* ...on a PCI405 board */
...
...
@@ -53,9 +54,9 @@
"mem_linux=14336k\0" \
"optargs=panic=0\0" \
"ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \
"addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
"addcon
s
=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
""
#define CONFIG_BOOTCOMMAND "run ramargs;run addcon;loadpci"
#define CONFIG_BOOTCOMMAND "run ramargs;run addcon
s
;loadpci"
#define CONFIG_PREBOOT
/* enable preboot variable */
...
...
include/configs/ebony.h
浏览文件 @
87e06627
...
...
@@ -133,8 +133,9 @@
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM
/* Use SPD EEPROM for setup
*/
#define CONFIG_SPD_EEPROM
1
/* Use SPD EEPROM for setup
*/
#define SPD_EEPROM_ADDRESS {0x53,0x52}
/* SPD i2c spd addresses */
#define CONFIG_PROG_SDRAM_TLB 1
/* setup SDRAM TLB's dynamically*/
/*-----------------------------------------------------------------------
* I2C
...
...
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