diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
index 27be1cc21eb1c9310c083dde3e9906848b65a5ae..ef1941e5a6b36a8cb302733c77fb99ae33d3121d 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
@@ -9,8 +9,7 @@
 
 #include "ddrphy-regs.h"
 
-int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
-			bool ddr3plus)
+int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus)
 {
 	u32 tmp;
 
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h
index a466118258ee433457374851e1eb54b084ed258a..87f6d0d3a25fb5a4a6c64c4a44777b8ef47b7ac2 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-regs.h
+++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h
@@ -170,8 +170,7 @@ struct ddrphy {
 #define DDRPHY_BASE(ch, phy)	(0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
 
 #ifndef __ASSEMBLY__
-int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
-			bool ddr3plus);
+int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus);
 void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
 int ddrphy_training(struct ddrphy __iomem *phy);
 #endif
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
index 957a38fec44f83dbdfae3432ede8d72e373036a2..bee3ef4bff6b1b60fb65636a02e7d1fb0aa451a8 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
@@ -113,14 +113,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
 
 	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 
-	ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus);
+	ph1_ld4_ddrphy_init(phy0_0, freq, ddr3plus);
 
 	ddrphy_prepare_training(phy0_0, 0);
 	ddrphy_training(phy0_0);
 
 	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 
-	ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus);
+	ph1_ld4_ddrphy_init(phy1_0, freq, ddr3plus);
 
 	ddrphy_prepare_training(phy1_0, 1);
 	ddrphy_training(phy1_0);
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
index 877f5ef9cc617cc8f72d56bd02d17c23748ed7e3..0a2485e6ae780924607c7ba3d76d08fdc988bf97 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
@@ -138,32 +138,28 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
 
 	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 
-	ph1_ld4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size,
-			    bd->dram_ddr3plus);
+	ph1_ld4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ddr3plus);
 
 	ddrphy_prepare_training(phy0_0, 0);
 	ddrphy_training(phy0_0);
 
 	writel(0x00000103, dramcont0 + UMC_DIOCTLA);
 
-	ph1_ld4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size,
-			    bd->dram_ddr3plus);
+	ph1_ld4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ddr3plus);
 
 	ddrphy_prepare_training(phy0_1, 1);
 	ddrphy_training(phy0_1);
 
 	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 
-	ph1_ld4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size,
-			    bd->dram_ddr3plus);
+	ph1_ld4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ddr3plus);
 
 	ddrphy_prepare_training(phy1_0, 0);
 	ddrphy_training(phy1_0);
 
 	writel(0x00000103, dramcont1 + UMC_DIOCTLA);
 
-	ph1_ld4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size,
-			    bd->dram_ddr3plus);
+	ph1_ld4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ddr3plus);
 
 	ddrphy_prepare_training(phy1_1, 1);
 	ddrphy_training(phy1_1);
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
index a27f91f895b46495cb6dde2d89d674f312b7b5df..73ad934cffc23eb3e17efc583b28fe015f0ac683 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
@@ -97,14 +97,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
 
 	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 
-	ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus);
+	ph1_ld4_ddrphy_init(phy0_0, freq, ddr3plus);
 
 	ddrphy_prepare_training(phy0_0, 0);
 	ddrphy_training(phy0_0);
 
 	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 
-	ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus);
+	ph1_ld4_ddrphy_init(phy1_0, freq, ddr3plus);
 
 	ddrphy_prepare_training(phy1_0, 1);
 	ddrphy_training(phy1_0);