Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
OS
U-Boot.Mirror
提交
6a1f7e54
U
U-Boot.Mirror
项目概览
OS
/
U-Boot.Mirror
通知
1
Star
0
Fork
0
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
U
U-Boot.Mirror
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
6a1f7e54
编写于
4月 08, 2010
作者:
W
Wolfgang Denk
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'master' of
git://git.denx.de/u-boot-arm
上级
d8bc0a28
b5045cdd
变更
22
显示空白变更内容
内联
并排
Showing
22 changed file
with
463 addition
and
90 deletion
+463
-90
MAINTAINERS
MAINTAINERS
+18
-11
board/armltd/integrator/integrator.c
board/armltd/integrator/integrator.c
+0
-2
board/samsung/smdkc100/smdkc100.c
board/samsung/smdkc100/smdkc100.c
+39
-0
cpu/arm1176/cpu.c
cpu/arm1176/cpu.c
+2
-0
cpu/arm1176/start.S
cpu/arm1176/start.S
+4
-0
cpu/arm920t/ep93xx/timer.c
cpu/arm920t/ep93xx/timer.c
+29
-33
cpu/arm926ejs/at91/clock.c
cpu/arm926ejs/at91/clock.c
+2
-1
cpu/arm926ejs/nomadik/timer.c
cpu/arm926ejs/nomadik/timer.c
+12
-3
cpu/arm_cortexa8/s5pc1xx/Makefile
cpu/arm_cortexa8/s5pc1xx/Makefile
+2
-0
cpu/arm_cortexa8/s5pc1xx/clock.c
cpu/arm_cortexa8/s5pc1xx/clock.c
+1
-6
cpu/arm_cortexa8/s5pc1xx/gpio.c
cpu/arm_cortexa8/s5pc1xx/gpio.c
+143
-0
cpu/arm_cortexa8/s5pc1xx/sromc.c
cpu/arm_cortexa8/s5pc1xx/sromc.c
+53
-0
doc/README.s5pc1xx
doc/README.s5pc1xx
+17
-1
drivers/usb/host/ohci-at91.c
drivers/usb/host/ohci-at91.c
+13
-15
drivers/watchdog/at91sam9_wdt.c
drivers/watchdog/at91sam9_wdt.c
+11
-10
include/asm-arm/arch-at91/at91_pmc.h
include/asm-arm/arch-at91/at91_pmc.h
+18
-5
include/asm-arm/arch-s5pc1xx/clk.h
include/asm-arm/arch-s5pc1xx/clk.h
+6
-0
include/asm-arm/arch-s5pc1xx/gpio.h
include/asm-arm/arch-s5pc1xx/gpio.h
+29
-0
include/asm-arm/arch-s5pc1xx/smc.h
include/asm-arm/arch-s5pc1xx/smc.h
+53
-0
include/configs/meesc.h
include/configs/meesc.h
+0
-1
include/configs/otc570.h
include/configs/otc570.h
+0
-1
include/configs/smdkc100.h
include/configs/smdkc100.h
+11
-1
未找到文件。
MAINTAINERS
浏览文件 @
6a1f7e54
...
@@ -616,6 +616,10 @@ Simon Kagstrom <simon.kagstrom@netinsight.net>
...
@@ -616,6 +616,10 @@ Simon Kagstrom <simon.kagstrom@netinsight.net>
openrd_base ARM926EJS (Kirkwood SoC)
openrd_base ARM926EJS (Kirkwood SoC)
Minkyu Kang <mk7.kang@samsung.com>
SMDKC100 ARM CORTEX-A8 (S5PC100 SoC)
Nishant Kamat <nskamat@ti.com>
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
omap1610h2 ARM926EJS
...
@@ -630,17 +634,17 @@ Sergey Kubushyn <ksi@koi8.net>
...
@@ -630,17 +634,17 @@ Sergey Kubushyn <ksi@koi8.net>
SONATA ARM926EJS
SONATA ARM926EJS
SCHMOOGIE ARM926EJS
SCHMOOGIE ARM926EJS
Sandeep Paulraj <s-paulraj@ti.com>
davinci_dm355evm ARM926EJS
davinci_dm355leopard ARM926EJS
davinci_dm365evm ARM926EJS
davinci_dm6467evm ARM926EJS
Prakash Kumar <prakash@embedx.com>
Prakash Kumar <prakash@embedx.com>
cerf250 xscale
cerf250 xscale
Vipin Kumar <vipin.kumar@st.com>
spear300 ARM926EJS (spear300 Soc)
spear310 ARM926EJS (spear310 Soc)
spear320 ARM926EJS (spear320 Soc)
spear600 ARM926EJS (spear600 Soc)
Sergey Lapin <slapin@ossfans.org>
Sergey Lapin <slapin@ossfans.org>
afeb9260 ARM926EJS (AT91SAM9260 SoC)
afeb9260 ARM926EJS (AT91SAM9260 SoC)
...
@@ -673,6 +677,13 @@ Kyungmin Park <kyungmin.park@samsung.com>
...
@@ -673,6 +677,13 @@ Kyungmin Park <kyungmin.park@samsung.com>
apollon ARM1136EJS
apollon ARM1136EJS
Sandeep Paulraj <s-paulraj@ti.com>
davinci_dm355evm ARM926EJS
davinci_dm355leopard ARM926EJS
davinci_dm365evm ARM926EJS
davinci_dm6467evm ARM926EJS
Peter Pearse <peter.pearse@arm.com>
Peter Pearse <peter.pearse@arm.com>
integratorcp All current ARM supplied & supported core modules
integratorcp All current ARM supplied & supported core modules
-see http://www.arm.com/products/DevTools/Hardware_Platforms.html
-see http://www.arm.com/products/DevTools/Hardware_Platforms.html
...
@@ -773,10 +784,6 @@ Alex Z
...
@@ -773,10 +784,6 @@ Alex Z
lart SA1100
lart SA1100
dnp1110 SA1110
dnp1110 SA1110
Minkyu Kang <mk7.kang@samsung.com>
SMDKC100 ARM CORTEX-A8 (S5PC100 SoC)
-------------------------------------------------------------------------
-------------------------------------------------------------------------
Unknown / orphaned boards:
Unknown / orphaned boards:
...
...
board/armltd/integrator/integrator.c
浏览文件 @
6a1f7e54
...
@@ -132,9 +132,7 @@ int board_eth_init(bd_t *bis)
...
@@ -132,9 +132,7 @@ int board_eth_init(bd_t *bis)
#ifdef CONFIG_SMC91111
#ifdef CONFIG_SMC91111
rc
=
smc91111_initialize
(
0
,
CONFIG_SMC91111_BASE
);
rc
=
smc91111_initialize
(
0
,
CONFIG_SMC91111_BASE
);
#endif
#endif
#ifdef CONFIG_PCI
rc
+=
pci_eth_init
(
bis
);
rc
+=
pci_eth_init
(
bis
);
#endif
return
rc
;
return
rc
;
}
}
#endif
#endif
board/samsung/smdkc100/smdkc100.c
浏览文件 @
6a1f7e54
...
@@ -23,10 +23,40 @@
...
@@ -23,10 +23,40 @@
*/
*/
#include <common.h>
#include <common.h>
#include <asm/io.h>
#include <asm/arch/smc.h>
#include <asm/arch/gpio.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR
;
DECLARE_GLOBAL_DATA_PTR
;
/*
* Miscellaneous platform dependent initialisations
*/
static
void
smc9115_pre_init
(
void
)
{
u32
smc_bw_conf
,
smc_bc_conf
;
struct
s5pc100_gpio
*
const
gpio
=
(
struct
s5pc100_gpio
*
)
S5PC100_GPIO_BASE
;
/* gpio configuration GPK0CON */
gpio_cfg_pin
(
&
gpio
->
gpio_k0
,
CONFIG_ENV_SROM_BANK
,
GPIO_FUNC
(
2
));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf
=
SMC_DATA16_WIDTH
(
CONFIG_ENV_SROM_BANK
);
smc_bc_conf
=
SMC_BC_TACS
(
0x0
)
|
SMC_BC_TCOS
(
0x4
)
|
SMC_BC_TACC
(
0xe
)
|
SMC_BC_TCOH
(
0x1
)
|
SMC_BC_TAH
(
0x4
)
|
SMC_BC_TACP
(
0x6
)
|
SMC_BC_PMC
(
0x0
);
/* Select and configure the SROMC bank */
s5pc1xx_config_sromc
(
CONFIG_ENV_SROM_BANK
,
smc_bw_conf
,
smc_bc_conf
);
}
int
board_init
(
void
)
int
board_init
(
void
)
{
{
smc9115_pre_init
();
gd
->
bd
->
bi_arch_number
=
MACH_TYPE_SMDKC100
;
gd
->
bd
->
bi_arch_number
=
MACH_TYPE_SMDKC100
;
gd
->
bd
->
bi_boot_params
=
PHYS_SDRAM_1
+
0x100
;
gd
->
bd
->
bi_boot_params
=
PHYS_SDRAM_1
+
0x100
;
...
@@ -49,3 +79,12 @@ int checkboard(void)
...
@@ -49,3 +79,12 @@ int checkboard(void)
return
0
;
return
0
;
}
}
#endif
#endif
int
board_eth_init
(
bd_t
*
bis
)
{
int
rc
=
0
;
#ifdef CONFIG_SMC911X
rc
=
smc911x_initialize
(
0
,
CONFIG_SMC911X_BASE
);
#endif
return
rc
;
}
cpu/arm1176/cpu.c
浏览文件 @
6a1f7e54
...
@@ -33,7 +33,9 @@
...
@@ -33,7 +33,9 @@
#include <common.h>
#include <common.h>
#include <command.h>
#include <command.h>
#ifdef CONFIG_S3C64XX
#include <asm/arch/s3c6400.h>
#include <asm/arch/s3c6400.h>
#endif
#include <asm/system.h>
#include <asm/system.h>
static
void
cache_flush
(
void
);
static
void
cache_flush
(
void
);
...
...
cpu/arm1176/start.S
浏览文件 @
6a1f7e54
...
@@ -35,7 +35,9 @@
...
@@ -35,7 +35,9 @@
#ifdef CONFIG_ENABLE_MMU
#ifdef CONFIG_ENABLE_MMU
#include <asm/proc/domain.h>
#include <asm/proc/domain.h>
#endif
#endif
#ifdef CONFIG_S3C64XX
#include <asm/arch/s3c6400.h>
#include <asm/arch/s3c6400.h>
#endif
#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
...
@@ -190,10 +192,12 @@ mmu_disable:
...
@@ -190,10 +192,12 @@ mmu_disable:
#endif
#endif
mmu_disable_phys
:
mmu_disable_phys
:
#ifdef CONFIG_S3C64XX
/
*
Peri
port
setup
*/
/
*
Peri
port
setup
*/
ldr
r0
,
=
0x70000000
ldr
r0
,
=
0x70000000
orr
r0
,
r0
,
#
0x13
orr
r0
,
r0
,
#
0x13
mcr
p15
,
0
,
r0
,
c15
,
c2
,
4
@
256
M
(
0x70000000
-
0x7fffffff
)
mcr
p15
,
0
,
r0
,
c15
,
c2
,
4
@
256
M
(
0x70000000
-
0x7fffffff
)
#endif
/
*
/
*
*
Go
setup
Memory
and
board
specific
bits
prior
to
relocation
.
*
Go
setup
Memory
and
board
specific
bits
prior
to
relocation
.
...
...
cpu/arm920t/ep93xx/timer.c
浏览文件 @
6a1f7e54
/*
/*
* Cirrus Logic EP93xx timer support.
* Cirrus Logic EP93xx timer support.
*
*
* Copyright (C) 2009, 2010
* Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
* Matthias Kaehlcke <matthias@kaehlcke.net>
*
*
* Copyright (C) 2004, 2005
* Copyright (C) 2004, 2005
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
...
@@ -42,17 +41,9 @@
...
@@ -42,17 +41,9 @@
static
struct
ep93xx_timer
static
struct
ep93xx_timer
{
{
unsigned
long
long
ticks
;
unsigned
long
long
ticks
;
unsigned
long
last_
update
;
unsigned
long
last_
read
;
}
timer
;
}
timer
;
static
inline
unsigned
long
clk_to_systicks
(
unsigned
long
long
clk_ticks
)
{
unsigned
long
long
sys_ticks
=
(
clk_ticks
*
CONFIG_SYS_HZ
);
do_div
(
sys_ticks
,
TIMER_FREQ
);
return
(
unsigned
long
)
sys_ticks
;
}
static
inline
unsigned
long
long
usecs_to_ticks
(
unsigned
long
usecs
)
static
inline
unsigned
long
long
usecs_to_ticks
(
unsigned
long
usecs
)
{
{
unsigned
long
long
ticks
=
(
unsigned
long
long
)
usecs
*
TIMER_FREQ
;
unsigned
long
long
ticks
=
(
unsigned
long
long
)
usecs
*
TIMER_FREQ
;
...
@@ -61,11 +52,18 @@ static inline unsigned long long usecs_to_ticks(unsigned long usecs)
...
@@ -61,11 +52,18 @@ static inline unsigned long long usecs_to_ticks(unsigned long usecs)
return
ticks
;
return
ticks
;
}
}
static
inline
unsigned
long
read_timer
(
void
)
static
inline
void
read_timer
(
void
)
{
{
struct
timer_regs
*
timer
=
(
struct
timer_regs
*
)
TIMER_BASE
;
struct
timer_regs
*
timer_regs
=
(
struct
timer_regs
*
)
TIMER_BASE
;
const
unsigned
long
now
=
TIMER_MAX_VAL
-
readl
(
&
timer_regs
->
timer3
.
value
);
if
(
now
>=
timer
.
last_read
)
timer
.
ticks
+=
now
-
timer
.
last_read
;
else
/* an overflow occurred */
timer
.
ticks
+=
TIMER_MAX_VAL
-
timer
.
last_read
+
now
;
return
TIMER_MAX_VAL
-
readl
(
&
timer
->
timer3
.
value
)
;
timer
.
last_read
=
now
;
}
}
/*
/*
...
@@ -73,17 +71,14 @@ static inline unsigned long read_timer(void)
...
@@ -73,17 +71,14 @@ static inline unsigned long read_timer(void)
*/
*/
unsigned
long
long
get_ticks
(
void
)
unsigned
long
long
get_ticks
(
void
)
{
{
const
unsigned
long
now
=
read_timer
()
;
unsigned
long
long
sys_ticks
;
if
(
now
>=
timer
.
last_update
)
read_timer
();
timer
.
ticks
+=
now
-
timer
.
last_update
;
else
/* an overflow occurred */
timer
.
ticks
+=
TIMER_MAX_VAL
-
timer
.
last_update
+
now
;
timer
.
last_update
=
now
;
sys_ticks
=
timer
.
ticks
*
CONFIG_SYS_HZ
;
do_div
(
sys_ticks
,
TIMER_FREQ
);
return
clk_to_systicks
(
timer
.
ticks
)
;
return
sys_ticks
;
}
}
unsigned
long
get_timer_masked
(
void
)
unsigned
long
get_timer_masked
(
void
)
...
@@ -98,7 +93,7 @@ unsigned long get_timer(unsigned long base)
...
@@ -98,7 +93,7 @@ unsigned long get_timer(unsigned long base)
void
reset_timer_masked
(
void
)
void
reset_timer_masked
(
void
)
{
{
timer
.
last_update
=
read_timer
();
read_timer
();
timer
.
ticks
=
0
;
timer
.
ticks
=
0
;
}
}
...
@@ -109,28 +104,29 @@ void reset_timer(void)
...
@@ -109,28 +104,29 @@ void reset_timer(void)
void
__udelay
(
unsigned
long
usec
)
void
__udelay
(
unsigned
long
usec
)
{
{
/* read the timer and update timer.ticks */
unsigned
long
long
target
;
get_ticks
();
read_timer
();
const
unsigned
long
long
target
=
timer
.
ticks
+
usecs_to_ticks
(
usec
);
target
=
timer
.
ticks
+
usecs_to_ticks
(
usec
);
while
(
timer
.
ticks
<
target
)
while
(
timer
.
ticks
<
target
)
get_ticks
();
read_timer
();
}
}
int
timer_init
(
void
)
int
timer_init
(
void
)
{
{
struct
timer_regs
*
timer
=
(
struct
timer_regs
*
)
TIMER_BASE
;
struct
timer_regs
*
timer
_regs
=
(
struct
timer_regs
*
)
TIMER_BASE
;
/* use timer 3 with 508KHz and free running */
/* use timer 3 with 508KHz and free running
, not enabled now
*/
writel
(
TIMER_CLKSEL
,
&
timer
->
timer3
.
control
);
writel
(
TIMER_CLKSEL
,
&
timer
_regs
->
timer3
.
control
);
/* set initial timer value
3
*/
/* set initial timer value */
writel
(
TIMER_MAX_VAL
,
&
timer
->
timer3
.
load
);
writel
(
TIMER_MAX_VAL
,
&
timer
_regs
->
timer3
.
load
);
/* Enable the timer */
/* Enable the timer */
writel
(
TIMER_ENABLE
|
TIMER_CLKSEL
,
writel
(
TIMER_ENABLE
|
TIMER_CLKSEL
,
&
timer
->
timer3
.
control
);
&
timer
_regs
->
timer3
.
control
);
reset_timer_masked
();
reset_timer_masked
();
...
...
cpu/arm926ejs/at91/clock.c
浏览文件 @
6a1f7e54
...
@@ -203,7 +203,8 @@ int at91_clock_init(unsigned long main_clock)
...
@@ -203,7 +203,8 @@ int at91_clock_init(unsigned long main_clock)
if
(
mckr
&
AT91_PMC_MCKR_MDIV_MASK
)
if
(
mckr
&
AT91_PMC_MCKR_MDIV_MASK
)
freq
/=
2
;
/* processor clock division */
freq
/=
2
;
/* processor clock division */
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
mck_rate_hz
=
(
mckr
&
AT91_PMC_MCKR_MDIV_MASK
)
==
AT91SAM9_PMC_MDIV_3
mck_rate_hz
=
(
mckr
&
AT91_PMC_MCKR_MDIV_MASK
)
==
(
AT91_PMC_MCKR_MDIV_2
|
AT91_PMC_MCKR_MDIV_4
)
?
freq
/
3
?
freq
/
3
:
freq
/
(
1
<<
((
mckr
&
AT91_PMC_MCKR_MDIV_MASK
)
>>
8
));
:
freq
/
(
1
<<
((
mckr
&
AT91_PMC_MCKR_MDIV_MASK
)
>>
8
));
#else
#else
...
...
cpu/arm926ejs/nomadik/timer.c
浏览文件 @
6a1f7e54
...
@@ -34,8 +34,8 @@
...
@@ -34,8 +34,8 @@
#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
/* macro to read the
32 bit timer: since it decrements, we invert read value
*/
/* macro to read the
decrementing 32 bit timer as an increasing count
*/
#define READ_TIMER() (
~
readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
#define READ_TIMER() (
0 -
readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
/* Configure a free-running, auto-wrap counter with no prescaler */
/* Configure a free-running, auto-wrap counter with no prescaler */
int
timer_init
(
void
)
int
timer_init
(
void
)
...
@@ -49,7 +49,16 @@ int timer_init(void)
...
@@ -49,7 +49,16 @@ int timer_init(void)
/* Restart counting from 0 */
/* Restart counting from 0 */
void
reset_timer
(
void
)
void
reset_timer
(
void
)
{
{
writel
(
0
,
CONFIG_SYS_TIMERBASE
+
MTU_LR
(
0
));
/* Immediate effect */
ulong
val
;
writel
(
0
,
CONFIG_SYS_TIMERBASE
+
MTU_LR
(
0
));
/*
* The load-register isn't really immediate: it changes on clock
* edges, so we must wait for our newly-written value to appear.
* Since we might miss reading 0, wait for any change in value.
*/
val
=
READ_TIMER
();
while
(
READ_TIMER
()
==
val
)
;
}
}
/* Return how many HZ passed since "base" */
/* Return how many HZ passed since "base" */
...
...
cpu/arm_cortexa8/s5pc1xx/Makefile
浏览文件 @
6a1f7e54
...
@@ -33,6 +33,8 @@ SOBJS += reset.o
...
@@ -33,6 +33,8 @@ SOBJS += reset.o
COBJS
+=
clock.o
COBJS
+=
clock.o
COBJS
+=
cpu_info.o
COBJS
+=
cpu_info.o
COBJS
+=
gpio.o
COBJS
+=
sromc.o
COBJS
+=
timer.o
COBJS
+=
timer.o
SRCS
:=
$(SOBJS:.o=.S)
$(COBJS:.o=.c)
SRCS
:=
$(SOBJS:.o=.S)
$(COBJS:.o=.c)
...
...
cpu/arm_cortexa8/s5pc1xx/clock.c
浏览文件 @
6a1f7e54
...
@@ -25,12 +25,7 @@
...
@@ -25,12 +25,7 @@
#include <common.h>
#include <common.h>
#include <asm/io.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
#define APLL 0
#define MPLL 1
#define EPLL 2
#define HPLL 3
#define VPLL 4
#define CLK_M 0
#define CLK_M 0
#define CLK_D 1
#define CLK_D 1
...
...
cpu/arm_cortexa8/s5pc1xx/gpio.c
0 → 100644
浏览文件 @
6a1f7e54
/*
* (C) Copyright 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#define CON_MASK(x) (0xf << ((x) << 2))
#define CON_SFR(x, v) ((v) << ((x) << 2))
#define DAT_MASK(x) (0x1 << (x))
#define DAT_SET(x) (0x1 << (x))
#define PULL_MASK(x) (0x3 << ((x) << 1))
#define PULL_MODE(x, v) ((v) << ((x) << 1))
#define DRV_MASK(x) (0x3 << ((x) << 1))
#define DRV_SET(x, m) ((m) << ((x) << 1))
#define RATE_MASK(x) (0x1 << (x + 16))
#define RATE_SET(x) (0x1 << (x + 16))
void
gpio_cfg_pin
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
,
int
cfg
)
{
unsigned
int
value
;
value
=
readl
(
&
bank
->
con
);
value
&=
~
CON_MASK
(
gpio
);
value
|=
CON_SFR
(
gpio
,
cfg
);
writel
(
value
,
&
bank
->
con
);
}
void
gpio_direction_output
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
,
int
en
)
{
unsigned
int
value
;
gpio_cfg_pin
(
bank
,
gpio
,
GPIO_OUTPUT
);
value
=
readl
(
&
bank
->
dat
);
value
&=
~
DAT_MASK
(
gpio
);
if
(
en
)
value
|=
DAT_SET
(
gpio
);
writel
(
value
,
&
bank
->
dat
);
}
void
gpio_direction_input
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
)
{
gpio_cfg_pin
(
bank
,
gpio
,
GPIO_INPUT
);
}
void
gpio_set_value
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
,
int
en
)
{
unsigned
int
value
;
value
=
readl
(
&
bank
->
dat
);
value
&=
~
DAT_MASK
(
gpio
);
if
(
en
)
value
|=
DAT_SET
(
gpio
);
writel
(
value
,
&
bank
->
dat
);
}
unsigned
int
gpio_get_value
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
)
{
unsigned
int
value
;
value
=
readl
(
&
bank
->
dat
);
return
!!
(
value
&
DAT_MASK
(
gpio
));
}
void
gpio_set_pull
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
,
int
mode
)
{
unsigned
int
value
;
value
=
readl
(
&
bank
->
pull
);
value
&=
~
PULL_MASK
(
gpio
);
switch
(
mode
)
{
case
GPIO_PULL_DOWN
:
case
GPIO_PULL_UP
:
value
|=
PULL_MODE
(
gpio
,
mode
);
break
;
default:
return
;
}
writel
(
value
,
&
bank
->
pull
);
}
void
gpio_set_drv
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
,
int
mode
)
{
unsigned
int
value
;
value
=
readl
(
&
bank
->
drv
);
value
&=
~
DRV_MASK
(
gpio
);
switch
(
mode
)
{
case
GPIO_DRV_1X
:
case
GPIO_DRV_2X
:
case
GPIO_DRV_3X
:
case
GPIO_DRV_4X
:
value
|=
DRV_SET
(
gpio
,
mode
);
break
;
default:
return
;
}
writel
(
value
,
&
bank
->
drv
);
}
void
gpio_set_rate
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
,
int
mode
)
{
unsigned
int
value
;
value
=
readl
(
&
bank
->
drv
);
value
&=
~
RATE_MASK
(
gpio
);
switch
(
mode
)
{
case
GPIO_DRV_FAST
:
case
GPIO_DRV_SLOW
:
value
|=
RATE_SET
(
gpio
);
break
;
default:
return
;
}
writel
(
value
,
&
bank
->
drv
);
}
cpu/arm_cortexa8/s5pc1xx/sromc.c
0 → 100644
浏览文件 @
6a1f7e54
/*
* Copyright (C) 2010 Samsung Electronics
* Naveen Krishna Ch <ch.naveen@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/smc.h>
/*
* s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the
* band width control and bank control registers
* srom_bank - SROM Bank 0 to 5
* smc_bw_conf - SMC Band witdh reg configuration value
* smc_bc_conf - SMC Bank Control reg configuration value
*/
void
s5pc1xx_config_sromc
(
u32
srom_bank
,
u32
smc_bw_conf
,
u32
smc_bc_conf
)
{
u32
tmp
;
struct
s5pc1xx_smc
*
srom
;
if
(
cpu_is_s5pc100
())
srom
=
(
struct
s5pc1xx_smc
*
)
S5PC100_SROMC_BASE
;
else
srom
=
(
struct
s5pc1xx_smc
*
)
S5PC110_SROMC_BASE
;
/* Configure SMC_BW register to handle proper SROMC bank */
tmp
=
srom
->
bw
;
tmp
&=
~
(
0xF
<<
(
srom_bank
*
4
));
tmp
|=
smc_bw_conf
;
srom
->
bw
=
tmp
;
/* Configure SMC_BC register */
srom
->
bc
[
srom_bank
]
=
smc_bc_conf
;
}
doc/README.s5pc1xx
浏览文件 @
6a1f7e54
...
@@ -41,7 +41,23 @@ To check SoC:
...
@@ -41,7 +41,23 @@ To check SoC:
printf("cpu is s5pc110\n");
printf("cpu is s5pc110\n");
gpio
gpio
not supported yet.
struct s5pc100_gpio *gpio = (struct s5pc100_gpio*)S5PC100_GPIO_BASE;
/* GPA[0] pin set to irq */
gpio_cfg_pin(&gpio->gpio_a, 0, GPIO_IRQ);
/* GPA[0] pin set to input */
gpio_direction_input(&gpio->gpio_a, 0);
/* GPA[0] pin set to output/high */
gpio_direction_output(&gpio->gpio_a, 0, 1);
/* GPA[0] value set to low */
gpio_set_value(&gpio->gpio_a, 0, 0);
/* get GPA[0] value */
value = gpio_get_value(&gpio->gpio_a, 0);
Links
Links
=====
=====
...
...
drivers/usb/host/ohci-at91.c
浏览文件 @
6a1f7e54
...
@@ -25,11 +25,6 @@
...
@@ -25,11 +25,6 @@
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
#ifndef CONFIG_AT91_LEGACY
#define CONFIG_AT91_LEGACY
#warning Please update to use C structur SoC access !
#endif
#include <asm/arch/hardware.h>
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
#include <asm/arch/io.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pmc.h>
...
@@ -37,22 +32,23 @@
...
@@ -37,22 +32,23 @@
int
usb_cpu_init
(
void
)
int
usb_cpu_init
(
void
)
{
{
at91_pmc_t
*
pmc
=
(
at91_pmc_t
*
)
AT91_PMC_BASE
;
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
defined(CONFIG_AT91SAM9261)
defined(CONFIG_AT91SAM9261)
/* Enable PLLB */
/* Enable PLLB */
at91_sys_write
(
AT91_CKGR_PLLBR
,
get_pllb_init
()
);
writel
(
get_pllb_init
(),
&
pmc
->
pllbr
);
while
((
at91_sys_read
(
AT91_PMC_SR
)
&
AT91_PMC_LOCKB
)
!=
AT91_PMC_LOCKB
)
while
((
readl
(
&
pmc
->
sr
)
&
AT91_PMC_LOCKB
)
!=
AT91_PMC_LOCKB
)
;
;
#endif
#endif
/* Enable USB host clock. */
/* Enable USB host clock. */
at91_sys_write
(
AT91_PMC_PCER
,
1
<<
AT91_ID_UHP
);
writel
(
1
<<
AT91_ID_UHP
,
&
pmc
->
pcer
);
#ifdef CONFIG_AT91SAM9261
#ifdef CONFIG_AT91SAM9261
at91_sys_write
(
AT91_PMC_SCER
,
AT91_PMC_UHP
|
AT91_PMC_HCK0
);
writel
(
AT91_PMC_UHP
|
AT91_PMC_HCK0
,
&
pmc
->
scer
);
#else
#else
at91_sys_write
(
AT91_PMC_SCER
,
AT91_PMC_UHP
);
writel
(
AT91_PMC_UHP
,
&
pmc
->
scer
);
#endif
#endif
return
0
;
return
0
;
...
@@ -60,19 +56,21 @@ int usb_cpu_init(void)
...
@@ -60,19 +56,21 @@ int usb_cpu_init(void)
int
usb_cpu_stop
(
void
)
int
usb_cpu_stop
(
void
)
{
{
at91_pmc_t
*
pmc
=
(
at91_pmc_t
*
)
AT91_PMC_BASE
;
/* Disable USB host clock. */
/* Disable USB host clock. */
at91_sys_write
(
AT91_PMC_PCDR
,
1
<<
AT91_ID_UHP
);
writel
(
1
<<
AT91_ID_UHP
,
&
pmc
->
pcdr
);
#ifdef CONFIG_AT91SAM9261
#ifdef CONFIG_AT91SAM9261
at91_sys_write
(
AT91_PMC_SCDR
,
AT91_PMC_UHP
|
AT91_PMC_HCK0
);
writel
(
AT91_PMC_UHP
|
AT91_PMC_HCK0
,
&
pmc
->
scdr
);
#else
#else
at91_sys_write
(
AT91_PMC_SCDR
,
AT91_PMC_UHP
);
writel
(
AT91_PMC_UHP
,
&
pmc
->
scdr
);
#endif
#endif
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20)
defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20)
/* Disable PLLB */
/* Disable PLLB */
at91_sys_write
(
AT91_CKGR_PLLBR
,
0
);
writel
(
0
,
&
pmc
->
pllbr
);
while
((
at91_sys_read
(
AT91_PMC_SR
)
&
AT91_PMC_LOCKB
)
!=
0
)
while
((
readl
(
&
pmc
->
sr
)
&
AT91_PMC_LOCKB
)
!=
0
)
;
;
#endif
#endif
...
...
drivers/watchdog/at91sam9_wdt.c
浏览文件 @
6a1f7e54
...
@@ -42,11 +42,10 @@
...
@@ -42,11 +42,10 @@
static
int
at91_wdt_settimeout
(
unsigned
int
timeout
)
static
int
at91_wdt_settimeout
(
unsigned
int
timeout
)
{
{
unsigned
int
reg
;
unsigned
int
reg
;
unsigned
int
mr
;
at91_wdt_t
*
wd
=
(
at91_wdt_t
*
)
AT91_WDT_BASE
;
/* Check if disabled */
/* Check if disabled */
mr
=
at91_sys_read
(
AT91_WDT_MR
);
if
(
readl
(
&
wd
->
mr
)
&
AT91_WDT_MR_WDDIS
)
{
if
(
mr
&
AT91_WDT_WDDIS
)
{
printf
(
"sorry, watchdog is disabled
\n
"
);
printf
(
"sorry, watchdog is disabled
\n
"
);
return
-
1
;
return
-
1
;
}
}
...
@@ -57,19 +56,21 @@ static int at91_wdt_settimeout(unsigned int timeout)
...
@@ -57,19 +56,21 @@ static int at91_wdt_settimeout(unsigned int timeout)
* Since WDV is a 12-bit counter, the maximum period is
* Since WDV is a 12-bit counter, the maximum period is
* 4096 / 256 = 16 seconds.
* 4096 / 256 = 16 seconds.
*/
*/
reg
=
AT91_WDT_WDRSTEN
/* causes watchdog reset */
/* | AT91_WDT_WDRPROC causes processor reset only */
reg
=
AT91_WDT_MR_WDRSTEN
/* causes watchdog reset */
|
AT91_WDT_WDDBGHLT
/* disabled in debug mode */
|
AT91_WDT_MR_WDDBGHLT
/* disabled in debug mode */
|
AT91_WDT_WDD
/* restart at any time */
|
AT91_WDT_MR_WDD
(
0xfff
)
/* restart at any time */
|
(
timeout
&
AT91_WDT_WDV
);
/* timer value */
|
AT91_WDT_MR_WDV
(
timeout
);
/* timer value */
at91_sys_write
(
AT91_WDT_MR
,
reg
);
writel
(
reg
,
&
wd
->
mr
);
return
0
;
return
0
;
}
}
void
hw_watchdog_reset
(
void
)
void
hw_watchdog_reset
(
void
)
{
{
at91_sys_write
(
AT91_WDT_CR
,
AT91_WDT_KEY
|
AT91_WDT_WDRSTT
);
at91_wdt_t
*
wd
=
(
at91_wdt_t
*
)
AT91_WDT_BASE
;
writel
(
AT91_WDT_CR_WDRSTT
|
AT91_WDT_CR_KEY
,
&
wd
->
cr
);
}
}
void
hw_watchdog_init
(
void
)
void
hw_watchdog_init
(
void
)
...
...
include/asm-arm/arch-at91/at91_pmc.h
浏览文件 @
6a1f7e54
...
@@ -108,11 +108,12 @@ typedef struct at91_pmc {
...
@@ -108,11 +108,12 @@ typedef struct at91_pmc {
#define AT91_PMC_IXR_PCKRDY3 0x00000800
#define AT91_PMC_IXR_PCKRDY3 0x00000800
#ifdef CONFIG_AT91_LEGACY
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_SCER (AT91_PMC + 0x00)
/* System Clock Enable Register */
#define AT91_PMC_SCER (AT91_PMC + 0x00)
/* System Clock Enable Register */
#define AT91_PMC_SCDR (AT91_PMC + 0x04)
/* System Clock Disable Register */
#define AT91_PMC_SCDR (AT91_PMC + 0x04)
/* System Clock Disable Register */
#define AT91_PMC_SCSR (AT91_PMC + 0x08)
/* System Clock Status Register */
#define AT91_PMC_SCSR (AT91_PMC + 0x08)
/* System Clock Status Register */
#endif
#define AT91_PMC_PCK (1 << 0)
/* Processor Clock */
#define AT91_PMC_PCK (1 << 0)
/* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1)
/* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_UDP (1 << 1)
/* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2)
/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2)
/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
...
@@ -128,27 +129,34 @@ typedef struct at91_pmc {
...
@@ -128,27 +129,34 @@ typedef struct at91_pmc {
#define AT91_PMC_HCK0 (1 << 16)
/* AHB Clock (USB host) [AT91SAM9261 only] */
#define AT91_PMC_HCK0 (1 << 16)
/* AHB Clock (USB host) [AT91SAM9261 only] */
#define AT91_PMC_HCK1 (1 << 17)
/* AHB Clock (LCD) [AT91SAM9261 only] */
#define AT91_PMC_HCK1 (1 << 17)
/* AHB Clock (LCD) [AT91SAM9261 only] */
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_PCER (AT91_PMC + 0x10)
/* Peripheral Clock Enable Register */
#define AT91_PMC_PCER (AT91_PMC + 0x10)
/* Peripheral Clock Enable Register */
#define AT91_PMC_PCDR (AT91_PMC + 0x14)
/* Peripheral Clock Disable Register */
#define AT91_PMC_PCDR (AT91_PMC + 0x14)
/* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18)
/* Peripheral Clock Status Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18)
/* Peripheral Clock Status Register */
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C)
/* UTMI Clock Register [SAM9RL, CAP9] */
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C)
/* UTMI Clock Register [SAM9RL, CAP9] */
#endif
#define AT91_PMC_UPLLEN (1 << 16)
/* UTMI PLL Enable */
#define AT91_PMC_UPLLEN (1 << 16)
/* UTMI PLL Enable */
#define AT91_PMC_UPLLCOUNT (0xf << 20)
/* UTMI PLL Start-up Time */
#define AT91_PMC_UPLLCOUNT (0xf << 20)
/* UTMI PLL Start-up Time */
#define AT91_PMC_BIASEN (1 << 24)
/* UTMI BIAS Enable */
#define AT91_PMC_BIASEN (1 << 24)
/* UTMI BIAS Enable */
#define AT91_PMC_BIASCOUNT (0xf << 28)
/* UTMI PLL Start-up Time */
#define AT91_PMC_BIASCOUNT (0xf << 28)
/* UTMI PLL Start-up Time */
#ifdef CONFIG_AT91_LEGACY
#define AT91_CKGR_MOR (AT91_PMC + 0x20)
/* Main Oscillator Register [not on SAM9RL] */
#define AT91_CKGR_MOR (AT91_PMC + 0x20)
/* Main Oscillator Register [not on SAM9RL] */
#endif
#define AT91_PMC_MOSCEN (1 << 0)
/* Main Oscillator Enable */
#define AT91_PMC_MOSCEN (1 << 0)
/* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1)
/* Oscillator Bypass [SAM9x, CAP9] */
#define AT91_PMC_OSCBYPASS (1 << 1)
/* Oscillator Bypass [SAM9x, CAP9] */
#define AT91_PMC_OSCOUNT (0xff << 8)
/* Main Oscillator Start-up Time */
#define AT91_PMC_OSCOUNT (0xff << 8)
/* Main Oscillator Start-up Time */
#ifdef CONFIG_AT91_LEGACY
#define AT91_CKGR_MCFR (AT91_PMC + 0x24)
/* Main Clock Frequency Register */
#define AT91_CKGR_MCFR (AT91_PMC + 0x24)
/* Main Clock Frequency Register */
#endif
#define AT91_PMC_MAINF (0xffff << 0)
/* Main Clock Frequency */
#define AT91_PMC_MAINF (0xffff << 0)
/* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16)
/* Main Clock Ready */
#define AT91_PMC_MAINRDY (1 << 16)
/* Main Clock Ready */
#ifdef CONFIG_AT91_LEGACY
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28)
/* PLL A Register */
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28)
/* PLL A Register */
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c)
/* PLL B Register */
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c)
/* PLL B Register */
#endif
#define AT91_PMC_DIV (0xff << 0)
/* Divider */
#define AT91_PMC_DIV (0xff << 0)
/* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8)
/* PLL Counter */
#define AT91_PMC_PLLCOUNT (0x3f << 8)
/* PLL Counter */
#define AT91_PMC_OUT (3 << 14)
/* PLL Clock Frequency Range */
#define AT91_PMC_OUT (3 << 14)
/* PLL Clock Frequency Range */
...
@@ -160,7 +168,9 @@ typedef struct at91_pmc {
...
@@ -160,7 +168,9 @@ typedef struct at91_pmc {
#define AT91_PMC_USB96M (1 << 28)
/* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_USB96M (1 << 28)
/* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_PLLA_WR_ERRATA (1 << 29)
/* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
#define AT91_PMC_PLLA_WR_ERRATA (1 << 29)
/* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_MCKR (AT91_PMC + 0x30)
/* Master Clock Register */
#define AT91_PMC_MCKR (AT91_PMC + 0x30)
/* Master Clock Register */
#endif
#define AT91_PMC_CSS (3 << 0)
/* Master Clock Selection */
#define AT91_PMC_CSS (3 << 0)
/* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
...
@@ -188,11 +198,13 @@ typedef struct at91_pmc {
...
@@ -188,11 +198,13 @@ typedef struct at91_pmc {
#define AT91_PMC_PDIV_1 (0 << 12)
#define AT91_PMC_PDIV_1 (0 << 12)
#define AT91_PMC_PDIV_2 (1 << 12)
#define AT91_PMC_PDIV_2 (1 << 12)
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4))
/* Programmable Clock 0-3 Registers */
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4))
/* Programmable Clock 0-3 Registers */
#define AT91_PMC_IER (AT91_PMC + 0x60)
/* Interrupt Enable Register */
#define AT91_PMC_IER (AT91_PMC + 0x60)
/* Interrupt Enable Register */
#define AT91_PMC_IDR (AT91_PMC + 0x64)
/* Interrupt Disable Register */
#define AT91_PMC_IDR (AT91_PMC + 0x64)
/* Interrupt Disable Register */
#define AT91_PMC_SR (AT91_PMC + 0x68)
/* Status Register */
#define AT91_PMC_SR (AT91_PMC + 0x68)
/* Status Register */
#endif
#define AT91_PMC_MOSCS (1 << 0)
/* MOSCS Flag */
#define AT91_PMC_MOSCS (1 << 0)
/* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1)
/* PLLA Lock */
#define AT91_PMC_LOCKA (1 << 1)
/* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2)
/* PLLB Lock */
#define AT91_PMC_LOCKB (1 << 2)
/* PLLB Lock */
...
@@ -203,12 +215,13 @@ typedef struct at91_pmc {
...
@@ -203,12 +215,13 @@ typedef struct at91_pmc {
#define AT91_PMC_PCK1RDY (1 << 9)
/* Programmable Clock 1 */
#define AT91_PMC_PCK1RDY (1 << 9)
/* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10)
/* Programmable Clock 2 */
#define AT91_PMC_PCK2RDY (1 << 10)
/* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11)
/* Programmable Clock 3 */
#define AT91_PMC_PCK3RDY (1 << 11)
/* Programmable Clock 3 */
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_IMR (AT91_PMC + 0x6c)
/* Interrupt Mask Register */
#define AT91_PMC_IMR (AT91_PMC + 0x6c)
/* Interrupt Mask Register */
#define AT91_PMC_PROT (AT91_PMC + 0xe4)
/* Protect Register [AT91CAP9 revC only] */
#define AT91_PMC_PROT (AT91_PMC + 0xe4)
/* Protect Register [AT91CAP9 revC only] */
#endif
#define AT91_PMC_PROTKEY 0x504d4301
/* Activation Code */
#define AT91_PMC_PROTKEY 0x504d4301
/* Activation Code */
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_VER (AT91_PMC + 0xfc)
/* PMC Module Version [AT91CAP9 only] */
#define AT91_PMC_VER (AT91_PMC + 0xfc)
/* PMC Module Version [AT91CAP9 only] */
#endif
/* CONFIG_AT91_LEGACY */
#endif
/* CONFIG_AT91_LEGACY */
#endif
#endif
include/asm-arm/arch-s5pc1xx/clk.h
浏览文件 @
6a1f7e54
...
@@ -23,6 +23,12 @@
...
@@ -23,6 +23,12 @@
#ifndef __ASM_ARM_ARCH_CLK_H_
#ifndef __ASM_ARM_ARCH_CLK_H_
#define __ASM_ARM_ARCH_CLK_H_
#define __ASM_ARM_ARCH_CLK_H_
#define APLL 0
#define MPLL 1
#define EPLL 2
#define HPLL 3
#define VPLL 4
void
s5pc1xx_clock_init
(
void
);
void
s5pc1xx_clock_init
(
void
);
extern
unsigned
long
(
*
get_pll_clk
)(
int
pllreg
);
extern
unsigned
long
(
*
get_pll_clk
)(
int
pllreg
);
...
...
include/asm-arm/arch-s5pc1xx/gpio.h
浏览文件 @
6a1f7e54
...
@@ -124,6 +124,35 @@ struct s5pc110_gpio {
...
@@ -124,6 +124,35 @@ struct s5pc110_gpio {
struct
s5pc1xx_gpio_bank
gpio_h2
;
struct
s5pc1xx_gpio_bank
gpio_h2
;
struct
s5pc1xx_gpio_bank
gpio_h3
;
struct
s5pc1xx_gpio_bank
gpio_h3
;
};
};
/* functions */
void
gpio_cfg_pin
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
,
int
cfg
);
void
gpio_direction_output
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
,
int
en
);
void
gpio_direction_input
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
);
void
gpio_set_value
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
,
int
en
);
unsigned
int
gpio_get_value
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
);
void
gpio_set_pull
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
,
int
mode
);
void
gpio_set_drv
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
,
int
mode
);
void
gpio_set_rate
(
struct
s5pc1xx_gpio_bank
*
bank
,
int
gpio
,
int
mode
);
#endif
#endif
/* Pin configurations */
#define GPIO_INPUT 0x0
#define GPIO_OUTPUT 0x1
#define GPIO_IRQ 0xf
#define GPIO_FUNC(x) (x)
/* Pull mode */
#define GPIO_PULL_NONE 0x0
#define GPIO_PULL_DOWN 0x1
#define GPIO_PULL_UP 0x2
/* Drive Strength level */
#define GPIO_DRV_1X 0x0
#define GPIO_DRV_2X 0x1
#define GPIO_DRV_3X 0x2
#define GPIO_DRV_4X 0x3
#define GPIO_DRV_FAST 0x0
#define GPIO_DRV_SLOW 0x1
#endif
#endif
include/asm-arm/arch-s5pc1xx/smc.h
0 → 100644
浏览文件 @
6a1f7e54
/*
* (C) Copyright 2010 Samsung Electronics
* Naveen Krishna Ch <ch.naveen@samsung.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Note: This file contains the register description for Memory subsystem
* (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
*
* Only SROMC is defined as of now
*/
#ifndef __ASM_ARCH_SMC_H_
#define __ASM_ARCH_SMC_H_
#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1))
/* 0-> Half-word base address*/
/* 1-> Byte base address*/
#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2))
#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3))
#define SMC_BC_TACS(x) (x << 28)
/* 0clk address set-up */
#define SMC_BC_TCOS(x) (x << 24)
/* 4clk chip selection set-up */
#define SMC_BC_TACC(x) (x << 16)
/* 14clk access cycle */
#define SMC_BC_TCOH(x) (x << 12)
/* 1clk chip selection hold */
#define SMC_BC_TAH(x) (x << 8)
/* 4clk address holding time */
#define SMC_BC_TACP(x) (x << 4)
/* 6clk page mode access cycle */
#define SMC_BC_PMC(x) (x << 0)
/* normal(1data)page mode configuration */
#ifndef __ASSEMBLY__
struct
s5pc1xx_smc
{
unsigned
int
bw
;
unsigned
int
bc
[
6
];
};
#endif
/* __ASSEMBLY__ */
/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
void
s5pc1xx_config_sromc
(
u32
srom_bank
,
u32
smc_bw_conf
,
u32
smc_bc_conf
);
#endif
/* __ASM_ARCH_SMC_H_ */
include/configs/meesc.h
浏览文件 @
6a1f7e54
...
@@ -82,7 +82,6 @@
...
@@ -82,7 +82,6 @@
*/
*/
#include <config_cmd_default.h>
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_IMLS
...
...
include/configs/otc570.h
浏览文件 @
6a1f7e54
...
@@ -131,7 +131,6 @@
...
@@ -131,7 +131,6 @@
* Command line configuration.
* Command line configuration.
*/
*/
#include <config_cmd_default.h>
#include <config_cmd_default.h>
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_IMLS
...
...
include/configs/smdkc100.h
浏览文件 @
6a1f7e54
...
@@ -83,7 +83,6 @@
...
@@ -83,7 +83,6 @@
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_NAND
#undef CONFIG_CMD_NAND
#undef CONFIG_CMD_NET
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_REGINFO
...
@@ -235,4 +234,15 @@
...
@@ -235,4 +234,15 @@
#define CONFIG_DOS_PARTITION 1
#define CONFIG_DOS_PARTITION 1
/*
* Ethernet Contoller driver
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X 1
/* we have a SMC9115 on-board */
#define CONFIG_SMC911X_16_BIT 1
/* SMC911X_16_BIT Mode */
#define CONFIG_SMC911X_BASE 0x98800300
/* SMC911X Drive Base */
#define CONFIG_ENV_SROM_BANK 3
/* Select SROM Bank-3 for Ethernet*/
#endif
/* CONFIG_CMD_NET */
#endif
/* __CONFIG_H */
#endif
/* __CONFIG_H */
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录