Blackfin: add workaround for anomaly 05000242

DESCRIPTION:
If the DF bit is set prior to a hardware reset, the PLL will continue to
divide CLKIN by 2 after the hardware reset, but the DF bit itself will be
cleared in the PLL_CTL register.

WORKAROUND:
Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by
2 after reset.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

cpu/blackfin/initcode.c

@@ -401,7 +401,7 @@ void initcode(ADI_BOOT_DATA *bootstruct)
 		/* Only reprogram when needed to avoid triggering unnecessary
 		 * PLL relock sequences.
 		 */
-		if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
+		if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
 			serial_putc('!');
 			bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
 			asm("idle;");