diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 3fe13daaf38d6be5b1f514273fedda65a4379d62..8e000d309240181e7b61319990f4fcadfd5cf02c 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -204,6 +204,18 @@ _start_440:
 	mfspr	r1,mcsr
 	mtspr	mcsr,r1
 #endif
+
+	/*----------------------------------------------------------------*/
+	/* CCR0 init */
+	/*----------------------------------------------------------------*/
+	/* Disable store gathering & broadcast, guarantee inst/data
+	* cache block touch, force load/store alignment
+	* (see errata 1.12: 440_33)
+	*/
+	lis	r1,0x0030	/* store gathering & broadcast disable */
+	ori	r1,r1,0x6000	/* cache touch */
+	mtspr	ccr0,r1
+
 	/*----------------------------------------------------------------*/
 	/* Initialize debug */
 	/*----------------------------------------------------------------*/
@@ -225,17 +237,6 @@ _start_440:
 	mtspr	dbsr,r1		/* Clear all valid bits */
 skip_debug_init:
 
-	/*----------------------------------------------------------------*/
-	/* CCR0 init */
-	/*----------------------------------------------------------------*/
-	/* Disable store gathering & broadcast, guarantee inst/data
-	* cache block touch, force load/store alignment
-	* (see errata 1.12: 440_33)
-	*/
-	lis	r1,0x0030	/* store gathering & broadcast disable */
-	ori	r1,r1,0x6000	/* cache touch */
-	mtspr	ccr0,r1
-
 #if defined (CONFIG_440SPE)
 	/*----------------------------------------------------------------+
 	| Initialize Core Configuration Reg1.