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提交 34af2da9 编写于 作者: T Tom Rini
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ppc: Remove MPC8349ITX board 

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
this board.
Signed-off-by: NTom Rini <trini@konsulko.com>
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arch/powerpc/cpu/mpc83xx/Kconfig
浏览文件 @ 34af2da9
......@@ -75,11 +75,6 @@ config TARGET_MPC8349EMDS_SDRAM
select SYS_FSL_DDR_BE
select SYS_FSL_HAS_DDR2
config TARGET_MPC8349ITX
bool "Support MPC8349ITX"
select ARCH_MPC8349
imply CMD_IRQ
config TARGET_MPC837XEMDS
bool "Support MPC837XEMDS"
select ARCH_MPC837X
......@@ -336,7 +331,6 @@ source "board/freescale/mpc8315erdb/Kconfig"
source "board/freescale/mpc8323erdb/Kconfig"
source "board/freescale/mpc832xemds/Kconfig"
source "board/freescale/mpc8349emds/Kconfig"
source "board/freescale/mpc8349itx/Kconfig"
source "board/freescale/mpc837xemds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
......
board/freescale/mpc8349itx/Kconfig 已删除 100644 → 0
浏览文件 @ c861d21c
if TARGET_MPC8349ITX
config SYS_BOARD
default "mpc8349itx"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "MPC8349ITX"
endif
board/freescale/mpc8349itx/MAINTAINERS 已删除 100644 → 0
浏览文件 @ c861d21c
MPC8349ITX BOARD
#M: -
S: Maintained
F: board/freescale/mpc8349itx/
F: include/configs/MPC8349ITX.h
F: configs/MPC8349ITX_defconfig
F: configs/MPC8349ITX_LOWBOOT_defconfig
F: configs/MPC8349ITXGP_defconfig
board/freescale/mpc8349itx/Makefile 已删除 100644 → 0
浏览文件 @ c861d21c
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) Freescale Semiconductor, Inc. 2006.
obj-y += mpc8349itx.o
obj-$(CONFIG_PCI) += pci.o
board/freescale/mpc8349itx/README 已删除 100644 → 0
浏览文件 @ c861d21c
Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
---------------------------------------------------
1. Board Description
The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring
the Freescale MPC8349E processor in a Mini-ITX form factor.
The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences:
A) One 8MB on-board flash EEPROM chip, instead of two.
B) No SATA controller
C) No Compact Flash slot
D) No Mini-PCI slot
E) No Vitesse 7385 5-port Ethernet switch
F) No 4-port USB Type-A interface
2. Board Switches and Jumpers
2.0 Descriptions for all of the board jumpers can be found in the User
Guide. Of particular interest to U-Boot developers is jumper J22:
Pos. Name Default Description
-----------------------------------------------------------------------
A LGPL0 ON (0) HRCW source, bit 0
B LGPL1 ON (0) HRCW source, bit 1
C LGPL3 ON (0) HRCW source, bit 2
D LGPL5 OFF (1) PCI_SYNC_OUT frequency
E BOOT1 ON (0) Flash EEPROM boot device
F PCI_M66EN ON (0) PCI 66MHz enable
G I2C-WP ON (0) I2C EEPROM write protection
H F_WP OFF (1) Flash EEPROM write protection
Jumper J22.E is only for the ITX, and it decides the configuration
of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip
U4 is located at address FE000000 and flash chip U7 is at FE800000.
If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000.
For U-Boot development, J22.E can be used to switch back-and-forth
between two U-Boot images.
3. Memory Map
3.1. The memory map should look pretty much like this:
0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB)
0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB)
0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB)
0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB)
0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB)
0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB)
0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only)
0xF001_0000 - 0xF001_FFFF Local bus expansion slot
0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only)
0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory
0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only)
3.2 Flash EEPROM layout.
On the ITX, jumper J22.E is used to determine which flash chips are
at which address. When J22.E is switched, addresses from FE000000
to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF.
On the ITX, at the normal boot address (aka HIGHBOOT):
FE00_0000 HRCW
FE70_0000 Alternative U-Boot image
FE80_0000 Alternative HRCW
FEF0_0000 U-Boot image
FEFF_FFFF End of flash
On the ITX, at the low boot address (LOWBOOT)
FE00_0000 HRCW and U-Boot image
FE04_0000 U-Boot environment variables
FE80_0000 Alternative HRCW and U-Boot image
FEFF_FFFF End of flash
On the ITX-GP, the only option is LOWBOOT and there is only one chip
FE00_0000 HRCW and U-Boot image
FE04_0000 U-Boot environment variables
F7FF_FFFF End of flash
4. Definitions
4.1 Explanation of NEW definitions in:
include/configs/MPC8349ITX.h
CONFIG_MPC83xx MPC83xx family
CONFIG_MPC8349 MPC8349 specific
CONFIG_MPC8349ITX MPC8349E-mITX
5. Compilation
Assuming you're using BASH shell:
export CROSS_COMPILE=your-cross-compile-prefix
cd u-boot
make distclean
make MPC8349ITX_config
or:
make MPC8349ITXGP_config
or:
make MPC8349ITX_LOWBOOT_config
make
6. Downloading and Flashing Images
6.1 Download via tftp:
tftp $loadaddr <uboot>
where "<uboot>" is the path and filename, on the TFTP server, of
the U-Boot image.
6.1 Reflash U-Boot Image using U-Boot
setenv uboot <uboot>
run tftpflash
where "<uboot>" is the path and filename, on the TFTP server, of
the U-Boot image.
6.2 Using the HRCW to switch between two different U-Boot images on the ITX
Because the ITX has 16MB of flash, it is possible to keep two U-Boot
images in flash, and use the HRCW to specify which one is to be used
when the board boots. This trick is especially effective with a
hardware debugger that can override the HRCW, such as the BDI-2000.
When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image
at address FE000000. When the BMS bit is 1, the ITX will boot the
image at address FEF00000.
Therefore, just put a U-Boot image at both FE000000 and FEF00000 and
change the BMS bit whenever you want to boot the other image.
Step-by-step instructions:
1) Build an ITX image to be loaded at FEF00000
make distclean
make MPC8349ITX_config
make
2) Take the u-boot.bin image and flash it at FEF00000.
tftp $loadaddr u-boot.bin
protect off all
erase FEF00000 +$filesize
cp.b $loadaddr FEF00000 $filesize
3) Build an ITX image to be loaded at FE000000
make distclean
make MPC8349ITX_LOWBOOT_config
make
4) Take the u-boot.bin image and flash it at FE000000.
tftp $loadaddr u-boot.bin
protect off FE000000 +$filesize
erase FE000000 +$filesize
cp.b $loadaddr FE000000 $filesize
The HRCW in flash is currently set to boot the image at FE000000.
If you have a hardware debugger, configure it to set the HRCW to
B460A000 04040000 if you want to boot the image at FEF00000, or set
it to B060A000 04040000 if you want to boot the image at FE000000.
To change the HRCW in flash to boot the image at FEF00000, use these
U-Boot commands:
cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000
mw.b 1020 b4 8 ; modify BMS bit
protect off FE000000 +10000
erase FE000000 +10000
cp.b 1000 FE000000 10000
7. Notes
1) The console baudrate for MPC8349EITX is 115200bps.
board/freescale/mpc8349itx/mpc8349itx.c 已删除 100644 → 0
浏览文件 @ c861d21c
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006.
*/
#include <common.h>
#include <fdt_support.h>
#include <init.h>
#include <ioports.h>
#include <log.h>
#include <mpc83xx.h>
#include <i2c.h>
#include <miiphy.h>
#include <vsc7385.h>
#ifdef CONFIG_PCI
#include <asm/mpc8349_pci.h>
#include <pci.h>
#endif
#include <spd_sdram.h>
#include <asm/bitops.h>
#include <asm/global_data.h>
#include <asm/mmu.h>
#if defined(CONFIG_OF_LIBFDT)
#include <linux/libfdt.h>
#endif
#include <linux/delay.h>
#include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPD_EEPROM
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
/* The size of RAM, in bytes */
u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
u32 ddr_size_log2 = __ilog2(ddr_size);
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[0].csbnds =
((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
CSBNDS_EA_SHIFT) & CSBNDS_EA);
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
/* Only one CS for DDR */
im->ddr.cs_config[1] = 0;
im->ddr.cs_config[2] = 0;
im->ddr.cs_config[3] = 0;
debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
im->ddr.sdram_mode =
(0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
im->ddr.sdram_interval =
(0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
SDRAM_INTERVAL_BSTOPRE_SHIFT);
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
udelay(200);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
return CONFIG_SYS_DDR_SIZE;
}
#endif
#ifdef CONFIG_PCI
/*
* Initialize PCI Devices, report devices found
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
{
PCI_ANY_ID,
PCI_ANY_ID,
PCI_ANY_ID,
PCI_ANY_ID,
0x0f,
PCI_ANY_ID,
pci_cfgfunc_config_device,
{
PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
},
{}
}
#endif
volatile static struct pci_controller hose[] = {
{
#ifndef CONFIG_PCI_PNP
config_table:pci_mpc83xxmitx_config_table,
#endif
},
{
#ifndef CONFIG_PCI_PNP
config_table:pci_mpc83xxmitx_config_table,
#endif
}
};
#endif /* CONFIG_PCI */
int dram_init(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
#ifdef CONFIG_DDR_ECC
volatile ddr83xx_t *ddr = &im->ddr;
#endif
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
#ifdef CONFIG_SPD_EEPROM
msize = spd_sdram();
#else
msize = fixed_sdram();
#endif
#ifdef CONFIG_DDR_ECC
if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
/* Unlike every other board, on the 83xx spd_sdram() returns
megabytes instead of just bytes. That's why we need to
multiple by 1MB when calling ddr_enable_ecc(). */
ddr_enable_ecc(msize * 1048576);
#endif
/* return total bus RAM size(bytes) */
gd->ram_size = msize * 1024 * 1024;
return 0;
}
int checkboard(void)
{
#ifdef CONFIG_TARGET_MPC8349ITX
puts("Board: Freescale MPC8349E-mITX\n");
#else
puts("Board: Freescale MPC8349E-mITX-GP\n");
#endif
return 0;
}
/*
* Implement a work-around for a hardware problem with compact
* flash.
*
* Program the UPM if compact flash is enabled.
*/
int misc_init_f(void)
{
#ifdef CONFIG_VSC7385_ENET
volatile u32 *vsc7385_cpuctrl;
/* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
means it is 0 when the IRQ is not active. This makes the wire-AND
logic always assert IRQ7 to CPU even if there is no request from the
switch. Since the compact flash and the switch share the same IRQ,
the Linux kernel will think that the compact flash is requesting irq
and get stuck when it tries to clear the IRQ. Thus we need to set
the L2_IRQ0 and L2_IRQ1 to active low.
The following code sets the L1_IRQ and L2_IRQ polarity to active low.
Without this code, compact flash will not work in Linux because
unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
don't enable compact flash for U-Boot.
*/
vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
*vsc7385_cpuctrl |= 0x0c;
#endif
#ifdef CONFIG_COMPACT_FLASH
/* UPM Table Configuration Code */
static uint UPMATable[] = {
0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
};
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
*/
immap->im_lbc.mamr = 0x08404440;
upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
puts("UPMA: Configured for compact flash\n");
#endif
return 0;
}
/*
* Miscellaneous late-boot configurations
*
* Make sure the EEPROM has the HRCW correctly programmed.
* Make sure the RTC is correctly programmed.
*
* The MPC8349E-mITX can be configured to load the HRCW from
* EEPROM instead of flash. This is controlled via jumpers
* LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
* jumpered), but if they're set to 001 or 010, then the HRCW is
* read from the "I2C EEPROM".
*
* This function makes sure that the I2C EEPROM is programmed
* correctly.
*
* If a VSC7385 microcode image is present, then upload it.
*/
int misc_init_r(void)
{
int rc = 0;
#if defined(CONFIG_SYS_I2C)
unsigned int orig_bus = i2c_get_bus_num();
u8 i2c_data;
#ifdef CONFIG_SYS_I2C_RTC_ADDR
u8 ds1339_data[17];
#endif
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
static u8 eeprom_data[] = /* HRCW data */
{
0xAA, 0x55, 0xAA, /* Preamble */
0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
0x02, 0x40, /* RCWL ADDR=0x0_0900 */
(CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
(CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
(CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
CONFIG_SYS_HRCW_LOW & 0xFF,
0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
0x02, 0x41, /* RCWH ADDR=0x0_0904 */
(CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
(CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
(CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
CONFIG_SYS_HRCW_HIGH & 0xFF
};
u8 data[sizeof(eeprom_data)];
#endif
printf("Board revision: ");
i2c_set_bus_num(1);
if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
else {
printf("Unknown\n");
rc = 1;
}
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
i2c_set_bus_num(0);
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
if (i2c_write
(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
sizeof(eeprom_data)) != 0) {
puts("Failure writing the HRCW to EEPROM via I2C.\n");
rc = 1;
}
}
} else {
puts("Failure reading the HRCW from EEPROM via I2C.\n");
rc = 1;
}
#endif
#ifdef CONFIG_SYS_I2C_RTC_ADDR
i2c_set_bus_num(1);
if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
== 0) {
/* Work-around for MPC8349E-mITX bug #13601.
If the RTC does not contain valid register values, the DS1339
Linux driver will not work.
*/
/* Make sure status register bits 6-2 are zero */
ds1339_data[0x0f] &= ~0x7c;
/* Check for a valid day register value */
ds1339_data[0x03] &= ~0xf8;
if (ds1339_data[0x03] == 0) {
ds1339_data[0x03] = 1;
}
/* Check for a valid date register value */
ds1339_data[0x04] &= ~0xc0;
if ((ds1339_data[0x04] == 0) ||
((ds1339_data[0x04] & 0x0f) > 9) ||
(ds1339_data[0x04] >= 0x32)) {
ds1339_data[0x04] = 1;
}
/* Check for a valid month register value */
ds1339_data[0x05] &= ~0x60;
if ((ds1339_data[0x05] == 0) ||
((ds1339_data[0x05] & 0x0f) > 9) ||
((ds1339_data[0x05] >= 0x13)
&& (ds1339_data[0x05] <= 0x19))) {
ds1339_data[0x05] = 1;
}
/* Enable Oscillator and rate select */
ds1339_data[0x0e] = 0x1c;
/* Work-around for MPC8349E-mITX bug #13330.
Ensure that the RTC control register contains the value 0x1c.
This affects SATA performance.
*/
if (i2c_write
(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
sizeof(ds1339_data))) {
puts("Failure writing to the RTC via I2C.\n");
rc = 1;
}
} else {
puts("Failure reading from the RTC via I2C.\n");
rc = 1;
}
#endif
i2c_set_bus_num(orig_bus);
#endif
#ifdef CONFIG_VSC7385_IMAGE
if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
CONFIG_VSC7385_IMAGE_SIZE)) {
puts("Failure uploading VSC7385 microcode.\n");
rc = 1;
}
#endif
return rc;
}
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
return 0;
}
#endif
board/freescale/mpc8349itx/pci.c 已删除 100644 → 0
浏览文件 @ c861d21c
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <linux/delay.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
#include <asm/fsl_i2c.h>
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
size: CONFIG_SYS_PCI1_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CONFIG_SYS_PCI1_IO_BASE,
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
size: CONFIG_SYS_PCI1_IO_SIZE,
flags: PCI_REGION_IO
},
{
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
size: CONFIG_SYS_PCI1_MMIO_SIZE,
flags: PCI_REGION_MEM
},
};
#ifdef CONFIG_MPC83XX_PCI2
static struct pci_region pci2_regions[] = {
{
bus_start: CONFIG_SYS_PCI2_MEM_BASE,
phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
size: CONFIG_SYS_PCI2_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CONFIG_SYS_PCI2_IO_BASE,
phys_start: CONFIG_SYS_PCI2_IO_PHYS,
size: CONFIG_SYS_PCI2_IO_SIZE,
flags: PCI_REGION_IO
},
{
bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
size: CONFIG_SYS_PCI2_MMIO_SIZE,
flags: PCI_REGION_MEM
},
};
#endif
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
#ifndef CONFIG_MPC83XX_PCI2
struct pci_region *reg[] = { pci1_regions };
#else
struct pci_region *reg[] = { pci1_regions, pci2_regions };
#endif
u8 reg8;
#if defined(CONFIG_SYS_I2C)
i2c_set_bus_num(1);
/* Read the PCI_M66EN jumper setting */
if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) ||
(i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
if (reg8 & I2C_8574_PCI66)
clk->occr = 0xff000000; /* 66 MHz PCI */
else
clk->occr = 0xff600001; /* 33 MHz PCI */
} else {
clk->occr = 0xff600001; /* 33 MHz PCI */
}
#else
clk->occr = 0xff000000; /* 66 MHz PCI */
#endif
udelay(2000);
/* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
udelay(2000);
#ifndef CONFIG_MPC83XX_PCI2
mpc83xx_pci_init(1, reg);
#else
mpc83xx_pci_init(2, reg);
#endif
}
configs/MPC8349ITXGP_defconfig 已删除 100644 → 0
浏览文件 @ c861d21c
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
CONFIG_CORE_PLL_RATIO_2_1=y
CONFIG_PCI_HOST_MODE_ENABLE=y
CONFIG_PCI_INT_ARBITER1_ENABLE=y
CONFIG_PCI_INT_ARBITER2_ENABLE=y
CONFIG_BOOT_MEMORY_SPACE_LOW=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
CONFIG_TSEC1_MODE_GMII=y
CONFIG_TSEC2_MODE_GMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="SDRAM"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT1=y
CONFIG_BAT1_NAME="PCI1_MEM"
CONFIG_BAT1_BASE=0x80000000
CONFIG_BAT1_LENGTH_256_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT1_USER_MODE_VALID=y
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
CONFIG_BAT2=y
CONFIG_BAT2_NAME="PCI1_MMIO"
CONFIG_BAT2_BASE=0x90000000
CONFIG_BAT2_LENGTH_256_MBYTES=y
CONFIG_BAT2_ACCESS_RW=y
CONFIG_BAT2_ICACHE_INHIBITED=y
CONFIG_BAT2_ICACHE_GUARDED=y
CONFIG_BAT2_DCACHE_INHIBITED=y
CONFIG_BAT2_DCACHE_GUARDED=y
CONFIG_BAT2_USER_MODE_VALID=y
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
CONFIG_BAT3=y
CONFIG_BAT3_NAME="PCI2_MEM"
CONFIG_BAT3_BASE=0xA0000000
CONFIG_BAT3_LENGTH_256_MBYTES=y
CONFIG_BAT3_ACCESS_RW=y
CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT3_USER_MODE_VALID=y
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
CONFIG_BAT4=y
CONFIG_BAT4_NAME="PCI2_MMIO"
CONFIG_BAT4_BASE=0xB0000000
CONFIG_BAT4_LENGTH_256_MBYTES=y
CONFIG_BAT4_ACCESS_RW=y
CONFIG_BAT4_ICACHE_INHIBITED=y
CONFIG_BAT4_ICACHE_GUARDED=y
CONFIG_BAT4_DCACHE_INHIBITED=y
CONFIG_BAT4_DCACHE_GUARDED=y
CONFIG_BAT4_USER_MODE_VALID=y
CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
CONFIG_BAT5=y
CONFIG_BAT5_NAME="IMMR"
CONFIG_BAT5_BASE=0xE0000000
CONFIG_BAT5_LENGTH_256_MBYTES=y
CONFIG_BAT5_ACCESS_RW=y
CONFIG_BAT5_ICACHE_INHIBITED=y
CONFIG_BAT5_ICACHE_GUARDED=y
CONFIG_BAT5_DCACHE_INHIBITED=y
CONFIG_BAT5_DCACHE_GUARDED=y
CONFIG_BAT5_USER_MODE_VALID=y
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
CONFIG_BAT6=y
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
CONFIG_BAT6_BASE=0xF0000000
CONFIG_BAT6_LENGTH_256_MBYTES=y
CONFIG_BAT6_ACCESS_RW=y
CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_ICACHE_GUARDED=y
CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_DCACHE_GUARDED=y
CONFIG_BAT6_USER_MODE_VALID=y
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_16_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xF8000000
CONFIG_LBLAW1_NAME="VSC7385"
CONFIG_LBLAW1_LENGTH_128_KBYTES=y
CONFIG_LBLAW3=y
CONFIG_LBLAW3_BASE=0xF0000000
CONFIG_LBLAW3_NAME="CF"
CONFIG_LBLAW3_LENGTH_64_KBYTES=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xFE000000
CONFIG_BR0_PORTSIZE_16BIT=y
CONFIG_OR0_AM_16_MBYTES=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_SCY_15=y
CONFIG_OR0_CSNT_EARLIER=y
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_OR0_EAD_EXTRA=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="VSC7385"
CONFIG_BR1_OR1_BASE=0xF8000000
CONFIG_OR1_AM_128_KBYTES=y
CONFIG_OR1_SCY_15=y
CONFIG_OR1_CSNT_EARLIER=y
CONFIG_OR1_XACS_EXTENDED=y
CONFIG_OR1_SETA_EXTERNAL=y
CONFIG_OR1_TRLX_RELAXED=y
CONFIG_OR1_EHTR_8_CYCLE=y
CONFIG_OR1_EAD_EXTRA=y
CONFIG_ELBC_BR2_OR2=y
CONFIG_BR2_OR2_NAME="LED"
CONFIG_BR2_OR2_BASE=0xF9000000
CONFIG_OR2_AM_2_MBYTES=y
CONFIG_OR2_SCY_9=y
CONFIG_OR2_CSNT_EARLIER=y
CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR2_XACS_EXTENDED=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_8_CYCLE=y
CONFIG_OR2_EAD_EXTRA=y
CONFIG_ELBC_BR3_OR3=y
CONFIG_BR3_OR3_NAME="CF"
CONFIG_BR3_OR3_BASE=0xF0000000
CONFIG_BR3_PORTSIZE_16BIT=y
CONFIG_BR3_MACHINE_UPMA=y
CONFIG_OR3_BI_BURSTINHIBIT=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_SPCR_TSEC1EP_3=y
CONFIG_SPCR_TSEC2EP_3=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000"
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitxgp:eth0:off console=ttyS0,115200"
CONFIG_MISC_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFE080000
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
configs/MPC8349ITX_LOWBOOT_defconfig 已删除 100644 → 0
浏览文件 @ c861d21c
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
CONFIG_CORE_PLL_RATIO_2_1=y
CONFIG_PCI_HOST_MODE_ENABLE=y
CONFIG_PCI_INT_ARBITER1_ENABLE=y
CONFIG_PCI_INT_ARBITER2_ENABLE=y
CONFIG_BOOT_MEMORY_SPACE_LOW=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
CONFIG_TSEC1_MODE_GMII=y
CONFIG_TSEC2_MODE_GMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="SDRAM"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT1=y
CONFIG_BAT1_NAME="PCI1_MEM"
CONFIG_BAT1_BASE=0x80000000
CONFIG_BAT1_LENGTH_256_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT1_USER_MODE_VALID=y
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
CONFIG_BAT2=y
CONFIG_BAT2_NAME="PCI1_MMIO"
CONFIG_BAT2_BASE=0x90000000
CONFIG_BAT2_LENGTH_256_MBYTES=y
CONFIG_BAT2_ACCESS_RW=y
CONFIG_BAT2_ICACHE_INHIBITED=y
CONFIG_BAT2_ICACHE_GUARDED=y
CONFIG_BAT2_DCACHE_INHIBITED=y
CONFIG_BAT2_DCACHE_GUARDED=y
CONFIG_BAT2_USER_MODE_VALID=y
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
CONFIG_BAT3=y
CONFIG_BAT3_NAME="PCI2_MEM"
CONFIG_BAT3_BASE=0xA0000000
CONFIG_BAT3_LENGTH_256_MBYTES=y
CONFIG_BAT3_ACCESS_RW=y
CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT3_USER_MODE_VALID=y
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
CONFIG_BAT4=y
CONFIG_BAT4_NAME="PCI2_MMIO"
CONFIG_BAT4_BASE=0xB0000000
CONFIG_BAT4_LENGTH_256_MBYTES=y
CONFIG_BAT4_ACCESS_RW=y
CONFIG_BAT4_ICACHE_INHIBITED=y
CONFIG_BAT4_ICACHE_GUARDED=y
CONFIG_BAT4_DCACHE_INHIBITED=y
CONFIG_BAT4_DCACHE_GUARDED=y
CONFIG_BAT4_USER_MODE_VALID=y
CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
CONFIG_BAT5=y
CONFIG_BAT5_NAME="IMMR"
CONFIG_BAT5_BASE=0xE0000000
CONFIG_BAT5_LENGTH_256_MBYTES=y
CONFIG_BAT5_ACCESS_RW=y
CONFIG_BAT5_ICACHE_INHIBITED=y
CONFIG_BAT5_ICACHE_GUARDED=y
CONFIG_BAT5_DCACHE_INHIBITED=y
CONFIG_BAT5_DCACHE_GUARDED=y
CONFIG_BAT5_USER_MODE_VALID=y
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
CONFIG_BAT6=y
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
CONFIG_BAT6_BASE=0xF0000000
CONFIG_BAT6_LENGTH_256_MBYTES=y
CONFIG_BAT6_ACCESS_RW=y
CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_ICACHE_GUARDED=y
CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_DCACHE_GUARDED=y
CONFIG_BAT6_USER_MODE_VALID=y
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_16_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xF8000000
CONFIG_LBLAW1_NAME="VSC7385"
CONFIG_LBLAW1_LENGTH_128_KBYTES=y
CONFIG_LBLAW3=y
CONFIG_LBLAW3_BASE=0xF0000000
CONFIG_LBLAW3_NAME="CF"
CONFIG_LBLAW3_LENGTH_64_KBYTES=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xFE000000
CONFIG_BR0_PORTSIZE_16BIT=y
CONFIG_OR0_AM_16_MBYTES=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_SCY_15=y
CONFIG_OR0_CSNT_EARLIER=y
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_OR0_EAD_EXTRA=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="VSC7385"
CONFIG_BR1_OR1_BASE=0xF8000000
CONFIG_OR1_AM_128_KBYTES=y
CONFIG_OR1_SCY_15=y
CONFIG_OR1_CSNT_EARLIER=y
CONFIG_OR1_XACS_EXTENDED=y
CONFIG_OR1_SETA_EXTERNAL=y
CONFIG_OR1_TRLX_RELAXED=y
CONFIG_OR1_EHTR_8_CYCLE=y
CONFIG_OR1_EAD_EXTRA=y
CONFIG_ELBC_BR2_OR2=y
CONFIG_BR2_OR2_NAME="LED"
CONFIG_BR2_OR2_BASE=0xF9000000
CONFIG_OR2_AM_2_MBYTES=y
CONFIG_OR2_SCY_9=y
CONFIG_OR2_CSNT_EARLIER=y
CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR2_XACS_EXTENDED=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_8_CYCLE=y
CONFIG_OR2_EAD_EXTRA=y
CONFIG_ELBC_BR3_OR3=y
CONFIG_BR3_OR3_NAME="CF"
CONFIG_BR3_OR3_BASE=0xF0000000
CONFIG_BR3_PORTSIZE_16BIT=y
CONFIG_BR3_MACHINE_UPMA=y
CONFIG_OR3_BI_BURSTINHIBIT=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_SPCR_TSEC1EP_3=y
CONFIG_SPCR_TSEC2EP_3=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200"
CONFIG_MISC_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="MPC8349E-mITX> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SATA=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFE080000
CONFIG_SATA_SIL3114=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
configs/MPC8349ITX_defconfig 已删除 100644 → 0
浏览文件 @ c861d21c
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFEF00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
CONFIG_CORE_PLL_RATIO_2_1=y
CONFIG_PCI_HOST_MODE_ENABLE=y
CONFIG_PCI_INT_ARBITER1_ENABLE=y
CONFIG_PCI_INT_ARBITER2_ENABLE=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
CONFIG_TSEC1_MODE_GMII=y
CONFIG_TSEC2_MODE_GMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="SDRAM"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT1=y
CONFIG_BAT1_NAME="PCI1_MEM"
CONFIG_BAT1_BASE=0x80000000
CONFIG_BAT1_LENGTH_256_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT1_USER_MODE_VALID=y
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
CONFIG_BAT2=y
CONFIG_BAT2_NAME="PCI1_MMIO"
CONFIG_BAT2_BASE=0x90000000
CONFIG_BAT2_LENGTH_256_MBYTES=y
CONFIG_BAT2_ACCESS_RW=y
CONFIG_BAT2_ICACHE_INHIBITED=y
CONFIG_BAT2_ICACHE_GUARDED=y
CONFIG_BAT2_DCACHE_INHIBITED=y
CONFIG_BAT2_DCACHE_GUARDED=y
CONFIG_BAT2_USER_MODE_VALID=y
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
CONFIG_BAT3=y
CONFIG_BAT3_NAME="PCI2_MEM"
CONFIG_BAT3_BASE=0xA0000000
CONFIG_BAT3_LENGTH_256_MBYTES=y
CONFIG_BAT3_ACCESS_RW=y
CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT3_USER_MODE_VALID=y
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
CONFIG_BAT4=y
CONFIG_BAT4_NAME="PCI2_MMIO"
CONFIG_BAT4_BASE=0xB0000000
CONFIG_BAT4_LENGTH_256_MBYTES=y
CONFIG_BAT4_ACCESS_RW=y
CONFIG_BAT4_ICACHE_INHIBITED=y
CONFIG_BAT4_ICACHE_GUARDED=y
CONFIG_BAT4_DCACHE_INHIBITED=y
CONFIG_BAT4_DCACHE_GUARDED=y
CONFIG_BAT4_USER_MODE_VALID=y
CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
CONFIG_BAT5=y
CONFIG_BAT5_NAME="IMMR"
CONFIG_BAT5_BASE=0xE0000000
CONFIG_BAT5_LENGTH_256_MBYTES=y
CONFIG_BAT5_ACCESS_RW=y
CONFIG_BAT5_ICACHE_INHIBITED=y
CONFIG_BAT5_ICACHE_GUARDED=y
CONFIG_BAT5_DCACHE_INHIBITED=y
CONFIG_BAT5_DCACHE_GUARDED=y
CONFIG_BAT5_USER_MODE_VALID=y
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
CONFIG_BAT6=y
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
CONFIG_BAT6_BASE=0xF0000000
CONFIG_BAT6_LENGTH_256_MBYTES=y
CONFIG_BAT6_ACCESS_RW=y
CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_ICACHE_GUARDED=y
CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_DCACHE_GUARDED=y
CONFIG_BAT6_USER_MODE_VALID=y
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_16_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xF8000000
CONFIG_LBLAW1_NAME="VSC7385"
CONFIG_LBLAW1_LENGTH_128_KBYTES=y
CONFIG_LBLAW3=y
CONFIG_LBLAW3_BASE=0xF0000000
CONFIG_LBLAW3_NAME="CF"
CONFIG_LBLAW3_LENGTH_64_KBYTES=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xFE000000
CONFIG_BR0_PORTSIZE_16BIT=y
CONFIG_OR0_AM_16_MBYTES=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_SCY_15=y
CONFIG_OR0_CSNT_EARLIER=y
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_OR0_EAD_EXTRA=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="VSC7385"
CONFIG_BR1_OR1_BASE=0xF8000000
CONFIG_OR1_AM_128_KBYTES=y
CONFIG_OR1_SCY_15=y
CONFIG_OR1_CSNT_EARLIER=y
CONFIG_OR1_XACS_EXTENDED=y
CONFIG_OR1_SETA_EXTERNAL=y
CONFIG_OR1_TRLX_RELAXED=y
CONFIG_OR1_EHTR_8_CYCLE=y
CONFIG_OR1_EAD_EXTRA=y
CONFIG_ELBC_BR2_OR2=y
CONFIG_BR2_OR2_NAME="LED"
CONFIG_BR2_OR2_BASE=0xF9000000
CONFIG_OR2_AM_2_MBYTES=y
CONFIG_OR2_SCY_9=y
CONFIG_OR2_CSNT_EARLIER=y
CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR2_XACS_EXTENDED=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_8_CYCLE=y
CONFIG_OR2_EAD_EXTRA=y
CONFIG_ELBC_BR3_OR3=y
CONFIG_BR3_OR3_NAME="CF"
CONFIG_BR3_OR3_BASE=0xF0000000
CONFIG_BR3_PORTSIZE_16BIT=y
CONFIG_BR3_MACHINE_UPMA=y
CONFIG_OR3_BI_BURSTINHIBIT=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_SPCR_TSEC1EP_3=y
CONFIG_SPCR_TSEC2EP_3=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200"
CONFIG_MISC_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="MPC8349E-mITX> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SATA=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFEF80000
CONFIG_SATA_SIL3114=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
include/configs/MPC8349ITX.h 已删除 100644 → 0
浏览文件 @ c861d21c
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006.
*/
/*
MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
Memory map:
0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
0xF001_0000-0xF001_FFFF Local bus expansion slot
0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
I2C address list:
Align. Board
Bus Addr Part No. Description Length Location
----------------------------------------------------------------
I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
I2C1 0x20 PCF8574 I2C Expander 0 U8
I2C1 0x21 PCF8574 I2C Expander 0 U10
I2C1 0x38 PCF8574A I2C Expander 0 U8
I2C1 0x39 PCF8574A I2C Expander 0 U10
I2C1 0x51 (DDR) DDR EEPROM 1 U1
I2C1 0x68 DS1339 RTC 1 U68
Note that a given board has *either* a pair of 8574s or a pair of 8574As.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* On-board devices
*/
#ifdef CONFIG_TARGET_MPC8349ITX
/* The CF card interface on the back of the board */
#define CONFIG_COMPACT_FLASH
#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
#endif
#include <linux/stringify.h>
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C
/*
* Device configurations
*/
/* I2C */
#ifdef CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
/* Don't probe these addresses: */
#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
{1, CONFIG_SYS_I2C_8574_ADDR2}, \
{1, CONFIG_SYS_I2C_8574A_ADDR1}, \
{1, CONFIG_SYS_I2C_8574A_ADDR2} }
/* Bit definitions for the 8574[A] I2C expander */
/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
#define I2C_8574_REVISION 0x03
#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
#endif
/* Compact Flash */
#ifdef CONFIG_COMPACT_FLASH
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_IDE_MAXDEVICE 1
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
#define CONFIG_SYS_ATA_REG_OFFSET 0
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
#define CONFIG_SYS_ATA_STRIDE 2
/* If a CF card is not inserted, time out quickly */
#define ATA_RESET_TIME 1
#endif
/*
* SATA
*/
#ifdef CONFIG_SATA_SIL3114
#define CONFIG_SYS_SATA_MAX_DEVICE 4
#define CONFIG_LBA48
#endif
#ifdef CONFIG_SYS_USB_HOST
/*
* Support USB
*/
#define CONFIG_USB_EHCI_FSL
/* Current USB implementation supports the only USB controller,
* so we have to choose between the MPH or the DR ones */
#if 1
#define CONFIG_HAS_FSL_MPH_USB
#else
#define CONFIG_HAS_FSL_DR_USB
#endif
#endif
/*
* DDR Setup
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_83XX_DDR_USES_CS0
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
#ifdef CONFIG_SYS_I2C
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
#endif
/* No SPD? Then manually set up DDR parameters */
#ifndef CONFIG_SPD_EEPROM
#define CONFIG_SYS_DDR_SIZE 256 /* Mb */
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_1 0x26242321
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
#endif
/*
*Flash on the Local Bus
*/
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* 127 64KB sectors + 8 8KB sectors per device */
#define CONFIG_SYS_MAX_FLASH_SECT 135
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
/* The ITX has two flash chips, but the ITX-GP has only one. To support both
boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_FLASH_BANKS_LIST \
{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
/* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE 0xFEFFE000
#define CONFIG_VSC7385_IMAGE_SIZE 8192
#endif
/*
* BRx, ORx, LBLAWBARx, and LBLAWARx
*/
/* Vitesse 7385 */
#define CONFIG_SYS_VSC7385_BASE 0xF8000000
#define CONFIG_SYS_LED_BASE 0xF9000000
/* Compact Flash */
#ifdef CONFIG_COMPACT_FLASH
#define CONFIG_SYS_CF_BASE 0xF0000000
#endif
/*
* U-Boot memory configuration
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
/*
* Serial Port
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONSOLE ttyS0
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
/*
* PCI
*/
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_MPC83XX_PCI2
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE \
(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
#ifdef CONFIG_MPC83XX_PCI2
#define CONFIG_SYS_PCI2_MEM_BASE \
(CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI2_MMIO_BASE \
(CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS \
(CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
#endif
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR 0x00000000
#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
#define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
/* TSEC */
#ifdef CONFIG_TSEC_ENET
#define CONFIG_TSEC1
#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
#define TSEC1_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#endif
#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define TSEC2_PHY_ADDR 4
#define TSEC2_PHYIDX 0
#define TSEC2_FLAGS TSEC_GIGABIT
#endif
#define CONFIG_ETHPRIME "Freescale TSEC"
#endif
/*
* Environment
*/
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
/* Watchdog */
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
/*
* System performance
*/
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
/*
* System IO Config
*/
/* Needed for gigabit to work on TSEC 1 */
#define CONFIG_SYS_SICRH SICRH_TSOBI1
/* USB DR as device + USB MPH as host */
#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
/*
* Environment Configuration
*/
#define CONFIG_NETDEV "eth0"
/* Default path and filenames */
#define CONFIG_ROOTPATH "/nfsroot/rootfs"
#define CONFIG_BOOTFILE "uImage"
/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH "u-boot.bin"
#ifdef CONFIG_TARGET_MPC8349ITX
#define CONFIG_FDTFILE "mpc8349emitx.dtb"
#else
#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=" __stringify(CONSOLE) "\0" \
"netdev=" CONFIG_NETDEV "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
" $filesize; " \
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
" $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" CONFIG_FDTFILE "\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
" console=$console,$baudrate $othbootargs; " \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw" \
" console=$console,$baudrate $othbootargs; " \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#endif
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