diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 97f155daa1abf9d90479ee8466ed54273780f94c..457c4b8ba69fee567e4f652ba7c84e095e047480 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -13,6 +13,7 @@ void reset_deassert_peripherals_handoff(void);
 void socfpga_bridges_reset(int enable);
 
 void socfpga_per_reset(u32 reset, int set);
+void socfpga_per_reset_all(void);
 
 struct socfpga_reset_manager {
 	u32	status;
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 6a11c19200d7c72d94e3706627096e2d2573d00a..1186358a71a3259715173ad95ac4fb74a656db70 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -39,6 +39,19 @@ void socfpga_per_reset(u32 reset, int set)
 		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
 }
 
+/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ */
+void socfpga_per_reset_all(void)
+{
+	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
+
+	writel(~l4wd0, &reset_manager_base->per_mod_reset);
+	writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+}
+
 /*
  * Write the reset manager register to cause reset
  */