diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index dd9268fbf209c54f68bf65ee7519ca5fd8f9787d..38d019056a29df27fdbb2d01c43c84e244c7381c 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -216,22 +216,45 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_MSMC_CTRL_BASE		0x0bc00000
 #define KS2_MSMC_DATA_BASE		0x0c000000
 
+/* KS2 Generic Privilege ID Settings for MSMC2 */
+#define KS2_MSMC_SEGMENT_C6X_0		0
+#define KS2_MSMC_SEGMENT_C6X_1		1
+#define KS2_MSMC_SEGMENT_C6X_2		2
+#define KS2_MSMC_SEGMENT_C6X_3		3
+#define KS2_MSMC_SEGMENT_C6X_4		4
+#define KS2_MSMC_SEGMENT_C6X_5		5
+#define KS2_MSMC_SEGMENT_C6X_6		6
+#define KS2_MSMC_SEGMENT_C6X_7		7
+
+#define KS2_MSMC_SEGMENT_DEBUG		12
+
 /* KS2 HK/L/E MSMC PRIVIDs  for MSMC2 */
 #define K2HKLE_MSMC_SEGMENT_ARM		8
 #define K2HKLE_MSMC_SEGMENT_NETCP	9
 #define K2HKLE_MSMC_SEGMENT_QM_PDSP	10
 #define K2HKLE_MSMC_SEGMENT_PCIE0	11
 
+/* K2HK specific Privilege ID Settings */
+#define K2HKE_MSMC_SEGMENT_HYPERLINK	14
+
 /* K2L specific Privilege ID Settings */
 #define K2L_MSMC_SEGMENT_PCIE1		14
 
 /* K2E specific Privilege ID Settings */
 #define K2E_MSMC_SEGMENT_PCIE1		13
+#define K2E_MSMC_SEGMENT_TSIP		15
 
 /* K2G specific Privilege ID Settings */
 #define K2G_MSMC_SEGMENT_ARM		1
+#define K2G_MSMC_SEGMENT_ICSS0		2
+#define K2G_MSMC_SEGMENT_ICSS1		3
 #define K2G_MSMC_SEGMENT_NSS		4
 #define K2G_MSMC_SEGMENT_PCIE		5
+#define K2G_MSMC_SEGMENT_USB		6
+#define K2G_MSMC_SEGMENT_MLB		8
+#define K2G_MSMC_SEGMENT_PMMC		9
+#define K2G_MSMC_SEGMENT_DSS		10
+#define K2G_MSMC_SEGMENT_MMC		11
 
 /* MSMC segment size shift bits */
 #define KS2_MSMC_SEG_SIZE_SHIFT		12
diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index 2368315ff68ca09834a47615cabd748976f11031..3b6d5efce1a1386f2203d5e75b0e46892612e47f 100644
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -98,29 +98,57 @@ static void config_pcie_mode(int pcie_port,  enum pci_mode mode)
 
 static void msmc_k2hkle_common_setup(void)
 {
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
 	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
 	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
 #ifdef KS2_MSMC_SEGMENT_QM_PDSP
 	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
 #endif
 	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
+}
+
+static void msmc_k2hk_setup(void)
+{
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
+	msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
 }
 
 static inline void msmc_k2l_setup(void)
 {
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
 	msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
 }
 
 static inline void msmc_k2e_setup(void)
 {
 	msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
+	msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
+	msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
 }
 
-static inline void msmc_k2g_setup(void)
+static void msmc_k2g_setup(void)
 {
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
 	msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
+	msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
+	msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
 	msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
 	msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
+	msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
+	msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
+	msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
+	msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
+	msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
 }
 
 int arch_cpu_init(void)
@@ -136,6 +164,8 @@ int arch_cpu_init(void)
 			msmc_k2e_setup();
 		else if (cpu_is_k2l())
 			msmc_k2l_setup();
+		else
+			msmc_k2hk_setup();
 	}
 
 	/* Initialize the PCIe-0 to work as Root Complex */