提交 1d2c2a62 编写于 作者: K Kumar Gala

powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)

CoreNet Platform Cache single-bit tag error scrubbing will cause tag
corruption.  Disable the feature to workaround the issue.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
上级 7c57f3e8
...@@ -59,6 +59,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ...@@ -59,6 +59,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136) #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
puts("Work-around for Erratum ESDHC136 enabled\n"); puts("Work-around for Erratum ESDHC136 enabled\n");
#endif #endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
puts("Work-around for Erratum CPC-A002 enabled\n");
#endif
return 0; return 0;
} }
......
...@@ -142,6 +142,10 @@ static void enable_cpc(void) ...@@ -142,6 +142,10 @@ static void enable_cpc(void)
u32 cpccfg0 = in_be32(&cpc->cpccfg0); u32 cpccfg0 = in_be32(&cpc->cpccfg0);
size += CPC_CFG0_SZ_K(cpccfg0); size += CPC_CFG0_SZ_K(cpccfg0);
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
#endif
out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
/* Read back to sync write */ /* Read back to sync write */
in_be32(&cpc->cpccsr0); in_be32(&cpc->cpccsr0);
......
/* /*
* MPC85xx Internal Memory Map * MPC85xx Internal Memory Map
* *
* Copyright 2007-2010 Freescale Semiconductor, Inc. * Copyright 2007-2011 Freescale Semiconductor, Inc.
* *
* Copyright(c) 2002,2003 Motorola Inc. * Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com) * Xianghua Xiao (x.xiao@motorola.com)
...@@ -1619,6 +1619,7 @@ typedef struct cpc_corenet { ...@@ -1619,6 +1619,7 @@ typedef struct cpc_corenet {
#define CPC_SRCR0_SRAMEN 0x00000001 #define CPC_SRCR0_SRAMEN 0x00000001
#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
#endif /* CONFIG_SYS_FSL_CPC */ #endif /* CONFIG_SYS_FSL_CPC */
/* Global Utilities Block */ /* Global Utilities Block */
......
...@@ -40,6 +40,7 @@ ...@@ -40,6 +40,7 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC136 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136
#define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_CPU22
#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
#define CONFIG_SYS_P4080_ERRATUM_SERDES8 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
#include "corenet_ds.h" #include "corenet_ds.h"
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