board_f: Drop return value from initdram()

At present we cannot use this function as an init sequence call without a
wrapper, since it returns the RAM size. Adjust it to set the RAM size in
global_data instead, and return 0 on success.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NStefan Roese <sr@denx.de>

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -874,7 +874,7 @@ void update_early_mmu_table(void)
 
 __weak int dram_init(void)
 {
-	gd->ram_size = initdram();
+	initdram();
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 	/* This will break-before-make MMU for DDR */
 	update_early_mmu_table();

arch/mips/mach-ath79/dram.c

@@ -9,8 +9,12 @@
 #include <asm/addrspace.h>
 #include <mach/ddr.h>
 
-phys_size_t initdram(void)
+DECLARE_GLOBAL_DATA_PTR;
+
+int initdram(void)
 {
 	ddr_tap_tuning();
-	return get_ram_size((void *)KSEG1, SZ_256M);
+	gd->ram_size = get_ram_size((void *)KSEG1, SZ_256M);
+
+	return 0;
 }

arch/mips/mach-pic32/cpu.c

@@ -110,12 +110,14 @@ static void ddr2_pmd_ungate(void)
 }
 
 /* initialize the DDR2 Controller and DDR2 PHY */
-phys_size_t initdram(void)
+int initdram(void)
 {
 	ddr2_pmd_ungate();
 	ddr2_phy_init();
 	ddr2_ctrl_init();
-	return ddr2_calculate_size();
+	gd->ram_size = ddr2_calculate_size();
+
+	return 0;
 }
 
 int misc_init_r(void)

arch/powerpc/cpu/mpc85xx/cpu.c

@@ -401,17 +401,19 @@ void mpc85xx_reginfo(void)
 #ifndef CONFIG_FSL_CORENET
 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
 	!defined(CONFIG_SYS_INIT_L2_ADDR)
-phys_size_t initdram(void)
+int initdram(void)
 {
 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
 	defined(CONFIG_ARCH_QEMU_E500)
-	return fsl_ddr_sdram_size();
+	gd->ram_size = fsl_ddr_sdram_size();
 #else
-	return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 #endif
+
+	return 0;
 }
 #else /* CONFIG_SYS_RAMBOOT */
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size = 0;
 
@@ -460,7 +462,9 @@ phys_size_t initdram(void)
 #endif
 
 	debug("DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 #endif /* CONFIG_SYS_RAMBOOT */
 #endif

arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c

@@ -33,6 +33,8 @@
 
 #include "ecc.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)				\
 	do {								\
 		u32 data;						\
@@ -414,7 +416,7 @@ static unsigned char spd_read(uchar chip, uint addr)
  *		 banks appropriately. If Auto Memory Configuration is
  *		 not used, it is assumed that no DIMM is plugged
  *-----------------------------------------------------------------------------*/
-phys_size_t initdram(void)
+int initdram(void)
 {
 	unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 	unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
@@ -429,7 +431,9 @@ phys_size_t initdram(void)
 		 * Reduce RAM size to avoid overwriting memory used by
 		 * current stack? Not sure what is happening.
 		 */
-		return sdram_memsize() / 2;
+		gd->ram_size = sdram_memsize() / 2;
+
+		return 0;
 	}
 
 	num_dimm_banks = sizeof(iic0_dimm_addr);
@@ -650,7 +654,9 @@ phys_size_t initdram(void)
 	 */
 	set_mcsr(get_mcsr());
 
-	return sdram_memsize();
+	gd->ram_size = sdram_memsize();
+
+	return 0;
 }
 
 static void get_spd_info(unsigned long *dimm_populated,
@@ -2855,7 +2861,7 @@ static void test(void)
  *		time parameters.
  * 		Configures the PPC405EX(r) and PPC460EX/GT
  *---------------------------------------------------------------------------*/
-phys_size_t initdram(void)
+int initdram(void)
 {
 	unsigned long val;
 
@@ -3011,7 +3017,9 @@ phys_size_t initdram(void)
 	set_mcsr(get_mcsr());
 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
 
-	return (CONFIG_SYS_MBYTES_SDRAM << 20);
+	gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
+
+	return 0;
 }
 #endif /* CONFIG_SPD_EEPROM */
 

arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c

@@ -30,6 +30,8 @@
 #include <asm/mmu.h>
 #include <asm/cache.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_SPD_EEPROM) &&				\
 	(defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
 
@@ -998,7 +1000,7 @@ static void program_ddr0_44(unsigned long dimm_ranks[],
  *		 banks appropriately. If Auto Memory Configuration is
  *		 not used, it is assumed that no DIMM is plugged
  *-----------------------------------------------------------------------------*/
-phys_size_t initdram(void)
+int initdram(void)
 {
 	unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 	unsigned long dimm_ranks[MAXDIMMS];
@@ -1212,7 +1214,9 @@ phys_size_t initdram(void)
 #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
 
 	program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 void board_add_ram_info(int use_default)

arch/powerpc/cpu/ppc4xx/sdram.c

@@ -17,6 +17,8 @@
 #include "sdram.h"
 #include "ecc.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_SDRAM_BANK0
 
 #ifndef CONFIG_440
@@ -148,7 +150,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
 /*
  * Autodetect onboard SDRAM on 405 platforms
  */
-phys_size_t initdram(void)
+int initdram(void)
 {
 	ulong speed;
 	ulong sdtr1;
@@ -226,11 +228,13 @@ phys_size_t initdram(void)
 			/*
 			 * OK, size detected -> all done
 			 */
-			return size;
+			gd->ram_size = size;
+
+			return 0;
 		}
 	}
 
-	return 0;
+	return -ENXIO;
 }
 
 #else /* CONFIG_440 */
@@ -349,7 +353,7 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
  *	 so this should be extended for other future boards
  *	 using this routine!
  */
-phys_size_t initdram(void)
+int initdram(void)
 {
 	int i;
 	int tr1_bank1;
@@ -440,11 +444,13 @@ phys_size_t initdram(void)
 			/*
 			 * OK, size detected -> all done
 			 */
-			return size;
+			gd->ram_size = size;
+
+			return 0;
 		}
 	}
 
-	return 0;				/* nothing found !		*/
+	return -ENXIO;			/* nothing found !		*/
 }
 
 #endif /* CONFIG_440 */

board/Arcturus/ucp1020/spl.c

@@ -110,7 +110,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	gd->ram_size = initdram();
+	initdram();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else

board/BuS/eb_cpu5282/eb_cpu5282.c

@@ -35,7 +35,7 @@ int checkboard (void)
 	return 0;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	int size, i;
 
@@ -92,7 +92,9 @@ phys_size_t initdram(void)
 	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
 	size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
 #endif
-	return size;
+	gd->ram_size = size;
+
+	return 0;
 }
 
 #if defined(CONFIG_SYS_DRAM_TEST)

board/a3m071/a3m071.c

@@ -76,7 +76,7 @@ static void sdram_start(int hi_addr)
  * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  */
-phys_size_t initdram(void)
+int initdram(void)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
@@ -153,7 +153,9 @@ phys_size_t initdram(void)
 	if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
 		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
 
-	return dramsize + dramsize2;
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
 }
 
 static void get_revisions(int *failsavelevel, int *digiboardversion,

board/a4m072/a4m072.c

@@ -23,6 +23,8 @@
 
 #include "mt46v32m16.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
@@ -71,7 +73,7 @@ static void sdram_start (int hi_addr)
  *            is something else than 0x00000000.
  */
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	ulong dramsize = 0;
 	uint svr, pvr;
@@ -150,7 +152,9 @@ phys_size_t initdram(void)
 		__asm__ volatile ("sync");
 	}
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 }
 
 int checkboard (void)

board/amcc/acadia/memory.c

@@ -15,6 +15,8 @@
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern void board_pll_init_f(void);
 
 static void cram_bcr_write(u32 wr_val)
@@ -41,7 +43,7 @@ static void cram_bcr_write(u32 wr_val)
 	return;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	int i;
 	u32 val;
@@ -77,5 +79,7 @@ phys_size_t initdram(void)
 	for (i=0; i<200000; i++)
 		;
 
-	return (CONFIG_SYS_MBYTES_RAM << 20);
+	gd->ram_size = CONFIG_SYS_MBYTES_RAM << 20;
+
+	return 0;
 }

board/amcc/bamboo/bamboo.c

@@ -12,6 +12,8 @@
 #include <asm/ppc440.h>
 #include "bamboo.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void ext_bus_cntlr_init(void);
 void configure_ppc440ep_pins(void);
 int is_nand_selected(void);
@@ -436,9 +438,11 @@ int checkboard(void)
 }
 
 
-phys_size_t initdram(void)
+int initdram(void)
 {
-	return spd_sdram();
+	gd->ram_size = spd_sdram();
+
+	return 0;
 }
 
 /*----------------------------------------------------------------------------+

board/amcc/bubinga/bubinga.c

@@ -9,6 +9,8 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 long int spd_sdram(void);
 
 int board_early_init_f(void)
@@ -55,7 +57,9 @@ int checkboard(void)
   initdram() reads EEPROM via I2c. EEPROM contains all of
   the necessary info for SDRAM controller configuration
    ------------------------------------------------------------------------- */
-phys_size_t initdram(void)
+int initdram(void)
 {
-	return spd_sdram();
+	gd->ram_size = spd_sdram();
+
+	return 0;
 }

board/amcc/sequoia/sdram.c

@@ -20,6 +20,8 @@
 #include <asm/io.h>
 #include <asm/ppc440.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*-----------------------------------------------------------------------------+
  * Prototypes
  *-----------------------------------------------------------------------------*/
@@ -31,7 +33,7 @@ extern void denali_core_search_data_eye(void);
  * initdram -- 440EPx's DDR controller is a DENALI Core
  *
  ************************************************************************/
-phys_size_t initdram(void)
+int initdram(void)
 {
 #if !defined(CONFIG_SYS_RAMBOOT)
 	ulong speed = get_bus_freq(0);
@@ -88,5 +90,7 @@ phys_size_t initdram(void)
 	 */
 	set_mcsr(get_mcsr());
 
-	return (CONFIG_SYS_MBYTES_SDRAM << 20);
+	gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
+
+	return 0;
 }

board/amcc/walnut/walnut.c

@@ -9,6 +9,8 @@
 #include <asm/processor.h>
 #include <spd_sdram.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int board_early_init_f(void)
 {
 	/*-------------------------------------------------------------------------+
@@ -74,7 +76,9 @@ int checkboard(void)
  * initdram() reads EEPROM via I2c. EEPROM contains all of
  * the necessary info for SDRAM controller configuration
  */
-phys_size_t initdram(void)
+int initdram(void)
 {
-	return spd_sdram();
+	gd->ram_size = spd_sdram();
+
+	return 0;
 }

board/amcc/yosemite/yosemite.c

@@ -286,7 +286,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
 	*tr1_value = (first_good + last_bad) / 2;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	register uint reg;
 	int tr1_bank1, tr1_bank2;
@@ -334,7 +334,10 @@ phys_size_t initdram(void)
 	sdram_tr1_set(0x08000000, &tr1_bank2);
 	mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
 
-	return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024);	/* return bytes */
+	gd->ram_size = CONFIG_SYS_SDRAM_BANKS *
+		(CONFIG_SYS_KBYTES_SDRAM * 1024);	/* set bytes */
+
+	return 0;
 }
 
 /*************************************************************************

board/astro/mcf5373l/mcf5373l.c

@@ -27,7 +27,7 @@ int checkboard(void)
 	return 0;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
 	sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
@@ -79,8 +79,10 @@ phys_size_t initdram(void)
 	 * (Do not rely on the SDCS register(s) being set to 0x00000000
 	 * during reset as stated in the data sheet.)
 	 */
-	return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				0x80000000 - CONFIG_SYS_SDRAM_BASE);
+
+	return 0;
 }
 
 #define UART_BASE MMAP_UART0

board/canmb/canmb.c

@@ -18,6 +18,8 @@
 #include "mt48lc16m32s2-75.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
@@ -65,7 +67,7 @@ static void sdram_start (int hi_addr)
  *            is something else than 0x00000000.
  */
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
@@ -163,7 +165,9 @@ phys_size_t initdram(void)
 
 #endif /* CONFIG_SYS_RAMBOOT */
 
-	return dramsize + dramsize2;
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
 }
 
 int checkboard (void)

board/cm5200/cm5200.c

@@ -97,7 +97,7 @@ static mem_conf_t* get_mem_config(int board_type)
 /*
  * Initalize SDRAM - configure SDRAM controller, detect memory size.
  */
-phys_size_t initdram(void)
+int initdram(void)
 {
 	ulong dramsize = 0;
 #ifndef CONFIG_SYS_RAMBOOT
@@ -150,7 +150,9 @@ phys_size_t initdram(void)
 	*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
 	__asm__ volatile ("sync");
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 }
 
 

board/cobra5272/cobra5272.c

@@ -8,6 +8,7 @@
 #include <common.h>
 #include <asm/immap.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard (void)
 {
@@ -16,7 +17,7 @@ int checkboard (void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
 
@@ -26,7 +27,9 @@ phys_size_t initdram(void)
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *) 0) = 0;
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 };
 
 int testdram (void)

board/davedenx/aria/aria.c

@@ -18,9 +18,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-phys_size_t initdram(void)
+int initdram(void)
 {
-	return fixed_sdram(NULL, NULL, 0);
+	gd->ram_size = fixed_sdram(NULL, NULL, 0);
+
+	return 0;
 }
 
 int misc_init_r(void)

board/dbau1x00/dbau1x00.c

@@ -11,11 +11,15 @@
 #include <asm/mipsregs.h>
 #include <asm/io.h>
 
-phys_size_t initdram(void)
+DECLARE_GLOBAL_DATA_PTR;
+
+int initdram(void)
 {
 	/* Sdram is setup by assembler code */
 	/* If memory could be changed, we should return the true value here */
-	return MEM_SIZE*1024*1024;
+	gd->ram_size = MEM_SIZE * 1024 * 1024;
+
+	return 0;
 }
 
 #define BCSR_PCMCIA_PC0DRVEN		0x0010

board/esd/mecp5123/mecp5123.c

@@ -62,9 +62,11 @@ int board_early_init_f(void)
 	return 0;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
-	return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
+	gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0));
+
+	return 0;
 }
 
 int misc_init_r(void)

board/esd/pmc440/sdram.c

@@ -24,6 +24,8 @@
 #include <asm/mmu.h>
 #include <asm/ppc440.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern int denali_wait_for_dlllock(void);
 extern void denali_core_search_data_eye(void);
 
@@ -105,7 +107,7 @@ int initdram_by_rb(int rows, int banks)
 	return 0;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t size;
 	int n;
@@ -125,12 +127,14 @@ phys_size_t initdram(void)
 			       sdram_conf[n].banks);
 
 		/* check for suitable configuration */
-		if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size)
-			return size;
+		if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size) {
+			gd->ram_size = size;
+			return 0;
+		}
 
 		/* delete TLB entries */
 		remove_tlb(CONFIG_SYS_SDRAM_BASE, size);
 	}
 
-	return 0;
+	return -ENXIO;
 }

board/esd/vme8349/vme8349.c

@@ -26,15 +26,17 @@
 #include <i2c.h>
 #include <netdev.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void ddr_enable_ecc(unsigned int dram_size);
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main memory */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
@@ -52,7 +54,9 @@ phys_size_t initdram(void)
 	msize = get_ram_size(0, msize);
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize * 1024 * 1024;
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 int checkboard(void)

board/freescale/b4860qds/ddr.c

@@ -176,7 +176,7 @@ found:
 	popts->cpo_sample = 0x3e;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -189,7 +189,9 @@ phys_size_t initdram(void)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,

board/freescale/b4860qds/spl.c

@@ -108,7 +108,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	puts("\n\n");
 
-	gd->ram_size = initdram();
+	initdram();
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_boot();

board/freescale/c29xpcie/spl.c

@@ -67,7 +67,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram();
+	initdram();
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("TPL\n");

board/freescale/corenet_ds/ddr.c

@@ -260,7 +260,7 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -278,5 +278,7 @@ phys_size_t initdram(void)
 	dram_size *= 0x100000;
 
 	debug("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }

board/freescale/ls1021aqds/ddr.c

@@ -164,7 +164,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -179,7 +179,9 @@ phys_size_t initdram(void)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 void dram_init_banksize(void)

board/freescale/ls1021aqds/ls1021aqds.c

@@ -162,9 +162,7 @@ int dram_init(void)
 	 * before accessing DDR SPD.
 	 */
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-	gd->ram_size = initdram();
-
-	return 0;
+	return initdram();
 }
 
 #ifdef CONFIG_FSL_ESDHC

board/freescale/ls1043aqds/ddr.c

@@ -108,7 +108,7 @@ found:
 #endif
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -125,5 +125,7 @@ phys_size_t initdram(void)
 	fsl_dp_ddr_restore();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }

board/freescale/ls1043aqds/ls1043aqds.c

@@ -153,7 +153,7 @@ int dram_init(void)
 	 * before accessing DDR SPD.
 	 */
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-	gd->ram_size = initdram();
+	initdram();
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 	/* This will break-before-make MMU for DDR */
 	update_early_mmu_table();

board/freescale/ls1043ardb/ddr.c

@@ -170,7 +170,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 }
 #endif
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -186,5 +186,7 @@ phys_size_t initdram(void)
 	fsl_dp_ddr_restore();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }

board/freescale/ls1046aqds/ddr.c

@@ -92,7 +92,7 @@ found:
 	popts->cpo_sample = 0x70;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -110,5 +110,7 @@ phys_size_t initdram(void)
 
 	erratum_a008850_post();
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }

board/freescale/ls1046aqds/ls1046aqds.c

@@ -149,7 +149,7 @@ int dram_init(void)
 	 * before accessing DDR SPD.
 	 */
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-	gd->ram_size = initdram();
+	initdram();
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 	/* This will break-before-make MMU for DDR */
 	update_early_mmu_table();

board/freescale/ls1046ardb/ddr.c

@@ -96,7 +96,7 @@ found:
 	popts->cpo_sample = 0x70;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -110,5 +110,7 @@ phys_size_t initdram(void)
 
 	erratum_a008850_post();
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }

board/freescale/ls2080a/ddr.c

@@ -158,14 +158,12 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 	return 0;
 }
 #endif
-phys_size_t initdram(void)
+int initdram(void)
 {
-	phys_size_t dram_size;
-
 	puts("Initializing DDR....");
 
 	puts("using SPD\n");
-	dram_size = fsl_ddr_sdram();
+	gd->ram_size = fsl_ddr_sdram();
 
-	return dram_size;
+	return 0;
 }

board/freescale/ls2080aqds/ddr.c

@@ -155,17 +155,15 @@ found:
 	}
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
-	phys_size_t dram_size;
-
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-	return fsl_ddr_sdram_size();
+	gd->ram_size = fsl_ddr_sdram_size();
 #else
 	puts("Initializing DDR....using SPD\n");
 
-	dram_size = fsl_ddr_sdram();
+	gd->ram_size = fsl_ddr_sdram();
 #endif
 
-	return dram_size;
+	return 0;
 }

board/freescale/ls2080ardb/ddr.c

@@ -158,17 +158,15 @@ found:
 	}
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
-	phys_size_t dram_size;
-
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-	return fsl_ddr_sdram_size();
+	gd->ram_size = fsl_ddr_sdram_size();
 #else
 	puts("Initializing DDR....using SPD\n");
 
-	dram_size = fsl_ddr_sdram();
+	gd->ram_size = fsl_ddr_sdram();
 #endif
 
-	return dram_size;
+	return 0;
 }

board/freescale/m5208evbe/m5208evbe.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
@@ -68,7 +68,9 @@ phys_size_t initdram(void)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)

board/freescale/m52277evb/m52277evb.c

@@ -21,7 +21,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	u32 dramsize;
 
@@ -78,7 +78,9 @@ phys_size_t initdram(void)
 
 	udelay(100);
 #endif
-	return (dramsize);
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)

board/freescale/m5235evb/m5235evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
@@ -97,7 +97,9 @@ phys_size_t initdram(void)
 		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
 	}
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)

board/freescale/m5249evb/m5249evb.c

@@ -10,6 +10,8 @@
 #include <malloc.h>
 #include <asm/immap.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard (void) {
 	ulong val;
 	uchar val8;
@@ -29,7 +31,7 @@ int checkboard (void) {
 };
 
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	unsigned long	junk = 0xa5a59696;
 
@@ -82,7 +84,9 @@ phys_size_t initdram(void)
 	mbar_writeLong(MCFSIM_DACR0, 0x0000b364);  /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
 	*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 };
 
 

board/freescale/m5253demo/m5253demo.c

@@ -13,6 +13,8 @@
 #include <netdev.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard(void)
 {
 	puts("Board: ");
@@ -20,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	u32 dramsize = 0;
 
@@ -73,7 +75,9 @@ phys_size_t initdram(void)
 		mb();
 	}
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 }
 
 int testdram(void)

board/freescale/m5253evbe/m5253evbe.c

@@ -12,6 +12,8 @@
 #include <asm/immap.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard(void)
 {
 	puts("Board: ");
@@ -19,7 +21,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	/*
 	 * Check to see if the SDRAM has already been initialized
@@ -66,7 +68,9 @@ phys_size_t initdram(void)
 		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
 	}
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 }
 
 int testdram(void)

board/freescale/m5272c3/m5272c3.c

@@ -11,6 +11,7 @@
 #include <asm/immap.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard (void) {
 	puts ("Board: ");
@@ -18,7 +19,7 @@ int checkboard (void) {
 	return 0;
 	};
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
 
@@ -28,7 +29,9 @@ phys_size_t initdram(void)
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *)0) = 0;
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 	};
 
 int testdram (void) {

board/freescale/m5275evb/m5275evb.c

@@ -13,6 +13,8 @@
 #include <asm/immap.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PERIOD		13	/* system bus period in ns */
 #define SDRAM_TREFI	7800	/* in ns */
 
@@ -23,7 +25,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
 	gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
@@ -88,7 +90,9 @@ phys_size_t initdram(void)
 		| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
 		| MCF_SDRAMC_SDCR_DQS_OE(0x3));
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 };
 
 int testdram(void)

board/freescale/m5282evb/m5282evb.c

@@ -16,7 +16,7 @@ int checkboard (void)
 	return 0;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	u32 dramsize, i, dramclk;
 
@@ -80,5 +80,7 @@ phys_size_t initdram(void)
 		/* Write to the SDRAM Mode Register */
 		*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
 	}
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 }

board/freescale/m53017evb/m53017evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
@@ -68,7 +68,9 @@ phys_size_t initdram(void)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)

board/freescale/m5329evb/m5329evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
@@ -62,7 +62,9 @@ phys_size_t initdram(void)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)

board/freescale/m5373evb/m5373evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
@@ -62,7 +62,9 @@ phys_size_t initdram(void)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)

board/freescale/m54418twr/m54418twr.c

@@ -25,7 +25,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	u32 dramsize;
 
@@ -104,7 +104,9 @@ phys_size_t initdram(void)
 
 	udelay(100);
 #endif
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)

board/freescale/m54451evb/m54451evb.c

@@ -26,7 +26,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	u32 dramsize;
 #ifdef CONFIG_CF_SBF
@@ -82,7 +82,9 @@ phys_size_t initdram(void)
 
 	udelay(100);
 #endif
-	return (dramsize);
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)

board/freescale/m54455evb/m54455evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	u32 dramsize;
 #ifdef CONFIG_CF_SBF
@@ -75,7 +75,9 @@ phys_size_t initdram(void)
 
 	udelay(100);
 #endif
-	return (dramsize << 1);
+	gd->ram_size = dramsize << 1;
+
+	return 0;
 };
 
 int testdram(void)

board/freescale/m547xevb/m547xevb.c

@@ -23,7 +23,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	siu_t *siu = (siu_t *) (MMAP_SIU);
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
@@ -79,7 +79,9 @@ phys_size_t initdram(void)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)

board/freescale/m548xevb/m548xevb.c

@@ -23,7 +23,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	siu_t *siu = (siu_t *) (MMAP_SIU);
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
@@ -79,7 +79,9 @@ phys_size_t initdram(void)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)

board/freescale/mpc5121ads/mpc5121ads.c

@@ -95,7 +95,7 @@ int is_micron(void){
 	return(ismicron);
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	u32 msize = 0;
 	/*
@@ -167,7 +167,9 @@ phys_size_t initdram(void)
 				sizeof(elpida_init_sequence)/sizeof(u32));
 	}
 
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }
 
 int misc_init_r(void)

board/freescale/mpc8308rdb/sdram.c

@@ -65,17 +65,19 @@ static long fixed_sdram(void)
 	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;
 
 	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM */
 	msize = fixed_sdram();
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }

board/freescale/mpc8313erdb/sdram.c

@@ -97,14 +97,14 @@ static long fixed_sdram(void)
 	return msize;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile fsl_lbc_t *lbc = &im->im_lbc;
 	u32 msize;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	msize = fixed_sdram();
@@ -120,5 +120,7 @@ phys_size_t initdram(void)
 #endif
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }

board/freescale/mpc8315erdb/sdram.c

@@ -92,13 +92,13 @@ static long fixed_sdram(void)
 }
 #endif /* CONFIG_SYS_RAMBOOT */
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM */
 	msize = fixed_sdram();
@@ -106,6 +106,8 @@ phys_size_t initdram(void)
 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
 		resume_from_sleep();
 
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
 }

board/freescale/mpc8323erdb/mpc8323erdb.c

@@ -21,6 +21,8 @@
 #endif
 #include <asm/mmu.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* UCC3 */
 	{1,  0, 1, 0, 1}, /* TxD0 */
@@ -68,21 +70,23 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 
 int fixed_sdram(void);
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 
 	msize = fixed_sdram();
 
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return (msize * 1024 * 1024);
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 /*************************************************************************

board/freescale/mpc832xemds/mpc832xemds.c

@@ -23,6 +23,8 @@
 #include "../common/pq-mds-pib.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* ETH3 */
 	{1,  0, 1, 0, 1}, /* TxD0 */
@@ -88,21 +90,23 @@ int board_early_init_r(void)
 
 int fixed_sdram(void);
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 
 	msize = fixed_sdram();
 
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return (msize * 1024 * 1024);
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 /*************************************************************************

board/freescale/mpc8349emds/mpc8349emds.c

@@ -22,6 +22,8 @@
 #include <libfdt.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int fixed_sdram(void);
 void sdram_init(void);
 
@@ -46,13 +48,13 @@ int board_early_init_f (void)
 
 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	phys_size_t msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
@@ -73,8 +75,10 @@ phys_size_t initdram(void)
 	 */
 	sdram_init();
 
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
 }
 
 #if !defined(CONFIG_SPD_EEPROM)

board/freescale/mpc8349itx/mpc8349itx.c

@@ -20,6 +20,8 @@
 #include <libfdt.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SPD_EEPROM
 /*************************************************************************
  *  fixed sdram init -- doesn't use serial presence detect.
@@ -116,7 +118,7 @@ volatile static struct pci_controller hose[] = {
 };
 #endif				/* CONFIG_PCI */
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
@@ -125,7 +127,7 @@ phys_size_t initdram(void)
 #endif
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
@@ -144,7 +146,9 @@ phys_size_t initdram(void)
 #endif
 
 	/* return total bus RAM size(bytes) */
-	return msize * 1024 * 1024;
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 int checkboard(void)

board/freescale/mpc837xemds/mpc837xemds.c

@@ -20,6 +20,8 @@
 #include "pci.h"
 #include "../common/pq-mds-pib.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int board_early_init_f(void)
 {
 	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
@@ -216,13 +218,13 @@ extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 int fixed_sdram(void);
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 #if defined(CONFIG_SPD_EEPROM)
 	msize = spd_sdram();
@@ -236,7 +238,9 @@ phys_size_t initdram(void)
 #endif
 
 	/* return total bus DDR size(bytes) */
-	return (msize * 1024 * 1024);
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 #if !defined(CONFIG_SPD_EEPROM)

board/freescale/mpc837xerdb/mpc837xerdb.c

@@ -16,6 +16,8 @@
 #include <vsc7385.h>
 #include <fsl_esdhc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_SYS_DRAM_TEST)
 int
 testdram(void)
@@ -60,13 +62,13 @@ void ddr_enable_ecc(unsigned int dram_size);
 #endif
 int fixed_sdram(void);
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 #if defined(CONFIG_SPD_EEPROM)
 	msize = spd_sdram();
@@ -79,7 +81,9 @@ phys_size_t initdram(void)
 	ddr_enable_ecc(msize * 1024 * 1024);
 #endif
 	/* return total bus DDR size(bytes) */
-	return (msize * 1024 * 1024);
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 #if !defined(CONFIG_SPD_EEPROM)

board/freescale/mpc8610hpcd/mpc8610hpcd.c

@@ -19,6 +19,8 @@
 #include <spd_sdram.h>
 #include <netdev.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void sdram_init(void);
 phys_size_t fixed_sdram(void);
 int mpc8610hpcd_diu_init(void);
@@ -116,7 +118,7 @@ int checkboard(void)
 }
 
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size = 0;
 
@@ -129,7 +131,9 @@ phys_size_t initdram(void)
 	setup_ddr_bat(dram_size);
 
 	debug(" DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 

board/freescale/mpc8641hpcn/mpc8641hpcn.c

@@ -16,6 +16,8 @@
 #include <fdt_support.h>
 #include <netdev.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 phys_size_t fixed_sdram(void);
 
 int checkboard(void)
@@ -37,7 +39,7 @@ int checkboard(void)
 	return 0;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size = 0;
 
@@ -50,7 +52,9 @@ phys_size_t initdram(void)
 	setup_ddr_bat(dram_size);
 
 	debug("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 

board/freescale/p1010rdb/spl.c

@@ -94,7 +94,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram();
+	initdram();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("\nTertiary program loader running in sram...");
 #else

board/freescale/p1022ds/spl.c

@@ -111,7 +111,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	gd->ram_size = initdram();
+	initdram();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else

board/freescale/p1_p2_rdb_pc/spl.c

@@ -108,7 +108,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	gd->ram_size = initdram();
+	initdram();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else

board/freescale/p2041rdb/ddr.c

@@ -12,6 +12,8 @@
 #include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 struct board_specific_parameters {
 	u32 n_ranks;
 	u32 datarate_mhz_high;
@@ -116,7 +118,7 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size = 0;
 
@@ -127,12 +129,14 @@ phys_size_t initdram(void)
 		dram_size = fsl_ddr_sdram();
 	} else {
 		puts("no SPD and fixed parameters\n");
-		return dram_size;
+		return -ENXIO;
 	}
 
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
 	debug("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }

board/freescale/t102xqds/ddr.c

@@ -169,7 +169,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -187,5 +187,7 @@ phys_size_t initdram(void)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }

board/freescale/t102xqds/spl.c

@@ -142,7 +142,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram();
+	initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t102xrdb/ddr.c

@@ -229,7 +229,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -249,5 +249,7 @@ phys_size_t initdram(void)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }

board/freescale/t102xrdb/spl.c

@@ -129,7 +129,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram();
+	initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t1040qds/ddr.c

@@ -117,7 +117,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -134,5 +134,7 @@ phys_size_t initdram(void)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }

board/freescale/t104xrdb/ddr.c

@@ -120,7 +120,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -137,5 +137,7 @@ phys_size_t initdram(void)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }

board/freescale/t104xrdb/spl.c

@@ -125,7 +125,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	puts("\n\n");
 
-	gd->ram_size = initdram();
+	initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t208xqds/ddr.c

@@ -104,7 +104,7 @@ found:
 	popts->cpo_sample = 0x64;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -118,5 +118,7 @@ phys_size_t initdram(void)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }

board/freescale/t208xqds/spl.c

@@ -128,7 +128,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram();
+	initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t208xrdb/ddr.c

@@ -97,7 +97,7 @@ found:
 	popts->cpo_sample = 0x54;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -111,5 +111,7 @@ phys_size_t initdram(void)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }

board/freescale/t208xrdb/spl.c

@@ -98,7 +98,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram();
+	initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t4qds/ddr.c

@@ -112,7 +112,7 @@ found:
 	popts->cpo_sample = 0x63;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -127,5 +127,7 @@ phys_size_t initdram(void)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }

board/freescale/t4qds/spl.c

@@ -133,7 +133,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram();
+	initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t4rdb/ddr.c

@@ -105,7 +105,7 @@ found:
 	popts->cpo_sample = 0x64;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -120,5 +120,7 @@ phys_size_t initdram(void)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }

board/freescale/t4rdb/spl.c

@@ -91,7 +91,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram();
+	initdram();
 
 	mmc_boot();
 }

board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c

@@ -10,9 +10,11 @@
 #include <config.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(void)
+int initdram(void)
 {
-	return 1;
+	/* Does not set gd->ram_size here */
+
+	return 0;
 }
 
 int checkboard(void)

board/gaisler/gr_ep2s60/gr_ep2s60.c

@@ -10,9 +10,11 @@
 #include <config.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(void)
+int initdram(void)
 {
-	return 1;
+	/* Does not set gd->ram_size here */
+
+	return 0;
 }
 
 int checkboard(void)

board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c

@@ -9,9 +9,11 @@
 #include <config.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(void)
+int initdram(void)
 {
-	return 1;
+	/* Does not set gd->ram_size here */
+
+	return 0;
 }
 
 int checkboard(void)

board/gaisler/grsim/grsim.c

@@ -10,9 +10,11 @@
 #include <common.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(void)
+int initdram(void)
 {
-	return 1;
+	/* Does not set gd->ram_size here */
+
+	return 0;
 }
 
 int checkboard(void)

board/gaisler/grsim_leon2/grsim_leon2.c

@@ -10,9 +10,11 @@
 #include <common.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(void)
+int initdram(void)
 {
-	return 1;
+	/* Does not set gd->ram_size here */
+
+	return 0;
 }
 
 int checkboard(void)

board/gdsys/mpc8308/sdram.c

@@ -66,17 +66,19 @@ static long fixed_sdram(void)
 	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;
 
 	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM */
 	msize = fixed_sdram();
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }

board/ids/ids8313/ids8313.c

@@ -119,14 +119,14 @@ static int setup_sdram(void)
 	return msize;
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	fsl_lbc_t *lbc = &im->im_lbc;
 	u32 msize = 0;
 
 	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	msize = setup_sdram();
 
@@ -134,7 +134,9 @@ phys_size_t initdram(void)
 	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
 	sync();
 
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)

board/ifm/ac14xx/ac14xx.c

@@ -310,9 +310,12 @@ u32 sdram_init_seq[] = {
 	/* EMPTY, optional, we don't do it */
 };
 
-phys_size_t initdram(void)
+int initdram(void)
 {
-	return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
+	gd->ram_size = fixed_sdram(NULL, sdram_init_seq,
+				   ARRAY_SIZE(sdram_init_seq));
+
+	return 0;
 }
 
 int misc_init_r(void)

board/ifm/o2dnt2/o2dnt2.c

@@ -66,7 +66,7 @@ static void sdram_start(int hi_addr)
  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  */
-phys_size_t initdram(void)
+int initdram(void)
 {
 	struct mpc5xxx_mmap_ctl *mmap_ctl =
 		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
@@ -181,7 +181,9 @@ phys_size_t initdram(void)
 	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
 		out_be32(&sdram->sdelay, 0x04);
 
-	return dramsize + dramsize2;
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
 }
 
 

board/imgtec/boston/ddr.c

@@ -10,11 +10,16 @@
 
 #include "boston-regs.h"
 
-phys_size_t initdram(void)
+DECLARE_GLOBAL_DATA_PTR;
+
+int initdram(void)
 {
 	u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0);
 
-	return (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) << 30;
+	gd->ram_size = (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) <<
+			30;
+
+	return 0;
 }
 
 ulong board_get_usable_ram_top(ulong total_size)

board/imgtec/malta/malta.c

@@ -19,6 +19,8 @@
 
 #include "superio.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 enum core_card {
 	CORE_UNKNOWN,
 	CORE_LV,
@@ -83,9 +85,11 @@ static enum sys_con malta_sys_con(void)
 	}
 }
 
-phys_size_t initdram(void)
+int initdram(void)
 {
-	return CONFIG_SYS_MEM_SIZE;
+	gd->ram_size = CONFIG_SYS_MEM_SIZE;
+
+	return 0;
 }
 
 int checkboard(void)