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体验新版 GitCode,发现更多精彩内容 >>
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07dd6eb0
编写于
10月 21, 2007
作者:
W
Wolfgang Denk
浏览文件
操作
浏览文件
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差异文件
Merge branch 'master' of
git://www.denx.de/git/u-boot-tq-group
上级
b407f1a4
da3aad55
变更
3
显示空白变更内容
内联
并排
Showing
3 changed file
with
47 addition
and
31 deletion
+47
-31
board/tqm8xx/tqm8xx.c
board/tqm8xx/tqm8xx.c
+9
-7
include/configs/TQM860M.h
include/configs/TQM860M.h
+9
-4
include/configs/TQM866M.h
include/configs/TQM866M.h
+29
-20
未找到文件。
board/tqm8xx/tqm8xx.c
浏览文件 @
07dd6eb0
...
...
@@ -354,6 +354,8 @@ long int initdram (int board_type)
udelay
(
10000
);
#ifdef CONFIG_CAN_DRIVER
/* UPM initialization for CAN @ CLKOUT <= 66 MHz */
/* Initialize OR3 / BR3 */
memctl
->
memc_or3
=
CFG_OR3_CAN
;
memctl
->
memc_br3
=
CFG_BR3_CAN
;
...
...
@@ -362,7 +364,7 @@ long int initdram (int board_type)
memctl
->
memc_mbmr
=
MBMR_GPL_B4DIS
;
/* GPL_B4 ouput line Disable */
/* Initialize UPMB for CAN: single read */
memctl
->
memc_mdr
=
0xFFFFC
0
04
;
memctl
->
memc_mdr
=
0xFFFFC
C
04
;
memctl
->
memc_mcr
=
0x0100
|
UPMB
;
memctl
->
memc_mdr
=
0x0FFFD004
;
...
...
@@ -374,23 +376,23 @@ long int initdram (int board_type)
memctl
->
memc_mdr
=
0x3FFFC004
;
memctl
->
memc_mcr
=
0x0103
|
UPMB
;
memctl
->
memc_mdr
=
0xFFFFDC0
5
;
memctl
->
memc_mdr
=
0xFFFFDC0
7
;
memctl
->
memc_mcr
=
0x0104
|
UPMB
;
/* Initialize UPMB for CAN: single write */
memctl
->
memc_mdr
=
0xFFFCC
0
04
;
memctl
->
memc_mdr
=
0xFFFCC
C
04
;
memctl
->
memc_mcr
=
0x0118
|
UPMB
;
memctl
->
memc_mdr
=
0xCFFCD
0
04
;
memctl
->
memc_mdr
=
0xCFFCD
C
04
;
memctl
->
memc_mcr
=
0x0119
|
UPMB
;
memctl
->
memc_mdr
=
0x
0
FFCC000
;
memctl
->
memc_mdr
=
0x
3
FFCC000
;
memctl
->
memc_mcr
=
0x011A
|
UPMB
;
memctl
->
memc_mdr
=
0x
7
FFCC004
;
memctl
->
memc_mdr
=
0x
F
FFCC004
;
memctl
->
memc_mcr
=
0x011B
|
UPMB
;
memctl
->
memc_mdr
=
0xFFFDC
C
05
;
memctl
->
memc_mdr
=
0xFFFDC
4
05
;
memctl
->
memc_mcr
=
0x011C
|
UPMB
;
#endif
/* CONFIG_CAN_DRIVER */
...
...
include/configs/TQM860M.h
浏览文件 @
07dd6eb0
...
...
@@ -69,9 +69,14 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860M/uImage\0" \
"fdt_addr=400
8
0000\0" \
"kernel_addr=40
0A
0000\0" \
"fdt_addr=400
C
0000\0" \
"kernel_addr=40
10
0000\0" \
"ramdisk_addr=40280000\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=protect off 40000000 +${filesize};" \
"erase 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"protect on 40000000 +${filesize}\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
...
...
@@ -172,7 +177,7 @@
#define CFG_FLASH_BASE 0x40000000
#define CFG_MONITOR_LEN (256 << 10)
/* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (
128 << 10)
/* Reserve 128
kB for malloc() */
#define CFG_MALLOC_LEN (
256 << 10)
/* Reserve 256
kB for malloc() */
/*
* For booting Linux, the board info and command line data
...
...
@@ -193,7 +198,7 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000
/* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x08000
/* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x
2
0000
/* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x
4
0000
/* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
...
...
include/configs/TQM866M.h
浏览文件 @
07dd6eb0
...
...
@@ -81,9 +81,14 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM866M/uImage\0" \
"fdt_addr=400
8
0000\0" \
"kernel_addr=40
0A
0000\0" \
"fdt_addr=400
C
0000\0" \
"kernel_addr=40
10
0000\0" \
"ramdisk_addr=40280000\0" \
"load=tftp 200000 ${u-boot}\0" \
"update=protect off 40000000 +${filesize};" \
"erase 40000000 +${filesize};" \
"cp.b 200000 40000000 ${filesize};" \
"protect on 40000000 +${filesize}\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
...
...
@@ -215,7 +220,7 @@
#define CFG_FLASH_BASE 0x40000000
#define CFG_MONITOR_LEN (256 << 10)
/* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (
128 << 10)
/* Reserve 128
kB for malloc() */
#define CFG_MALLOC_LEN (
256 << 10)
/* Reserve 256
kB for malloc() */
/*
* For booting Linux, the board info and command line data
...
...
@@ -236,7 +241,7 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000
/* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x08000
/* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x
2
0000
/* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x
4
0000
/* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
...
...
@@ -421,26 +426,30 @@
#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
/*
* Memory Periodic Timer Prescaler
* Periodic timer for refresh, start with refresh rate for 40 MHz clock
* (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
* Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
*
* CPUclock(MHz) * 31.2
* CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0
* 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
*
* CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us
* CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us
* CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us
* CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us
*
* Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
* be met also in the default configuration, i.e. if environment variable
* 'cpuclk' is not set.
*/
#define CFG_MAMR_PTA
39
#define CFG_MAMR_PTA
97
/*
* For 16 MBit, refresh rates could be 31.3 us
* (= 64 ms / 2K = 125 / quad bursts).
* For a simpler initialization, 15.6 us is used instead.
*
* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
* Memory Periodic Timer Prescaler Register (MPTPR) values.
*/
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16
/* setting for 2 banks */
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32
/* setting for 1 bank */
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8
/* setting for 2 banks */
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16
/* setting for 1 bank */
/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16
/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8
/*
* MAMR settings for SDRAM
...
...
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