diff --git a/Configurations/00-base-templates.conf b/Configurations/00-base-templates.conf index c28e4e1b515e3b23ff28f21e728299270573b17c..83d38e032bf7dae876e509203ceb07f77b47071e 100644 --- a/Configurations/00-base-templates.conf +++ b/Configurations/00-base-templates.conf @@ -185,7 +185,7 @@ bn_asm_src => "asm/sparcv8plus.S sparcv9-mont.S sparcv9a-mont.S vis3-mont.S sparct4-mont.S sparcv9-gf2m.S", ec_asm_src => "ecp_nistz256.c ecp_nistz256-sparcv9.S", des_asm_src => "des_enc-sparc.S fcrypt_b.c dest4-sparcv9.S", - aes_asm_src => "aes_core.c aes_cbc.c aes-sparcv9.S aest4-sparcv9.S", + aes_asm_src => "aes_core.c aes_cbc.c aes-sparcv9.S aest4-sparcv9.S aesfx-sparcv9.S", md5_asm_src => "md5-sparcv9.S", sha1_asm_src => "sha1-sparcv9.S sha256-sparcv9.S sha512-sparcv9.S", cmll_asm_src => "camellia.c cmll_misc.c cmll_cbc.c cmllt4-sparcv9.S", diff --git a/crypto/evp/e_aes.c b/crypto/evp/e_aes.c index f0e410fc20b76ab9c5d7c5fe4d9af856ab341498..4d40efe8d55c6c6c50dbffc336dc998d32b1c3a5 100644 --- a/crypto/evp/e_aes.c +++ b/crypto/evp/e_aes.c @@ -184,7 +184,7 @@ void AES_xts_decrypt(const char *inp, char *out, size_t len, const unsigned char iv[16]); #endif -#if defined(OPENSSL_CPUID_OBJ) && (defined(__powerpc__) || defined(__ppc__) || defined(_ARCH_PPC)) +#if defined(OPENSSL_CPUID_OBJ) && (defined(__powerpc__) || defined(__ppc__) || defined(_ARCH_PPC)) # include "ppc_arch.h" # ifdef VPAES_ASM # define VPAES_CAPABLE (OPENSSL_ppccap_P & PPC_ALTIVEC) @@ -587,6 +587,15 @@ const EVP_CIPHER *EVP_aes_##keylen##_##mode(void) \ extern unsigned int OPENSSL_sparcv9cap_P[]; +/* + * Initial Fujitsu SPARC64 X support + */ +# define HWAES_CAPABLE (OPENSSL_sparcv9cap_P[0] & SPARCV9_FJAESX) +# define HWAES_set_encrypt_key aes_fx_set_encrypt_key +# define HWAES_set_decrypt_key aes_fx_set_decrypt_key +# define HWAES_encrypt aes_fx_encrypt +# define HWAES_decrypt aes_fx_decrypt + # define SPARC_AES_CAPABLE (OPENSSL_sparcv9cap_P[1] & CFR_AES) void aes_t4_set_encrypt_key(const unsigned char *key, int bits, AES_KEY *ks);