diff --git a/crypto/arm_arch.h b/crypto/arm_arch.h
index 5a831076800338f3447bde20c4e78544a2700d5c..d68318c851919416a1c3bb07d1964d1aea3bf010 100644
--- a/crypto/arm_arch.h
+++ b/crypto/arm_arch.h
@@ -46,6 +46,10 @@ extern unsigned int OPENSSL_armcap_P;
                                      
 #define ARMV7_NEON      (1<<0)
 #define ARMV7_TICK      (1<<1)
+#define ARMV8_AES       (1<<2)
+#define ARMV8_SHA1      (1<<3)
+#define ARMV8_SHA256    (1<<4)
+#define ARMV8_PMULL     (1<<5)
 #endif
 
 #endif
diff --git a/crypto/armcap.c b/crypto/armcap.c
index 9abaf396e53e4f5f02a05639d66ccdd9cc023495..550414425d6bd9a8d1c56a5ac377abe03e57ac95 100644
--- a/crypto/armcap.c
+++ b/crypto/armcap.c
@@ -19,6 +19,10 @@ static void ill_handler (int sig) { siglongjmp(ill_jmp,sig); }
  * ARM compilers support inline assembler...
  */
 void _armv7_neon_probe(void);
+void _armv8_aes_probe(void);
+void _armv8_sha1_probe(void);
+void _armv8_sha256_probe(void);
+void _armv8_pmull_probe(void);
 unsigned int _armv7_tick(void);
 
 unsigned int OPENSSL_rdtsc(void)
@@ -68,6 +72,26 @@ void OPENSSL_cpuid_setup(void)
 		{
 		_armv7_neon_probe();
 		OPENSSL_armcap_P |= ARMV7_NEON;
+		if (sigsetjmp(ill_jmp,1) == 0)
+			{
+			_armv8_aes_probe();
+			OPENSSL_armcap_P |= ARMV8_AES;
+			}
+		if (sigsetjmp(ill_jmp,1) == 0)
+			{
+			_armv8_sha1_probe();
+			OPENSSL_armcap_P |= ARMV8_SHA1;
+			}
+		if (sigsetjmp(ill_jmp,1) == 0)
+			{
+			_armv8_sha256_probe();
+			OPENSSL_armcap_P |= ARMV8_SHA256;
+			}
+		if (sigsetjmp(ill_jmp,1) == 0)
+			{
+			_armv8_pmull_probe();
+			OPENSSL_armcap_P |= ARMV8_PMULL;
+			}
 		}
 	if (sigsetjmp(ill_jmp,1) == 0)
 		{
diff --git a/crypto/armv4cpuid.S b/crypto/armv4cpuid.S
index 2d618deaa43e431e895708a4c3d0716547da9585..edd619800fc825214e7a76c90f84907008a41091 100644
--- a/crypto/armv4cpuid.S
+++ b/crypto/armv4cpuid.S
@@ -18,6 +18,34 @@ _armv7_tick:
 	.word	0xe12fff1e	@ bx	lr
 .size	_armv7_tick,.-_armv7_tick
 
+.global	_armv8_aes_probe
+.type	_armv8_aes_probe,%function
+_armv8_aes_probe:
+	.word	0xf3b00300	@ aese.8	q0,q0
+	.word	0xe12fff1e	@ bx	lr
+.size	_armv8_aes_probe,.-_armv8_aes_probe
+
+.global	_armv8_sha1_probe
+.type	_armv8_sha1_probe,%function
+_armv8_sha1_probe:
+	.word	0xf2000c40	@ sha1c.32	q0,q0,q0
+	.word	0xe12fff1e	@ bx	lr
+.size	_armv8_sha1_probe,.-_armv8_sha1_probe
+
+.global	_armv8_sha256_probe
+.type	_armv8_sha256_probe,%function
+_armv8_sha256_probe:
+	.word	0xf3000c40	@ sha256h.32	q0,q0,q0
+	.word	0xe12fff1e	@ bx	lr
+.size	_armv8_sha256_probe,.-_armv8_sha256_probe
+.global	_armv8_pmull_probe
+.type	_armv8_pmull_probe,%function
+_armv8_pmull_probe:
+	.word	0xf2a00e00	@ vmull.p64	q0,d0,d0
+	.word	0xe12fff1e	@ bx	lr
+.size	_armv8_pmull_probe,.-_armv8_pmull_probe
+
+.align	5
 .global	OPENSSL_atomic_add
 .type	OPENSSL_atomic_add,%function
 OPENSSL_atomic_add: