diff --git a/arch/arm/arm/src/startup/reset_vector_mp.S b/arch/arm/arm/src/startup/reset_vector_mp.S
index 7f7e29626dfdb73cf9da68829c4c316c15bdd787..b1f9ff479a36fcb857407d7a5806ae161f337b0c 100644
--- a/arch/arm/arm/src/startup/reset_vector_mp.S
+++ b/arch/arm/arm/src/startup/reset_vector_mp.S
@@ -121,8 +121,9 @@ reset_vector:
     mcr     p15, 0, r0, c13, c0, 4
     /* do some early cpu setup: i/d cache disable, mmu disabled */
     mrc     p15, 0, r0, c1, c0, 0
-    bic     r0, #(1<<12)
-    bic     r0, #(1<<2 | 1<<0)
+    bic     r0, #(1 << 12)          /* i cache */
+    bic     r0, #(1 << 2)           /* d cache */
+    bic     r0, #(1 << 0)           /* mmu */
     mcr     p15, 0, r0, c1, c0, 0
 
     /* enable fpu+neon */
@@ -282,11 +283,11 @@ mmu_setup:
     mcr    p15, 0, r12, c1, c0, 1               /* ACTLR, Auxlliary Control Register */
     dsb
     mrc     p15, 0, r12, c1, c0, 0
-    bic     r12, #(1 << 29 | 1 << 28)
-    orr     r12, #(1 << 0)
+    bic     r12, #(1 << 29 | 1 << 28)           /* Disable TRE/AFE */
+    orr     r12, #(1 << 0)                      /* mmu enable */
     bic     r12, #(1 << 1)
-    orr     r12, #(1 << 2)
-    orr     r12, #(1 << 12)
+    orr     r12, #(1 << 2)                     /* D cache enable */
+    orr     r12, #(1 << 12)                    /* I cache enable */
     mcr     p15, 0, r12, c1, c0, 0              /* Set SCTLR with r12: Turn on the MMU, I/D cache Disable TRE/AFE */
     isb
     ldr     pc,  =1f                            /* Convert to VA */
diff --git a/arch/arm/arm/src/startup/reset_vector_up.S b/arch/arm/arm/src/startup/reset_vector_up.S
index 75994ac15b8205688c0aadcb146a6774881596a5..a54f468aea6460958ad8ac29f9ccf5578d101f0f 100644
--- a/arch/arm/arm/src/startup/reset_vector_up.S
+++ b/arch/arm/arm/src/startup/reset_vector_up.S
@@ -101,8 +101,9 @@ __exception_handlers:
 reset_vector:
     /* do some early cpu setup: i/d cache disable, mmu disabled */
     mrc     p15, 0, r0, c1, c0, 0
-    bic     r0, #(1<<12)
-    bic     r0, #(1<<2 | 1<<0)
+    bic     r0, #(1 << 12)          /* i cache */
+    bic     r0, #(1 << 2)           /* d cache */
+    bic     r0, #(1 << 0)           /* mmu */
     mcr     p15, 0, r0, c1, c0, 0
 
     /* enable fpu+neon */
@@ -269,11 +270,11 @@ mmu_setup:
     isb
 
     mrc     p15, 0, r12, c1, c0, 0
-    bic     r12, #(1 << 29 | 1 << 28)
-    orr     r12, #(1 << 0)
+    bic     r12, #(1 << 29 | 1 << 28)           /* Disable TRE/AFE */
+    orr     r12, #(1 << 0)                      /* mmu enable */
     bic     r12, #(1 << 1)
-    orr     r12, #(1 << 2)
-    orr     r12, #(1 << 12)
+    orr     r12, #(1 << 2)                      /* D cache enable */
+    orr     r12, #(1 << 12)                     /* I cache enable */
     mcr     p15, 0, r12, c1, c0, 0              /* Set SCTLR with r12: Turn on the MMU, I/D cache Disable TRE/AFE */
     isb