All asm/ipc.h files do only #include <asm-generic/ipc.h>.

This patch therefore removes all include/asm-*/ipc.h files and moves the
contents of include/asm-generic/ipc.h to include/linux/ipc.h.
Signed-off-by: NAdrian Bunk <bunk@kernel.org>
Cc: <linux-arch@vger.kernel.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

This cleans up the formatting in the vDSO linker script, mostly just the
use of whitespace.  It's intended to approximate the kernel standard
conventions for indenting C, treating elements of the linker script about
like initialized variable definitions.
Signed-off-by: NRoland McGrath <roland@redhat.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Identical handlers of PTRACE_DETACH go into ptrace_request().
Not touching compat code.
Not touching archs that don't call ptrace_request.
Signed-off-by: NAlexey Dobriyan <adobriyan@sw.ru>
Acked-by: NChristoph Hellwig <hch@infradead.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

As noted by Christoph Hellwig, pktgen was the only user so
it can now be removed.

[ Add missing cases caught by Adrian Bunk. -DaveM ]
Signed-off-by: NRobert Olsson <robert.olsson@its.uu.se>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

These were previously discarded at link time, though as with MIPS
we keep them around until runtime to satisfy .rodata references.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

With the PERCPU() macro introduction .data.cacheline_aligned was
inhereting PAGE_SIZE alignment, fix that up for L1_CACHE_BYTES
again. Likewise, the initramfs section wants PAGE_SIZE alignment.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NThomas Renninger <trenn@suse.de>
Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Bryan Wu <bryan.wu@analog.com>
Cc: Andi Kleen <ak@suse.de>
Cc: "Luck, Tony" <tony.luck@intel.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: "David S. Miller" <davem@davemloft.net>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NDave Jones <davej@redhat.com>

At some point way back when (2.5 or so) quite a few syscalls hadn't
yet been wired up as cond_syscalls(), so we opted to just do direct
sys_ni_syscall wrapping in the assembly code instead. That's all
been fixed up since then, so we can drop the wrapping.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

kgdb had its own ranged I-cache flushing routine that attempted to
duplicate the flush_icache_range() functionality, but managed to do
an explicit D-cache writeback & invalidate twice on SH-4. This is
a no-op for SH-3, and the flush_icache_range() semantics already do
what kgdb was feebly attempting to do already, so just move over to
that and kill off the wrapper.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The kgdb console setup was callable from a left-over deferred
initialization path, which in turn depends on __init symbols. Since
the deferred initialization was removed some time ago, kill off the
rest of those remnants and move kgdb_init() and friends to __init.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

setup_early_printk() can be static, and with that, we can kill off
the early initialization variable and move the CON_BOOT check in
to the function body.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This conditionalizes gUSA support. gUSA is not supported on
SMP configurations, and it's not necessary there anyways due
to having other atomicity options (ie, movli.l/movco.l).

Anything implementing the LL/SC semantics (all SH-4A CPUs)
can switch to userspace atomicity implementations without
requiring gUSA. This is left default-enabled on all UP so
that glibc doesn't break.

Those that know what they are doing can disable this explicitly.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Currently gUSA toggles hardirqs to disable preemption in the signal
handler. Make the preemption toggling explicit, and kill off some
CONFIG_PREEMPT ifdefs in the process.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Currently clock propagation only works for one level, but we have some
clocks which need to propagate multiple levels, so make this recursive.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Not all of the SH-X2 URAM blocks are mapped in the same place,
SH7785 happens to map it on the opposite end of the address space
from SH7722, correct the addresses.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This moves off of smp_processor_id() and only sets the probe
information for the boot CPU directly. This will be copied out
for the secondaries, so there's no reason to do this each time.

This also allows for some header tidying.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

There was some debug code left in here that caused the pin changes
to never be hit. Kill that off, and all is well.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The probing logic works for both URAM and L2, with no way to
distinguish between the two. Disable the probing for now and
let the CPU subtypes that have this in a real L2 configuration
explicitly say so.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The uClinux MTD device uses _ebss, add the symbol and corresponding
export.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds basic support for SH-X3 SMP (4 CPUs).

More IPI and cache debugging is necessary, mostly interfacing the
d-cache coherency and the I-cache broadcast invalidates. Only for
testing at present!
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Now that the SMP stubs are in place, call in to the setup code
to be defined by the platform.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

There was a very preliminary bunch of SMP code scattered around for the
SH7604 microcontrollers from way back when, and it has mostly suffered
bitrot since then. With the tree already having been slowly getting
prepped for SMP, this plugs in most of the remaining platform-independent
bits.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This implements initial support for the SMP INTC (particularly
INTC2) controllers.

These are largely implemented as conventional blocks, with
register sets grouped together at fixed strides relative to
the CPU id.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds the TLB flushing routines for SMP systems, based on
the MIPS implementation, with some additional SH-specific
flush routines.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This consolidates the cpu_data definitions and gets rid of the special
boot_cpu_data. It's made a wrapper to the boot CPU, in order to keep
the existing in-tree users happy.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The cpufreq driver banner is currently printed for each CPU, move
it down so it's not as noisy and it's only printed once.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Add SH7785 URAM as node 1, follows the SH-X3 change.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Get the SH7343 and SH7770 stuff linking again. Both of these still
require proper INTC support.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch contains the following fixes and improvements:
- Fix address typo for INTMSK2 / INTMSKCLR2 registers on sh7780.
- Adds IRQ_MODE_IRLnnnn_MASK using intc controller for IRL masking.
- Good old IRQ_MODE_IRLnnnn should not register any intc controller.
- plat_irq_setup_pins() now selects IRL or IRQ mode.
- the holding function is now disabled using ICR0.

By default all external pin interrupts are disabled.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

All processor specific interrupt code is now converted to make use
of the new intc code. The config option CONFIG_CPU_HAS_INTC_IRQ is
because of that pointless.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

  CC      arch/sh/kernel/cpu/sh4/sq.o
arch/sh/kernel/cpu/sh4/sq.c: In function 'sq_flush_range':
arch/sh/kernel/cpu/sh4/sq.c:65: warning: passing argument 1 of 'prefetch' discards qualifiers from pointer target type

This didn't actually need to be volatile in the first place, so just
kill off the qualifier entirely.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch converts the cpu specific interrupt setup code for sh7206
from ipr to intc. New vectors are also added to match the information
provided by the datasheet.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch converts the cpu specific interrupt setup code for sh7619
from ipr to intc. New vectors are also added to match the information
provided by the datasheet.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch makes sure the serial port interrupt irqs matches the
datasheet.  Only irqs for SCIF1 are changed. While at some cosmetic
spaces are added.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch contains various intc fixes for problems reported by
Markus Brunner on the linuxsh-dev mailing list:

http://marc.info/?l=linuxsh-dev&m=118701948224991&w=1

Apart from added comments, the fixes are:

- add intc_set_priority() function prototype to hw_irq.h
- fix off-by-one error in intc_set_priority()
- make sure _INTC_WIDTH() is set for primary priority masking

Big thanks to Markus for finding these problems. Version two fixes
a compile error and an inverted primary check.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Acked-by: NMarkus Brunner <super.firetwister@gmail.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

With the intc core improved it is now possible to put the intc data
structures in the initdata section.

Version two of this patch puts the __initdata inside DECLARE_INTC_DESC()
and removes the __initdata included in the board specific r2d code.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

With the intc dual prio register support in place it is now possible
to add the ipi vectors to x3.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch reworks the intc core, implementing the following features:

- Support dual priority registers - one set and one clear register
- All 8/16/32 bit register combinations are now supported
- Both single mask and single enable bitmap register are supported
- Add code to set interrupt priority
- Speedup sense and priority configuration code
- Allocate data using bootmem, allows intc data structures to be
  __initdata
- Save memory - allocated memory footprint is smaller than intc
  structures
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>