Skip to content

K
kernel_linux

OpenHarmony / kernel_linux
上一次同步 4 年多

通知 15
Star 8
Fork 2
K
kernel_linux
提交 fe767560 编写于 作者: M Michael Turquette
浏览文件
操作

Merge branch 'clk-omap-legacy' into clk-next 

Conflicts:
	arch/arm/mach-omap2/cclock3xxx_data.c
上级 035a61c3 d6540b19
显示空白变更内容
内联 并排
Showing with 5548 addition and 3810 deletion
arch/arm/mach-omap2/Makefile
浏览文件 @ fe767560
......@@ -187,7 +187,7 @@ obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
......
arch/arm/mach-omap2/cclock3xxx_data.c 已删除 100644 → 0
浏览文件 @ 035a61c3
/*
* OMAP3 clock data
*
* Copyright (C) 2007-2012 Texas Instruments, Inc.
* Copyright (C) 2007-2011 Nokia Corporation
*
* Written by Paul Walmsley
* Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
* With many device clock fixes by Kevin Hilman and Jouni Högander
* DPLL bypass clock support added by Roman Tereshonkov
*
*/
/*
* Virtual clocks are introduced as convenient tools.
* They are sources for other clocks and not supposed
* to be requested from drivers directly.
*/
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/clk-private.h>
#include <linux/list.h>
#include <linux/io.h>
#include "soc.h"
#include "iomap.h"
#include "clock.h"
#include "clock3xxx.h"
#include "clock34xx.h"
#include "clock36xx.h"
#include "clock3517.h"
#include "cm3xxx.h"
#include "cm-regbits-34xx.h"
#include "prm3xxx.h"
#include "prm-regbits-34xx.h"
#include "control.h"
/*
* clocks
*/
#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
/* Maximum DPLL multiplier, divider values for OMAP3 */
#define OMAP3_MAX_DPLL_MULT 2047
#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
#define OMAP3_MAX_DPLL_DIV 128
DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0);
DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0);
DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0);
DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0);
DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0);
DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0);
DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0);
DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0);
static const char *osc_sys_ck_parent_names[] = {
"virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
"virt_38_4m_ck", "virt_16_8m_ck",
};
DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck_core, 0x0,
OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
static struct dpll_data dpll3_dd = {
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
.div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
.clk_bypass = &sys_ck,
.clk_ref = &sys_ck,
.freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
.control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
.auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
.autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
.autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
.idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
.idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
};
static struct clk dpll3_ck;
static const char *dpll3_ck_parent_names[] = {
"sys_ck",
"sys_ck",
};
static const struct clk_ops dpll3_ck_ops = {
.init = &omap2_init_clk_clkdm,
.get_parent = &omap2_init_dpll_parent,
.recalc_rate = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
};
static struct clk_hw_omap dpll3_ck_hw = {
.hw = {
.clk = &dpll3_ck,
},
.ops = &clkhwops_omap3_dpll,
.dpll_data = &dpll3_dd,
.clkdm_name = "dpll3_clkdm",
};
DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck_core, 0x0,
OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
static struct clk core_ck;
static const char *core_ck_parent_names[] = {
"dpll3_m2_ck",
};
static const struct clk_ops core_ck_ops = {};
DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck_core, 0x0,
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick_core, 0x0,
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
static struct clk security_l4_ick2;
static const char *security_l4_ick2_parent_names[] = {
"l4_ick",
};
DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL);
DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops);
static struct clk aes1_ick;
static const char *aes1_ick_parent_names[] = {
"security_l4_ick2",
};
static const struct clk_ops aes1_ick_ops = {
.enable = &omap2_dflt_clk_enable,
.disable = &omap2_dflt_clk_disable,
.is_enabled = &omap2_dflt_clk_is_enabled,
};
static struct clk_hw_omap aes1_ick_hw = {
.hw = {
.clk = &aes1_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_AES1_SHIFT,
};
DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops);
static struct clk core_l4_ick;
static const struct clk_ops core_l4_ick_ops = {
.init = &omap2_init_clk_clkdm,
};
DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm");
DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
static struct clk aes2_ick;
static const char *aes2_ick_parent_names[] = {
"core_l4_ick",
};
static const struct clk_ops aes2_ick_ops = {
.init = &omap2_init_clk_clkdm,
.enable = &omap2_dflt_clk_enable,
.disable = &omap2_dflt_clk_disable,
.is_enabled = &omap2_dflt_clk_is_enabled,
};
static struct clk_hw_omap aes2_ick_hw = {
.hw = {
.clk = &aes2_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_AES2_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk dpll1_fck;
static struct dpll_data dpll1_dd = {
.mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
.mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
.div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
.clk_bypass = &dpll1_fck,
.clk_ref = &sys_ck,
.freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
.control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
.enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
.auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
.autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
.autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
.idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
.idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
};
static struct clk dpll1_ck;
static const struct clk_ops dpll1_ck_ops = {
.init = &omap2_init_clk_clkdm,
.enable = &omap3_noncore_dpll_enable,
.disable = &omap3_noncore_dpll_disable,
.get_parent = &omap2_init_dpll_parent,
.recalc_rate = &omap3_dpll_recalc,
.set_rate = &omap3_noncore_dpll_set_rate,
.set_parent = &omap3_noncore_dpll_set_parent,
.set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
.determine_rate = &omap3_noncore_dpll_determine_rate,
.round_rate = &omap2_dpll_round_rate,
};
static struct clk_hw_omap dpll1_ck_hw = {
.hw = {
.clk = &dpll1_ck,
},
.ops = &clkhwops_omap3_dpll,
.dpll_data = &dpll1_dd,
.clkdm_name = "dpll1_clkdm",
};
DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck_core, 0x0, 2, 1);
DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck_core, 0x0,
OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
static struct clk mpu_ck;
static const char *mpu_ck_parent_names[] = {
"dpll1_x2m2_ck",
};
DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck_core, 0x0,
OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
0x0, NULL);
static struct clk cam_ick;
static struct clk_hw_omap cam_ick_hw = {
.hw = {
.clk = &cam_ick,
},
.ops = &clkhwops_iclk,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
.clkdm_name = "cam_clkdm",
};
DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops);
/* DPLL4 */
/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
/* Type: DPLL */
static struct dpll_data dpll4_dd;
static struct dpll_data dpll4_dd_34xx __initdata = {
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
.mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
.div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
.clk_bypass = &sys_ck,
.clk_ref = &sys_ck,
.freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
.control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
.auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
.autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
.autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
.idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
.idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
};
static struct dpll_data dpll4_dd_3630 __initdata = {
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
.mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
.div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
.clk_bypass = &sys_ck,
.clk_ref = &sys_ck,
.control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
.auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
.autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
.autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
.idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
.idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
.dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
.sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
.max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
.flags = DPLL_J_TYPE
};
static struct clk dpll4_ck;
static const struct clk_ops dpll4_ck_ops = {
.init = &omap2_init_clk_clkdm,
.enable = &omap3_noncore_dpll_enable,
.disable = &omap3_noncore_dpll_disable,
.get_parent = &omap2_init_dpll_parent,
.recalc_rate = &omap3_dpll_recalc,
.set_rate = &omap3_dpll4_set_rate,
.set_parent = &omap3_noncore_dpll_set_parent,
.set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
.determine_rate = &omap3_noncore_dpll_determine_rate,
.round_rate = &omap2_dpll_round_rate,
};
static struct clk_hw_omap dpll4_ck_hw = {
.hw = {
.clk = &dpll4_ck,
},
.dpll_data = &dpll4_dd,
.ops = &clkhwops_omap3_dpll,
.clkdm_name = "dpll4_clkdm",
};
DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
static const struct clk_div_table dpll4_mx_ck_div_table[] = {
{ .div = 1, .val = 1 },
{ .div = 2, .val = 2 },
{ .div = 3, .val = 3 },
{ .div = 4, .val = 4 },
{ .div = 5, .val = 5 },
{ .div = 6, .val = 6 },
{ .div = 7, .val = 7 },
{ .div = 8, .val = 8 },
{ .div = 9, .val = 9 },
{ .div = 10, .val = 10 },
{ .div = 11, .val = 11 },
{ .div = 12, .val = 12 },
{ .div = 13, .val = 13 },
{ .div = 14, .val = 14 },
{ .div = 15, .val = 15 },
{ .div = 16, .val = 16 },
{ .div = 17, .val = 17 },
{ .div = 18, .val = 18 },
{ .div = 19, .val = 19 },
{ .div = 20, .val = 20 },
{ .div = 21, .val = 21 },
{ .div = 22, .val = 22 },
{ .div = 23, .val = 23 },
{ .div = 24, .val = 24 },
{ .div = 25, .val = 25 },
{ .div = 26, .val = 26 },
{ .div = 27, .val = 27 },
{ .div = 28, .val = 28 },
{ .div = 29, .val = 29 },
{ .div = 30, .val = 30 },
{ .div = 31, .val = 31 },
{ .div = 32, .val = 32 },
{ .div = 0 },
};
DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
static struct clk dpll4_m5x2_ck;
static const char *dpll4_m5x2_ck_parent_names[] = {
"dpll4_m5_ck",
};
static const struct clk_ops dpll4_m5x2_ck_ops = {
.init = &omap2_init_clk_clkdm,
.enable = &omap2_dflt_clk_enable,
.disable = &omap2_dflt_clk_disable,
.is_enabled = &omap2_dflt_clk_is_enabled,
.set_rate = &omap3_clkoutx2_set_rate,
.recalc_rate = &omap3_clkoutx2_recalc,
.round_rate = &omap3_clkoutx2_round_rate,
};
static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
.init = &omap2_init_clk_clkdm,
.enable = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
.disable = &omap2_dflt_clk_disable,
.recalc_rate = &omap3_clkoutx2_recalc,
};
static struct clk_hw_omap dpll4_m5x2_ck_hw = {
.hw = {
.clk = &dpll4_m5x2_ck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
.flags = INVERT_ENABLE,
.clkdm_name = "dpll4_clkdm",
};
DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names,
dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
static struct clk_core dpll4_m5x2_ck_3630_core = {
.name = "dpll4_m5x2_ck",
.hw = &dpll4_m5x2_ck_hw.hw,
.parent_names = dpll4_m5x2_ck_parent_names,
.num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
.ops = &dpll4_m5x2_ck_3630_ops,
.flags = CLK_SET_RATE_PARENT,
};
static struct clk dpll4_m5x2_ck_3630 = {
.core = &dpll4_m5x2_ck_3630_core,
};
static struct clk cam_mclk;
static const char *cam_mclk_parent_names[] = {
"dpll4_m5x2_ck",
};
static struct clk_hw_omap cam_mclk_hw = {
.hw = {
.clk = &cam_mclk,
},
.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
.clkdm_name = "cam_clkdm",
};
static struct clk_core cam_mclk_core = {
.name = "cam_mclk",
.hw = &cam_mclk_hw.hw,
.parent_names = cam_mclk_parent_names,
.num_parents = ARRAY_SIZE(cam_mclk_parent_names),
.ops = &aes2_ick_ops,
.flags = CLK_SET_RATE_PARENT,
};
static struct clk cam_mclk = {
.core = &cam_mclk_core,
};
static const struct clksel_rate clkout2_src_core_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
{ .div = 0 }
};
static const struct clksel_rate clkout2_src_sys_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
{ .div = 0 }
};
static const struct clksel_rate clkout2_src_96m_rates[] = {
{ .div = 1, .val = 2, .flags = RATE_IN_3XXX },
{ .div = 0 }
};
DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
static struct clk dpll4_m2x2_ck;
static const char *dpll4_m2x2_ck_parent_names[] = {
"dpll4_m2_ck",
};
static struct clk_hw_omap dpll4_m2x2_ck_hw = {
.hw = {
.clk = &dpll4_m2x2_ck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_96M_SHIFT,
.flags = INVERT_ENABLE,
.clkdm_name = "dpll4_clkdm",
};
DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
static struct clk_core dpll4_m2x2_ck_3630_core = {
.name = "dpll4_m2x2_ck",
.hw = &dpll4_m2x2_ck_hw.hw,
.parent_names = dpll4_m2x2_ck_parent_names,
.num_parents = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
.ops = &dpll4_m5x2_ck_3630_ops,
};
static struct clk dpll4_m2x2_ck_3630 = {
.core = &dpll4_m2x2_ck_3630_core,
};
static struct clk omap_96m_alwon_fck;
static const char *omap_96m_alwon_fck_parent_names[] = {
"dpll4_m2x2_ck",
};
DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
core_ck_ops);
static struct clk cm_96m_fck;
static const char *cm_96m_fck_parent_names[] = {
"omap_96m_alwon_fck",
};
DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
static const struct clksel_rate clkout2_src_54m_rates[] = {
{ .div = 1, .val = 3, .flags = RATE_IN_3XXX },
{ .div = 0 }
};
DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
0, dpll4_mx_ck_div_table, NULL);
static struct clk dpll4_m3x2_ck;
static const char *dpll4_m3x2_ck_parent_names[] = {
"dpll4_m3_ck",
};
static struct clk_hw_omap dpll4_m3x2_ck_hw = {
.hw = {
.clk = &dpll4_m3x2_ck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_TV_SHIFT,
.flags = INVERT_ENABLE,
.clkdm_name = "dpll4_clkdm",
};
DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
static struct clk_core dpll4_m3x2_ck_3630_core = {
.name = "dpll4_m3x2_ck",
.hw = &dpll4_m3x2_ck_hw.hw,
.parent_names = dpll4_m3x2_ck_parent_names,
.num_parents = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
.ops = &dpll4_m5x2_ck_3630_ops,
};
static struct clk dpll4_m3x2_ck_3630 = {
.core = &dpll4_m3x2_ck_3630_core,
};
static const char *omap_54m_fck_parent_names[] = {
"dpll4_m3x2_ck", "sys_altclk",
};
DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
static const struct clksel clkout2_src_clksel[] = {
{ .parent = &core_ck, .rates = clkout2_src_core_rates },
{ .parent = &sys_ck, .rates = clkout2_src_sys_rates },
{ .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
{ .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
{ .parent = NULL },
};
static const char *clkout2_src_ck_parent_names[] = {
"core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
};
static const struct clk_ops clkout2_src_ck_ops = {
.init = &omap2_init_clk_clkdm,
.enable = &omap2_dflt_clk_enable,
.disable = &omap2_dflt_clk_disable,
.is_enabled = &omap2_dflt_clk_is_enabled,
.recalc_rate = &omap2_clksel_recalc,
.get_parent = &omap2_clksel_find_parent_index,
.set_parent = &omap2_clksel_set_parent,
};
DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
OMAP3430_CLKOUT2SOURCE_MASK,
OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
static const struct clksel_rate omap_48m_cm96m_rates[] = {
{ .div = 2, .val = 0, .flags = RATE_IN_3XXX },
{ .div = 0 }
};
static const struct clksel_rate omap_48m_alt_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
{ .div = 0 }
};
static const struct clksel omap_48m_clksel[] = {
{ .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
{ .parent = &sys_altclk, .rates = omap_48m_alt_rates },
{ .parent = NULL },
};
static const char *omap_48m_fck_parent_names[] = {
"cm_96m_fck", "sys_altclk",
};
static struct clk omap_48m_fck;
static const struct clk_ops omap_48m_fck_ops = {
.recalc_rate = &omap2_clksel_recalc,
.get_parent = &omap2_clksel_find_parent_index,
.set_parent = &omap2_clksel_set_parent,
};
static struct clk_hw_omap omap_48m_fck_hw = {
.hw = {
.clk = &omap_48m_fck,
},
.clksel = omap_48m_clksel,
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_SOURCE_48M_MASK,
};
DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck_core, 0x0,
1, 4);
static struct clk core_12m_fck;
static const char *core_12m_fck_parent_names[] = {
"omap_12m_fck",
};
DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm");
DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops);
static struct clk core_48m_fck;
static const char *core_48m_fck_parent_names[] = {
"omap_48m_fck",
};
DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm");
DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
static const char *omap_96m_fck_parent_names[] = {
"cm_96m_fck", "sys_ck",
};
DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0,
OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL);
static struct clk core_96m_fck;
static const char *core_96m_fck_parent_names[] = {
"omap_96m_fck",
};
DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm");
DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops);
static struct clk core_l3_ick;
static const char *core_l3_ick_parent_names[] = {
"l3_ick",
};
DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck_core, 0x0,
2, 1);
static struct clk corex2_fck;
static const char *corex2_fck_parent_names[] = {
"dpll3_m2x2_ck",
};
DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
static const char *cpefuse_fck_parent_names[] = {
"sys_ck",
};
static struct clk cpefuse_fck;
static struct clk_hw_omap cpefuse_fck_hw = {
.hw = {
.clk = &cpefuse_fck,
},
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(cpefuse_fck, cpefuse_fck_parent_names, aes2_ick_ops);
static struct clk csi2_96m_fck;
static const char *csi2_96m_fck_parent_names[] = {
"core_96m_fck",
};
static struct clk_hw_omap csi2_96m_fck_hw = {
.hw = {
.clk = &csi2_96m_fck,
},
.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_CSI2_SHIFT,
.clkdm_name = "cam_clkdm",
};
DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
static struct clk d2d_26m_fck;
static struct clk_hw_omap d2d_26m_fck_hw = {
.hw = {
.clk = &d2d_26m_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
.clkdm_name = "d2d_clkdm",
};
DEFINE_STRUCT_CLK(d2d_26m_fck, cpefuse_fck_parent_names, aes2_ick_ops);
static struct clk des1_ick;
static struct clk_hw_omap des1_ick_hw = {
.hw = {
.clk = &des1_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_DES1_SHIFT,
};
DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops);
static struct clk des2_ick;
static struct clk_hw_omap des2_ick_hw = {
.hw = {
.clk = &des2_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_DES2_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck_core, 0x0,
OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
static struct clk dpll2_fck;
static struct dpll_data dpll2_dd = {
.mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
.mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
.div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
.clk_bypass = &dpll2_fck,
.clk_ref = &sys_ck,
.freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
.control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
.enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
.modes = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
(1 << DPLL_LOW_POWER_BYPASS)),
.auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
.autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
.autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
.idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
.idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
};
static struct clk dpll2_ck;
static struct clk_hw_omap dpll2_ck_hw = {
.hw = {
.clk = &dpll2_ck,
},
.ops = &clkhwops_omap3_dpll,
.dpll_data = &dpll2_dd,
.clkdm_name = "dpll2_clkdm",
};
DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck_core, 0x0,
OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck_core, 0x0,
OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck_core, 0x0,
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
static struct clk dpll3_m3x2_ck;
static const char *dpll3_m3x2_ck_parent_names[] = {
"dpll3_m3_ck",
};
static struct clk_hw_omap dpll3_m3x2_ck_hw = {
.hw = {
.clk = &dpll3_m3x2_ck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
.flags = INVERT_ENABLE,
.clkdm_name = "dpll3_clkdm",
};
DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
static struct clk_core dpll3_m3x2_ck_3630_core = {
.name = "dpll3_m3x2_ck",
.hw = &dpll3_m3x2_ck_hw.hw,
.parent_names = dpll3_m3x2_ck_parent_names,
.num_parents = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
.ops = &dpll4_m5x2_ck_3630_ops,
};
static struct clk dpll3_m3x2_ck_3630 = {
.core = &dpll3_m3x2_ck_3630_core,
};
DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck_core, 0x0, 2, 1);
DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
0, dpll4_mx_ck_div_table, NULL);
static struct clk dpll4_m4x2_ck;
static const char *dpll4_m4x2_ck_parent_names[] = {
"dpll4_m4_ck",
};
static struct clk_hw_omap dpll4_m4x2_ck_hw = {
.hw = {
.clk = &dpll4_m4x2_ck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
.flags = INVERT_ENABLE,
.clkdm_name = "dpll4_clkdm",
};
DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names,
dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
static struct clk_core dpll4_m4x2_ck_3630_core = {
.name = "dpll4_m4x2_ck",
.hw = &dpll4_m4x2_ck_hw.hw,
.parent_names = dpll4_m4x2_ck_parent_names,
.num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
.ops = &dpll4_m5x2_ck_3630_ops,
.flags = CLK_SET_RATE_PARENT,
};
static struct clk dpll4_m4x2_ck_3630 = {
.core = &dpll4_m4x2_ck_3630_core,
};
DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck_core, 0x0,
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
static struct clk dpll4_m6x2_ck;
static const char *dpll4_m6x2_ck_parent_names[] = {
"dpll4_m6_ck",
};
static struct clk_hw_omap dpll4_m6x2_ck_hw = {
.hw = {
.clk = &dpll4_m6x2_ck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
.flags = INVERT_ENABLE,
.clkdm_name = "dpll4_clkdm",
};
DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
static struct clk_core dpll4_m6x2_ck_3630_core = {
.name = "dpll4_m6x2_ck",
.hw = &dpll4_m6x2_ck_hw.hw,
.parent_names = dpll4_m6x2_ck_parent_names,
.num_parents = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
.ops = &dpll4_m5x2_ck_3630_ops,
};
static struct clk dpll4_m6x2_ck_3630 = {
.core = &dpll4_m6x2_ck_3630_core,
};
DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck_core, 0x0, 2, 1);
static struct dpll_data dpll5_dd = {
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
.mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
.div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
.clk_bypass = &sys_ck,
.clk_ref = &sys_ck,
.freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
.control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
.enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
.auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
.autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
.autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
.idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
.idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
};
static struct clk dpll5_ck;
static struct clk_hw_omap dpll5_ck_hw = {
.hw = {
.clk = &dpll5_ck,
},
.ops = &clkhwops_omap3_dpll,
.dpll_data = &dpll5_dd,
.clkdm_name = "dpll5_clkdm",
};
DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck_core, 0x0,
OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
static struct clk dss1_alwon_fck_3430es1;
static const char *dss1_alwon_fck_3430es1_parent_names[] = {
"dpll4_m4x2_ck",
};
static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
.hw = {
.clk = &dss1_alwon_fck_3430es1,
},
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_DSS1_SHIFT,
.clkdm_name = "dss_clkdm",
};
DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1,
dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
CLK_SET_RATE_PARENT);
static struct clk dss1_alwon_fck_3430es2;
static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
.hw = {
.clk = &dss1_alwon_fck_3430es2,
},
.ops = &clkhwops_omap3430es2_dss_usbhost_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_DSS1_SHIFT,
.clkdm_name = "dss_clkdm",
};
DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2,
dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
CLK_SET_RATE_PARENT);
static struct clk dss2_alwon_fck;
static struct clk_hw_omap dss2_alwon_fck_hw = {
.hw = {
.clk = &dss2_alwon_fck,
},
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_DSS2_SHIFT,
.clkdm_name = "dss_clkdm",
};
DEFINE_STRUCT_CLK(dss2_alwon_fck, cpefuse_fck_parent_names, aes2_ick_ops);
static struct clk dss_96m_fck;
static struct clk_hw_omap dss_96m_fck_hw = {
.hw = {
.clk = &dss_96m_fck,
},
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
.clkdm_name = "dss_clkdm",
};
DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops);
static struct clk dss_ick_3430es1;
static struct clk_hw_omap dss_ick_3430es1_hw = {
.hw = {
.clk = &dss_ick_3430es1,
},
.ops = &clkhwops_iclk,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
.clkdm_name = "dss_clkdm",
};
DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops);
static struct clk dss_ick_3430es2;
static struct clk_hw_omap dss_ick_3430es2_hw = {
.hw = {
.clk = &dss_ick_3430es2,
},
.ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
.clkdm_name = "dss_clkdm",
};
DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops);
static struct clk dss_tv_fck;
static const char *dss_tv_fck_parent_names[] = {
"omap_54m_fck",
};
static struct clk_hw_omap dss_tv_fck_hw = {
.hw = {
.clk = &dss_tv_fck,
},
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
.clkdm_name = "dss_clkdm",
};
DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops);
static struct clk emac_fck;
static const char *emac_fck_parent_names[] = {
"rmii_ck",
};
static struct clk_hw_omap emac_fck_hw = {
.hw = {
.clk = &emac_fck,
},
.enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
.enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
};
DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops);
static struct clk ipss_ick;
static const char *ipss_ick_parent_names[] = {
"core_l3_ick",
};
static struct clk_hw_omap ipss_ick_hw = {
.hw = {
.clk = &ipss_ick,
},
.ops = &clkhwops_am35xx_ipss_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = AM35XX_EN_IPSS_SHIFT,
.clkdm_name = "core_l3_clkdm",
};
DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops);
static struct clk emac_ick;
static const char *emac_ick_parent_names[] = {
"ipss_ick",
};
static struct clk_hw_omap emac_ick_hw = {
.hw = {
.clk = &emac_ick,
},
.ops = &clkhwops_am35xx_ipss_module_wait,
.enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
.enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
.clkdm_name = "core_l3_clkdm",
};
DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops);
static struct clk emu_core_alwon_ck;
static const char *emu_core_alwon_ck_parent_names[] = {
"dpll3_m3x2_ck",
};
DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm");
DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names,
core_l4_ick_ops);
static struct clk emu_mpu_alwon_ck;
static const char *emu_mpu_alwon_ck_parent_names[] = {
"mpu_ck",
};
DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL);
DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops);
static struct clk emu_per_alwon_ck;
static const char *emu_per_alwon_ck_parent_names[] = {
"dpll4_m6x2_ck",
};
DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm");
DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names,
core_l4_ick_ops);
static const char *emu_src_ck_parent_names[] = {
"sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
};
static const struct clksel_rate emu_src_sys_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
{ .div = 0 },
};
static const struct clksel_rate emu_src_core_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
{ .div = 0 },
};
static const struct clksel_rate emu_src_per_rates[] = {
{ .div = 1, .val = 2, .flags = RATE_IN_3XXX },
{ .div = 0 },
};
static const struct clksel_rate emu_src_mpu_rates[] = {
{ .div = 1, .val = 3, .flags = RATE_IN_3XXX },
{ .div = 0 },
};
static const struct clksel emu_src_clksel[] = {
{ .parent = &sys_ck, .rates = emu_src_sys_rates },
{ .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
{ .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
{ .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
{ .parent = NULL },
};
static const struct clk_ops emu_src_ck_ops = {
.init = &omap2_init_clk_clkdm,
.recalc_rate = &omap2_clksel_recalc,
.get_parent = &omap2_clksel_find_parent_index,
.set_parent = &omap2_clksel_set_parent,
.enable = &omap2_clkops_enable_clkdm,
.disable = &omap2_clkops_disable_clkdm,
};
static struct clk emu_src_ck;
static struct clk_hw_omap emu_src_ck_hw = {
.hw = {
.clk = &emu_src_ck,
},
.clksel = emu_src_clksel,
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_MUX_CTRL_MASK,
.clkdm_name = "emu_clkdm",
};
DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck_core, 0x0,
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
static struct clk fac_ick;
static struct clk_hw_omap fac_ick_hw = {
.hw = {
.clk = &fac_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk fshostusb_fck;
static const char *fshostusb_fck_parent_names[] = {
"core_48m_fck",
};
static struct clk_hw_omap fshostusb_fck_hw = {
.hw = {
.clk = &fshostusb_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops);
static struct clk gfx_l3_ck;
static struct clk_hw_omap gfx_l3_ck_hw = {
.hw = {
.clk = &gfx_l3_ck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
.enable_bit = OMAP_EN_GFX_SHIFT,
.clkdm_name = "gfx_3430es1_clkdm",
};
DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick_core, 0x0,
OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
static struct clk gfx_cg1_ck;
static const char *gfx_cg1_ck_parent_names[] = {
"gfx_l3_fck",
};
static struct clk_hw_omap gfx_cg1_ck_hw = {
.hw = {
.clk = &gfx_cg1_ck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_2D_SHIFT,
.clkdm_name = "gfx_3430es1_clkdm",
};
DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
static struct clk gfx_cg2_ck;
static struct clk_hw_omap gfx_cg2_ck_hw = {
.hw = {
.clk = &gfx_cg2_ck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_3D_SHIFT,
.clkdm_name = "gfx_3430es1_clkdm",
};
DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
static struct clk gfx_l3_ick;
static const char *gfx_l3_ick_parent_names[] = {
"gfx_l3_ck",
};
DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm");
DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops);
static struct clk wkup_32k_fck;
static const char *wkup_32k_fck_parent_names[] = {
"omap_32k_fck",
};
DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm");
DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops);
static struct clk gpio1_dbck;
static const char *gpio1_dbck_parent_names[] = {
"wkup_32k_fck",
};
static struct clk_hw_omap gpio1_dbck_hw = {
.hw = {
.clk = &gpio1_dbck,
},
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.clkdm_name = "wkup_clkdm",
};
DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
static struct clk wkup_l4_ick;
DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
DEFINE_STRUCT_CLK(wkup_l4_ick, cpefuse_fck_parent_names, core_l4_ick_ops);
static struct clk gpio1_ick;
static const char *gpio1_ick_parent_names[] = {
"wkup_l4_ick",
};
static struct clk_hw_omap gpio1_ick_hw = {
.hw = {
.clk = &gpio1_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.clkdm_name = "wkup_clkdm",
};
DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops);
static struct clk per_32k_alwon_fck;
DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm");
DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names,
core_l4_ick_ops);
static struct clk gpio2_dbck;
static const char *gpio2_dbck_parent_names[] = {
"per_32k_alwon_fck",
};
static struct clk_hw_omap gpio2_dbck_hw = {
.hw = {
.clk = &gpio2_dbck,
},
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
static struct clk per_l4_ick;
DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm");
DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
static struct clk gpio2_ick;
static const char *gpio2_ick_parent_names[] = {
"per_l4_ick",
};
static struct clk_hw_omap gpio2_ick_hw = {
.hw = {
.clk = &gpio2_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops);
static struct clk gpio3_dbck;
static struct clk_hw_omap gpio3_dbck_hw = {
.hw = {
.clk = &gpio3_dbck,
},
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
static struct clk gpio3_ick;
static struct clk_hw_omap gpio3_ick_hw = {
.hw = {
.clk = &gpio3_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops);
static struct clk gpio4_dbck;
static struct clk_hw_omap gpio4_dbck_hw = {
.hw = {
.clk = &gpio4_dbck,
},
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
static struct clk gpio4_ick;
static struct clk_hw_omap gpio4_ick_hw = {
.hw = {
.clk = &gpio4_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops);
static struct clk gpio5_dbck;
static struct clk_hw_omap gpio5_dbck_hw = {
.hw = {
.clk = &gpio5_dbck,
},
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
static struct clk gpio5_ick;
static struct clk_hw_omap gpio5_ick_hw = {
.hw = {
.clk = &gpio5_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops);
static struct clk gpio6_dbck;
static struct clk_hw_omap gpio6_dbck_hw = {
.hw = {
.clk = &gpio6_dbck,
},
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
static struct clk gpio6_ick;
static struct clk_hw_omap gpio6_ick_hw = {
.hw = {
.clk = &gpio6_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops);
static struct clk gpmc_fck;
static struct clk_hw_omap gpmc_fck_hw = {
.hw = {
.clk = &gpmc_fck,
},
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l3_clkdm",
};
DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops);
static const struct clksel omap343x_gpt_clksel[] = {
{ .parent = &omap_32k_fck, .rates = gpt_32k_rates },
{ .parent = &sys_ck, .rates = gpt_sys_rates },
{ .parent = NULL },
};
static const char *gpt10_fck_parent_names[] = {
"omap_32k_fck", "sys_ck",
};
DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel,
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_GPT10_MASK,
OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait,
gpt10_fck_parent_names, clkout2_src_ck_ops);
static struct clk gpt10_ick;
static struct clk_hw_omap gpt10_ick_hw = {
.hw = {
.clk = &gpt10_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel,
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_GPT11_MASK,
OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait,
gpt10_fck_parent_names, clkout2_src_ck_ops);
static struct clk gpt11_ick;
static struct clk_hw_omap gpt11_ick_hw = {
.hw = {
.clk = &gpt11_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk gpt12_fck;
static const char *gpt12_fck_parent_names[] = {
"secure_32k_fck",
};
DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm");
DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops);
static struct clk gpt12_ick;
static struct clk_hw_omap gpt12_ick_hw = {
.hw = {
.clk = &gpt12_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT12_SHIFT,
.clkdm_name = "wkup_clkdm",
};
DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel,
OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_GPT1_MASK,
OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait,
gpt10_fck_parent_names, clkout2_src_ck_ops);
static struct clk gpt1_ick;
static struct clk_hw_omap gpt1_ick_hw = {
.hw = {
.clk = &gpt1_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
.clkdm_name = "wkup_clkdm",
};
DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_GPT2_MASK,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait,
gpt10_fck_parent_names, clkout2_src_ck_ops);
static struct clk gpt2_ick;
static struct clk_hw_omap gpt2_ick_hw = {
.hw = {
.clk = &gpt2_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_GPT3_MASK,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait,
gpt10_fck_parent_names, clkout2_src_ck_ops);
static struct clk gpt3_ick;
static struct clk_hw_omap gpt3_ick_hw = {
.hw = {
.clk = &gpt3_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_GPT4_MASK,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait,
gpt10_fck_parent_names, clkout2_src_ck_ops);
static struct clk gpt4_ick;
static struct clk_hw_omap gpt4_ick_hw = {
.hw = {
.clk = &gpt4_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_GPT5_MASK,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait,
gpt10_fck_parent_names, clkout2_src_ck_ops);
static struct clk gpt5_ick;
static struct clk_hw_omap gpt5_ick_hw = {
.hw = {
.clk = &gpt5_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_GPT6_MASK,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait,
gpt10_fck_parent_names, clkout2_src_ck_ops);
static struct clk gpt6_ick;
static struct clk_hw_omap gpt6_ick_hw = {
.hw = {
.clk = &gpt6_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_GPT7_MASK,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait,
gpt10_fck_parent_names, clkout2_src_ck_ops);
static struct clk gpt7_ick;
static struct clk_hw_omap gpt7_ick_hw = {
.hw = {
.clk = &gpt7_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_GPT8_MASK,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait,
gpt10_fck_parent_names, clkout2_src_ck_ops);
static struct clk gpt8_ick;
static struct clk_hw_omap gpt8_ick_hw = {
.hw = {
.clk = &gpt8_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_GPT9_MASK,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait,
gpt10_fck_parent_names, clkout2_src_ck_ops);
static struct clk gpt9_ick;
static struct clk_hw_omap gpt9_ick_hw = {
.hw = {
.clk = &gpt9_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops);
static struct clk hdq_fck;
static const char *hdq_fck_parent_names[] = {
"core_12m_fck",
};
static struct clk_hw_omap hdq_fck_hw = {
.hw = {
.clk = &hdq_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops);
static struct clk hdq_ick;
static struct clk_hw_omap hdq_ick_hw = {
.hw = {
.clk = &hdq_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk hecc_ck;
static struct clk_hw_omap hecc_ck_hw = {
.hw = {
.clk = &hecc_ck,
},
.ops = &clkhwops_am35xx_ipss_module_wait,
.enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
.enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
.clkdm_name = "core_l3_clkdm",
};
DEFINE_STRUCT_CLK(hecc_ck, cpefuse_fck_parent_names, aes2_ick_ops);
static struct clk hsotgusb_fck_am35xx;
static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
.hw = {
.clk = &hsotgusb_fck_am35xx,
},
.enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
.enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
.clkdm_name = "core_l3_clkdm",
};
DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, cpefuse_fck_parent_names, aes2_ick_ops);
static struct clk hsotgusb_ick_3430es1;
static struct clk_hw_omap hsotgusb_ick_3430es1_hw = {
.hw = {
.clk = &hsotgusb_ick_3430es1,
},
.ops = &clkhwops_iclk,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
.clkdm_name = "core_l3_clkdm",
};
DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops);
static struct clk hsotgusb_ick_3430es2;
static struct clk_hw_omap hsotgusb_ick_3430es2_hw = {
.hw = {
.clk = &hsotgusb_ick_3430es2,
},
.ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
.clkdm_name = "core_l3_clkdm",
};
DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops);
static struct clk hsotgusb_ick_am35xx;
static struct clk_hw_omap hsotgusb_ick_am35xx_hw = {
.hw = {
.clk = &hsotgusb_ick_am35xx,
},
.ops = &clkhwops_am35xx_ipss_module_wait,
.enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
.enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
.clkdm_name = "core_l3_clkdm",
};
DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops);
static struct clk i2c1_fck;
static struct clk_hw_omap i2c1_fck_hw = {
.hw = {
.clk = &i2c1_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
static struct clk i2c1_ick;
static struct clk_hw_omap i2c1_ick_hw = {
.hw = {
.clk = &i2c1_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk i2c2_fck;
static struct clk_hw_omap i2c2_fck_hw = {
.hw = {
.clk = &i2c2_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
static struct clk i2c2_ick;
static struct clk_hw_omap i2c2_ick_hw = {
.hw = {
.clk = &i2c2_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk i2c3_fck;
static struct clk_hw_omap i2c3_fck_hw = {
.hw = {
.clk = &i2c3_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
static struct clk i2c3_ick;
static struct clk_hw_omap i2c3_ick_hw = {
.hw = {
.clk = &i2c3_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk icr_ick;
static struct clk_hw_omap icr_ick_hw = {
.hw = {
.clk = &icr_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_ICR_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk iva2_ck;
static const char *iva2_ck_parent_names[] = {
"dpll2_m2_ck",
};
static struct clk_hw_omap iva2_ck_hw = {
.hw = {
.clk = &iva2_ck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
.clkdm_name = "iva2_clkdm",
};
DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops);
static struct clk mad2d_ick;
static struct clk_hw_omap mad2d_ick_hw = {
.hw = {
.clk = &mad2d_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP3430_EN_MAD2D_SHIFT,
.clkdm_name = "d2d_clkdm",
};
DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
static struct clk mailboxes_ick;
static struct clk_hw_omap mailboxes_ick_hw = {
.hw = {
.clk = &mailboxes_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops);
static const struct clksel_rate common_mcbsp_96m_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
{ .div = 0 }
};
static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
{ .div = 0 }
};
static const struct clksel mcbsp_15_clksel[] = {
{ .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
{ .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
{ .parent = NULL },
};
static const char *mcbsp1_fck_parent_names[] = {
"core_96m_fck", "mcbsp_clks",
};
DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel,
OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
OMAP2_MCBSP1_CLKS_MASK,
OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait,
mcbsp1_fck_parent_names, clkout2_src_ck_ops);
static struct clk mcbsp1_ick;
static struct clk_hw_omap mcbsp1_ick_hw = {
.hw = {
.clk = &mcbsp1_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk per_96m_fck;
DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm");
DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops);
static const struct clksel mcbsp_234_clksel[] = {
{ .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
{ .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
{ .parent = NULL },
};
static const char *mcbsp2_fck_parent_names[] = {
"per_96m_fck", "mcbsp_clks",
};
DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel,
OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
OMAP2_MCBSP2_CLKS_MASK,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait,
mcbsp2_fck_parent_names, clkout2_src_ck_ops);
static struct clk mcbsp2_ick;
static struct clk_hw_omap mcbsp2_ick_hw = {
.hw = {
.clk = &mcbsp2_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel,
OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
OMAP2_MCBSP3_CLKS_MASK,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait,
mcbsp2_fck_parent_names, clkout2_src_ck_ops);
static struct clk mcbsp3_ick;
static struct clk_hw_omap mcbsp3_ick_hw = {
.hw = {
.clk = &mcbsp3_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel,
OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
OMAP2_MCBSP4_CLKS_MASK,
OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait,
mcbsp2_fck_parent_names, clkout2_src_ck_ops);
static struct clk mcbsp4_ick;
static struct clk_hw_omap mcbsp4_ick_hw = {
.hw = {
.clk = &mcbsp4_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel,
OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
OMAP2_MCBSP5_CLKS_MASK,
OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait,
mcbsp1_fck_parent_names, clkout2_src_ck_ops);
static struct clk mcbsp5_ick;
static struct clk_hw_omap mcbsp5_ick_hw = {
.hw = {
.clk = &mcbsp5_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk mcspi1_fck;
static struct clk_hw_omap mcspi1_fck_hw = {
.hw = {
.clk = &mcspi1_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
static struct clk mcspi1_ick;
static struct clk_hw_omap mcspi1_ick_hw = {
.hw = {
.clk = &mcspi1_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk mcspi2_fck;
static struct clk_hw_omap mcspi2_fck_hw = {
.hw = {
.clk = &mcspi2_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
static struct clk mcspi2_ick;
static struct clk_hw_omap mcspi2_ick_hw = {
.hw = {
.clk = &mcspi2_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk mcspi3_fck;
static struct clk_hw_omap mcspi3_fck_hw = {
.hw = {
.clk = &mcspi3_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops);
static struct clk mcspi3_ick;
static struct clk_hw_omap mcspi3_ick_hw = {
.hw = {
.clk = &mcspi3_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk mcspi4_fck;
static struct clk_hw_omap mcspi4_fck_hw = {
.hw = {
.clk = &mcspi4_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops);
static struct clk mcspi4_ick;
static struct clk_hw_omap mcspi4_ick_hw = {
.hw = {
.clk = &mcspi4_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk mmchs1_fck;
static struct clk_hw_omap mmchs1_fck_hw = {
.hw = {
.clk = &mmchs1_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
static struct clk mmchs1_ick;
static struct clk_hw_omap mmchs1_ick_hw = {
.hw = {
.clk = &mmchs1_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk mmchs2_fck;
static struct clk_hw_omap mmchs2_fck_hw = {
.hw = {
.clk = &mmchs2_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
static struct clk mmchs2_ick;
static struct clk_hw_omap mmchs2_ick_hw = {
.hw = {
.clk = &mmchs2_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk mmchs3_fck;
static struct clk_hw_omap mmchs3_fck_hw = {
.hw = {
.clk = &mmchs3_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
static struct clk mmchs3_ick;
static struct clk_hw_omap mmchs3_ick_hw = {
.hw = {
.clk = &mmchs3_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk modem_fck;
static struct clk_hw_omap modem_fck_hw = {
.hw = {
.clk = &modem_fck,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MODEM_SHIFT,
.clkdm_name = "d2d_clkdm",
};
DEFINE_STRUCT_CLK(modem_fck, cpefuse_fck_parent_names, aes2_ick_ops);
static struct clk mspro_fck;
static struct clk_hw_omap mspro_fck_hw = {
.hw = {
.clk = &mspro_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
static struct clk mspro_ick;
static struct clk_hw_omap mspro_ick_hw = {
.hw = {
.clk = &mspro_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk omap_192m_alwon_fck;
DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL);
DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names,
core_ck_ops);
static struct clk omap_32ksync_ick;
static struct clk_hw_omap omap_32ksync_ick_hw = {
.hw = {
.clk = &omap_32ksync_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
.clkdm_name = "wkup_clkdm",
};
DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops);
static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_36XX },
{ .div = 2, .val = 2, .flags = RATE_IN_36XX },
{ .div = 0 }
};
static const struct clksel omap_96m_alwon_fck_clksel[] = {
{ .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
{ .parent = NULL }
};
static struct clk omap_96m_alwon_fck_3630;
static const char *omap_96m_alwon_fck_3630_parent_names[] = {
"omap_192m_alwon_fck",
};
static const struct clk_ops omap_96m_alwon_fck_3630_ops = {
.set_rate = &omap2_clksel_set_rate,
.recalc_rate = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
};
static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
.hw = {
.clk = &omap_96m_alwon_fck_3630,
},
.clksel = omap_96m_alwon_fck_clksel,
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3630_CLKSEL_96M_MASK,
};
static struct clk_core omap_96m_alwon_fck_3630_core = {
.name = "omap_96m_alwon_fck",
.hw = &omap_96m_alwon_fck_3630_hw.hw,
.parent_names = omap_96m_alwon_fck_3630_parent_names,
.num_parents = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
.ops = &omap_96m_alwon_fck_3630_ops,
};
static struct clk omap_96m_alwon_fck_3630 = {
.core = &omap_96m_alwon_fck_3630_core,
};
static struct clk omapctrl_ick;
static struct clk_hw_omap omapctrl_ick_hw = {
.hw = {
.clk = &omapctrl_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck_core, 0x0,
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck_core, 0x0,
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
static struct clk per_48m_fck;
DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm");
DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
static struct clk security_l3_ick;
DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
static struct clk pka_ick;
static const char *pka_ick_parent_names[] = {
"security_l3_ick",
};
static struct clk_hw_omap pka_ick_hw = {
.hw = {
.clk = &pka_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_PKA_SHIFT,
};
DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick_core, 0x0,
OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
static struct clk rng_ick;
static struct clk_hw_omap rng_ick_hw = {
.hw = {
.clk = &rng_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_RNG_SHIFT,
};
DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
static struct clk sad2d_ick;
static struct clk_hw_omap sad2d_ick_hw = {
.hw = {
.clk = &sad2d_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SAD2D_SHIFT,
.clkdm_name = "d2d_clkdm",
};
DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
static struct clk sdrc_ick;
static struct clk_hw_omap sdrc_ick_hw = {
.hw = {
.clk = &sdrc_ick,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SDRC_SHIFT,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l3_clkdm",
};
DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops);
static const struct clksel_rate sgx_core_rates[] = {
{ .div = 2, .val = 5, .flags = RATE_IN_36XX },
{ .div = 3, .val = 0, .flags = RATE_IN_3XXX },
{ .div = 4, .val = 1, .flags = RATE_IN_3XXX },
{ .div = 6, .val = 2, .flags = RATE_IN_3XXX },
{ .div = 0 }
};
static const struct clksel_rate sgx_96m_rates[] = {
{ .div = 1, .val = 3, .flags = RATE_IN_3XXX },
{ .div = 0 }
};
static const struct clksel_rate sgx_192m_rates[] = {
{ .div = 1, .val = 4, .flags = RATE_IN_36XX },
{ .div = 0 }
};
static const struct clksel_rate sgx_corex2_rates[] = {
{ .div = 3, .val = 6, .flags = RATE_IN_36XX },
{ .div = 5, .val = 7, .flags = RATE_IN_36XX },
{ .div = 0 }
};
static const struct clksel sgx_clksel[] = {
{ .parent = &core_ck, .rates = sgx_core_rates },
{ .parent = &cm_96m_fck, .rates = sgx_96m_rates },
{ .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
{ .parent = &corex2_fck, .rates = sgx_corex2_rates },
{ .parent = NULL },
};
static const char *sgx_fck_parent_names[] = {
"core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
};
static struct clk sgx_fck;
static const struct clk_ops sgx_fck_ops = {
.init = &omap2_init_clk_clkdm,
.enable = &omap2_dflt_clk_enable,
.disable = &omap2_dflt_clk_disable,
.is_enabled = &omap2_dflt_clk_is_enabled,
.recalc_rate = &omap2_clksel_recalc,
.set_rate = &omap2_clksel_set_rate,
.round_rate = &omap2_clksel_round_rate,
.get_parent = &omap2_clksel_find_parent_index,
.set_parent = &omap2_clksel_set_parent,
};
DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel,
OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
OMAP3430ES2_CLKSEL_SGX_MASK,
OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
&clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops);
static struct clk sgx_ick;
static struct clk_hw_omap sgx_ick_hw = {
.hw = {
.clk = &sgx_ick,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
.clkdm_name = "sgx_clkdm",
};
DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops);
static struct clk sha11_ick;
static struct clk_hw_omap sha11_ick_hw = {
.hw = {
.clk = &sha11_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_SHA11_SHIFT,
};
DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops);
static struct clk sha12_ick;
static struct clk_hw_omap sha12_ick_hw = {
.hw = {
.clk = &sha12_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SHA12_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk sr1_fck;
static struct clk_hw_omap sr1_fck_hw = {
.hw = {
.clk = &sr1_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_SR1_SHIFT,
.clkdm_name = "wkup_clkdm",
};
DEFINE_STRUCT_CLK(sr1_fck, cpefuse_fck_parent_names, aes2_ick_ops);
static struct clk sr2_fck;
static struct clk_hw_omap sr2_fck_hw = {
.hw = {
.clk = &sr2_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_SR2_SHIFT,
.clkdm_name = "wkup_clkdm",
};
DEFINE_STRUCT_CLK(sr2_fck, cpefuse_fck_parent_names, aes2_ick_ops);
static struct clk sr_l4_ick;
DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm");
DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
static struct clk ssi_l4_ick;
DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm");
DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
static struct clk ssi_ick_3430es1;
static const char *ssi_ick_3430es1_parent_names[] = {
"ssi_l4_ick",
};
static struct clk_hw_omap ssi_ick_3430es1_hw = {
.hw = {
.clk = &ssi_ick_3430es1,
},
.ops = &clkhwops_iclk,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops);
static struct clk ssi_ick_3430es2;
static struct clk_hw_omap ssi_ick_3430es2_hw = {
.hw = {
.clk = &ssi_ick_3430es2,
},
.ops = &clkhwops_omap3430es2_iclk_ssi_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops);
static const struct clksel_rate ssi_ssr_corex2_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
{ .div = 0 }
};
static const struct clksel ssi_ssr_clksel[] = {
{ .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
{ .parent = NULL },
};
static const char *ssi_ssr_fck_3430es1_parent_names[] = {
"corex2_fck",
};
static const struct clk_ops ssi_ssr_fck_3430es1_ops = {
.init = &omap2_init_clk_clkdm,
.enable = &omap2_dflt_clk_enable,
.disable = &omap2_dflt_clk_disable,
.is_enabled = &omap2_dflt_clk_is_enabled,
.recalc_rate = &omap2_clksel_recalc,
.set_rate = &omap2_clksel_set_rate,
.round_rate = &omap2_clksel_round_rate,
};
DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm",
ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_SSI_MASK,
OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
OMAP3430_EN_SSI_SHIFT,
NULL, ssi_ssr_fck_3430es1_parent_names,
ssi_ssr_fck_3430es1_ops);
DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_SSI_MASK,
OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
OMAP3430_EN_SSI_SHIFT,
NULL, ssi_ssr_fck_3430es1_parent_names,
ssi_ssr_fck_3430es1_ops);
DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
&ssi_ssr_fck_3430es1_core, 0x0, 1, 2);
DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
&ssi_ssr_fck_3430es2_core, 0x0, 1, 2);
static struct clk sys_clkout1;
static const char *sys_clkout1_parent_names[] = {
"osc_sys_ck",
};
static struct clk_hw_omap sys_clkout1_hw = {
.hw = {
.clk = &sys_clkout1,
},
.enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
.enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
};
DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck_core, 0x0,
OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
0x0, NULL);
DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck_core,
0x0,
OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
OMAP3430_CLKSEL_TRACECLK_SHIFT,
OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
static struct clk ts_fck;
static struct clk_hw_omap ts_fck_hw = {
.hw = {
.clk = &ts_fck,
},
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_TS_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops);
static struct clk uart1_fck;
static struct clk_hw_omap uart1_fck_hw = {
.hw = {
.clk = &uart1_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_UART1_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
static struct clk uart1_ick;
static struct clk_hw_omap uart1_ick_hw = {
.hw = {
.clk = &uart1_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART1_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk uart2_fck;
static struct clk_hw_omap uart2_fck_hw = {
.hw = {
.clk = &uart2_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_UART2_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
static struct clk uart2_ick;
static struct clk_hw_omap uart2_ick_hw = {
.hw = {
.clk = &uart2_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART2_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops);
static struct clk uart3_fck;
static const char *uart3_fck_parent_names[] = {
"per_48m_fck",
};
static struct clk_hw_omap uart3_fck_hw = {
.hw = {
.clk = &uart3_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_UART3_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops);
static struct clk uart3_ick;
static struct clk_hw_omap uart3_ick_hw = {
.hw = {
.clk = &uart3_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_UART3_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops);
static struct clk uart4_fck;
static struct clk_hw_omap uart4_fck_hw = {
.hw = {
.clk = &uart4_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3630_EN_UART4_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops);
static struct clk uart4_fck_am35xx;
static struct clk_hw_omap uart4_fck_am35xx_hw = {
.hw = {
.clk = &uart4_fck_am35xx,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = AM35XX_EN_UART4_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops);
static struct clk uart4_ick;
static struct clk_hw_omap uart4_ick_hw = {
.hw = {
.clk = &uart4_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3630_EN_UART4_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops);
static struct clk uart4_ick_am35xx;
static struct clk_hw_omap uart4_ick_am35xx_hw = {
.hw = {
.clk = &uart4_ick_am35xx,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = AM35XX_EN_UART4_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops);
static const struct clksel_rate div2_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
{ .div = 0 }
};
static const struct clksel usb_l4_clksel[] = {
{ .parent = &l4_ick, .rates = div2_rates },
{ .parent = NULL },
};
static const char *usb_l4_ick_parent_names[] = {
"l4_ick",
};
DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel,
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
&clkhwops_iclk_wait, usb_l4_ick_parent_names,
ssi_ssr_fck_3430es1_ops);
static struct clk usbhost_120m_fck;
static const char *usbhost_120m_fck_parent_names[] = {
"dpll5_m2_ck",
};
static struct clk_hw_omap usbhost_120m_fck_hw = {
.hw = {
.clk = &usbhost_120m_fck,
},
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
.clkdm_name = "usbhost_clkdm",
};
DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names,
aes2_ick_ops);
static struct clk usbhost_48m_fck;
static struct clk_hw_omap usbhost_48m_fck_hw = {
.hw = {
.clk = &usbhost_48m_fck,
},
.ops = &clkhwops_omap3430es2_dss_usbhost_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
.clkdm_name = "usbhost_clkdm",
};
DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops);
static struct clk usbhost_ick;
static struct clk_hw_omap usbhost_ick_hw = {
.hw = {
.clk = &usbhost_ick,
},
.ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
.clkdm_name = "usbhost_clkdm",
};
DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops);
static struct clk usbtll_fck;
static struct clk_hw_omap usbtll_fck_hw = {
.hw = {
.clk = &usbtll_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops);
static struct clk usbtll_ick;
static struct clk_hw_omap usbtll_ick_hw = {
.hw = {
.clk = &usbtll_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
.clkdm_name = "core_l4_clkdm",
};
DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops);
static const struct clksel_rate usim_96m_rates[] = {
{ .div = 2, .val = 3, .flags = RATE_IN_3XXX },
{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
{ .div = 8, .val = 5, .flags = RATE_IN_3XXX },
{ .div = 10, .val = 6, .flags = RATE_IN_3XXX },
{ .div = 0 }
};
static const struct clksel_rate usim_120m_rates[] = {
{ .div = 4, .val = 7, .flags = RATE_IN_3XXX },
{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
{ .div = 16, .val = 9, .flags = RATE_IN_3XXX },
{ .div = 20, .val = 10, .flags = RATE_IN_3XXX },
{ .div = 0 }
};
static const struct clksel usim_clksel[] = {
{ .parent = &omap_96m_fck, .rates = usim_96m_rates },
{ .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
{ .parent = &sys_ck, .rates = div2_rates },
{ .parent = NULL },
};
static const char *usim_fck_parent_names[] = {
"omap_96m_fck", "dpll5_m2_ck", "sys_ck",
};
static struct clk usim_fck;
static const struct clk_ops usim_fck_ops = {
.enable = &omap2_dflt_clk_enable,
.disable = &omap2_dflt_clk_disable,
.is_enabled = &omap2_dflt_clk_is_enabled,
.recalc_rate = &omap2_clksel_recalc,
.get_parent = &omap2_clksel_find_parent_index,
.set_parent = &omap2_clksel_set_parent,
};
DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel,
OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
OMAP3430ES2_CLKSEL_USIMOCP_MASK,
OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait,
usim_fck_parent_names, usim_fck_ops);
static struct clk usim_ick;
static struct clk_hw_omap usim_ick_hw = {
.hw = {
.clk = &usim_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
.clkdm_name = "wkup_clkdm",
};
DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops);
static struct clk vpfe_fck;
static const char *vpfe_fck_parent_names[] = {
"pclk_ck",
};
static struct clk_hw_omap vpfe_fck_hw = {
.hw = {
.clk = &vpfe_fck,
},
.enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
.enable_bit = AM35XX_VPFE_FCLK_SHIFT,
};
DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops);
static struct clk vpfe_ick;
static struct clk_hw_omap vpfe_ick_hw = {
.hw = {
.clk = &vpfe_ick,
},
.ops = &clkhwops_am35xx_ipss_module_wait,
.enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
.enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
.clkdm_name = "core_l3_clkdm",
};
DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops);
static struct clk wdt1_fck;
DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm");
DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops);
static struct clk wdt1_ick;
static struct clk_hw_omap wdt1_ick_hw = {
.hw = {
.clk = &wdt1_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT1_SHIFT,
.clkdm_name = "wkup_clkdm",
};
DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
static struct clk wdt2_fck;
static struct clk_hw_omap wdt2_fck_hw = {
.hw = {
.clk = &wdt2_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
.clkdm_name = "wkup_clkdm",
};
DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops);
static struct clk wdt2_ick;
static struct clk_hw_omap wdt2_ick_hw = {
.hw = {
.clk = &wdt2_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
.clkdm_name = "wkup_clkdm",
};
DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops);
static struct clk wdt3_fck;
static struct clk_hw_omap wdt3_fck_hw = {
.hw = {
.clk = &wdt3_fck,
},
.ops = &clkhwops_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops);
static struct clk wdt3_ick;
static struct clk_hw_omap wdt3_ick_hw = {
.hw = {
.clk = &wdt3_ick,
},
.ops = &clkhwops_iclk_wait,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
.clkdm_name = "per_clkdm",
};
DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
/*
* clocks specific to omap3430es1
*/
static struct omap_clk omap3430es1_clks[] = {
CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
CLK(NULL, "fshostusb_fck", &fshostusb_fck),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
CLK(NULL, "fac_ick", &fac_ick),
CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
CLK(NULL, "usb_l4_ick", &usb_l4_ick),
CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
CLK("omapdss_dss", "ick", &dss_ick_3430es1),
CLK(NULL, "dss_ick", &dss_ick_3430es1),
};
/*
* clocks specific to am35xx
*/
static struct omap_clk am35xx_clks[] = {
CLK(NULL, "ipss_ick", &ipss_ick),
CLK(NULL, "rmii_ck", &rmii_ck),
CLK(NULL, "pclk_ck", &pclk_ck),
CLK(NULL, "emac_ick", &emac_ick),
CLK(NULL, "emac_fck", &emac_fck),
CLK("davinci_emac.0", NULL, &emac_ick),
CLK("davinci_mdio.0", NULL, &emac_fck),
CLK("vpfe-capture", "master", &vpfe_ick),
CLK("vpfe-capture", "slave", &vpfe_fck),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
CLK(NULL, "hecc_ck", &hecc_ck),
CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
};
/*
* clocks specific to omap36xx
*/
static struct omap_clk omap36xx_clks[] = {
CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
CLK(NULL, "uart4_fck", &uart4_fck),
};
/*
* clocks common to omap36xx omap34xx
*/
static struct omap_clk omap34xx_omap36xx_clks[] = {
CLK(NULL, "aes1_ick", &aes1_ick),
CLK("omap_rng", "ick", &rng_ick),
CLK("omap3-rom-rng", "ick", &rng_ick),
CLK(NULL, "sha11_ick", &sha11_ick),
CLK(NULL, "des1_ick", &des1_ick),
CLK(NULL, "cam_mclk", &cam_mclk),
CLK(NULL, "cam_ick", &cam_ick),
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
CLK(NULL, "security_l3_ick", &security_l3_ick),
CLK(NULL, "pka_ick", &pka_ick),
CLK(NULL, "icr_ick", &icr_ick),
CLK("omap-aes", "ick", &aes2_ick),
CLK("omap-sham", "ick", &sha12_ick),
CLK(NULL, "des2_ick", &des2_ick),
CLK(NULL, "mspro_ick", &mspro_ick),
CLK(NULL, "mailboxes_ick", &mailboxes_ick),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
CLK(NULL, "sr1_fck", &sr1_fck),
CLK(NULL, "sr2_fck", &sr2_fck),
CLK(NULL, "sr_l4_ick", &sr_l4_ick),
CLK(NULL, "security_l4_ick2", &security_l4_ick2),
CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
CLK(NULL, "dpll2_fck", &dpll2_fck),
CLK(NULL, "iva2_ck", &iva2_ck),
CLK(NULL, "modem_fck", &modem_fck),
CLK(NULL, "sad2d_ick", &sad2d_ick),
CLK(NULL, "mad2d_ick", &mad2d_ick),
CLK(NULL, "mspro_fck", &mspro_fck),
CLK(NULL, "dpll2_ck", &dpll2_ck),
CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
};
/*
* clocks common to omap36xx and omap3430es2plus
*/
static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
CLK(NULL, "usim_fck", &usim_fck),
CLK(NULL, "usim_ick", &usim_ick),
};
/*
* clocks common to am35xx omap36xx and omap3430es2plus
*/
static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
CLK(NULL, "dpll5_ck", &dpll5_ck),
CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
CLK(NULL, "sgx_fck", &sgx_fck),
CLK(NULL, "sgx_ick", &sgx_ick),
CLK(NULL, "cpefuse_fck", &cpefuse_fck),
CLK(NULL, "ts_fck", &ts_fck),
CLK(NULL, "usbtll_fck", &usbtll_fck),
CLK(NULL, "usbtll_ick", &usbtll_ick),
CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
CLK(NULL, "mmchs3_ick", &mmchs3_ick),
CLK(NULL, "mmchs3_fck", &mmchs3_fck),
CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
CLK("omapdss_dss", "ick", &dss_ick_3430es2),
CLK(NULL, "dss_ick", &dss_ick_3430es2),
CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
CLK(NULL, "usbhost_ick", &usbhost_ick),
};
/*
* common clocks
*/
static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "apb_pclk", &dummy_apb_pclk),
CLK(NULL, "omap_32k_fck", &omap_32k_fck),
CLK(NULL, "virt_12m_ck", &virt_12m_ck),
CLK(NULL, "virt_13m_ck", &virt_13m_ck),
CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
CLK(NULL, "osc_sys_ck", &osc_sys_ck),
CLK("twl", "fck", &osc_sys_ck),
CLK(NULL, "sys_ck", &sys_ck),
CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
CLK(NULL, "sys_altclk", &sys_altclk),
CLK(NULL, "mcbsp_clks", &mcbsp_clks),
CLK(NULL, "sys_clkout1", &sys_clkout1),
CLK(NULL, "dpll1_ck", &dpll1_ck),
CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
CLK(NULL, "dpll3_ck", &dpll3_ck),
CLK(NULL, "core_ck", &core_ck),
CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
CLK(NULL, "dpll4_ck", &dpll4_ck),
CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
CLK(NULL, "omap_96m_fck", &omap_96m_fck),
CLK(NULL, "cm_96m_fck", &cm_96m_fck),
CLK(NULL, "omap_54m_fck", &omap_54m_fck),
CLK(NULL, "omap_48m_fck", &omap_48m_fck),
CLK(NULL, "omap_12m_fck", &omap_12m_fck),
CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
CLK(NULL, "sys_clkout2", &sys_clkout2),
CLK(NULL, "corex2_fck", &corex2_fck),
CLK(NULL, "dpll1_fck", &dpll1_fck),
CLK(NULL, "mpu_ck", &mpu_ck),
CLK(NULL, "arm_fck", &arm_fck),
CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
CLK(NULL, "l3_ick", &l3_ick),
CLK(NULL, "l4_ick", &l4_ick),
CLK(NULL, "rm_ick", &rm_ick),
CLK(NULL, "gpt10_fck", &gpt10_fck),
CLK(NULL, "gpt11_fck", &gpt11_fck),
CLK(NULL, "core_96m_fck", &core_96m_fck),
CLK(NULL, "mmchs2_fck", &mmchs2_fck),
CLK(NULL, "mmchs1_fck", &mmchs1_fck),
CLK(NULL, "i2c3_fck", &i2c3_fck),
CLK(NULL, "i2c2_fck", &i2c2_fck),
CLK(NULL, "i2c1_fck", &i2c1_fck),
CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
CLK(NULL, "core_48m_fck", &core_48m_fck),
CLK(NULL, "mcspi4_fck", &mcspi4_fck),
CLK(NULL, "mcspi3_fck", &mcspi3_fck),
CLK(NULL, "mcspi2_fck", &mcspi2_fck),
CLK(NULL, "mcspi1_fck", &mcspi1_fck),
CLK(NULL, "uart2_fck", &uart2_fck),
CLK(NULL, "uart1_fck", &uart1_fck),
CLK(NULL, "core_12m_fck", &core_12m_fck),
CLK("omap_hdq.0", "fck", &hdq_fck),
CLK(NULL, "hdq_fck", &hdq_fck),
CLK(NULL, "core_l3_ick", &core_l3_ick),
CLK(NULL, "sdrc_ick", &sdrc_ick),
CLK(NULL, "gpmc_fck", &gpmc_fck),
CLK(NULL, "core_l4_ick", &core_l4_ick),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
CLK(NULL, "mmchs2_ick", &mmchs2_ick),
CLK(NULL, "mmchs1_ick", &mmchs1_ick),
CLK("omap_hdq.0", "ick", &hdq_ick),
CLK(NULL, "hdq_ick", &hdq_ick),
CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
CLK(NULL, "mcspi4_ick", &mcspi4_ick),
CLK(NULL, "mcspi3_ick", &mcspi3_ick),
CLK(NULL, "mcspi2_ick", &mcspi2_ick),
CLK(NULL, "mcspi1_ick", &mcspi1_ick),
CLK("omap_i2c.3", "ick", &i2c3_ick),
CLK("omap_i2c.2", "ick", &i2c2_ick),
CLK("omap_i2c.1", "ick", &i2c1_ick),
CLK(NULL, "i2c3_ick", &i2c3_ick),
CLK(NULL, "i2c2_ick", &i2c2_ick),
CLK(NULL, "i2c1_ick", &i2c1_ick),
CLK(NULL, "uart2_ick", &uart2_ick),
CLK(NULL, "uart1_ick", &uart1_ick),
CLK(NULL, "gpt11_ick", &gpt11_ick),
CLK(NULL, "gpt10_ick", &gpt10_ick),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
CLK(NULL, "omapctrl_ick", &omapctrl_ick),
CLK(NULL, "dss_tv_fck", &dss_tv_fck),
CLK(NULL, "dss_96m_fck", &dss_96m_fck),
CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
CLK(NULL, "init_60m_fclk", &dummy_ck),
CLK(NULL, "gpt1_fck", &gpt1_fck),
CLK(NULL, "aes2_ick", &aes2_ick),
CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
CLK(NULL, "gpio1_dbck", &gpio1_dbck),
CLK(NULL, "sha12_ick", &sha12_ick),
CLK(NULL, "wdt2_fck", &wdt2_fck),
CLK("omap_wdt", "ick", &wdt2_ick),
CLK(NULL, "wdt2_ick", &wdt2_ick),
CLK(NULL, "wdt1_ick", &wdt1_ick),
CLK(NULL, "gpio1_ick", &gpio1_ick),
CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
CLK(NULL, "gpt12_ick", &gpt12_ick),
CLK(NULL, "gpt1_ick", &gpt1_ick),
CLK(NULL, "per_96m_fck", &per_96m_fck),
CLK(NULL, "per_48m_fck", &per_48m_fck),
CLK(NULL, "uart3_fck", &uart3_fck),
CLK(NULL, "gpt2_fck", &gpt2_fck),
CLK(NULL, "gpt3_fck", &gpt3_fck),
CLK(NULL, "gpt4_fck", &gpt4_fck),
CLK(NULL, "gpt5_fck", &gpt5_fck),
CLK(NULL, "gpt6_fck", &gpt6_fck),
CLK(NULL, "gpt7_fck", &gpt7_fck),
CLK(NULL, "gpt8_fck", &gpt8_fck),
CLK(NULL, "gpt9_fck", &gpt9_fck),
CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
CLK(NULL, "gpio6_dbck", &gpio6_dbck),
CLK(NULL, "gpio5_dbck", &gpio5_dbck),
CLK(NULL, "gpio4_dbck", &gpio4_dbck),
CLK(NULL, "gpio3_dbck", &gpio3_dbck),
CLK(NULL, "gpio2_dbck", &gpio2_dbck),
CLK(NULL, "wdt3_fck", &wdt3_fck),
CLK(NULL, "per_l4_ick", &per_l4_ick),
CLK(NULL, "gpio6_ick", &gpio6_ick),
CLK(NULL, "gpio5_ick", &gpio5_ick),
CLK(NULL, "gpio4_ick", &gpio4_ick),
CLK(NULL, "gpio3_ick", &gpio3_ick),
CLK(NULL, "gpio2_ick", &gpio2_ick),
CLK(NULL, "wdt3_ick", &wdt3_ick),
CLK(NULL, "uart3_ick", &uart3_ick),
CLK(NULL, "uart4_ick", &uart4_ick),
CLK(NULL, "gpt9_ick", &gpt9_ick),
CLK(NULL, "gpt8_ick", &gpt8_ick),
CLK(NULL, "gpt7_ick", &gpt7_ick),
CLK(NULL, "gpt6_ick", &gpt6_ick),
CLK(NULL, "gpt5_ick", &gpt5_ick),
CLK(NULL, "gpt4_ick", &gpt4_ick),
CLK(NULL, "gpt3_ick", &gpt3_ick),
CLK(NULL, "gpt2_ick", &gpt2_ick),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
CLK(NULL, "mcbsp4_ick", &mcbsp2_ick),
CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
CLK(NULL, "mcbsp2_ick", &mcbsp4_ick),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
CLK("etb", "emu_src_ck", &emu_src_ck),
CLK(NULL, "emu_src_ck", &emu_src_ck),
CLK(NULL, "pclk_fck", &pclk_fck),
CLK(NULL, "pclkx2_fck", &pclkx2_fck),
CLK(NULL, "atclk_fck", &atclk_fck),
CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
CLK(NULL, "traceclk_fck", &traceclk_fck),
CLK(NULL, "secure_32k_fck", &secure_32k_fck),
CLK(NULL, "gpt12_fck", &gpt12_fck),
CLK(NULL, "wdt1_fck", &wdt1_fck),
CLK(NULL, "timer_32k_ck", &omap_32k_fck),
CLK(NULL, "timer_sys_ck", &sys_ck),
CLK(NULL, "cpufreq_ck", &dpll1_ck),
};
static const char *enable_init_clks[] = {
"sdrc_ick",
"gpmc_fck",
"omapctrl_ick",
};
int __init omap3xxx_clk_init(void)
{
if (omap3_has_192mhz_clk())
omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
if (cpu_is_omap3630()) {
dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
}
/*
* XXX This type of dynamic rewriting of the clock tree is
* deprecated and should be revised soon.
*/
if (cpu_is_omap3630())
dpll4_dd = dpll4_dd_3630;
else
dpll4_dd = dpll4_dd_34xx;
/*
* 3505 must be tested before 3517, since 3517 returns true
* for both AM3517 chips and AM3517 family chips, which
* includes 3505. Unfortunately there's no obvious family
* test for 3517/3505 :-(
*/
if (soc_is_am35xx()) {
cpu_mask = RATE_IN_34XX;
omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
} else if (cpu_is_omap3630()) {
cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
omap_clocks_register(omap36xx_omap3430es2plus_clks,
ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
omap_clocks_register(omap34xx_omap36xx_clks,
ARRAY_SIZE(omap34xx_omap36xx_clks));
omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
} else if (soc_is_am33xx()) {
cpu_mask = RATE_IN_AM33XX;
} else if (cpu_is_ti814x()) {
cpu_mask = RATE_IN_TI814X;
} else if (cpu_is_omap34xx()) {
if (omap_rev() == OMAP3430_REV_ES1_0) {
cpu_mask = RATE_IN_3430ES1;
omap_clocks_register(omap3430es1_clks,
ARRAY_SIZE(omap3430es1_clks));
omap_clocks_register(omap34xx_omap36xx_clks,
ARRAY_SIZE(omap34xx_omap36xx_clks));
omap_clocks_register(omap3xxx_clks,
ARRAY_SIZE(omap3xxx_clks));
} else {
/*
* Assume that anything that we haven't matched yet
* has 3430ES2-type clocks.
*/
cpu_mask = RATE_IN_3430ES2PLUS;
omap_clocks_register(omap34xx_omap36xx_clks,
ARRAY_SIZE(omap34xx_omap36xx_clks));
omap_clocks_register(omap36xx_omap3430es2plus_clks,
ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
omap_clocks_register(omap3xxx_clks,
ARRAY_SIZE(omap3xxx_clks));
}
} else {
WARN(1, "clock: could not identify OMAP3 variant\n");
}
omap2_clk_disable_autoidle_all();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
(clk_get_rate(&osc_sys_ck) / 1000000),
(clk_get_rate(&osc_sys_ck) / 100000) % 10,
(clk_get_rate(&core_ck) / 1000000),
(clk_get_rate(&arm_fck) / 1000000));
/*
* Lock DPLL5 -- here only until other device init code can
* handle this
*/
if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
omap3_clk_lock_dpll5();
/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
sdrc_ick_p = clk_get(NULL, "sdrc_ick");
arm_fck_p = clk_get(NULL, "arm_fck");
return 0;
}
arch/arm/mach-omap2/io.c
浏览文件 @ fe767560
......@@ -461,7 +461,17 @@ void __init omap3_init_early(void)
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = omap3xxx_clk_init;
if (!of_have_populated_dt()) {
omap3_prcm_legacy_iomaps_init();
if (soc_is_am35xx())
omap_clk_soc_init = am35xx_clk_legacy_init;
else if (cpu_is_omap3630())
omap_clk_soc_init = omap36xx_clk_legacy_init;
else if (omap_rev() == OMAP3430_REV_ES1_0)
omap_clk_soc_init = omap3430es1_clk_legacy_init;
else
omap_clk_soc_init = omap3430_clk_legacy_init;
}
}
void __init omap3430_init_early(void)
......@@ -509,8 +519,6 @@ void __init ti81xx_init_early(void)
omap_hwmod_init_postsetup();
if (of_have_populated_dt())
omap_clk_soc_init = ti81xx_dt_clk_init;
else
omap_clk_soc_init = omap3xxx_clk_init;
}
void __init omap3_init_late(void)
......@@ -731,6 +739,7 @@ int __init omap_clk_init(void)
ti_clk_init_features();
if (of_have_populated_dt()) {
ret = of_prcm_init();
if (ret)
return ret;
......@@ -740,6 +749,7 @@ int __init omap_clk_init(void)
ti_dt_clk_init_retry_clks();
ti_dt_clockdomains_setup();
}
ret = omap_clk_soc_init();
......
arch/arm/mach-omap2/prm.h
浏览文件 @ fe767560
......@@ -20,6 +20,7 @@ extern void __iomem *prm_base;
extern u16 prm_features;
extern void omap2_set_globals_prm(void __iomem *prm);
int of_prcm_init(void);
void omap3_prcm_legacy_iomaps_init(void);
# endif
/*
......
arch/arm/mach-omap2/prm_common.c
浏览文件 @ fe767560
......@@ -35,6 +35,8 @@
#include "prm44xx.h"
#include "common.h"
#include "clock.h"
#include "cm.h"
#include "control.h"
/*
* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
......@@ -627,6 +629,15 @@ int __init of_prcm_init(void)
return 0;
}
void __init omap3_prcm_legacy_iomaps_init(void)
{
ti_clk_ll_ops = &omap_clk_ll_ops;
clk_memmaps[TI_CLKM_CM] = cm_base + OMAP3430_IVA2_MOD;
clk_memmaps[TI_CLKM_PRM] = prm_base + OMAP3430_IVA2_MOD;
clk_memmaps[TI_CLKM_SCRM] = omap_ctrl_base_get();
}
static int __init prm_late_init(void)
{
if (prm_ll_data->late_init)
......
drivers/clk/ti/Makefile
浏览文件 @ fe767560
......@@ -5,7 +5,8 @@ clk-common = dpll.o composite.o divider.o gate.o \
obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o
obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o
obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o clk-3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
clk-3xxx.o clk-3xxx-legacy.o
obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o
obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o
obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
......
drivers/clk/ti/clk-3xxx-legacy.c 0 → 100644
浏览文件 @ fe767560
/*
* OMAP3 Legacy clock data
*
* Copyright (C) 2014 Texas Instruments, Inc
* Tero Kristo (t-kristo@ti.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
#include "clock.h"
static struct ti_clk_fixed virt_12m_ck_data = {
.frequency = 12000000,
};
static struct ti_clk virt_12m_ck = {
.name = "virt_12m_ck",
.type = TI_CLK_FIXED,
.data = &virt_12m_ck_data,
};
static struct ti_clk_fixed virt_13m_ck_data = {
.frequency = 13000000,
};
static struct ti_clk virt_13m_ck = {
.name = "virt_13m_ck",
.type = TI_CLK_FIXED,
.data = &virt_13m_ck_data,
};
static struct ti_clk_fixed virt_19200000_ck_data = {
.frequency = 19200000,
};
static struct ti_clk virt_19200000_ck = {
.name = "virt_19200000_ck",
.type = TI_CLK_FIXED,
.data = &virt_19200000_ck_data,
};
static struct ti_clk_fixed virt_26000000_ck_data = {
.frequency = 26000000,
};
static struct ti_clk virt_26000000_ck = {
.name = "virt_26000000_ck",
.type = TI_CLK_FIXED,
.data = &virt_26000000_ck_data,
};
static struct ti_clk_fixed virt_38_4m_ck_data = {
.frequency = 38400000,
};
static struct ti_clk virt_38_4m_ck = {
.name = "virt_38_4m_ck",
.type = TI_CLK_FIXED,
.data = &virt_38_4m_ck_data,
};
static struct ti_clk_fixed virt_16_8m_ck_data = {
.frequency = 16800000,
};
static struct ti_clk virt_16_8m_ck = {
.name = "virt_16_8m_ck",
.type = TI_CLK_FIXED,
.data = &virt_16_8m_ck_data,
};
static const char *osc_sys_ck_parents[] = {
"virt_12m_ck",
"virt_13m_ck",
"virt_19200000_ck",
"virt_26000000_ck",
"virt_38_4m_ck",
"virt_16_8m_ck",
};
static struct ti_clk_mux osc_sys_ck_data = {
.num_parents = ARRAY_SIZE(osc_sys_ck_parents),
.reg = 0xd40,
.module = TI_CLKM_PRM,
.parents = osc_sys_ck_parents,
};
static struct ti_clk osc_sys_ck = {
.name = "osc_sys_ck",
.type = TI_CLK_MUX,
.data = &osc_sys_ck_data,
};
static struct ti_clk_divider sys_ck_data = {
.parent = "osc_sys_ck",
.bit_shift = 6,
.max_div = 3,
.reg = 0x1270,
.module = TI_CLKM_PRM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk sys_ck = {
.name = "sys_ck",
.type = TI_CLK_DIVIDER,
.data = &sys_ck_data,
};
static const char *dpll3_ck_parents[] = {
"sys_ck",
"sys_ck",
};
static struct ti_clk_dpll dpll3_ck_data = {
.num_parents = ARRAY_SIZE(dpll3_ck_parents),
.control_reg = 0xd00,
.idlest_reg = 0xd20,
.mult_div1_reg = 0xd40,
.autoidle_reg = 0xd30,
.module = TI_CLKM_CM,
.parents = dpll3_ck_parents,
.flags = CLKF_CORE,
.freqsel_mask = 0xf0,
.div1_mask = 0x7f00,
.idlest_mask = 0x1,
.auto_recal_bit = 0x3,
.max_divider = 0x80,
.min_divider = 0x1,
.recal_en_bit = 0x5,
.max_multiplier = 0x7ff,
.enable_mask = 0x7,
.mult_mask = 0x7ff0000,
.recal_st_bit = 0x5,
.autoidle_mask = 0x7,
};
static struct ti_clk dpll3_ck = {
.name = "dpll3_ck",
.clkdm_name = "dpll3_clkdm",
.type = TI_CLK_DPLL,
.data = &dpll3_ck_data,
};
static struct ti_clk_divider dpll3_m2_ck_data = {
.parent = "dpll3_ck",
.bit_shift = 27,
.max_div = 31,
.reg = 0xd40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll3_m2_ck = {
.name = "dpll3_m2_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll3_m2_ck_data,
};
static struct ti_clk_fixed_factor core_ck_data = {
.parent = "dpll3_m2_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk core_ck = {
.name = "core_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_ck_data,
};
static struct ti_clk_divider l3_ick_data = {
.parent = "core_ck",
.max_div = 3,
.reg = 0xa40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk l3_ick = {
.name = "l3_ick",
.type = TI_CLK_DIVIDER,
.data = &l3_ick_data,
};
static struct ti_clk_fixed_factor security_l3_ick_data = {
.parent = "l3_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk security_l3_ick = {
.name = "security_l3_ick",
.type = TI_CLK_FIXED_FACTOR,
.data = &security_l3_ick_data,
};
static struct ti_clk_fixed_factor wkup_l4_ick_data = {
.parent = "sys_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk wkup_l4_ick = {
.name = "wkup_l4_ick",
.type = TI_CLK_FIXED_FACTOR,
.data = &wkup_l4_ick_data,
};
static struct ti_clk_gate usim_ick_data = {
.parent = "wkup_l4_ick",
.bit_shift = 9,
.reg = 0xc10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk usim_ick = {
.name = "usim_ick",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &usim_ick_data,
};
static struct ti_clk_gate dss2_alwon_fck_data = {
.parent = "sys_ck",
.bit_shift = 1,
.reg = 0xe00,
.module = TI_CLKM_CM,
};
static struct ti_clk dss2_alwon_fck = {
.name = "dss2_alwon_fck",
.clkdm_name = "dss_clkdm",
.type = TI_CLK_GATE,
.data = &dss2_alwon_fck_data,
};
static struct ti_clk_divider l4_ick_data = {
.parent = "l3_ick",
.bit_shift = 2,
.max_div = 3,
.reg = 0xa40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk l4_ick = {
.name = "l4_ick",
.type = TI_CLK_DIVIDER,
.data = &l4_ick_data,
};
static struct ti_clk_fixed_factor core_l4_ick_data = {
.parent = "l4_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk core_l4_ick = {
.name = "core_l4_ick",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_l4_ick_data,
};
static struct ti_clk_gate mmchs2_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 25,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mmchs2_ick = {
.name = "mmchs2_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mmchs2_ick_data,
};
static const char *dpll4_ck_parents[] = {
"sys_ck",
"sys_ck",
};
static struct ti_clk_dpll dpll4_ck_data = {
.num_parents = ARRAY_SIZE(dpll4_ck_parents),
.control_reg = 0xd00,
.idlest_reg = 0xd20,
.mult_div1_reg = 0xd44,
.autoidle_reg = 0xd30,
.module = TI_CLKM_CM,
.parents = dpll4_ck_parents,
.flags = CLKF_PER,
.freqsel_mask = 0xf00000,
.modes = 0x82,
.div1_mask = 0x7f,
.idlest_mask = 0x2,
.auto_recal_bit = 0x13,
.max_divider = 0x80,
.min_divider = 0x1,
.recal_en_bit = 0x6,
.max_multiplier = 0x7ff,
.enable_mask = 0x70000,
.mult_mask = 0x7ff00,
.recal_st_bit = 0x6,
.autoidle_mask = 0x38,
};
static struct ti_clk dpll4_ck = {
.name = "dpll4_ck",
.clkdm_name = "dpll4_clkdm",
.type = TI_CLK_DPLL,
.data = &dpll4_ck_data,
};
static struct ti_clk_divider dpll4_m2_ck_data = {
.parent = "dpll4_ck",
.max_div = 63,
.reg = 0xd48,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll4_m2_ck = {
.name = "dpll4_m2_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll4_m2_ck_data,
};
static struct ti_clk_fixed_factor dpll4_m2x2_mul_ck_data = {
.parent = "dpll4_m2_ck",
.div = 1,
.mult = 2,
};
static struct ti_clk dpll4_m2x2_mul_ck = {
.name = "dpll4_m2x2_mul_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll4_m2x2_mul_ck_data,
};
static struct ti_clk_gate dpll4_m2x2_ck_data = {
.parent = "dpll4_m2x2_mul_ck",
.bit_shift = 0x1b,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m2x2_ck = {
.name = "dpll4_m2x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m2x2_ck_data,
};
static struct ti_clk_fixed_factor omap_96m_alwon_fck_data = {
.parent = "dpll4_m2x2_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk omap_96m_alwon_fck = {
.name = "omap_96m_alwon_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &omap_96m_alwon_fck_data,
};
static struct ti_clk_fixed_factor cm_96m_fck_data = {
.parent = "omap_96m_alwon_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk cm_96m_fck = {
.name = "cm_96m_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &cm_96m_fck_data,
};
static const char *omap_96m_fck_parents[] = {
"cm_96m_fck",
"sys_ck",
};
static struct ti_clk_mux omap_96m_fck_data = {
.bit_shift = 6,
.num_parents = ARRAY_SIZE(omap_96m_fck_parents),
.reg = 0xd40,
.module = TI_CLKM_CM,
.parents = omap_96m_fck_parents,
};
static struct ti_clk omap_96m_fck = {
.name = "omap_96m_fck",
.type = TI_CLK_MUX,
.data = &omap_96m_fck_data,
};
static struct ti_clk_fixed_factor core_96m_fck_data = {
.parent = "omap_96m_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk core_96m_fck = {
.name = "core_96m_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_96m_fck_data,
};
static struct ti_clk_gate mspro_fck_data = {
.parent = "core_96m_fck",
.bit_shift = 23,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk mspro_fck = {
.name = "mspro_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mspro_fck_data,
};
static struct ti_clk_gate dss_ick_3430es2_data = {
.parent = "l4_ick",
.bit_shift = 0,
.reg = 0xe10,
.module = TI_CLKM_CM,
.flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk dss_ick_3430es2 = {
.name = "dss_ick",
.clkdm_name = "dss_clkdm",
.type = TI_CLK_GATE,
.data = &dss_ick_3430es2_data,
};
static struct ti_clk_gate uart4_ick_am35xx_data = {
.parent = "core_l4_ick",
.bit_shift = 23,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk uart4_ick_am35xx = {
.name = "uart4_ick_am35xx",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &uart4_ick_am35xx_data,
};
static struct ti_clk_fixed_factor security_l4_ick2_data = {
.parent = "l4_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk security_l4_ick2 = {
.name = "security_l4_ick2",
.type = TI_CLK_FIXED_FACTOR,
.data = &security_l4_ick2_data,
};
static struct ti_clk_gate aes1_ick_data = {
.parent = "security_l4_ick2",
.bit_shift = 3,
.reg = 0xa14,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk aes1_ick = {
.name = "aes1_ick",
.type = TI_CLK_GATE,
.data = &aes1_ick_data,
};
static const char *dpll5_ck_parents[] = {
"sys_ck",
"sys_ck",
};
static struct ti_clk_dpll dpll5_ck_data = {
.num_parents = ARRAY_SIZE(dpll5_ck_parents),
.control_reg = 0xd04,
.idlest_reg = 0xd24,
.mult_div1_reg = 0xd4c,
.autoidle_reg = 0xd34,
.module = TI_CLKM_CM,
.parents = dpll5_ck_parents,
.freqsel_mask = 0xf0,
.modes = 0x82,
.div1_mask = 0x7f,
.idlest_mask = 0x1,
.auto_recal_bit = 0x3,
.max_divider = 0x80,
.min_divider = 0x1,
.recal_en_bit = 0x19,
.max_multiplier = 0x7ff,
.enable_mask = 0x7,
.mult_mask = 0x7ff00,
.recal_st_bit = 0x19,
.autoidle_mask = 0x7,
};
static struct ti_clk dpll5_ck = {
.name = "dpll5_ck",
.clkdm_name = "dpll5_clkdm",
.type = TI_CLK_DPLL,
.data = &dpll5_ck_data,
};
static struct ti_clk_divider dpll5_m2_ck_data = {
.parent = "dpll5_ck",
.max_div = 31,
.reg = 0xd50,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll5_m2_ck = {
.name = "dpll5_m2_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll5_m2_ck_data,
};
static struct ti_clk_gate usbhost_120m_fck_data = {
.parent = "dpll5_m2_ck",
.bit_shift = 1,
.reg = 0x1400,
.module = TI_CLKM_CM,
};
static struct ti_clk usbhost_120m_fck = {
.name = "usbhost_120m_fck",
.clkdm_name = "usbhost_clkdm",
.type = TI_CLK_GATE,
.data = &usbhost_120m_fck_data,
};
static struct ti_clk_fixed_factor cm_96m_d2_fck_data = {
.parent = "cm_96m_fck",
.div = 2,
.mult = 1,
};
static struct ti_clk cm_96m_d2_fck = {
.name = "cm_96m_d2_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &cm_96m_d2_fck_data,
};
static struct ti_clk_fixed sys_altclk_data = {
.frequency = 0x0,
};
static struct ti_clk sys_altclk = {
.name = "sys_altclk",
.type = TI_CLK_FIXED,
.data = &sys_altclk_data,
};
static const char *omap_48m_fck_parents[] = {
"cm_96m_d2_fck",
"sys_altclk",
};
static struct ti_clk_mux omap_48m_fck_data = {
.bit_shift = 3,
.num_parents = ARRAY_SIZE(omap_48m_fck_parents),
.reg = 0xd40,
.module = TI_CLKM_CM,
.parents = omap_48m_fck_parents,
};
static struct ti_clk omap_48m_fck = {
.name = "omap_48m_fck",
.type = TI_CLK_MUX,
.data = &omap_48m_fck_data,
};
static struct ti_clk_fixed_factor core_48m_fck_data = {
.parent = "omap_48m_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk core_48m_fck = {
.name = "core_48m_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_48m_fck_data,
};
static struct ti_clk_fixed mcbsp_clks_data = {
.frequency = 0x0,
};
static struct ti_clk mcbsp_clks = {
.name = "mcbsp_clks",
.type = TI_CLK_FIXED,
.data = &mcbsp_clks_data,
};
static struct ti_clk_gate mcbsp2_gate_fck_data = {
.parent = "mcbsp_clks",
.bit_shift = 0,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk_fixed_factor per_96m_fck_data = {
.parent = "omap_96m_alwon_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk per_96m_fck = {
.name = "per_96m_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &per_96m_fck_data,
};
static const char *mcbsp2_mux_fck_parents[] = {
"per_96m_fck",
"mcbsp_clks",
};
static struct ti_clk_mux mcbsp2_mux_fck_data = {
.bit_shift = 6,
.num_parents = ARRAY_SIZE(mcbsp2_mux_fck_parents),
.reg = 0x274,
.module = TI_CLKM_SCRM,
.parents = mcbsp2_mux_fck_parents,
};
static struct ti_clk_composite mcbsp2_fck_data = {
.mux = &mcbsp2_mux_fck_data,
.gate = &mcbsp2_gate_fck_data,
};
static struct ti_clk mcbsp2_fck = {
.name = "mcbsp2_fck",
.type = TI_CLK_COMPOSITE,
.data = &mcbsp2_fck_data,
};
static struct ti_clk_fixed_factor dpll3_m2x2_ck_data = {
.parent = "dpll3_m2_ck",
.div = 1,
.mult = 2,
};
static struct ti_clk dpll3_m2x2_ck = {
.name = "dpll3_m2x2_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll3_m2x2_ck_data,
};
static struct ti_clk_fixed_factor corex2_fck_data = {
.parent = "dpll3_m2x2_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk corex2_fck = {
.name = "corex2_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &corex2_fck_data,
};
static struct ti_clk_gate ssi_ssr_gate_fck_3430es1_data = {
.parent = "corex2_fck",
.bit_shift = 0,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_NO_WAIT,
};
static int ssi_ssr_div_fck_3430es1_divs[] = {
0,
1,
2,
3,
4,
0,
6,
0,
8,
};
static struct ti_clk_divider ssi_ssr_div_fck_3430es1_data = {
.num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es1_divs),
.parent = "corex2_fck",
.bit_shift = 8,
.dividers = ssi_ssr_div_fck_3430es1_divs,
.reg = 0xa40,
.module = TI_CLKM_CM,
};
static struct ti_clk_composite ssi_ssr_fck_3430es1_data = {
.gate = &ssi_ssr_gate_fck_3430es1_data,
.divider = &ssi_ssr_div_fck_3430es1_data,
};
static struct ti_clk ssi_ssr_fck_3430es1 = {
.name = "ssi_ssr_fck",
.type = TI_CLK_COMPOSITE,
.data = &ssi_ssr_fck_3430es1_data,
};
static struct ti_clk_fixed_factor ssi_sst_fck_3430es1_data = {
.parent = "ssi_ssr_fck",
.div = 2,
.mult = 1,
};
static struct ti_clk ssi_sst_fck_3430es1 = {
.name = "ssi_sst_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &ssi_sst_fck_3430es1_data,
};
static struct ti_clk_fixed omap_32k_fck_data = {
.frequency = 32768,
};
static struct ti_clk omap_32k_fck = {
.name = "omap_32k_fck",
.type = TI_CLK_FIXED,
.data = &omap_32k_fck_data,
};
static struct ti_clk_fixed_factor per_32k_alwon_fck_data = {
.parent = "omap_32k_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk per_32k_alwon_fck = {
.name = "per_32k_alwon_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &per_32k_alwon_fck_data,
};
static struct ti_clk_gate gpio5_dbck_data = {
.parent = "per_32k_alwon_fck",
.bit_shift = 16,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk gpio5_dbck = {
.name = "gpio5_dbck",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio5_dbck_data,
};
static struct ti_clk_gate gpt1_ick_data = {
.parent = "wkup_l4_ick",
.bit_shift = 0,
.reg = 0xc10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt1_ick = {
.name = "gpt1_ick",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &gpt1_ick_data,
};
static struct ti_clk_gate mcspi3_fck_data = {
.parent = "core_48m_fck",
.bit_shift = 20,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk mcspi3_fck = {
.name = "mcspi3_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mcspi3_fck_data,
};
static struct ti_clk_gate gpt2_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 3,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static const char *gpt2_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt2_mux_fck_data = {
.num_parents = ARRAY_SIZE(gpt2_mux_fck_parents),
.reg = 0x1040,
.module = TI_CLKM_CM,
.parents = gpt2_mux_fck_parents,
};
static struct ti_clk_composite gpt2_fck_data = {
.mux = &gpt2_mux_fck_data,
.gate = &gpt2_gate_fck_data,
};
static struct ti_clk gpt2_fck = {
.name = "gpt2_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt2_fck_data,
};
static struct ti_clk_gate gpt10_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 11,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt10_ick = {
.name = "gpt10_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &gpt10_ick_data,
};
static struct ti_clk_gate uart2_fck_data = {
.parent = "core_48m_fck",
.bit_shift = 14,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk uart2_fck = {
.name = "uart2_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &uart2_fck_data,
};
static struct ti_clk_fixed_factor sr_l4_ick_data = {
.parent = "l4_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk sr_l4_ick = {
.name = "sr_l4_ick",
.type = TI_CLK_FIXED_FACTOR,
.data = &sr_l4_ick_data,
};
static struct ti_clk_fixed_factor omap_96m_d8_fck_data = {
.parent = "omap_96m_fck",
.div = 8,
.mult = 1,
};
static struct ti_clk omap_96m_d8_fck = {
.name = "omap_96m_d8_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &omap_96m_d8_fck_data,
};
static struct ti_clk_divider dpll4_m5_ck_data = {
.parent = "dpll4_ck",
.max_div = 63,
.reg = 0xf40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll4_m5_ck = {
.name = "dpll4_m5_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll4_m5_ck_data,
};
static struct ti_clk_fixed_factor dpll4_m5x2_mul_ck_data = {
.parent = "dpll4_m5_ck",
.div = 1,
.mult = 2,
.flags = CLKF_SET_RATE_PARENT,
};
static struct ti_clk dpll4_m5x2_mul_ck = {
.name = "dpll4_m5x2_mul_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll4_m5x2_mul_ck_data,
};
static struct ti_clk_gate dpll4_m5x2_ck_data = {
.parent = "dpll4_m5x2_mul_ck",
.bit_shift = 0x1e,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m5x2_ck = {
.name = "dpll4_m5x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m5x2_ck_data,
};
static struct ti_clk_gate cam_mclk_data = {
.parent = "dpll4_m5x2_ck",
.bit_shift = 0,
.reg = 0xf00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_RATE_PARENT,
};
static struct ti_clk cam_mclk = {
.name = "cam_mclk",
.type = TI_CLK_GATE,
.data = &cam_mclk_data,
};
static struct ti_clk_gate mcbsp3_gate_fck_data = {
.parent = "mcbsp_clks",
.bit_shift = 1,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static const char *mcbsp3_mux_fck_parents[] = {
"per_96m_fck",
"mcbsp_clks",
};
static struct ti_clk_mux mcbsp3_mux_fck_data = {
.num_parents = ARRAY_SIZE(mcbsp3_mux_fck_parents),
.reg = 0x2d8,
.module = TI_CLKM_SCRM,
.parents = mcbsp3_mux_fck_parents,
};
static struct ti_clk_composite mcbsp3_fck_data = {
.mux = &mcbsp3_mux_fck_data,
.gate = &mcbsp3_gate_fck_data,
};
static struct ti_clk mcbsp3_fck = {
.name = "mcbsp3_fck",
.type = TI_CLK_COMPOSITE,
.data = &mcbsp3_fck_data,
};
static struct ti_clk_gate csi2_96m_fck_data = {
.parent = "core_96m_fck",
.bit_shift = 1,
.reg = 0xf00,
.module = TI_CLKM_CM,
};
static struct ti_clk csi2_96m_fck = {
.name = "csi2_96m_fck",
.clkdm_name = "cam_clkdm",
.type = TI_CLK_GATE,
.data = &csi2_96m_fck_data,
};
static struct ti_clk_gate gpt9_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 10,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static const char *gpt9_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt9_mux_fck_data = {
.bit_shift = 7,
.num_parents = ARRAY_SIZE(gpt9_mux_fck_parents),
.reg = 0x1040,
.module = TI_CLKM_CM,
.parents = gpt9_mux_fck_parents,
};
static struct ti_clk_composite gpt9_fck_data = {
.mux = &gpt9_mux_fck_data,
.gate = &gpt9_gate_fck_data,
};
static struct ti_clk gpt9_fck = {
.name = "gpt9_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt9_fck_data,
};
static struct ti_clk_divider dpll3_m3_ck_data = {
.parent = "dpll3_ck",
.bit_shift = 16,
.max_div = 31,
.reg = 0x1140,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll3_m3_ck = {
.name = "dpll3_m3_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll3_m3_ck_data,
};
static struct ti_clk_fixed_factor dpll3_m3x2_mul_ck_data = {
.parent = "dpll3_m3_ck",
.div = 1,
.mult = 2,
};
static struct ti_clk dpll3_m3x2_mul_ck = {
.name = "dpll3_m3x2_mul_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll3_m3x2_mul_ck_data,
};
static struct ti_clk_gate sr2_fck_data = {
.parent = "sys_ck",
.bit_shift = 7,
.reg = 0xc00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk sr2_fck = {
.name = "sr2_fck",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &sr2_fck_data,
};
static struct ti_clk_fixed pclk_ck_data = {
.frequency = 27000000,
};
static struct ti_clk pclk_ck = {
.name = "pclk_ck",
.type = TI_CLK_FIXED,
.data = &pclk_ck_data,
};
static struct ti_clk_gate wdt2_ick_data = {
.parent = "wkup_l4_ick",
.bit_shift = 5,
.reg = 0xc10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk wdt2_ick = {
.name = "wdt2_ick",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &wdt2_ick_data,
};
static struct ti_clk_fixed_factor core_l3_ick_data = {
.parent = "l3_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk core_l3_ick = {
.name = "core_l3_ick",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_l3_ick_data,
};
static struct ti_clk_gate mcspi4_fck_data = {
.parent = "core_48m_fck",
.bit_shift = 21,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk mcspi4_fck = {
.name = "mcspi4_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mcspi4_fck_data,
};
static struct ti_clk_fixed_factor per_48m_fck_data = {
.parent = "omap_48m_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk per_48m_fck = {
.name = "per_48m_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &per_48m_fck_data,
};
static struct ti_clk_gate uart4_fck_data = {
.parent = "per_48m_fck",
.bit_shift = 18,
.reg = 0x1000,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk uart4_fck = {
.name = "uart4_fck",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &uart4_fck_data,
};
static struct ti_clk_fixed_factor omap_96m_d10_fck_data = {
.parent = "omap_96m_fck",
.div = 10,
.mult = 1,
};
static struct ti_clk omap_96m_d10_fck = {
.name = "omap_96m_d10_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &omap_96m_d10_fck_data,
};
static struct ti_clk_gate usim_gate_fck_data = {
.parent = "omap_96m_fck",
.bit_shift = 9,
.reg = 0xc00,
.module = TI_CLKM_CM,
};
static struct ti_clk_fixed_factor per_l4_ick_data = {
.parent = "l4_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk per_l4_ick = {
.name = "per_l4_ick",
.type = TI_CLK_FIXED_FACTOR,
.data = &per_l4_ick_data,
};
static struct ti_clk_gate gpt5_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 6,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt5_ick = {
.name = "gpt5_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpt5_ick_data,
};
static struct ti_clk_gate mcspi2_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 19,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mcspi2_ick = {
.name = "mcspi2_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mcspi2_ick_data,
};
static struct ti_clk_fixed_factor ssi_l4_ick_data = {
.parent = "l4_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk ssi_l4_ick = {
.name = "ssi_l4_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_FIXED_FACTOR,
.data = &ssi_l4_ick_data,
};
static struct ti_clk_gate ssi_ick_3430es1_data = {
.parent = "ssi_l4_ick",
.bit_shift = 0,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
};
static struct ti_clk ssi_ick_3430es1 = {
.name = "ssi_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &ssi_ick_3430es1_data,
};
static struct ti_clk_gate i2c2_fck_data = {
.parent = "core_96m_fck",
.bit_shift = 16,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk i2c2_fck = {
.name = "i2c2_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &i2c2_fck_data,
};
static struct ti_clk_divider dpll1_fck_data = {
.parent = "core_ck",
.bit_shift = 19,
.max_div = 7,
.reg = 0x940,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll1_fck = {
.name = "dpll1_fck",
.type = TI_CLK_DIVIDER,
.data = &dpll1_fck_data,
};
static const char *dpll1_ck_parents[] = {
"sys_ck",
"dpll1_fck",
};
static struct ti_clk_dpll dpll1_ck_data = {
.num_parents = ARRAY_SIZE(dpll1_ck_parents),
.control_reg = 0x904,
.idlest_reg = 0x924,
.mult_div1_reg = 0x940,
.autoidle_reg = 0x934,
.module = TI_CLKM_CM,
.parents = dpll1_ck_parents,
.freqsel_mask = 0xf0,
.modes = 0xa0,
.div1_mask = 0x7f,
.idlest_mask = 0x1,
.auto_recal_bit = 0x3,
.max_divider = 0x80,
.min_divider = 0x1,
.recal_en_bit = 0x7,
.max_multiplier = 0x7ff,
.enable_mask = 0x7,
.mult_mask = 0x7ff00,
.recal_st_bit = 0x7,
.autoidle_mask = 0x7,
};
static struct ti_clk dpll1_ck = {
.name = "dpll1_ck",
.clkdm_name = "dpll1_clkdm",
.type = TI_CLK_DPLL,
.data = &dpll1_ck_data,
};
static struct ti_clk_fixed secure_32k_fck_data = {
.frequency = 32768,
};
static struct ti_clk secure_32k_fck = {
.name = "secure_32k_fck",
.type = TI_CLK_FIXED,
.data = &secure_32k_fck_data,
};
static struct ti_clk_gate gpio5_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 16,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpio5_ick = {
.name = "gpio5_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio5_ick_data,
};
static struct ti_clk_divider dpll4_m4_ck_data = {
.parent = "dpll4_ck",
.max_div = 32,
.reg = 0xe40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll4_m4_ck = {
.name = "dpll4_m4_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll4_m4_ck_data,
};
static struct ti_clk_fixed_factor dpll4_m4x2_mul_ck_data = {
.parent = "dpll4_m4_ck",
.div = 1,
.mult = 2,
.flags = CLKF_SET_RATE_PARENT,
};
static struct ti_clk dpll4_m4x2_mul_ck = {
.name = "dpll4_m4x2_mul_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll4_m4x2_mul_ck_data,
};
static struct ti_clk_gate dpll4_m4x2_ck_data = {
.parent = "dpll4_m4x2_mul_ck",
.bit_shift = 0x1d,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m4x2_ck = {
.name = "dpll4_m4x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m4x2_ck_data,
};
static struct ti_clk_gate dss1_alwon_fck_3430es2_data = {
.parent = "dpll4_m4x2_ck",
.bit_shift = 0,
.reg = 0xe00,
.module = TI_CLKM_CM,
.flags = CLKF_DSS | CLKF_SET_RATE_PARENT,
};
static struct ti_clk dss1_alwon_fck_3430es2 = {
.name = "dss1_alwon_fck",
.clkdm_name = "dss_clkdm",
.type = TI_CLK_GATE,
.data = &dss1_alwon_fck_3430es2_data,
};
static struct ti_clk_gate uart3_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 11,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk uart3_ick = {
.name = "uart3_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &uart3_ick_data,
};
static struct ti_clk_divider dpll4_m3_ck_data = {
.parent = "dpll4_ck",
.bit_shift = 8,
.max_div = 32,
.reg = 0xe40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll4_m3_ck = {
.name = "dpll4_m3_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll4_m3_ck_data,
};
static struct ti_clk_gate mcbsp3_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 1,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mcbsp3_ick = {
.name = "mcbsp3_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &mcbsp3_ick_data,
};
static struct ti_clk_gate gpio3_dbck_data = {
.parent = "per_32k_alwon_fck",
.bit_shift = 14,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk gpio3_dbck = {
.name = "gpio3_dbck",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio3_dbck_data,
};
static struct ti_clk_gate fac_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 8,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk fac_ick = {
.name = "fac_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &fac_ick_data,
};
static struct ti_clk_gate clkout2_src_gate_ck_data = {
.parent = "core_ck",
.bit_shift = 7,
.reg = 0xd70,
.module = TI_CLKM_CM,
.flags = CLKF_NO_WAIT,
};
static struct ti_clk_fixed_factor dpll4_m3x2_mul_ck_data = {
.parent = "dpll4_m3_ck",
.div = 1,
.mult = 2,
};
static struct ti_clk dpll4_m3x2_mul_ck = {
.name = "dpll4_m3x2_mul_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll4_m3x2_mul_ck_data,
};
static struct ti_clk_gate dpll4_m3x2_ck_data = {
.parent = "dpll4_m3x2_mul_ck",
.bit_shift = 0x1c,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m3x2_ck = {
.name = "dpll4_m3x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m3x2_ck_data,
};
static const char *omap_54m_fck_parents[] = {
"dpll4_m3x2_ck",
"sys_altclk",
};
static struct ti_clk_mux omap_54m_fck_data = {
.bit_shift = 5,
.num_parents = ARRAY_SIZE(omap_54m_fck_parents),
.reg = 0xd40,
.module = TI_CLKM_CM,
.parents = omap_54m_fck_parents,
};
static struct ti_clk omap_54m_fck = {
.name = "omap_54m_fck",
.type = TI_CLK_MUX,
.data = &omap_54m_fck_data,
};
static const char *clkout2_src_mux_ck_parents[] = {
"core_ck",
"sys_ck",
"cm_96m_fck",
"omap_54m_fck",
};
static struct ti_clk_mux clkout2_src_mux_ck_data = {
.num_parents = ARRAY_SIZE(clkout2_src_mux_ck_parents),
.reg = 0xd70,
.module = TI_CLKM_CM,
.parents = clkout2_src_mux_ck_parents,
};
static struct ti_clk_composite clkout2_src_ck_data = {
.mux = &clkout2_src_mux_ck_data,
.gate = &clkout2_src_gate_ck_data,
};
static struct ti_clk clkout2_src_ck = {
.name = "clkout2_src_ck",
.type = TI_CLK_COMPOSITE,
.data = &clkout2_src_ck_data,
};
static struct ti_clk_gate i2c1_fck_data = {
.parent = "core_96m_fck",
.bit_shift = 15,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk i2c1_fck = {
.name = "i2c1_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &i2c1_fck_data,
};
static struct ti_clk_gate wdt3_fck_data = {
.parent = "per_32k_alwon_fck",
.bit_shift = 12,
.reg = 0x1000,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk wdt3_fck = {
.name = "wdt3_fck",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &wdt3_fck_data,
};
static struct ti_clk_gate gpt7_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 8,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static const char *gpt7_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt7_mux_fck_data = {
.bit_shift = 5,
.num_parents = ARRAY_SIZE(gpt7_mux_fck_parents),
.reg = 0x1040,
.module = TI_CLKM_CM,
.parents = gpt7_mux_fck_parents,
};
static struct ti_clk_composite gpt7_fck_data = {
.mux = &gpt7_mux_fck_data,
.gate = &gpt7_gate_fck_data,
};
static struct ti_clk gpt7_fck = {
.name = "gpt7_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt7_fck_data,
};
static struct ti_clk_gate usb_l4_gate_ick_data = {
.parent = "l4_ick",
.bit_shift = 5,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_INTERFACE,
};
static struct ti_clk_divider usb_l4_div_ick_data = {
.parent = "l4_ick",
.bit_shift = 4,
.max_div = 1,
.reg = 0xa40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk_composite usb_l4_ick_data = {
.gate = &usb_l4_gate_ick_data,
.divider = &usb_l4_div_ick_data,
};
static struct ti_clk usb_l4_ick = {
.name = "usb_l4_ick",
.type = TI_CLK_COMPOSITE,
.data = &usb_l4_ick_data,
};
static struct ti_clk_gate uart4_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 18,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk uart4_ick = {
.name = "uart4_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &uart4_ick_data,
};
static struct ti_clk_fixed dummy_ck_data = {
.frequency = 0,
};
static struct ti_clk dummy_ck = {
.name = "dummy_ck",
.type = TI_CLK_FIXED,
.data = &dummy_ck_data,
};
static const char *gpt3_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt3_mux_fck_data = {
.bit_shift = 1,
.num_parents = ARRAY_SIZE(gpt3_mux_fck_parents),
.reg = 0x1040,
.module = TI_CLKM_CM,
.parents = gpt3_mux_fck_parents,
};
static struct ti_clk_gate gpt9_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 10,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt9_ick = {
.name = "gpt9_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpt9_ick_data,
};
static struct ti_clk_gate gpt10_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 11,
.reg = 0xa00,
.module = TI_CLKM_CM,
};
static struct ti_clk_gate dss_ick_3430es1_data = {
.parent = "l4_ick",
.bit_shift = 0,
.reg = 0xe10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
};
static struct ti_clk dss_ick_3430es1 = {
.name = "dss_ick",
.clkdm_name = "dss_clkdm",
.type = TI_CLK_GATE,
.data = &dss_ick_3430es1_data,
};
static struct ti_clk_gate gpt11_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 12,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt11_ick = {
.name = "gpt11_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &gpt11_ick_data,
};
static struct ti_clk_divider dpll2_fck_data = {
.parent = "core_ck",
.bit_shift = 19,
.max_div = 7,
.reg = 0x40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll2_fck = {
.name = "dpll2_fck",
.type = TI_CLK_DIVIDER,
.data = &dpll2_fck_data,
};
static struct ti_clk_gate uart1_fck_data = {
.parent = "core_48m_fck",
.bit_shift = 13,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk uart1_fck = {
.name = "uart1_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &uart1_fck_data,
};
static struct ti_clk_gate hsotgusb_ick_3430es1_data = {
.parent = "core_l3_ick",
.bit_shift = 4,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
};
static struct ti_clk hsotgusb_ick_3430es1 = {
.name = "hsotgusb_ick_3430es1",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &hsotgusb_ick_3430es1_data,
};
static struct ti_clk_gate gpio2_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 13,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpio2_ick = {
.name = "gpio2_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio2_ick_data,
};
static struct ti_clk_gate mmchs1_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 24,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mmchs1_ick = {
.name = "mmchs1_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mmchs1_ick_data,
};
static struct ti_clk_gate modem_fck_data = {
.parent = "sys_ck",
.bit_shift = 31,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk modem_fck = {
.name = "modem_fck",
.clkdm_name = "d2d_clkdm",
.type = TI_CLK_GATE,
.data = &modem_fck_data,
};
static struct ti_clk_gate mcbsp4_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 2,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mcbsp4_ick = {
.name = "mcbsp4_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &mcbsp4_ick_data,
};
static struct ti_clk_gate gpio1_ick_data = {
.parent = "wkup_l4_ick",
.bit_shift = 3,
.reg = 0xc10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpio1_ick = {
.name = "gpio1_ick",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &gpio1_ick_data,
};
static const char *gpt6_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt6_mux_fck_data = {
.bit_shift = 4,
.num_parents = ARRAY_SIZE(gpt6_mux_fck_parents),
.reg = 0x1040,
.module = TI_CLKM_CM,
.parents = gpt6_mux_fck_parents,
};
static struct ti_clk_fixed_factor dpll1_x2_ck_data = {
.parent = "dpll1_ck",
.div = 1,
.mult = 2,
};
static struct ti_clk dpll1_x2_ck = {
.name = "dpll1_x2_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll1_x2_ck_data,
};
static struct ti_clk_divider dpll1_x2m2_ck_data = {
.parent = "dpll1_x2_ck",
.max_div = 31,
.reg = 0x944,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll1_x2m2_ck = {
.name = "dpll1_x2m2_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll1_x2m2_ck_data,
};
static struct ti_clk_fixed_factor mpu_ck_data = {
.parent = "dpll1_x2m2_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk mpu_ck = {
.name = "mpu_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &mpu_ck_data,
};
static struct ti_clk_divider arm_fck_data = {
.parent = "mpu_ck",
.max_div = 2,
.reg = 0x924,
.module = TI_CLKM_CM,
};
static struct ti_clk arm_fck = {
.name = "arm_fck",
.type = TI_CLK_DIVIDER,
.data = &arm_fck_data,
};
static struct ti_clk_fixed_factor core_d3_ck_data = {
.parent = "core_ck",
.div = 3,
.mult = 1,
};
static struct ti_clk core_d3_ck = {
.name = "core_d3_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_d3_ck_data,
};
static struct ti_clk_gate gpt11_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 12,
.reg = 0xa00,
.module = TI_CLKM_CM,
};
static const char *gpt11_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt11_mux_fck_data = {
.bit_shift = 7,
.num_parents = ARRAY_SIZE(gpt11_mux_fck_parents),
.reg = 0xa40,
.module = TI_CLKM_CM,
.parents = gpt11_mux_fck_parents,
};
static struct ti_clk_composite gpt11_fck_data = {
.mux = &gpt11_mux_fck_data,
.gate = &gpt11_gate_fck_data,
};
static struct ti_clk gpt11_fck = {
.name = "gpt11_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt11_fck_data,
};
static struct ti_clk_fixed_factor core_d6_ck_data = {
.parent = "core_ck",
.div = 6,
.mult = 1,
};
static struct ti_clk core_d6_ck = {
.name = "core_d6_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_d6_ck_data,
};
static struct ti_clk_gate uart4_fck_am35xx_data = {
.parent = "core_48m_fck",
.bit_shift = 23,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk uart4_fck_am35xx = {
.name = "uart4_fck_am35xx",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &uart4_fck_am35xx_data,
};
static struct ti_clk_gate dpll3_m3x2_ck_data = {
.parent = "dpll3_m3x2_mul_ck",
.bit_shift = 0xc,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll3_m3x2_ck = {
.name = "dpll3_m3x2_ck",
.type = TI_CLK_GATE,
.data = &dpll3_m3x2_ck_data,
};
static struct ti_clk_fixed_factor emu_core_alwon_ck_data = {
.parent = "dpll3_m3x2_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk emu_core_alwon_ck = {
.name = "emu_core_alwon_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &emu_core_alwon_ck_data,
};
static struct ti_clk_divider dpll4_m6_ck_data = {
.parent = "dpll4_ck",
.bit_shift = 24,
.max_div = 63,
.reg = 0x1140,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll4_m6_ck = {
.name = "dpll4_m6_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll4_m6_ck_data,
};
static struct ti_clk_fixed_factor dpll4_m6x2_mul_ck_data = {
.parent = "dpll4_m6_ck",
.div = 1,
.mult = 2,
};
static struct ti_clk dpll4_m6x2_mul_ck = {
.name = "dpll4_m6x2_mul_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll4_m6x2_mul_ck_data,
};
static struct ti_clk_gate dpll4_m6x2_ck_data = {
.parent = "dpll4_m6x2_mul_ck",
.bit_shift = 0x1f,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m6x2_ck = {
.name = "dpll4_m6x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m6x2_ck_data,
};
static struct ti_clk_fixed_factor emu_per_alwon_ck_data = {
.parent = "dpll4_m6x2_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk emu_per_alwon_ck = {
.name = "emu_per_alwon_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &emu_per_alwon_ck_data,
};
static struct ti_clk_fixed_factor emu_mpu_alwon_ck_data = {
.parent = "mpu_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk emu_mpu_alwon_ck = {
.name = "emu_mpu_alwon_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &emu_mpu_alwon_ck_data,
};
static const char *emu_src_mux_ck_parents[] = {
"sys_ck",
"emu_core_alwon_ck",
"emu_per_alwon_ck",
"emu_mpu_alwon_ck",
};
static struct ti_clk_mux emu_src_mux_ck_data = {
.num_parents = ARRAY_SIZE(emu_src_mux_ck_parents),
.reg = 0x1140,
.module = TI_CLKM_CM,
.parents = emu_src_mux_ck_parents,
};
static struct ti_clk emu_src_mux_ck = {
.name = "emu_src_mux_ck",
.type = TI_CLK_MUX,
.data = &emu_src_mux_ck_data,
};
static struct ti_clk_gate emu_src_ck_data = {
.parent = "emu_src_mux_ck",
.flags = CLKF_CLKDM,
};
static struct ti_clk emu_src_ck = {
.name = "emu_src_ck",
.clkdm_name = "emu_clkdm",
.type = TI_CLK_GATE,
.data = &emu_src_ck_data,
};
static struct ti_clk_divider atclk_fck_data = {
.parent = "emu_src_ck",
.bit_shift = 4,
.max_div = 3,
.reg = 0x1140,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk atclk_fck = {
.name = "atclk_fck",
.type = TI_CLK_DIVIDER,
.data = &atclk_fck_data,
};
static struct ti_clk_gate ipss_ick_data = {
.parent = "core_l3_ick",
.bit_shift = 4,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_AM35XX | CLKF_INTERFACE,
};
static struct ti_clk ipss_ick = {
.name = "ipss_ick",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &ipss_ick_data,
};
static struct ti_clk_gate emac_ick_data = {
.parent = "ipss_ick",
.bit_shift = 1,
.reg = 0x59c,
.module = TI_CLKM_SCRM,
.flags = CLKF_AM35XX,
};
static struct ti_clk emac_ick = {
.name = "emac_ick",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &emac_ick_data,
};
static struct ti_clk_gate vpfe_ick_data = {
.parent = "ipss_ick",
.bit_shift = 2,
.reg = 0x59c,
.module = TI_CLKM_SCRM,
.flags = CLKF_AM35XX,
};
static struct ti_clk vpfe_ick = {
.name = "vpfe_ick",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &vpfe_ick_data,
};
static const char *dpll2_ck_parents[] = {
"sys_ck",
"dpll2_fck",
};
static struct ti_clk_dpll dpll2_ck_data = {
.num_parents = ARRAY_SIZE(dpll2_ck_parents),
.control_reg = 0x4,
.idlest_reg = 0x24,
.mult_div1_reg = 0x40,
.autoidle_reg = 0x34,
.module = TI_CLKM_CM,
.parents = dpll2_ck_parents,
.freqsel_mask = 0xf0,
.modes = 0xa2,
.div1_mask = 0x7f,
.idlest_mask = 0x1,
.auto_recal_bit = 0x3,
.max_divider = 0x80,
.min_divider = 0x1,
.recal_en_bit = 0x8,
.max_multiplier = 0x7ff,
.enable_mask = 0x7,
.mult_mask = 0x7ff00,
.recal_st_bit = 0x8,
.autoidle_mask = 0x7,
};
static struct ti_clk dpll2_ck = {
.name = "dpll2_ck",
.clkdm_name = "dpll2_clkdm",
.type = TI_CLK_DPLL,
.data = &dpll2_ck_data,
};
static struct ti_clk_divider dpll2_m2_ck_data = {
.parent = "dpll2_ck",
.max_div = 31,
.reg = 0x44,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll2_m2_ck = {
.name = "dpll2_m2_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll2_m2_ck_data,
};
static const char *mcbsp4_mux_fck_parents[] = {
"per_96m_fck",
"mcbsp_clks",
};
static struct ti_clk_mux mcbsp4_mux_fck_data = {
.bit_shift = 2,
.num_parents = ARRAY_SIZE(mcbsp4_mux_fck_parents),
.reg = 0x2d8,
.module = TI_CLKM_SCRM,
.parents = mcbsp4_mux_fck_parents,
};
static const char *mcbsp1_mux_fck_parents[] = {
"core_96m_fck",
"mcbsp_clks",
};
static struct ti_clk_mux mcbsp1_mux_fck_data = {
.bit_shift = 2,
.num_parents = ARRAY_SIZE(mcbsp1_mux_fck_parents),
.reg = 0x274,
.module = TI_CLKM_SCRM,
.parents = mcbsp1_mux_fck_parents,
};
static struct ti_clk_gate gpt8_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 9,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk_gate gpt8_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 9,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt8_ick = {
.name = "gpt8_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpt8_ick_data,
};
static const char *gpt10_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt10_mux_fck_data = {
.bit_shift = 6,
.num_parents = ARRAY_SIZE(gpt10_mux_fck_parents),
.reg = 0xa40,
.module = TI_CLKM_CM,
.parents = gpt10_mux_fck_parents,
};
static struct ti_clk_gate mmchs3_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 30,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mmchs3_ick = {
.name = "mmchs3_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mmchs3_ick_data,
};
static struct ti_clk_gate gpio3_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 14,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpio3_ick = {
.name = "gpio3_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio3_ick_data,
};
static const char *traceclk_src_fck_parents[] = {
"sys_ck",
"emu_core_alwon_ck",
"emu_per_alwon_ck",
"emu_mpu_alwon_ck",
};
static struct ti_clk_mux traceclk_src_fck_data = {
.bit_shift = 2,
.num_parents = ARRAY_SIZE(traceclk_src_fck_parents),
.reg = 0x1140,
.module = TI_CLKM_CM,
.parents = traceclk_src_fck_parents,
};
static struct ti_clk traceclk_src_fck = {
.name = "traceclk_src_fck",
.type = TI_CLK_MUX,
.data = &traceclk_src_fck_data,
};
static struct ti_clk_divider traceclk_fck_data = {
.parent = "traceclk_src_fck",
.bit_shift = 11,
.max_div = 7,
.reg = 0x1140,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk traceclk_fck = {
.name = "traceclk_fck",
.type = TI_CLK_DIVIDER,
.data = &traceclk_fck_data,
};
static struct ti_clk_gate mcbsp5_gate_fck_data = {
.parent = "mcbsp_clks",
.bit_shift = 10,
.reg = 0xa00,
.module = TI_CLKM_CM,
};
static struct ti_clk_gate sad2d_ick_data = {
.parent = "l3_ick",
.bit_shift = 3,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk sad2d_ick = {
.name = "sad2d_ick",
.clkdm_name = "d2d_clkdm",
.type = TI_CLK_GATE,
.data = &sad2d_ick_data,
};
static const char *gpt1_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt1_mux_fck_data = {
.num_parents = ARRAY_SIZE(gpt1_mux_fck_parents),
.reg = 0xc40,
.module = TI_CLKM_CM,
.parents = gpt1_mux_fck_parents,
};
static struct ti_clk_gate hecc_ck_data = {
.parent = "sys_ck",
.bit_shift = 3,
.reg = 0x59c,
.module = TI_CLKM_SCRM,
.flags = CLKF_AM35XX,
};
static struct ti_clk hecc_ck = {
.name = "hecc_ck",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &hecc_ck_data,
};
static struct ti_clk_gate gpt1_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 0,
.reg = 0xc00,
.module = TI_CLKM_CM,
};
static struct ti_clk_composite gpt1_fck_data = {
.mux = &gpt1_mux_fck_data,
.gate = &gpt1_gate_fck_data,
};
static struct ti_clk gpt1_fck = {
.name = "gpt1_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt1_fck_data,
};
static struct ti_clk_gate dpll4_m2x2_ck_omap36xx_data = {
.parent = "dpll4_m2x2_mul_ck",
.bit_shift = 0x1b,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m2x2_ck_omap36xx = {
.name = "dpll4_m2x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m2x2_ck_omap36xx_data,
.patch = &dpll4_m2x2_ck,
};
static struct ti_clk_divider gfx_l3_fck_data = {
.parent = "l3_ick",
.max_div = 7,
.reg = 0xb40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk gfx_l3_fck = {
.name = "gfx_l3_fck",
.type = TI_CLK_DIVIDER,
.data = &gfx_l3_fck_data,
};
static struct ti_clk_gate gfx_cg1_ck_data = {
.parent = "gfx_l3_fck",
.bit_shift = 1,
.reg = 0xb00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk gfx_cg1_ck = {
.name = "gfx_cg1_ck",
.clkdm_name = "gfx_3430es1_clkdm",
.type = TI_CLK_GATE,
.data = &gfx_cg1_ck_data,
};
static struct ti_clk_gate mailboxes_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 7,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mailboxes_ick = {
.name = "mailboxes_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mailboxes_ick_data,
};
static struct ti_clk_gate sha11_ick_data = {
.parent = "security_l4_ick2",
.bit_shift = 1,
.reg = 0xa14,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk sha11_ick = {
.name = "sha11_ick",
.type = TI_CLK_GATE,
.data = &sha11_ick_data,
};
static struct ti_clk_gate hsotgusb_ick_am35xx_data = {
.parent = "ipss_ick",
.bit_shift = 0,
.reg = 0x59c,
.module = TI_CLKM_SCRM,
.flags = CLKF_AM35XX,
};
static struct ti_clk hsotgusb_ick_am35xx = {
.name = "hsotgusb_ick_am35xx",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &hsotgusb_ick_am35xx_data,
};
static struct ti_clk_gate mmchs3_fck_data = {
.parent = "core_96m_fck",
.bit_shift = 30,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk mmchs3_fck = {
.name = "mmchs3_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mmchs3_fck_data,
};
static struct ti_clk_divider pclk_fck_data = {
.parent = "emu_src_ck",
.bit_shift = 8,
.max_div = 7,
.reg = 0x1140,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk pclk_fck = {
.name = "pclk_fck",
.type = TI_CLK_DIVIDER,
.data = &pclk_fck_data,
};
static const char *dpll4_ck_omap36xx_parents[] = {
"sys_ck",
"sys_ck",
};
static struct ti_clk_dpll dpll4_ck_omap36xx_data = {
.num_parents = ARRAY_SIZE(dpll4_ck_omap36xx_parents),
.control_reg = 0xd00,
.idlest_reg = 0xd20,
.mult_div1_reg = 0xd44,
.autoidle_reg = 0xd30,
.module = TI_CLKM_CM,
.parents = dpll4_ck_omap36xx_parents,
.modes = 0x82,
.div1_mask = 0x7f,
.idlest_mask = 0x2,
.auto_recal_bit = 0x13,
.max_divider = 0x80,
.min_divider = 0x1,
.recal_en_bit = 0x6,
.max_multiplier = 0xfff,
.enable_mask = 0x70000,
.mult_mask = 0xfff00,
.recal_st_bit = 0x6,
.autoidle_mask = 0x38,
.sddiv_mask = 0xff000000,
.dco_mask = 0xe00000,
.flags = CLKF_PER | CLKF_J_TYPE,
};
static struct ti_clk dpll4_ck_omap36xx = {
.name = "dpll4_ck",
.type = TI_CLK_DPLL,
.data = &dpll4_ck_omap36xx_data,
.patch = &dpll4_ck,
};
static struct ti_clk_gate uart3_fck_data = {
.parent = "per_48m_fck",
.bit_shift = 11,
.reg = 0x1000,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk uart3_fck = {
.name = "uart3_fck",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &uart3_fck_data,
};
static struct ti_clk_fixed_factor wkup_32k_fck_data = {
.parent = "omap_32k_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk wkup_32k_fck = {
.name = "wkup_32k_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &wkup_32k_fck_data,
};
static struct ti_clk_gate sys_clkout1_data = {
.parent = "osc_sys_ck",
.bit_shift = 7,
.reg = 0xd70,
.module = TI_CLKM_PRM,
};
static struct ti_clk sys_clkout1 = {
.name = "sys_clkout1",
.type = TI_CLK_GATE,
.data = &sys_clkout1_data,
};
static struct ti_clk_fixed_factor gpmc_fck_data = {
.parent = "core_l3_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk gpmc_fck = {
.name = "gpmc_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &gpmc_fck_data,
};
static struct ti_clk_fixed_factor dpll5_m2_d20_ck_data = {
.parent = "dpll5_m2_ck",
.div = 20,
.mult = 1,
};
static struct ti_clk dpll5_m2_d20_ck = {
.name = "dpll5_m2_d20_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll5_m2_d20_ck_data,
};
static struct ti_clk_gate dpll4_m5x2_ck_omap36xx_data = {
.parent = "dpll4_m5x2_mul_ck",
.bit_shift = 0x1e,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_HSDIV | CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m5x2_ck_omap36xx = {
.name = "dpll4_m5x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m5x2_ck_omap36xx_data,
.patch = &dpll4_m5x2_ck,
};
static struct ti_clk_gate ssi_ssr_gate_fck_3430es2_data = {
.parent = "corex2_fck",
.bit_shift = 0,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_NO_WAIT,
};
static struct ti_clk_gate uart1_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 13,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk uart1_ick = {
.name = "uart1_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &uart1_ick_data,
};
static struct ti_clk_gate iva2_ck_data = {
.parent = "dpll2_m2_ck",
.bit_shift = 0,
.reg = 0x0,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk iva2_ck = {
.name = "iva2_ck",
.clkdm_name = "iva2_clkdm",
.type = TI_CLK_GATE,
.data = &iva2_ck_data,
};
static struct ti_clk_gate pka_ick_data = {
.parent = "security_l3_ick",
.bit_shift = 4,
.reg = 0xa14,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk pka_ick = {
.name = "pka_ick",
.type = TI_CLK_GATE,
.data = &pka_ick_data,
};
static struct ti_clk_gate gpt12_ick_data = {
.parent = "wkup_l4_ick",
.bit_shift = 1,
.reg = 0xc10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt12_ick = {
.name = "gpt12_ick",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &gpt12_ick_data,
};
static const char *mcbsp5_mux_fck_parents[] = {
"core_96m_fck",
"mcbsp_clks",
};
static struct ti_clk_mux mcbsp5_mux_fck_data = {
.bit_shift = 4,
.num_parents = ARRAY_SIZE(mcbsp5_mux_fck_parents),
.reg = 0x2d8,
.module = TI_CLKM_SCRM,
.parents = mcbsp5_mux_fck_parents,
};
static struct ti_clk_composite mcbsp5_fck_data = {
.mux = &mcbsp5_mux_fck_data,
.gate = &mcbsp5_gate_fck_data,
};
static struct ti_clk mcbsp5_fck = {
.name = "mcbsp5_fck",
.type = TI_CLK_COMPOSITE,
.data = &mcbsp5_fck_data,
};
static struct ti_clk_gate usbhost_48m_fck_data = {
.parent = "omap_48m_fck",
.bit_shift = 0,
.reg = 0x1400,
.module = TI_CLKM_CM,
.flags = CLKF_DSS,
};
static struct ti_clk usbhost_48m_fck = {
.name = "usbhost_48m_fck",
.clkdm_name = "usbhost_clkdm",
.type = TI_CLK_GATE,
.data = &usbhost_48m_fck_data,
};
static struct ti_clk_gate des1_ick_data = {
.parent = "security_l4_ick2",
.bit_shift = 0,
.reg = 0xa14,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk des1_ick = {
.name = "des1_ick",
.type = TI_CLK_GATE,
.data = &des1_ick_data,
};
static struct ti_clk_gate sgx_gate_fck_data = {
.parent = "core_ck",
.bit_shift = 1,
.reg = 0xb00,
.module = TI_CLKM_CM,
};
static struct ti_clk_fixed_factor core_d4_ck_data = {
.parent = "core_ck",
.div = 4,
.mult = 1,
};
static struct ti_clk core_d4_ck = {
.name = "core_d4_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_d4_ck_data,
};
static struct ti_clk_fixed_factor omap_192m_alwon_fck_data = {
.parent = "dpll4_m2x2_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk omap_192m_alwon_fck = {
.name = "omap_192m_alwon_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &omap_192m_alwon_fck_data,
};
static struct ti_clk_fixed_factor core_d2_ck_data = {
.parent = "core_ck",
.div = 2,
.mult = 1,
};
static struct ti_clk core_d2_ck = {
.name = "core_d2_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_d2_ck_data,
};
static struct ti_clk_fixed_factor corex2_d3_fck_data = {
.parent = "corex2_fck",
.div = 3,
.mult = 1,
};
static struct ti_clk corex2_d3_fck = {
.name = "corex2_d3_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &corex2_d3_fck_data,
};
static struct ti_clk_fixed_factor corex2_d5_fck_data = {
.parent = "corex2_fck",
.div = 5,
.mult = 1,
};
static struct ti_clk corex2_d5_fck = {
.name = "corex2_d5_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &corex2_d5_fck_data,
};
static const char *sgx_mux_fck_parents[] = {
"core_d3_ck",
"core_d4_ck",
"core_d6_ck",
"cm_96m_fck",
"omap_192m_alwon_fck",
"core_d2_ck",
"corex2_d3_fck",
"corex2_d5_fck",
};
static struct ti_clk_mux sgx_mux_fck_data = {
.num_parents = ARRAY_SIZE(sgx_mux_fck_parents),
.reg = 0xb40,
.module = TI_CLKM_CM,
.parents = sgx_mux_fck_parents,
};
static struct ti_clk_composite sgx_fck_data = {
.mux = &sgx_mux_fck_data,
.gate = &sgx_gate_fck_data,
};
static struct ti_clk sgx_fck = {
.name = "sgx_fck",
.type = TI_CLK_COMPOSITE,
.data = &sgx_fck_data,
};
static struct ti_clk_gate mcspi1_fck_data = {
.parent = "core_48m_fck",
.bit_shift = 18,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk mcspi1_fck = {
.name = "mcspi1_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mcspi1_fck_data,
};
static struct ti_clk_gate mmchs2_fck_data = {
.parent = "core_96m_fck",
.bit_shift = 25,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk mmchs2_fck = {
.name = "mmchs2_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mmchs2_fck_data,
};
static struct ti_clk_gate mcspi2_fck_data = {
.parent = "core_48m_fck",
.bit_shift = 19,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk mcspi2_fck = {
.name = "mcspi2_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mcspi2_fck_data,
};
static struct ti_clk_gate vpfe_fck_data = {
.parent = "pclk_ck",
.bit_shift = 10,
.reg = 0x59c,
.module = TI_CLKM_SCRM,
};
static struct ti_clk vpfe_fck = {
.name = "vpfe_fck",
.type = TI_CLK_GATE,
.data = &vpfe_fck_data,
};
static struct ti_clk_gate gpt4_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 5,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk_gate mcbsp1_gate_fck_data = {
.parent = "mcbsp_clks",
.bit_shift = 9,
.reg = 0xa00,
.module = TI_CLKM_CM,
};
static struct ti_clk_gate gpt5_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 6,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static const char *gpt5_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt5_mux_fck_data = {
.bit_shift = 3,
.num_parents = ARRAY_SIZE(gpt5_mux_fck_parents),
.reg = 0x1040,
.module = TI_CLKM_CM,
.parents = gpt5_mux_fck_parents,
};
static struct ti_clk_composite gpt5_fck_data = {
.mux = &gpt5_mux_fck_data,
.gate = &gpt5_gate_fck_data,
};
static struct ti_clk gpt5_fck = {
.name = "gpt5_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt5_fck_data,
};
static struct ti_clk_gate ts_fck_data = {
.parent = "omap_32k_fck",
.bit_shift = 1,
.reg = 0xa08,
.module = TI_CLKM_CM,
};
static struct ti_clk ts_fck = {
.name = "ts_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &ts_fck_data,
};
static struct ti_clk_fixed_factor wdt1_fck_data = {
.parent = "secure_32k_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk wdt1_fck = {
.name = "wdt1_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &wdt1_fck_data,
};
static struct ti_clk_gate dpll4_m6x2_ck_omap36xx_data = {
.parent = "dpll4_m6x2_mul_ck",
.bit_shift = 0x1f,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m6x2_ck_omap36xx = {
.name = "dpll4_m6x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m6x2_ck_omap36xx_data,
.patch = &dpll4_m6x2_ck,
};
static const char *gpt4_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt4_mux_fck_data = {
.bit_shift = 2,
.num_parents = ARRAY_SIZE(gpt4_mux_fck_parents),
.reg = 0x1040,
.module = TI_CLKM_CM,
.parents = gpt4_mux_fck_parents,
};
static struct ti_clk_gate usbhost_ick_data = {
.parent = "l4_ick",
.bit_shift = 0,
.reg = 0x1410,
.module = TI_CLKM_CM,
.flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk usbhost_ick = {
.name = "usbhost_ick",
.clkdm_name = "usbhost_clkdm",
.type = TI_CLK_GATE,
.data = &usbhost_ick_data,
};
static struct ti_clk_gate mcbsp2_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 0,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mcbsp2_ick = {
.name = "mcbsp2_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &mcbsp2_ick_data,
};
static struct ti_clk_gate omapctrl_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 6,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk omapctrl_ick = {
.name = "omapctrl_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &omapctrl_ick_data,
};
static struct ti_clk_fixed_factor omap_96m_d4_fck_data = {
.parent = "omap_96m_fck",
.div = 4,
.mult = 1,
};
static struct ti_clk omap_96m_d4_fck = {
.name = "omap_96m_d4_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &omap_96m_d4_fck_data,
};
static struct ti_clk_gate gpt6_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 7,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt6_ick = {
.name = "gpt6_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpt6_ick_data,
};
static struct ti_clk_gate dpll3_m3x2_ck_omap36xx_data = {
.parent = "dpll3_m3x2_mul_ck",
.bit_shift = 0xc,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll3_m3x2_ck_omap36xx = {
.name = "dpll3_m3x2_ck",
.type = TI_CLK_GATE,
.data = &dpll3_m3x2_ck_omap36xx_data,
.patch = &dpll3_m3x2_ck,
};
static struct ti_clk_gate i2c3_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 17,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk i2c3_ick = {
.name = "i2c3_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &i2c3_ick_data,
};
static struct ti_clk_gate gpio6_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 17,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpio6_ick = {
.name = "gpio6_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio6_ick_data,
};
static struct ti_clk_gate mspro_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 23,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mspro_ick = {
.name = "mspro_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mspro_ick_data,
};
static struct ti_clk_composite mcbsp1_fck_data = {
.mux = &mcbsp1_mux_fck_data,
.gate = &mcbsp1_gate_fck_data,
};
static struct ti_clk mcbsp1_fck = {
.name = "mcbsp1_fck",
.type = TI_CLK_COMPOSITE,
.data = &mcbsp1_fck_data,
};
static struct ti_clk_gate gpt3_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 4,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk_fixed rmii_ck_data = {
.frequency = 50000000,
};
static struct ti_clk rmii_ck = {
.name = "rmii_ck",
.type = TI_CLK_FIXED,
.data = &rmii_ck_data,
};
static struct ti_clk_gate gpt6_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 7,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk_composite gpt6_fck_data = {
.mux = &gpt6_mux_fck_data,
.gate = &gpt6_gate_fck_data,
};
static struct ti_clk gpt6_fck = {
.name = "gpt6_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt6_fck_data,
};
static struct ti_clk_fixed_factor dpll5_m2_d4_ck_data = {
.parent = "dpll5_m2_ck",
.div = 4,
.mult = 1,
};
static struct ti_clk dpll5_m2_d4_ck = {
.name = "dpll5_m2_d4_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll5_m2_d4_ck_data,
};
static struct ti_clk_fixed_factor sys_d2_ck_data = {
.parent = "sys_ck",
.div = 2,
.mult = 1,
};
static struct ti_clk sys_d2_ck = {
.name = "sys_d2_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &sys_d2_ck_data,
};
static struct ti_clk_fixed_factor omap_96m_d2_fck_data = {
.parent = "omap_96m_fck",
.div = 2,
.mult = 1,
};
static struct ti_clk omap_96m_d2_fck = {
.name = "omap_96m_d2_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &omap_96m_d2_fck_data,
};
static struct ti_clk_fixed_factor dpll5_m2_d8_ck_data = {
.parent = "dpll5_m2_ck",
.div = 8,
.mult = 1,
};
static struct ti_clk dpll5_m2_d8_ck = {
.name = "dpll5_m2_d8_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll5_m2_d8_ck_data,
};
static struct ti_clk_fixed_factor dpll5_m2_d16_ck_data = {
.parent = "dpll5_m2_ck",
.div = 16,
.mult = 1,
};
static struct ti_clk dpll5_m2_d16_ck = {
.name = "dpll5_m2_d16_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll5_m2_d16_ck_data,
};
static const char *usim_mux_fck_parents[] = {
"sys_ck",
"sys_d2_ck",
"omap_96m_d2_fck",
"omap_96m_d4_fck",
"omap_96m_d8_fck",
"omap_96m_d10_fck",
"dpll5_m2_d4_ck",
"dpll5_m2_d8_ck",
"dpll5_m2_d16_ck",
"dpll5_m2_d20_ck",
};
static struct ti_clk_mux usim_mux_fck_data = {
.bit_shift = 3,
.num_parents = ARRAY_SIZE(usim_mux_fck_parents),
.reg = 0xc40,
.module = TI_CLKM_CM,
.parents = usim_mux_fck_parents,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk_composite usim_fck_data = {
.mux = &usim_mux_fck_data,
.gate = &usim_gate_fck_data,
};
static struct ti_clk usim_fck = {
.name = "usim_fck",
.type = TI_CLK_COMPOSITE,
.data = &usim_fck_data,
};
static int ssi_ssr_div_fck_3430es2_divs[] = {
0,
1,
2,
3,
4,
0,
6,
0,
8,
};
static struct ti_clk_divider ssi_ssr_div_fck_3430es2_data = {
.num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es2_divs),
.parent = "corex2_fck",
.bit_shift = 8,
.dividers = ssi_ssr_div_fck_3430es2_divs,
.reg = 0xa40,
.module = TI_CLKM_CM,
};
static struct ti_clk_composite ssi_ssr_fck_3430es2_data = {
.gate = &ssi_ssr_gate_fck_3430es2_data,
.divider = &ssi_ssr_div_fck_3430es2_data,
};
static struct ti_clk ssi_ssr_fck_3430es2 = {
.name = "ssi_ssr_fck",
.type = TI_CLK_COMPOSITE,
.data = &ssi_ssr_fck_3430es2_data,
};
static struct ti_clk_gate dss1_alwon_fck_3430es1_data = {
.parent = "dpll4_m4x2_ck",
.bit_shift = 0,
.reg = 0xe00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_RATE_PARENT,
};
static struct ti_clk dss1_alwon_fck_3430es1 = {
.name = "dss1_alwon_fck",
.clkdm_name = "dss_clkdm",
.type = TI_CLK_GATE,
.data = &dss1_alwon_fck_3430es1_data,
};
static struct ti_clk_gate gpt3_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 4,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt3_ick = {
.name = "gpt3_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpt3_ick_data,
};
static struct ti_clk_fixed_factor omap_12m_fck_data = {
.parent = "omap_48m_fck",
.div = 4,
.mult = 1,
};
static struct ti_clk omap_12m_fck = {
.name = "omap_12m_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &omap_12m_fck_data,
};
static struct ti_clk_fixed_factor core_12m_fck_data = {
.parent = "omap_12m_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk core_12m_fck = {
.name = "core_12m_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_12m_fck_data,
};
static struct ti_clk_gate hdq_fck_data = {
.parent = "core_12m_fck",
.bit_shift = 22,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk hdq_fck = {
.name = "hdq_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &hdq_fck_data,
};
static struct ti_clk_gate usbtll_fck_data = {
.parent = "dpll5_m2_ck",
.bit_shift = 2,
.reg = 0xa08,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk usbtll_fck = {
.name = "usbtll_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &usbtll_fck_data,
};
static struct ti_clk_gate hsotgusb_fck_am35xx_data = {
.parent = "sys_ck",
.bit_shift = 8,
.reg = 0x59c,
.module = TI_CLKM_SCRM,
};
static struct ti_clk hsotgusb_fck_am35xx = {
.name = "hsotgusb_fck_am35xx",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &hsotgusb_fck_am35xx_data,
};
static struct ti_clk_gate hsotgusb_ick_3430es2_data = {
.parent = "core_l3_ick",
.bit_shift = 4,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_HSOTGUSB | CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk hsotgusb_ick_3430es2 = {
.name = "hsotgusb_ick_3430es2",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &hsotgusb_ick_3430es2_data,
};
static struct ti_clk_gate gfx_l3_ck_data = {
.parent = "l3_ick",
.bit_shift = 0,
.reg = 0xb10,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk gfx_l3_ck = {
.name = "gfx_l3_ck",
.clkdm_name = "gfx_3430es1_clkdm",
.type = TI_CLK_GATE,
.data = &gfx_l3_ck_data,
};
static struct ti_clk_fixed_factor gfx_l3_ick_data = {
.parent = "gfx_l3_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk gfx_l3_ick = {
.name = "gfx_l3_ick",
.type = TI_CLK_FIXED_FACTOR,
.data = &gfx_l3_ick_data,
};
static struct ti_clk_gate mcbsp1_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 9,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mcbsp1_ick = {
.name = "mcbsp1_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mcbsp1_ick_data,
};
static struct ti_clk_fixed_factor gpt12_fck_data = {
.parent = "secure_32k_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk gpt12_fck = {
.name = "gpt12_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &gpt12_fck_data,
};
static struct ti_clk_gate gfx_cg2_ck_data = {
.parent = "gfx_l3_fck",
.bit_shift = 2,
.reg = 0xb00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk gfx_cg2_ck = {
.name = "gfx_cg2_ck",
.clkdm_name = "gfx_3430es1_clkdm",
.type = TI_CLK_GATE,
.data = &gfx_cg2_ck_data,
};
static struct ti_clk_gate i2c2_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 16,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk i2c2_ick = {
.name = "i2c2_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &i2c2_ick_data,
};
static struct ti_clk_gate gpio4_dbck_data = {
.parent = "per_32k_alwon_fck",
.bit_shift = 15,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk gpio4_dbck = {
.name = "gpio4_dbck",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio4_dbck_data,
};
static struct ti_clk_gate i2c3_fck_data = {
.parent = "core_96m_fck",
.bit_shift = 17,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk i2c3_fck = {
.name = "i2c3_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &i2c3_fck_data,
};
static struct ti_clk_composite gpt3_fck_data = {
.mux = &gpt3_mux_fck_data,
.gate = &gpt3_gate_fck_data,
};
static struct ti_clk gpt3_fck = {
.name = "gpt3_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt3_fck_data,
};
static struct ti_clk_gate i2c1_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 15,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk i2c1_ick = {
.name = "i2c1_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &i2c1_ick_data,
};
static struct ti_clk_gate omap_32ksync_ick_data = {
.parent = "wkup_l4_ick",
.bit_shift = 2,
.reg = 0xc10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk omap_32ksync_ick = {
.name = "omap_32ksync_ick",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &omap_32ksync_ick_data,
};
static struct ti_clk_gate aes2_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 28,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk aes2_ick = {
.name = "aes2_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &aes2_ick_data,
};
static const char *gpt8_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt8_mux_fck_data = {
.bit_shift = 6,
.num_parents = ARRAY_SIZE(gpt8_mux_fck_parents),
.reg = 0x1040,
.module = TI_CLKM_CM,
.parents = gpt8_mux_fck_parents,
};
static struct ti_clk_composite gpt8_fck_data = {
.mux = &gpt8_mux_fck_data,
.gate = &gpt8_gate_fck_data,
};
static struct ti_clk gpt8_fck = {
.name = "gpt8_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt8_fck_data,
};
static struct ti_clk_gate mcbsp4_gate_fck_data = {
.parent = "mcbsp_clks",
.bit_shift = 2,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk_composite mcbsp4_fck_data = {
.mux = &mcbsp4_mux_fck_data,
.gate = &mcbsp4_gate_fck_data,
};
static struct ti_clk mcbsp4_fck = {
.name = "mcbsp4_fck",
.type = TI_CLK_COMPOSITE,
.data = &mcbsp4_fck_data,
};
static struct ti_clk_gate gpio2_dbck_data = {
.parent = "per_32k_alwon_fck",
.bit_shift = 13,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk gpio2_dbck = {
.name = "gpio2_dbck",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio2_dbck_data,
};
static struct ti_clk_gate usbtll_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 2,
.reg = 0xa18,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk usbtll_ick = {
.name = "usbtll_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &usbtll_ick_data,
};
static struct ti_clk_gate mcspi4_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 21,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mcspi4_ick = {
.name = "mcspi4_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mcspi4_ick_data,
};
static struct ti_clk_gate dss_96m_fck_data = {
.parent = "omap_96m_fck",
.bit_shift = 2,
.reg = 0xe00,
.module = TI_CLKM_CM,
};
static struct ti_clk dss_96m_fck = {
.name = "dss_96m_fck",
.clkdm_name = "dss_clkdm",
.type = TI_CLK_GATE,
.data = &dss_96m_fck_data,
};
static struct ti_clk_divider rm_ick_data = {
.parent = "l4_ick",
.bit_shift = 1,
.max_div = 3,
.reg = 0xc40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk rm_ick = {
.name = "rm_ick",
.type = TI_CLK_DIVIDER,
.data = &rm_ick_data,
};
static struct ti_clk_gate hdq_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 22,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk hdq_ick = {
.name = "hdq_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &hdq_ick_data,
};
static struct ti_clk_fixed_factor dpll3_x2_ck_data = {
.parent = "dpll3_ck",
.div = 1,
.mult = 2,
};
static struct ti_clk dpll3_x2_ck = {
.name = "dpll3_x2_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll3_x2_ck_data,
};
static struct ti_clk_gate mad2d_ick_data = {
.parent = "l3_ick",
.bit_shift = 3,
.reg = 0xa18,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mad2d_ick = {
.name = "mad2d_ick",
.clkdm_name = "d2d_clkdm",
.type = TI_CLK_GATE,
.data = &mad2d_ick_data,
};
static struct ti_clk_gate fshostusb_fck_data = {
.parent = "core_48m_fck",
.bit_shift = 5,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk fshostusb_fck = {
.name = "fshostusb_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &fshostusb_fck_data,
};
static struct ti_clk_gate sr1_fck_data = {
.parent = "sys_ck",
.bit_shift = 6,
.reg = 0xc00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk sr1_fck = {
.name = "sr1_fck",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &sr1_fck_data,
};
static struct ti_clk_gate des2_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 26,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk des2_ick = {
.name = "des2_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &des2_ick_data,
};
static struct ti_clk_gate sdrc_ick_data = {
.parent = "core_l3_ick",
.bit_shift = 1,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk sdrc_ick = {
.name = "sdrc_ick",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &sdrc_ick_data,
};
static struct ti_clk_composite gpt4_fck_data = {
.mux = &gpt4_mux_fck_data,
.gate = &gpt4_gate_fck_data,
};
static struct ti_clk gpt4_fck = {
.name = "gpt4_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt4_fck_data,
};
static struct ti_clk_gate dpll4_m3x2_ck_omap36xx_data = {
.parent = "dpll4_m3x2_mul_ck",
.bit_shift = 0x1c,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m3x2_ck_omap36xx = {
.name = "dpll4_m3x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m3x2_ck_omap36xx_data,
.patch = &dpll4_m3x2_ck,
};
static struct ti_clk_gate cpefuse_fck_data = {
.parent = "sys_ck",
.bit_shift = 0,
.reg = 0xa08,
.module = TI_CLKM_CM,
};
static struct ti_clk cpefuse_fck = {
.name = "cpefuse_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &cpefuse_fck_data,
};
static struct ti_clk_gate mcspi3_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 20,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mcspi3_ick = {
.name = "mcspi3_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mcspi3_ick_data,
};
static struct ti_clk_fixed_factor ssi_sst_fck_3430es2_data = {
.parent = "ssi_ssr_fck",
.div = 2,
.mult = 1,
};
static struct ti_clk ssi_sst_fck_3430es2 = {
.name = "ssi_sst_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &ssi_sst_fck_3430es2_data,
};
static struct ti_clk_gate gpio1_dbck_data = {
.parent = "wkup_32k_fck",
.bit_shift = 3,
.reg = 0xc00,
.module = TI_CLKM_CM,
};
static struct ti_clk gpio1_dbck = {
.name = "gpio1_dbck",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &gpio1_dbck_data,
};
static struct ti_clk_gate gpt4_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 5,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt4_ick = {
.name = "gpt4_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpt4_ick_data,
};
static struct ti_clk_gate gpt2_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 3,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt2_ick = {
.name = "gpt2_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpt2_ick_data,
};
static struct ti_clk_gate mmchs1_fck_data = {
.parent = "core_96m_fck",
.bit_shift = 24,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk mmchs1_fck = {
.name = "mmchs1_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mmchs1_fck_data,
};
static struct ti_clk_fixed dummy_apb_pclk_data = {
.frequency = 0x0,
};
static struct ti_clk dummy_apb_pclk = {
.name = "dummy_apb_pclk",
.type = TI_CLK_FIXED,
.data = &dummy_apb_pclk_data,
};
static struct ti_clk_gate gpio6_dbck_data = {
.parent = "per_32k_alwon_fck",
.bit_shift = 17,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk gpio6_dbck = {
.name = "gpio6_dbck",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio6_dbck_data,
};
static struct ti_clk_gate uart2_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 14,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk uart2_ick = {
.name = "uart2_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &uart2_ick_data,
};
static struct ti_clk_fixed_factor dpll4_x2_ck_data = {
.parent = "dpll4_ck",
.div = 1,
.mult = 2,
};
static struct ti_clk dpll4_x2_ck = {
.name = "dpll4_x2_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll4_x2_ck_data,
};
static struct ti_clk_gate gpt7_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 8,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt7_ick = {
.name = "gpt7_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpt7_ick_data,
};
static struct ti_clk_gate dss_tv_fck_data = {
.parent = "omap_54m_fck",
.bit_shift = 2,
.reg = 0xe00,
.module = TI_CLKM_CM,
};
static struct ti_clk dss_tv_fck = {
.name = "dss_tv_fck",
.clkdm_name = "dss_clkdm",
.type = TI_CLK_GATE,
.data = &dss_tv_fck_data,
};
static struct ti_clk_gate mcbsp5_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 10,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mcbsp5_ick = {
.name = "mcbsp5_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mcbsp5_ick_data,
};
static struct ti_clk_gate mcspi1_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 18,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mcspi1_ick = {
.name = "mcspi1_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mcspi1_ick_data,
};
static struct ti_clk_gate d2d_26m_fck_data = {
.parent = "sys_ck",
.bit_shift = 3,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk d2d_26m_fck = {
.name = "d2d_26m_fck",
.clkdm_name = "d2d_clkdm",
.type = TI_CLK_GATE,
.data = &d2d_26m_fck_data,
};
static struct ti_clk_gate wdt3_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 12,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk wdt3_ick = {
.name = "wdt3_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &wdt3_ick_data,
};
static struct ti_clk_divider pclkx2_fck_data = {
.parent = "emu_src_ck",
.bit_shift = 6,
.max_div = 3,
.reg = 0x1140,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk pclkx2_fck = {
.name = "pclkx2_fck",
.type = TI_CLK_DIVIDER,
.data = &pclkx2_fck_data,
};
static struct ti_clk_gate sha12_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 27,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk sha12_ick = {
.name = "sha12_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &sha12_ick_data,
};
static struct ti_clk_gate emac_fck_data = {
.parent = "rmii_ck",
.bit_shift = 9,
.reg = 0x59c,
.module = TI_CLKM_SCRM,
};
static struct ti_clk emac_fck = {
.name = "emac_fck",
.type = TI_CLK_GATE,
.data = &emac_fck_data,
};
static struct ti_clk_composite gpt10_fck_data = {
.mux = &gpt10_mux_fck_data,
.gate = &gpt10_gate_fck_data,
};
static struct ti_clk gpt10_fck = {
.name = "gpt10_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt10_fck_data,
};
static struct ti_clk_gate wdt2_fck_data = {
.parent = "wkup_32k_fck",
.bit_shift = 5,
.reg = 0xc00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk wdt2_fck = {
.name = "wdt2_fck",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &wdt2_fck_data,
};
static struct ti_clk_gate cam_ick_data = {
.parent = "l4_ick",
.bit_shift = 0,
.reg = 0xf10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
};
static struct ti_clk cam_ick = {
.name = "cam_ick",
.clkdm_name = "cam_clkdm",
.type = TI_CLK_GATE,
.data = &cam_ick_data,
};
static struct ti_clk_gate ssi_ick_3430es2_data = {
.parent = "ssi_l4_ick",
.bit_shift = 0,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_SSI | CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk ssi_ick_3430es2 = {
.name = "ssi_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &ssi_ick_3430es2_data,
};
static struct ti_clk_gate gpio4_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 15,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpio4_ick = {
.name = "gpio4_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio4_ick_data,
};
static struct ti_clk_gate wdt1_ick_data = {
.parent = "wkup_l4_ick",
.bit_shift = 4,
.reg = 0xc10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk wdt1_ick = {
.name = "wdt1_ick",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &wdt1_ick_data,
};
static struct ti_clk_gate rng_ick_data = {
.parent = "security_l4_ick2",
.bit_shift = 2,
.reg = 0xa14,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk rng_ick = {
.name = "rng_ick",
.type = TI_CLK_GATE,
.data = &rng_ick_data,
};
static struct ti_clk_gate icr_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 29,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk icr_ick = {
.name = "icr_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &icr_ick_data,
};
static struct ti_clk_gate sgx_ick_data = {
.parent = "l3_ick",
.bit_shift = 0,
.reg = 0xb10,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk sgx_ick = {
.name = "sgx_ick",
.clkdm_name = "sgx_clkdm",
.type = TI_CLK_GATE,
.data = &sgx_ick_data,
};
static struct ti_clk_divider sys_clkout2_data = {
.parent = "clkout2_src_ck",
.bit_shift = 3,
.max_div = 64,
.reg = 0xd70,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_POWER_OF_TWO,
};
static struct ti_clk sys_clkout2 = {
.name = "sys_clkout2",
.type = TI_CLK_DIVIDER,
.data = &sys_clkout2_data,
};
static struct ti_clk_alias omap34xx_omap36xx_clks[] = {
CLK(NULL, "security_l4_ick2", &security_l4_ick2),
CLK(NULL, "aes1_ick", &aes1_ick),
CLK("omap_rng", "ick", &rng_ick),
CLK("omap3-rom-rng", "ick", &rng_ick),
CLK(NULL, "sha11_ick", &sha11_ick),
CLK(NULL, "des1_ick", &des1_ick),
CLK(NULL, "cam_mclk", &cam_mclk),
CLK(NULL, "cam_ick", &cam_ick),
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
CLK(NULL, "security_l3_ick", &security_l3_ick),
CLK(NULL, "pka_ick", &pka_ick),
CLK(NULL, "icr_ick", &icr_ick),
CLK(NULL, "des2_ick", &des2_ick),
CLK(NULL, "mspro_ick", &mspro_ick),
CLK(NULL, "mailboxes_ick", &mailboxes_ick),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
CLK(NULL, "sr1_fck", &sr1_fck),
CLK(NULL, "sr2_fck", &sr2_fck),
CLK(NULL, "sr_l4_ick", &sr_l4_ick),
CLK(NULL, "dpll2_fck", &dpll2_fck),
CLK(NULL, "dpll2_ck", &dpll2_ck),
CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
CLK(NULL, "iva2_ck", &iva2_ck),
CLK(NULL, "modem_fck", &modem_fck),
CLK(NULL, "sad2d_ick", &sad2d_ick),
CLK(NULL, "mad2d_ick", &mad2d_ick),
CLK(NULL, "mspro_fck", &mspro_fck),
{ NULL },
};
static struct ti_clk_alias omap36xx_omap3430es2plus_clks[] = {
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
CLK(NULL, "sys_d2_ck", &sys_d2_ck),
CLK(NULL, "omap_96m_d2_fck", &omap_96m_d2_fck),
CLK(NULL, "omap_96m_d4_fck", &omap_96m_d4_fck),
CLK(NULL, "omap_96m_d8_fck", &omap_96m_d8_fck),
CLK(NULL, "omap_96m_d10_fck", &omap_96m_d10_fck),
CLK(NULL, "dpll5_m2_d4_ck", &dpll5_m2_d4_ck),
CLK(NULL, "dpll5_m2_d8_ck", &dpll5_m2_d8_ck),
CLK(NULL, "dpll5_m2_d16_ck", &dpll5_m2_d16_ck),
CLK(NULL, "dpll5_m2_d20_ck", &dpll5_m2_d20_ck),
CLK(NULL, "usim_fck", &usim_fck),
CLK(NULL, "usim_ick", &usim_ick),
{ NULL },
};
static struct ti_clk_alias omap3xxx_clks[] = {
CLK(NULL, "apb_pclk", &dummy_apb_pclk),
CLK(NULL, "omap_32k_fck", &omap_32k_fck),
CLK(NULL, "virt_12m_ck", &virt_12m_ck),
CLK(NULL, "virt_13m_ck", &virt_13m_ck),
CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
CLK(NULL, "osc_sys_ck", &osc_sys_ck),
CLK("twl", "fck", &osc_sys_ck),
CLK(NULL, "sys_ck", &sys_ck),
CLK(NULL, "timer_sys_ck", &sys_ck),
CLK(NULL, "dpll4_ck", &dpll4_ck),
CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
CLK(NULL, "dpll4_m2x2_mul_ck", &dpll4_m2x2_mul_ck),
CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
CLK(NULL, "dpll3_ck", &dpll3_ck),
CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
CLK(NULL, "dpll3_m3x2_mul_ck", &dpll3_m3x2_mul_ck),
CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
CLK(NULL, "sys_altclk", &sys_altclk),
CLK(NULL, "mcbsp_clks", &mcbsp_clks),
CLK(NULL, "sys_clkout1", &sys_clkout1),
CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
CLK(NULL, "core_ck", &core_ck),
CLK(NULL, "dpll1_fck", &dpll1_fck),
CLK(NULL, "dpll1_ck", &dpll1_ck),
CLK(NULL, "cpufreq_ck", &dpll1_ck),
CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
CLK(NULL, "cm_96m_fck", &cm_96m_fck),
CLK(NULL, "omap_96m_fck", &omap_96m_fck),
CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
CLK(NULL, "dpll4_m3x2_mul_ck", &dpll4_m3x2_mul_ck),
CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
CLK(NULL, "omap_54m_fck", &omap_54m_fck),
CLK(NULL, "cm_96m_d2_fck", &cm_96m_d2_fck),
CLK(NULL, "omap_48m_fck", &omap_48m_fck),
CLK(NULL, "omap_12m_fck", &omap_12m_fck),
CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
CLK(NULL, "dpll4_m4x2_mul_ck", &dpll4_m4x2_mul_ck),
CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
CLK(NULL, "dpll4_m5x2_mul_ck", &dpll4_m5x2_mul_ck),
CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
CLK(NULL, "dpll4_m6x2_mul_ck", &dpll4_m6x2_mul_ck),
CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
CLK(NULL, "sys_clkout2", &sys_clkout2),
CLK(NULL, "corex2_fck", &corex2_fck),
CLK(NULL, "mpu_ck", &mpu_ck),
CLK(NULL, "arm_fck", &arm_fck),
CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
CLK(NULL, "l3_ick", &l3_ick),
CLK(NULL, "l4_ick", &l4_ick),
CLK(NULL, "rm_ick", &rm_ick),
CLK(NULL, "timer_32k_ck", &omap_32k_fck),
CLK(NULL, "gpt10_fck", &gpt10_fck),
CLK(NULL, "gpt11_fck", &gpt11_fck),
CLK(NULL, "core_96m_fck", &core_96m_fck),
CLK(NULL, "mmchs2_fck", &mmchs2_fck),
CLK(NULL, "mmchs1_fck", &mmchs1_fck),
CLK(NULL, "i2c3_fck", &i2c3_fck),
CLK(NULL, "i2c2_fck", &i2c2_fck),
CLK(NULL, "i2c1_fck", &i2c1_fck),
CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
CLK(NULL, "core_48m_fck", &core_48m_fck),
CLK(NULL, "mcspi4_fck", &mcspi4_fck),
CLK(NULL, "mcspi3_fck", &mcspi3_fck),
CLK(NULL, "mcspi2_fck", &mcspi2_fck),
CLK(NULL, "mcspi1_fck", &mcspi1_fck),
CLK(NULL, "uart2_fck", &uart2_fck),
CLK(NULL, "uart1_fck", &uart1_fck),
CLK(NULL, "core_12m_fck", &core_12m_fck),
CLK("omap_hdq.0", "fck", &hdq_fck),
CLK(NULL, "hdq_fck", &hdq_fck),
CLK(NULL, "core_l3_ick", &core_l3_ick),
CLK(NULL, "sdrc_ick", &sdrc_ick),
CLK(NULL, "gpmc_fck", &gpmc_fck),
CLK(NULL, "core_l4_ick", &core_l4_ick),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
CLK(NULL, "mmchs2_ick", &mmchs2_ick),
CLK(NULL, "mmchs1_ick", &mmchs1_ick),
CLK("omap_hdq.0", "ick", &hdq_ick),
CLK(NULL, "hdq_ick", &hdq_ick),
CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
CLK(NULL, "mcspi4_ick", &mcspi4_ick),
CLK(NULL, "mcspi3_ick", &mcspi3_ick),
CLK(NULL, "mcspi2_ick", &mcspi2_ick),
CLK(NULL, "mcspi1_ick", &mcspi1_ick),
CLK("omap_i2c.3", "ick", &i2c3_ick),
CLK("omap_i2c.2", "ick", &i2c2_ick),
CLK("omap_i2c.1", "ick", &i2c1_ick),
CLK(NULL, "i2c3_ick", &i2c3_ick),
CLK(NULL, "i2c2_ick", &i2c2_ick),
CLK(NULL, "i2c1_ick", &i2c1_ick),
CLK(NULL, "uart2_ick", &uart2_ick),
CLK(NULL, "uart1_ick", &uart1_ick),
CLK(NULL, "gpt11_ick", &gpt11_ick),
CLK(NULL, "gpt10_ick", &gpt10_ick),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
CLK(NULL, "omapctrl_ick", &omapctrl_ick),
CLK(NULL, "dss_tv_fck", &dss_tv_fck),
CLK(NULL, "dss_96m_fck", &dss_96m_fck),
CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
CLK(NULL, "init_60m_fclk", &dummy_ck),
CLK(NULL, "gpt1_fck", &gpt1_fck),
CLK(NULL, "aes2_ick", &aes2_ick),
CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
CLK(NULL, "gpio1_dbck", &gpio1_dbck),
CLK(NULL, "sha12_ick", &sha12_ick),
CLK(NULL, "wdt2_fck", &wdt2_fck),
CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
CLK("omap_wdt", "ick", &wdt2_ick),
CLK(NULL, "wdt2_ick", &wdt2_ick),
CLK(NULL, "wdt1_ick", &wdt1_ick),
CLK(NULL, "gpio1_ick", &gpio1_ick),
CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
CLK(NULL, "gpt12_ick", &gpt12_ick),
CLK(NULL, "gpt1_ick", &gpt1_ick),
CLK(NULL, "per_96m_fck", &per_96m_fck),
CLK(NULL, "per_48m_fck", &per_48m_fck),
CLK(NULL, "uart3_fck", &uart3_fck),
CLK(NULL, "gpt2_fck", &gpt2_fck),
CLK(NULL, "gpt3_fck", &gpt3_fck),
CLK(NULL, "gpt4_fck", &gpt4_fck),
CLK(NULL, "gpt5_fck", &gpt5_fck),
CLK(NULL, "gpt6_fck", &gpt6_fck),
CLK(NULL, "gpt7_fck", &gpt7_fck),
CLK(NULL, "gpt8_fck", &gpt8_fck),
CLK(NULL, "gpt9_fck", &gpt9_fck),
CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
CLK(NULL, "gpio6_dbck", &gpio6_dbck),
CLK(NULL, "gpio5_dbck", &gpio5_dbck),
CLK(NULL, "gpio4_dbck", &gpio4_dbck),
CLK(NULL, "gpio3_dbck", &gpio3_dbck),
CLK(NULL, "gpio2_dbck", &gpio2_dbck),
CLK(NULL, "wdt3_fck", &wdt3_fck),
CLK(NULL, "per_l4_ick", &per_l4_ick),
CLK(NULL, "gpio6_ick", &gpio6_ick),
CLK(NULL, "gpio5_ick", &gpio5_ick),
CLK(NULL, "gpio4_ick", &gpio4_ick),
CLK(NULL, "gpio3_ick", &gpio3_ick),
CLK(NULL, "gpio2_ick", &gpio2_ick),
CLK(NULL, "wdt3_ick", &wdt3_ick),
CLK(NULL, "uart3_ick", &uart3_ick),
CLK(NULL, "uart4_ick", &uart4_ick),
CLK(NULL, "gpt9_ick", &gpt9_ick),
CLK(NULL, "gpt8_ick", &gpt8_ick),
CLK(NULL, "gpt7_ick", &gpt7_ick),
CLK(NULL, "gpt6_ick", &gpt6_ick),
CLK(NULL, "gpt5_ick", &gpt5_ick),
CLK(NULL, "gpt4_ick", &gpt4_ick),
CLK(NULL, "gpt3_ick", &gpt3_ick),
CLK(NULL, "gpt2_ick", &gpt2_ick),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
CLK(NULL, "mcbsp4_ick", &mcbsp2_ick),
CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
CLK(NULL, "mcbsp2_ick", &mcbsp4_ick),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
CLK("etb", "emu_src_ck", &emu_src_ck),
CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
CLK(NULL, "emu_src_ck", &emu_src_ck),
CLK(NULL, "pclk_fck", &pclk_fck),
CLK(NULL, "pclkx2_fck", &pclkx2_fck),
CLK(NULL, "atclk_fck", &atclk_fck),
CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
CLK(NULL, "traceclk_fck", &traceclk_fck),
CLK(NULL, "secure_32k_fck", &secure_32k_fck),
CLK(NULL, "gpt12_fck", &gpt12_fck),
CLK(NULL, "wdt1_fck", &wdt1_fck),
{ NULL },
};
static struct ti_clk_alias omap36xx_am35xx_omap3430es2plus_clks[] = {
CLK(NULL, "dpll5_ck", &dpll5_ck),
CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
CLK(NULL, "core_d3_ck", &core_d3_ck),
CLK(NULL, "core_d4_ck", &core_d4_ck),
CLK(NULL, "core_d6_ck", &core_d6_ck),
CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
CLK(NULL, "core_d2_ck", &core_d2_ck),
CLK(NULL, "corex2_d3_fck", &corex2_d3_fck),
CLK(NULL, "corex2_d5_fck", &corex2_d5_fck),
CLK(NULL, "sgx_fck", &sgx_fck),
CLK(NULL, "sgx_ick", &sgx_ick),
CLK(NULL, "cpefuse_fck", &cpefuse_fck),
CLK(NULL, "ts_fck", &ts_fck),
CLK(NULL, "usbtll_fck", &usbtll_fck),
CLK(NULL, "usbtll_ick", &usbtll_ick),
CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
CLK(NULL, "mmchs3_ick", &mmchs3_ick),
CLK(NULL, "mmchs3_fck", &mmchs3_fck),
CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
CLK("omapdss_dss", "ick", &dss_ick_3430es2),
CLK(NULL, "dss_ick", &dss_ick_3430es2),
CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
CLK(NULL, "usbhost_ick", &usbhost_ick),
{ NULL },
};
static struct ti_clk_alias omap3430es1_clks[] = {
CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
CLK(NULL, "fshostusb_fck", &fshostusb_fck),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
CLK(NULL, "fac_ick", &fac_ick),
CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
CLK(NULL, "usb_l4_ick", &usb_l4_ick),
CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
CLK("omapdss_dss", "ick", &dss_ick_3430es1),
CLK(NULL, "dss_ick", &dss_ick_3430es1),
{ NULL },
};
static struct ti_clk_alias omap36xx_clks[] = {
CLK(NULL, "uart4_fck", &uart4_fck),
{ NULL },
};
static struct ti_clk_alias am35xx_clks[] = {
CLK(NULL, "ipss_ick", &ipss_ick),
CLK(NULL, "rmii_ck", &rmii_ck),
CLK(NULL, "pclk_ck", &pclk_ck),
CLK(NULL, "emac_ick", &emac_ick),
CLK(NULL, "emac_fck", &emac_fck),
CLK("davinci_emac.0", NULL, &emac_ick),
CLK("davinci_mdio.0", NULL, &emac_fck),
CLK("vpfe-capture", "master", &vpfe_ick),
CLK("vpfe-capture", "slave", &vpfe_fck),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
CLK(NULL, "hecc_ck", &hecc_ck),
CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
{ NULL },
};
static struct ti_clk *omap36xx_clk_patches[] = {
&dpll4_m3x2_ck_omap36xx,
&dpll3_m3x2_ck_omap36xx,
&dpll4_m6x2_ck_omap36xx,
&dpll4_m2x2_ck_omap36xx,
&dpll4_m5x2_ck_omap36xx,
&dpll4_ck_omap36xx,
NULL,
};
static const char *enable_init_clks[] = {
"sdrc_ick",
"gpmc_fck",
"omapctrl_ick",
};
static void __init omap3_clk_legacy_common_init(void)
{
omap2_clk_disable_autoidle_all();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
(clk_get_rate(osc_sys_ck.clk) / 1000000),
(clk_get_rate(osc_sys_ck.clk) / 100000) % 10,
(clk_get_rate(core_ck.clk) / 1000000),
(clk_get_rate(arm_fck.clk) / 1000000));
}
int __init omap3430es1_clk_legacy_init(void)
{
int r;
r = ti_clk_register_legacy_clks(omap3430es1_clks);
r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
r |= ti_clk_register_legacy_clks(omap3xxx_clks);
omap3_clk_legacy_common_init();
return r;
}
int __init omap3430_clk_legacy_init(void)
{
int r;
r = ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks);
r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
r |= ti_clk_register_legacy_clks(omap3xxx_clks);
omap3_clk_legacy_common_init();
omap3_clk_lock_dpll5();
return r;
}
int __init omap36xx_clk_legacy_init(void)
{
int r;
ti_clk_patch_legacy_clks(omap36xx_clk_patches);
r = ti_clk_register_legacy_clks(omap36xx_clks);
r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks);
r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
r |= ti_clk_register_legacy_clks(omap3xxx_clks);
omap3_clk_legacy_common_init();
omap3_clk_lock_dpll5();
return r;
}
int __init am35xx_clk_legacy_init(void)
{
int r;
r = ti_clk_register_legacy_clks(am35xx_clks);
r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
r |= ti_clk_register_legacy_clks(omap3xxx_clks);
omap3_clk_legacy_common_init();
omap3_clk_lock_dpll5();
return r;
}
drivers/clk/ti/clk.c
浏览文件 @ fe767560
......@@ -22,6 +22,8 @@
#include <linux/of_address.h>
#include <linux/list.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
......@@ -183,3 +185,126 @@ void ti_dt_clk_init_retry_clks(void)
retries--;
}
}
void __init ti_clk_patch_legacy_clks(struct ti_clk **patch)
{
while (*patch) {
memcpy((*patch)->patch, *patch, sizeof(**patch));
patch++;
}
}
struct clk __init *ti_clk_register_clk(struct ti_clk *setup)
{
struct clk *clk;
struct ti_clk_fixed *fixed;
struct ti_clk_fixed_factor *fixed_factor;
struct clk_hw *clk_hw;
if (setup->clk)
return setup->clk;
switch (setup->type) {
case TI_CLK_FIXED:
fixed = setup->data;
clk = clk_register_fixed_rate(NULL, setup->name, NULL,
CLK_IS_ROOT, fixed->frequency);
break;
case TI_CLK_MUX:
clk = ti_clk_register_mux(setup);
break;
case TI_CLK_DIVIDER:
clk = ti_clk_register_divider(setup);
break;
case TI_CLK_COMPOSITE:
clk = ti_clk_register_composite(setup);
break;
case TI_CLK_FIXED_FACTOR:
fixed_factor = setup->data;
clk = clk_register_fixed_factor(NULL, setup->name,
fixed_factor->parent,
0, fixed_factor->mult,
fixed_factor->div);
break;
case TI_CLK_GATE:
clk = ti_clk_register_gate(setup);
break;
case TI_CLK_DPLL:
clk = ti_clk_register_dpll(setup);
break;
default:
pr_err("bad type for %s!\n", setup->name);
clk = ERR_PTR(-EINVAL);
}
if (!IS_ERR(clk)) {
setup->clk = clk;
if (setup->clkdm_name) {
if (__clk_get_flags(clk) & CLK_IS_BASIC) {
pr_warn("can't setup clkdm for basic clk %s\n",
setup->name);
} else {
clk_hw = __clk_get_hw(clk);
to_clk_hw_omap(clk_hw)->clkdm_name =
setup->clkdm_name;
omap2_init_clk_clkdm(clk_hw);
}
}
}
return clk;
}
int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks)
{
struct clk *clk;
bool retry;
struct ti_clk_alias *retry_clk;
struct ti_clk_alias *tmp;
while (clks->clk) {
clk = ti_clk_register_clk(clks->clk);
if (IS_ERR(clk)) {
if (PTR_ERR(clk) == -EAGAIN) {
list_add(&clks->link, &retry_list);
} else {
pr_err("register for %s failed: %ld\n",
clks->clk->name, PTR_ERR(clk));
return PTR_ERR(clk);
}
} else {
clks->lk.clk = clk;
clkdev_add(&clks->lk);
}
clks++;
}
retry = true;
while (!list_empty(&retry_list) && retry) {
retry = false;
list_for_each_entry_safe(retry_clk, tmp, &retry_list, link) {
pr_debug("retry-init: %s\n", retry_clk->clk->name);
clk = ti_clk_register_clk(retry_clk->clk);
if (IS_ERR(clk)) {
if (PTR_ERR(clk) == -EAGAIN) {
continue;
} else {
pr_err("register for %s failed: %ld\n",
retry_clk->clk->name,
PTR_ERR(clk));
return PTR_ERR(clk);
}
} else {
retry = true;
retry_clk->lk.clk = clk;
clkdev_add(&retry_clk->lk);
list_del(&retry_clk->link);
}
}
}
return 0;
}
drivers/clk/ti/clock.h 0 → 100644
浏览文件 @ fe767560
/*
* TI Clock driver internal definitions
*
* Copyright (C) 2014 Texas Instruments, Inc
* Tero Kristo (t-kristo@ti.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DRIVERS_CLK_TI_CLOCK__
#define __DRIVERS_CLK_TI_CLOCK__
enum {
TI_CLK_FIXED,
TI_CLK_MUX,
TI_CLK_DIVIDER,
TI_CLK_COMPOSITE,
TI_CLK_FIXED_FACTOR,
TI_CLK_GATE,
TI_CLK_DPLL,
};
/* Global flags */
#define CLKF_INDEX_POWER_OF_TWO (1 << 0)
#define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
#define CLKF_SET_RATE_PARENT (1 << 2)
#define CLKF_OMAP3 (1 << 3)
#define CLKF_AM35XX (1 << 4)
/* Gate flags */
#define CLKF_SET_BIT_TO_DISABLE (1 << 5)
#define CLKF_INTERFACE (1 << 6)
#define CLKF_SSI (1 << 7)
#define CLKF_DSS (1 << 8)
#define CLKF_HSOTGUSB (1 << 9)
#define CLKF_WAIT (1 << 10)
#define CLKF_NO_WAIT (1 << 11)
#define CLKF_HSDIV (1 << 12)
#define CLKF_CLKDM (1 << 13)
/* DPLL flags */
#define CLKF_LOW_POWER_STOP (1 << 5)
#define CLKF_LOCK (1 << 6)
#define CLKF_LOW_POWER_BYPASS (1 << 7)
#define CLKF_PER (1 << 8)
#define CLKF_CORE (1 << 9)
#define CLKF_J_TYPE (1 << 10)
#define CLK(dev, con, ck) \
{ \
.lk = { \
.dev_id = dev, \
.con_id = con, \
}, \
.clk = ck, \
}
struct ti_clk {
const char *name;
const char *clkdm_name;
int type;
void *data;
struct ti_clk *patch;
struct clk *clk;
};
struct ti_clk_alias {
struct ti_clk *clk;
struct clk_lookup lk;
struct list_head link;
};
struct ti_clk_fixed {
u32 frequency;
u16 flags;
};
struct ti_clk_mux {
u8 bit_shift;
int num_parents;
u16 reg;
u8 module;
const char **parents;
u16 flags;
};
struct ti_clk_divider {
const char *parent;
u8 bit_shift;
u16 max_div;
u16 reg;
u8 module;
int *dividers;
int num_dividers;
u16 flags;
};
struct ti_clk_fixed_factor {
const char *parent;
u16 div;
u16 mult;
u16 flags;
};
struct ti_clk_gate {
const char *parent;
u8 bit_shift;
u16 reg;
u8 module;
u16 flags;
};
struct ti_clk_composite {
struct ti_clk_divider *divider;
struct ti_clk_mux *mux;
struct ti_clk_gate *gate;
u16 flags;
};
struct ti_clk_clkdm_gate {
const char *parent;
u16 flags;
};
struct ti_clk_dpll {
int num_parents;
u16 control_reg;
u16 idlest_reg;
u16 autoidle_reg;
u16 mult_div1_reg;
u8 module;
const char **parents;
u16 flags;
u8 modes;
u32 mult_mask;
u32 div1_mask;
u32 enable_mask;
u32 autoidle_mask;
u32 freqsel_mask;
u32 idlest_mask;
u32 dco_mask;
u32 sddiv_mask;
u16 max_multiplier;
u16 max_divider;
u8 min_divider;
u8 auto_recal_bit;
u8 recal_en_bit;
u8 recal_st_bit;
};
struct clk *ti_clk_register_gate(struct ti_clk *setup);
struct clk *ti_clk_register_interface(struct ti_clk *setup);
struct clk *ti_clk_register_mux(struct ti_clk *setup);
struct clk *ti_clk_register_divider(struct ti_clk *setup);
struct clk *ti_clk_register_composite(struct ti_clk *setup);
struct clk *ti_clk_register_dpll(struct ti_clk *setup);
struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup);
struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
void ti_clk_patch_legacy_clks(struct ti_clk **patch);
struct clk *ti_clk_register_clk(struct ti_clk *setup);
int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
#endif
drivers/clk/ti/composite.c
浏览文件 @ fe767560
......@@ -23,6 +23,8 @@
#include <linux/clk/ti.h>
#include <linux/list.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
......@@ -116,7 +118,43 @@ static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
static void __init ti_clk_register_composite(struct clk_hw *hw,
struct clk *ti_clk_register_composite(struct ti_clk *setup)
{
struct ti_clk_composite *comp;
struct clk_hw *gate;
struct clk_hw *mux;
struct clk_hw *div;
int num_parents = 1;
const char **parent_names = NULL;
struct clk *clk;
comp = setup->data;
div = ti_clk_build_component_div(comp->divider);
gate = ti_clk_build_component_gate(comp->gate);
mux = ti_clk_build_component_mux(comp->mux);
if (div)
parent_names = &comp->divider->parent;
if (gate)
parent_names = &comp->gate->parent;
if (mux) {
num_parents = comp->mux->num_parents;
parent_names = comp->mux->parents;
}
clk = clk_register_composite(NULL, setup->name,
parent_names, num_parents, mux,
&ti_clk_mux_ops, div,
&ti_composite_divider_ops, gate,
&ti_composite_gate_ops, 0);
return clk;
}
static void __init _register_composite(struct clk_hw *hw,
struct device_node *node)
{
struct clk *clk;
......@@ -136,7 +174,7 @@ static void __init ti_clk_register_composite(struct clk_hw *hw,
pr_debug("component %s not ready for %s, retry\n",
cclk->comp_nodes[i]->name, node->name);
if (!ti_clk_retry_init(node, hw,
ti_clk_register_composite))
_register_composite))
return;
goto cleanup;
......@@ -216,7 +254,7 @@ static void __init of_ti_composite_clk_setup(struct device_node *node)
for (i = 0; i < num_clks; i++)
cclk->comp_nodes[i] = _get_component_node(node, i);
ti_clk_register_composite(&cclk->hw, node);
_register_composite(&cclk->hw, node);
}
CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock",
of_ti_composite_clk_setup);
......
drivers/clk/ti/divider.c
浏览文件 @ fe767560
......@@ -21,6 +21,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
......@@ -300,6 +301,134 @@ static struct clk *_register_divider(struct device *dev, const char *name,
return clk;
}
static struct clk_div_table *
_get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
{
int valid_div = 0;
struct clk_div_table *table;
int i;
int div;
u32 val;
u8 flags;
if (!setup->num_dividers) {
/* Clk divider table not provided, determine min/max divs */
flags = setup->flags;
if (flags & CLKF_INDEX_STARTS_AT_ONE)
val = 1;
else
val = 0;
div = 1;
while (div < setup->max_div) {
if (flags & CLKF_INDEX_POWER_OF_TWO)
div <<= 1;
else
div++;
val++;
}
*width = fls(val);
return NULL;
}
for (i = 0; i < setup->num_dividers; i++)
if (setup->dividers[i])
valid_div++;
table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
if (!table)
return ERR_PTR(-ENOMEM);
valid_div = 0;
*width = 0;
for (i = 0; i < setup->num_dividers; i++)
if (setup->dividers[i]) {
table[valid_div].div = setup->dividers[i];
table[valid_div].val = i;
valid_div++;
*width = i;
}
*width = fls(*width);
return table;
}
struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
{
struct clk_divider *div;
struct clk_omap_reg *reg;
if (!setup)
return NULL;
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
return ERR_PTR(-ENOMEM);
reg = (struct clk_omap_reg *)&div->reg;
reg->index = setup->module;
reg->offset = setup->reg;
if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
div->flags |= CLK_DIVIDER_ONE_BASED;
if (setup->flags & CLKF_INDEX_POWER_OF_TWO)
div->flags |= CLK_DIVIDER_POWER_OF_TWO;
div->table = _get_div_table_from_setup(setup, &div->width);
div->shift = setup->bit_shift;
return &div->hw;
}
struct clk *ti_clk_register_divider(struct ti_clk *setup)
{
struct ti_clk_divider *div;
struct clk_omap_reg *reg_setup;
u32 reg;
u8 width;
u32 flags = 0;
u8 div_flags = 0;
struct clk_div_table *table;
struct clk *clk;
div = setup->data;
reg_setup = (struct clk_omap_reg *)&reg;
reg_setup->index = div->module;
reg_setup->offset = div->reg;
if (div->flags & CLKF_INDEX_STARTS_AT_ONE)
div_flags |= CLK_DIVIDER_ONE_BASED;
if (div->flags & CLKF_INDEX_POWER_OF_TWO)
div_flags |= CLK_DIVIDER_POWER_OF_TWO;
if (div->flags & CLKF_SET_RATE_PARENT)
flags |= CLK_SET_RATE_PARENT;
table = _get_div_table_from_setup(div, &width);
if (IS_ERR(table))
return (struct clk *)table;
clk = _register_divider(NULL, setup->name, div->parent,
flags, (void __iomem *)reg, div->bit_shift,
width, div_flags, table, NULL);
if (IS_ERR(clk))
kfree(table);
return clk;
}
static struct clk_div_table *
__init ti_clk_get_div_table(struct device_node *node)
{
......@@ -455,7 +584,8 @@ static void __init of_ti_divider_clk_setup(struct device_node *node)
goto cleanup;
clk = _register_divider(NULL, node->name, parent_name, flags, reg,
shift, width, clk_divider_flags, table, NULL);
shift, width, clk_divider_flags, table,
NULL);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
......
drivers/clk/ti/dpll.c
浏览文件 @ fe767560
......@@ -21,6 +21,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
......@@ -130,7 +131,7 @@ static const struct clk_ops dpll_x2_ck_ops = {
};
/**
* ti_clk_register_dpll - low level registration of a DPLL clock
* _register_dpll - low level registration of a DPLL clock
* @hw: hardware clock definition for the clock
* @node: device node for the clock
*
......@@ -138,7 +139,7 @@ static const struct clk_ops dpll_x2_ck_ops = {
* clk-bypass is missing), the clock is added to retry list and
* the initialization is retried on later stage.
*/
static void __init ti_clk_register_dpll(struct clk_hw *hw,
static void __init _register_dpll(struct clk_hw *hw,
struct device_node *node)
{
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
......@@ -151,7 +152,7 @@ static void __init ti_clk_register_dpll(struct clk_hw *hw,
if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) {
pr_debug("clk-ref or clk-bypass missing for %s, retry later\n",
node->name);
if (!ti_clk_retry_init(node, hw, ti_clk_register_dpll))
if (!ti_clk_retry_init(node, hw, _register_dpll))
return;
goto cleanup;
......@@ -175,18 +176,114 @@ static void __init ti_clk_register_dpll(struct clk_hw *hw,
kfree(clk_hw);
}
void __iomem *_get_reg(u8 module, u16 offset)
{
u32 reg;
struct clk_omap_reg *reg_setup;
reg_setup = (struct clk_omap_reg *)&reg;
reg_setup->index = module;
reg_setup->offset = offset;
return (void __iomem *)reg;
}
struct clk *ti_clk_register_dpll(struct ti_clk *setup)
{
struct clk_hw_omap *clk_hw;
struct clk_init_data init = { NULL };
struct dpll_data *dd;
struct clk *clk;
struct ti_clk_dpll *dpll;
const struct clk_ops *ops = &omap3_dpll_ck_ops;
struct clk *clk_ref;
struct clk *clk_bypass;
dpll = setup->data;
if (dpll->num_parents < 2)
return ERR_PTR(-EINVAL);
clk_ref = clk_get_sys(NULL, dpll->parents[0]);
clk_bypass = clk_get_sys(NULL, dpll->parents[1]);
if (IS_ERR_OR_NULL(clk_ref) || IS_ERR_OR_NULL(clk_bypass))
return ERR_PTR(-EAGAIN);
dd = kzalloc(sizeof(*dd), GFP_KERNEL);
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
if (!dd || !clk_hw) {
clk = ERR_PTR(-ENOMEM);
goto cleanup;
}
clk_hw->dpll_data = dd;
clk_hw->ops = &clkhwops_omap3_dpll;
clk_hw->hw.init = &init;
clk_hw->flags = MEMMAP_ADDRESSING;
init.name = setup->name;
init.ops = ops;
init.num_parents = dpll->num_parents;
init.parent_names = dpll->parents;
dd->control_reg = _get_reg(dpll->module, dpll->control_reg);
dd->idlest_reg = _get_reg(dpll->module, dpll->idlest_reg);
dd->mult_div1_reg = _get_reg(dpll->module, dpll->mult_div1_reg);
dd->autoidle_reg = _get_reg(dpll->module, dpll->autoidle_reg);
dd->modes = dpll->modes;
dd->div1_mask = dpll->div1_mask;
dd->idlest_mask = dpll->idlest_mask;
dd->mult_mask = dpll->mult_mask;
dd->autoidle_mask = dpll->autoidle_mask;
dd->enable_mask = dpll->enable_mask;
dd->sddiv_mask = dpll->sddiv_mask;
dd->dco_mask = dpll->dco_mask;
dd->max_divider = dpll->max_divider;
dd->min_divider = dpll->min_divider;
dd->max_multiplier = dpll->max_multiplier;
dd->auto_recal_bit = dpll->auto_recal_bit;
dd->recal_en_bit = dpll->recal_en_bit;
dd->recal_st_bit = dpll->recal_st_bit;
dd->clk_ref = clk_ref;
dd->clk_bypass = clk_bypass;
if (dpll->flags & CLKF_CORE)
ops = &omap3_dpll_core_ck_ops;
if (dpll->flags & CLKF_PER)
ops = &omap3_dpll_per_ck_ops;
if (dpll->flags & CLKF_J_TYPE)
dd->flags |= DPLL_J_TYPE;
clk = clk_register(NULL, &clk_hw->hw);
if (!IS_ERR(clk))
return clk;
cleanup:
kfree(dd);
kfree(clk_hw);
return clk;
}
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
defined(CONFIG_SOC_AM43XX)
/**
* ti_clk_register_dpll_x2 - Registers a DPLLx2 clock
* _register_dpll_x2 - Registers a DPLLx2 clock
* @node: device node for this clock
* @ops: clk_ops for this clock
* @hw_ops: clk_hw_ops for this clock
*
* Initializes a DPLL x 2 clock from device tree data.
*/
static void ti_clk_register_dpll_x2(struct device_node *node,
static void _register_dpll_x2(struct device_node *node,
const struct clk_ops *ops,
const struct clk_hw_omap_ops *hw_ops)
{
......@@ -318,7 +415,7 @@ static void __init of_ti_dpll_setup(struct device_node *node,
if (dpll_mode)
dd->modes = dpll_mode;
ti_clk_register_dpll(&clk_hw->hw, node);
_register_dpll(&clk_hw->hw, node);
return;
cleanup:
......@@ -332,7 +429,7 @@ static void __init of_ti_dpll_setup(struct device_node *node,
defined(CONFIG_SOC_DRA7XX)
static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
{
ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
}
CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
of_ti_omap4_dpll_x2_setup);
......@@ -341,7 +438,7 @@ CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
{
ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
_register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
}
CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
of_ti_am3_dpll_x2_setup);
......
drivers/clk/ti/gate.c
浏览文件 @ fe767560
......@@ -22,6 +22,8 @@
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
#undef pr_fmt
......@@ -90,63 +92,162 @@ static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
return ret;
}
static void __init _of_ti_gate_clk_setup(struct device_node *node,
const struct clk_ops *ops,
static struct clk *_register_gate(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx,
u8 clk_gate_flags, const struct clk_ops *ops,
const struct clk_hw_omap_ops *hw_ops)
{
struct clk *clk;
struct clk_init_data init = { NULL };
struct clk_hw_omap *clk_hw;
const char *clk_name = node->name;
const char *parent_name;
u32 val;
struct clk *clk;
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
if (!clk_hw)
return;
return ERR_PTR(-ENOMEM);
clk_hw->hw.init = &init;
init.name = clk_name;
init.name = name;
init.ops = ops;
if (ops != &omap_gate_clkdm_clk_ops) {
clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0);
if (!clk_hw->enable_reg)
goto cleanup;
clk_hw->enable_reg = reg;
clk_hw->enable_bit = bit_idx;
clk_hw->ops = hw_ops;
if (!of_property_read_u32(node, "ti,bit-shift", &val))
clk_hw->enable_bit = val;
clk_hw->flags = MEMMAP_ADDRESSING | clk_gate_flags;
init.parent_names = &parent_name;
init.num_parents = 1;
init.flags = flags;
clk = clk_register(NULL, &clk_hw->hw);
if (IS_ERR(clk))
kfree(clk_hw);
return clk;
}
struct clk *ti_clk_register_gate(struct ti_clk *setup)
{
const struct clk_ops *ops = &omap_gate_clk_ops;
const struct clk_hw_omap_ops *hw_ops = NULL;
u32 reg;
struct clk_omap_reg *reg_setup;
u32 flags = 0;
u8 clk_gate_flags = 0;
struct ti_clk_gate *gate;
gate = setup->data;
if (gate->flags & CLKF_INTERFACE)
return ti_clk_register_interface(setup);
reg_setup = (struct clk_omap_reg *)&reg;
if (gate->flags & CLKF_SET_RATE_PARENT)
flags |= CLK_SET_RATE_PARENT;
if (gate->flags & CLKF_SET_BIT_TO_DISABLE)
clk_gate_flags |= INVERT_ENABLE;
if (gate->flags & CLKF_HSDIV) {
ops = &omap_gate_clk_hsdiv_restore_ops;
hw_ops = &clkhwops_wait;
}
clk_hw->ops = hw_ops;
if (gate->flags & CLKF_DSS)
hw_ops = &clkhwops_omap3430es2_dss_usbhost_wait;
if (gate->flags & CLKF_WAIT)
hw_ops = &clkhwops_wait;
if (gate->flags & CLKF_CLKDM)
ops = &omap_gate_clkdm_clk_ops;
if (gate->flags & CLKF_AM35XX)
hw_ops = &clkhwops_am35xx_ipss_module_wait;
clk_hw->flags = MEMMAP_ADDRESSING;
reg_setup->index = gate->module;
reg_setup->offset = gate->reg;
return _register_gate(NULL, setup->name, gate->parent, flags,
(void __iomem *)reg, gate->bit_shift,
clk_gate_flags, ops, hw_ops);
}
struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup)
{
struct clk_hw_omap *gate;
struct clk_omap_reg *reg;
const struct clk_hw_omap_ops *ops = &clkhwops_wait;
if (!setup)
return NULL;
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
reg = (struct clk_omap_reg *)&gate->enable_reg;
reg->index = setup->module;
reg->offset = setup->reg;
gate->enable_bit = setup->bit_shift;
if (setup->flags & CLKF_NO_WAIT)
ops = NULL;
if (setup->flags & CLKF_INTERFACE)
ops = &clkhwops_iclk_wait;
gate->ops = ops;
gate->flags = MEMMAP_ADDRESSING;
return &gate->hw;
}
static void __init _of_ti_gate_clk_setup(struct device_node *node,
const struct clk_ops *ops,
const struct clk_hw_omap_ops *hw_ops)
{
struct clk *clk;
const char *parent_name;
void __iomem *reg = NULL;
u8 enable_bit = 0;
u32 val;
u32 flags = 0;
u8 clk_gate_flags = 0;
if (ops != &omap_gate_clkdm_clk_ops) {
reg = ti_clk_get_reg_addr(node, 0);
if (!reg)
return;
if (!of_property_read_u32(node, "ti,bit-shift", &val))
enable_bit = val;
}
if (of_clk_get_parent_count(node) != 1) {
pr_err("%s must have 1 parent\n", clk_name);
goto cleanup;
pr_err("%s must have 1 parent\n", node->name);
return;
}
parent_name = of_clk_get_parent_name(node, 0);
init.parent_names = &parent_name;
init.num_parents = 1;
if (of_property_read_bool(node, "ti,set-rate-parent"))
init.flags |= CLK_SET_RATE_PARENT;
flags |= CLK_SET_RATE_PARENT;
if (of_property_read_bool(node, "ti,set-bit-to-disable"))
clk_hw->flags |= INVERT_ENABLE;
clk_gate_flags |= INVERT_ENABLE;
clk = clk_register(NULL, &clk_hw->hw);
clk = _register_gate(NULL, node->name, parent_name, flags, reg,
enable_bit, clk_gate_flags, ops, hw_ops);
if (!IS_ERR(clk)) {
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
return;
}
cleanup:
kfree(clk_hw);
}
static void __init
......
drivers/clk/ti/interface.c
浏览文件 @ fe767560
......@@ -20,6 +20,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
......@@ -31,53 +32,100 @@ static const struct clk_ops ti_interface_clk_ops = {
.is_enabled = &omap2_dflt_clk_is_enabled,
};
static void __init _of_ti_interface_clk_setup(struct device_node *node,
static struct clk *_register_interface(struct device *dev, const char *name,
const char *parent_name,
void __iomem *reg, u8 bit_idx,
const struct clk_hw_omap_ops *ops)
{
struct clk *clk;
struct clk_init_data init = { NULL };
struct clk_hw_omap *clk_hw;
const char *parent_name;
u32 val;
struct clk *clk;
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
if (!clk_hw)
return;
return ERR_PTR(-ENOMEM);
clk_hw->hw.init = &init;
clk_hw->ops = ops;
clk_hw->flags = MEMMAP_ADDRESSING;
clk_hw->enable_reg = reg;
clk_hw->enable_bit = bit_idx;
clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0);
if (!clk_hw->enable_reg)
goto cleanup;
if (!of_property_read_u32(node, "ti,bit-shift", &val))
clk_hw->enable_bit = val;
init.name = node->name;
init.name = name;
init.ops = &ti_interface_clk_ops;
init.flags = 0;
parent_name = of_clk_get_parent_name(node, 0);
if (!parent_name) {
pr_err("%s must have a parent\n", node->name);
goto cleanup;
}
init.num_parents = 1;
init.parent_names = &parent_name;
clk = clk_register(NULL, &clk_hw->hw);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
if (IS_ERR(clk))
kfree(clk_hw);
else
omap2_init_clk_hw_omap_clocks(clk);
return clk;
}
struct clk *ti_clk_register_interface(struct ti_clk *setup)
{
const struct clk_hw_omap_ops *ops = &clkhwops_iclk_wait;
u32 reg;
struct clk_omap_reg *reg_setup;
struct ti_clk_gate *gate;
gate = setup->data;
reg_setup = (struct clk_omap_reg *)&reg;
reg_setup->index = gate->module;
reg_setup->offset = gate->reg;
if (gate->flags & CLKF_NO_WAIT)
ops = &clkhwops_iclk;
if (gate->flags & CLKF_HSOTGUSB)
ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait;
if (gate->flags & CLKF_DSS)
ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait;
if (gate->flags & CLKF_SSI)
ops = &clkhwops_omap3430es2_iclk_ssi_wait;
if (gate->flags & CLKF_AM35XX)
ops = &clkhwops_am35xx_ipss_wait;
return _register_interface(NULL, setup->name, gate->parent,
(void __iomem *)reg, gate->bit_shift, ops);
}
static void __init _of_ti_interface_clk_setup(struct device_node *node,
const struct clk_hw_omap_ops *ops)
{
struct clk *clk;
const char *parent_name;
void __iomem *reg;
u8 enable_bit = 0;
u32 val;
reg = ti_clk_get_reg_addr(node, 0);
if (!reg)
return;
if (!of_property_read_u32(node, "ti,bit-shift", &val))
enable_bit = val;
parent_name = of_clk_get_parent_name(node, 0);
if (!parent_name) {
pr_err("%s must have a parent\n", node->name);
return;
}
cleanup:
kfree(clk_hw);
clk = _register_interface(NULL, node->name, parent_name, reg,
enable_bit, ops);
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
}
static void __init of_ti_interface_clk_setup(struct device_node *node)
......
drivers/clk/ti/mux.c
浏览文件 @ fe767560
......@@ -21,6 +21,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
......@@ -144,6 +145,39 @@ static struct clk *_register_mux(struct device *dev, const char *name,
return clk;
}
struct clk *ti_clk_register_mux(struct ti_clk *setup)
{
struct ti_clk_mux *mux;
u32 flags;
u8 mux_flags = 0;
struct clk_omap_reg *reg_setup;
u32 reg;
u32 mask;
reg_setup = (struct clk_omap_reg *)&reg;
mux = setup->data;
flags = CLK_SET_RATE_NO_REPARENT;
mask = mux->num_parents;
if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE))
mask--;
mask = (1 << fls(mask)) - 1;
reg_setup->index = mux->module;
reg_setup->offset = mux->reg;
if (mux->flags & CLKF_INDEX_STARTS_AT_ONE)
mux_flags |= CLK_MUX_INDEX_ONE;
if (mux->flags & CLKF_SET_RATE_PARENT)
flags |= CLK_SET_RATE_PARENT;
return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
flags, (void __iomem *)reg, mux->bit_shift, mask,
mux_flags, NULL, NULL);
}
/**
* of_mux_clk_setup - Setup function for simple mux rate clock
* @node: DT node for the clock
......@@ -194,8 +228,9 @@ static void of_mux_clk_setup(struct device_node *node)
mask = (1 << fls(mask)) - 1;
clk = _register_mux(NULL, node->name, parent_names, num_parents, flags,
reg, shift, mask, clk_mux_flags, NULL, NULL);
clk = _register_mux(NULL, node->name, parent_names, num_parents,
flags, reg, shift, mask, clk_mux_flags, NULL,
NULL);
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
......@@ -205,6 +240,37 @@ static void of_mux_clk_setup(struct device_node *node)
}
CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
{
struct clk_mux *mux;
struct clk_omap_reg *reg;
int num_parents;
if (!setup)
return NULL;
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
reg = (struct clk_omap_reg *)&mux->reg;
mux->shift = setup->bit_shift;
reg->index = setup->module;
reg->offset = setup->reg;
if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
mux->flags |= CLK_MUX_INDEX_ONE;
num_parents = setup->num_parents;
mux->mask = num_parents - 1;
mux->mask = (1 << fls(mux->mask)) - 1;
return &mux->hw;
}
static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
{
struct clk_mux *mux;
......
include/linux/clk/ti.h
浏览文件 @ fe767560
......@@ -218,6 +218,13 @@ struct ti_dt_clk {
/* Maximum number of clock memmaps */
#define CLK_MAX_MEMMAPS 4
/* Static memmap indices */
enum {
TI_CLKM_CM = 0,
TI_CLKM_PRM,
TI_CLKM_SCRM,
};
typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
/**
......@@ -349,4 +356,9 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
int omap3430_clk_legacy_init(void);
int omap3430es1_clk_legacy_init(void);
int omap36xx_clk_legacy_init(void);
int am35xx_clk_legacy_init(void);
#endif
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或