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kernel_linux
提交 fdc614e8 编写于 作者: R Russell King 提交者： Russell King
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Merge branches 'pxa-misc', 'pxa-pwm' and 'pxa-multi' into pxa

上级 bdb08cb2 c0f7edb3 9fc697b0
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Showing with 2198 addition and 2343 deletion
arch/arm/Kconfig
浏览文件 @ fdc614e8
...@@ -22,6 +22,9 @@ config ARM ...@@ -22,6 +22,9 @@ config ARM
Europe. There is an ARM Linux project with a web page at Europe. There is an ARM Linux project with a web page at
<http://www.arm.linux.org.uk/>. <http://www.arm.linux.org.uk/>.
config HAVE_PWM
bool
config SYS_SUPPORTS_APM_EMULATION config SYS_SUPPORTS_APM_EMULATION
bool bool
......
arch/arm/common/sharpsl_pm.c
浏览文件 @ fdc614e8
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/arch/pm.h> #include <asm/arch/pm.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/sharpsl.h> #include <asm/arch/sharpsl.h>
#include <asm/hardware/sharpsl_pm.h> #include <asm/hardware/sharpsl_pm.h>
...@@ -157,6 +158,7 @@ static void sharpsl_battery_thread(struct work_struct *private_) ...@@ -157,6 +158,7 @@ static void sharpsl_battery_thread(struct work_struct *private_)
dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage, dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage,
sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies); sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies);
#ifdef CONFIG_BACKLIGHT_CORGI
/* If battery is low. limit backlight intensity to save power. */ /* If battery is low. limit backlight intensity to save power. */
if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE) if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
&& ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) || && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) ||
...@@ -169,6 +171,7 @@ static void sharpsl_battery_thread(struct work_struct *private_) ...@@ -169,6 +171,7 @@ static void sharpsl_battery_thread(struct work_struct *private_)
sharpsl_pm.machinfo->backlight_limit(0); sharpsl_pm.machinfo->backlight_limit(0);
sharpsl_pm.flags &= ~SHARPSL_BL_LIMIT; sharpsl_pm.flags &= ~SHARPSL_BL_LIMIT;
} }
#endif
/* Suspend if critical battery level */ /* Suspend if critical battery level */
if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE) if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
......
arch/arm/configs/em_x270_defconfig 已删除 100644 → 0
浏览文件 @ bdb08cb2
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.22
# Mon Jul 9 15:18:20 2007
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y
# CONFIG_GENERIC_CLOCKEVENTS is not set
CONFIG_MMU=y
# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ZONE_DMA=y
CONFIG_ARCH_MTD_XIP=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_LOCALVERSION="-em-x270"
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_IPC_NS is not set
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_UTS_NS is not set
# CONFIG_AUDIT is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=17
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
#
# Block layer
#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
#
# System Type
#
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_PNX4008 is not set
CONFIG_ARCH_PXA=y
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
#
# Intel PXA2xx Implementations
#
# CONFIG_ARCH_LUBBOCK is not set
# CONFIG_MACH_LOGICPD_PXA270 is not set
# CONFIG_MACH_MAINSTONE is not set
# CONFIG_ARCH_PXA_IDP is not set
# CONFIG_PXA_SHARPSL is not set
# CONFIG_MACH_TRIZEPS4 is not set
CONFIG_MACH_EM_X270=y
CONFIG_PXA27x=y
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_XSCALE=y
CONFIG_CPU_32v5=y
CONFIG_CPU_ABRT_EV5T=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_TLB_V4WBI=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
#
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_OUTER_CACHE is not set
CONFIG_IWMMXT=y
CONFIG_XSCALE_PMU=y
#
# Bus support
#
# CONFIG_ARCH_SUPPORTS_MSI is not set
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
# Kernel Features
#
# CONFIG_TICK_ONESHOT is not set
# CONFIG_PREEMPT is not set
# CONFIG_NO_IDLE_HZ is not set
CONFIG_HZ=100
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_ALIGNMENT_TRAP=y
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE=""
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_NWFPE_XP is not set
# CONFIG_FPE_FASTFPE is not set
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
#
# Power management options
#
CONFIG_PM=y
CONFIG_PM_LEGACY=y
# CONFIG_PM_DEBUG is not set
# CONFIG_PM_SYSFS_DEPRECATED is not set
CONFIG_APM_EMULATION=m
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
CONFIG_BT=m
CONFIG_BT_L2CAP=m
CONFIG_BT_SCO=m
CONFIG_BT_RFCOMM=m
# CONFIG_BT_RFCOMM_TTY is not set
CONFIG_BT_BNEP=m
# CONFIG_BT_BNEP_MC_FILTER is not set
# CONFIG_BT_BNEP_PROTO_FILTER is not set
CONFIG_BT_HIDP=m
#
# Bluetooth device drivers
#
CONFIG_BT_HCIUSB=m
# CONFIG_BT_HCIUSB_SCO is not set
CONFIG_BT_HCIUART=m
# CONFIG_BT_HCIUART_H4 is not set
# CONFIG_BT_HCIUART_BCSP is not set
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
# CONFIG_BT_HCIVHCI is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
CONFIG_IEEE80211=m
# CONFIG_IEEE80211_DEBUG is not set
CONFIG_IEEE80211_CRYPT_WEP=m
CONFIG_IEEE80211_CRYPT_CCMP=m
# CONFIG_IEEE80211_CRYPT_TKIP is not set
# CONFIG_IEEE80211_SOFTMAC is not set
# CONFIG_RFKILL is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
#
# Connector - unified userspace <-> kernelspace linker
#
# CONFIG_CONNECTOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
# CONFIG_MTD_AFS_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
# CONFIG_MTD_CFI_NOSWAP is not set
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_SHARP_SL is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_NAND_ECC_SMC is not set
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
# CONFIG_MTD_NAND_H1900 is not set
CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_NAND_SHARPSL is not set
# CONFIG_MTD_NAND_NANDSIM is not set
CONFIG_MTD_NAND_PLATFORM=y
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNPACPI is not set
#
# Block devices
#
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=12000
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_SCSI_PROC_FS is not set
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
#
# SCSI low-level drivers
#
# CONFIG_ISCSI_TCP is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_ATA is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Network device support
#
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_PHYLIB is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_SMC91X is not set
CONFIG_DM9000=y
# CONFIG_SMC911X is not set
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
#
# USB Network Adapters
#
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET_MII is not set
# CONFIG_USB_USBNET is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
CONFIG_KEYBOARD_PXA27x=m
# CONFIG_KEYBOARD_GPIO is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_UCB1400 is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
# CONFIG_WATCHDOG is not set
CONFIG_HW_RANDOM=m
# CONFIG_NVRAM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
# CONFIG_HWMON is not set
#
# Misc devices
#
#
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
#
# LED devices
#
# CONFIG_NEW_LEDS is not set
#
# LED drivers
#
#
# LED Triggers
#
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_SYS_FOPS is not set
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set
#
# Frame buffer hardware drivers
#
# CONFIG_FB_S1D13XXX is not set
CONFIG_FB_PXA=y
# CONFIG_FB_PXA_PARAMETERS is not set
# CONFIG_FB_MBX is not set
# CONFIG_FB_VIRTUAL is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
#
# Sound
#
CONFIG_SOUND=m
#
# Advanced Linux Sound Architecture
#
CONFIG_SND=m
CONFIG_SND_TIMER=m
CONFIG_SND_PCM=m
# CONFIG_SND_SEQUENCER is not set
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=m
CONFIG_SND_PCM_OSS=m
CONFIG_SND_PCM_OSS_PLUGINS=y
# CONFIG_SND_DYNAMIC_MINORS is not set
CONFIG_SND_SUPPORT_OLD_API=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
#
# Generic devices
#
CONFIG_SND_AC97_CODEC=m
# CONFIG_SND_DUMMY is not set
# CONFIG_SND_MTPAV is not set
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
#
# ALSA ARM devices
#
CONFIG_SND_PXA2XX_PCM=m
CONFIG_SND_PXA2XX_AC97=m
#
# USB devices
#
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_CAIAQ is not set
#
# System on Chip audio support
#
# CONFIG_SND_SOC is not set
#
# Open Sound System
#
# CONFIG_SOUND_PRIME is not set
CONFIG_AC97_BUS=m
#
# HID Devices
#
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
#
# USB Input Devices
#
CONFIG_USB_HID=y
# CONFIG_USB_HIDINPUT_POWERBOOK is not set
# CONFIG_HID_FF is not set
# CONFIG_USB_HIDDEV is not set
#
# USB support
#
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
# CONFIG_USB_ARCH_HAS_EHCI is not set
CONFIG_USB=y
# CONFIG_USB_DEBUG is not set
#
# Miscellaneous USB options
#
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_SUSPEND is not set
# CONFIG_USB_OTG is not set
#
# USB Host Controller Drivers
#
# CONFIG_USB_ISP116X_HCD is not set
CONFIG_USB_OHCI_HCD=y
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_SL811_HCD is not set
#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# may also be needed; see USB_STORAGE Help for more information
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_LIBUSUAL is not set
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_MON is not set
#
# USB port drivers
#
#
# USB Serial Converter support
#
# CONFIG_USB_SERIAL is not set
#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_AUERSWALD is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_PHIDGET is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
#
# USB DSL modem support
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
CONFIG_MMC=m
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_UNSAFE_RESUME is not set
#
# MMC/SD Card Drivers
#
CONFIG_MMC_BLOCK=m
#
# MMC/SD Host Controller Drivers
#
CONFIG_MMC_PXA=m
#
# Real Time Clock
#
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=m
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
#
# SPI RTC drivers
#
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_M48T86 is not set
CONFIG_RTC_DRV_V3020=m
#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_SA1100=m
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_XATTR=y
# CONFIG_EXT3_FS_POSIX_ACL is not set
# CONFIG_EXT3_FS_SECURITY is not set
# CONFIG_EXT4DEV_FS is not set
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
CONFIG_JFFS2_SUMMARY=y
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_BIND34 is not set
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=y
# CONFIG_SMB_NLS_DEFAULT is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_UTF8=y
#
# Distributed Lock Manager
#
# CONFIG_DLM is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
# CONFIG_DETECT_SOFTLOCKUP is not set
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
CONFIG_FRAME_POINTER=y
CONFIG_FORCED_INLINING=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y
# CONFIG_DEBUG_ICEDCC is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=m
CONFIG_CRYPTO_BLKCIPHER=m
CONFIG_CRYPTO_MANAGER=m
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_GF128MUL is not set
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_CBC=m
CONFIG_CRYPTO_PCBC=m
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_SERPENT is not set
CONFIG_CRYPTO_AES=m
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_TEA is not set
CONFIG_CRYPTO_ARC4=m
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
#
# Hardware crypto devices
#
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
arch/arm/configs/cm_x270_defconfig → arch/arm/configs/xm_x270_defconfig
浏览文件 @ fdc614e8
# #
# Automatically generated make config: don't edit # Automatically generated make config: don't edit
# Linux kernel version: 2.6.22 # Linux kernel version: 2.6.25
# Wed Jul 18 14:11:48 2007 # Sun May 11 15:12:52 2008
# #
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME=y
# CONFIG_GENERIC_CLOCKEVENTS is not set CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_MMU=y CONFIG_MMU=y
# CONFIG_NO_IOPORT is not set # CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_HARDIRQS=y
...@@ -21,21 +21,18 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y ...@@ -21,21 +21,18 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U64 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_SUPPORTS_AOUT=y
CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA=y
CONFIG_ARCH_MTD_XIP=y CONFIG_ARCH_MTD_XIP=y
CONFIG_VECTORS_BASE=0xffff0000 CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
# #
# Code maturity level options # General setup
# #
CONFIG_EXPERIMENTAL=y CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set # CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SWAP=y CONFIG_SWAP=y
...@@ -44,13 +41,20 @@ CONFIG_SYSVIPC_SYSCTL=y ...@@ -44,13 +41,20 @@ CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set # CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set # CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
# CONFIG_AUDIT is not set # CONFIG_AUDIT is not set
CONFIG_IKCONFIG=y CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_GROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
# CONFIG_RT_GROUP_SCHED is not set
CONFIG_USER_SCHED=y
# CONFIG_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set # CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
CONFIG_BLK_DEV_INITRD=y CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="" CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y
...@@ -58,6 +62,7 @@ CONFIG_SYSCTL=y ...@@ -58,6 +62,7 @@ CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y CONFIG_EMBEDDED=y
CONFIG_UID16=y CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y CONFIG_SYSCTL_SYSCALL=y
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_KALLSYMS=y CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set
...@@ -65,24 +70,34 @@ CONFIG_HOTPLUG=y ...@@ -65,24 +70,34 @@ CONFIG_HOTPLUG=y
CONFIG_PRINTK=y CONFIG_PRINTK=y
CONFIG_BUG=y CONFIG_BUG=y
CONFIG_ELF_CORE=y CONFIG_ELF_CORE=y
# CONFIG_COMPAT_BRK is not set
CONFIG_BASE_FULL=y CONFIG_BASE_FULL=y
CONFIG_FUTEX=y CONFIG_FUTEX=y
CONFIG_ANON_INODES=y CONFIG_ANON_INODES=y
# CONFIG_EPOLL is not set CONFIG_EPOLL=y
# CONFIG_SIGNALFD is not set CONFIG_SIGNALFD=y
# CONFIG_TIMERFD is not set CONFIG_TIMERFD=y
# CONFIG_EVENTFD is not set CONFIG_EVENTFD=y
CONFIG_SHMEM=y CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y # CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_SLAB=y # CONFIG_SLUB_DEBUG is not set
# CONFIG_SLUB is not set # CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set # CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
# CONFIG_HAVE_DMA_ATTRS is not set
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_RT_MUTEXES=y CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set # CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0 CONFIG_BASE_SMALL=0
CONFIG_MODULES=y CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set # CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y CONFIG_KMOD=y
...@@ -99,11 +114,12 @@ CONFIG_IOSCHED_NOOP=y ...@@ -99,11 +114,12 @@ CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set # CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_CLASSIC_RCU=y
# #
# System Type # System Type
...@@ -131,6 +147,8 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" ...@@ -131,6 +147,8 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# CONFIG_ARCH_L7200 is not set # CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PNX4008 is not set
CONFIG_ARCH_PXA=y CONFIG_ARCH_PXA=y
# CONFIG_ARCH_RPC is not set # CONFIG_ARCH_RPC is not set
...@@ -140,19 +158,41 @@ CONFIG_ARCH_PXA=y ...@@ -140,19 +158,41 @@ CONFIG_ARCH_PXA=y
# CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set # CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_MSM7X00A is not set
CONFIG_DMABOUNCE=y CONFIG_DMABOUNCE=y
# #
# Intel PXA2xx Implementations # Intel PXA2xx/PXA3xx Implementations
# #
#
# Select target boards
#
# CONFIG_ARCH_GUMSTIX is not set
# CONFIG_ARCH_LUBBOCK is not set # CONFIG_ARCH_LUBBOCK is not set
# CONFIG_MACH_LOGICPD_PXA270 is not set # CONFIG_MACH_LOGICPD_PXA270 is not set
# CONFIG_MACH_MAINSTONE is not set # CONFIG_MACH_MAINSTONE is not set
# CONFIG_ARCH_PXA_IDP is not set # CONFIG_ARCH_PXA_IDP is not set
# CONFIG_PXA_SHARPSL is not set # CONFIG_PXA_SHARPSL is not set
# CONFIG_ARCH_PXA_ESERIES is not set
# CONFIG_MACH_TRIZEPS4 is not set # CONFIG_MACH_TRIZEPS4 is not set
CONFIG_MACH_EM_X270=y
# CONFIG_MACH_COLIBRI is not set
# CONFIG_MACH_ZYLONITE is not set
# CONFIG_MACH_LITTLETON is not set
CONFIG_MACH_ARMCORE=y CONFIG_MACH_ARMCORE=y
# CONFIG_MACH_MAGICIAN is not set
# CONFIG_MACH_PCM027 is not set
CONFIG_PXA27x=y CONFIG_PXA27x=y
# CONFIG_PXA_PWM is not set
#
# Boot options
#
#
# Power management
#
# #
# Processor Type # Processor Type
...@@ -161,6 +201,7 @@ CONFIG_CPU_32=y ...@@ -161,6 +201,7 @@ CONFIG_CPU_32=y
CONFIG_CPU_XSCALE=y CONFIG_CPU_XSCALE=y
CONFIG_CPU_32v5=y CONFIG_CPU_32v5=y
CONFIG_CPU_ABRT_EV5T=y CONFIG_CPU_ABRT_EV5T=y
CONFIG_CPU_PABRT_NOIFAR=y
CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_TLB_V4WBI=y CONFIG_CPU_TLB_V4WBI=y
CONFIG_CPU_CP15=y CONFIG_CPU_CP15=y
...@@ -182,21 +223,41 @@ CONFIG_PCI=y ...@@ -182,21 +223,41 @@ CONFIG_PCI=y
CONFIG_PCI_SYSCALL=y CONFIG_PCI_SYSCALL=y
CONFIG_PCI_HOST_ITE8152=y CONFIG_PCI_HOST_ITE8152=y
# CONFIG_ARCH_SUPPORTS_MSI is not set # CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_PCI_LEGACY=y
# CONFIG_PCI_DEBUG is not set # CONFIG_PCI_DEBUG is not set
CONFIG_PCCARD=m
# CONFIG_PCMCIA_DEBUG is not set
CONFIG_PCMCIA=m
CONFIG_PCMCIA_LOAD_CIS=y
CONFIG_PCMCIA_IOCTL=y
CONFIG_CARDBUS=y
# #
# PCCARD (PCMCIA/CardBus) support # PC-card bridges
# #
# CONFIG_PCCARD is not set CONFIG_YENTA=m
# CONFIG_YENTA_O2 is not set
# CONFIG_YENTA_RICOH is not set
CONFIG_YENTA_TI=y
# CONFIG_YENTA_ENE_TUNE is not set
# CONFIG_YENTA_TOSHIBA is not set
# CONFIG_PD6729 is not set
# CONFIG_I82092 is not set
CONFIG_PCMCIA_PXA2XX=m
CONFIG_PCCARD_NONSTATIC=m
# #
# Kernel Features # Kernel Features
# #
# CONFIG_TICK_ONESHOT is not set CONFIG_TICK_ONESHOT=y
# CONFIG_PREEMPT is not set CONFIG_NO_HZ=y
# CONFIG_NO_IDLE_HZ is not set # CONFIG_NO_IDLE_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
# CONFIG_PREEMPT is not set
CONFIG_HZ=100 CONFIG_HZ=100
# CONFIG_AEABI is not set CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
CONFIG_SELECT_MEMORY_MODEL=y CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM_MANUAL=y
...@@ -205,6 +266,8 @@ CONFIG_FLATMEM_MANUAL=y ...@@ -205,6 +266,8 @@ CONFIG_FLATMEM_MANUAL=y
CONFIG_FLATMEM=y CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set # CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4096 CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set # CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1 CONFIG_ZONE_DMA_FLAG=1
...@@ -217,10 +280,15 @@ CONFIG_ALIGNMENT_TRAP=y ...@@ -217,10 +280,15 @@ CONFIG_ALIGNMENT_TRAP=y
# #
CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="" CONFIG_CMDLINE="root=1f03 mem=32M"
# CONFIG_XIP_KERNEL is not set # CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set # CONFIG_KEXEC is not set
#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
# #
# Floating point emulation # Floating point emulation
# #
...@@ -238,16 +306,17 @@ CONFIG_FPE_NWFPE=y ...@@ -238,16 +306,17 @@ CONFIG_FPE_NWFPE=y
CONFIG_BINFMT_ELF=y CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_AOUT is not set # CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set # CONFIG_BINFMT_MISC is not set
# CONFIG_ARTHUR is not set
# #
# Power management options # Power management options
# #
CONFIG_PM=y CONFIG_PM=y
# CONFIG_PM_LEGACY is not set
# CONFIG_PM_DEBUG is not set # CONFIG_PM_DEBUG is not set
# CONFIG_PM_SYSFS_DEPRECATED is not set CONFIG_PM_SLEEP=y
# CONFIG_APM_EMULATION is not set CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_APM_EMULATION=m
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# #
# Networking # Networking
...@@ -258,15 +327,16 @@ CONFIG_NET=y ...@@ -258,15 +327,16 @@ CONFIG_NET=y
# Networking options # Networking options
# #
CONFIG_PACKET=y CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set CONFIG_PACKET_MMAP=y
CONFIG_UNIX=y CONFIG_UNIX=y
CONFIG_XFRM=y CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set # CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
# CONFIG_NET_KEY is not set # CONFIG_NET_KEY is not set
CONFIG_INET=y CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set # CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y CONFIG_IP_PNP=y
...@@ -275,6 +345,7 @@ CONFIG_IP_PNP_BOOTP=y ...@@ -275,6 +345,7 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set # CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set # CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set # CONFIG_NET_IPGRE is not set
# CONFIG_IP_MROUTE is not set
# CONFIG_ARPD is not set # CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set # CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set # CONFIG_INET_AH is not set
...@@ -285,15 +356,13 @@ CONFIG_IP_PNP_BOOTP=y ...@@ -285,15 +356,13 @@ CONFIG_IP_PNP_BOOTP=y
CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y CONFIG_INET_XFRM_MODE_BEET=y
CONFIG_INET_DIAG=y # CONFIG_INET_LRO is not set
CONFIG_INET_TCP_DIAG=y # CONFIG_INET_DIAG is not set
# CONFIG_TCP_CONG_ADVANCED is not set # CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set # CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set # CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set # CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set # CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set # CONFIG_IP_DCCP is not set
...@@ -310,10 +379,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" ...@@ -310,10 +379,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_LAPB is not set # CONFIG_LAPB is not set
# CONFIG_ECONET is not set # CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set # CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set # CONFIG_NET_SCHED is not set
# #
...@@ -321,8 +386,33 @@ CONFIG_DEFAULT_TCP_CONG="cubic" ...@@ -321,8 +386,33 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# #
# CONFIG_NET_PKTGEN is not set # CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set # CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set # CONFIG_IRDA is not set
# CONFIG_BT is not set CONFIG_BT=m
CONFIG_BT_L2CAP=m
CONFIG_BT_SCO=m
CONFIG_BT_RFCOMM=m
# CONFIG_BT_RFCOMM_TTY is not set
CONFIG_BT_BNEP=m
# CONFIG_BT_BNEP_MC_FILTER is not set
# CONFIG_BT_BNEP_PROTO_FILTER is not set
CONFIG_BT_HIDP=m
#
# Bluetooth device drivers
#
CONFIG_BT_HCIUSB=m
CONFIG_BT_HCIUSB_SCO=y
# CONFIG_BT_HCIBTSDIO is not set
# CONFIG_BT_HCIUART is not set
# CONFIG_BT_HCIBCM203X is not set
# CONFIG_BT_HCIBPA10X is not set
# CONFIG_BT_HCIBFUSB is not set
# CONFIG_BT_HCIDTL1 is not set
# CONFIG_BT_HCIBT3C is not set
# CONFIG_BT_HCIBLUECARD is not set
# CONFIG_BT_HCIBTUART is not set
# CONFIG_BT_HCIVHCI is not set
# CONFIG_AF_RXRPC is not set # CONFIG_AF_RXRPC is not set
# #
...@@ -331,12 +421,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" ...@@ -331,12 +421,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_CFG80211 is not set # CONFIG_CFG80211 is not set
CONFIG_WIRELESS_EXT=y CONFIG_WIRELESS_EXT=y
# CONFIG_MAC80211 is not set # CONFIG_MAC80211 is not set
CONFIG_IEEE80211=m # CONFIG_IEEE80211 is not set
# CONFIG_IEEE80211_DEBUG is not set
CONFIG_IEEE80211_CRYPT_WEP=m
CONFIG_IEEE80211_CRYPT_CCMP=m
# CONFIG_IEEE80211_CRYPT_TKIP is not set
# CONFIG_IEEE80211_SOFTMAC is not set
# CONFIG_RFKILL is not set # CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set # CONFIG_NET_9P is not set
...@@ -347,38 +432,47 @@ CONFIG_IEEE80211_CRYPT_CCMP=m ...@@ -347,38 +432,47 @@ CONFIG_IEEE80211_CRYPT_CCMP=m
# #
# Generic Driver Options # Generic Driver Options
# #
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y CONFIG_FW_LOADER=m
# CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set # CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set # CONFIG_CONNECTOR is not set
CONFIG_MTD=m CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set # CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set # CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_AFS_PARTS is not set # CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_AR7_PARTS is not set
# #
# User Modules And Translation Layers # User Modules And Translation Layers
# #
CONFIG_MTD_CHAR=m CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=m CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=m CONFIG_MTD_BLOCK=y
# CONFIG_MTD_BLOCK_RO is not set
# CONFIG_FTL is not set # CONFIG_FTL is not set
# CONFIG_NFTL is not set # CONFIG_NFTL is not set
# CONFIG_INFTL is not set # CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set # CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set # CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
# #
# RAM/ROM/Flash chip drivers # RAM/ROM/Flash chip drivers
# #
# CONFIG_MTD_CFI is not set CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_NOSWAP=y
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_GEOMETRY is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y CONFIG_MTD_MAP_BANK_WIDTH_4=y
...@@ -389,15 +483,29 @@ CONFIG_MTD_CFI_I1=y ...@@ -389,15 +483,29 @@ CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set # CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_OTP is not set
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set # CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set # CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set # CONFIG_MTD_ABSENT is not set
# CONFIG_MTD_XIP is not set
# #
# Mapping drivers for chip access # Mapping drivers for chip access
# #
# CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0x0
CONFIG_MTD_PHYSMAP_LEN=0x400000
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
CONFIG_MTD_PXA2XX=y
# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_IMPA7 is not set
# CONFIG_MTD_SHARP_SL is not set # CONFIG_MTD_SHARP_SL is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set # CONFIG_MTD_PLATRAM is not set
# #
...@@ -415,18 +523,19 @@ CONFIG_MTD_CFI_I2=y ...@@ -415,18 +523,19 @@ CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set # CONFIG_MTD_DOC2001PLUS is not set
CONFIG_MTD_NAND=m CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_VERIFY_WRITE is not set # CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_NAND_ECC_SMC is not set # CONFIG_MTD_NAND_ECC_SMC is not set
# CONFIG_MTD_NAND_MUSEUM_IDS is not set # CONFIG_MTD_NAND_MUSEUM_IDS is not set
# CONFIG_MTD_NAND_H1900 is not set # CONFIG_MTD_NAND_H1900 is not set
CONFIG_MTD_NAND_IDS=m CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_NAND_SHARPSL is not set # CONFIG_MTD_NAND_SHARPSL is not set
# CONFIG_MTD_NAND_CAFE is not set # CONFIG_MTD_NAND_CAFE is not set
CONFIG_MTD_NAND_CM_X270=m CONFIG_MTD_NAND_CM_X270=y
# CONFIG_MTD_NAND_NANDSIM is not set # CONFIG_MTD_NAND_NANDSIM is not set
# CONFIG_MTD_NAND_PLATFORM is not set CONFIG_MTD_NAND_PLATFORM=y
# CONFIG_MTD_ALAUDA is not set
# CONFIG_MTD_ONENAND is not set # CONFIG_MTD_ONENAND is not set
# #
...@@ -447,36 +556,13 @@ CONFIG_BLK_DEV_LOOP=y ...@@ -447,36 +556,13 @@ CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_UB is not set # CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=12000 CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set # CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set # CONFIG_ATA_OVER_ETH is not set
CONFIG_IDE=m # CONFIG_MISC_DEVICES is not set
CONFIG_IDE_MAX_HWIFS=4 CONFIG_HAVE_IDE=y
CONFIG_BLK_DEV_IDE=m # CONFIG_IDE is not set
#
# Please see Documentation/ide.txt for help/info on IDE drives
#
# CONFIG_BLK_DEV_IDE_SATA is not set
CONFIG_BLK_DEV_IDEDISK=m
# CONFIG_IDEDISK_MULTI_MODE is not set
CONFIG_BLK_DEV_IDECD=m
# CONFIG_BLK_DEV_IDETAPE is not set
# CONFIG_BLK_DEV_IDEFLOPPY is not set
# CONFIG_BLK_DEV_IDESCSI is not set
# CONFIG_IDE_TASK_IOCTL is not set
CONFIG_IDE_PROC_FS=y
#
# IDE chipset support/bugfixes
#
# CONFIG_IDE_GENERIC is not set
# CONFIG_BLK_DEV_IDEPCI is not set
# CONFIG_IDEPCI_PCIBUS_ORDER is not set
# CONFIG_IDE_ARM is not set
# CONFIG_BLK_DEV_IDEDMA is not set
# CONFIG_BLK_DEV_HD is not set
# #
# SCSI device support # SCSI device support
...@@ -486,7 +572,7 @@ CONFIG_SCSI=y ...@@ -486,7 +572,7 @@ CONFIG_SCSI=y
CONFIG_SCSI_DMA=y CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set # CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set # CONFIG_SCSI_NETLINK is not set
# CONFIG_SCSI_PROC_FS is not set CONFIG_SCSI_PROC_FS=y
# #
# SCSI support type (disk, tape, CD-ROM) # SCSI support type (disk, tape, CD-ROM)
...@@ -513,12 +599,9 @@ CONFIG_SCSI_WAIT_SCAN=m ...@@ -513,12 +599,9 @@ CONFIG_SCSI_WAIT_SCAN=m
# CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# CONFIG_SCSI_LOWLEVEL=y
# SCSI low-level drivers
#
# CONFIG_ISCSI_TCP is not set # CONFIG_ISCSI_TCP is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_3W_9XXX is not set # CONFIG_SCSI_3W_9XXX is not set
...@@ -529,6 +612,7 @@ CONFIG_SCSI_WAIT_SCAN=m ...@@ -529,6 +612,7 @@ CONFIG_SCSI_WAIT_SCAN=m
# CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set # CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set # CONFIG_SCSI_ARCMSR is not set
# CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set # CONFIG_MEGARAID_LEGACY is not set
...@@ -539,8 +623,10 @@ CONFIG_SCSI_WAIT_SCAN=m ...@@ -539,8 +623,10 @@ CONFIG_SCSI_WAIT_SCAN=m
# CONFIG_SCSI_IPS is not set # CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set # CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_STEX is not set # CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set # CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_FC is not set # CONFIG_SCSI_QLA_FC is not set
# CONFIG_SCSI_QLA_ISCSI is not set # CONFIG_SCSI_QLA_ISCSI is not set
...@@ -550,16 +636,69 @@ CONFIG_SCSI_WAIT_SCAN=m ...@@ -550,16 +636,69 @@ CONFIG_SCSI_WAIT_SCAN=m
# CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_NSP32 is not set
# CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_SRP is not set # CONFIG_SCSI_SRP is not set
# CONFIG_ATA is not set # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
CONFIG_ATA=m
# CONFIG_ATA_NONSTANDARD is not set
# CONFIG_SATA_PMP is not set
# CONFIG_SATA_AHCI is not set
# CONFIG_SATA_SIL24 is not set
CONFIG_ATA_SFF=y
# CONFIG_SATA_SVW is not set
# CONFIG_ATA_PIIX is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_NV is not set
# CONFIG_PDC_ADMA is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_PROMISE is not set
# CONFIG_SATA_SX4 is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_ULI is not set
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set
# CONFIG_SATA_INIC162X is not set
# CONFIG_PATA_ALI is not set
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CS5520 is not set
# CONFIG_PATA_CS5530 is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_ATA_GENERIC is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_OPTIDMA is not set
CONFIG_PATA_PCMCIA=m
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
# CONFIG_PATA_RZ1000 is not set
# CONFIG_PATA_SC1200 is not set
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_SIL680 is not set
# CONFIG_PATA_SIS is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set
# CONFIG_PATA_PLATFORM is not set
# CONFIG_MD is not set # CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set # CONFIG_FUSION is not set
# CONFIG_FUSION_SPI is not set
# CONFIG_FUSION_FC is not set
# CONFIG_FUSION_SAS is not set
# #
# IEEE 1394 (FireWire) support # IEEE 1394 (FireWire) support
...@@ -574,6 +713,7 @@ CONFIG_NETDEVICES=y ...@@ -574,6 +713,7 @@ CONFIG_NETDEVICES=y
# CONFIG_MACVLAN is not set # CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set # CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set # CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_ARCNET is not set # CONFIG_ARCNET is not set
# CONFIG_PHYLIB is not set # CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y CONFIG_NET_ETHERNET=y
...@@ -585,64 +725,65 @@ CONFIG_MII=y ...@@ -585,64 +725,65 @@ CONFIG_MII=y
# CONFIG_NET_VENDOR_3COM is not set # CONFIG_NET_VENDOR_3COM is not set
# CONFIG_SMC91X is not set # CONFIG_SMC91X is not set
CONFIG_DM9000=y CONFIG_DM9000=y
CONFIG_DM9000_DEBUGLEVEL=1
# CONFIG_SMC911X is not set # CONFIG_SMC911X is not set
# CONFIG_NET_TULIP is not set # CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set # CONFIG_HP100 is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
CONFIG_NET_PCI=y CONFIG_NET_PCI=y
# CONFIG_PCNET32 is not set # CONFIG_PCNET32 is not set
# CONFIG_AMD8111_ETH is not set # CONFIG_AMD8111_ETH is not set
# CONFIG_ADAPTEC_STARFIRE is not set # CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_B44 is not set # CONFIG_B44 is not set
# CONFIG_FORCEDETH is not set # CONFIG_FORCEDETH is not set
# CONFIG_DGRS is not set
# CONFIG_EEPRO100 is not set # CONFIG_EEPRO100 is not set
# CONFIG_E100 is not set # CONFIG_E100 is not set
# CONFIG_FEALNX is not set # CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set # CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set # CONFIG_NE2K_PCI is not set
# CONFIG_8139CP is not set # CONFIG_8139CP is not set
CONFIG_8139TOO=m CONFIG_8139TOO=y
# CONFIG_8139TOO_PIO is not set # CONFIG_8139TOO_PIO is not set
# CONFIG_8139TOO_TUNE_TWISTER is not set # CONFIG_8139TOO_TUNE_TWISTER is not set
# CONFIG_8139TOO_8129 is not set # CONFIG_8139TOO_8129 is not set
# CONFIG_8139_OLD_RX_RESET is not set # CONFIG_8139_OLD_RX_RESET is not set
# CONFIG_R6040 is not set
# CONFIG_SIS900 is not set # CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set # CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set # CONFIG_SUNDANCE is not set
# CONFIG_TLAN is not set # CONFIG_TLAN is not set
# CONFIG_VIA_RHINE is not set # CONFIG_VIA_RHINE is not set
# CONFIG_SC92031 is not set # CONFIG_SC92031 is not set
CONFIG_NETDEV_1000=y # CONFIG_NETDEV_1000 is not set
# CONFIG_ACENIC is not set # CONFIG_NETDEV_10000 is not set
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SIS190 is not set
# CONFIG_SKGE is not set
# CONFIG_SKY2 is not set
# CONFIG_VIA_VELOCITY is not set
# CONFIG_TIGON3 is not set
# CONFIG_BNX2 is not set
# CONFIG_QLA3XXX is not set
# CONFIG_ATL1 is not set
CONFIG_NETDEV_10000=y
# CONFIG_CHELSIO_T1 is not set
# CONFIG_CHELSIO_T3 is not set
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
# CONFIG_MYRI10GE is not set
# CONFIG_NETXEN_NIC is not set
# CONFIG_MLX4_CORE is not set
# CONFIG_TR is not set # CONFIG_TR is not set
# #
# Wireless LAN # Wireless LAN
# #
# CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set CONFIG_WLAN_80211=y
# CONFIG_PCMCIA_RAYCS is not set
# CONFIG_IPW2100 is not set
# CONFIG_IPW2200 is not set
CONFIG_LIBERTAS=m
# CONFIG_LIBERTAS_USB is not set
# CONFIG_LIBERTAS_CS is not set
CONFIG_LIBERTAS_SDIO=m
# CONFIG_LIBERTAS_DEBUG is not set
# CONFIG_HERMES is not set
# CONFIG_ATMEL is not set
# CONFIG_AIRO_CS is not set
# CONFIG_PCMCIA_WL3501 is not set
# CONFIG_PRISM54 is not set
# CONFIG_USB_ZD1201 is not set
# CONFIG_USB_NET_RNDIS_WLAN is not set
# CONFIG_IWLWIFI is not set
# CONFIG_IWLWIFI_LEDS is not set
# CONFIG_HOSTAP is not set
# #
# USB Network Adapters # USB Network Adapters
...@@ -651,15 +792,24 @@ CONFIG_NETDEV_10000=y ...@@ -651,15 +792,24 @@ CONFIG_NETDEV_10000=y
# CONFIG_USB_KAWETH is not set # CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set # CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set # CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET_MII is not set
# CONFIG_USB_USBNET is not set # CONFIG_USB_USBNET is not set
# CONFIG_NET_PCMCIA is not set
# CONFIG_WAN is not set # CONFIG_WAN is not set
# CONFIG_FDDI is not set # CONFIG_FDDI is not set
# CONFIG_HIPPI is not set # CONFIG_HIPPI is not set
# CONFIG_PPP is not set CONFIG_PPP=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_ASYNC=m
# CONFIG_PPP_SYNC_TTY is not set
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_BSDCOMP=m
# CONFIG_PPP_MPPE is not set
# CONFIG_PPPOE is not set
# CONFIG_PPPOL2TP is not set
# CONFIG_SLIP is not set # CONFIG_SLIP is not set
CONFIG_SLHC=m
# CONFIG_NET_FC is not set # CONFIG_NET_FC is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set # CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set # CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_NET_POLL_CONTROLLER is not set
...@@ -675,20 +825,32 @@ CONFIG_INPUT=y ...@@ -675,20 +825,32 @@ CONFIG_INPUT=y
# #
# Userland interfaces # Userland interfaces
# #
# CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set # CONFIG_INPUT_EVBUG is not set
# CONFIG_INPUT_APMPOWER is not set
# #
# Input Device Drivers # Input Device Drivers
# #
# CONFIG_INPUT_KEYBOARD is not set CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
CONFIG_KEYBOARD_PXA27x=m
# CONFIG_KEYBOARD_GPIO is not set
# CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set # CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set
...@@ -697,13 +859,22 @@ CONFIG_INPUT_TOUCHSCREEN=y ...@@ -697,13 +859,22 @@ CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
CONFIG_TOUCHSCREEN_UCB1400=m CONFIG_TOUCHSCREEN_UCB1400=m
CONFIG_TOUCHSCREEN_WM97XX=m
# CONFIG_TOUCHSCREEN_WM9705 is not set
CONFIG_TOUCHSCREEN_WM9712=y
# CONFIG_TOUCHSCREEN_WM9713 is not set
# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_INPUT_MISC is not set # CONFIG_INPUT_MISC is not set
# #
# Hardware I/O ports # Hardware I/O ports
# #
# CONFIG_SERIO is not set CONFIG_SERIO=y
# CONFIG_SERIO_SERPORT is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set # CONFIG_GAMEPORT is not set
# #
...@@ -713,7 +884,9 @@ CONFIG_VT=y ...@@ -713,7 +884,9 @@ CONFIG_VT=y
CONFIG_VT_CONSOLE=y CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set # CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_NOZOMI is not set
# #
# Serial drivers # Serial drivers
...@@ -730,83 +903,141 @@ CONFIG_SERIAL_CORE_CONSOLE=y ...@@ -730,83 +903,141 @@ CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set # CONFIG_SERIAL_JSM is not set
CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256 CONFIG_LEGACY_PTY_COUNT=16
# CONFIG_IPMI_HANDLER is not set # CONFIG_IPMI_HANDLER is not set
# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set
CONFIG_HW_RANDOM=m
# CONFIG_NVRAM is not set # CONFIG_NVRAM is not set
# CONFIG_R3964 is not set # CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set # CONFIG_APPLICOM is not set
# CONFIG_DRM is not set
#
# PCMCIA character devices
#
# CONFIG_SYNCLINK_CS is not set
# CONFIG_CARDMAN_4000 is not set
# CONFIG_CARDMAN_4040 is not set
# CONFIG_IPWIRELESS is not set
# CONFIG_RAW_DRIVER is not set # CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set # CONFIG_TCG_TPM is not set
CONFIG_DEVPORT=y CONFIG_DEVPORT=y
# CONFIG_I2C is not set CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=m
#
# I2C Hardware Bus support
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_I810 is not set
CONFIG_I2C_PXA=y
# CONFIG_I2C_PXA_SLAVE is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_PROSAVAGE is not set
# CONFIG_I2C_SAVAGE4 is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_TINY_USB is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set
# CONFIG_I2C_VOODOO3 is not set
# CONFIG_I2C_PCA_PLATFORM is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_TPS65010 is not set
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
# CONFIG_SPI is not set
CONFIG_HAVE_GPIO_LIB=y
# #
# SPI support # GPIO Support
# #
# CONFIG_SPI is not set # CONFIG_DEBUG_GPIO is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_HWMON is not set
CONFIG_MISC_DEVICES=y
# CONFIG_PHANTOM is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
# #
# Multifunction device drivers # I2C GPIO expanders:
# #
# CONFIG_MFD_SM501 is not set # CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
# #
# LED devices # SPI GPIO expanders:
# #
CONFIG_NEW_LEDS=y # CONFIG_W1 is not set
CONFIG_LEDS_CLASS=y # CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_WATCHDOG is not set
# #
# LED drivers # Sonics Silicon Backplane
# #
CONFIG_LEDS_CM_X270=y CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
# #
# LED Triggers # Multifunction device drivers
# #
CONFIG_LEDS_TRIGGERS=y # CONFIG_MFD_SM501 is not set
# CONFIG_LEDS_TRIGGER_TIMER is not set # CONFIG_MFD_ASIC3 is not set
# CONFIG_LEDS_TRIGGER_IDE_DISK is not set # CONFIG_HTC_EGPIO is not set
CONFIG_LEDS_TRIGGER_HEARTBEAT=y # CONFIG_HTC_PASIC3 is not set
# #
# Multimedia devices # Multimedia devices
# #
#
# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set # CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set # CONFIG_DVB_CORE is not set
CONFIG_DAB=y
# CONFIG_USB_DABUSB is not set
# #
# Graphics support # Multimedia drivers
# #
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # CONFIG_DAB is not set
# #
# Display device support # Graphics support
# #
# CONFIG_DISPLAY_SUPPORT is not set # CONFIG_DRM is not set
# CONFIG_VGASTATE is not set # CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set # CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set # CONFIG_FB_DDC is not set
CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set # CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set # CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set # CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_SYS_FOPS is not set # CONFIG_FB_SYS_FOPS is not set
CONFIG_FB_DEFERRED_IO=y CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set # CONFIG_FB_SVGALIB is not set
...@@ -842,9 +1073,17 @@ CONFIG_FB_DEFERRED_IO=y ...@@ -842,9 +1073,17 @@ CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_ARK is not set # CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set # CONFIG_FB_PM3 is not set
CONFIG_FB_PXA=y CONFIG_FB_PXA=y
# CONFIG_FB_PXA_PARAMETERS is not set # CONFIG_FB_PXA_SMARTPANEL is not set
CONFIG_FB_PXA_PARAMETERS=y
CONFIG_FB_MBX=m CONFIG_FB_MBX=m
# CONFIG_FB_AM200EPD is not set
# CONFIG_FB_VIRTUAL is not set # CONFIG_FB_VIRTUAL is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
# #
# Console display driver support # Console display driver support
...@@ -904,10 +1143,12 @@ CONFIG_SND_AC97_CODEC=m ...@@ -904,10 +1143,12 @@ CONFIG_SND_AC97_CODEC=m
# CONFIG_SND_AU8810 is not set # CONFIG_SND_AU8810 is not set
# CONFIG_SND_AU8820 is not set # CONFIG_SND_AU8820 is not set
# CONFIG_SND_AU8830 is not set # CONFIG_SND_AU8830 is not set
# CONFIG_SND_AW2 is not set
# CONFIG_SND_AZT3328 is not set # CONFIG_SND_AZT3328 is not set
# CONFIG_SND_BT87X is not set # CONFIG_SND_BT87X is not set
# CONFIG_SND_CA0106 is not set # CONFIG_SND_CA0106 is not set
# CONFIG_SND_CMIPCI is not set # CONFIG_SND_CMIPCI is not set
# CONFIG_SND_OXYGEN is not set
# CONFIG_SND_CS4281 is not set # CONFIG_SND_CS4281 is not set
# CONFIG_SND_CS46XX is not set # CONFIG_SND_CS46XX is not set
# CONFIG_SND_DARLA20 is not set # CONFIG_SND_DARLA20 is not set
...@@ -932,6 +1173,7 @@ CONFIG_SND_AC97_CODEC=m ...@@ -932,6 +1173,7 @@ CONFIG_SND_AC97_CODEC=m
# CONFIG_SND_HDA_INTEL is not set # CONFIG_SND_HDA_INTEL is not set
# CONFIG_SND_HDSP is not set # CONFIG_SND_HDSP is not set
# CONFIG_SND_HDSPM is not set # CONFIG_SND_HDSPM is not set
# CONFIG_SND_HIFIER is not set
# CONFIG_SND_ICE1712 is not set # CONFIG_SND_ICE1712 is not set
# CONFIG_SND_ICE1724 is not set # CONFIG_SND_ICE1724 is not set
# CONFIG_SND_INTEL8X0 is not set # CONFIG_SND_INTEL8X0 is not set
...@@ -949,6 +1191,7 @@ CONFIG_SND_AC97_CODEC=m ...@@ -949,6 +1191,7 @@ CONFIG_SND_AC97_CODEC=m
# CONFIG_SND_TRIDENT is not set # CONFIG_SND_TRIDENT is not set
# CONFIG_SND_VIA82XX is not set # CONFIG_SND_VIA82XX is not set
# CONFIG_SND_VIA82XX_MODEM is not set # CONFIG_SND_VIA82XX_MODEM is not set
# CONFIG_SND_VIRTUOSO is not set
# CONFIG_SND_VX222 is not set # CONFIG_SND_VX222 is not set
# CONFIG_SND_YMFPCI is not set # CONFIG_SND_YMFPCI is not set
# CONFIG_SND_AC97_POWER_SAVE is not set # CONFIG_SND_AC97_POWER_SAVE is not set
...@@ -965,11 +1208,25 @@ CONFIG_SND_PXA2XX_AC97=m ...@@ -965,11 +1208,25 @@ CONFIG_SND_PXA2XX_AC97=m
# CONFIG_SND_USB_AUDIO is not set # CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_CAIAQ is not set # CONFIG_SND_USB_CAIAQ is not set
#
# PCMCIA devices
#
# CONFIG_SND_VXPOCKET is not set
# CONFIG_SND_PDAUDIOCF is not set
# #
# System on Chip audio support # System on Chip audio support
# #
# CONFIG_SND_SOC is not set # CONFIG_SND_SOC is not set
#
# ALSA SoC audio for Freescale SOCs
#
#
# SoC Audio for the Texas Instruments OMAP
#
# #
# Open Sound System # Open Sound System
# #
...@@ -977,7 +1234,8 @@ CONFIG_SND_PXA2XX_AC97=m ...@@ -977,7 +1234,8 @@ CONFIG_SND_PXA2XX_AC97=m
CONFIG_AC97_BUS=m CONFIG_AC97_BUS=m
CONFIG_HID_SUPPORT=y CONFIG_HID_SUPPORT=y
CONFIG_HID=y CONFIG_HID=y
# CONFIG_HID_DEBUG is not set CONFIG_HID_DEBUG=y
# CONFIG_HIDRAW is not set
# #
# USB Input Devices # USB Input Devices
...@@ -992,6 +1250,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y ...@@ -992,6 +1250,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB_ARCH_HAS_EHCI=y
CONFIG_USB=y CONFIG_USB=y
# CONFIG_USB_DEBUG is not set # CONFIG_USB_DEBUG is not set
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
# #
# Miscellaneous USB options # Miscellaneous USB options
...@@ -1000,8 +1259,9 @@ CONFIG_USB_DEVICEFS=y ...@@ -1000,8 +1259,9 @@ CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set # CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_SUSPEND is not set # CONFIG_USB_SUSPEND is not set
# CONFIG_USB_PERSIST is not set
# CONFIG_USB_OTG is not set # CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# #
# USB Host Controller Drivers # USB Host Controller Drivers
...@@ -1033,13 +1293,16 @@ CONFIG_USB_STORAGE=y ...@@ -1033,13 +1293,16 @@ CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set # CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_KARMA is not set # CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
# CONFIG_USB_LIBUSUAL is not set # CONFIG_USB_LIBUSUAL is not set
# #
...@@ -1052,10 +1315,6 @@ CONFIG_USB_MON=y ...@@ -1052,10 +1315,6 @@ CONFIG_USB_MON=y
# #
# USB port drivers # USB port drivers
# #
#
# USB Serial Converter support
#
# CONFIG_USB_SERIAL is not set # CONFIG_USB_SERIAL is not set
# #
...@@ -1080,14 +1339,6 @@ CONFIG_USB_MON=y ...@@ -1080,14 +1339,6 @@ CONFIG_USB_MON=y
# CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set # CONFIG_USB_TEST is not set
#
# USB DSL modem support
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set # CONFIG_USB_GADGET is not set
CONFIG_MMC=m CONFIG_MMC=m
# CONFIG_MMC_DEBUG is not set # CONFIG_MMC_DEBUG is not set
...@@ -1098,6 +1349,7 @@ CONFIG_MMC=m ...@@ -1098,6 +1349,7 @@ CONFIG_MMC=m
# #
CONFIG_MMC_BLOCK=m CONFIG_MMC_BLOCK=m
CONFIG_MMC_BLOCK_BOUNCE=y CONFIG_MMC_BLOCK_BOUNCE=y
# CONFIG_SDIO_UART is not set
# #
# MMC/SD Host Controller Drivers # MMC/SD Host Controller Drivers
...@@ -1105,10 +1357,22 @@ CONFIG_MMC_BLOCK_BOUNCE=y ...@@ -1105,10 +1357,22 @@ CONFIG_MMC_BLOCK_BOUNCE=y
CONFIG_MMC_PXA=m CONFIG_MMC_PXA=m
# CONFIG_MMC_SDHCI is not set # CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_TIFM_SD is not set # CONFIG_MMC_TIFM_SD is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
# #
# Real Time Clock # LED drivers
#
# CONFIG_LEDS_GPIO is not set
CONFIG_LEDS_CM_X270=y
#
# LED Triggers
# #
CONFIG_LEDS_TRIGGERS=y
# CONFIG_LEDS_TRIGGER_TIMER is not set
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
CONFIG_RTC_LIB=y CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y CONFIG_RTC_HCTOSYS=y
...@@ -1124,12 +1388,33 @@ CONFIG_RTC_INTF_DEV=y ...@@ -1124,12 +1388,33 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set # CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_S35390A is not set
#
# SPI RTC drivers
#
# #
# Platform RTC drivers # Platform RTC drivers
# #
# CONFIG_RTC_DRV_CMOS is not set # CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set # CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T59 is not set # CONFIG_RTC_DRV_M48T59 is not set
CONFIG_RTC_DRV_V3020=y CONFIG_RTC_DRV_V3020=y
...@@ -1138,19 +1423,7 @@ CONFIG_RTC_DRV_V3020=y ...@@ -1138,19 +1423,7 @@ CONFIG_RTC_DRV_V3020=y
# on-CPU RTC drivers # on-CPU RTC drivers
# #
CONFIG_RTC_DRV_SA1100=y CONFIG_RTC_DRV_SA1100=y
# CONFIG_UIO is not set
#
# DMA Engine support
#
# CONFIG_DMA_ENGINE is not set
#
# DMA Clients
#
#
# DMA Devices
#
# #
# File systems # File systems
...@@ -1164,20 +1437,16 @@ CONFIG_EXT3_FS_XATTR=y ...@@ -1164,20 +1437,16 @@ CONFIG_EXT3_FS_XATTR=y
# CONFIG_EXT3_FS_SECURITY is not set # CONFIG_EXT3_FS_SECURITY is not set
# CONFIG_EXT4DEV_FS is not set # CONFIG_EXT4DEV_FS is not set
CONFIG_JBD=y CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=y CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set # CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set # CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set # CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set # CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set # CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set CONFIG_DNOTIFY=y
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set # CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set # CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set # CONFIG_FUSE_FS is not set
...@@ -1191,9 +1460,9 @@ CONFIG_DNOTIFY=y ...@@ -1191,9 +1460,9 @@ CONFIG_DNOTIFY=y
# #
# DOS/FAT/NT Filesystems # DOS/FAT/NT Filesystems
# #
CONFIG_FAT_FS=y CONFIG_FAT_FS=m
CONFIG_MSDOS_FS=y # CONFIG_MSDOS_FS is not set
CONFIG_VFAT_FS=y CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set # CONFIG_NTFS_FS is not set
...@@ -1207,7 +1476,6 @@ CONFIG_SYSFS=y ...@@ -1207,7 +1476,6 @@ CONFIG_SYSFS=y
CONFIG_TMPFS=y CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set # CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set # CONFIG_CONFIGFS_FS is not set
# #
...@@ -1220,22 +1488,30 @@ CONFIG_RAMFS=y ...@@ -1220,22 +1488,30 @@ CONFIG_RAMFS=y
# CONFIG_BEFS_FS is not set # CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set # CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set # CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
CONFIG_JFFS2_SUMMARY=y
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_CRAMFS is not set # CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set # CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_HPFS_FS is not set # CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set # CONFIG_QNX4FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set # CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set # CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
#
# Network File Systems
#
CONFIG_NFS_FS=y CONFIG_NFS_FS=y
CONFIG_NFS_V3=y CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set # CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set # CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y CONFIG_LOCKD=y
...@@ -1245,9 +1521,13 @@ CONFIG_SUNRPC=y ...@@ -1245,9 +1521,13 @@ CONFIG_SUNRPC=y
# CONFIG_SUNRPC_BIND34 is not set # CONFIG_SUNRPC_BIND34 is not set
# CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=y # CONFIG_SMB_FS is not set
# CONFIG_SMB_NLS_DEFAULT is not set CONFIG_CIFS=m
# CONFIG_CIFS is not set # CONFIG_CIFS_STATS is not set
# CONFIG_CIFS_WEAK_PW_HASH is not set
# CONFIG_CIFS_XATTR is not set
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_EXPERIMENTAL is not set
# CONFIG_NCP_FS is not set # CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set # CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set # CONFIG_AFS_FS is not set
...@@ -1255,15 +1535,27 @@ CONFIG_SMB_FS=y ...@@ -1255,15 +1535,27 @@ CONFIG_SMB_FS=y
# #
# Partition Types # Partition Types
# #
# CONFIG_PARTITION_ADVANCED is not set CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# # CONFIG_MINIX_SUBPARTITION is not set
# Native Language Support # CONFIG_SOLARIS_X86_PARTITION is not set
# # CONFIG_UNIXWARE_DISKLABEL is not set
CONFIG_NLS=y # CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
# CONFIG_SYSV68_PARTITION is not set
CONFIG_NLS=m
CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_437=m
# CONFIG_NLS_CODEPAGE_737 is not set # CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set # CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set # CONFIG_NLS_CODEPAGE_850 is not set
...@@ -1287,7 +1579,7 @@ CONFIG_NLS_CODEPAGE_437=y ...@@ -1287,7 +1579,7 @@ CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set # CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set # CONFIG_NLS_ASCII is not set
CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_1=m
# CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set # CONFIG_NLS_ISO8859_4 is not set
...@@ -1300,53 +1592,52 @@ CONFIG_NLS_ISO8859_1=y ...@@ -1300,53 +1592,52 @@ CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_15 is not set # CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set CONFIG_NLS_UTF8=m
#
# Distributed Lock Manager
#
# CONFIG_DLM is not set # CONFIG_DLM is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
# #
# Kernel hacking # Kernel hacking
# #
# CONFIG_PRINTK_TIME is not set # CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y CONFIG_ENABLE_MUST_CHECK=y
CONFIG_MAGIC_SYSRQ=y CONFIG_FRAME_WARN=0
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set # CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set # CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set # CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set # CONFIG_DEBUG_SHIRQ is not set
# CONFIG_DETECT_SOFTLOCKUP is not set # CONFIG_DETECT_SOFTLOCKUP is not set
CONFIG_SCHED_DEBUG=y # CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHEDSTATS is not set # CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set # CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_SLAB is not set # CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set # CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set # CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set # CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set # CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set # CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_WRITECOUNT is not set
# CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y CONFIG_FRAME_POINTER=y
CONFIG_FORCED_INLINING=y # CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_FAULT_INJECTION is not set # CONFIG_FAULT_INJECTION is not set
# CONFIG_SAMPLES is not set
CONFIG_DEBUG_USER=y CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_ERRORS=y
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_LL=y CONFIG_DEBUG_LL=y
# CONFIG_DEBUG_ICEDCC is not set # CONFIG_DEBUG_ICEDCC is not set
...@@ -1355,55 +1646,96 @@ CONFIG_DEBUG_LL=y ...@@ -1355,55 +1646,96 @@ CONFIG_DEBUG_LL=y
# #
# CONFIG_KEYS is not set # CONFIG_KEYS is not set
# CONFIG_SECURITY is not set # CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_CRYPTO=y CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=m
CONFIG_CRYPTO_BLKCIPHER=m #
CONFIG_CRYPTO_MANAGER=m # Crypto core or helper
#
# CONFIG_CRYPTO_MANAGER is not set
# CONFIG_CRYPTO_GF128MUL is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_AUTHENC is not set
# CONFIG_CRYPTO_TEST is not set
#
# Authenticated Encryption with Associated Data
#
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_SEQIV is not set
#
# Block modes
#
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_XTS is not set
#
# Hash modes
#
# CONFIG_CRYPTO_HMAC is not set # CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set # CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_NULL is not set
#
# Digest
#
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_MD4 is not set # CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set # CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_WP512 is not set
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_CBC=m #
CONFIG_CRYPTO_PCBC=m # Ciphers
# CONFIG_CRYPTO_LRW is not set #
# CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_DES is not set # CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_SERPENT is not set
CONFIG_CRYPTO_AES=m
# CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set # CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_DES is not set
CONFIG_CRYPTO_ARC4=m # CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set # CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_TWOFISH is not set
#
# Compression
#
# CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set # CONFIG_CRYPTO_LZO is not set
# CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_HW is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_HW=y
# #
# Library routines # Library routines
# #
CONFIG_BITREVERSE=y CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set # CONFIG_GENERIC_FIND_FIRST_BIT is not set
# CONFIG_GENERIC_FIND_NEXT_BIT is not set
CONFIG_CRC_CCITT=m
# CONFIG_CRC16 is not set # CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set # CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y CONFIG_CRC32=y
# CONFIG_CRC7 is not set # CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set # CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y CONFIG_HAS_IOPORT=y
......
arch/arm/mach-pxa/Kconfig
浏览文件 @ fdc614e8
...@@ -20,8 +20,7 @@ endmenu ...@@ -20,8 +20,7 @@ endmenu
endif endif
choice menu "Select target boards"
prompt "Select target board"
config ARCH_GUMSTIX config ARCH_GUMSTIX
bool "Gumstix XScale boards" bool "Gumstix XScale boards"
...@@ -37,10 +36,12 @@ config ARCH_LUBBOCK ...@@ -37,10 +36,12 @@ config ARCH_LUBBOCK
config MACH_LOGICPD_PXA270 config MACH_LOGICPD_PXA270
bool "LogicPD PXA270 Card Engine Development Platform" bool "LogicPD PXA270 Card Engine Development Platform"
select PXA27x select PXA27x
select HAVE_PWM
config MACH_MAINSTONE config MACH_MAINSTONE
bool "Intel HCDDBBVA0 Development Platform" bool "Intel HCDDBBVA0 Development Platform"
select PXA27x select PXA27x
select HAVE_PWM
config ARCH_PXA_IDP config ARCH_PXA_IDP
bool "Accelent Xscale IDP" bool "Accelent Xscale IDP"
...@@ -116,6 +117,7 @@ config MACH_COLIBRI ...@@ -116,6 +117,7 @@ config MACH_COLIBRI
config MACH_ZYLONITE config MACH_ZYLONITE
bool "PXA3xx Development Platform" bool "PXA3xx Development Platform"
select PXA3xx select PXA3xx
select HAVE_PWM
config MACH_LITTLETON config MACH_LITTLETON
bool "PXA3xx Form Factor Platform (aka Littleton)" bool "PXA3xx Form Factor Platform (aka Littleton)"
...@@ -138,7 +140,7 @@ config MACH_PCM027 ...@@ -138,7 +140,7 @@ config MACH_PCM027
select PXA27x select PXA27x
select IWMMXT select IWMMXT
endchoice endmenu
choice choice
prompt "Used baseboard" prompt "Used baseboard"
...@@ -146,25 +148,24 @@ choice ...@@ -146,25 +148,24 @@ choice
config MACH_PCM990_BASEBOARD config MACH_PCM990_BASEBOARD
bool "PHYTEC PCM-990 development board" bool "PHYTEC PCM-990 development board"
select HAVE_PWM
endchoice endchoice
if PXA_SHARPSL
choice choice
prompt "Select target Sharp Zaurus device range" prompt "display on pcm990"
depends on MACH_PCM990_BASEBOARD
config PXA_SHARPSL_25x config PCM990_DISPLAY_SHARP
bool "Sharp PXA25x models (SL-5600, SL-C7xx and SL-C6000x)" bool "sharp lq084v1dg21 stn display"
select PXA25x
config PXA_SHARPSL_27x config PCM990_DISPLAY_NEC
bool "Sharp PXA270 models (SL-Cxx00)" bool "nec nl6448bc20_18d tft display"
select PXA27x
endchoice config PCM990_DISPLAY_NONE
bool "no display"
endif endchoice
if ARCH_GUMSTIX if ARCH_GUMSTIX
...@@ -199,28 +200,33 @@ endmenu ...@@ -199,28 +200,33 @@ endmenu
config MACH_POODLE config MACH_POODLE
bool "Enable Sharp SL-5600 (Poodle) Support" bool "Enable Sharp SL-5600 (Poodle) Support"
depends on PXA_SHARPSL_25x depends on PXA_SHARPSL
select PXA25x
select SHARP_LOCOMO select SHARP_LOCOMO
select PXA_SSP select PXA_SSP
config MACH_CORGI config MACH_CORGI
bool "Enable Sharp SL-C700 (Corgi) Support" bool "Enable Sharp SL-C700 (Corgi) Support"
depends on PXA_SHARPSL_25x depends on PXA_SHARPSL
select PXA25x
select PXA_SHARP_C7xx select PXA_SHARP_C7xx
config MACH_SHEPHERD config MACH_SHEPHERD
bool "Enable Sharp SL-C750 (Shepherd) Support" bool "Enable Sharp SL-C750 (Shepherd) Support"
depends on PXA_SHARPSL_25x depends on PXA_SHARPSL
select PXA25x
select PXA_SHARP_C7xx select PXA_SHARP_C7xx
config MACH_HUSKY config MACH_HUSKY
bool "Enable Sharp SL-C760 (Husky) Support" bool "Enable Sharp SL-C760 (Husky) Support"
depends on PXA_SHARPSL_25x depends on PXA_SHARPSL
select PXA25x
select PXA_SHARP_C7xx select PXA_SHARP_C7xx
config MACH_AKITA config MACH_AKITA
bool "Enable Sharp SL-1000 (Akita) Support" bool "Enable Sharp SL-1000 (Akita) Support"
depends on PXA_SHARPSL_27x depends on PXA_SHARPSL
select PXA27x
select PXA_SHARP_Cxx00 select PXA_SHARP_Cxx00
select MACH_SPITZ select MACH_SPITZ
select I2C select I2C
...@@ -228,17 +234,20 @@ config MACH_AKITA ...@@ -228,17 +234,20 @@ config MACH_AKITA
config MACH_SPITZ config MACH_SPITZ
bool "Enable Sharp Zaurus SL-3000 (Spitz) Support" bool "Enable Sharp Zaurus SL-3000 (Spitz) Support"
depends on PXA_SHARPSL_27x depends on PXA_SHARPSL
select PXA27x
select PXA_SHARP_Cxx00 select PXA_SHARP_Cxx00
config MACH_BORZOI config MACH_BORZOI
bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support" bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support"
depends on PXA_SHARPSL_27x depends on PXA_SHARPSL
select PXA27x
select PXA_SHARP_Cxx00 select PXA_SHARP_Cxx00
config MACH_TOSA config MACH_TOSA
bool "Enable Sharp SL-6000x (Tosa) Support" bool "Enable Sharp SL-6000x (Tosa) Support"
depends on PXA_SHARPSL_25x depends on PXA_SHARPSL
select PXA25x
config PXA25x config PXA25x
bool bool
...@@ -273,4 +282,10 @@ config PXA_SSP ...@@ -273,4 +282,10 @@ config PXA_SSP
tristate tristate
help help
Enable support for PXA2xx SSP ports Enable support for PXA2xx SSP ports
config PXA_PWM
tristate
default BACKLIGHT_PWM
help
Enable support for PXA2xx/PXA3xx PWM controllers
endif endif
arch/arm/mach-pxa/Makefile
浏览文件 @ fdc614e8
...@@ -10,6 +10,7 @@ obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o ...@@ -10,6 +10,7 @@ obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
# Generic drivers that other drivers may depend upon # Generic drivers that other drivers may depend upon
obj-$(CONFIG_PXA_SSP) += ssp.o obj-$(CONFIG_PXA_SSP) += ssp.o
obj-$(CONFIG_PXA_PWM) += pwm.o
# SoC-specific code # SoC-specific code
obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa25x.o obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa25x.o
......
arch/arm/mach-pxa/clock.c
浏览文件 @ fdc614e8
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h> #include <asm/arch/pxa2xx-gpio.h>
#include <asm/hardware.h> #include <asm/hardware.h>
......
arch/arm/mach-pxa/cm-x270-pci.c
浏览文件 @ fdc614e8
...@@ -41,6 +41,7 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size, ...@@ -41,6 +41,7 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
{ {
unsigned int sz = SZ_64M >> PAGE_SHIFT; unsigned int sz = SZ_64M >> PAGE_SHIFT;
if (machine_is_armcore()) {
pr_info("Adjusting zones for CM-x270\n"); pr_info("Adjusting zones for CM-x270\n");
/* /*
...@@ -53,6 +54,7 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size, ...@@ -53,6 +54,7 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
zone_size[0] = sz; zone_size[0] = sz;
zhole_size[1] = zhole_size[0]; zhole_size[1] = zhole_size[0];
zhole_size[0] = 0; zhole_size[0] = 0;
}
} }
static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
......
arch/arm/mach-pxa/corgi.c
浏览文件 @ fdc614e8
...@@ -36,6 +36,7 @@ ...@@ -36,6 +36,7 @@
#include <asm/mach/irq.h> #include <asm/mach/irq.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h> #include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/irda.h> #include <asm/arch/irda.h>
#include <asm/arch/mmc.h> #include <asm/arch/mmc.h>
......
arch/arm/mach-pxa/corgi_pm.c
浏览文件 @ fdc614e8
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#include <asm/arch/sharpsl.h> #include <asm/arch/sharpsl.h>
#include <asm/arch/corgi.h> #include <asm/arch/corgi.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h> #include <asm/arch/pxa2xx-gpio.h>
#include "sharpsl.h" #include "sharpsl.h"
...@@ -204,7 +205,9 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = { ...@@ -204,7 +205,9 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = {
.read_devdata = corgipm_read_devdata, .read_devdata = corgipm_read_devdata,
.charger_wakeup = corgi_charger_wakeup, .charger_wakeup = corgi_charger_wakeup,
.should_wakeup = corgi_should_wakeup, .should_wakeup = corgi_should_wakeup,
#ifdef CONFIG_BACKLIGHT_CORGI
.backlight_limit = corgibl_limit_intensity, .backlight_limit = corgibl_limit_intensity,
#endif
.charge_on_volt = SHARPSL_CHARGE_ON_VOLT, .charge_on_volt = SHARPSL_CHARGE_ON_VOLT,
.charge_on_temp = SHARPSL_CHARGE_ON_TEMP, .charge_on_temp = SHARPSL_CHARGE_ON_TEMP,
.charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH, .charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH,
...@@ -226,6 +229,10 @@ static int __devinit corgipm_init(void) ...@@ -226,6 +229,10 @@ static int __devinit corgipm_init(void)
{ {
int ret; int ret;
if (!machine_is_corgi() && !machine_is_shepherd()
&& !machine_is_husky())
return -ENODEV;
corgipm_device = platform_device_alloc("sharpsl-pm", -1); corgipm_device = platform_device_alloc("sharpsl-pm", -1);
if (!corgipm_device) if (!corgipm_device)
return -ENOMEM; return -ENOMEM;
......
arch/arm/mach-pxa/devices.c
浏览文件 @ fdc614e8
...@@ -10,11 +10,13 @@ ...@@ -10,11 +10,13 @@
#include <asm/arch/mmc.h> #include <asm/arch/mmc.h>
#include <asm/arch/irda.h> #include <asm/arch/irda.h>
#include <asm/arch/i2c.h> #include <asm/arch/i2c.h>
#include <asm/arch/mfp-pxa27x.h>
#include <asm/arch/ohci.h> #include <asm/arch/ohci.h>
#include <asm/arch/pxa27x_keypad.h> #include <asm/arch/pxa27x_keypad.h>
#include <asm/arch/camera.h> #include <asm/arch/camera.h>
#include "devices.h" #include "devices.h"
#include "generic.h"
void __init pxa_register_device(struct platform_device *dev, void *data) void __init pxa_register_device(struct platform_device *dev, void *data)
{ {
...@@ -233,8 +235,15 @@ struct platform_device pxa_device_i2c = { ...@@ -233,8 +235,15 @@ struct platform_device pxa_device_i2c = {
.num_resources = ARRAY_SIZE(pxai2c_resources), .num_resources = ARRAY_SIZE(pxai2c_resources),
}; };
static unsigned long pxa27x_i2c_mfp_cfg[] = {
GPIO117_I2C_SCL,
GPIO118_I2C_SDA,
};
void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
{ {
if (cpu_is_pxa27x())
pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg));
pxa_register_device(&pxa_device_i2c, info); pxa_register_device(&pxa_device_i2c, info);
} }
...@@ -280,6 +289,36 @@ struct platform_device pxa_device_rtc = { ...@@ -280,6 +289,36 @@ struct platform_device pxa_device_rtc = {
#ifdef CONFIG_PXA25x #ifdef CONFIG_PXA25x
static struct resource pxa25x_resource_pwm0[] = {
[0] = {
.start = 0x40b00000,
.end = 0x40b0000f,
.flags = IORESOURCE_MEM,
},
};
struct platform_device pxa25x_device_pwm0 = {
.name = "pxa25x-pwm",
.id = 0,
.resource = pxa25x_resource_pwm0,
.num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
};
static struct resource pxa25x_resource_pwm1[] = {
[0] = {
.start = 0x40c00000,
.end = 0x40c0000f,
.flags = IORESOURCE_MEM,
},
};
struct platform_device pxa25x_device_pwm1 = {
.name = "pxa25x-pwm",
.id = 1,
.resource = pxa25x_resource_pwm1,
.num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
};
static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32); static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa25x_resource_ssp[] = { static struct resource pxa25x_resource_ssp[] = {
...@@ -568,6 +607,36 @@ struct platform_device pxa27x_device_ssp3 = { ...@@ -568,6 +607,36 @@ struct platform_device pxa27x_device_ssp3 = {
.num_resources = ARRAY_SIZE(pxa27x_resource_ssp3), .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
}; };
static struct resource pxa27x_resource_pwm0[] = {
[0] = {
.start = 0x40b00000,
.end = 0x40b0001f,
.flags = IORESOURCE_MEM,
},
};
struct platform_device pxa27x_device_pwm0 = {
.name = "pxa27x-pwm",
.id = 0,
.resource = pxa27x_resource_pwm0,
.num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
};
static struct resource pxa27x_resource_pwm1[] = {
[0] = {
.start = 0x40c00000,
.end = 0x40c0001f,
.flags = IORESOURCE_MEM,
},
};
struct platform_device pxa27x_device_pwm1 = {
.name = "pxa27x-pwm",
.id = 1,
.resource = pxa27x_resource_pwm1,
.num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
};
static struct resource pxa27x_resource_camera[] = { static struct resource pxa27x_resource_camera[] = {
[0] = { [0] = {
.start = 0x50000000, .start = 0x50000000,
......
arch/arm/mach-pxa/devices.h
浏览文件 @ fdc614e8
...@@ -24,4 +24,9 @@ extern struct platform_device pxa27x_device_ssp2; ...@@ -24,4 +24,9 @@ extern struct platform_device pxa27x_device_ssp2;
extern struct platform_device pxa27x_device_ssp3; extern struct platform_device pxa27x_device_ssp3;
extern struct platform_device pxa3xx_device_ssp4; extern struct platform_device pxa3xx_device_ssp4;
extern struct platform_device pxa25x_device_pwm0;
extern struct platform_device pxa25x_device_pwm1;
extern struct platform_device pxa27x_device_pwm0;
extern struct platform_device pxa27x_device_pwm1;
void __init pxa_register_device(struct platform_device *dev, void *data); void __init pxa_register_device(struct platform_device *dev, void *data);
arch/arm/mach-pxa/em-x270.c
浏览文件 @ fdc614e8
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-gpio.h> #include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/pxa27x-udc.h>
#include <asm/arch/pxafb.h> #include <asm/arch/pxafb.h>
#include <asm/arch/ohci.h> #include <asm/arch/ohci.h>
#include <asm/arch/mmc.h> #include <asm/arch/mmc.h>
......
arch/arm/mach-pxa/generic.c
浏览文件 @ fdc614e8
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h> /* for __pxa_set_cken */
#include "generic.h" #include "generic.h"
......
arch/arm/mach-pxa/lpd270.c
浏览文件 @ fdc614e8
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
#include <linux/ioport.h> #include <linux/ioport.h>
#include <linux/mtd/mtd.h> #include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h> #include <linux/mtd/partitions.h>
#include <linux/pwm_backlight.h>
#include <asm/types.h> #include <asm/types.h>
#include <asm/setup.h> #include <asm/setup.h>
...@@ -134,9 +135,12 @@ static struct sys_device lpd270_irq_device = { ...@@ -134,9 +135,12 @@ static struct sys_device lpd270_irq_device = {
static int __init lpd270_irq_device_init(void) static int __init lpd270_irq_device_init(void)
{ {
int ret = sysdev_class_register(&lpd270_irq_sysclass); int ret = -ENODEV;
if (machine_is_logicpd_pxa270()) {
ret = sysdev_class_register(&lpd270_irq_sysclass);
if (ret == 0) if (ret == 0)
ret = sysdev_register(&lpd270_irq_device); ret = sysdev_register(&lpd270_irq_device);
}
return ret; return ret;
} }
...@@ -233,21 +237,20 @@ static struct platform_device lpd270_flash_device[2] = { ...@@ -233,21 +237,20 @@ static struct platform_device lpd270_flash_device[2] = {
}, },
}; };
static void lpd270_backlight_power(int on) static struct platform_pwm_backlight_data lpd270_backlight_data = {
{ .pwm_id = 0,
if (on) { .max_brightness = 1,
pxa_gpio_mode(GPIO16_PWM0_MD); .dft_brightness = 1,
pxa_set_cken(CKEN_PWM0, 1); .pwm_period_ns = 78770,
PWM_CTRL0 = 0; };
PWM_PWDUTY0 = 0x3ff;
PWM_PERVAL0 = 0x3ff; static struct platform_device lpd270_backlight_device = {
} else { .name = "pwm-backlight",
PWM_CTRL0 = 0; .dev = {
PWM_PWDUTY0 = 0x0; .parent = &pxa27x_device_pwm0.dev,
PWM_PERVAL0 = 0x3FF; .platform_data = &lpd270_backlight_data,
pxa_set_cken(CKEN_PWM0, 0); },
} };
}
/* 5.7" TFT QVGA (LoLo display number 1) */ /* 5.7" TFT QVGA (LoLo display number 1) */
static struct pxafb_mode_info sharp_lq057q3dc02_mode = { static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
...@@ -269,7 +272,6 @@ static struct pxafb_mach_info sharp_lq057q3dc02 = { ...@@ -269,7 +272,6 @@ static struct pxafb_mach_info sharp_lq057q3dc02 = {
.num_modes = 1, .num_modes = 1,
.lccr0 = 0x07800080, .lccr0 = 0x07800080,
.lccr3 = 0x00400000, .lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
}; };
/* 12.1" TFT SVGA (LoLo display number 2) */ /* 12.1" TFT SVGA (LoLo display number 2) */
...@@ -292,7 +294,6 @@ static struct pxafb_mach_info sharp_lq121s1dg31 = { ...@@ -292,7 +294,6 @@ static struct pxafb_mach_info sharp_lq121s1dg31 = {
.num_modes = 1, .num_modes = 1,
.lccr0 = 0x07800080, .lccr0 = 0x07800080,
.lccr3 = 0x00400000, .lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
}; };
/* 3.6" TFT QVGA (LoLo display number 3) */ /* 3.6" TFT QVGA (LoLo display number 3) */
...@@ -315,7 +316,6 @@ static struct pxafb_mach_info sharp_lq036q1da01 = { ...@@ -315,7 +316,6 @@ static struct pxafb_mach_info sharp_lq036q1da01 = {
.num_modes = 1, .num_modes = 1,
.lccr0 = 0x07800080, .lccr0 = 0x07800080,
.lccr3 = 0x00400000, .lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
}; };
/* 6.4" TFT VGA (LoLo display number 5) */ /* 6.4" TFT VGA (LoLo display number 5) */
...@@ -338,7 +338,6 @@ static struct pxafb_mach_info sharp_lq64d343 = { ...@@ -338,7 +338,6 @@ static struct pxafb_mach_info sharp_lq64d343 = {
.num_modes = 1, .num_modes = 1,
.lccr0 = 0x07800080, .lccr0 = 0x07800080,
.lccr3 = 0x00400000, .lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
}; };
/* 10.4" TFT VGA (LoLo display number 7) */ /* 10.4" TFT VGA (LoLo display number 7) */
...@@ -361,7 +360,6 @@ static struct pxafb_mach_info sharp_lq10d368 = { ...@@ -361,7 +360,6 @@ static struct pxafb_mach_info sharp_lq10d368 = {
.num_modes = 1, .num_modes = 1,
.lccr0 = 0x07800080, .lccr0 = 0x07800080,
.lccr3 = 0x00400000, .lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
}; };
/* 3.5" TFT QVGA (LoLo display number 8) */ /* 3.5" TFT QVGA (LoLo display number 8) */
...@@ -384,7 +382,6 @@ static struct pxafb_mach_info sharp_lq035q7db02_20 = { ...@@ -384,7 +382,6 @@ static struct pxafb_mach_info sharp_lq035q7db02_20 = {
.num_modes = 1, .num_modes = 1,
.lccr0 = 0x07800080, .lccr0 = 0x07800080,
.lccr3 = 0x00400000, .lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
}; };
static struct pxafb_mach_info *lpd270_lcd_to_use; static struct pxafb_mach_info *lpd270_lcd_to_use;
...@@ -414,6 +411,7 @@ __setup("lcd=", lpd270_set_lcd); ...@@ -414,6 +411,7 @@ __setup("lcd=", lpd270_set_lcd);
static struct platform_device *platform_devices[] __initdata = { static struct platform_device *platform_devices[] __initdata = {
&smc91x_device, &smc91x_device,
&lpd270_backlight_device,
&lpd270_audio_device, &lpd270_audio_device,
&lpd270_flash_device[0], &lpd270_flash_device[0],
&lpd270_flash_device[1], &lpd270_flash_device[1],
...@@ -454,6 +452,7 @@ static void __init lpd270_init(void) ...@@ -454,6 +452,7 @@ static void __init lpd270_init(void)
* On LogicPD PXA270, we route AC97_SYSCLK via GPIO45. * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
*/ */
pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD); pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
pxa_gpio_mode(GPIO16_PWM0_MD);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
......
arch/arm/mach-pxa/magician.c
浏览文件 @ fdc614e8
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
#include <linux/mtd/map.h> #include <linux/mtd/map.h>
#include <linux/mtd/physmap.h> #include <linux/mtd/physmap.h>
#include <linux/pda_power.h> #include <linux/pda_power.h>
#include <linux/pwm_backlight.h>
#include <asm/gpio.h> #include <asm/gpio.h>
#include <asm/hardware.h> #include <asm/hardware.h>
...@@ -33,12 +34,14 @@ ...@@ -33,12 +34,14 @@
#include <asm/arch/magician.h> #include <asm/arch/magician.h>
#include <asm/arch/mfp-pxa27x.h> #include <asm/arch/mfp-pxa27x.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxafb.h> #include <asm/arch/pxafb.h>
#include <asm/arch/i2c.h> #include <asm/arch/i2c.h>
#include <asm/arch/mmc.h> #include <asm/arch/mmc.h>
#include <asm/arch/irda.h> #include <asm/arch/irda.h>
#include <asm/arch/ohci.h> #include <asm/arch/ohci.h>
#include "devices.h"
#include "generic.h" #include "generic.h"
static unsigned long magician_pin_config[] = { static unsigned long magician_pin_config[] = {
...@@ -348,40 +351,58 @@ static struct pxafb_mach_info samsung_info = { ...@@ -348,40 +351,58 @@ static struct pxafb_mach_info samsung_info = {
* Backlight * Backlight
*/ */
static void magician_set_bl_intensity(int intensity) static int magician_backlight_init(struct device *dev)
{ {
if (intensity) { int ret;
PWM_CTRL0 = 1;
PWM_PERVAL0 = 0xc8; ret = gpio_request(EGPIO_MAGICIAN_BL_POWER, "BL_POWER");
if (intensity > 0xc7) { if (ret)
PWM_PWDUTY0 = intensity - 0x48; goto err;
ret = gpio_request(EGPIO_MAGICIAN_BL_POWER2, "BL_POWER2");
if (ret)
goto err2;
return 0;
err2:
gpio_free(EGPIO_MAGICIAN_BL_POWER);
err:
return ret;
}
static int magician_backlight_notify(int brightness)
{
gpio_set_value(EGPIO_MAGICIAN_BL_POWER, brightness);
if (brightness >= 200) {
gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1); gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1);
return brightness - 72;
} else { } else {
PWM_PWDUTY0 = intensity;
gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0); gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0);
} return brightness;
gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 1);
pxa_set_cken(CKEN_PWM0, 1);
} else {
/* PWM_PWDUTY0 = intensity; */
gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 0);
pxa_set_cken(CKEN_PWM0, 0);
} }
} }
static struct generic_bl_info backlight_info = { static void magician_backlight_exit(struct device *dev)
.default_intensity = 0x64, {
.limit_mask = 0x0b, gpio_free(EGPIO_MAGICIAN_BL_POWER);
.max_intensity = 0xc7+0x48, gpio_free(EGPIO_MAGICIAN_BL_POWER2);
.set_bl_intensity = magician_set_bl_intensity, }
static struct platform_pwm_backlight_data backlight_data = {
.pwm_id = 0,
.max_brightness = 272,
.dft_brightness = 100,
.pwm_period_ns = 30923,
.init = magician_backlight_init,
.notify = magician_backlight_notify,
.exit = magician_backlight_exit,
}; };
static struct platform_device backlight = { static struct platform_device backlight = {
.name = "generic-bl", .name = "pwm-backlight",
.dev = { .dev = {
.platform_data = &backlight_info, .parent = &pxa27x_device_pwm0.dev,
.platform_data = &backlight_data,
}, },
.id = -1,
}; };
/* /*
......
arch/arm/mach-pxa/mainstone.c
浏览文件 @ fdc614e8
...@@ -23,9 +23,9 @@ ...@@ -23,9 +23,9 @@
#include <linux/ioport.h> #include <linux/ioport.h>
#include <linux/mtd/mtd.h> #include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h> #include <linux/mtd/partitions.h>
#include <linux/backlight.h>
#include <linux/input.h> #include <linux/input.h>
#include <linux/gpio_keys.h> #include <linux/gpio_keys.h>
#include <linux/pwm_backlight.h>
#include <asm/types.h> #include <asm/types.h>
#include <asm/setup.h> #include <asm/setup.h>
...@@ -349,56 +349,27 @@ static struct platform_device mst_flash_device[2] = { ...@@ -349,56 +349,27 @@ static struct platform_device mst_flash_device[2] = {
}, },
}; };
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static int mainstone_backlight_update_status(struct backlight_device *bl) static struct platform_pwm_backlight_data mainstone_backlight_data = {
{ .pwm_id = 0,
int brightness = bl->props.brightness; .max_brightness = 1023,
.dft_brightness = 1023,
if (bl->props.power != FB_BLANK_UNBLANK || .pwm_period_ns = 78770,
bl->props.fb_blank != FB_BLANK_UNBLANK) };
brightness = 0;
if (brightness != 0)
pxa_set_cken(CKEN_PWM0, 1);
PWM_CTRL0 = 0;
PWM_PWDUTY0 = brightness;
PWM_PERVAL0 = bl->props.max_brightness;
if (brightness == 0)
pxa_set_cken(CKEN_PWM0, 0);
return 0; /* pointless return value */
}
static int mainstone_backlight_get_brightness(struct backlight_device *bl)
{
return PWM_PWDUTY0;
}
static /*const*/ struct backlight_ops mainstone_backlight_ops = { static struct platform_device mainstone_backlight_device = {
.update_status = mainstone_backlight_update_status, .name = "pwm-backlight",
.get_brightness = mainstone_backlight_get_brightness, .dev = {
.parent = &pxa27x_device_pwm0.dev,
.platform_data = &mainstone_backlight_data,
},
}; };
static void __init mainstone_backlight_register(void) static void __init mainstone_backlight_register(void)
{ {
struct backlight_device *bl; int ret = platform_device_register(&mainstone_backlight_device);
if (ret)
bl = backlight_device_register("mainstone-bl", &pxa_device_fb.dev, printk(KERN_ERR "mainstone: failed to register backlight device: %d\n", ret);
NULL, &mainstone_backlight_ops);
if (IS_ERR(bl)) {
printk(KERN_ERR "mainstone: unable to register backlight: %ld\n",
PTR_ERR(bl));
return;
}
/*
* broken design - register-then-setup interfaces are
* utterly broken by definition.
*/
bl->props.max_brightness = 1023;
bl->props.brightness = 1023;
backlight_update_status(bl);
} }
#else #else
#define mainstone_backlight_register() do { } while (0) #define mainstone_backlight_register() do { } while (0)
......
arch/arm/mach-pxa/mfp-pxa2xx.c
浏览文件 @ fdc614e8
...@@ -20,6 +20,7 @@ ...@@ -20,6 +20,7 @@
#include <asm/arch/hardware.h> #include <asm/arch/hardware.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/mfp-pxa2xx.h> #include <asm/arch/mfp-pxa2xx.h>
#include "generic.h" #include "generic.h"
......
arch/arm/mach-pxa/pcm990-baseboard.c
浏览文件 @ fdc614e8
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/ide.h> #include <linux/ide.h>
#include <linux/i2c.h> #include <linux/i2c.h>
#include <linux/pwm_backlight.h>
#include <media/soc_camera.h> #include <media/soc_camera.h>
...@@ -36,9 +37,99 @@ ...@@ -36,9 +37,99 @@
#include <asm/arch/mmc.h> #include <asm/arch/mmc.h>
#include <asm/arch/ohci.h> #include <asm/arch/ohci.h>
#include <asm/arch/pcm990_baseboard.h> #include <asm/arch/pcm990_baseboard.h>
#include <asm/arch/pxafb.h>
#include "devices.h"
/* /*
* The PCM-990 development baseboard uses PCM-027's hardeware in the * pcm990_lcd_power - control power supply to the LCD
* @on: 0 = switch off, 1 = switch on
*
* Called by the pxafb driver
*/
#ifndef CONFIG_PCM990_DISPLAY_NONE
static void pcm990_lcd_power(int on, struct fb_var_screeninfo *var)
{
if (on) {
/* enable LCD-Latches
* power on LCD
*/
__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) =
PCM990_CTRL_LCDPWR + PCM990_CTRL_LCDON;
} else {
/* disable LCD-Latches
* power off LCD
*/
__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) = 0x00;
}
}
#endif
#if defined(CONFIG_PCM990_DISPLAY_SHARP)
static struct pxafb_mode_info fb_info_sharp_lq084v1dg21 = {
.pixclock = 28000,
.xres = 640,
.yres = 480,
.bpp = 16,
.hsync_len = 20,
.left_margin = 103,
.right_margin = 47,
.vsync_len = 6,
.upper_margin = 28,
.lower_margin = 5,
.sync = 0,
.cmap_greyscale = 0,
};
static struct pxafb_mach_info pcm990_fbinfo __initdata = {
.modes = &fb_info_sharp_lq084v1dg21,
.num_modes = 1,
.lccr0 = LCCR0_PAS,
.lccr3 = LCCR3_PCP,
.pxafb_lcd_power = pcm990_lcd_power,
};
#elif defined(CONFIG_PCM990_DISPLAY_NEC)
struct pxafb_mode_info fb_info_nec_nl6448bc20_18d = {
.pixclock = 39720,
.xres = 640,
.yres = 480,
.bpp = 16,
.hsync_len = 32,
.left_margin = 16,
.right_margin = 48,
.vsync_len = 2,
.upper_margin = 12,
.lower_margin = 17,
.sync = 0,
.cmap_greyscale = 0,
};
static struct pxafb_mach_info pcm990_fbinfo __initdata = {
.modes = &fb_info_nec_nl6448bc20_18d,
.num_modes = 1,
.lccr0 = LCCR0_Act,
.lccr3 = LCCR3_PixFlEdg,
.pxafb_lcd_power = pcm990_lcd_power,
};
#endif
static struct platform_pwm_backlight_data pcm990_backlight_data = {
.pwm_id = 0,
.max_brightness = 1023,
.dft_brightness = 1023,
.pwm_period_ns = 78770,
};
static struct platform_device pcm990_backlight_device = {
.name = "pwm-backlight",
.dev = {
.parent = &pxa27x_device_pwm0.dev,
.platform_data = &pcm990_backlight_data,
},
};
/*
* The PCM-990 development baseboard uses PCM-027's hardware in the
* following way: * following way:
* *
* - LCD support is in use * - LCD support is in use
...@@ -393,6 +484,12 @@ void __init pcm990_baseboard_init(void) ...@@ -393,6 +484,12 @@ void __init pcm990_baseboard_init(void)
/* register CPLD's IRQ controller */ /* register CPLD's IRQ controller */
pcm990_init_irq(); pcm990_init_irq();
#ifndef CONFIG_PCM990_DISPLAY_NONE
set_pxa_fb_info(&pcm990_fbinfo);
#endif
pxa_gpio_mode(GPIO16_PWM0_MD);
platform_device_register(&pcm990_backlight_device);
platform_device_register(&pxa27x_device_ac97); platform_device_register(&pxa27x_device_ac97);
/* MMC */ /* MMC */
......
arch/arm/mach-pxa/poodle.c
浏览文件 @ fdc614e8
...@@ -32,6 +32,7 @@ ...@@ -32,6 +32,7 @@
#include <asm/mach/irq.h> #include <asm/mach/irq.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h> #include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/mmc.h> #include <asm/arch/mmc.h>
#include <asm/arch/udc.h> #include <asm/arch/udc.h>
......
arch/arm/mach-pxa/pwm.c 0 → 100644
浏览文件 @ fdc614e8
/*
* linux/arch/arm/mach-pxa/pwm.c
*
* simple driver for PWM (Pulse Width Modulator) controller
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* 2008-02-13 initial version
* eric miao <eric.miao@marvell.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/pwm.h>
#include <asm/div64.h>
#include <asm/arch/pxa-regs.h>
/* PWM registers and bits definitions */
#define PWMCR (0x00)
#define PWMDCR (0x04)
#define PWMPCR (0x08)
#define PWMCR_SD (1 << 6)
#define PWMDCR_FD (1 << 10)
struct pwm_device {
struct list_head node;
struct platform_device *pdev;
const char *label;
struct clk *clk;
int clk_enabled;
void __iomem *mmio_base;
unsigned int use_count;
unsigned int pwm_id;
};
/*
* period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
* duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
*/
int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
{
unsigned long long c;
unsigned long period_cycles, prescale, pv, dc;
if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
return -EINVAL;
c = clk_get_rate(pwm->clk);
c = c * period_ns;
do_div(c, 1000000000);
period_cycles = c;
if (period_cycles < 0)
period_cycles = 1;
prescale = (period_cycles - 1) / 1024;
pv = period_cycles / (prescale + 1) - 1;
if (prescale > 63)
return -EINVAL;
if (duty_ns == period_ns)
dc = PWMDCR_FD;
else
dc = (pv + 1) * duty_ns / period_ns;
/* NOTE: the clock to PWM has to be enabled first
* before writing to the registers
*/
clk_enable(pwm->clk);
__raw_writel(prescale, pwm->mmio_base + PWMCR);
__raw_writel(dc, pwm->mmio_base + PWMDCR);
__raw_writel(pv, pwm->mmio_base + PWMPCR);
clk_disable(pwm->clk);
return 0;
}
EXPORT_SYMBOL(pwm_config);
int pwm_enable(struct pwm_device *pwm)
{
int rc = 0;
if (!pwm->clk_enabled) {
rc = clk_enable(pwm->clk);
if (!rc)
pwm->clk_enabled = 1;
}
return rc;
}
EXPORT_SYMBOL(pwm_enable);
void pwm_disable(struct pwm_device *pwm)
{
if (pwm->clk_enabled) {
clk_disable(pwm->clk);
pwm->clk_enabled = 0;
}
}
EXPORT_SYMBOL(pwm_disable);
static DEFINE_MUTEX(pwm_lock);
static LIST_HEAD(pwm_list);
struct pwm_device *pwm_request(int pwm_id, const char *label)
{
struct pwm_device *pwm;
int found = 0;
mutex_lock(&pwm_lock);
list_for_each_entry(pwm, &pwm_list, node) {
if (pwm->pwm_id == pwm_id) {
found = 1;
break;
}
}
if (found) {
if (pwm->use_count == 0) {
pwm->use_count++;
pwm->label = label;
} else
pwm = ERR_PTR(-EBUSY);
} else
pwm = ERR_PTR(-ENOENT);
mutex_unlock(&pwm_lock);
return pwm;
}
EXPORT_SYMBOL(pwm_request);
void pwm_free(struct pwm_device *pwm)
{
mutex_lock(&pwm_lock);
if (pwm->use_count) {
pwm->use_count--;
pwm->label = NULL;
} else
pr_warning("PWM device already freed\n");
mutex_unlock(&pwm_lock);
}
EXPORT_SYMBOL(pwm_free);
static inline void __add_pwm(struct pwm_device *pwm)
{
mutex_lock(&pwm_lock);
list_add_tail(&pwm->node, &pwm_list);
mutex_unlock(&pwm_lock);
}
static struct pwm_device *pwm_probe(struct platform_device *pdev,
unsigned int pwm_id, struct pwm_device *parent_pwm)
{
struct pwm_device *pwm;
struct resource *r;
int ret = 0;
pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
if (pwm == NULL) {
dev_err(&pdev->dev, "failed to allocate memory\n");
return ERR_PTR(-ENOMEM);
}
pwm->clk = clk_get(&pdev->dev, "PWMCLK");
if (IS_ERR(pwm->clk)) {
ret = PTR_ERR(pwm->clk);
goto err_free;
}
pwm->clk_enabled = 0;
pwm->use_count = 0;
pwm->pwm_id = pwm_id;
pwm->pdev = pdev;
if (parent_pwm != NULL) {
/* registers for the second PWM has offset of 0x10 */
pwm->mmio_base = parent_pwm->mmio_base + 0x10;
__add_pwm(pwm);
return pwm;
}
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (r == NULL) {
dev_err(&pdev->dev, "no memory resource defined\n");
ret = -ENODEV;
goto err_free_clk;
}
r = request_mem_region(r->start, r->end - r->start + 1, pdev->name);
if (r == NULL) {
dev_err(&pdev->dev, "failed to request memory resource\n");
ret = -EBUSY;
goto err_free_clk;
}
pwm->mmio_base = ioremap(r->start, r->end - r->start + 1);
if (pwm->mmio_base == NULL) {
dev_err(&pdev->dev, "failed to ioremap() registers\n");
ret = -ENODEV;
goto err_free_mem;
}
__add_pwm(pwm);
platform_set_drvdata(pdev, pwm);
return pwm;
err_free_mem:
release_mem_region(r->start, r->end - r->start + 1);
err_free_clk:
clk_put(pwm->clk);
err_free:
kfree(pwm);
return ERR_PTR(ret);
}
static int __devinit pxa25x_pwm_probe(struct platform_device *pdev)
{
struct pwm_device *pwm = pwm_probe(pdev, pdev->id, NULL);
if (IS_ERR(pwm))
return PTR_ERR(pwm);
return 0;
}
static int __devinit pxa27x_pwm_probe(struct platform_device *pdev)
{
struct pwm_device *pwm;
pwm = pwm_probe(pdev, pdev->id, NULL);
if (IS_ERR(pwm))
return PTR_ERR(pwm);
pwm = pwm_probe(pdev, pdev->id + 2, pwm);
if (IS_ERR(pwm))
return PTR_ERR(pwm);
return 0;
}
static int __devexit pwm_remove(struct platform_device *pdev)
{
struct pwm_device *pwm;
struct resource *r;
pwm = platform_get_drvdata(pdev);
if (pwm == NULL)
return -ENODEV;
mutex_lock(&pwm_lock);
list_del(&pwm->node);
mutex_unlock(&pwm_lock);
iounmap(pwm->mmio_base);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(r->start, r->end - r->start + 1);
clk_put(pwm->clk);
kfree(pwm);
return 0;
}
static struct platform_driver pxa25x_pwm_driver = {
.driver = {
.name = "pxa25x-pwm",
},
.probe = pxa25x_pwm_probe,
.remove = __devexit_p(pwm_remove),
};
static struct platform_driver pxa27x_pwm_driver = {
.driver = {
.name = "pxa27x-pwm",
},
.probe = pxa27x_pwm_probe,
.remove = __devexit_p(pwm_remove),
};
static int __init pwm_init(void)
{
int ret = 0;
ret = platform_driver_register(&pxa25x_pwm_driver);
if (ret) {
printk(KERN_ERR "failed to register pxa25x_pwm_driver\n");
return ret;
}
ret = platform_driver_register(&pxa27x_pwm_driver);
if (ret) {
printk(KERN_ERR "failed to register pxa27x_pwm_driver\n");
return ret;
}
return ret;
}
arch_initcall(pwm_init);
static void __exit pwm_exit(void)
{
platform_driver_unregister(&pxa25x_pwm_driver);
platform_driver_unregister(&pxa27x_pwm_driver);
}
module_exit(pwm_exit);
MODULE_LICENSE("GPL v2");
arch/arm/mach-pxa/pxa25x.c
浏览文件 @ fdc614e8
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/arch/irqs.h> #include <asm/arch/irqs.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/mfp-pxa25x.h> #include <asm/arch/mfp-pxa25x.h>
#include <asm/arch/pm.h> #include <asm/arch/pm.h>
#include <asm/arch/dma.h> #include <asm/arch/dma.h>
...@@ -133,12 +134,12 @@ static struct clk pxa25x_clks[] = { ...@@ -133,12 +134,12 @@ static struct clk pxa25x_clks[] = {
INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev), INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev),
INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev),
INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev),
INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL),
/* /*
INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
*/ */
INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
...@@ -275,6 +276,8 @@ static struct platform_device *pxa25x_devices[] __initdata = { ...@@ -275,6 +276,8 @@ static struct platform_device *pxa25x_devices[] __initdata = {
&pxa25x_device_ssp, &pxa25x_device_ssp,
&pxa25x_device_nssp, &pxa25x_device_nssp,
&pxa25x_device_assp, &pxa25x_device_assp,
&pxa25x_device_pwm0,
&pxa25x_device_pwm1,
}; };
static struct sys_device pxa25x_sysdev[] = { static struct sys_device pxa25x_sysdev[] = {
......
arch/arm/mach-pxa/pxa27x.c
浏览文件 @ fdc614e8
...@@ -157,12 +157,13 @@ static struct clk pxa27x_clks[] = { ...@@ -157,12 +157,13 @@ static struct clk pxa27x_clks[] = {
INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
INIT_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
INIT_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL),
INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL), INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL),
/* /*
INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL),
INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL),
INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL), INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL), INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
...@@ -349,11 +350,14 @@ struct platform_device pxa27x_device_i2c_power = { ...@@ -349,11 +350,14 @@ struct platform_device pxa27x_device_i2c_power = {
void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info) void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{ {
local_irq_disable();
PCFR |= PCFR_PI2CEN;
local_irq_enable();
pxa27x_device_i2c_power.dev.platform_data = info; pxa27x_device_i2c_power.dev.platform_data = info;
} }
static struct platform_device *devices[] __initdata = { static struct platform_device *devices[] __initdata = {
&pxa_device_udc, /* &pxa_device_udc, The UDC driver is PXA25x only */
&pxa_device_ffuart, &pxa_device_ffuart,
&pxa_device_btuart, &pxa_device_btuart,
&pxa_device_stuart, &pxa_device_stuart,
...@@ -363,6 +367,8 @@ static struct platform_device *devices[] __initdata = { ...@@ -363,6 +367,8 @@ static struct platform_device *devices[] __initdata = {
&pxa27x_device_ssp1, &pxa27x_device_ssp1,
&pxa27x_device_ssp2, &pxa27x_device_ssp2,
&pxa27x_device_ssp3, &pxa27x_device_ssp3,
&pxa27x_device_pwm0,
&pxa27x_device_pwm1,
}; };
static struct sys_device pxa27x_sysdev[] = { static struct sys_device pxa27x_sysdev[] = {
......
arch/arm/mach-pxa/pxa3xx.c
浏览文件 @ fdc614e8
...@@ -239,6 +239,8 @@ static struct clk pxa3xx_clks[] = { ...@@ -239,6 +239,8 @@ static struct clk pxa3xx_clks[] = {
PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
...@@ -520,7 +522,7 @@ void __init pxa3xx_init_irq(void) ...@@ -520,7 +522,7 @@ void __init pxa3xx_init_irq(void)
*/ */
static struct platform_device *devices[] __initdata = { static struct platform_device *devices[] __initdata = {
&pxa_device_udc, /* &pxa_device_udc, The UDC driver is PXA25x only */
&pxa_device_ffuart, &pxa_device_ffuart,
&pxa_device_btuart, &pxa_device_btuart,
&pxa_device_stuart, &pxa_device_stuart,
...@@ -530,6 +532,8 @@ static struct platform_device *devices[] __initdata = { ...@@ -530,6 +532,8 @@ static struct platform_device *devices[] __initdata = {
&pxa27x_device_ssp2, &pxa27x_device_ssp2,
&pxa27x_device_ssp3, &pxa27x_device_ssp3,
&pxa3xx_device_ssp4, &pxa3xx_device_ssp4,
&pxa27x_device_pwm0,
&pxa27x_device_pwm1,
}; };
static struct sys_device pxa3xx_sysdev[] = { static struct sys_device pxa3xx_sysdev[] = {
......
arch/arm/mach-pxa/spitz_pm.c
浏览文件 @ fdc614e8
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#include <asm/arch/sharpsl.h> #include <asm/arch/sharpsl.h>
#include <asm/arch/spitz.h> #include <asm/arch/spitz.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h> #include <asm/arch/pxa2xx-gpio.h>
#include "sharpsl.h" #include "sharpsl.h"
...@@ -207,7 +208,9 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = { ...@@ -207,7 +208,9 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = {
.read_devdata = spitzpm_read_devdata, .read_devdata = spitzpm_read_devdata,
.charger_wakeup = spitz_charger_wakeup, .charger_wakeup = spitz_charger_wakeup,
.should_wakeup = spitz_should_wakeup, .should_wakeup = spitz_should_wakeup,
#ifdef CONFIG_BACKLIGHT_CORGI
.backlight_limit = corgibl_limit_intensity, .backlight_limit = corgibl_limit_intensity,
#endif
.charge_on_volt = SHARPSL_CHARGE_ON_VOLT, .charge_on_volt = SHARPSL_CHARGE_ON_VOLT,
.charge_on_temp = SHARPSL_CHARGE_ON_TEMP, .charge_on_temp = SHARPSL_CHARGE_ON_TEMP,
.charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH, .charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH,
...@@ -229,6 +232,10 @@ static int __devinit spitzpm_init(void) ...@@ -229,6 +232,10 @@ static int __devinit spitzpm_init(void)
{ {
int ret; int ret;
if (!machine_is_spitz() && !machine_is_akita()
&& !machine_is_borzoi())
return -ENODEV;
spitzpm_device = platform_device_alloc("sharpsl-pm", -1); spitzpm_device = platform_device_alloc("sharpsl-pm", -1);
if (!spitzpm_device) if (!spitzpm_device)
return -ENOMEM; return -ENOMEM;
......
arch/arm/mach-pxa/standby.S
浏览文件 @ fdc614e8
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
.text .text
...@@ -35,20 +36,20 @@ ENTRY(pxa_cpu_standby) ...@@ -35,20 +36,20 @@ ENTRY(pxa_cpu_standby)
#ifdef CONFIG_PXA3xx #ifdef CONFIG_PXA3xx
#define MDCNFG 0x0000 #define PXA3_MDCNFG 0x0000
#define MDCNFG_DMCEN (1 << 30) #define PXA3_MDCNFG_DMCEN (1 << 30)
#define DDR_HCAL 0x0060 #define PXA3_DDR_HCAL 0x0060
#define DDR_HCAL_HCRNG 0x1f #define PXA3_DDR_HCAL_HCRNG 0x1f
#define DDR_HCAL_HCPROG (1 << 28) #define PXA3_DDR_HCAL_HCPROG (1 << 28)
#define DDR_HCAL_HCEN (1 << 31) #define PXA3_DDR_HCAL_HCEN (1 << 31)
#define DMCIER 0x0070 #define PXA3_DMCIER 0x0070
#define DMCIER_EDLP (1 << 29) #define PXA3_DMCIER_EDLP (1 << 29)
#define DMCISR 0x0078 #define PXA3_DMCISR 0x0078
#define RCOMP 0x0100 #define PXA3_RCOMP 0x0100
#define RCOMP_SWEVAL (1 << 31) #define PXA3_RCOMP_SWEVAL (1 << 31)
ENTRY(pm_enter_standby_start) ENTRY(pm_enter_standby_start)
mov r1, #0xf6000000 @ DMEMC_REG_BASE (MDCNFG) mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG)
add r1, r1, #0x00100000 add r1, r1, #0x00100000
/* /*
...@@ -59,54 +60,54 @@ ENTRY(pm_enter_standby_start) ...@@ -59,54 +60,54 @@ ENTRY(pm_enter_standby_start)
* This also means that only the dynamic memory controller * This also means that only the dynamic memory controller
* can be reliably accessed in the code following standby. * can be reliably accessed in the code following standby.
*/ */
ldr r2, [r1] @ Dummy read MDCNFG ldr r2, [r1] @ Dummy read PXA3_MDCNFG
mcr p14, 0, r0, c7, c0, 0 mcr p14, 0, r0, c7, c0, 0
.rept 8 .rept 8
nop nop
.endr .endr
ldr r0, [r1, #DDR_HCAL] @ Clear (and wait for) HCEN ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
bic r0, r0, #DDR_HCAL_HCEN bic r0, r0, #PXA3_DDR_HCAL_HCEN
str r0, [r1, #DDR_HCAL] str r0, [r1, #PXA3_DDR_HCAL]
1: ldr r0, [r1, #DDR_HCAL] 1: ldr r0, [r1, #PXA3_DDR_HCAL]
tst r0, #DDR_HCAL_HCEN tst r0, #PXA3_DDR_HCAL_HCEN
bne 1b bne 1b
ldr r0, [r1, #RCOMP] @ Initiate RCOMP ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
orr r0, r0, #RCOMP_SWEVAL orr r0, r0, #PXA3_RCOMP_SWEVAL
str r0, [r1, #RCOMP] str r0, [r1, #PXA3_RCOMP]
mov r0, #~0 @ Clear interrupts mov r0, #~0 @ Clear interrupts
str r0, [r1, #DMCISR] str r0, [r1, #PXA3_DMCISR]
ldr r0, [r1, #DMCIER] @ set DMIER[EDLP] ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
orr r0, r0, #DMCIER_EDLP orr r0, r0, #PXA3_DMCIER_EDLP
str r0, [r1, #DMCIER] str r0, [r1, #PXA3_DMCIER]
ldr r0, [r1, #DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
bic r0, r0, #DDR_HCAL_HCRNG bic r0, r0, #PXA3_DDR_HCAL_HCRNG
orr r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG orr r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
str r0, [r1, #DDR_HCAL] str r0, [r1, #PXA3_DDR_HCAL]
1: ldr r0, [r1, #DMCISR] 1: ldr r0, [r1, #PXA3_DMCISR]
tst r0, #DMCIER_EDLP tst r0, #PXA3_DMCIER_EDLP
beq 1b beq 1b
ldr r0, [r1, #MDCNFG] @ set MDCNFG[DMCEN] ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
orr r0, r0, #MDCNFG_DMCEN orr r0, r0, #PXA3_MDCNFG_DMCEN
str r0, [r1, #MDCNFG] str r0, [r1, #PXA3_MDCNFG]
1: ldr r0, [r1, #MDCNFG] 1: ldr r0, [r1, #PXA3_MDCNFG]
tst r0, #MDCNFG_DMCEN tst r0, #PXA3_MDCNFG_DMCEN
beq 1b beq 1b
ldr r0, [r1, #DDR_HCAL] @ set DDR_HCAL[HCRNG] ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
orr r0, r0, #2 @ HCRNG orr r0, r0, #2 @ HCRNG
str r0, [r1, #DDR_HCAL] str r0, [r1, #PXA3_DDR_HCAL]
ldr r0, [r1, #DMCIER] @ Clear the interrupt ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt
bic r0, r0, #0x20000000 bic r0, r0, #0x20000000
str r0, [r1, #DMCIER] str r0, [r1, #PXA3_DMCIER]
mov pc, lr mov pc, lr
ENTRY(pm_enter_standby_end) ENTRY(pm_enter_standby_end)
......
arch/arm/mach-pxa/trizeps4.c
浏览文件 @ fdc614e8
...@@ -41,6 +41,7 @@ ...@@ -41,6 +41,7 @@
#include <asm/mach/flash.h> #include <asm/mach/flash.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h> #include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/trizeps4.h> #include <asm/arch/trizeps4.h>
#include <asm/arch/audio.h> #include <asm/arch/audio.h>
...@@ -487,6 +488,7 @@ static void __init trizeps4_map_io(void) ...@@ -487,6 +488,7 @@ static void __init trizeps4_map_io(void)
ConXS_BCR = trizeps_conxs_bcr; ConXS_BCR = trizeps_conxs_bcr;
#endif #endif
#warning FIXME - accessing PM registers directly is deprecated
PWER = 0x00000002; PWER = 0x00000002;
PFER = 0x00000000; PFER = 0x00000000;
PRER = 0x00000002; PRER = 0x00000002;
......
arch/arm/mach-pxa/zylonite.c
浏览文件 @ fdc614e8
...@@ -18,6 +18,7 @@ ...@@ -18,6 +18,7 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pwm_backlight.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
...@@ -28,12 +29,12 @@ ...@@ -28,12 +29,12 @@
#include <asm/arch/mmc.h> #include <asm/arch/mmc.h>
#include <asm/arch/pxa27x_keypad.h> #include <asm/arch/pxa27x_keypad.h>
#include "devices.h"
#include "generic.h" #include "generic.h"
#define MAX_SLOTS 3 #define MAX_SLOTS 3
struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS]; struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS];
int gpio_backlight;
int gpio_eth_irq; int gpio_eth_irq;
int wm9713_irq; int wm9713_irq;
...@@ -62,10 +63,20 @@ static struct platform_device smc91x_device = { ...@@ -62,10 +63,20 @@ static struct platform_device smc91x_device = {
}; };
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static void zylonite_backlight_power(int on) static struct platform_pwm_backlight_data zylonite_backlight_data = {
{ .pwm_id = 3,
gpio_set_value(gpio_backlight, on); .max_brightness = 100,
} .dft_brightness = 100,
.pwm_period_ns = 10000,
};
static struct platform_device zylonite_backlight_device = {
.name = "pwm-backlight",
.dev = {
.parent = &pxa27x_device_pwm1.dev,
.platform_data = &zylonite_backlight_data,
},
};
static struct pxafb_mode_info toshiba_ltm035a776c_mode = { static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
.pixclock = 110000, .pixclock = 110000,
...@@ -98,7 +109,6 @@ static struct pxafb_mode_info toshiba_ltm04c380k_mode = { ...@@ -98,7 +109,6 @@ static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
static struct pxafb_mach_info zylonite_toshiba_lcd_info = { static struct pxafb_mach_info zylonite_toshiba_lcd_info = {
.num_modes = 1, .num_modes = 1,
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
.pxafb_backlight_power = zylonite_backlight_power,
}; };
static struct pxafb_mode_info sharp_ls037_modes[] = { static struct pxafb_mode_info sharp_ls037_modes[] = {
...@@ -134,13 +144,11 @@ static struct pxafb_mach_info zylonite_sharp_lcd_info = { ...@@ -134,13 +144,11 @@ static struct pxafb_mach_info zylonite_sharp_lcd_info = {
.modes = sharp_ls037_modes, .modes = sharp_ls037_modes,
.num_modes = 2, .num_modes = 2,
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
.pxafb_backlight_power = zylonite_backlight_power,
}; };
static void __init zylonite_init_lcd(void) static void __init zylonite_init_lcd(void)
{ {
/* backlight GPIO: output, default on */ platform_device_register(&zylonite_backlight_device);
gpio_direction_output(gpio_backlight, 1);
if (lcd_id & 0x20) { if (lcd_id & 0x20) {
set_pxa_fb_info(&zylonite_sharp_lcd_info); set_pxa_fb_info(&zylonite_sharp_lcd_info);
......
arch/arm/mach-pxa/zylonite_pxa300.c
浏览文件 @ fdc614e8
...@@ -50,6 +50,7 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = { ...@@ -50,6 +50,7 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
GPIO75_LCD_BIAS, GPIO75_LCD_BIAS,
GPIO76_LCD_VSYNC, GPIO76_LCD_VSYNC,
GPIO127_LCD_CS_N, GPIO127_LCD_CS_N,
GPIO20_PWM3_OUT, /* backlight */
/* BTUART */ /* BTUART */
GPIO111_UART2_RTS, GPIO111_UART2_RTS,
...@@ -200,9 +201,6 @@ void __init zylonite_pxa300_init(void) ...@@ -200,9 +201,6 @@ void __init zylonite_pxa300_init(void)
/* detect LCD panel */ /* detect LCD panel */
zylonite_detect_lcd_panel(); zylonite_detect_lcd_panel();
/* GPIO pin assignment */
gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20);
/* MMC card detect & write protect for controller 0 */ /* MMC card detect & write protect for controller 0 */
zylonite_mmc_slot[0].gpio_cd = EXT_GPIO(0); zylonite_mmc_slot[0].gpio_cd = EXT_GPIO(0);
zylonite_mmc_slot[0].gpio_wp = EXT_GPIO(2); zylonite_mmc_slot[0].gpio_wp = EXT_GPIO(2);
......
arch/arm/mach-pxa/zylonite_pxa320.c
浏览文件 @ fdc614e8
...@@ -49,6 +49,7 @@ static mfp_cfg_t mfp_cfg[] __initdata = { ...@@ -49,6 +49,7 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
GPIO15_2_LCD_LCLK, GPIO15_2_LCD_LCLK,
GPIO16_2_LCD_PCLK, GPIO16_2_LCD_PCLK,
GPIO17_2_LCD_BIAS, GPIO17_2_LCD_BIAS,
GPIO14_PWM3_OUT, /* backlight */
/* FFUART */ /* FFUART */
GPIO41_UART1_RXD | MFP_LPM_EDGE_FALL, GPIO41_UART1_RXD | MFP_LPM_EDGE_FALL,
...@@ -187,7 +188,6 @@ void __init zylonite_pxa320_init(void) ...@@ -187,7 +188,6 @@ void __init zylonite_pxa320_init(void)
zylonite_detect_lcd_panel(); zylonite_detect_lcd_panel();
/* GPIO pin assignment */ /* GPIO pin assignment */
gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO14);
gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9); gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9);
/* MMC card detect & write protect for controller 0 */ /* MMC card detect & write protect for controller 0 */
......
drivers/i2c/busses/i2c-pxa.c
浏览文件 @ fdc614e8
...@@ -944,32 +944,6 @@ static const struct i2c_algorithm i2c_pxa_pio_algorithm = { ...@@ -944,32 +944,6 @@ static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
.functionality = i2c_pxa_functionality, .functionality = i2c_pxa_functionality,
}; };
static void i2c_pxa_enable(struct platform_device *dev)
{
if (cpu_is_pxa27x()) {
switch (dev->id) {
case 0:
pxa_gpio_mode(GPIO117_I2CSCL_MD);
pxa_gpio_mode(GPIO118_I2CSDA_MD);
break;
case 1:
local_irq_disable();
PCFR |= PCFR_PI2CEN;
local_irq_enable();
break;
}
}
}
static void i2c_pxa_disable(struct platform_device *dev)
{
if (cpu_is_pxa27x() && dev->id == 1) {
local_irq_disable();
PCFR &= ~PCFR_PI2CEN;
local_irq_enable();
}
}
#define res_len(r) ((r)->end - (r)->start + 1) #define res_len(r) ((r)->end - (r)->start + 1)
static int i2c_pxa_probe(struct platform_device *dev) static int i2c_pxa_probe(struct platform_device *dev)
{ {
...@@ -1035,7 +1009,6 @@ static int i2c_pxa_probe(struct platform_device *dev) ...@@ -1035,7 +1009,6 @@ static int i2c_pxa_probe(struct platform_device *dev)
#endif #endif
clk_enable(i2c->clk); clk_enable(i2c->clk);
i2c_pxa_enable(dev);
if (plat) { if (plat) {
i2c->adap.class = plat->class; i2c->adap.class = plat->class;
...@@ -1079,7 +1052,6 @@ static int i2c_pxa_probe(struct platform_device *dev) ...@@ -1079,7 +1052,6 @@ static int i2c_pxa_probe(struct platform_device *dev)
free_irq(irq, i2c); free_irq(irq, i2c);
ereqirq: ereqirq:
clk_disable(i2c->clk); clk_disable(i2c->clk);
i2c_pxa_disable(dev);
iounmap(i2c->reg_base); iounmap(i2c->reg_base);
eremap: eremap:
clk_put(i2c->clk); clk_put(i2c->clk);
...@@ -1102,7 +1074,6 @@ static int __exit i2c_pxa_remove(struct platform_device *dev) ...@@ -1102,7 +1074,6 @@ static int __exit i2c_pxa_remove(struct platform_device *dev)
clk_disable(i2c->clk); clk_disable(i2c->clk);
clk_put(i2c->clk); clk_put(i2c->clk);
i2c_pxa_disable(dev);
iounmap(i2c->reg_base); iounmap(i2c->reg_base);
release_mem_region(i2c->iobase, i2c->iosize); release_mem_region(i2c->iobase, i2c->iosize);
......
drivers/pcmcia/pxa2xx_cm_x270.c
浏览文件 @ fdc614e8
...@@ -18,6 +18,7 @@ ...@@ -18,6 +18,7 @@
#include <pcmcia/ss.h> #include <pcmcia/ss.h>
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-gpio.h> #include <asm/arch/pxa2xx-gpio.h>
...@@ -130,7 +131,7 @@ static void cmx270_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) ...@@ -130,7 +131,7 @@ static void cmx270_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
} }
static struct pcmcia_low_level cmx270_pcmcia_ops = { static struct pcmcia_low_level cmx270_pcmcia_ops __initdata = {
.owner = THIS_MODULE, .owner = THIS_MODULE,
.hw_init = cmx270_pcmcia_hw_init, .hw_init = cmx270_pcmcia_hw_init,
.hw_shutdown = cmx270_pcmcia_shutdown, .hw_shutdown = cmx270_pcmcia_shutdown,
...@@ -147,15 +148,21 @@ static int __init cmx270_pcmcia_init(void) ...@@ -147,15 +148,21 @@ static int __init cmx270_pcmcia_init(void)
{ {
int ret; int ret;
if (!machine_is_armcore())
return -ENODEV;
cmx270_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); cmx270_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
if (!cmx270_pcmcia_device) if (!cmx270_pcmcia_device)
return -ENOMEM; return -ENOMEM;
cmx270_pcmcia_device->dev.platform_data = &cmx270_pcmcia_ops; ret = platform_device_add_data(cmx270_pcmcia_device, &cmx270_pcmcia_ops,
sizeof(cmx270_pcmcia_ops));
if (ret == 0) {
printk(KERN_INFO "Registering cm-x270 PCMCIA interface.\n"); printk(KERN_INFO "Registering cm-x270 PCMCIA interface.\n");
ret = platform_device_add(cmx270_pcmcia_device); ret = platform_device_add(cmx270_pcmcia_device);
}
if (ret) if (ret)
platform_device_put(cmx270_pcmcia_device); platform_device_put(cmx270_pcmcia_device);
......
drivers/pcmcia/pxa2xx_mainstone.c
浏览文件 @ fdc614e8
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
#include <pcmcia/ss.h> #include <pcmcia/ss.h>
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
...@@ -136,7 +137,7 @@ static void mst_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) ...@@ -136,7 +137,7 @@ static void mst_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
{ {
} }
static struct pcmcia_low_level mst_pcmcia_ops = { static struct pcmcia_low_level mst_pcmcia_ops __initdata = {
.owner = THIS_MODULE, .owner = THIS_MODULE,
.hw_init = mst_pcmcia_hw_init, .hw_init = mst_pcmcia_hw_init,
.hw_shutdown = mst_pcmcia_hw_shutdown, .hw_shutdown = mst_pcmcia_hw_shutdown,
...@@ -153,12 +154,16 @@ static int __init mst_pcmcia_init(void) ...@@ -153,12 +154,16 @@ static int __init mst_pcmcia_init(void)
{ {
int ret; int ret;
if (!machine_is_mainstone())
return -ENODEV;
mst_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); mst_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
if (!mst_pcmcia_device) if (!mst_pcmcia_device)
return -ENOMEM; return -ENOMEM;
mst_pcmcia_device->dev.platform_data = &mst_pcmcia_ops; ret = platform_device_add_data(mst_pcmcia_device, &mst_pcmcia_ops,
sizeof(mst_pcmcia_ops));
if (ret == 0)
ret = platform_device_add(mst_pcmcia_device); ret = platform_device_add(mst_pcmcia_device);
if (ret) if (ret)
......
drivers/pcmcia/pxa2xx_sharpsl.c
浏览文件 @ fdc614e8
...@@ -222,7 +222,7 @@ static void sharpsl_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) ...@@ -222,7 +222,7 @@ static void sharpsl_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
sharpsl_pcmcia_init_reset(skt); sharpsl_pcmcia_init_reset(skt);
} }
static struct pcmcia_low_level sharpsl_pcmcia_ops = { static struct pcmcia_low_level sharpsl_pcmcia_ops __initdata = {
.owner = THIS_MODULE, .owner = THIS_MODULE,
.hw_init = sharpsl_pcmcia_hw_init, .hw_init = sharpsl_pcmcia_hw_init,
.hw_shutdown = sharpsl_pcmcia_hw_shutdown, .hw_shutdown = sharpsl_pcmcia_hw_shutdown,
...@@ -261,10 +261,12 @@ static int __init sharpsl_pcmcia_init(void) ...@@ -261,10 +261,12 @@ static int __init sharpsl_pcmcia_init(void)
if (!sharpsl_pcmcia_device) if (!sharpsl_pcmcia_device)
return -ENOMEM; return -ENOMEM;
sharpsl_pcmcia_device->dev.platform_data = &sharpsl_pcmcia_ops; ret = platform_device_add_data(sharpsl_pcmcia_device,
&sharpsl_pcmcia_ops, sizeof(sharpsl_pcmcia_ops));
if (ret == 0) {
sharpsl_pcmcia_device->dev.parent = platform_scoop_config->devs[0].dev; sharpsl_pcmcia_device->dev.parent = platform_scoop_config->devs[0].dev;
ret = platform_device_add(sharpsl_pcmcia_device); ret = platform_device_add(sharpsl_pcmcia_device);
}
if (ret) if (ret)
platform_device_put(sharpsl_pcmcia_device); platform_device_put(sharpsl_pcmcia_device);
......
drivers/usb/gadget/pxa27x_udc.c
浏览文件 @ fdc614e8
...@@ -38,7 +38,7 @@ ...@@ -38,7 +38,7 @@
#include <linux/usb.h> #include <linux/usb.h>
#include <linux/usb/ch9.h> #include <linux/usb/ch9.h>
#include <linux/usb/gadget.h> #include <linux/usb/gadget.h>
#include <asm/arch/pxa2xx-regs.h> /* FIXME: for PSSR */
#include <asm/arch/udc.h> #include <asm/arch/udc.h>
#include "pxa27x_udc.h" #include "pxa27x_udc.h"
...@@ -2359,6 +2359,7 @@ static int pxa_udc_resume(struct platform_device *_dev) ...@@ -2359,6 +2359,7 @@ static int pxa_udc_resume(struct platform_device *_dev)
* Software must configure the USB OTG pad, UDC, and UHC * Software must configure the USB OTG pad, UDC, and UHC
* to the state they were in before entering sleep mode. * to the state they were in before entering sleep mode.
*/ */
if (cpu_is_pxa27x())
PSSR |= PSSR_OTGPH; PSSR |= PSSR_OTGPH;
return 0; return 0;
......
drivers/usb/gadget/pxa27x_udc.h
浏览文件 @ fdc614e8
...@@ -484,12 +484,4 @@ static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget) ...@@ -484,12 +484,4 @@ static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget)
#define ep_warn(ep, fmt, arg...) \ #define ep_warn(ep, fmt, arg...) \
dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg) dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg)
/*
* Cannot include pxa-regs.h, as register names are similar.
* So PSSR is redefined here. This should be removed once UDC registers will
* be gone from pxa-regs.h.
*/
#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status */
#define PSSR_OTGPH (1 << 6) /* OTG Peripheral Hold */
#endif /* __LINUX_USB_GADGET_PXA27X_H */ #endif /* __LINUX_USB_GADGET_PXA27X_H */
drivers/usb/gadget/pxa2xx_udc.c
浏览文件 @ fdc614e8
...@@ -46,19 +46,25 @@ ...@@ -46,19 +46,25 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/seq_file.h> #include <linux/seq_file.h>
#include <linux/debugfs.h> #include <linux/debugfs.h>
#include <linux/io.h>
#include <asm/byteorder.h> #include <asm/byteorder.h>
#include <asm/dma.h> #include <asm/dma.h>
#include <asm/gpio.h> #include <asm/gpio.h>
#include <asm/io.h>
#include <asm/system.h> #include <asm/system.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/unaligned.h> #include <asm/unaligned.h>
#include <asm/hardware.h>
#include <linux/usb/ch9.h> #include <linux/usb/ch9.h>
#include <linux/usb/gadget.h> #include <linux/usb/gadget.h>
/*
* This driver is PXA25x only. Grab the right register definitions.
*/
#ifdef CONFIG_ARCH_PXA
#include <asm/arch/pxa25x-udc.h>
#endif
#include <asm/mach/udc_pxa2xx.h> #include <asm/mach/udc_pxa2xx.h>
......
drivers/usb/host/ohci-pxa27x.c
浏览文件 @ fdc614e8
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h> /* FIXME: for PSSR */
#include <asm/arch/ohci.h> #include <asm/arch/ohci.h>
#define PXA_UHC_MAX_PORTNUM 3 #define PXA_UHC_MAX_PORTNUM 3
...@@ -104,7 +105,7 @@ static int pxa27x_start_hc(struct device *dev) ...@@ -104,7 +105,7 @@ static int pxa27x_start_hc(struct device *dev)
UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
/* Clear any OTG Pin Hold */ /* Clear any OTG Pin Hold */
if (PSSR & PSSR_OTGPH) if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
PSSR |= PSSR_OTGPH; PSSR |= PSSR_OTGPH;
return 0; return 0;
......
drivers/video/backlight/Kconfig
浏览文件 @ fdc614e8
...@@ -112,3 +112,10 @@ config BACKLIGHT_CARILLO_RANCH ...@@ -112,3 +112,10 @@ config BACKLIGHT_CARILLO_RANCH
help help
If you have a Intel LE80578 (Carillo Ranch) say Y to enable the If you have a Intel LE80578 (Carillo Ranch) say Y to enable the
backlight driver. backlight driver.
config BACKLIGHT_PWM
tristate "Generic PWM based Backlight Driver"
depends on BACKLIGHT_CLASS_DEVICE && HAVE_PWM
help
If you have a LCD backlight adjustable by PWM, say Y to enable
this driver.
drivers/video/backlight/Makefile
浏览文件 @ fdc614e8
...@@ -10,3 +10,4 @@ obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o ...@@ -10,3 +10,4 @@ obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o
obj-$(CONFIG_BACKLIGHT_OMAP1) += omap1_bl.o obj-$(CONFIG_BACKLIGHT_OMAP1) += omap1_bl.o
obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o
obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o
obj-$(CONFIG_BACKLIGHT_PWM) += pwm_bl.o
drivers/video/backlight/pwm_bl.c 0 → 100644
浏览文件 @ fdc614e8
/*
* linux/drivers/video/backlight/pwm_bl.c
*
* simple PWM based backlight control, board code has to setup
* 1) pin configuration so PWM waveforms can output
* 2) platform_data casts to the PWM id (0/1/2/3 on PXA)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <linux/backlight.h>
#include <linux/err.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
struct pwm_bl_data {
struct pwm_device *pwm;
unsigned int period;
int (*notify)(int brightness);
};
static int pwm_backlight_update_status(struct backlight_device *bl)
{
struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
int brightness = bl->props.brightness;
int max = bl->props.max_brightness;
if (bl->props.power != FB_BLANK_UNBLANK)
brightness = 0;
if (bl->props.fb_blank != FB_BLANK_UNBLANK)
brightness = 0;
if (pb->notify)
brightness = pb->notify(brightness);
if (brightness == 0) {
pwm_config(pb->pwm, 0, pb->period);
pwm_disable(pb->pwm);
} else {
pwm_config(pb->pwm, brightness * pb->period / max, pb->period);
pwm_enable(pb->pwm);
}
return 0;
}
static int pwm_backlight_get_brightness(struct backlight_device *bl)
{
return bl->props.brightness;
}
static struct backlight_ops pwm_backlight_ops = {
.update_status = pwm_backlight_update_status,
.get_brightness = pwm_backlight_get_brightness,
};
static int pwm_backlight_probe(struct platform_device *pdev)
{
struct platform_pwm_backlight_data *data = pdev->dev.platform_data;
struct backlight_device *bl;
struct pwm_bl_data *pb;
int ret;
if (!data)
return -EINVAL;
if (data->init) {
ret = data->init(&pdev->dev);
if (ret < 0)
return ret;
}
pb = kzalloc(sizeof(*pb), GFP_KERNEL);
if (!pb) {
ret = -ENOMEM;
goto err_alloc;
}
pb->period = data->pwm_period_ns;
pb->notify = data->notify;
pb->pwm = pwm_request(data->pwm_id, "backlight");
if (IS_ERR(pb->pwm)) {
dev_err(&pdev->dev, "unable to request PWM for backlight\n");
ret = PTR_ERR(pb->pwm);
goto err_pwm;
}
bl = backlight_device_register(pdev->name, &pdev->dev,
pb, &pwm_backlight_ops);
if (IS_ERR(bl)) {
dev_err(&pdev->dev, "failed to register backlight\n");
ret = PTR_ERR(bl);
goto err_bl;
}
bl->props.max_brightness = data->max_brightness;
bl->props.brightness = data->dft_brightness;
backlight_update_status(bl);
platform_set_drvdata(pdev, bl);
return 0;
err_bl:
pwm_free(pb->pwm);
err_pwm:
kfree(pb);
err_alloc:
if (data->exit)
data->exit(&pdev->dev);
return ret;
}
static int pwm_backlight_remove(struct platform_device *pdev)
{
struct platform_pwm_backlight_data *data = pdev->dev.platform_data;
struct backlight_device *bl = platform_get_drvdata(pdev);
struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
backlight_device_unregister(bl);
pwm_config(pb->pwm, 0, pb->period);
pwm_disable(pb->pwm);
pwm_free(pb->pwm);
kfree(pb);
if (data->exit)
data->exit(&pdev->dev);
return 0;
}
#ifdef CONFIG_PM
static int pwm_backlight_suspend(struct platform_device *pdev,
pm_message_t state)
{
struct backlight_device *bl = platform_get_drvdata(pdev);
struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
pwm_config(pb->pwm, 0, pb->period);
pwm_disable(pb->pwm);
return 0;
}
static int pwm_backlight_resume(struct platform_device *pdev)
{
struct backlight_device *bl = platform_get_drvdata(pdev);
backlight_update_status(bl);
return 0;
}
#else
#define pwm_backlight_suspend NULL
#define pwm_backlight_resume NULL
#endif
static struct platform_driver pwm_backlight_driver = {
.driver = {
.name = "pwm-backlight",
.owner = THIS_MODULE,
},
.probe = pwm_backlight_probe,
.remove = pwm_backlight_remove,
.suspend = pwm_backlight_suspend,
.resume = pwm_backlight_resume,
};
static int __init pwm_backlight_init(void)
{
return platform_driver_register(&pwm_backlight_driver);
}
module_init(pwm_backlight_init);
static void __exit pwm_backlight_exit(void)
{
platform_driver_unregister(&pwm_backlight_driver);
}
module_exit(pwm_backlight_exit);
MODULE_DESCRIPTION("PWM based Backlight Driver");
MODULE_LICENSE("GPL");
include/asm-arm/arch-pxa/pxa-regs.h
浏览文件 @ fdc614e8
...@@ -599,418 +599,6 @@ ...@@ -599,418 +599,6 @@
#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
/*
* USB Device Controller
* PXA25x and PXA27x USB device controller registers are different.
*/
#if defined(CONFIG_PXA25x)
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
#define UDCCR __REG(0x40600000) /* UDC Control Register */
#define UDCCR_UDE (1 << 0) /* UDC enable */
#define UDCCR_UDA (1 << 1) /* UDC active */
#define UDCCR_RSM (1 << 2) /* Device resume */
#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
#define UDCCS0_IPR (1 << 1) /* IN packet ready */
#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
#define UDCCS0_SST (1 << 4) /* Sent stall */
#define UDCCS0_FST (1 << 5) /* Force stall */
#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
#define UDCCS0_SA (1 << 7) /* Setup active */
/* Bulk IN - Endpoint 1,6,11 */
#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_BI_SST (1 << 4) /* Sent stall */
#define UDCCS_BI_FST (1 << 5) /* Force stall */
#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
/* Bulk OUT - Endpoint 2,7,12 */
#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_BO_DME (1 << 3) /* DMA enable */
#define UDCCS_BO_SST (1 << 4) /* Sent stall */
#define UDCCS_BO_FST (1 << 5) /* Force stall */
#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
/* Isochronous IN - Endpoint 3,8,13 */
#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
/* Isochronous OUT - Endpoint 4,9,14 */
#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
#define UDCCS_IO_DME (1 << 3) /* DMA enable */
#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
/* Interrupt IN - Endpoint 5,10,15 */
#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_INT_SST (1 << 4) /* Sent stall */
#define UDCCS_INT_FST (1 << 5) /* Force stall */
#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
#elif defined(CONFIG_PXA27x)
#define UDCCR __REG(0x40600000) /* UDC Control Register */
#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
Protocol Port Support */
#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
Support */
#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
Enable */
#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
#define UDCCR_ACN_S 11
#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
#define UDCCR_AIN_S 8
#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
Setting Number */
#define UDCCR_AAISN_S 5
#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
Configuration */
#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
Error */
#define UDCCR_UDR (1 << 2) /* UDC Resume */
#define UDCCR_UDA (1 << 1) /* UDC Active */
#define UDCCR_UDE (1 << 0) /* UDC Enable */
#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
#define UDC_INT_FIFOERROR (0x2)
#define UDC_INT_PACKETCMP (0x1)
#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
Rising Edge Interrupt Enable */
#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
Falling Edge Interrupt Enable */
#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
Interrupt Enable */
#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
Interrupt Enable */
#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
Interrupt Enable */
#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
Interrupt Enable */
#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
Edge Interrupt Enable */
#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
Edge Interrupt Enable */
#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
Interrupt Enable */
#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
#define UDCCSR0_SA (1 << 7) /* Setup Active */
#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
#define UDCCSR0_FST (1 << 5) /* Force Stall */
#define UDCCSR0_SST (1 << 4) /* Sent Stall */
#define UDCCSR0_DME (1 << 3) /* DMA Enable */
#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
#define UDCCSR_FST (1 << 5) /* Force STALL */
#define UDCCSR_SST (1 << 4) /* Sent STALL */
#define UDCCSR_DME (1 << 3) /* DMA Enable */
#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
#define UDCCSR_PC (1 << 1) /* Packet Complete */
#define UDCCSR_FS (1 << 0) /* FIFO needs service */
#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
#define UDCDN(x) __REG2(0x40600300, (x)<<2)
#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
#define UDCCN(x) __REG2(0x40600400, (x)<<2)
#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
#define UDCCONR_CN_S (25)
#define UDCCONR_IN (0x07 << 22) /* Interface Number */
#define UDCCONR_IN_S (22)
#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
#define UDCCONR_AISN_S (19)
#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
#define UDCCONR_EN_S (15)
#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
#define UDCCONR_ET_S (13)
#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
#define UDCCONR_MPS_S (2)
#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
#define UDC_INT_FIFOERROR (0x2)
#define UDC_INT_PACKETCMP (0x1)
#define UDC_FNR_MASK (0x7ff)
#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
#define UDC_BCR_MASK (0x3ff)
#endif
/* /*
* Fast Infrared Communication Port * Fast Infrared Communication Port
*/ */
...@@ -1237,120 +825,9 @@ ...@@ -1237,120 +825,9 @@
#endif #endif
/* /*
* Power Manager * Power Manager - see pxa2xx-regs.h
*/ */
#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
#define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */
#define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */
#define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */
#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
#define PCMD(x) __REG2(0x40F00080, (x)<<2)
#define PCMD0 __REG(0x40F00080 + 0 * 4)
#define PCMD1 __REG(0x40F00080 + 1 * 4)
#define PCMD2 __REG(0x40F00080 + 2 * 4)
#define PCMD3 __REG(0x40F00080 + 3 * 4)
#define PCMD4 __REG(0x40F00080 + 4 * 4)
#define PCMD5 __REG(0x40F00080 + 5 * 4)
#define PCMD6 __REG(0x40F00080 + 6 * 4)
#define PCMD7 __REG(0x40F00080 + 7 * 4)
#define PCMD8 __REG(0x40F00080 + 8 * 4)
#define PCMD9 __REG(0x40F00080 + 9 * 4)
#define PCMD10 __REG(0x40F00080 + 10 * 4)
#define PCMD11 __REG(0x40F00080 + 11 * 4)
#define PCMD12 __REG(0x40F00080 + 12 * 4)
#define PCMD13 __REG(0x40F00080 + 13 * 4)
#define PCMD14 __REG(0x40F00080 + 14 * 4)
#define PCMD15 __REG(0x40F00080 + 15 * 4)
#define PCMD16 __REG(0x40F00080 + 16 * 4)
#define PCMD17 __REG(0x40F00080 + 17 * 4)
#define PCMD18 __REG(0x40F00080 + 18 * 4)
#define PCMD19 __REG(0x40F00080 + 19 * 4)
#define PCMD20 __REG(0x40F00080 + 20 * 4)
#define PCMD21 __REG(0x40F00080 + 21 * 4)
#define PCMD22 __REG(0x40F00080 + 22 * 4)
#define PCMD23 __REG(0x40F00080 + 23 * 4)
#define PCMD24 __REG(0x40F00080 + 24 * 4)
#define PCMD25 __REG(0x40F00080 + 25 * 4)
#define PCMD26 __REG(0x40F00080 + 26 * 4)
#define PCMD27 __REG(0x40F00080 + 27 * 4)
#define PCMD28 __REG(0x40F00080 + 28 * 4)
#define PCMD29 __REG(0x40F00080 + 29 * 4)
#define PCMD30 __REG(0x40F00080 + 30 * 4)
#define PCMD31 __REG(0x40F00080 + 31 * 4)
#define PCMD_MBC (1<<12)
#define PCMD_DCE (1<<11)
#define PCMD_LC (1<<10)
/* FIXME: PCMD_SQC need be checked. */
#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
bit 9 should be 0 all day. */
#define PVCR_VCSA (0x1<<14)
#define PVCR_CommandDelay (0xf80)
#define PCFR_PI2C_EN (0x1 << 6)
#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
#define PSSR_RDH (1 << 5) /* Read Disable Hold */
#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
#define PSSR_STS (1 << 3) /* Standby Mode Status */
#define PSSR_VFS (1 << 2) /* VDD Fault Status */
#define PSSR_BFS (1 << 1) /* Battery Fault Status */
#define PSSR_SSS (1 << 0) /* Software Sleep Status */
#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
#define PCFR_RO (1 << 15) /* RDH Override */
#define PCFR_PO (1 << 14) /* PH Override */
#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
#define RCSR_GPR (1 << 3) /* GPIO Reset */
#define RCSR_SMR (1 << 2) /* Sleep Mode */
#define RCSR_WDR (1 << 1) /* Watchdog Reset */
#define RCSR_HWR (1 << 0) /* Hardware Reset */
#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
/* /*
* SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
*/ */
...@@ -1360,52 +837,9 @@ ...@@ -1360,52 +837,9 @@
*/ */
/* /*
* Core Clock * Core Clock - see include/asm-arm/arch-pxa/pxa2xx-regs.h
*/ */
#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
#define CKEN __REG(0x41300004) /* Clock Enable Register */
#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
#define CKEN_IM (20) /* Internal Memory Clock Enable */
#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
#define CKEN_USIM (18) /* USIM Unit Clock Enable */
#define CKEN_MSL (17) /* MSL Unit Clock Enable */
#define CKEN_LCD (16) /* LCD Unit Clock Enable */
#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
#define CKEN_I2C (14) /* I2C Unit Clock Enable */
#define CKEN_FICP (13) /* FICP Unit Clock Enable */
#define CKEN_MMC (12) /* MMC Unit Clock Enable */
#define CKEN_USB (11) /* USB Unit Clock Enable */
#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
#define CKEN_I2S (8) /* I2S Unit Clock Enable */
#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
#define CKEN_STUART (5) /* STUART Unit Clock Enable */
#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
#define CKEN_SSP (3) /* SSP Unit Clock Enable */
#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
#ifdef CONFIG_PXA27x #ifdef CONFIG_PXA27x
/* Camera Interface */ /* Camera Interface */
......
include/asm-arm/arch-pxa/pxa25x-udc.h 0 → 100644
浏览文件 @ fdc614e8
#ifndef _ASM_ARCH_PXA25X_UDC_H
#define _ASM_ARCH_PXA25X_UDC_H
#ifdef _ASM_ARCH_PXA27X_UDC_H
#error You can't include both PXA25x and PXA27x UDC support
#endif
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
#define UDCCR __REG(0x40600000) /* UDC Control Register */
#define UDCCR_UDE (1 << 0) /* UDC enable */
#define UDCCR_UDA (1 << 1) /* UDC active */
#define UDCCR_RSM (1 << 2) /* Device resume */
#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
#define UDCCS0_IPR (1 << 1) /* IN packet ready */
#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
#define UDCCS0_SST (1 << 4) /* Sent stall */
#define UDCCS0_FST (1 << 5) /* Force stall */
#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
#define UDCCS0_SA (1 << 7) /* Setup active */
/* Bulk IN - Endpoint 1,6,11 */
#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_BI_SST (1 << 4) /* Sent stall */
#define UDCCS_BI_FST (1 << 5) /* Force stall */
#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
/* Bulk OUT - Endpoint 2,7,12 */
#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_BO_DME (1 << 3) /* DMA enable */
#define UDCCS_BO_SST (1 << 4) /* Sent stall */
#define UDCCS_BO_FST (1 << 5) /* Force stall */
#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
/* Isochronous IN - Endpoint 3,8,13 */
#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
/* Isochronous OUT - Endpoint 4,9,14 */
#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
#define UDCCS_IO_DME (1 << 3) /* DMA enable */
#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
/* Interrupt IN - Endpoint 5,10,15 */
#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_INT_SST (1 << 4) /* Sent stall */
#define UDCCS_INT_FST (1 << 5) /* Force stall */
#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
#endif
include/asm-arm/arch-pxa/pxa27x-udc.h 0 → 100644
浏览文件 @ fdc614e8
#ifndef _ASM_ARCH_PXA27X_UDC_H
#define _ASM_ARCH_PXA27X_UDC_H
#ifdef _ASM_ARCH_PXA25X_UDC_H
#error You cannot include both PXA25x and PXA27x UDC support
#endif
#define UDCCR __REG(0x40600000) /* UDC Control Register */
#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
Protocol Port Support */
#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
Support */
#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
Enable */
#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
#define UDCCR_ACN_S 11
#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
#define UDCCR_AIN_S 8
#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
Setting Number */
#define UDCCR_AAISN_S 5
#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
Configuration */
#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
Error */
#define UDCCR_UDR (1 << 2) /* UDC Resume */
#define UDCCR_UDA (1 << 1) /* UDC Active */
#define UDCCR_UDE (1 << 0) /* UDC Enable */
#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
#define UDC_INT_FIFOERROR (0x2)
#define UDC_INT_PACKETCMP (0x1)
#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
Rising Edge Interrupt Enable */
#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
Falling Edge Interrupt Enable */
#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
Interrupt Enable */
#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
Interrupt Enable */
#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
Interrupt Enable */
#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
Interrupt Enable */
#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
Edge Interrupt Enable */
#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
Edge Interrupt Enable */
#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
Interrupt Enable */
#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
#define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
#define UDCCSR0_SA (1 << 7) /* Setup Active */
#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
#define UDCCSR0_FST (1 << 5) /* Force Stall */
#define UDCCSR0_SST (1 << 4) /* Sent Stall */
#define UDCCSR0_DME (1 << 3) /* DMA Enable */
#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
#define UDCCSR_FST (1 << 5) /* Force STALL */
#define UDCCSR_SST (1 << 4) /* Sent STALL */
#define UDCCSR_DME (1 << 3) /* DMA Enable */
#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
#define UDCCSR_PC (1 << 1) /* Packet Complete */
#define UDCCSR_FS (1 << 0) /* FIFO needs service */
#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
#define UDCDN(x) __REG2(0x40600300, (x)<<2)
#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
#define UDCCN(x) __REG2(0x40600400, (x)<<2)
#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
#define UDCCONR_CN_S (25)
#define UDCCONR_IN (0x07 << 22) /* Interface Number */
#define UDCCONR_IN_S (22)
#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
#define UDCCONR_AISN_S (19)
#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
#define UDCCONR_EN_S (15)
#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
#define UDCCONR_ET_S (13)
#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
#define UDCCONR_MPS_S (2)
#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
#define UDC_INT_FIFOERROR (0x2)
#define UDC_INT_PACKETCMP (0x1)
#define UDC_FNR_MASK (0x7ff)
#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
#define UDC_BCR_MASK (0x3ff)
#endif
include/asm-arm/arch-pxa/pxa2xx-regs.h
浏览文件 @ fdc614e8
...@@ -81,4 +81,166 @@ ...@@ -81,4 +81,166 @@
#endif #endif
/*
* Power Manager
*/
#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
#define PCMD(x) __REG2(0x40F00080, (x)<<2)
#define PCMD0 __REG(0x40F00080 + 0 * 4)
#define PCMD1 __REG(0x40F00080 + 1 * 4)
#define PCMD2 __REG(0x40F00080 + 2 * 4)
#define PCMD3 __REG(0x40F00080 + 3 * 4)
#define PCMD4 __REG(0x40F00080 + 4 * 4)
#define PCMD5 __REG(0x40F00080 + 5 * 4)
#define PCMD6 __REG(0x40F00080 + 6 * 4)
#define PCMD7 __REG(0x40F00080 + 7 * 4)
#define PCMD8 __REG(0x40F00080 + 8 * 4)
#define PCMD9 __REG(0x40F00080 + 9 * 4)
#define PCMD10 __REG(0x40F00080 + 10 * 4)
#define PCMD11 __REG(0x40F00080 + 11 * 4)
#define PCMD12 __REG(0x40F00080 + 12 * 4)
#define PCMD13 __REG(0x40F00080 + 13 * 4)
#define PCMD14 __REG(0x40F00080 + 14 * 4)
#define PCMD15 __REG(0x40F00080 + 15 * 4)
#define PCMD16 __REG(0x40F00080 + 16 * 4)
#define PCMD17 __REG(0x40F00080 + 17 * 4)
#define PCMD18 __REG(0x40F00080 + 18 * 4)
#define PCMD19 __REG(0x40F00080 + 19 * 4)
#define PCMD20 __REG(0x40F00080 + 20 * 4)
#define PCMD21 __REG(0x40F00080 + 21 * 4)
#define PCMD22 __REG(0x40F00080 + 22 * 4)
#define PCMD23 __REG(0x40F00080 + 23 * 4)
#define PCMD24 __REG(0x40F00080 + 24 * 4)
#define PCMD25 __REG(0x40F00080 + 25 * 4)
#define PCMD26 __REG(0x40F00080 + 26 * 4)
#define PCMD27 __REG(0x40F00080 + 27 * 4)
#define PCMD28 __REG(0x40F00080 + 28 * 4)
#define PCMD29 __REG(0x40F00080 + 29 * 4)
#define PCMD30 __REG(0x40F00080 + 30 * 4)
#define PCMD31 __REG(0x40F00080 + 31 * 4)
#define PCMD_MBC (1<<12)
#define PCMD_DCE (1<<11)
#define PCMD_LC (1<<10)
/* FIXME: PCMD_SQC need be checked. */
#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
bit 9 should be 0 all day. */
#define PVCR_VCSA (0x1<<14)
#define PVCR_CommandDelay (0xf80)
#define PCFR_PI2C_EN (0x1 << 6)
#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
#define PSSR_RDH (1 << 5) /* Read Disable Hold */
#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
#define PSSR_STS (1 << 3) /* Standby Mode Status */
#define PSSR_VFS (1 << 2) /* VDD Fault Status */
#define PSSR_BFS (1 << 1) /* Battery Fault Status */
#define PSSR_SSS (1 << 0) /* Software Sleep Status */
#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
#define PCFR_RO (1 << 15) /* RDH Override */
#define PCFR_PO (1 << 14) /* PH Override */
#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
#define RCSR_GPR (1 << 3) /* GPIO Reset */
#define RCSR_SMR (1 << 2) /* Sleep Mode */
#define RCSR_WDR (1 << 1) /* Watchdog Reset */
#define RCSR_HWR (1 << 0) /* Hardware Reset */
#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
/*
* PXA2xx specific Core clock definitions
*/
#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
#define CKEN __REG(0x41300004) /* Clock Enable Register */
#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
#define CKEN_IM (20) /* Internal Memory Clock Enable */
#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
#define CKEN_USIM (18) /* USIM Unit Clock Enable */
#define CKEN_MSL (17) /* MSL Unit Clock Enable */
#define CKEN_LCD (16) /* LCD Unit Clock Enable */
#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
#define CKEN_I2C (14) /* I2C Unit Clock Enable */
#define CKEN_FICP (13) /* FICP Unit Clock Enable */
#define CKEN_MMC (12) /* MMC Unit Clock Enable */
#define CKEN_USB (11) /* USB Unit Clock Enable */
#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
#define CKEN_I2S (8) /* I2S Unit Clock Enable */
#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
#define CKEN_STUART (5) /* STUART Unit Clock Enable */
#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
#define CKEN_SSP (3) /* SSP Unit Clock Enable */
#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
#endif #endif
include/asm-arm/arch-pxa/system.h
浏览文件 @ fdc614e8
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
#include <asm/proc-fns.h> #include <asm/proc-fns.h>
#include "hardware.h" #include "hardware.h"
#include "pxa2xx-regs.h"
#include "pxa-regs.h" #include "pxa-regs.h"
static inline void arch_idle(void) static inline void arch_idle(void)
......
include/asm-arm/arch-pxa/zylonite.h
浏览文件 @ fdc614e8
...@@ -15,7 +15,6 @@ struct platform_mmc_slot { ...@@ -15,7 +15,6 @@ struct platform_mmc_slot {
extern struct platform_mmc_slot zylonite_mmc_slot[]; extern struct platform_mmc_slot zylonite_mmc_slot[];
extern int gpio_backlight;
extern int gpio_eth_irq; extern int gpio_eth_irq;
extern int wm9713_irq; extern int wm9713_irq;
......
include/linux/pwm.h 0 → 100644
浏览文件 @ fdc614e8
#ifndef __LINUX_PWM_H
#define __LINUX_PWM_H
struct pwm_device;
/*
* pwm_request - request a PWM device
*/
struct pwm_device *pwm_request(int pwm_id, const char *label);
/*
* pwm_free - free a PWM device
*/
void pwm_free(struct pwm_device *pwm);
/*
* pwm_config - change a PWM device configuration
*/
int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns);
/*
* pwm_enable - start a PWM output toggling
*/
int pwm_enable(struct pwm_device *pwm);
/*
* pwm_disable - stop a PWM output toggling
*/
void pwm_disable(struct pwm_device *pwm);
#endif /* __ASM_ARCH_PWM_H */
include/linux/pwm_backlight.h 0 → 100644
浏览文件 @ fdc614e8
/*
* Generic PWM backlight driver data - see drivers/video/backlight/pwm_bl.c
*/
#ifndef __LINUX_PWM_BACKLIGHT_H
#define __LINUX_PWM_BACKLIGHT_H
struct platform_pwm_backlight_data {
int pwm_id;
unsigned int max_brightness;
unsigned int dft_brightness;
unsigned int pwm_period_ns;
int (*init)(struct device *dev);
int (*notify)(int brightness);
void (*exit)(struct device *dev);
};
#endif
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