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kernel_linux
提交 f7a3427f 编写于 作者: L Linus Walleij
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Merge branch 'pinmux/next/fixes' of git://linuxtv.org/pinchartl/fbdev into devel 

Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
上级 da52faa5 e120cacf
隐藏空白更改
内联 并排
Showing with 1132 addition and 668 deletion
drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
浏览文件 @ f7a3427f
......@@ -21,7 +21,6 @@
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <mach/irqs.h>
#include <mach/r8a73a4.h>
#include "core.h"
#include "sh_pfc.h"
......
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
浏览文件 @ f7a3427f
......@@ -22,7 +22,6 @@
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <mach/r8a7740.h>
#include <mach/irqs.h>
#include "core.h"
......
drivers/pinctrl/sh-pfc/pfc-r8a7779.c
浏览文件 @ f7a3427f
......@@ -1674,6 +1674,79 @@ static const unsigned int hspi2_b_pins[] = {
static const unsigned int hspi2_b_mux[] = {
HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
};
/* - I2C1 ------------------------------------------------------------------ */
static const unsigned int i2c1_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
};
static const unsigned int i2c1_mux[] = {
SCL1_MARK, SDA1_MARK,
};
static const unsigned int i2c1_b_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
};
static const unsigned int i2c1_b_mux[] = {
SCL1_B_MARK, SDA1_B_MARK,
};
static const unsigned int i2c1_c_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
};
static const unsigned int i2c1_c_mux[] = {
SCL1_C_MARK, SDA1_C_MARK,
};
static const unsigned int i2c1_d_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
};
static const unsigned int i2c1_d_mux[] = {
SCL1_D_MARK, SDA1_D_MARK,
};
/* - I2C2 ------------------------------------------------------------------ */
static const unsigned int i2c2_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26),
};
static const unsigned int i2c2_mux[] = {
SCL2_MARK, SDA2_MARK,
};
static const unsigned int i2c2_b_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
};
static const unsigned int i2c2_b_mux[] = {
SCL2_B_MARK, SDA2_B_MARK,
};
static const unsigned int i2c2_c_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 30),
};
static const unsigned int i2c2_c_mux[] = {
SCL2_C_MARK, SDA2_C_MARK,
};
static const unsigned int i2c2_d_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
};
static const unsigned int i2c2_d_mux[] = {
SCL2_D_MARK, SDA2_D_MARK,
};
/* - I2C3 ------------------------------------------------------------------ */
static const unsigned int i2c3_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 30),
};
static const unsigned int i2c3_mux[] = {
SCL3_MARK, SDA3_MARK,
};
static const unsigned int i2c3_b_pins[] = {
/* SCL, SDA, */
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30),
};
static const unsigned int i2c3_b_mux[] = {
SCL3_B_MARK, SDA3_B_MARK,
};
/* - INTC ------------------------------------------------------------------- */
static const unsigned int intc_irq0_pins[] = {
/* IRQ */
......@@ -2543,6 +2616,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(hspi1_d),
SH_PFC_PIN_GROUP(hspi2),
SH_PFC_PIN_GROUP(hspi2_b),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c1_c),
SH_PFC_PIN_GROUP(i2c1_d),
SH_PFC_PIN_GROUP(i2c2),
SH_PFC_PIN_GROUP(i2c2_b),
SH_PFC_PIN_GROUP(i2c2_c),
SH_PFC_PIN_GROUP(i2c2_d),
SH_PFC_PIN_GROUP(i2c3),
SH_PFC_PIN_GROUP(i2c3_b),
SH_PFC_PIN_GROUP(intc_irq0),
SH_PFC_PIN_GROUP(intc_irq0_b),
SH_PFC_PIN_GROUP(intc_irq1),
......@@ -2703,6 +2786,25 @@ static const char * const hspi2_groups[] = {
"hspi2_b",
};
static const char * const i2c1_groups[] = {
"i2c1",
"i2c1_b",
"i2c1_c",
"i2c1_d",
};
static const char * const i2c2_groups[] = {
"i2c2",
"i2c2_b",
"i2c2_c",
"i2c2_d",
};
static const char * const i2c3_groups[] = {
"i2c3",
"i2c3_b",
};
static const char * const intc_groups[] = {
"intc_irq0",
"intc_irq0_b",
......@@ -2886,6 +2988,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(hspi0),
SH_PFC_FUNCTION(hspi1),
SH_PFC_FUNCTION(hspi2),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(intc),
SH_PFC_FUNCTION(lbsc),
SH_PFC_FUNCTION(mmc0),
......
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
浏览文件 @ f7a3427f
......@@ -111,18 +111,18 @@ enum {
FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
FN_SCL2_CIS_C, FN_D7, FN_AD_DI_B, FN_SDA2_C,
FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C,
FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,
FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
/* IPSR1 */
FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,
FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,
FN_SCIFA1_TXD_C, FN_AVB_TXD2,
FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,
FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
......@@ -141,9 +141,9 @@ enum {
FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B,
FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B,
FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
......@@ -182,11 +182,11 @@ enum {
/* IPSR5 */
FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B,
FN_INTC_EN0_N, FN_SCL1_CIS, FN_EX_CS5_N, FN_CAN0_RX,
FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N,
FN_SDA1_CIS, FN_BS_N, FN_IETX, FN_HTX1_B,
FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
......@@ -209,29 +209,29 @@ enum {
FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER,
FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
FN_I2C2_SCL_E, FN_ETH_RX_ER,
FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0,
FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
FN_HRX0_E, FN_STP_ISSYNC_0_B,
FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
FN_ETH_REF_CLK, FN_HCTS0_N_E,
FN_STP_IVCXO27_1_B, FN_HRX0_F,
/* IPSR7 */
FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
FN_ETH_MDIO, FN_HRTS0_N_E,
FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,
FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,
FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,
FN_HTX0_F, FN_BPFCLK_G,
FN_ETH_TX_EN, FN_SIM0_CLK_C,
FN_HRTS0_N_F, FN_ETH_MAGIC,
FN_SIM0_RST_C, FN_ETH_TXD0,
FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
FN_ETH_MDC, FN_STP_ISD_1_B,
FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
......@@ -239,26 +239,25 @@ enum {
FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
FN_ATACS00_N, FN_AVB_RXD1,
FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
FN_MII_RXD2,
/* IPSR8 */
FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV,
FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1,
FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
FN_VI1_CLK, FN_AVB_RX_DV,
FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
FN_SCIFA1_RXD_D, FN_AVB_MDC,
FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5,
FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
......@@ -269,26 +268,26 @@ enum {
FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD,
FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK,
FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
FN_AVB_TX_EN, FN_SD1_CMD,
FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
FN_SD1_DAT0, FN_AVB_TX_CLK,
FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2,
FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0,
FN_SCIFB0_TXD_B, FN_SD1_DAT2,
FN_AVB_COL, FN_SCIFB0_CTS_N_B,
FN_SD1_DAT3, FN_AVB_RXD0,
FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B,
FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
FN_VI3_CLK_B,
/* IPSR10 */
FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
......@@ -297,10 +296,10 @@ enum {
FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
......@@ -321,12 +320,12 @@ enum {
FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B,
FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B,
FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN,
FN_FMIN_E, FN_FMIN_F,
FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
FN_I2C2_SDA_B, FN_MLB_DAT,
FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B,
FN_SSI_SCK0129, FN_CAN_CLK_B,
FN_MOUT0,
/* IPSR12 */
......@@ -353,12 +352,12 @@ enum {
/* IPSR13 */
FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
FN_SCIFB1_CTS_N, FN_BPFCLK_D,
FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
FN_BPFCLK_F, FN_RDS_CLK_E, FN_SSI_WS6,
FN_BPFCLK_F, FN_SSI_WS6,
FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
......@@ -366,8 +365,8 @@ enum {
FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
FN_BPFCLK_E, FN_RDS_CLK_D, FN_SSI_SDATA7_B,
FN_FMIN_G, FN_RDS_DATA_F, FN_SSI_SDATA8,
FN_BPFCLK_E, FN_SSI_SDATA7_B,
FN_FMIN_G, FN_SSI_SDATA8,
FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
......@@ -378,29 +377,29 @@ enum {
FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_SDA1_C,
FN_SDA1_CIS_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C,
FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS,
FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS,
FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
FN_HRTS0_N_C,
/* IPSR15 */
FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7,
FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
FN_DU2_DB0, FN_LCDOUT16, FN_SCL2, FN_SCL2_CIS,
FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17,
FN_SDA2, FN_SDA2_CIS, FN_HSCK0, FN_TS_SDEN0,
FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
......@@ -408,7 +407,7 @@ enum {
FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
FN_SCIFA2_RXD_B, FN_MSIOF0_SS1, FN_ADICHS0,
FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
FN_DU2_DG6, FN_LCDOUT14,
......@@ -416,7 +415,7 @@ enum {
FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C,
FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
FN_TCLK1_B,
......@@ -451,6 +450,7 @@ enum {
FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
FN_SEL_CAN1_0, FN_SEL_CAN1_1,
FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
FN_SEL_ADI_0, FN_SEL_ADI_1,
FN_SEL_SSP_0, FN_SEL_SSP_1,
FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
......@@ -458,8 +458,6 @@ enum {
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
......@@ -491,17 +489,17 @@ enum {
VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK,
VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK,
D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK,
IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK,
D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK,
SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK,
SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
......@@ -519,9 +517,9 @@ enum {
A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK,
VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK,
VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
......@@ -558,11 +556,11 @@ enum {
EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK,
INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK,
SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
......@@ -584,28 +582,28 @@ enum {
DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK,
SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,
ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,
IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,
RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,
ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,
ETH_MDIO_MARK, HRTS0_N_E_MARK,
SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,
HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,
SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,
HTX0_F_MARK, BPFCLK_G_MARK,
ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
HRTS0_N_F_MARK, ETH_MAGIC_MARK,
SIM0_RST_C_MARK, ETH_TXD0_MARK,
STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,
ETH_MDC_MARK, STP_ISD_1_B_MARK,
TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
......@@ -613,25 +611,24 @@ enum {
PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,
ATACS00_N_MARK, AVB_RXD1_MARK,
VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
MII_RXD2_MARK,
VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK,
MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK,
VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
VI1_CLK_MARK, AVB_RX_DV_MARK,
VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
......@@ -641,25 +638,25 @@ enum {
SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK,
SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK,
SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK,
AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK,
SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK,
GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
AVB_TX_EN_MARK, SD1_CMD_MARK,
AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
SD1_DAT0_MARK, AVB_TX_CLK_MARK,
SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK,
SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK,
SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
SD1_DAT3_MARK, AVB_RXD0_MARK,
SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK,
IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
VI3_CLK_B_MARK,
SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK,
GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
......@@ -668,10 +665,10 @@ enum {
SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK,
SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK,
SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
......@@ -691,12 +688,12 @@ enum {
SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK,
RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK,
MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK,
SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK,
FMIN_E_MARK, FMIN_F_MARK,
MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
I2C2_SDA_B_MARK, MLB_DAT_MARK,
SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK,
SSI_SCK0129_MARK, CAN_CLK_B_MARK,
MOUT0_MARK,
SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
......@@ -721,12 +718,12 @@ enum {
SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK,
SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK,
BPFCLK_F_MARK, SSI_WS6_MARK,
SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
......@@ -734,8 +731,8 @@ enum {
LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK,
FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK,
BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
FMIN_G_MARK, SSI_SDATA8_MARK,
STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
......@@ -745,28 +742,28 @@ enum {
AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK,
SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK,
SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK,
LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK,
SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
HRTS0_N_C_MARK,
SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK,
SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK,
TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
......@@ -774,14 +771,14 @@ enum {
LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
DU2_DG6_MARK, LCDOUT14_MARK,
MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK,
ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
TCLK1_B_MARK,
PINMUX_MARK_END,
......@@ -835,22 +832,22 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
PINMUX_IPSR_DATA(IP0_22_20, D6),
PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_C, SEL_IIC2_2),
PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_CIS_C, SEL_I2C2_2),
PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
PINMUX_IPSR_DATA(IP0_26_23, D7),
PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_C, SEL_IIC2_2),
PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_CIS_C, SEL_I2C2_2),
PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0),
PINMUX_IPSR_DATA(IP0_30_27, D8),
PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0),
PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
......@@ -858,21 +855,18 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP1_3_0, D9),
PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1),
PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
PINMUX_IPSR_DATA(IP1_7_4, D10),
PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2),
PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
PINMUX_IPSR_DATA(IP1_11_8, D11),
PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3),
PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
......@@ -883,7 +877,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
PINMUX_IPSR_DATA(IP1_17_15, D13),
PINMUX_IPSR_MODSEL_DATA(IP1_17_15, AVB_TXD5, SEL_SCIFA1_2),
PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5),
PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
......@@ -931,6 +925,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
PINMUX_IPSR_DATA(IP2_25_22, A9),
PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
......@@ -938,6 +933,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
PINMUX_IPSR_DATA(IP2_28_26, A10),
PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
......@@ -952,14 +948,14 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
PINMUX_IPSR_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B),
PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
PINMUX_IPSR_DATA(IP3_7_4, A12),
PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
PINMUX_IPSR_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B),
PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
PINMUX_IPSR_DATA(IP3_11_8, A13),
PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
......@@ -967,7 +963,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_0),
PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
PINMUX_IPSR_DATA(IP3_14_12, A14),
PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
......@@ -1059,14 +1055,14 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
PINMUX_IPSR_MODSEL_DATA(IP5_5_3, EX_CS4_N, SEL_I2C1_0),
PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N),
PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1, SEL_IIC1_0),
PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1_CIS, SEL_I2C1_0),
PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
......@@ -1074,9 +1070,9 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1, SEL_IIC1_0),
PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1_CIS, SEL_I2C1_0),
PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
PINMUX_IPSR_DATA(IP5_12_10, BS_N),
PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
......@@ -1106,7 +1102,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
PINMUX_IPSR_DATA(IP5_26_24, EX_WAIT0),
PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0),
PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
......@@ -1148,28 +1144,24 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
......@@ -1177,41 +1169,32 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),
PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6),
PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
......@@ -1237,16 +1220,13 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3),
PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
......@@ -1261,34 +1241,27 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER),
PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK),
PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV),
PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
PINMUX_IPSR_DATA(IP8_17_16, MII_CRS),
PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
PINMUX_IPSR_DATA(IP8_19_18, MII_MDC),
PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO),
PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC),
PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3),
PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT),
PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
......@@ -1315,8 +1288,8 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1),
PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1),
PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
......@@ -1324,31 +1297,25 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1),
PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1),
PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN),
PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER),
PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK),
PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
PINMUX_IPSR_DATA(IP9_23_22, MII_LINK),
PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
PINMUX_IPSR_DATA(IP9_25_24, MII_COL),
PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0),
PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
......@@ -1356,8 +1323,8 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3),
PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3),
PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
......@@ -1367,8 +1334,8 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3),
PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3),
PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
......@@ -1398,7 +1365,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0),
PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
......@@ -1408,7 +1374,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0),
PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
......@@ -1471,25 +1436,20 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1),
PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3),
PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4),
PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1),
PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1),
PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1),
PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1),
PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN),
PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1),
PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
......@@ -1505,7 +1465,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_TX_B, SEL_CAN1_1),
PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1),
PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
......@@ -1560,12 +1520,10 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_C, SEL_RDS_2),
PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_E, SEL_RDS_4),
PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
......@@ -1574,7 +1532,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
PINMUX_IPSR_MODSEL_DATA(IP13_12_10, RDS_DATA_C, SEL_RDS_2),
PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
......@@ -1600,10 +1557,8 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_CLK_D, SEL_RDS_3),
PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_DATA_F, SEL_RDS_5),
PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
......@@ -1633,8 +1588,8 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_C, SEL_IIC1_2),
PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_CIS_C, SEL_I2C1_2),
PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
......@@ -1647,16 +1602,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
PINMUX_IPSR_MODSEL_DATA(IP14_15_12, CTS0_N, SEL_SCIF0_0),
PINMUX_IPSR_DATA(IP14_15_12, CTS0_N),
PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0),
PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0),
PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_C, SEL_IIC1_2),
PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_CIS_C, SEL_I2C1_2),
PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11),
PINMUX_IPSR_DATA(IP14_15_12, PWM0_B),
PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS),
PINMUX_IPSR_DATA(IP14_18_16, RTS0_N),
PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
......@@ -1679,7 +1634,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP14_27_25, QCLK),
PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
PINMUX_IPSR_DATA(IP14_30_28, RTS1_N_TANS),
PINMUX_IPSR_DATA(IP14_30_28, RTS1_N),
PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
......@@ -1687,28 +1642,30 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
PINMUX_IPSR_DATA(IP15_2_0, SCK2),
PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0),
PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0),
PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2, SEL_IIC2_0),
PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2_CIS, SEL_I2C2_0),
PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0),
PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2, SEL_IIC2_0),
PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2_CIS, SEL_I2C2_0),
PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0),
PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SDA2_CIS, SEL_I2C2_0),
PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
......@@ -1734,7 +1691,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
PINMUX_IPSR_MODSEL_DATA(IP15_25_23, SCIFA2_RXD_B, SEL_SCIFA2_1),
PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
......@@ -1757,7 +1714,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HRX0_C, SEL_HSCIF0_2),
PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
......@@ -1800,128 +1757,6 @@ static const unsigned int eth_rmii_mux[] = {
ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
};
/* - INTC ------------------------------------------------------------------- */
static const unsigned int intc_irq0_pins[] = {
/* IRQ */
RCAR_GP_PIN(1, 25),
};
static const unsigned int intc_irq0_mux[] = {
IRQ0_MARK,
};
static const unsigned int intc_irq1_pins[] = {
/* IRQ */
RCAR_GP_PIN(1, 27),
};
static const unsigned int intc_irq1_mux[] = {
IRQ1_MARK,
};
static const unsigned int intc_irq2_pins[] = {
/* IRQ */
RCAR_GP_PIN(1, 29),
};
static const unsigned int intc_irq2_mux[] = {
IRQ2_MARK,
};
static const unsigned int intc_irq3_pins[] = {
/* IRQ */
RCAR_GP_PIN(1, 23),
};
static const unsigned int intc_irq3_mux[] = {
IRQ3_MARK,
};
/* - SCIF0 ----------------------------------------------------------------- */
static const unsigned int scif0_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
};
static const unsigned int scif0_data_mux[] = {
RX0_MARK, TX0_MARK,
};
static const unsigned int scif0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 27),
};
static const unsigned int scif0_clk_mux[] = {
SCK0_MARK,
};
static const unsigned int scif0_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
};
static const unsigned int scif0_ctrl_mux[] = {
RTS0_N_TANS_MARK, CTS0_N_MARK,
};
static const unsigned int scif0_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
};
static const unsigned int scif0_data_b_mux[] = {
RX0_B_MARK, TX0_B_MARK,
};
/* - SCIF1 ----------------------------------------------------------------- */
static const unsigned int scif1_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
};
static const unsigned int scif1_data_mux[] = {
RX1_MARK, TX1_MARK,
};
static const unsigned int scif1_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 20),
};
static const unsigned int scif1_clk_mux[] = {
SCK1_MARK,
};
static const unsigned int scif1_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
};
static const unsigned int scif1_ctrl_mux[] = {
RTS1_N_TANS_MARK, CTS1_N_MARK,
};
static const unsigned int scif1_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
};
static const unsigned int scif1_data_b_mux[] = {
RX1_B_MARK, TX1_B_MARK,
};
static const unsigned int scif1_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
};
static const unsigned int scif1_data_c_mux[] = {
RX1_C_MARK, TX1_C_MARK,
};
static const unsigned int scif1_data_d_pins[] = {
/* RX, TX */
RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
};
static const unsigned int scif1_data_d_mux[] = {
RX1_D_MARK, TX1_D_MARK,
};
static const unsigned int scif1_clk_d_pins[] = {
/* SCK */
RCAR_GP_PIN(3, 17),
};
static const unsigned int scif1_clk_d_mux[] = {
SCK1_D_MARK,
};
static const unsigned int scif1_data_e_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
};
static const unsigned int scif1_data_e_mux[] = {
RX1_E_MARK, TX1_E_MARK,
};
static const unsigned int scif1_clk_e_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 20),
};
static const unsigned int scif1_clk_e_mux[] = {
SCK1_E_MARK,
};
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
......@@ -2057,6 +1892,390 @@ static const unsigned int hscif1_ctrl_b_pins[] = {
static const unsigned int hscif1_ctrl_b_mux[] = {
HRTS1_N_B_MARK, HCTS1_N_B_MARK,
};
/* - INTC ------------------------------------------------------------------- */
static const unsigned int intc_irq0_pins[] = {
/* IRQ */
RCAR_GP_PIN(1, 25),
};
static const unsigned int intc_irq0_mux[] = {
IRQ0_MARK,
};
static const unsigned int intc_irq1_pins[] = {
/* IRQ */
RCAR_GP_PIN(1, 27),
};
static const unsigned int intc_irq1_mux[] = {
IRQ1_MARK,
};
static const unsigned int intc_irq2_pins[] = {
/* IRQ */
RCAR_GP_PIN(1, 29),
};
static const unsigned int intc_irq2_mux[] = {
IRQ2_MARK,
};
static const unsigned int intc_irq3_pins[] = {
/* IRQ */
RCAR_GP_PIN(1, 23),
};
static const unsigned int intc_irq3_mux[] = {
IRQ3_MARK,
};
/* - MMCIF0 ----------------------------------------------------------------- */
static const unsigned int mmc0_data1_pins[] = {
/* D[0] */
RCAR_GP_PIN(3, 18),
};
static const unsigned int mmc0_data1_mux[] = {
MMC0_D0_MARK,
};
static const unsigned int mmc0_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
};
static const unsigned int mmc0_data4_mux[] = {
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
};
static const unsigned int mmc0_data8_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
};
static const unsigned int mmc0_data8_mux[] = {
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
};
static const unsigned int mmc0_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
};
static const unsigned int mmc0_ctrl_mux[] = {
MMC0_CLK_MARK, MMC0_CMD_MARK,
};
/* - MMCIF1 ----------------------------------------------------------------- */
static const unsigned int mmc1_data1_pins[] = {
/* D[0] */
RCAR_GP_PIN(3, 26),
};
static const unsigned int mmc1_data1_mux[] = {
MMC1_D0_MARK,
};
static const unsigned int mmc1_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
};
static const unsigned int mmc1_data4_mux[] = {
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
};
static const unsigned int mmc1_data8_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
};
static const unsigned int mmc1_data8_mux[] = {
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
};
static const unsigned int mmc1_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
};
static const unsigned int mmc1_ctrl_mux[] = {
MMC1_CLK_MARK, MMC1_CMD_MARK,
};
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 12),
};
static const unsigned int msiof0_clk_mux[] = {
MSIOF0_SCK_MARK,
};
static const unsigned int msiof0_sync_pins[] = {
/* SYNC */
RCAR_GP_PIN(5, 13),
};
static const unsigned int msiof0_sync_mux[] = {
MSIOF0_SYNC_MARK,
};
static const unsigned int msiof0_ss1_pins[] = {
/* SS1 */
RCAR_GP_PIN(5, 14),
};
static const unsigned int msiof0_ss1_mux[] = {
MSIOF0_SS1_MARK,
};
static const unsigned int msiof0_ss2_pins[] = {
/* SS2 */
RCAR_GP_PIN(5, 16),
};
static const unsigned int msiof0_ss2_mux[] = {
MSIOF0_SS2_MARK,
};
static const unsigned int msiof0_rx_pins[] = {
/* RXD */
RCAR_GP_PIN(5, 17),
};
static const unsigned int msiof0_rx_mux[] = {
MSIOF0_RXD_MARK,
};
static const unsigned int msiof0_tx_pins[] = {
/* TXD */
RCAR_GP_PIN(5, 15),
};
static const unsigned int msiof0_tx_mux[] = {
MSIOF0_TXD_MARK,
};
/* - MSIOF1 ----------------------------------------------------------------- */
static const unsigned int msiof1_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 8),
};
static const unsigned int msiof1_clk_mux[] = {
MSIOF1_SCK_MARK,
};
static const unsigned int msiof1_sync_pins[] = {
/* SYNC */
RCAR_GP_PIN(4, 9),
};
static const unsigned int msiof1_sync_mux[] = {
MSIOF1_SYNC_MARK,
};
static const unsigned int msiof1_ss1_pins[] = {
/* SS1 */
RCAR_GP_PIN(4, 10),
};
static const unsigned int msiof1_ss1_mux[] = {
MSIOF1_SS1_MARK,
};
static const unsigned int msiof1_ss2_pins[] = {
/* SS2 */
RCAR_GP_PIN(4, 11),
};
static const unsigned int msiof1_ss2_mux[] = {
MSIOF1_SS2_MARK,
};
static const unsigned int msiof1_rx_pins[] = {
/* RXD */
RCAR_GP_PIN(4, 13),
};
static const unsigned int msiof1_rx_mux[] = {
MSIOF1_RXD_MARK,
};
static const unsigned int msiof1_tx_pins[] = {
/* TXD */
RCAR_GP_PIN(4, 12),
};
static const unsigned int msiof1_tx_mux[] = {
MSIOF1_TXD_MARK,
};
/* - MSIOF2 ----------------------------------------------------------------- */
static const unsigned int msiof2_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(0, 27),
};
static const unsigned int msiof2_clk_mux[] = {
MSIOF2_SCK_MARK,
};
static const unsigned int msiof2_sync_pins[] = {
/* SYNC */
RCAR_GP_PIN(0, 26),
};
static const unsigned int msiof2_sync_mux[] = {
MSIOF2_SYNC_MARK,
};
static const unsigned int msiof2_ss1_pins[] = {
/* SS1 */
RCAR_GP_PIN(0, 30),
};
static const unsigned int msiof2_ss1_mux[] = {
MSIOF2_SS1_MARK,
};
static const unsigned int msiof2_ss2_pins[] = {
/* SS2 */
RCAR_GP_PIN(0, 31),
};
static const unsigned int msiof2_ss2_mux[] = {
MSIOF2_SS2_MARK,
};
static const unsigned int msiof2_rx_pins[] = {
/* RXD */
RCAR_GP_PIN(0, 29),
};
static const unsigned int msiof2_rx_mux[] = {
MSIOF2_RXD_MARK,
};
static const unsigned int msiof2_tx_pins[] = {
/* TXD */
RCAR_GP_PIN(0, 28),
};
static const unsigned int msiof2_tx_mux[] = {
MSIOF2_TXD_MARK,
};
/* - MSIOF3 ----------------------------------------------------------------- */
static const unsigned int msiof3_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 4),
};
static const unsigned int msiof3_clk_mux[] = {
MSIOF3_SCK_MARK,
};
static const unsigned int msiof3_sync_pins[] = {
/* SYNC */
RCAR_GP_PIN(4, 30),
};
static const unsigned int msiof3_sync_mux[] = {
MSIOF3_SYNC_MARK,
};
static const unsigned int msiof3_ss1_pins[] = {
/* SS1 */
RCAR_GP_PIN(4, 31),
};
static const unsigned int msiof3_ss1_mux[] = {
MSIOF3_SS1_MARK,
};
static const unsigned int msiof3_ss2_pins[] = {
/* SS2 */
RCAR_GP_PIN(4, 27),
};
static const unsigned int msiof3_ss2_mux[] = {
MSIOF3_SS2_MARK,
};
static const unsigned int msiof3_rx_pins[] = {
/* RXD */
RCAR_GP_PIN(5, 2),
};
static const unsigned int msiof3_rx_mux[] = {
MSIOF3_RXD_MARK,
};
static const unsigned int msiof3_tx_pins[] = {
/* TXD */
RCAR_GP_PIN(5, 3),
};
static const unsigned int msiof3_tx_mux[] = {
MSIOF3_TXD_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
};
static const unsigned int scif0_data_mux[] = {
RX0_MARK, TX0_MARK,
};
static const unsigned int scif0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 27),
};
static const unsigned int scif0_clk_mux[] = {
SCK0_MARK,
};
static const unsigned int scif0_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
};
static const unsigned int scif0_ctrl_mux[] = {
RTS0_N_MARK, CTS0_N_MARK,
};
static const unsigned int scif0_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
};
static const unsigned int scif0_data_b_mux[] = {
RX0_B_MARK, TX0_B_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
static const unsigned int scif1_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
};
static const unsigned int scif1_data_mux[] = {
RX1_MARK, TX1_MARK,
};
static const unsigned int scif1_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 20),
};
static const unsigned int scif1_clk_mux[] = {
SCK1_MARK,
};
static const unsigned int scif1_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
};
static const unsigned int scif1_ctrl_mux[] = {
RTS1_N_MARK, CTS1_N_MARK,
};
static const unsigned int scif1_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
};
static const unsigned int scif1_data_b_mux[] = {
RX1_B_MARK, TX1_B_MARK,
};
static const unsigned int scif1_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
};
static const unsigned int scif1_data_c_mux[] = {
RX1_C_MARK, TX1_C_MARK,
};
static const unsigned int scif1_data_d_pins[] = {
/* RX, TX */
RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
};
static const unsigned int scif1_data_d_mux[] = {
RX1_D_MARK, TX1_D_MARK,
};
static const unsigned int scif1_clk_d_pins[] = {
/* SCK */
RCAR_GP_PIN(3, 17),
};
static const unsigned int scif1_clk_d_mux[] = {
SCK1_D_MARK,
};
static const unsigned int scif1_data_e_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
};
static const unsigned int scif1_data_e_mux[] = {
RX1_E_MARK, TX1_E_MARK,
};
static const unsigned int scif1_clk_e_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 20),
};
static const unsigned int scif1_clk_e_mux[] = {
SCK1_E_MARK,
};
/* - SCIF2 ------------------------------------------------------------------ */
static const unsigned int scif2_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
};
static const unsigned int scif2_data_mux[] = {
RX2_MARK, TX2_MARK,
};
static const unsigned int scif2_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 4),
};
static const unsigned int scif2_clk_mux[] = {
SCK2_MARK,
};
static const unsigned int scif2_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
};
static const unsigned int scif2_data_b_mux[] = {
RX2_B_MARK, TX2_B_MARK,
};
/* - SCIFA0 ----------------------------------------------------------------- */
static const unsigned int scifa0_data_pins[] = {
/* RXD, TXD */
......@@ -2367,155 +2586,58 @@ static const unsigned int scifb1_clk_g_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 20),
};
static const unsigned int scifb1_clk_g_mux[] = {
SCIFB1_SCK_G_MARK,
};
/* - SCIFB2 ----------------------------------------------------------------- */
static const unsigned int scifb2_data_pins[] = {
/* RXD, TXD */
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
};
static const unsigned int scifb2_data_mux[] = {
SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
};
static const unsigned int scifb2_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 21),
};
static const unsigned int scifb2_clk_mux[] = {
SCIFB2_SCK_MARK,
};
static const unsigned int scifb2_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
};
static const unsigned int scifb2_ctrl_mux[] = {
SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
};
static const unsigned int scifb2_data_b_pins[] = {
/* RXD, TXD */
RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
};
static const unsigned int scifb2_data_b_mux[] = {
SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
};
static const unsigned int scifb2_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(0, 31),
};
static const unsigned int scifb2_clk_b_mux[] = {
SCIFB2_SCK_B_MARK,
};
static const unsigned int scifb2_ctrl_b_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
};
static const unsigned int scifb2_ctrl_b_mux[] = {
SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
};
static const unsigned int scifb2_data_c_pins[] = {
/* RXD, TXD */
RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
};
static const unsigned int scifb2_data_c_mux[] = {
SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
};
/* - TPU0 ------------------------------------------------------------------- */
static const unsigned int tpu0_to0_pins[] = {
/* TO */
RCAR_GP_PIN(0, 20),
};
static const unsigned int tpu0_to0_mux[] = {
TPU0TO0_MARK,
};
static const unsigned int tpu0_to1_pins[] = {
/* TO */
RCAR_GP_PIN(0, 21),
};
static const unsigned int tpu0_to1_mux[] = {
TPU0TO1_MARK,
};
static const unsigned int tpu0_to2_pins[] = {
/* TO */
RCAR_GP_PIN(0, 22),
};
static const unsigned int tpu0_to2_mux[] = {
TPU0TO2_MARK,
};
static const unsigned int tpu0_to3_pins[] = {
/* TO */
RCAR_GP_PIN(0, 23),
};
static const unsigned int tpu0_to3_mux[] = {
TPU0TO3_MARK,
};
/* - MMCIF0 ----------------------------------------------------------------- */
static const unsigned int mmc0_data1_pins[] = {
/* D[0] */
RCAR_GP_PIN(3, 18),
};
static const unsigned int mmc0_data1_mux[] = {
MMC0_D0_MARK,
};
static const unsigned int mmc0_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
static const unsigned int scifb1_clk_g_mux[] = {
SCIFB1_SCK_G_MARK,
};
static const unsigned int mmc0_data4_mux[] = {
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
/* - SCIFB2 ----------------------------------------------------------------- */
static const unsigned int scifb2_data_pins[] = {
/* RXD, TXD */
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
};
static const unsigned int mmc0_data8_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
static const unsigned int scifb2_data_mux[] = {
SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
};
static const unsigned int mmc0_data8_mux[] = {
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
static const unsigned int scifb2_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 21),
};
static const unsigned int mmc0_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
static const unsigned int scifb2_clk_mux[] = {
SCIFB2_SCK_MARK,
};
static const unsigned int mmc0_ctrl_mux[] = {
MMC0_CLK_MARK, MMC0_CMD_MARK,
static const unsigned int scifb2_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
};
/* - MMCIF1 ----------------------------------------------------------------- */
static const unsigned int mmc1_data1_pins[] = {
/* D[0] */
RCAR_GP_PIN(3, 26),
static const unsigned int scifb2_ctrl_mux[] = {
SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
};
static const unsigned int mmc1_data1_mux[] = {
MMC1_D0_MARK,
static const unsigned int scifb2_data_b_pins[] = {
/* RXD, TXD */
RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
};
static const unsigned int mmc1_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
static const unsigned int scifb2_data_b_mux[] = {
SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
};
static const unsigned int mmc1_data4_mux[] = {
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
static const unsigned int scifb2_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(0, 31),
};
static const unsigned int mmc1_data8_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
static const unsigned int scifb2_clk_b_mux[] = {
SCIFB2_SCK_B_MARK,
};
static const unsigned int mmc1_data8_mux[] = {
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
static const unsigned int scifb2_ctrl_b_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
};
static const unsigned int mmc1_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
static const unsigned int scifb2_ctrl_b_mux[] = {
SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
};
static const unsigned int mmc1_ctrl_mux[] = {
MMC1_CLK_MARK, MMC1_CMD_MARK,
static const unsigned int scifb2_data_c_pins[] = {
/* RXD, TXD */
RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
};
static const unsigned int scifb2_data_c_mux[] = {
SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
......@@ -2661,6 +2783,137 @@ static const unsigned int sdhi3_wp_pins[] = {
static const unsigned int sdhi3_wp_mux[] = {
SD3_WP_MARK,
};
/* - TPU0 ------------------------------------------------------------------- */
static const unsigned int tpu0_to0_pins[] = {
/* TO */
RCAR_GP_PIN(0, 20),
};
static const unsigned int tpu0_to0_mux[] = {
TPU0TO0_MARK,
};
static const unsigned int tpu0_to1_pins[] = {
/* TO */
RCAR_GP_PIN(0, 21),
};
static const unsigned int tpu0_to1_mux[] = {
TPU0TO1_MARK,
};
static const unsigned int tpu0_to2_pins[] = {
/* TO */
RCAR_GP_PIN(0, 22),
};
static const unsigned int tpu0_to2_mux[] = {
TPU0TO2_MARK,
};
static const unsigned int tpu0_to3_pins[] = {
/* TO */
RCAR_GP_PIN(0, 23),
};
static const unsigned int tpu0_to3_mux[] = {
TPU0TO3_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC/VBUS */
RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
};
static const unsigned int usb0_mux[] = {
USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
};
/* - USB1 ------------------------------------------------------------------- */
static const unsigned int usb1_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
};
static const unsigned int usb1_mux[] = {
USB1_PWEN_MARK, USB1_OVC_MARK,
};
/* - USB2 ------------------------------------------------------------------- */
static const unsigned int usb2_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
};
static const unsigned int usb2_mux[] = {
USB2_PWEN_MARK, USB2_OVC_MARK,
};
/* - VIN0 ------------------------------------------------------------------- */
static const unsigned int vin0_data_g_pins[] = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
};
static const unsigned int vin0_data_g_mux[] = {
VI0_G0_MARK, VI0_G1_MARK, VI0_G2_MARK,
VI0_G3_MARK, VI0_G4_MARK, VI0_G5_MARK,
VI0_G6_MARK, VI0_G7_MARK,
};
static const unsigned int vin0_data_r_pins[] = {
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
};
static const unsigned int vin0_data_r_mux[] = {
VI0_R0_MARK, VI0_R1_MARK, VI0_R2_MARK,
VI0_R3_MARK, VI0_R4_MARK, VI0_R5_MARK,
VI0_R6_MARK, VI0_R7_MARK,
};
static const unsigned int vin0_data_b_pins[] = {
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
};
static const unsigned int vin0_data_b_mux[] = {
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
};
static const unsigned int vin0_hsync_signal_pins[] = {
RCAR_GP_PIN(0, 12),
};
static const unsigned int vin0_hsync_signal_mux[] = {
VI0_HSYNC_N_MARK,
};
static const unsigned int vin0_vsync_signal_pins[] = {
RCAR_GP_PIN(0, 13),
};
static const unsigned int vin0_vsync_signal_mux[] = {
VI0_VSYNC_N_MARK,
};
static const unsigned int vin0_field_signal_pins[] = {
RCAR_GP_PIN(0, 15),
};
static const unsigned int vin0_field_signal_mux[] = {
VI0_FIELD_MARK,
};
static const unsigned int vin0_data_enable_pins[] = {
RCAR_GP_PIN(0, 14),
};
static const unsigned int vin0_data_enable_mux[] = {
VI0_CLKENB_MARK,
};
static const unsigned int vin0_clk_pins[] = {
RCAR_GP_PIN(2, 0),
};
static const unsigned int vin0_clk_mux[] = {
VI0_CLK_MARK,
};
/* - VIN1 ------------------------------------------------------------------- */
static const unsigned int vin1_data_pins[] = {
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
};
static const unsigned int vin1_data_mux[] = {
VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
};
static const unsigned int vin1_clk_pins[] = {
RCAR_GP_PIN(2, 9),
};
static const unsigned int vin1_clk_mux[] = {
VI1_CLK_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(eth_link),
......@@ -2698,6 +2951,30 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(mmc1_data4),
SH_PFC_PIN_GROUP(mmc1_data8),
SH_PFC_PIN_GROUP(mmc1_ctrl),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
SH_PFC_PIN_GROUP(msiof0_ss2),
SH_PFC_PIN_GROUP(msiof0_rx),
SH_PFC_PIN_GROUP(msiof0_tx),
SH_PFC_PIN_GROUP(msiof1_clk),
SH_PFC_PIN_GROUP(msiof1_sync),
SH_PFC_PIN_GROUP(msiof1_ss1),
SH_PFC_PIN_GROUP(msiof1_ss2),
SH_PFC_PIN_GROUP(msiof1_rx),
SH_PFC_PIN_GROUP(msiof1_tx),
SH_PFC_PIN_GROUP(msiof2_clk),
SH_PFC_PIN_GROUP(msiof2_sync),
SH_PFC_PIN_GROUP(msiof2_ss1),
SH_PFC_PIN_GROUP(msiof2_ss2),
SH_PFC_PIN_GROUP(msiof2_rx),
SH_PFC_PIN_GROUP(msiof2_tx),
SH_PFC_PIN_GROUP(msiof3_clk),
SH_PFC_PIN_GROUP(msiof3_sync),
SH_PFC_PIN_GROUP(msiof3_ss1),
SH_PFC_PIN_GROUP(msiof3_ss2),
SH_PFC_PIN_GROUP(msiof3_rx),
SH_PFC_PIN_GROUP(msiof3_tx),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
......@@ -2711,6 +2988,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif1_clk_d),
SH_PFC_PIN_GROUP(scif1_data_e),
SH_PFC_PIN_GROUP(scif1_clk_e),
SH_PFC_PIN_GROUP(scif2_data),
SH_PFC_PIN_GROUP(scif2_clk),
SH_PFC_PIN_GROUP(scif2_data_b),
SH_PFC_PIN_GROUP(scifa0_data),
SH_PFC_PIN_GROUP(scifa0_clk),
SH_PFC_PIN_GROUP(scifa0_ctrl),
......@@ -2786,6 +3066,19 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(tpu0_to1),
SH_PFC_PIN_GROUP(tpu0_to2),
SH_PFC_PIN_GROUP(tpu0_to3),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb2),
SH_PFC_PIN_GROUP(vin0_data_g),
SH_PFC_PIN_GROUP(vin0_data_r),
SH_PFC_PIN_GROUP(vin0_data_b),
SH_PFC_PIN_GROUP(vin0_hsync_signal),
SH_PFC_PIN_GROUP(vin0_vsync_signal),
SH_PFC_PIN_GROUP(vin0_field_signal),
SH_PFC_PIN_GROUP(vin0_data_enable),
SH_PFC_PIN_GROUP(vin0_clk),
SH_PFC_PIN_GROUP(vin1_data),
SH_PFC_PIN_GROUP(vin1_clk),
};
static const char * const eth_groups[] = {
......@@ -2795,6 +3088,31 @@ static const char * const eth_groups[] = {
"eth_rmii",
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
"hscif0_ctrl",
"hscif0_data_b",
"hscif0_ctrl_b",
"hscif0_data_c",
"hscif0_ctrl_c",
"hscif0_data_d",
"hscif0_ctrl_d",
"hscif0_data_e",
"hscif0_ctrl_e",
"hscif0_data_f",
"hscif0_ctrl_f",
};
static const char * const hscif1_groups[] = {
"hscif1_data",
"hscif1_clk",
"hscif1_ctrl",
"hscif1_data_b",
"hscif1_clk_b",
"hscif1_ctrl_b",
};
static const char * const intc_groups[] = {
"intc_irq0",
"intc_irq1",
......@@ -2802,6 +3120,56 @@ static const char * const intc_groups[] = {
"intc_irq3",
};
static const char * const mmc0_groups[] = {
"mmc0_data1",
"mmc0_data4",
"mmc0_data8",
"mmc0_ctrl",
};
static const char * const mmc1_groups[] = {
"mmc1_data1",
"mmc1_data4",
"mmc1_data8",
"mmc1_ctrl",
};
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
"msiof0_ss1",
"msiof0_ss2",
"msiof0_rx",
"msiof0_tx",
};
static const char * const msiof1_groups[] = {
"msiof1_clk",
"msiof1_sync",
"msiof1_ss1",
"msiof1_ss2",
"msiof1_rx",
"msiof1_tx",
};
static const char * const msiof2_groups[] = {
"msiof2_clk",
"msiof2_sync",
"msiof2_ss1",
"msiof2_ss2",
"msiof2_rx",
"msiof2_tx",
};
static const char * const msiof3_groups[] = {
"msiof3_clk",
"msiof3_sync",
"msiof3_ss1",
"msiof3_ss2",
"msiof3_rx",
"msiof3_tx",
};
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
......@@ -2821,29 +3189,10 @@ static const char * const scif1_groups[] = {
"scif1_clk_e",
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
"hscif0_ctrl",
"hscif0_data_b",
"hscif0_ctrl_b",
"hscif0_data_c",
"hscif0_ctrl_c",
"hscif0_data_d",
"hscif0_ctrl_d",
"hscif0_data_e",
"hscif0_ctrl_e",
"hscif0_data_f",
"hscif0_ctrl_f",
};
static const char * const hscif1_groups[] = {
"hscif1_data",
"hscif1_clk",
"hscif1_ctrl",
"hscif1_data_b",
"hscif1_clk_b",
"hscif1_ctrl_b",
static const char * const scif2_groups[] = {
"scif2_data",
"scif2_clk",
"scif2_data_b",
};
static const char * const scifa0_groups[] = {
......@@ -2915,27 +3264,6 @@ static const char * const scifb2_groups[] = {
"scifb2_data_c",
};
static const char * const tpu0_groups[] = {
"tpu0_to0",
"tpu0_to1",
"tpu0_to2",
"tpu0_to3",
};
static const char * const mmc0_groups[] = {
"mmc0_data1",
"mmc0_data4",
"mmc0_data8",
"mmc0_ctrl",
};
static const char * const mmc1_groups[] = {
"mmc1_data1",
"mmc1_data4",
"mmc1_data8",
"mmc1_ctrl",
};
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
......@@ -2968,6 +3296,41 @@ static const char * const sdhi3_groups[] = {
"sdhi3_wp",
};
static const char * const tpu0_groups[] = {
"tpu0_to0",
"tpu0_to1",
"tpu0_to2",
"tpu0_to3",
};
static const char * const usb0_groups[] = {
"usb0",
};
static const char * const usb1_groups[] = {
"usb1",
};
static const char * const usb2_groups[] = {
"usb2",
};
static const char * const vin0_groups[] = {
"vin0_data_g",
"vin0_data_r",
"vin0_data_b",
"vin0_hsync_signal",
"vin0_vsync_signal",
"vin0_field_signal",
"vin0_data_enable",
"vin0_clk",
};
static const char * const vin1_groups[] = {
"vin1_data",
"vin1_clk",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(eth),
SH_PFC_FUNCTION(hscif0),
......@@ -2975,8 +3338,13 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(intc),
SH_PFC_FUNCTION(mmc0),
SH_PFC_FUNCTION(mmc1),
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
SH_PFC_FUNCTION(scifa0),
SH_PFC_FUNCTION(scifa1),
SH_PFC_FUNCTION(scifa2),
......@@ -2988,6 +3356,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(tpu0),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb2),
SH_PFC_FUNCTION(vin0),
SH_PFC_FUNCTION(vin1),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
......@@ -3200,16 +3573,16 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP0_31 [1] */
0, 0,
/* IP0_30_27 [4] */
FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,
FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_26_23 [4] */
FN_D7, FN_AD_DI_B, FN_SDA2_C,
FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C,
0, 0, 0, 0, 0, 0, 0, 0, 0,
FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_22_20 [3] */
FN_D6, FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
FN_SCL2_CIS_C, 0, 0,
FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
FN_I2C2_SCL_C, 0, 0,
/* IP0_19_16 [4] */
FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
......@@ -3256,15 +3629,15 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
0, 0,
/* IP1_11_8 [4] */
FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,
FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_7_4 [4] */
FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,
FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_3_0 [4] */
FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,
FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
0, 0, 0, 0, 0, 0, 0, 0, 0, }
},
......@@ -3277,11 +3650,11 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
/* IP2_25_22 [4] */
FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B,
FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_21_18 [4] */
FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B,
FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_17_15 [3] */
FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
......@@ -3391,12 +3764,12 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
/* IP5_9_6 [4] */
FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N,
FN_SDA1_CIS, 0, 0, 0, 0, 0, 0,
FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
/* IP5_5_3 [3] */
FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B,
FN_INTC_EN0_N, FN_SCL1_CIS,
FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
FN_INTC_EN0_N, FN_I2C1_SCL,
/* IP5_2_0 [3] */
FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
FN_VI2_R3, 0, 0, }
......@@ -3404,24 +3777,24 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
/* IP6_31_29 [3] */
FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
/* IP6_28_26 [3] */
FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
FN_ETH_LINK, 0, FN_HTX0_E,
FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
/* IP6_25_23 [3] */
FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
/* IP6_22_20 [3] */
FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
/* IP6_19_17 [3] */
FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,
FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0,
FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
/* IP6_16_14 [3] */
FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
FN_SCL2_CIS_E, 0,
FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
FN_I2C2_SCL_E, 0,
/* IP6_13_11 [3] */
FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
......@@ -3442,10 +3815,9 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP7_31 [1] */
0, 0,
/* IP7_30_29 [2] */
FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
FN_MII_RXD2,
FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
/* IP7_28_27 [2] */
FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
/* IP7_26_25 [2] */
FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
/* IP7_24_22 [3] */
......@@ -3458,20 +3830,19 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
FN_GLO_SS_C, 0, 0, 0,
/* IP7_15_13 [3] */
FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
FN_ETH_MDC, 0, FN_STP_ISD_1_B,
FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
/* IP7_12_10 [3] */
FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
FN_GLO_SCLK_C, 0, 0, 0,
/* IP7_9_8 [2] */
FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,
FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
/* IP7_7_6 [2] */
FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,
FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
/* IP7_5_3 [3] */
FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
0, 0, 0,
FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
/* IP7_2_0 [3] */
FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
FN_ETH_MDIO, 0, FN_HRTS0_N_E,
FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
......@@ -3489,22 +3860,21 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
/* IP8_25_24 [2] */
FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
FN_AVB_MAGIC, FN_MII_MAGIC,
FN_AVB_MAGIC, 0,
/* IP8_23_22 [2] */
FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
/* IP8_21_20 [2] */
FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
FN_MII_MDIO,
FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
/* IP8_19_18 [2] */
FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
/* IP8_17_16 [2] */
FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS,
FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
/* IP8_15_14 [2] */
FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0,
FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
/* IP8_13_12 [2] */
FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0,
FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
/* IP8_11_10 [2] */
FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0,
FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
/* IP8_9_8 [2] */
FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
/* IP8_7_6 [2] */
......@@ -3514,34 +3884,34 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP8_3_2 [2] */
FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
/* IP8_1_0 [2] */
FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, }
FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
/* IP9_31_28 [4] */
FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D,
FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
/* IP9_27_26 [2] */
FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B,
FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
/* IP9_25_24 [2] */
FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
/* IP9_23_22 [2] */
FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B,
FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
/* IP9_21_20 [2] */
FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B,
FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
/* IP9_19_18 [2] */
FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
/* IP9_17_16 [2] */
FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0,
FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
/* IP9_15_12 [4] */
FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
/* IP9_11_8 [4] */
FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
/* IP9_7_6 [2] */
FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
/* IP9_5_4 [2] */
......@@ -3563,11 +3933,11 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
/* IP10_22_19 [4] */
FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
/* IP10_18_15 [4] */
FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
0, 0, 0, 0, 0, 0,
......@@ -3587,7 +3957,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI3_DATA0_B, 0,
/* IP10_3_0 [4] */
FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
......@@ -3595,17 +3965,16 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP11_31_30 [2] */
FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
/* IP11_29_27 [3] */
FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
FN_RDS_CLK_B, 0, 0,
FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
0, 0, 0,
/* IP11_26_24 [3] */
FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B,
FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
0, 0, 0,
/* IP11_23_22 [2] */
FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0,
FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
/* IP11_21_18 [4] */
FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0,
0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
/* IP11_17_15 [3] */
FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
......@@ -3680,8 +4049,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP13_22_19 [4] */
FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
FN_RDS_CLK_D, FN_SSI_SDATA7_B, FN_FMIN_G, FN_RDS_DATA_F,
0, 0, 0, 0,
0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
/* IP13_18_16 [3] */
FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
......@@ -3689,15 +4057,15 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
/* IP13_12_10 [3] */
FN_SSI_SDATA6, FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
FN_CAN_DEBUGOUT8, 0, 0,
/* IP13_9_7 [3] */
FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
/* IP13_6_3 [4] */
FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
FN_BPFCLK_F, FN_RDS_CLK_E, 0, 0, 0, 0, 0, 0, 0,
FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_2_0 [3] */
FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
......@@ -3707,7 +4075,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP14_30 [1] */
0, 0,
/* IP14_30_28 [3] */
FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS,
FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
FN_HRTS0_N_C, 0,
/* IP14_27_25 [3] */
......@@ -3720,11 +4088,11 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
/* IP14_18_16 [3] */
FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS,
FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
/* IP14_15_12 [4] */
FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C,
FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
0, 0, 0, 0, 0, 0, 0,
/* IP14_11_9 [3] */
FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
......@@ -3734,7 +4102,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0,
/* IP14_5_3 [3] */
FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
FN_LCDOUT10, FN_SDA1_C, FN_SDA1_CIS_C,
FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
/* IP14_2_0 [3] */
FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
......@@ -3750,7 +4118,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
/* IP15_25_23 [3] */
FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
FN_DU2_DB7, FN_LCDOUT23, FN_SCIFA2_RXD_B, 0,
FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
/* IP15_22_20 [3] */
FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
......@@ -3766,13 +4134,13 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
0, 0, 0,
/* IP15_8_6 [3] */
FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17,
FN_SDA2, FN_SDA2_CIS, 0,
FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
FN_IIC2_SDA, FN_I2C2_SDA, 0,
/* IP15_5_3 [3] */
FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16,
FN_SCL2, FN_SCL2_CIS, 0,
FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
FN_IIC2_SCL, FN_I2C2_SCL, 0,
/* IP15_2_0 [3] */
FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7,
FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
},
{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
......@@ -3801,7 +4169,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
/* IP16_5_3 [3] */
FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, 0,
FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
/* IP16_2_0 [3] */
FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
......@@ -3877,8 +4245,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_CAN1_0, FN_SEL_CAN1_1,
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */
0, 0,
/* SEL_SCIF2 [1] */
FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
/* SEL_ADI [1] */
FN_SEL_ADI_0, FN_SEL_ADI_1,
/* SEL_SSP [1] */
......@@ -3891,9 +4259,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
/* SEL_GPS [2] */
FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
/* SEL_RDS [3] */
FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0,
/* RESERVED [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* SEL_SIM [2] */
FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
/* SEL_SSI8 [2] */
......
drivers/pinctrl/sh-pfc/pfc-sh7372.c
浏览文件 @ f7a3427f
......@@ -23,9 +23,7 @@
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <mach/irqs.h>
#include <mach/sh7372.h>
#include <linux/sh_intc.h>
#include "core.h"
#include "sh_pfc.h"
......
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
浏览文件 @ f7a3427f
......@@ -3660,43 +3660,39 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
/* External IRQ pins mapped at IRQPIN_BASE */
#define EXT_IRQ16L(n) irq_pin(n)
#define EXT_IRQ16H(n) irq_pin(n)
static const struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(EXT_IRQ16H(19), 9),
PINMUX_IRQ(EXT_IRQ16L(1), 10),
PINMUX_IRQ(EXT_IRQ16L(0), 11),
PINMUX_IRQ(EXT_IRQ16H(18), 13),
PINMUX_IRQ(EXT_IRQ16H(20), 14),
PINMUX_IRQ(EXT_IRQ16H(21), 15),
PINMUX_IRQ(EXT_IRQ16H(31), 26),
PINMUX_IRQ(EXT_IRQ16H(30), 27),
PINMUX_IRQ(EXT_IRQ16H(29), 28),
PINMUX_IRQ(EXT_IRQ16H(22), 40),
PINMUX_IRQ(EXT_IRQ16H(23), 53),
PINMUX_IRQ(EXT_IRQ16L(10), 54),
PINMUX_IRQ(EXT_IRQ16L(9), 56),
PINMUX_IRQ(EXT_IRQ16H(26), 115),
PINMUX_IRQ(EXT_IRQ16H(27), 116),
PINMUX_IRQ(EXT_IRQ16H(28), 117),
PINMUX_IRQ(EXT_IRQ16H(24), 118),
PINMUX_IRQ(EXT_IRQ16L(6), 147),
PINMUX_IRQ(EXT_IRQ16L(2), 149),
PINMUX_IRQ(EXT_IRQ16L(7), 150),
PINMUX_IRQ(EXT_IRQ16L(12), 156),
PINMUX_IRQ(EXT_IRQ16L(4), 159),
PINMUX_IRQ(EXT_IRQ16H(25), 164),
PINMUX_IRQ(EXT_IRQ16L(8), 223),
PINMUX_IRQ(EXT_IRQ16L(3), 224),
PINMUX_IRQ(EXT_IRQ16L(5), 227),
PINMUX_IRQ(EXT_IRQ16H(17), 234),
PINMUX_IRQ(EXT_IRQ16L(11), 238),
PINMUX_IRQ(EXT_IRQ16L(13), 239),
PINMUX_IRQ(EXT_IRQ16H(16), 249),
PINMUX_IRQ(EXT_IRQ16L(14), 251),
PINMUX_IRQ(EXT_IRQ16L(9), 308),
PINMUX_IRQ(irq_pin(19), 9),
PINMUX_IRQ(irq_pin(1), 10),
PINMUX_IRQ(irq_pin(0), 11),
PINMUX_IRQ(irq_pin(18), 13),
PINMUX_IRQ(irq_pin(20), 14),
PINMUX_IRQ(irq_pin(21), 15),
PINMUX_IRQ(irq_pin(31), 26),
PINMUX_IRQ(irq_pin(30), 27),
PINMUX_IRQ(irq_pin(29), 28),
PINMUX_IRQ(irq_pin(22), 40),
PINMUX_IRQ(irq_pin(23), 53),
PINMUX_IRQ(irq_pin(10), 54),
PINMUX_IRQ(irq_pin(9), 56),
PINMUX_IRQ(irq_pin(26), 115),
PINMUX_IRQ(irq_pin(27), 116),
PINMUX_IRQ(irq_pin(28), 117),
PINMUX_IRQ(irq_pin(24), 118),
PINMUX_IRQ(irq_pin(6), 147),
PINMUX_IRQ(irq_pin(2), 149),
PINMUX_IRQ(irq_pin(7), 150),
PINMUX_IRQ(irq_pin(12), 156),
PINMUX_IRQ(irq_pin(4), 159),
PINMUX_IRQ(irq_pin(25), 164),
PINMUX_IRQ(irq_pin(8), 223),
PINMUX_IRQ(irq_pin(3), 224),
PINMUX_IRQ(irq_pin(5), 227),
PINMUX_IRQ(irq_pin(17), 234),
PINMUX_IRQ(irq_pin(11), 238),
PINMUX_IRQ(irq_pin(13), 239),
PINMUX_IRQ(irq_pin(16), 249),
PINMUX_IRQ(irq_pin(14), 251),
PINMUX_IRQ(irq_pin(9), 308),
};
/* -----------------------------------------------------------------------------
......
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