Skip to content

K
kernel_linux

OpenHarmony / kernel_linux
上一次同步 4 年多

通知 15
Star 8
Fork 2
K
kernel_linux
提交 f0e201f2 编写于 作者: J Josh Poimboeuf 提交者： Alex Deucher
浏览文件
操作

drm/radeon: refactor CIK tiling table initialization 

Simplify the control flow of cik_tiling_mode_table_init() similar to how
it was done in gfx_v7_0.c and gfx_v8_0.c.
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NJosh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 358c258a
隐藏空白更改
内联 并排
Showing with 666 addition and 1025 deletion
drivers/gpu/drm/radeon/cik.c
浏览文件 @ f0e201f2
...@@ -2343,9 +2343,13 @@ static int cik_init_microcode(struct radeon_device *rdev) ...@@ -2343,9 +2343,13 @@ static int cik_init_microcode(struct radeon_device *rdev)
*/ */
static void cik_tiling_mode_table_init(struct radeon_device *rdev) static void cik_tiling_mode_table_init(struct radeon_device *rdev)
{ {
const u32 num_tile_mode_states = 32; u32 *tile = rdev->config.cik.tile_mode_array;
const u32 num_secondary_tile_mode_states = 16; u32 *macrotile = rdev->config.cik.macrotile_mode_array;
u32 reg_offset, gb_tile_moden, split_equal_to_row_size; const u32 num_tile_mode_states =
ARRAY_SIZE(rdev->config.cik.tile_mode_array);
const u32 num_secondary_tile_mode_states =
ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);
u32 reg_offset, split_equal_to_row_size;
u32 num_pipe_configs; u32 num_pipe_configs;
u32 num_rbs = rdev->config.cik.max_backends_per_se * u32 num_rbs = rdev->config.cik.max_backends_per_se *
rdev->config.cik.max_shader_engines; rdev->config.cik.max_shader_engines;
...@@ -2367,1032 +2371,669 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) ...@@ -2367,1032 +2371,669 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
if (num_pipe_configs > 8) if (num_pipe_configs > 8)
num_pipe_configs = 16; num_pipe_configs = 16;
if (num_pipe_configs == 16) { for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { tile[reg_offset] = 0;
switch (reg_offset) { for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
case 0: macrotile[reg_offset] = 0;
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | switch(num_pipe_configs) {
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | case 16:
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
case 1: PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
case 2: tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
case 3: PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
break; TILE_SPLIT(split_equal_to_row_size));
case 4: tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
TILE_SPLIT(split_equal_to_row_size)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
case 5: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
break; TILE_SPLIT(split_equal_to_row_size));
case 6: tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
break; tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 7: MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
TILE_SPLIT(split_equal_to_row_size)); MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
case 8: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
case 9: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
break; tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 10: MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
case 11: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 12: PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
case 13: tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
case 14: MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
case 16: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | NUM_BANKS(ADDR_SURF_16_BANK));
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
break; NUM_BANKS(ADDR_SURF_16_BANK));
case 17: macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | NUM_BANKS(ADDR_SURF_16_BANK));
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
case 27: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | NUM_BANKS(ADDR_SURF_16_BANK));
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
case 28: NUM_BANKS(ADDR_SURF_8_BANK));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); NUM_BANKS(ADDR_SURF_4_BANK));
break; macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 29: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | NUM_BANKS(ADDR_SURF_2_BANK));
PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) | macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
case 30: NUM_BANKS(ADDR_SURF_16_BANK));
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
default: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
gb_tile_moden = 0; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
break; NUM_BANKS(ADDR_SURF_16_BANK));
} macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
} NUM_BANKS(ADDR_SURF_8_BANK));
for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
switch (reg_offset) { BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
case 0: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | NUM_BANKS(ADDR_SURF_4_BANK));
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
break; NUM_BANKS(ADDR_SURF_2_BANK));
case 1: macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | NUM_BANKS(ADDR_SURF_2_BANK));
NUM_BANKS(ADDR_SURF_16_BANK));
break; for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
case 2: WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | break;
NUM_BANKS(ADDR_SURF_16_BANK));
break; case 8:
case 3: tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
NUM_BANKS(ADDR_SURF_16_BANK)); tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
case 4: PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
NUM_BANKS(ADDR_SURF_8_BANK)); PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
case 5: tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
NUM_BANKS(ADDR_SURF_4_BANK)); tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
case 6: PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | TILE_SPLIT(split_equal_to_row_size));
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
NUM_BANKS(ADDR_SURF_2_BANK)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
case 8: MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_16_BANK)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
case 9: TILE_SPLIT(split_equal_to_row_size));
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_16_BANK)); PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
case 10: tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
NUM_BANKS(ADDR_SURF_16_BANK)); tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
case 11: PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
NUM_BANKS(ADDR_SURF_8_BANK)); PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
case 12: tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_4_BANK)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
case 13: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
NUM_BANKS(ADDR_SURF_2_BANK)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
case 14: MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_2_BANK)); PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
default: tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = 0; MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
} SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
} PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
} else if (num_pipe_configs == 8) { SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
switch (reg_offset) { MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
case 0: PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
case 1: NUM_BANKS(ADDR_SURF_16_BANK));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 2: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | NUM_BANKS(ADDR_SURF_16_BANK));
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
case 3: NUM_BANKS(ADDR_SURF_16_BANK));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 4: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | NUM_BANKS(ADDR_SURF_4_BANK));
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
TILE_SPLIT(split_equal_to_row_size)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
case 5: NUM_BANKS(ADDR_SURF_2_BANK));
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
break; NUM_BANKS(ADDR_SURF_16_BANK));
case 6: macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | NUM_BANKS(ADDR_SURF_16_BANK));
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
case 7: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | NUM_BANKS(ADDR_SURF_16_BANK));
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
TILE_SPLIT(split_equal_to_row_size)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
break; NUM_BANKS(ADDR_SURF_16_BANK));
case 8: macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
break; NUM_BANKS(ADDR_SURF_8_BANK));
case 9: macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); NUM_BANKS(ADDR_SURF_4_BANK));
break; macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 10: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | NUM_BANKS(ADDR_SURF_2_BANK));
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
break; WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
case 11: for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | break;
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); case 4:
break;
case 12:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 13:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
break;
case 14:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 16:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 17:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 27:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
break;
case 28:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 29:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 30:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
default:
gb_tile_moden = 0;
break;
}
rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
}
for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
switch (reg_offset) {
case 0:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 1:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 2:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 3:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 4:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 5:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 6:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
case 8:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 9:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 10:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 11:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 12:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 13:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 14:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
default:
gb_tile_moden = 0;
break;
}
rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
}
} else if (num_pipe_configs == 4) {
if (num_rbs == 4) { if (num_rbs == 4) {
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
switch (reg_offset) { MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
case 0: PIPE_CONFIG(ADDR_SURF_P4_16x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); PIPE_CONFIG(ADDR_SURF_P4_16x16) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
case 1: tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
case 2: PIPE_CONFIG(ADDR_SURF_P4_16x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); PIPE_CONFIG(ADDR_SURF_P4_16x16) |
break; TILE_SPLIT(split_equal_to_row_size));
case 3: tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
PIPE_CONFIG(ADDR_SURF_P4_16x16) | tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P4_16x16) |
case 4: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
TILE_SPLIT(split_equal_to_row_size)); TILE_SPLIT(split_equal_to_row_size));
break; tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
case 5: PIPE_CONFIG(ADDR_SURF_P4_16x16));
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
break; tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 6: MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
PIPE_CONFIG(ADDR_SURF_P4_16x16) | tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P4_8x16) |
case 7: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
TILE_SPLIT(split_equal_to_row_size)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 8: PIPE_CONFIG(ADDR_SURF_P4_16x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
PIPE_CONFIG(ADDR_SURF_P4_16x16)); tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
case 9: PIPE_CONFIG(ADDR_SURF_P4_16x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
PIPE_CONFIG(ADDR_SURF_P4_16x16) | tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P4_8x16) |
case 10: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 11: PIPE_CONFIG(ADDR_SURF_P4_16x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); PIPE_CONFIG(ADDR_SURF_P4_16x16) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
case 12: tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
case 13: PIPE_CONFIG(ADDR_SURF_P4_16x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
break;
case 14:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 16:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 17:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 27:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
break;
case 28:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 29:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 30:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
default:
gb_tile_moden = 0;
break;
}
rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
}
} else if (num_rbs < 4) { } else if (num_rbs < 4) {
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
switch (reg_offset) { MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
case 0: PIPE_CONFIG(ADDR_SURF_P4_8x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); PIPE_CONFIG(ADDR_SURF_P4_8x16) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
case 1: tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
case 2: PIPE_CONFIG(ADDR_SURF_P4_8x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); PIPE_CONFIG(ADDR_SURF_P4_8x16) |
break; TILE_SPLIT(split_equal_to_row_size));
case 3: tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
PIPE_CONFIG(ADDR_SURF_P4_8x16) | tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P4_8x16) |
case 4: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(split_equal_to_row_size)); TILE_SPLIT(split_equal_to_row_size));
break; tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
case 5: PIPE_CONFIG(ADDR_SURF_P4_8x16));
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
break; tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 6: MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
PIPE_CONFIG(ADDR_SURF_P4_8x16) | tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P4_8x16) |
case 7: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(split_equal_to_row_size)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 8: PIPE_CONFIG(ADDR_SURF_P4_8x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
PIPE_CONFIG(ADDR_SURF_P4_8x16)); tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
case 9: PIPE_CONFIG(ADDR_SURF_P4_8x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
PIPE_CONFIG(ADDR_SURF_P4_8x16) | tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
break; PIPE_CONFIG(ADDR_SURF_P4_8x16) |
case 10: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 11: PIPE_CONFIG(ADDR_SURF_P4_8x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); PIPE_CONFIG(ADDR_SURF_P4_8x16) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
case 12: tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
case 13: PIPE_CONFIG(ADDR_SURF_P4_8x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
break;
case 14:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 16:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 17:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 27:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
break;
case 28:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 29:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 30:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
default:
gb_tile_moden = 0;
break;
}
rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
}
}
for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
switch (reg_offset) {
case 0:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 1:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 2:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 3:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 4:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 5:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 6:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 8:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 9:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 10:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 11:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 12:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 13:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 14:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
default:
gb_tile_moden = 0;
break;
}
rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
}
} else if (num_pipe_configs == 2) {
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
switch (reg_offset) {
case 0:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
break;
case 1:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
break;
case 2:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
break;
case 3:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
break;
case 4:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(split_equal_to_row_size));
break;
case 5:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break;
case 6:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
break;
case 7:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(split_equal_to_row_size));
break;
case 8:
gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
PIPE_CONFIG(ADDR_SURF_P2);
break;
case 9:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2));
break;
case 10:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 11:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 12:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 13:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
break;
case 14:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 16:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 17:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 27:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2));
break;
case 28:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 29:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
case 30:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break;
default:
gb_tile_moden = 0;
break;
}
rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
}
for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
switch (reg_offset) {
case 0:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 1:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 2:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 3:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 4:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 5:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 6:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 8:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 9:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 10:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 11:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 12:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 13:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 14:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
default:
gb_tile_moden = 0;
break;
}
rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
} }
} else
macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
break;
case 2:
tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(split_equal_to_row_size));
tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(split_equal_to_row_size));
tile[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
PIPE_CONFIG(ADDR_SURF_P2);
tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2));
tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2));
tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
break;
default:
DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs); DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
}
} }
/** /**
......
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或